Revision 0:5464d5e415e5, committed 2014-10-08

Comitter:

sinrab

Date:

Wed Oct 08 11:00:24 2014 +0000

Commit message:

The code from https://github.com/vpcola/Nucleo

Changed in this revision

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Arial10x10.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,153 @@
+
+#ifndef __ARIAL_10x10__
+#define __ARIAL_10x10__
+
+const Arial_Narrow10x14 as byte[3045] = (
+        $06, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char  
+        $02, $00, $00, $FC, $05, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char !
+        $03, $1C, $00, $00, $00, $1C, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char "
+        $07, $A0, $00, $A0, $06, $F0, $01, $AC, $00, $A0, $06, $F0, $01, $AC, $00, $00, $00, $00, $00, $00, $00,  ' Code for char #
+        $05, $38, $03, $44, $04, $FE, $0F, $44, $04, $88, $03, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char $
+        $0A, $38, $00, $44, $00, $44, $04, $38, $03, $80, $00, $60, $00, $98, $03, $44, $04, $40, $04, $80, $03,  ' Code for char %
+        $08, $00, $00, $80, $03, $78, $04, $44, $04, $A4, $04, $18, $03, $80, $07, $00, $04, $00, $00, $00, $00,  ' Code for char &
+        $01, $1C, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char '
+        $04, $00, $00, $E0, $07, $18, $18, $04, $20, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char (
+        $03, $04, $20, $18, $18, $E0, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char )
+        $03, $28, $00, $1C, $00, $28, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char *
+        $07, $40, $00, $40, $00, $40, $00, $F0, $01, $40, $00, $40, $00, $40, $00, $00, $00, $00, $00, $00, $00,  ' Code for char +
+        $02, $00, $10, $00, $0C, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ,
+        $03, $80, $00, $80, $00, $80, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char -
+        $02, $00, $00, $00, $04, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char .
+        $03, $00, $06, $E0, $01, $1C, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char /
+        $05, $F0, $01, $08, $02, $04, $04, $08, $02, $F0, $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char 0
+        $03, $10, $00, $08, $00, $FC, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char 1
+        $05, $18, $06, $04, $05, $84, $04, $48, $04, $30, $04, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char 2
+        $05, $08, $03, $04, $04, $44, $04, $A8, $02, $10, $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char 3
+        $05, $80, $01, $60, $01, $18, $01, $FC, $07, $00, $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char 4
+        $05, $70, $03, $2C, $04, $24, $04, $44, $02, $84, $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char 5
+        $05, $F0, $01, $48, $02, $24, $04, $44, $02, $88, $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char 6
+        $05, $04, $00, $04, $07, $E4, $00, $14, $00, $0C, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char 7
+        $05, $10, $01, $A8, $02, $44, $04, $A8, $02, $10, $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char 8
+        $05, $30, $02, $48, $04, $84, $04, $48, $02, $F0, $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char 9
+        $02, $00, $00, $10, $04, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char :
+        $02, $00, $10, $10, $0C, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ;
+        $05, $40, $00, $A0, $00, $A0, $00, $10, $01, $08, $02, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char <
+        $05, $90, $00, $90, $00, $90, $00, $90, $00, $90, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char =
+        $05, $08, $02, $10, $01, $A0, $00, $A0, $00, $40, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char >
+        $05, $18, $00, $0C, $00, $84, $05, $44, $00, $38, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ?
+        $0A, $E0, $07, $10, $08, $E8, $13, $14, $24, $14, $24, $14, $22, $E4, $27, $34, $24, $08, $14, $F0, $0B,  ' Code for char @
+        $07, $00, $06, $C0, $01, $B8, $00, $84, $00, $B8, $00, $C0, $01, $00, $06, $00, $00, $00, $00, $00, $00,  ' Code for char A
+        $06, $00, $00, $FC, $07, $44, $04, $44, $04, $44, $04, $B8, $03, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char B
+        $07, $00, $00, $F0, $01, $08, $02, $04, $04, $04, $04, $04, $04, $18, $03, $00, $00, $00, $00, $00, $00,  ' Code for char C
+        $07, $00, $00, $FC, $07, $04, $04, $04, $04, $04, $04, $08, $02, $F0, $01, $00, $00, $00, $00, $00, $00,  ' Code for char D
+        $06, $00, $00, $FC, $07, $44, $04, $44, $04, $44, $04, $44, $04, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char E
+        $06, $00, $00, $FC, $07, $44, $00, $44, $00, $44, $00, $04, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char F
+        $07, $00, $00, $F0, $01, $08, $02, $04, $04, $44, $04, $44, $04, $D8, $03, $00, $00, $00, $00, $00, $00,  ' Code for char G
+        $07, $00, $00, $FC, $07, $40, $00, $40, $00, $40, $00, $40, $00, $FC, $07, $00, $00, $00, $00, $00, $00,  ' Code for char H
+        $02, $00, $00, $FC, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char I
+        $04, $00, $03, $00, $04, $00, $04, $FC, $03, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char J
+        $06, $00, $00, $FC, $07, $40, $00, $F0, $00, $08, $03, $04, $04, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char K
+        $06, $00, $00, $FC, $07, $00, $04, $00, $04, $00, $04, $00, $04, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char L
+        $08, $00, $00, $FC, $07, $38, $00, $C0, $03, $00, $04, $C0, $03, $38, $00, $FC, $07, $00, $00, $00, $00,  ' Code for char M
+        $07, $00, $00, $FC, $07, $18, $00, $60, $00, $80, $00, $00, $03, $FC, $07, $00, $00, $00, $00, $00, $00,  ' Code for char N
+        $07, $00, $00, $F0, $01, $08, $02, $04, $04, $04, $04, $08, $02, $F0, $01, $00, $00, $00, $00, $00, $00,  ' Code for char O
+        $06, $00, $00, $FC, $07, $44, $00, $44, $00, $44, $00, $38, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char P
+        $07, $00, $00, $F0, $01, $08, $02, $04, $04, $04, $06, $08, $02, $F0, $0D, $00, $00, $00, $00, $00, $00,  ' Code for char Q
+        $08, $00, $00, $FC, $07, $44, $00, $44, $00, $C4, $00, $44, $01, $38, $02, $00, $04, $00, $00, $00, $00,  ' Code for char R
+        $06, $00, $00, $38, $03, $44, $04, $44, $04, $44, $04, $98, $03, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char S
+        $06, $00, $00, $04, $00, $04, $00, $FC, $07, $04, $00, $04, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char T
+        $07, $00, $00, $FC, $01, $00, $02, $00, $04, $00, $04, $00, $02, $FC, $01, $00, $00, $00, $00, $00, $00,  ' Code for char U
+        $07, $0C, $00, $70, $00, $80, $03, $00, $04, $80, $03, $70, $00, $0C, $00, $00, $00, $00, $00, $00, $00,  ' Code for char V
+        $09, $0C, $00, $F0, $03, $00, $04, $F8, $03, $04, $00, $F8, $03, $00, $04, $E0, $03, $1C, $00, $00, $00,  ' Code for char W
+        $07, $04, $04, $08, $02, $B0, $01, $40, $00, $B0, $01, $08, $02, $04, $04, $00, $00, $00, $00, $00, $00,  ' Code for char X
+        $07, $04, $00, $18, $00, $20, $00, $C0, $07, $20, $00, $18, $00, $04, $00, $00, $00, $00, $00, $00, $00,  ' Code for char Y
+        $06, $04, $06, $04, $05, $C4, $04, $24, $04, $14, $04, $0C, $04, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char Z
+        $03, $00, $00, $FC, $3F, $04, $20, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char [
+        $03, $0C, $00, $F0, $01, $00, $06, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char BackSlash
+        $02, $04, $20, $FC, $3F, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ]
+        $05, $40, $00, $38, $00, $04, $00, $38, $00, $40, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ^
+        $06, $00, $10, $00, $10, $00, $10, $00, $10, $00, $10, $00, $10, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char _
+        $02, $02, $00, $04, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char `
+        $05, $20, $03, $90, $04, $90, $04, $90, $04, $E0, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char a
+        $05, $FC, $07, $20, $02, $10, $04, $10, $04, $E0, $03, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char b
+        $04, $E0, $03, $10, $04, $10, $04, $20, $02, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char c
+        $05, $E0, $03, $10, $04, $10, $04, $20, $02, $FC, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char d
+        $05, $E0, $03, $90, $04, $90, $04, $90, $04, $E0, $02, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char e
+        $02, $FC, $07, $14, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char f
+        $05, $E0, $13, $10, $24, $10, $24, $20, $22, $F0, $1F, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char g
+        $05, $FC, $07, $20, $00, $10, $00, $10, $00, $E0, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char h
+        $01, $F4, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char i
+        $01, $F4, $3F, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char j
+        $04, $FC, $07, $40, $00, $A0, $01, $10, $06, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char k
+        $01, $FC, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char l
+        $07, $F0, $07, $20, $00, $10, $00, $E0, $07, $20, $00, $10, $00, $E0, $07, $00, $00, $00, $00, $00, $00,  ' Code for char m
+        $05, $F0, $07, $20, $00, $10, $00, $10, $00, $E0, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char n
+        $05, $E0, $03, $10, $04, $10, $04, $10, $04, $E0, $03, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char o
+        $05, $F0, $3F, $20, $02, $10, $04, $10, $04, $E0, $03, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char p
+        $05, $E0, $03, $10, $04, $10, $04, $20, $02, $F0, $3F, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char q
+        $03, $F0, $07, $20, $00, $10, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char r
+        $04, $60, $02, $90, $04, $90, $04, $20, $03, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char s
+        $02, $FC, $07, $10, $04, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char t
+        $05, $F0, $03, $00, $04, $00, $04, $00, $02, $F0, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char u
+        $05, $30, $00, $C0, $03, $00, $04, $C0, $03, $30, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char v
+        $07, $F0, $03, $00, $04, $C0, $03, $30, $00, $C0, $03, $00, $04, $F0, $03, $00, $00, $00, $00, $00, $00,  ' Code for char w
+        $05, $10, $04, $60, $03, $80, $00, $60, $03, $10, $04, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char x
+        $05, $30, $20, $C0, $21, $00, $1E, $C0, $01, $30, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char y
+        $04, $10, $06, $90, $05, $50, $04, $30, $04, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char z
+        $03, $80, $00, $78, $1F, $04, $20, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char {
+        $02, $00, $00, $FC, $3F, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char |
+        $03, $04, $20, $78, $1F, $80, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char }
+        $05, $60, $00, $20, $00, $60, $00, $40, $00, $20, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ~
+        $03, $FE, $07, $02, $04, $FE, $07, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char 
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char €
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char 
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ‚
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ƒ
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char „
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char …
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char †
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ‡
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ˆ
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ‰
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char Š
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ‹
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char Œ
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char 
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char Ž
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char 
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char 
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ‘
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ’
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char “
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ”
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char •
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char –
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char —
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ˜
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ™
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char š
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ›
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char œ
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char 
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ž
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char Ÿ
+        $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char  
+        $02, $00, $00, $90, $3F, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ¡
+        $05, $E0, $03, $10, $3C, $D0, $07, $3C, $04, $20, $02, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ¢
+        $05, $40, $06, $78, $02, $C4, $03, $44, $04, $18, $04, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char £
+        $05, $50, $01, $A0, $00, $10, $01, $B0, $01, $50, $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ¤
+        $05, $44, $01, $78, $01, $C0, $07, $78, $01, $44, $01, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ¥
+        $02, $00, $00, $7C, $3E, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ¦
+        $05, $80, $10, $58, $21, $24, $22, $44, $24, $88, $1B, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char §
+        $04, $00, $00, $04, $00, $00, $00, $04, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ¨
+        $08, $F0, $01, $08, $02, $E4, $04, $14, $05, $14, $05, $94, $04, $08, $02, $F0, $01, $00, $00, $00, $00,  ' Code for char ©
+        $03, $64, $00, $54, $00, $7C, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ª
+        $05, $00, $01, $80, $02, $40, $05, $80, $02, $40, $04, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char «
+        $05, $10, $00, $10, $00, $10, $00, $10, $00, $F0, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ¬
+        $03, $80, $00, $80, $00, $80, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ­
+        $08, $F0, $01, $08, $02, $04, $04, $F4, $05, $D4, $04, $74, $05, $08, $02, $F0, $01, $00, $00, $00, $00,  ' Code for char ®
+        $07, $01, $00, $01, $00, $01, $00, $01, $00, $01, $00, $01, $00, $01, $00, $00, $00, $00, $00, $00, $00,  ' Code for char ¯
+        $04, $00, $00, $08, $00, $14, $00, $08, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00   ' Code for char °
+        )
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/Helper/def.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,25 @@
+/* Copyright (C) 2013 mbed.org, MIT License
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge, publish, distribute,
+ * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef DEF_H
+#define DEF_H
+
+#include "cmsis.h"
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/Socket/Endpoint.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,139 @@
+/* Copyright (C) 2013 mbed.org, MIT License
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge, publish, distribute,
+ * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "Socket/Socket.h"
+#include "Socket/Endpoint.h"
+#include "Helper/def.h"
+#include <cstring>
+
+ #include "cc3000.h"
+
+/* Copied from lwip */
+static char *cc3000_inet_ntoa_r(const in_addr addr, char *buf, int buflen)
+{
+  uint32_t s_addr;
+  char inv[3];
+  char *rp;
+  uint8_t *ap;
+  uint8_t rem;
+  uint8_t n;
+  uint8_t i;
+  int len = 0;
+
+  s_addr = addr.s_addr;
+
+  rp = buf;
+  ap = (uint8_t *)&s_addr;
+  for(n = 0; n < 4; n++) {
+    i = 0;
+    do {
+      rem = *ap % (uint8_t)10;
+      *ap /= (uint8_t)10;
+      inv[i++] = '0' + rem;
+    } while(*ap);
+    while(i--) {
+      if (len++ >= buflen) {
+        return NULL;
+      }
+      *rp++ = inv[i];
+    }
+    if (len++ >= buflen) {
+      return NULL;
+    }
+    *rp++ = '.';
+    ap++;
+  }
+  *--rp = 0;
+  return buf;
+}
+
+Endpoint::Endpoint()  {
+    _cc3000_module = cc3000::get_instance();
+    if (_cc3000_module == NULL) {
+        error("Endpoint constructor error: no cc3000 instance available!\r\n");
+    }
+    reset_address();
+}
+Endpoint::~Endpoint() {}
+
+void Endpoint::reset_address(void) {
+    _ipAddress[0] = '\0';
+    std::memset(&_remote_host, 0, sizeof(sockaddr_in));
+}
+
+int Endpoint::set_address(const char* host, const int port) {
+    reset_address();
+
+    char address[5];
+    char *p_address = address;
+
+    signed int add[5];
+
+    // Dot-decimal notation
+    int result = std::sscanf(host, "%3u.%3u.%3u.%3u", &add[0], &add[1], &add[2], &add[3]);
+    for (int i=0;i<4;i++) {
+      address[i] = add[i];
+    }
+    std::memset(_ipAddress,0,sizeof(_ipAddress));
+
+    if (result != 4) {
+ #ifndef CC3000_TINY_DRIVER
+        //Resolve DNS address or populate hard-coded IP address
+        uint32_t address_integer;
+        int resolveRetCode;
+        resolveRetCode = _cc3000_module->_socket.gethostbyname((uint8_t *)host, strlen(host) , &address_integer);
+
+        if ((resolveRetCode > -1) && (0 != address_integer)) {
+            _remote_host.sin_addr.s_addr = htonl(address_integer);
+            cc3000_inet_ntoa_r(_remote_host.sin_addr, _ipAddress, sizeof(_ipAddress));
+        } else {
+            // Failed to resolve the address
+            DBG_SOCKET("Failed to resolve the hostname : %s",host);
+            return (-1);
+        }
+#else
+        return -1;
+#endif
+    } else {
+        std::memcpy((char*)&_remote_host.sin_addr.s_addr, p_address, 4);
+    }
+
+    _remote_host.sin_family = AF_INET;
+    _remote_host.sin_port = htons(port);
+
+    DBG_SOCKET("remote host address (string): %s",get_address());
+    DBG_SOCKET("remote host address from s_addr : %d.%d.%d.%d",
+            int(_remote_host.sin_addr.s_addr & 0xFF),
+            int((_remote_host.sin_addr.s_addr & 0xFF00) >> 8),
+            int((_remote_host.sin_addr.s_addr & 0xFF0000) >> 16),
+            int((_remote_host.sin_addr.s_addr & 0xFF000000) >> 24));
+    DBG_SOCKET("port: %d", port);
+
+    return 0;
+}
+
+char* Endpoint::get_address() {
+    if ((_ipAddress[0] == '\0') && (_remote_host.sin_addr.s_addr != 0))
+            cc3000_inet_ntoa_r(_remote_host.sin_addr, _ipAddress, sizeof(_ipAddress));
+    return _ipAddress;
+}
+
+
+int   Endpoint::get_port() {
+    return ntohs(_remote_host.sin_port);
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/Socket/Endpoint.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,68 @@
+/* Copyright (C) 2013 mbed.org, MIT License
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge, publish, distribute,
+ * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef ENDPOINT_H
+#define ENDPOINT_H
+
+#include "cc3000.h"
+
+using namespace mbed_cc3000;
+
+class UDPSocket;
+
+/**
+IP Endpoint (address, port)
+*/
+class Endpoint {
+    friend class UDPSocket;
+
+public:
+    /** IP Endpoint (address, port)
+     */
+    Endpoint(void);
+
+    ~Endpoint(void);
+
+    /** Reset the address of this endpoint
+     */
+    void reset_address(void);
+
+    /** Set the address of this endpoint
+    \param host The endpoint address (it can either be an IP Address or a hostname that will be resolved with DNS).
+    \param port The endpoint port
+    \return 0 on success, -1 on failure (when an hostname cannot be resolved by DNS).
+     */
+    int  set_address(const char* host, const int port);
+
+    /** Get the IP address of this endpoint
+    \return The IP address of this endpoint.
+     */
+    char* get_address(void);
+
+    /** Get the port of this endpoint
+    \return The port of this endpoint
+     */
+    int get_port(void);
+
+protected:
+    char _ipAddress[17];
+    sockaddr_in _remote_host;
+    cc3000 *_cc3000_module;
+};
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/Socket/Socket.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,115 @@
+/* Copyright (C) 2013 mbed.org, MIT License
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge, publish, distribute,
+ * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "Socket.h"
+#include <cstring>
+
+Socket::Socket() : _sock_fd(-1), _blocking(true), _timeout(1500) {
+    _cc3000_module = cc3000::get_instance();
+    if (_cc3000_module == NULL) {
+        error("Socket constructor error: no cc3000 instance available!\r\n");
+    }
+}
+
+int Socket::init_socket(int type, int protocol) {
+    if (_sock_fd != -1) {
+        DBG_SOCKET("Socket was initialized previously");
+        return -1;
+    }
+
+    int fd = _cc3000_module->_socket.socket(AF_INET, type, protocol);
+    if (fd < -1) {
+        DBG_SOCKET("Failed to create new socket (type: %d, protocol: %d)",type, protocol);
+        return -1;
+    }
+
+    DBG_SOCKET("Socket created (fd: %d type: %d, protocol: %d)",fd, type, protocol);
+    _sock_fd = fd;
+
+    return 0;
+}
+
+void Socket::set_blocking(bool blocking, unsigned int timeout) {
+    _blocking = blocking;
+    _timeout = timeout;
+}
+
+int Socket::set_option(int level, int optname, const void *optval, socklen_t optlen) {
+#ifndef CC3000_TINY_DRIVER
+    return _cc3000_module->_socket.setsockopt(_sock_fd, level, optname, optval, optlen);
+#else
+    return -1;
+#endif
+}
+
+int Socket::get_option(int level, int optname, void *optval, socklen_t *optlen) {
+    return _cc3000_module->_socket.getsockopt(_sock_fd, level, optname, optval, optlen);
+}
+
+int Socket::select(struct timeval *timeout, bool read, bool write) {
+    if (_sock_fd < 0) {
+        return -1;
+    }
+
+    fd_set fdSet;
+    FD_ZERO(&fdSet);
+    FD_SET(_sock_fd, &fdSet);
+
+    fd_set* readset  = (read ) ? (&fdSet) : (NULL);
+    fd_set* writeset = (write) ? (&fdSet) : (NULL);
+
+    int ret = _cc3000_module->_socket.select(_sock_fd+1, readset, writeset, NULL, timeout);
+
+    DBG_SOCKET("Select on sock_fd: %d, returns %d. fdSet: %d", _sock_fd, ret, FD_ISSET(_sock_fd, &fdSet));
+
+    // TODO
+    //return (ret <= 0 || !FD_ISSET(_sock_fd, &fdSet)) ? (-1) : (0);
+    if (FD_ISSET(_sock_fd, &fdSet)) {
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+int Socket::wait_readable(TimeInterval& timeout) {
+    return select(&timeout._time, true, false);
+}
+
+int Socket::wait_writable(TimeInterval& timeout) {
+    return select(&timeout._time, false, true);
+}
+
+int Socket::close() {
+    if (_sock_fd < 0 ) {
+        return -1;
+    }
+
+    _cc3000_module->_socket.closesocket(_sock_fd);
+    _sock_fd = -1;
+    return 0;
+}
+
+Socket::~Socket() {
+    close();
+}
+
+TimeInterval::TimeInterval(unsigned int ms) {
+    _time.tv_sec = ms / 1000;
+    _time.tv_usec = (ms - (_time.tv_sec * 1000)) * 1000;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/Socket/Socket.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,99 @@
+/* Copyright (C) 2013 mbed.org, MIT License
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge, publish, distribute,
+ * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef SOCKET_H
+#define SOCKET_H
+
+#include "cc3000.h"
+
+using namespace mbed_cc3000;
+
+class TimeInterval;
+
+/** Socket file descriptor and select wrapper
+  */
+class Socket {
+public:
+    /** Socket
+     */
+    Socket();
+
+    /** Set blocking or non-blocking mode of the socket and a timeout on
+        blocking socket operations
+    \param blocking  true for blocking mode, false for non-blocking mode.
+    \param timeout   timeout in ms [Default: (1500)ms].
+    */
+    void set_blocking(bool blocking, unsigned int timeout=1500);
+
+    /** Set socket options
+    \param level     stack level (see: lwip/sockets.h)
+    \param optname   option ID
+    \param optval    option value
+    \param socklen_t length of the option value
+    \return 0 on success, -1 on failure
+    */
+    int set_option(int level, int optname, const void *optval, socklen_t optlen);
+
+    /** Get socket options
+        \param level     stack level (see: lwip/sockets.h)
+        \param optname   option ID
+        \param optval    buffer pointer where to write the option value
+        \param socklen_t length of the option value
+        \return 0 on success, -1 on failure
+        */
+    int get_option(int level, int optname, void *optval, socklen_t *optlen);
+
+
+    /** Close the socket file descriptor
+     */
+    int close();
+
+    ~Socket();
+
+protected:
+    int _sock_fd;
+
+    int init_socket(int type, int protocol);
+
+    int wait_readable(TimeInterval& timeout);
+    int wait_writable(TimeInterval& timeout);
+
+    bool _blocking;
+    int _timeout;
+
+    cc3000 *_cc3000_module;
+private:
+    int select(struct timeval *timeout, bool read, bool write);
+};
+
+/** Time interval class used to specify timeouts
+ */
+class TimeInterval {
+    friend class Socket;
+
+public:
+    /** Time Interval
+     \param ms time interval expressed in milliseconds
+      */
+    TimeInterval(unsigned int ms);
+
+private:
+    struct timeval _time;
+};
+
+#endif /* SOCKET_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/Socket/TCPSocketConnection.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,184 @@
+/* Copyright (C) 2013 mbed.org, MIT License
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge, publish, distribute,
+ * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "TCPSocketConnection.h"
+#include <algorithm>
+
+TCPSocketConnection::TCPSocketConnection() : _is_connected(false) {
+    _cc3000_module = cc3000::get_instance();
+    if (_cc3000_module == NULL) {
+        error("Endpoint constructor error: no cc3000 instance available!\r\n");
+    }
+}
+
+int TCPSocketConnection::connect(const char *host, const int port) {
+    if (init_socket(SOCK_STREAM, IPPROTO_TCP) < 0) {
+        DBG_SOCKET("Failed to create tcp socket");
+        return -1;
+    }
+
+    if (set_address(host, port) != 0) {
+        DBG_SOCKET("Failed to set address (tcp)");
+        return -1;
+    }
+
+    if (_cc3000_module->_socket.connect(_sock_fd, (const sockaddr *)&_remote_host, sizeof(_remote_host)) < 0) {
+        DBG_SOCKET("Failed to connect (tcp)");
+        close();
+        return -1;
+    }
+
+    _is_connected = true;
+
+    return 0;
+}
+
+bool TCPSocketConnection::is_connected(void) {
+    return _is_connected;
+}
+
+int TCPSocketConnection::send(char* data, int length) {
+    if ((_sock_fd < 0) || !_is_connected) {
+        return -1;
+    }
+
+    if (!_blocking) {
+        TimeInterval timeout(_timeout);
+        if (wait_writable(timeout) != 0) {
+            return -1;
+        }
+    }
+
+    int n = _cc3000_module->_socket.send(_sock_fd, data, length, 0);
+    _is_connected = (n != 0);
+
+    return n;
+}
+
+int TCPSocketConnection::send_all(char *data, int length) {
+    if ((_sock_fd < 0) || !_is_connected) {
+        return -1;
+    }
+
+    int writtenLen = 0;
+    TimeInterval timeout(_timeout);
+    while (writtenLen < length) {
+        if (!_blocking) {
+            // Wait for socket to be writeable
+            if (wait_writable(timeout) != 0) {
+                return writtenLen;
+            }
+        }
+
+        int ret = _cc3000_module->_socket.send(_sock_fd, data + writtenLen, length - writtenLen, 0);
+        if (ret > 0) {
+            writtenLen += ret;
+            continue;
+        } else if (ret == 0) {
+            _is_connected = false;
+            return writtenLen;
+        } else {
+            return -1; //Connnection error
+        }
+    }
+
+    return writtenLen;
+}
+
+int TCPSocketConnection::receive(char *data, int length) {
+    if ((_sock_fd < 0) || !_is_connected) {
+        return -1;
+    }
+
+    if (!_blocking) {
+        TimeInterval timeout(_timeout);
+        if (wait_readable(timeout) != 0)
+            return -1;
+    }
+
+    int n = _cc3000_module->_socket.recv(_sock_fd, data, length, 0);
+    if (n >= 0) {
+        _is_connected = 1;
+    } else {
+        _is_connected = 0;
+    }
+
+    return n;
+}
+
+int TCPSocketConnection::receive_all(char *data, int length) {
+    if ((_sock_fd < 0) || !_is_connected) {
+        return -1;
+    }
+
+    int readLen = 0;
+    TimeInterval timeout(_timeout);
+    while (readLen < length) {
+        if (!_blocking) {
+            //Wait for socket to be readable
+            if (wait_readable(timeout) != 0)
+                return readLen;
+        }
+
+        int ret = _cc3000_module->_socket.recv(_sock_fd, data + readLen, length - readLen, 0);
+        if (ret > 0) {
+            readLen += ret;
+        } else if (ret == 0) {
+            _is_connected = false;
+            return readLen;
+        } else {
+            return -1; //Connnection error
+        }
+    }
+    return readLen;
+}
+
+int TCPSocketConnection::receive_until(char * data, int length, char ch)
+{
+    if ((_sock_fd < 0) || !_is_connected) {
+        return -1;
+    }
+
+    int readLen = 0;
+		char tmpdata = '\0';
+		
+    TimeInterval timeout(_timeout);
+    while ((readLen < length) && (tmpdata != ch))
+		{
+        if (!_blocking) {
+            //Wait for socket to be readable
+            if (wait_readable(timeout) != 0)
+                return readLen;
+        }
+
+        int ret = _cc3000_module->_socket.recv(_sock_fd, &tmpdata, 1, 0);
+				if( ret == 1)
+				{
+					data[readLen] = tmpdata;
+					readLen++;
+				}
+				
+				if (ret < 0)
+				{
+					_is_connected = false;
+					return -1;
+				}
+    }
+    return readLen;	
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/Socket/TCPSocketConnection.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,88 @@
+/* Copyright (C) 2013 mbed.org, MIT License
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge, publish, distribute,
+ * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef TCPSOCKET_H
+#define TCPSOCKET_H
+
+#include "Socket.h"
+#include "Endpoint.h"
+
+/**
+TCP socket connection
+*/
+class TCPSocketConnection: public Socket, public Endpoint {
+    friend class TCPSocketServer;
+
+public:
+    /** TCP socket connection
+    */
+    TCPSocketConnection();
+
+    /** Connects this TCP socket to the server
+    \param host The host to connect to. It can either be an IP Address or a hostname that will be resolved with DNS.
+    \param port The host's port to connect to.
+    \return 0 on success, -1 on failure.
+    */
+    int connect(const char *host, const int port);
+
+    /** Check if the socket is connected
+    \return true if connected, false otherwise.
+    */
+    bool is_connected(void);
+
+    /** Send data to the remote host.
+    \param data The buffer to send to the host.
+    \param length The length of the buffer to send.
+    \return the number of written bytes on success (>=0) or -1 on failure
+     */
+    int send(char *data, int length);
+
+    /** Send all the data to the remote host.
+    \param data The buffer to send to the host.
+    \param length The length of the buffer to send.
+    \return the number of written bytes on success (>=0) or -1 on failure
+    */
+    int send_all(char *data, int length);
+
+    /** Receive data from the remote host.
+    \param data The buffer in which to store the data received from the host.
+    \param length The maximum length of the buffer.
+    \return the number of received bytes on success (>=0) or -1 on failure
+     */
+    int receive(char *data, int length);
+
+    /** Receive all the data from the remote host.
+    \param data The buffer in which to store the data received from the host.
+    \param length The maximum length of the buffer.
+    \return the number of received bytes on success (>=0) or -1 on failure
+    */
+    int receive_all(char *data, int length);
+	/** Receive until a specific character is recived
+		\param data The buffer in which to store the data received from the host.
+		\param length The maximum length of the buffer
+		\return The number of bytes received on success or -1 on failure
+		*/
+		int receive_until(char * data, int length, char ch);
+		
+private:
+    bool _is_connected;
+    cc3000 *_cc3000_module;
+};
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/Socket/TCPSocketServer.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,85 @@
+/* Copyright (C) 2013 mbed.org, MIT License
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge, publish, distribute,
+ * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "TCPSocketServer.h"
+#include <string>
+
+TCPSocketServer::TCPSocketServer() {
+
+}
+
+int TCPSocketServer::bind(int port) {
+    if (init_socket(SOCK_STREAM, IPPROTO_TCP) < 0) {
+        return -1;
+    }
+
+    sockaddr_in localHost;
+    memset(&localHost, 0, sizeof(localHost));
+
+    localHost.sin_family = AF_INET;
+    localHost.sin_port = htons(port);
+    localHost.sin_addr.s_addr = 0;
+
+    if (_cc3000_module->_socket.bind(_sock_fd, (const sockaddr *)&localHost, sizeof(localHost)) < 0) {
+        close();
+        return -1;
+    }
+
+    return 0;
+}
+
+int TCPSocketServer::listen(int max) {
+    if (_sock_fd < 0) {
+        return -1;
+    }
+
+    if (_cc3000_module->_socket.listen(_sock_fd, max) < 0) {
+        close();
+        return -1;
+    }
+
+    return 0;
+}
+
+
+int TCPSocketServer::accept(TCPSocketConnection& connection) {
+    if (_sock_fd < 0) {
+        return -1;
+    }
+
+    if (!_blocking) {
+        TimeInterval timeout(_timeout);
+        if (wait_readable(timeout) != 0) {
+            return -1;
+        }
+    }
+
+    connection.reset_address();
+    socklen_t newSockRemoteHostLen = sizeof(connection._remote_host);
+    int fd = _cc3000_module->_socket.accept(_sock_fd, (sockaddr *) &connection._remote_host, &newSockRemoteHostLen);
+    if (fd < 0) {
+        return -1;
+    }
+    /* s_addr is returned in the little endian */
+    connection._remote_host.sin_addr.s_addr = htonl(connection._remote_host.sin_addr.s_addr);
+    connection._sock_fd = fd;
+    connection._is_connected = true;
+
+    return 0;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/Socket/TCPSocketServer.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,53 @@
+/* Copyright (C) 2013 mbed.org, MIT License
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge, publish, distribute,
+ * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef TCPSOCKETSERVER_H
+#define TCPSOCKETSERVER_H
+
+#include "Socket/Socket.h"
+#include "TCPSocketConnection.h"
+
+/** TCP Server.
+  */
+class TCPSocketServer : public Socket {
+  public:
+    /** Instantiate a TCP Server.
+    */
+    TCPSocketServer();
+
+    /** Bind a socket to a specific port.
+    \param port The port to listen for incoming connections on.
+    \return 0 on success, -1 on failure.
+    */
+    int bind(int port);
+
+    /** Start listening for incoming connections.
+    \param backlog number of pending connections that can be queued up at any
+                   one time [Default: 1].
+    \return 0 on success, -1 on failure.
+    */
+    int listen(int backlog=1);
+
+    /** Accept a new connection.
+    \param connection A TCPSocketConnection instance that will handle the incoming connection.
+    \return 0 on success, -1 on failure.
+    */
+    int accept(TCPSocketConnection& connection);
+};
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/Socket/UDPSocket.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,92 @@
+/* Copyright (C) 2013 mbed.org, MIT License
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge, publish, distribute,
+ * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "UDPSocket.h"
+
+#include <string>
+#include <algorithm>
+
+UDPSocket::UDPSocket() {
+
+}
+
+int UDPSocket::init(void) {
+    return init_socket(SOCK_DGRAM, IPPROTO_UDP);
+}
+
+int UDPSocket::bind(int port) {
+    if (init_socket(SOCK_DGRAM, IPPROTO_UDP) < 0) {
+        return -1;
+    }
+
+    sockaddr_in localHost;
+    std::memset(&localHost, 0, sizeof(sockaddr_in));
+
+    localHost.sin_family = AF_INET;
+    localHost.sin_port = htons(port);
+    localHost.sin_addr.s_addr = 0;
+
+    if (_cc3000_module->_socket.bind(_sock_fd, (sockaddr *)&localHost, sizeof(sockaddr_in)) != 0) {
+        DBG_SOCKET("Failed to bind a socket (udp). Closing socket");
+        _cc3000_module->_socket.closesocket(_sock_fd);
+        _sock_fd = -1;
+        return -1;
+    }
+
+    return 0;
+}
+
+int UDPSocket::sendTo(Endpoint &remote, char *packet, int length)
+{
+    if (_sock_fd < 0) {
+        return -1;
+    }
+    // TODO - seems to be a bug, waiting for TI to respond
+    // if (!_blocking) {
+    //     TimeInterval timeout(_timeout);
+    //     if (wait_writable(timeout) != 0) {
+    //         DBG_SOCKET("The socket is not writeable. _sock_fd: %d", _sock_fd);
+    //         return 0;
+    //     }
+    // }
+
+    return _cc3000_module->_socket.sendto(_sock_fd, packet, length, 0, (sockaddr *)&remote._remote_host, sizeof(sockaddr));
+}
+
+int UDPSocket::receiveFrom(Endpoint &remote, char *buffer, int length)
+{
+    if (_sock_fd < 0) {
+        return -1;
+    }
+
+    if (!_blocking) {
+        TimeInterval timeout(_timeout);
+        if (wait_readable(timeout) != 0) {
+            DBG_SOCKET("The socket is not readable. _sock_fd: %d", _sock_fd);
+            return 0;
+        }
+    }
+
+    remote.reset_address();
+    socklen_t remote_host_length = sizeof(remote._remote_host);
+
+    return _cc3000_module->_socket.recvfrom(_sock_fd, buffer, length, 0, (sockaddr *)&remote._remote_host, &remote_host_length);
+}
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/Socket/UDPSocket.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,69 @@
+/* Copyright (C) 2013 mbed.org, MIT License
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge, publish, distribute,
+ * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UDPSOCKET_H
+#define UDPSOCKET_H
+
+#include "Endpoint.h"
+#include "Socket.h"
+
+#include <cstdint>
+
+/**
+UDP Socket
+*/
+class UDPSocket: public Socket {
+
+public:
+    /** Instantiate an UDP Socket.
+    */
+    UDPSocket();
+
+    /** Init the UDP Client Socket without binding it to any specific port
+    \return 0 on success, -1 on failure.
+    */
+    int init(void);
+
+    /** Bind a UDP Server Socket to a specific port
+    \param port The port to listen for incoming connections on
+    \return 0 on success, -1 on failure.
+    */
+    int bind(int port = -1);
+
+    /** Send a packet to a remote endpoint
+    \param remote   The remote endpoint
+    \param packet   The packet to be sent
+    \param length   The length of the packet to be sent
+    \return the number of written bytes on success (>=0) or -1 on failure
+    */
+    int sendTo(Endpoint &remote, char *packet, int length);
+
+    /** Receive a packet from a remote endpoint
+    \param remote   The remote endpoint
+    \param buffer   The buffer for storing the incoming packet data. If a packet
+           is too long to fit in the supplied buffer, excess bytes are discarded
+    \param length   The length of the buffer
+    \return the number of received bytes on success (>=0) or -1 on failure
+    */
+    int receiveFrom(Endpoint &remote, char *buffer, int length);
+};
+
+#include "def.h"
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/cc3000.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,523 @@
+/*****************************************************************************
+*
+*  C++ interface/implementation created by Martin Kojtal (0xc0170). Thanks to
+*  Jim Carver and Frank Vannieuwkerke for their inital cc3000 mbed port and
+*  provided help.
+*
+*  This version of "host driver" uses CC3000 Host Driver Implementation. Thus
+*  read the following copyright:
+*
+*  Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*****************************************************************************/
+#include "cc3000.h"
+#include "cc3000_event.h"
+
+namespace mbed_cc3000 {
+
+/* TODO this prefix remove? verify */
+static uint8_t cc3000_prefix[] = {'T', 'T', 'T'};
+cc3000 *cc3000::_inst;
+
+cc3000::cc3000(PinName cc3000_irq, PinName cc3000_en, PinName cc3000_cs, SPI cc3000_spi)
+             : _event(_simple_link, _hci, _spi, *this), _socket(_simple_link, _hci, _event),
+               _spi(cc3000_irq, cc3000_en, cc3000_cs, cc3000_spi, _event, _simple_link), _hci(_spi),
+               _nvmem(_hci, _event, _simple_link), _netapp(_simple_link, _nvmem, _hci, _event),
+               _wlan(_simple_link, _event, _spi, _hci) {
+    _simple_link.set_tx_complete_signal(1);
+    memset(&_status, 0, sizeof(_status));
+    _inst = this;
+}
+
+cc3000::~cc3000() {
+}
+
+#if (CC3000_ETH_COMPAT == 1)
+cc3000::cc3000(PinName cc3000_irq, PinName cc3000_en, PinName cc3000_cs, SPI cc3000_spi, const char *ssid,
+               const char *phrase, Security sec, bool smart_config)
+             : _event(_simple_link, _hci, _spi, *this), _socket(_simple_link, _hci, _event),
+               _spi(cc3000_irq, cc3000_en, cc3000_cs, cc3000_spi, _event, _simple_link), _hci(_spi),
+               _nvmem(_hci, _event, _simple_link), _netapp(_simple_link, _nvmem, _hci, _event),
+               _wlan(_simple_link, _event, _spi, _hci), _sec(sec), _smart_config(smart_config) {
+    _simple_link.set_tx_complete_signal(1);
+    memset(&_status, 0, sizeof(_status));
+    strcpy((char *)_ssid, ssid);
+    strcpy((char *)_phrase, phrase);
+    _inst = this;
+}
+
+// Ethernet library compatible, functions return strings
+// Caches the ipconfig from the usync callback
+static char mac_addr[19]= "\0";
+static char ip_addr[17] = "\0";
+static char gateway[17] = "\0";
+static char networkmask[17] = "\0";
+
+void cc3000::init() {
+    _wlan.start(0);
+
+    uint32_t subnet[4] = {0};
+    uint32_t ip[4] = {0};
+    uint32_t getway[4] = {0};
+    uint32_t dns[4] = {0};
+
+    _netapp.dhcp(ip, subnet, getway, dns);
+    _wlan.stop();
+    wait(1);
+    _wlan.start(0);
+
+    _status.enabled = 1;
+    _wlan.set_event_mask(HCI_EVNT_WLAN_UNSOL_INIT | HCI_EVNT_WLAN_KEEPALIVE | HCI_EVNT_WLAN_ASYNC_PING_REPORT);
+}
+
+void cc3000::init(const char *ip, const char *mask, const char *gateway) {
+    _netapp.dhcp((uint32_t *)ip, (uint32_t *)mask, (uint32_t *)gateway, (uint32_t *)ip); //dns = ip
+    _wlan.stop();
+    wait(1);
+    _wlan.start(0);
+
+    _status.enabled = 1;
+    _wlan.set_event_mask(HCI_EVNT_WLAN_UNSOL_INIT | HCI_EVNT_WLAN_KEEPALIVE | HCI_EVNT_WLAN_ASYNC_PING_REPORT);
+}
+
+int cc3000::connect(unsigned int timeout_ms) {
+    Timer t;
+    int ret = 0;
+
+    if (_smart_config == false) {
+        _wlan.ioctl_set_connection_policy(0, 0, 0);
+    } else {
+        tUserFS user_info;
+        get_user_file_info((uint8_t *)&user_info, sizeof(user_info));
+        if (user_info.FTC == 1) {
+            _wlan.ioctl_set_connection_policy(0, 1, 1);
+        } else {
+            DBG_CC("Smart config is not set. Please run the first time configuration.");
+            return -1;
+        }
+    }
+
+    t.start();
+    while (is_connected() == false) {
+        if (strlen((const char *)_phrase) < 8) {
+            if (connect_open(_ssid)) {
+                break;
+            }
+        } else {
+#ifndef CC3000_TINY_DRIVER
+            if (connect_secure(_ssid,_phrase, _sec)) {
+                break;
+            }
+#else
+            return -1; /* secure connection not supported with TINY_DRIVER */
+#endif
+        }
+
+        if (t.read_ms() > timeout_ms) {
+            ret = -1;
+            DBG_CC("Connection to AP failed");
+            break;
+        }
+    }
+
+    while (is_dhcp_configured() == false)
+    {
+        if (t.read_ms() > timeout_ms) {
+            ret = -1;
+            DBG_CC("Connection to AP failed");
+            break;
+        }
+    }
+
+    return ret;
+}
+
+char* cc3000::getMACAddress() {
+    return mac_addr;
+}
+
+char* cc3000::getIPAddress() {
+    return ip_addr;
+}
+
+char* cc3000::getGateway() {
+    return gateway;
+}
+
+char* cc3000::getNetworkMask() {
+    return networkmask;
+}
+
+int cc3000::disconnect(void){
+    if (_wlan.disconnect()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+#endif
+
+void cc3000::usync_callback(int32_t event_type, uint8_t *data, uint8_t length) {
+    if (event_type == HCI_EVNT_WLAN_ASYNC_SIMPLE_CONFIG_DONE) {
+        DBG_CC("Callback : HCI_EVNT_WLAN_ASYNC_SIMPLE_CONFIG_DONE");
+        _status.smart_config_complete = 1;
+        _status.stop_smart_config = 1;
+    }
+
+    if (event_type == HCI_EVNT_WLAN_UNSOL_CONNECT) {
+        DBG_CC("Callback : HCI_EVNT_WLAN_UNSOL_CONNECT");
+        _status.connected = 1;
+        // Connect message is always followed by a DHCP message, connection is not useable until then
+        _status.dhcp      = 0;
+    }
+
+    if (event_type == HCI_EVNT_WLAN_UNSOL_DISCONNECT) {
+        DBG_CC("Callback : HCI_EVNT_WLAN_UNSOL_DISCONNECT");
+        _status.connected = 0;
+        _status.dhcp      = 0;
+        _status.dhcp_configured = 0;
+    }
+
+    if (event_type == HCI_EVNT_WLAN_UNSOL_DHCP) {
+#if (CC3000_ETH_COMPAT == 1)
+        _socket.inet_ntoa_r( htonl(*((uint32_t *)(&data[NETAPP_IPCONFIG_IP_OFFSET]))), ip_addr, 17);
+        _socket.inet_ntoa_r( htonl(*((uint32_t *)(&data[NETAPP_IPCONFIG_GW_OFFSET]))), gateway, 17);
+        _socket.inet_ntoa_r( htonl(*((uint32_t *)(&data[NETAPP_IPCONFIG_SUBNET_OFFSET]))), networkmask, 17);
+        _socket.inet_ntoa_r( htonl(*((uint32_t *)(&data[NETAPP_IPCONFIG_MAC_OFFSET]))), mac_addr, 19);
+#endif
+        if (*(data + NETAPP_IPCONFIG_MAC_OFFSET) == 0) {
+            _status.dhcp = 1;
+            DBG_CC("Callback : HCI_EVNT_WLAN_UNSOL_DHCP %i.%i.%i.%i", data[3], data[2], data[1], data[0]);
+        } else {
+            DBG_CC("Callback : HCI_EVNT_WLAN_UNSOL_DHCP - Disconnecting");
+            _status.dhcp = 0;
+        }
+    }
+
+    if (event_type == HCI_EVENT_CC3000_CAN_SHUT_DOWN) {
+        // Note this means the modules is idle, so it could be shutdown..
+        //DBG_CC("Callback : HCI_EVENT_CC3000_CAN_SHUT_DOWN");
+        _status.ok_to_shut_down = 1;
+    }
+
+    if (event_type == HCI_EVNT_WLAN_ASYNC_PING_REPORT) {
+        DBG_CC("Callback : HCI_EVNT_WLAN_ASYNC_PING_REPORT");
+        memcpy(&_ping_report, data, length);
+    }
+
+    if (event_type == HCI_EVNT_BSD_TCP_CLOSE_WAIT) {
+        uint8_t socketnum = data[0];
+        DBG_CC("Callback : HCI_EVNT_BSD_TCP_CLOSE_WAIT - Socket : %d", socketnum);
+        if (socketnum < MAX_SOCKETS) {
+            _closed_sockets[socketnum] = true; /* clients socket is closed */
+        }
+    }
+}
+
+void cc3000::start_smart_config(const uint8_t *smart_config_key) {
+    _status.smart_config_complete = 0;
+    _wlan.ioctl_set_connection_policy(0, 0, 0);
+
+    if (_status.connected == 1) {
+        disconnect();
+    }
+
+    //Wait until CC3000 is disconected
+    while (_status.connected == 1) {
+        wait_us(5);
+        _event.hci_unsolicited_event_handler();
+    }
+
+    // Trigger the Smart Config process
+    _wlan.smart_config_set_prefix(cc3000_prefix);
+    // Start the Smart Config process with AES disabled
+    _wlan.smart_config_start(0);
+
+    DBG_CC("Waiting for smartconfig to be completed");
+
+    // Wait for Smart config finished
+    while (_status.smart_config_complete == 0) {
+        wait_ms(100);
+    }
+
+    DBG_CC("Smartconfig finished");
+
+#ifndef CC3000_UNENCRYPTED_SMART_CONFIG
+    // create new entry for AES encryption key
+    _nvmem.create_entry(NVMEM_AES128_KEY_FILEID, 16);
+    // write AES key to NVMEM
+    _security.aes_write_key((uint8_t *)(&smart_config_key[0]));
+    // Decrypt configuration information and add profile
+    _wlan.smart_config_process();
+#endif
+
+    // Configure to connect automatically to the AP retrieved in the
+    // Smart config process
+    _wlan.ioctl_set_connection_policy(0, 0, 1);
+
+    // reset the CC3000
+    _wlan.stop();
+    _status.enabled = 0;
+    wait(5);
+    _wlan.start(0);
+    _status.enabled = 1;
+
+    // Mask out all non-required events
+    _wlan.set_event_mask(HCI_EVNT_WLAN_KEEPALIVE | HCI_EVNT_WLAN_UNSOL_INIT | HCI_EVNT_WLAN_ASYNC_PING_REPORT);
+}
+
+bool cc3000::connect_secure(const uint8_t *ssid, const uint8_t *key, int32_t security_mode) {
+#ifdef CC3000_TINY_DRIVER
+    return false; /* not supported*/
+#else
+    uint32_t ret;
+
+    //_wlan.disconnect();
+    wait_ms(3);
+    ret = _wlan.connect(security_mode, ssid, strlen((const char *)ssid), 0, (uint8_t *)key, strlen((const char *)key));
+    if (ret == 0) { /* TODO static internal cc3000 state 0 to TRUE */
+      ret = true;
+    } else {
+      ret = false;
+    }
+    return ret;
+#endif
+}
+
+bool cc3000::connect_non_blocking(const uint8_t *ssid, const uint8_t *key, int32_t security_mode)
+{
+    bool ret = false;
+
+    if (key == 0) {
+        if (connect_open(ssid)) {
+            ret = true;
+        }
+    } else {
+    #ifndef CC3000_TINY_DRIVER
+        if (connect_secure(ssid,key,security_mode)) {
+            ret = true;
+        }
+    #else
+        /* secure connection not supported with TINY_DRIVER */
+    #endif
+    }
+
+    return ret;
+}
+
+bool cc3000::connect_to_AP(const uint8_t *ssid, const uint8_t *key, int32_t security_mode) {
+    Timer t;
+    bool ret = true;
+
+    t.start();
+    while (is_connected() == false) {
+        if (key == 0) {
+            if (connect_open(ssid)) {
+                break;
+            }
+        } else {
+#ifndef CC3000_TINY_DRIVER
+            if (connect_secure(ssid,key,security_mode)) {
+                break;
+            }
+#else
+            return false; /* secure connection not supported with TINY_DRIVER */
+#endif
+        }
+
+        /* timeout 10 seconds */
+        if (t.read_ms() > 10000) {
+            ret = false;
+            DBG_CC("Connection to AP failed");
+            break;
+        }
+    }
+
+    return ret;
+}
+
+void cc3000::start(uint8_t patch) {
+    _wlan.start(patch);
+    _status.enabled = 1;
+    _wlan.set_event_mask(HCI_EVNT_WLAN_UNSOL_INIT | HCI_EVNT_WLAN_KEEPALIVE | HCI_EVNT_WLAN_ASYNC_PING_REPORT);
+}
+
+void cc3000::stop(void) {
+    _wlan.stop();
+    _status.enabled = 0;
+}
+
+void cc3000::restart(uint8_t patch) {
+    _wlan.stop();
+    _status.enabled = 0;
+    wait_ms(500);
+    _wlan.start(patch);
+    _status.enabled = 1;
+}
+
+bool cc3000::connect_open(const uint8_t *ssid) {
+    _wlan.disconnect();
+    wait_ms(3);
+    uint32_t ret;
+#ifndef CC3000_TINY_DRIVER
+    ret = _wlan.connect(0,ssid, strlen((const char *)ssid), 0, 0, 0);
+#else
+    ret = _wlan.connect(ssid, strlen((const char *)ssid));
+#endif
+    if (ret == 0) {
+        ret = true;
+    } else {
+        ret = false;
+    }
+    return ret;
+}
+
+bool cc3000::is_enabled()
+{
+    return _status.enabled;
+}
+
+bool cc3000::is_connected() {
+    if (( _status.connected ) && ( _status.dhcp )) {
+        return 1;
+    } else {
+        return 0;
+    }
+}
+
+bool cc3000::is_dhcp_configured() {
+    return _status.dhcp;
+}
+
+bool cc3000::is_smart_confing_completed() {
+    return _status.smart_config_complete;
+}
+
+uint8_t cc3000::get_mac_address(uint8_t address[6]) {
+    return _nvmem.get_mac_address(address);
+}
+
+uint8_t cc3000::set_mac_address(uint8_t address[6]) {
+    return _nvmem.set_mac_address(address);
+}
+
+void cc3000::get_user_file_info(uint8_t *info_file, size_t size) {
+    _nvmem.read( NVMEM_USER_FILE_1_FILEID, size, 0, info_file);
+}
+
+#ifndef CC3000_TINY_DRIVER
+bool cc3000::get_ip_config(tNetappIpconfigRetArgs *ip_config) {
+    if ((_status.dhcp == false) || (_status.connected == false)) {
+        return false;
+    }
+
+    _netapp.ipconfig(ip_config);
+    return true;
+}
+#endif
+
+void cc3000::delete_profiles(void) {
+    _wlan.ioctl_set_connection_policy(0, 0, 0);
+    _wlan.ioctl_del_profile(255);
+
+    tUserFS user_info;
+    get_user_file_info((uint8_t *)&user_info, sizeof(user_info));
+    user_info.FTC = 0;
+    set_user_file_info((uint8_t *)&user_info, sizeof(user_info));
+}
+
+void cc3000::set_user_file_info(uint8_t *info_file, size_t size) {
+    _nvmem.write( NVMEM_USER_FILE_1_FILEID, size, 0, info_file);
+}
+
+uint32_t cc3000::ping(uint32_t ip, uint8_t attempts, uint16_t timeout, uint8_t size) {
+#ifndef CC3000_TINY_DRIVER
+    uint32_t reversed_ip = (ip >> 24) | ((ip >> 8) & 0xFF00) | ((ip << 8) & 0xFF0000) | (ip << 24);
+
+    _ping_report.packets_received = 0;
+    if (_netapp.ping_send(&reversed_ip, attempts, size, timeout) == -1) {
+        DBG_CC("Failed to send ping");
+        return 0;
+    }
+    wait_ms(timeout*attempts*2);
+
+    /* known issue of cc3000 - sent number is send + received */
+    // TODO : Remove the Sent/recv'd counts until ti fix the firmware issue?
+    DBG_CC("Sent: %d",_ping_report.packets_sent);
+    DBG_CC("Received: %d",_ping_report.packets_received);
+    DBG_CC("Min time: %d",_ping_report.min_round_time);
+    DBG_CC("Max time: %d",_ping_report.max_round_time);
+    DBG_CC("Avg time: %d",_ping_report.avg_round_time);
+
+    return _ping_report.packets_received;
+#else
+    return 0;
+#endif
+}
+
+/* Conversion between uint types and C strings */
+uint8_t* UINT32_TO_STREAM_f (uint8_t *p, uint32_t u32)
+{
+    *(p)++ = (uint8_t)(u32);
+    *(p)++ = (uint8_t)((u32) >> 8);
+    *(p)++ = (uint8_t)((u32) >> 16);
+    *(p)++ = (uint8_t)((u32) >> 24);
+    return p;
+}
+
+
+uint8_t* UINT16_TO_STREAM_f (uint8_t *p, uint16_t u16)
+{
+    *(p)++ = (uint8_t)(u16);
+    *(p)++ = (uint8_t)((u16) >> 8);
+    return p;
+}
+
+
+uint16_t STREAM_TO_UINT16_f(uint8_t *p, uint16_t offset)
+{
+    return (uint16_t)((uint16_t)((uint16_t)
+           (*(p + offset + 1)) << 8) + (uint16_t)(*(p + offset)));
+}
+
+
+uint32_t STREAM_TO_UINT32_f(uint8_t *p, uint16_t offset)
+{
+    return (uint32_t)((uint32_t)((uint32_t)
+           (*(p + offset + 3)) << 24) + (uint32_t)((uint32_t)
+           (*(p + offset + 2)) << 16) + (uint32_t)((uint32_t)
+           (*(p + offset + 1)) << 8) + (uint32_t)(*(p + offset)));
+}
+
+} // mbed_cc3000 namespace
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/cc3000.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1827 @@
+/*****************************************************************************
+*
+*  C++ interface/implementation created by Martin Kojtal (0xc0170). Thanks to
+*  Jim Carver and Frank Vannieuwkerke for their inital cc3000 mbed port and
+*  provided help.
+*
+*  This version of "host driver" uses CC3000 Host Driver Implementation. Thus
+*  read the following copyright:
+*
+*  Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*****************************************************************************/
+#ifndef CC3000_H
+#define CC3000_H
+
+#include "mbed.h"
+#include "cc3000_common.h"
+#include "cc3000_spi.h"
+#include "cc3000_simplelink.h"
+#include "cc3000_netapp.h"
+#include "cc3000_nvmem.h"
+#include "cc3000_socket.h"
+
+#define MAX_SOCKETS 4
+// cc3000 Ethernet Interface - enabled by default
+#define CC3000_ETH_COMPAT   1
+
+/** Enable debug messages - set 1  */
+// Debug - Socket interface messages
+#define CC3000_DEBUG_SOCKET 0
+// Debug - HCI TX messages
+#define CC3000_DEBUG_HCI_TX 0
+// Debug - HCI Rx messages
+#define CC3000_DEBUG_HCI_RX 0
+// Debug - General Debug
+#define CC3000_DEBUG        0
+// Add colour to the debug messages, requires a VT100 terminal like putty, comment out to remove
+#define VT100_COLOUR        0
+
+#if (CC3000_DEBUG_SOCKET == 1)
+    #if (VT100_COLOUR == 1)
+        #define DBG_SOCKET(x, ...) std::printf("\x1b[2;32;40m[CC3000 : SOCKET] "x"\x1b[0;37;40m\r\n", ##__VA_ARGS__);
+    #else
+        #define DBG_SOCKET(x, ...) std::printf("[CC3000 : SOCKET] "x"\r\n", ##__VA_ARGS__);
+    #endif
+#else
+    #define DBG_SOCKET(x, ...)
+#endif
+
+#if (CC3000_DEBUG_HCI_TX == 1)
+    #if (VT100_COLOUR == 1)
+        #define DBG_HCI(x, ...) std::printf("\x1b[2;35;40m[CC3000 : HCI RX] "x"\x1b[0;37;40m\r\n", ##__VA_ARGS__);
+    #else
+        #define DBG_HCI(x, ...) std::printf("[CC3000 : HCI RX] "x"\r\n", ##__VA_ARGS__);
+    #endif
+#else
+    #define DBG_HCI(x, ...)
+#endif
+
+#if (CC3000_DEBUG_HCI_RX == 1)
+    #if (VT100_COLOUR == 1)
+        #define DBG_HCI_CMD(x, ...) std::printf("\x1b[2;36;40m[CC3000 : HCI TX] "x"\x1b[0;37;40m\r\n", ##__VA_ARGS__);
+    #else
+        #define DBG_HCI_CMD(x, ...) std::printf("[CC3000 : HCI TX] "x"\r\n", ##__VA_ARGS__);
+    #endif
+#else
+    #define DBG_HCI_CMD(x, ...)
+#endif
+
+#if (CC3000_DEBUG == 1)
+    #if (VT100_COLOUR == 1)
+        #define DBG_CC(x, ...) std::printf("\x1b[2;32;40m[CC3000] "x"\x1b[0;37;40m\r\n", ##__VA_ARGS__);
+    #else
+        #define DBG_CC(x, ...) std::printf("[CC3000] "x"\r\n", ##__VA_ARGS__);
+    #endif
+#else
+    #define DBG_CC(x, ...)
+#endif
+
+namespace mbed_cc3000 {
+
+/** User info structure
+ */
+typedef struct {
+    uint8_t FTC;           // First time config performed
+    uint8_t PP_version[2]; // Patch Programmer version
+    uint8_t SERV_PACK[2];  // Service Pack Version
+    uint8_t DRV_VER[3];    // Driver Version
+    uint8_t FW_VER[3];     // Firmware Version
+    uint8_t validCIK;      // CIK[] is valid (Client Interface Key)
+    uint8_t CIK[40];
+} tUserFS;
+
+/** Function pointers which are not yet implemented
+ */
+enum FunctionNumber {
+    FW_PATCHES          = 0,
+    DRIVER_PATCHES      = 1,
+    BOOTLOADER_PATCHES  = 2,
+};
+
+/** AP security
+ */
+enum Security {
+    NONE = 0,
+    WEP  = 1,
+    WPA  = 2,
+    WPA2 = 3
+};
+
+/** CC3000 Simple Link class which contains status of cc3000.
+ */
+class cc3000_simple_link {
+public:
+    /**
+     *  \brief ctor - sets magic number in the buffers (overflow mark).
+     *  \param none
+     *  \return none
+     */
+    cc3000_simple_link();
+    /**
+     *  \brief dtor
+     *  \param none
+     *  \return none
+     */
+    ~cc3000_simple_link();
+    /**
+     *  \brief Returns data received flag.
+     *  \return Data received flag.
+     */
+    uint8_t get_data_received_flag();
+    /**
+     *  \brief Set data received flag.
+     *  \param value The value to be set.
+     */
+    void set_data_received_flag(uint8_t value);
+    /** Returns if tx was completed.
+     *  \return
+     *    true if tx was completed,
+     *    false otherwise.
+     */
+    bool get_tx_complete_signal();
+    /**
+     *  \brief Sets flag that tx was completed.
+     *  \param value Value to be set
+     *  \return none
+     */
+    void set_tx_complete_signal(bool value);
+    /**
+     *  \brief Get receive buffer.
+     *  \param none
+     *  \return Pointer to the receive buffer.
+     */
+    uint8_t *get_received_buffer();
+    /**
+     *  \brief Get transmit buffer.
+     *  \param none
+     *  \return Pointer to the transmit buffer.
+     */
+    uint8_t *get_transmit_buffer();
+    /**
+     *  \brief Get number of free buffers.
+     *  \param none
+     *  \return
+     *      Number of free buffers.
+     */
+    uint16_t get_number_free_buffers();
+    /**
+     *  \brief Set number of free buffers.
+     *  \param value Number of free buffers.
+     *  \return none
+     */
+    void set_number_free_buffers(uint16_t value);
+    /**
+     *  \brief Retrieve buffer length.
+     *  \param none
+     *  \return Buffer length
+     */
+    uint16_t get_buffer_length();
+    /**
+     *  \brief Set buffer length
+     *  \param value The length
+     *  \return none
+     */
+    void set_buffer_length(uint16_t value);
+    /**
+     *  \brief Retrieve pending data flag.
+     *  \param none
+     *  \return Pending data flag
+     */
+    uint16_t get_pending_data();
+    /**
+     *  \brief Set pending data flag.
+     *  \param value Pending data value.
+     *  \return none
+     */
+    void set_pending_data(uint16_t value);
+    /**
+     *  \brief Retreive op code.
+     *  \param none
+     *  \return Op code
+     */
+    uint16_t get_op_code();
+    /**
+     *  \brief Set op code.
+     *  \param code op code.
+     *  \return none
+     */
+    void set_op_code(uint16_t code);
+    /**
+     *  \brief Get number of released packets.
+     *  \param none
+     *  \return Number of released packets.
+     */
+    uint16_t get_released_packets();
+    /**
+     *  \brief Set number of released packets.
+     *  \param value Number of released packets.
+     *  \return none
+     */
+    void set_number_of_released_packets(uint16_t value);
+    /**
+     *  \brief Get number of sent packats
+     *  \param none
+     *  \return Number of sent packets.
+     */
+    uint16_t get_sent_packets();
+    /**
+     *  \brief Set number of sent packets
+     *  \param value Number of sent packets.
+     *  \return none
+     */
+    void set_sent_packets(uint16_t value);
+    /**
+     *  \brief Retrieve transmit error
+     *  \param none
+     *  \return Transmit error
+     */
+    int32_t get_transmit_error();
+    /**
+     *  \brief Set transmit error.
+     *  \param value Error to be set.
+     *  \return none
+     */
+    void set_transmit_error(int32_t value);
+    /**
+     *  \brief Get buffer size.
+     *  \param none
+     *  \return Size of buffer.
+     */
+    uint16_t get_buffer_size();
+    /**
+     *  \brief Set buffer size.
+     *  \param value Buffer size.
+     *  \return none
+     */
+    void set_buffer_size(uint16_t value);
+    /**
+     *  \brief Not used currently.
+     *  \param function Number of desired function.
+     *  \return void pointer to the function (need to recast).
+     */
+    void *get_func_pointer(FunctionNumber function);
+    /**
+     *  \brief Retreive pointer to the received data.
+     *  \param none
+     *  \return Pointer to the received data buffer.
+     */
+    uint8_t *get_received_data();
+    /**
+     *  \brief Set received data pointer.
+     *  \param pointer Pointer to the buffer.
+     *  \return none
+     */
+    void set_received_data(uint8_t *pointer);
+private:
+    uint8_t  _data_received_flag;
+    bool     _tx_complete_signal;
+    uint16_t _rx_event_opcode;
+    uint16_t _free_buffers;
+    uint16_t _buffer_length;
+    uint16_t _buffer_size;
+    uint16_t _rx_data_pending;
+    uint16_t _sent_packets;
+    uint16_t _released_packets;
+    int32_t  _transmit_data_error;
+    uint8_t  *_received_data;
+    uint8_t  _rx_buffer[CC3000_RX_BUFFER_SIZE];
+    uint8_t  _tx_buffer[CC3000_TX_BUFFER_SIZE];
+private:
+    /* Not used currently */
+    int8_t *(* _fFWPatches)(uint32_t *length);
+    int8_t *(* _fDriverPatches)(uint32_t *length);
+    int8_t *(* _fBootLoaderPatches)(uint32_t *length);
+};
+
+/** Forward declaration classes
+ */
+class cc3000_hci;
+class cc3000_nvmem;
+class cc3000_spi;
+class cc3000;
+
+/** Event layer
+ */
+class cc3000_event {
+public:
+    /**
+     *  \brief Ctor
+     *  \param simplelink Reference to simple link object.
+     *  \param hci        Reference to hci object.
+     *  \param spi        Reference to spi object.
+     *  \param cc3000     Reference to cc3000 object.
+     *  \return none
+     */
+    cc3000_event(cc3000_simple_link &simplelink, cc3000_hci &hci, cc3000_spi &spi, cc3000 &cc3000);
+    /**
+     *  \brief Dtor
+     *  \param none
+     *  \return none
+     */
+     ~cc3000_event();
+    /**
+     *  \brief Handle unsolicited event from type patch request.
+     *  \param  event_hdr  event header
+     *  \return none
+     */
+    void hci_unsol_handle_patch_request(uint8_t *event_hdr);
+    /**
+    *  \brief  Parse the incoming event packets and issue corresponding event handler from global array of handlers pointers.
+    *  \param  ret_param      incoming data buffer
+    *  \param  from           from information (in case of data received)
+    *  \param  fromlen        from information length (in case of data received)
+    *  \return                none
+    */
+    uint8_t* hci_event_handler(void *ret_param, uint8_t *from, uint8_t *fromlen);
+    /**
+    *  \brief  Handle unsolicited events.
+    *  \param  event_hdr Event header
+    *  \return           1 if event supported and handled
+    *  \return           0 if event is not supported
+    */
+    int32_t hci_unsol_event_handler(uint8_t *event_hdr);
+    /**
+    *  \brief   Parse the incoming unsolicited event packets and start corresponding event handler.
+    *  \param   None
+    *  \return  ESUCCESS if successful, EFAIL if an error occurred.
+    */
+    int32_t hci_unsolicited_event_handler(void);
+    /**
+    *  \brief  Get the socket status.
+    *  \param  Sd Socket IS
+    *  \return Current status of the socket.
+    */
+    int32_t get_socket_active_status(int32_t sd);
+    /**
+    *  \brief Check if the socket ID and status are valid and set the global socket status accordingly.
+    *  \param Sd Sock descr
+    *  \param Status status to be set
+    *  \return  none
+    */
+    void set_socket_active_status(int32_t sd, int32_t status);
+    /**
+    *  \brief Keep track on the number of packets transmitted and update the number of free buffer in the SL device.
+    *  \brief Called when unsolicited event = HCI_EVNT_DATA_UNSOL_FREE_BUFF has received.
+    *  \param event pointer to the string contains parameters for IPERF.
+    *  \return ESUCCESS if successful, EFAIL if an error occurred.
+    */
+    int32_t hci_event_unsol_flowcontrol_handler(uint8_t *event);
+    /**
+    *  \brief Update the socket status.
+    *  \param resp_params Socket IS
+    *  \return Current status of the socket.
+    */
+    void update_socket_active_status(uint8_t *resp_params);
+    /**
+     *  \brief  Wait for event, pass it to the hci_event_handler and update the event opcode in a global variable.
+     *  \param  op_code   Command operation code
+     *  \param  ret_param Command return parameters
+     *  \return none
+     */
+    void simplelink_wait_event(uint16_t op_code, void *ret_param);
+    /**
+     *  \brief  Wait for data, pass it to the hci_event_handler and set the data available flag.
+     *  \param  buffer  Data buffer
+     *  \param  from    From information
+     *  \param  fromlen From information length
+     *  \return none
+     */
+    void simplelink_wait_data(uint8_t *buffer, uint8_t *from, uint8_t *fromlen);
+    /**
+     *  \brief Trigger Received event/data processing - called from the SPI library to receive the data
+     *  \param buffer pointer to the received data buffer\n
+     *                The function triggers Received event/data processing\n
+     *  \return none
+     */
+    void received_handler(uint8_t *buffer);
+private:
+    uint32_t            socket_active_status;
+    cc3000_simple_link  &_simple_link;
+    cc3000_hci          &_hci;
+    cc3000_spi          &_spi;
+    cc3000              &_cc3000;
+};
+
+/** Netapp layer
+ */
+class cc3000_netapp {
+public:
+    /**
+     *  \brief Ctor
+     *  \param simple_link Reference to the simple link object.
+     *  \param nvmem       Reference to the nvmem object.
+     *  \param hci         Reference to the hci object.
+     *  \param event       Reference to the event object.
+     *  \return none
+     */
+    cc3000_netapp(cc3000_simple_link &simple_link, cc3000_nvmem &nvmem, cc3000_hci &hci, cc3000_event &event);
+    /**
+     *  \brief Dtor
+     *  \param none
+     *  \return none
+     */
+    ~cc3000_netapp();
+    /**
+     *  \brief Configure device MAC address and store it in NVMEM.
+     *         The value of the MAC address configured through the API will be\n
+     *         stored in CC3000 non volatile memory, thus preserved over resets.\n
+     *  \param  mac   device mac address, 6 bytes. Saved: yes
+     *  \return       return on success 0, otherwise error.
+     */
+    int32_t config_mac_adrress(uint8_t *mac);
+    /**
+     *  \brief Configure the network interface, static or dynamic (DHCP).
+     *         In order to activate DHCP mode, ip, subnet_mask, default_gateway must be 0.\n
+     *         The default mode of CC3000 is DHCP mode. The configuration is saved in non volatile memory\n
+     *         and thus preserved over resets.\n
+     *  \param  ip                device mac address, 6 bytes. Saved: yes
+     *  \param  subnet_mask       device mac address, 6 bytes. Saved: yes
+     *  \param  default_gateway   device mac address, 6 bytes. Saved: yes
+     *  \param  dns_server        device mac address, 6 bytes. Saved: yes
+     *  \return 0 on success, otherwise error.
+     *  \note   If the mode is altered, a reset of CC3000 device is required to apply the changes.\n
+     *          Also note that an asynchronous event of type 'DHCP_EVENT' is generated only when\n
+     *          a connection to the AP was established. This event is generated when an IP address\n
+     *          is allocated either by the DHCP server or by static allocation.\n
+     */
+    int32_t dhcp(uint32_t *ip, uint32_t *subnet_mask,uint32_t *default_gateway, uint32_t *dns_server);
+#ifndef CC3000_TINY_DRIVER
+    /**
+     *  \brief Get the CC3000 Network interface information.
+     *        This information is only available after establishing a WLAN connection.\n
+     *        Undefined values are returned when this function is called before association.\n
+     *  \param  ipconfig  pointer to a tNetappIpconfigRetArgs structure for storing the network interface configuration.\n
+     *          tNetappIpconfigRetArgs: aucIP             - ip address,\n
+     *                                  aucSubnetMask     - mask
+     *                                  aucDefaultGateway - default gateway address\n
+     *                                  aucDHCPServer     - dhcp server address\n
+     *                                  aucDNSServer      - dns server address\n
+     *                                  uaMacAddr         - mac address\n
+     *                                  uaSSID            - connected AP ssid\n
+     *  \return  none
+     *  \note    This function is useful for figuring out the IP Configuration of\n
+     *           the device when DHCP is used and for figuring out the SSID of\n
+     *           the Wireless network the device is associated with.\n
+     */
+    void ipconfig(tNetappIpconfigRetArgs *ipconfig);
+    /**
+     *  \brief Set new timeout values for DHCP lease timeout, ARP  refresh timeout, keepalive event timeout and socket inactivity timeout
+     *  \param  dhcp       DHCP lease time request, also impact\n
+     *                     the DHCP renew timeout.\n
+     *                     Range:               [0-0xffffffff] seconds,\n
+     *                                          0 or 0xffffffff = infinite lease timeout.\n
+     *                     Resolution:          10 seconds.\n
+     *                     Influence:           only after reconnecting to the AP. \n
+     *                     Minimal bound value: MIN_TIMER_VAL_SECONDS - 20 seconds.\n
+     *                     The parameter is saved into the CC3000 NVMEM.\n
+     *                     The default value on CC3000 is 14400 seconds.\n
+     *
+     *  \param  arp        ARP refresh timeout, if ARP entry is not updated by\n
+     *                     incoming packet, the ARP entry will be  deleted by\n
+     *                     the end of the timeout. \n
+     *                     Range:               [0-0xffffffff] seconds, 0 = infinite ARP timeout\n
+     *                     Resolution:          10 seconds.\n
+     *                     Influence:           at runtime.\n
+     *                     Minimal bound value: MIN_TIMER_VAL_SECONDS - 20 seconds\n
+     *                     The parameter is saved into the CC3000 NVMEM.\n
+     *                     The default value on CC3000 is 3600 seconds.\n
+     *
+     *  \param  keep_alive     Keepalive event sent by the end of keepalive timeout\n
+     *                         Range:               [0-0xffffffff] seconds, 0 == infinite timeout\n
+     *                         Resolution:          10 seconds.\n
+     *                         Influence:           at runtime.\n
+     *                         Minimal bound value: MIN_TIMER_VAL_SECONDS - 20 sec\n
+     *                         The parameter is saved into the CC3000 NVMEM. \n
+     *                         The default value on CC3000 is 10 seconds.\n
+     *
+     *  \param  inactivity      Socket inactivity timeout, socket timeout is\n
+     *                          refreshed by incoming or outgoing packet, by the\n
+     *                          end of the socket timeout the socket will be closed\n
+     *                          Range:               [0-0xffffffff] sec, 0 == infinite timeout.\n
+     *                          Resolution:          10 seconds.\n
+     *                          Influence:           at runtime.\n
+     *                          Minimal bound value: MIN_TIMER_VAL_SECONDS - 20 sec\n
+     *                          The parameter is saved into the CC3000 NVMEM.\n
+     *                          The default value on CC3000 is 60 seconds.\n
+     *
+     *  \return 0 on success,otherwise error.
+     *
+     *  \note   A parameter set to a non zero value less than 20s automatically changes to 20s.
+     */
+    int32_t timeout_values(uint32_t *dhcp, uint32_t *arp,uint32_t *keep_alive, uint32_t *inactivity);
+    /**
+     *  \brief send ICMP ECHO_REQUEST to network hosts
+     *  \param  ip              destination IP address
+     *  \param  ping_attempts   number of echo requests to send
+     *  \param  ping_size       send buffer size which may be up to 1400 bytes
+     *  \param  ping_timeout    Time to wait for a response,in milliseconds.
+     *  \return 0 on success, otherwise error.
+     *
+     *  \note     A succesful operation will generate an asynchronous ping report event.\n
+     *            The report structure is defined by structure netapp_pingreport_args_t.\n
+     *  \warning  Calling this function while a Ping Request is in progress will kill the ping request in progress.
+     */
+    int32_t ping_send(uint32_t *ip, uint32_t ping_attempts, uint32_t ping_size, uint32_t ping_timeout);
+    /**
+     *  \brief Ping status request.
+     *         This API triggers the CC3000 to send asynchronous events: HCI_EVNT_WLAN_ASYNC_PING_REPORT.\n
+     *         This event will create the report structure in netapp_pingreport_args_t.\n
+     *         This structure is filled with ping results until the API is triggered.\n
+     *         netapp_pingreport_args_t: packets_sent     - echo sent\n
+     *                                   packets_received - echo reply\n
+     *                                   min_round_time   - minimum round time\n
+     *                                   max_round_time   - max round time\n
+     *                                   avg_round_time   - average round time\n
+     *
+     *  \param   none
+     *  \return  none
+     *  \note    When a ping operation is not active, the returned structure fields are 0.
+     */
+    void ping_report();
+    /**
+     *  \brief Stop any ping request.
+     *  \param none
+     *  \return 0 on success
+     *         -1 on error
+     */
+    int32_t ping_stop();
+    /**
+     *  \brief Flush ARP table
+     *  \param none
+     *  \return none
+     */
+    int32_t arp_flush();
+#endif
+private:
+    cc3000_simple_link  &_simple_link;
+    cc3000_nvmem        &_nvmem;
+    cc3000_hci          &_hci;
+    cc3000_event        &_event;
+};
+
+#ifndef CC3000_UNENCRYPTED_SMART_CONFIG
+/** Security class used only if encrypted smart config is set
+ */
+class cc3000_security {
+public:
+    /**
+     *  \brief Expand a 16 bytes key for AES128 implementation.
+     *  \param expanded_key expanded AES128 key
+     *  \param key AES128 key - 16 bytes
+     *  \return none
+     */
+    void expandKey(uint8_t *expanded_key, uint8_t *key);
+    /**
+     *  \brief multiply by 2 in the galois field.
+     *  \param value Argument to multiply
+     *  \return multiplied argument
+     */
+    uint8_t galois_mul2(uint8_t value);
+    /**
+     *  \brief internal implementation of AES128 encryption.
+     *      straight forward aes encryption implementation\n
+     *      first the group of operations
+     *      - addRoundKey
+     *      - subbytes
+     *      - shiftrows
+     *      - mixcolums\n
+     *
+     *      is executed 9 times, after this addroundkey to finish the 9th\n
+     *      round, after that the 10th round without mixcolums\n
+     *      no further subfunctions to save cycles for function calls\n
+     *      no structuring with "for (....)" to save cycles.\n
+     *  \param[in]     expanded_key expanded AES128 key
+     *  \param[in/out] state 16 bytes of plain text and cipher text
+     *  \return  none
+     */
+    void aes_encr(uint8_t *state, uint8_t *expanded_key);
+    /**
+     *  \brief internal implementation of AES128 decryption.
+     *      straightforward aes decryption implementation\n
+     *      the order of substeps is the exact reverse of decryption\n
+     *      inverse functions:
+     *      - addRoundKey is its own inverse
+     *      - rsbox is inverse of sbox
+     *      - rightshift instead of leftshift
+     *      - invMixColumns = barreto + mixColumns\n
+     *
+     *      no further subfunctions to save cycles for function calls\n
+     *      no structuring with "for (....)" to save cycles\n
+     *  \param[in]     expanded_key expanded AES128 key
+     *  \param[in\out] state 16 bytes of cipher text and plain text
+     *  \return  none
+     */
+    void aes_decr(uint8_t *state, uint8_t *expanded_key);
+    /**
+     *  \brief AES128 encryption.
+     *      Given AES128 key and 16 bytes plain text, cipher text of 16 bytes is computed.\n
+     *      The AES implementation is in mode ECB (Electronic Code Book).\n
+     *  \param[in]  key   AES128 key of size 16 bytes
+     *  \param[in\out] state   16 bytes of plain text and cipher text
+     *  \return  none
+     */
+    void aes_encrypt(uint8_t *state, uint8_t *key);
+    /**
+     *  \brief AES128 decryption.
+     *      Given AES128 key and  16 bytes cipher text, plain text of 16 bytes is computed.\n
+     *      The AES implementation is in mode ECB (Electronic Code Book).\n
+     *  \param[in]  key   AES128 key of size 16 bytes
+     *  \param[in\out] state   16 bytes of cipher text and plain text
+     *  \return  none
+     */
+    void aes_decrypt(uint8_t *state, uint8_t *key);
+    /**
+     *  \brief Read the AES128 key from fileID #12 in EEPROM.
+     *  \param[out]  key   AES128 key of size 16 bytes
+     *  \return  0 on success, error otherwise.
+     */
+    int32_t aes_read_key(uint8_t *key);
+    /**
+     *  \brief Write the AES128 key to fileID #12 in EEPROM.
+     *  \param[out]  key   AES128 key of size 16 bytes
+     *  \return  on success 0, error otherwise.
+     */
+    int32_t aes_write_key(uint8_t *key);
+private:
+    uint8_t _expanded_key[176];
+};
+#endif
+
+/** Socket layer
+ */
+class cc3000_socket {
+public:
+    /**
+     *  \brief Ctor
+     *  \param simplelink Reference to simple link object.
+     *  \param hci        Reference to hci object.
+     *  \param event      Reference to event object.
+     *  \return none
+     */
+    cc3000_socket(cc3000_simple_link &simplelink, cc3000_hci &hci, cc3000_event &event);
+    /**
+     *  \brief Dtor
+     *  \param
+     *  \return none
+     */
+    ~cc3000_socket();
+    /**
+     *  \brief create an endpoint for communication.
+     *      The socket function creates a socket that is bound to a specific transport service provider.\n
+     *      This function is called by the application layer to obtain a socket handle.\n
+     *
+     *  \param   domain    selects the protocol family which will be used for\n
+     *                     communication. On this version only AF_INET is supported\n
+     *  \param   type      specifies the communication semantics. On this version\n
+     *                     only SOCK_STREAM, SOCK_DGRAM, SOCK_RAW are supported\n
+     *  \param   protocol  specifies a particular protocol to be used with the\n
+     *                     socket IPPROTO_TCP, IPPROTO_UDP or IPPROTO_RAW are supported.\n
+     *  \return  On success, socket handle that is used for consequent socket operations\n
+     *           On error, -1 is returned.\n
+     */
+    int32_t socket(int32_t domain, int32_t type, int32_t protocol);
+    /**
+     *  \brief accept a connection on a socket.
+     *      This function is used with connection-based socket types\n
+     *      (SOCK_STREAM). It extracts the first connection request on the\n
+     *      queue of pending connections, creates a new connected socket, and\n
+     *      returns a new file descriptor referring to that socket.\n
+     *      The newly created socket is not in the listening state.\n
+     *      The original socket sd is unaffected by this call.\n
+     *      The argument sd is a socket that has been created with socket(),\n
+     *      bound to a local address with bind(), and is  listening for \n
+     *      connections after a listen(). The argument addr is a pointer \n
+     *      to a sockaddr structure. This structure is filled in with the \n
+     *      address of the peer socket, as known to the communications layer.\n
+     *      The exact format of the address returned addr is determined by the \n
+     *      socket's address family. The addrlen argument is a value-result\n
+     *      argument: it should initially contain the size of the structure\n
+     *      pointed to by addr, on return it will contain the actual\n
+     *      length (in bytes) of the address returned.\n
+     *
+     *  \param[in]   sd      socket descriptor (handle)\n
+     *  \param[out]  addr    the argument addr is a pointer to a sockaddr structure\n
+     *                       This structure is filled in with the address of the \n
+     *                       peer socket, as known to the communications layer.  \n
+     *                       determined. The exact format of the address returned \n
+     *                       addr is by the socket's address sockaddr. \n
+     *                       On this version only AF_INET is supported.\n
+     *                       This argument returns in network order.\n
+     *  \param[out] addrlen  the addrlen argument is a value-result argument: \n
+     *                       it should initially contain the size of the structure\n
+     *                       pointed to by addr.\n
+     *  \return  For socket in blocking mode:\n
+     *            - On success, socket handle. on failure negative\n
+     *           For socket in non-blocking mode:\n
+     *            - On connection establishment, socket handle\n
+     *            - On connection pending, SOC_IN_PROGRESS (-2)\n
+     *            - On failure, SOC_ERROR    (-1)\n
+     *  \sa     socket ; bind ; listen
+     */
+    int32_t accept(int32_t sd, sockaddr *addr, socklen_t *addrlen);
+    /**
+     *  \brief assign a name to a socket.
+     *      This function gives the socket the local address addr.\n
+     *      addr is addrlen bytes long. Traditionally, this is called when a \n
+     *      socket is created with socket, it exists in a name space (address \n
+     *      family) but has no name assigned.\n
+     *      It is necessary to assign a local address before a SOCK_STREAM\n
+     *      socket may receive connections.\n
+     *
+     *  \param[in]   sd      socket descriptor (handle)
+     *  \param[out]  addr    specifies the destination address. On this version\n
+     *                       only AF_INET is supported.\n
+     *  \param[out] addrlen  contains the size of the structure pointed to by addr.\n
+     *  \return      On success, zero is returned.\n
+     *               On error, -1 is returned.\n
+     *  \sa          socket ; accept ; listen
+     */
+    int32_t bind(int32_t sd, const sockaddr *addr, int32_t addrlen);
+    /**
+     *  \brief HostFlowControlConsumeBuff.
+     *      if SEND_NON_BLOCKING is not defined - block until a free buffer is available,\n
+     *      otherwise return the status of the available buffers.\n
+     *
+     *  \param  sd  socket descriptor
+     *  \return  0 in case there are buffers available, \n
+     *          -1 in case of bad socket\n
+     *          -2 if there are no free buffers present (only when SEND_NON_BLOCKING is enabled)\n
+     */
+    int32_t HostFlowControlConsumeBuff(int32_t sd);
+    /**
+     *  \brief The socket function closes a created socket.
+     *  \param   sd    socket handle.
+     *  \return  On success, zero is returned. On error, -1 is returned.
+     */
+    int32_t closesocket(int32_t sd);
+    /**
+     *  \brief listen for connections on a socket.
+     *      The willingness to accept incoming connections and a queue\n
+     *      limit for incoming connections are specified with listen(),\n
+     *      and then the connections are accepted with accept.\n
+     *      The listen() call applies only to sockets of type SOCK_STREAM\n
+     *      The backlog parameter defines the maximum length the queue of\n
+     *      pending connections may grow to. \n
+     *
+     *  \param[in]  sd       socket descriptor (handle)
+     *  \param[in]  backlog  specifies the listen queue depth. On this version\n
+     *                       backlog is not supported.\n
+     *  \return     On success, zero is returned.\n
+     *              On error, -1 is returned.\n
+     *  \sa         socket ; accept ; bind
+     *  \note       On this version, backlog is not supported
+     */
+    int32_t listen(int32_t sd, int32_t backlog);
+    /**
+     *  \brief initiate a connection on a socket.
+     *      Function connects the socket referred to by the socket descriptor\n
+     *      sd, to the address specified by addr. The addrlen argument \n
+     *      specifies the size of addr. The format of the address in addr is \n
+     *      determined by the address space of the socket. If it is of type \n
+     *      SOCK_DGRAM, this call specifies the peer with which the socket is \n
+     *      to be associated; this address is that to which datagrams are to be\n
+     *      sent, and the only address from which datagrams are to be received. \n
+     *      If the socket is of type SOCK_STREAM, this call attempts to make a \n
+     *      connection to another socket. The other socket is specified  by \n
+     *      address, which is an address in the communications space of the\n
+     *      socket. Note that the function implements only blocking behavior \n
+     *      thus the caller will be waiting either for the connection \n
+     *      establishment or for the connection establishment failure.\n
+     *
+     *  \param[in]   sd       socket descriptor (handle)
+     *  \param[in]   addr     specifies the destination addr. On this version\n
+     *                        only AF_INET is supported.\n
+     *  \param[out]  addrlen  contains the size of the structure pointed to by addr
+     *  \return      On success, zero is returned.\n
+                   On error, -1 is returned\n
+     *  \sa socket
+     */
+    int32_t connect(int32_t sd, const sockaddr *addr, int32_t addrlen);
+    /**
+     *  \brief Monitor socket activity.
+     *      Select allow a program to monitor multiple file descriptors,\n
+     *      waiting until one or more of the file descriptors become \n
+     *      "ready" for some class of I/O operation \n
+     *
+     *  \param[in]    nfds       the highest-numbered file descriptor in any of the\n
+     *                           three sets, plus 1.  \n
+     *  \param[out]   readsds    socket descriptors list for read monitoring\n
+     *  \param[out]   writesds   socket descriptors list for write monitoring\n
+     *  \param[out]   exceptsds  socket descriptors list for exception monitoring\n
+     *  \param[in]    timeout    is an upper bound on the amount of time elapsed\n
+     *                           before select() returns. Null means infinity \n
+     *                           timeout. The minimum timeout is 5 milliseconds,\n
+     *                          less than 5 milliseconds will be set\n
+     *                           automatically to 5 milliseconds.\n
+     *  \return    On success, select() returns the number of file descriptors\n
+     *             contained in the three returned descriptor sets (that is, the\n
+     *             total number of bits that are set in readfds, writefds,\n
+     *             exceptfds) which may be zero if the timeout expires before\n
+     *             anything interesting  happens.\n
+     *             On error, -1 is returned.\n
+     *                   *readsds - return the sockets on which Read request will\n
+     *                              return without delay with valid data.\n
+     *                   *writesds - return the sockets on which Write request \n
+     *                                 will return without delay.\n
+     *                   *exceptsds - return the sockets which closed recently.\n
+     *  \Note   If the timeout value set to less than 5ms it will automatically\n
+     *          change to 5ms to prevent overload of the system\n
+     *  \sa socket
+     */
+    int32_t select(int32_t nfds, fd_set *readsds, fd_set *writesds, fd_set *exceptsds, struct timeval *timeout);
+    /**
+     *  \brief get socket options.
+     *      This function manipulate the options associated with a socket.\n
+     *      Options may exist at multiple protocol levels; they are always\n
+     *      present at the uppermost socket level.\n
+     *      When manipulating socket options the level at which the option \n
+     *      resides and the name of the option must be specified.  \n
+     *      To manipulate options at the socket level, level is specified as \n
+     *      SOL_SOCKET. To manipulate options at any other level the protocol \n
+     *      number of the appropriate protocol controlling the option is \n
+     *      supplied. For example, to indicate that an option is to be \n
+     *      interpreted by the TCP protocol, level should be set to the \n
+     *      protocol number of TCP; \n
+     *      The parameters optval and optlen are used to access optval -\n
+     *      use for setsockopt(). For getsockopt() they identify a buffer\n
+     *      in which the value for the requested option(s) are to \n
+     *      be returned. For getsockopt(), optlen is a value-result \n
+     *      parameter, initially containing the size of the buffer \n
+     *      pointed to by option_value, and modified on return to \n
+     *      indicate the actual size of the value returned. If no option \n
+     *      value is to be supplied or returned, option_value may be NULL.\n
+     *
+     *  \param[in]   sd          socket handle
+     *  \param[in]   level       defines the protocol level for this option
+     *  \param[in]   optname     defines the option name to Interrogate
+     *  \param[out]  optval      specifies a value for the option
+     *  \param[out]  optlen      specifies the length of the option value
+     *  \return      On success, zero is returned. On error, -1 is returned
+     *
+     *  \Note   On this version the following two socket options are enabled:\n
+     *          The only protocol level supported in this version is SOL_SOCKET (level).\n
+     *               1. SOCKOPT_RECV_TIMEOUT (optname)\n
+     *                  SOCKOPT_RECV_TIMEOUT configures recv and recvfrom timeout in milliseconds.\n
+     *                  In that case optval should be pointer to unsigned long.\n
+     *               2. SOCKOPT_NONBLOCK (optname). sets the socket non-blocking mode on or off.\n
+     *                  In that case optval should be SOCK_ON or SOCK_OFF (optval).\n
+     *  \sa setsockopt
+     */
+    int32_t getsockopt (int32_t sd, int32_t level, int32_t optname, void *optval, socklen_t *optlen);
+    /**
+     *  \brief Read data from socket (simple_link_recv).
+     *      Return the length of the message on successful completion.\n
+     *      If a message is too long to fit in the supplied buffer, excess bytes may\n
+     *      be discarded depending on the type of socket the message is received from.\n
+     *
+     *  \param sd       socket handle
+     *  \param buf      read buffer
+     *  \param len      buffer length
+     *  \param flags    indicates blocking or non-blocking operation
+     *  \param from     pointer to an address structure indicating source address
+     *  \param fromlen  source address structure size
+     *  \return         Return the number of bytes received, or -1 if an error occurred
+     */
+    int32_t simple_link_recv(int32_t sd, void *buf, int32_t len, int32_t flags, sockaddr *from, socklen_t *fromlen, int32_t opcode);
+    /**
+     *  \brief Transmit a message to another socket (simple_link_send).
+     *  \param sd       socket handle
+     *  \param buf      write buffer
+     *  \param len      buffer length
+     *  \param flags    On this version, this parameter is not supported
+     *  \param to       pointer to an address structure indicating destination address
+     *  \param tolen    destination address structure size
+     *  \return         Return the number of bytes transmitted, or -1 if an error\n
+     *                  occurred, or -2 in case there are no free buffers available\n
+     *                  (only when SEND_NON_BLOCKING is enabled)\n
+     */
+    int32_t simple_link_send(int32_t sd, const void *buf, int32_t len, int32_t flags, const sockaddr *to, int32_t tolen, int32_t opcode);
+    /**
+     *  \brief Receive a message from a connection-mode socket.
+     *  \param[in]  sd     socket handle
+     *  \param[out] buf    Points to the buffer where the message should be stored
+     *  \param[in]  len    Specifies the length in bytes of the buffer pointed to \n
+     *                     by the buffer argument.\n
+     *  \param[in] flags   Specifies the type of message reception. \n
+     *                     On this version, this parameter is not supported.\n
+     *  \return         Return the number of bytes received, or -1 if an error occurred
+     *  \sa recvfrom
+     *  \Note On this version, only blocking mode is supported.
+     */
+    int32_t recv(int32_t sd, void *buf, int32_t len, int32_t flags);
+    /**
+     *  \brief read data from socket (recvfrom).
+     *      Receives a message from a connection-mode or connectionless-mode socket.\n
+     *      Note that raw sockets are not supported.\n
+     *
+     *  \param[in]  sd       socket handle
+     *  \param[out] buf      Points to the buffer where the message should be stored
+     *  \param[in]  len      Specifies the length in bytes of the buffer pointed to \n
+     *                       by the buffer argument.\n
+     *  \param[in] flags     Specifies the type of message reception.\n
+     *                       On this version, this parameter is not supported.\n
+     *  \param[in] from      pointer to an address structure indicating the source\n
+     *                       address: sockaddr. On this version only AF_INET is\n
+     *                       supported.\n
+     *  \param[in] fromlen   source address structure size
+     *  \return              Return the number of bytes received, or -1 if an error occurred
+     *  \sa recv
+     *  \Note On this version, only blocking mode is supported.
+     */
+    int32_t recvfrom(int32_t sd, void *buf, int32_t len, int32_t flags, sockaddr *from, socklen_t *fromlen);
+    /**
+     *  \brief Transmit a message to another socket (send).
+     *  \param sd       socket handle
+     *  \param buf      Points to a buffer containing the message to be sent
+     *  \param len      message size in bytes
+     *  \param flags    On this version, this parameter is not supported
+     *  \return         Return the number of bytes transmitted, or -1 if an\n
+     *                  error occurred\n
+     *  \Note           On this version, only blocking mode is supported.
+     *  \sa             sendto
+     */
+    int32_t send(int32_t sd, const void *buf, int32_t len, int32_t flags);
+    /**
+     *  \brief Transmit a message to another socket (sendto).
+     *  \param sd       socket handle
+     *  \param buf      Points to a buffer containing the message to be sent
+     *  \param len      message size in bytes
+     *  \param flags    On this version, this parameter is not supported
+     *  \param to       pointer to an address structure indicating the destination\n
+     *                  address: sockaddr. On this version only AF_INET is\n
+     *                  supported.\n
+     *  \param tolen    destination address structure size
+     *  \return         Return the number of bytes transmitted, or -1 if an error occurred
+     *  \Note           On this version, only blocking mode is supported.
+     *  \sa             send
+     */
+    int32_t sendto(int32_t sd, const void *buf, int32_t len, int32_t flags, const sockaddr *to, socklen_t tolen);
+    /**
+     *  \brief Set CC3000 in mDNS advertiser mode in order to advertise itself.
+     *  \param[in] mdns_enabled                 flag to enable/disable the mDNS feature
+     *  \param[in] device_service_name          Service name as part of the published\n
+     *                                          canonical domain name\n
+     *  \param[in] device_service_name_length   Length of the service name
+     *  \return   On success, zero is returned,\n
+     *            return SOC_ERROR if socket was not opened successfully, or if an error occurred.\n
+     */
+    int32_t mdns_advertiser(uint16_t mdns_enabled, uint8_t * device_service_name, uint16_t device_service_name_length);
+    /**
+     *  \brief
+     *  \param[in] s_addr in host format ( little endian )
+     *  \param[in] *buf     buffer to write too
+     *  \param[in] buflen   length of supplied buffer
+     *  \return    pointer to buf \n
+     */
+    char * inet_ntoa_r(uint32_t s_addr, char *buf, int buflen);
+#ifndef CC3000_TINY_DRIVER
+    /**
+     *  \brief Get host IP by name.\n
+     *      Obtain the IP Address of machine on network\n
+     *
+     *  \param[in]   hostname     host name
+     *  \param[in]   name_length  name length
+     *  \param[out]  out_ip_addr  This parameter is filled in with host IP address.\n
+     *                            In case that host name is not resolved, \n
+     *                            out_ip_addr is zero.\n
+     *  \return      On success, positive is returned.\n
+     *               On error, negative is returned by its name.\n
+     *  \note  On this version, only blocking mode is supported. Also note that\n
+     *         The function requires DNS server to be configured prior to its usage.\n
+     */
+    int32_t gethostbyname(uint8_t *hostname, uint16_t name_length, uint32_t *out_ip_addr);
+    /**
+     *  \brief set socket options.
+     *      This function manipulate the options associated with a socket.\n
+     *      Options may exist at multiple protocol levels; they are always\n
+     *      present at the uppermost socket level.\n
+     *      When manipulating socket options the level at which the option \n
+     *      resides and the name of the option must be specified.\n
+     *      To manipulate options at the socket level, level is specified as\n
+     *      SOL_SOCKET. To manipulate options at any other level the protocol \n
+     *      number of the appropriate protocol controlling the option is \n
+     *      supplied. For example, to indicate that an option is to be \n
+     *      interpreted by the TCP protocol, level should be set to the \n
+     *      protocol number of TCP; \n
+     *      The parameters optval and optlen are used to access optval - \n
+     *      use for setsockopt(). For getsockopt() they identify a buffer\n
+     *      in which the value for the requested option(s) are to \n
+     *      be returned. For getsockopt(), optlen is a value-result \n
+     *      parameter, initially containing the size of the buffer \n
+     *      pointed to by option_value, and modified on return to \n
+     *      indicate the actual size of the value returned. If no option \n
+     *      value is to be supplied or returned, option_value may be NULL.\n
+     *
+     *  \param[in]   sd          socket handle
+     *  \param[in]   level       defines the protocol level for this option
+     *  \param[in]   optname     defines the option name to Interrogate
+     *  \param[in]   optval      specifies a value for the option
+     *  \param[in]   optlen      specifies the length of the option value
+     *  \return      On success, zero is returned.\n
+     *               On error, -1 is returned\n
+     *
+     *  \Note   On this version the following two socket options are enabled:\n
+     *          The only protocol level supported in this version is SOL_SOCKET (level).\n
+     *               1. SOCKOPT_RECV_TIMEOUT (optname)\n
+     *                  SOCKOPT_RECV_TIMEOUT configures recv and recvfrom timeout in milliseconds.\n
+     *                  In that case optval should be pointer to unsigned long.\n
+     *               2. SOCKOPT_NONBLOCK (optname). sets the socket non-blocking mode on or off.\n
+     *                  In that case optval should be SOCK_ON or SOCK_OFF (optval).\n
+     *  \sa getsockopt
+     */
+    int32_t setsockopt(int32_t sd, int32_t level, int32_t optname, const void *optval, socklen_t optlen);
+#endif
+private:
+    cc3000_simple_link  &_simple_link;
+    cc3000_hci          &_hci;
+    cc3000_event        &_event;
+};
+
+/** SPI communication layer
+ */
+class cc3000_spi {
+public:
+    /**
+     *  \brief Ctor
+     *  \param irq         IRQ pin
+     *  \param cc3000_en   Enable pin
+     *  \param cc3000_cs   Chip select pin
+     *  \param cc3000_spi  SPI object
+     *  \param irq_port    Port for IRQ pin (needed for enable/disable interrupts)
+     *  \param event       Reference to the event object.
+     *  \param simple_link Reference to the simple link object.
+     *  \return none
+     */
+     cc3000_spi(PinName cc3000_irq, PinName cc3000_en, PinName cc3000_cs, SPI cc3000_spi, cc3000_event &event, cc3000_simple_link &simple_link);
+    /**
+     *  \brief Dtor
+     *  \param none
+     *  \return none
+     */
+     ~cc3000_spi();
+     /**
+      *  \brief Close SPI - disables IRQ and set received buffer to 0
+      *  \param none
+      *  \return none
+     */
+     void close();
+    /**
+     *  \brief Open the SPI interface
+     *  \param  none
+     *  \return none
+     */
+     void open();
+    /**
+     *  \brief First SPI write after powerup (delay needed between SPI header and body)
+     *  \param  buffer pointer to write buffer
+     *  \param  length buffer length
+     *  \return 0
+     */
+     uint32_t first_write(uint8_t *buffer, uint16_t length);
+    /**
+     *  \brief SPI Write function
+     *  \param  buffer pointer to write buffer
+     *  \param  length buffer length
+     *  \return 0
+     */
+     uint32_t write(uint8_t *buffer, uint16_t length);
+    /**
+     *  \brief Low level SPI write
+     *  \param  data pointer to data buffer
+     *  \param  size number of bytes
+     *  \return none
+     */
+     void write_synchronous(uint8_t *data, uint16_t size);
+    /**
+     *  \brief Low level SPI read
+     *  \param  data pointer to data buffer
+     *  \param  size number of bytes
+     *  \return none
+     */
+     void read_synchronous(uint8_t *data, uint16_t size);
+    /**
+     *  \brief Process the received SPI Header and in accordance with it - continue reading the packet
+     *  \param  None
+     *  \return 0
+     */
+     uint32_t read_data_cont();
+     /**
+     *  \brief Enable WLAN interrutp
+     *  \param  None
+     *  \return None
+     */
+    void wlan_irq_enable();
+     /**
+     *  \brief Disable WLAN interrutp
+     *  \param  None
+     *  \return None
+     */
+    void wlan_irq_disable();
+    /**
+     *  \brief Get WLAN interrupt status
+     *  \param   None
+     *  \return  0 : No interrupt occured
+     *           1 : Interrupt occured
+     */
+    uint32_t wlan_irq_read();
+    /**
+     *  \brief SPI interrupt Handler.
+     *      The external WLAN device asserts the IRQ line when data is ready.\n
+     *      The host CPU needs to acknowledges the IRQ by asserting CS.\n
+     *
+     *  \param  none
+     *  \return none
+     */
+    void WLAN_IRQHandler();
+    /**
+     *  \brief Enable/Disable the WLAN module
+     *  \param  value 1 : Enable
+     *                0 : Disable
+     *  \return None
+     */
+    void set_wlan_en(uint8_t value);
+private:
+    tSpiInfo            _spi_info;
+    InterruptIn         _wlan_irq;
+    DigitalOut          _wlan_en;
+    DigitalOut          _wlan_cs;
+    SPI                 _wlan_spi;
+    cc3000_event        &_event;
+    cc3000_simple_link  &_simple_link;
+    bool                _process_irq;
+};
+
+/** HCI layer
+ */
+class cc3000_hci {
+public:
+    /**
+     *  \brief Ctor
+     *  \param spi Reference to the spi object.
+     *  \return none
+     */
+    cc3000_hci(cc3000_spi &spi);
+    /**
+     *  \brief Dtor
+     *  \param none
+     *  \return none
+     */
+    ~cc3000_hci();
+    /**
+     *  \brief Initiate an HCI command.
+     *  \param op_code command operation code
+     *  \param buffer  pointer to the command's arguments buffer
+     *  \param length  length of the arguments
+     *  \return 0
+     */
+    uint16_t command_send(uint16_t op_code, uint8_t *buffer, uint8_t length);
+    /**
+     *  \brief Initiate an HCI data write operation
+     *  \param op_code     command operation code
+     *  \param args        pointer to the command's arguments buffer
+     *  \param arg_length  length of the arguments
+     *  \param data_length length od data
+     *  \param tail        pointer to the data buffer
+     *  \param tail_length buffer length
+     *  \return ESUCCESS
+     */
+    uint32_t data_send(uint8_t op_code, uint8_t *args, uint16_t arg_length,
+                        uint16_t data_length, const uint8_t *tail, uint16_t tail_length);
+    /**
+     *  \brief Prepare HCI header and initiate an HCI data write operation.
+     *  \param op_code     command operation code
+     *  \param buffer      pointer to the data buffer
+     *  \param arg_length  arguments length
+     *  \param data_length data length
+     *  \return none
+     */
+    void data_command_send(uint16_t op_code, uint8_t *buffer, uint8_t arg_length,
+                            uint16_t data_length);
+    /**
+     *  \brief Prepare HCI header and initiate an HCI patch write operation.
+     *  \param op_code     command operation code
+     *  \param buffer      pointer to the command's arguments buffer
+     *  \param patch       pointer to patch content buffer
+     *  \param data_length data length
+     *  \return none
+     */
+    void patch_send(uint8_t op_code, uint8_t *buffer, uint8_t *patch, uint16_t data_length);
+private:
+    cc3000_spi &_spi;
+};
+
+/** NVMEM layer
+ */
+class cc3000_nvmem {
+public:
+    /**
+     *  \brief Ctor
+     *  \param hci         Reference to the hci object.
+     *  \param event       Reference to the event object.
+     *  \param simple_link Reference to the simple link object.
+     *  \return none
+     */
+    cc3000_nvmem(cc3000_hci &hci, cc3000_event &event, cc3000_simple_link &simple_link);
+    /**
+     *  \brief Dtor
+     *  \param none
+     *  \return none
+     */
+    ~cc3000_nvmem();
+    /**
+     *  \brief Reads data from the file referred by the file_id parameter.
+     *      Reads data from file offset till length. Err if the file can't be used,
+     *      is invalid, or if the read is out of bounds.
+     *  \param file_id nvmem file id.
+     *  \param length  number of bytes to read.
+     *  \param offset  offset in file from where to read.
+     *  \param buff    output buffer pointer.
+     *  \return
+     *      Number of bytes read, otherwise error.
+     */
+    int32_t read(uint32_t file_id, uint32_t length, uint32_t offset, uint8_t *buff);
+    /**
+     *  \brief Write data to nvmem.
+     *  \param file_id      Nvmem file id
+     *  \param length       number of bytes to write
+     *  \param entry_offset offset in file to start write operation from
+     *  \param buff         data to write
+     *  \return
+     *      On success 0, error otherwise.
+     */
+    int32_t write(uint32_t file_id, uint32_t length, uint32_t entry_offset, uint8_t *buff);
+    /**
+     *  \brief Write MAC address to EEPROM.
+     *  \param mac Mac address to be set
+     *  \return
+     *      On success 0, error otherwise.
+     */
+    uint8_t set_mac_address(uint8_t *mac);
+    /**
+     *  \brief Read MAC address from EEPROM.
+     *  \param mac Mac address
+     *  \return
+     *      On success 0, error otherwise.
+     */
+    uint8_t get_mac_address(uint8_t *mac);
+    /**
+     *  \brief Program a patch to a specific file ID. The SP data is assumed to be organized in 2-dimensional.
+     *      Each line is SP_PORTION_SIZE bytes long.
+     *  \param file_id nvmem file id/
+     *  \param length  number of bytes to write
+     *  \param data    SP data to write
+     *  \return
+     *      On success 0, error otherwise.
+     */
+    uint8_t write_patch(uint32_t file_id, uint32_t length, const uint8_t *data);
+    /**
+     *  \brief Create new file entry and allocate space on the NVMEM. Applies only to user files.
+     *  \param file_id nvmem file Id
+     *  \param new_len entry ulLength
+     *  \return
+     */
+    int32_t create_entry(uint32_t file_id, uint32_t new_len);
+#ifndef CC3000_TINY_DRIVER
+    /**
+     *  \brief Read patch version. read package version (WiFi FW patch, river-supplicant-NS patch,
+     *      bootloader patch)
+     *  \param patch_ver First number indicates package ID and the second number indicates
+     *      package build number
+     *  \return
+     *      On success 0, error otherwise.
+     */
+    uint8_t read_sp_version(uint8_t* patch_ver);
+#endif
+private:
+    cc3000_hci          &_hci;
+    cc3000_event        &_event;
+    cc3000_simple_link  &_simple_link;
+};
+
+/** WLAN layer
+ */
+class cc3000_wlan {
+public:
+    /**
+     *  \brief Ctor
+     *  \param simple_link Reference to the simple link object.
+     *  \param event       Reference to the event object.
+     *  \param spi         Reference to the spi object.
+     *  \param hci         Reference to the hci object.
+     *  \return none
+     */
+    cc3000_wlan(cc3000_simple_link &simple_link, cc3000_event &event, cc3000_spi &spi, cc3000_hci &hci);
+    /**
+     *  \brief Dtor
+     *  \param none
+     *  \return none
+     */
+    ~cc3000_wlan();
+    /**
+     *  \brief Send SIMPLE LINK START to cc3000.
+     *  \param patches_available_host Flag to indicate if patches are available.
+     *  \return none
+     */
+    void simpleLink_init_start(uint16_t patches_available_host);
+    /**
+     *  \brief Start wlan device. Blocking call until init is completed.
+     *  \param patches_available_host Flag to indicate if patches are available.
+     *  \return none
+     */
+    void start(uint16_t patches_available_host);
+    /**
+     *  \brief Stop wlan device
+     *  \param none
+     *  \return none
+     */
+    void stop(void);
+#ifndef CC3000_TINY_DRIVER
+    /**
+     *  \brief Connect to AP.
+     *  \param sec_type    Security option.
+     *  \param ssid        up to 32 bytes, ASCII SSID
+     *  \param ssid_length length of SSID
+     *  \param b_ssid      6 bytes specified the AP bssid
+     *  \param key         up to 16 bytes specified the AP security key
+     *  \param key_len     key length
+     *  \return
+     *      On success, zero is returned. On error, negative is returned.
+     */
+    int32_t connect(uint32_t sec_type, const uint8_t *ssid, int32_t ssid_length, uint8_t *b_ssid, uint8_t *key, int32_t key_len);
+    /**
+     *  \brief Add profile. Up to 7 profiles are supported.
+     *  \param sec_type                      Security option.
+     *  \param ssid                          Up to 32 bytes, ASCII SSID
+     *  \param ssid_length                   Length of SSID
+     *  \param b_ssid                        6 bytes specified the AP bssid
+     *  \param priority                      Up to 16 bytes specified the AP security key
+     *  \param pairwise_cipher_or_tx_key_len Key length
+     *  \param group_cipher_tx_key_index     Key length for WEP security
+     *  \param key_mgmt                      KEY management
+     *  \param pf_or_key                     Security key
+     *  \param pass_phrase_length            Security key length for WPA\WPA2
+     *  \return
+     *      On success, zero is returned. On error, negative is returned.
+     */
+    int32_t add_profile(uint32_t sec_type, uint8_t* ssid, uint32_t ssid_length, uint8_t *b_ssid, uint32_t priority, uint32_t pairwise_cipher_or_tx_key_len, uint32_t group_cipher_tx_key_index,
+                          uint32_t key_mgmt, uint8_t* pf_or_key, uint32_t pass_phrase_length);
+    /**
+     *  \brief Gets entry from scan result table. The scan results are returned
+     *      one by one, and each entry represents a single AP found in the area.
+     *  \param scan_timeout Not supported yet
+     *  \param results      Scan result
+     *  \return
+     *      On success, zero is returned. On error, -1 is returned
+     */
+    int32_t ioctl_get_scan_results(uint32_t scan_timeout, uint8_t *results);
+    /**
+     *  \brief Start and stop scan procedure. Set scan parameters.
+     *  \param enable             Start/stop application scan
+     *  \param min_dwell_time     Minimum dwell time value to be used for each channel, in ms. (Default: 20)
+     *  \param max_dwell_time     Maximum dwell time value to be used for each channel, in ms. (Default: 30)
+     *  \param num_probe_requests Max probe request between dwell time. (Default:2)
+     *  \param channel_mask       Bitwise, up to 13 channels (0x1fff).
+     *  \param rssi_threshold     RSSI threshold. Saved: yes (Default: -80)
+     *  \param snr_threshold      NSR threshold. Saved: yes (Default: 0)
+     *  \param default_tx_power   probe Tx power. Saved: yes (Default: 205)
+     *  \param interval_list      Pointer to array with 16 entries (16 channels)
+     *  \return
+     *      On success, zero is returned. On error, -1 is returned.
+     */
+    int32_t ioctl_set_scan_params(uint32_t enable, uint32_t min_dwell_time, uint32_t max_dwell_time, uint32_t num_probe_requests,
+                                uint32_t channel_mask, int32_t rssi_threshold, uint32_t snr_threshold, uint32_t default_tx_power, uint32_t *interval_list);
+    /**
+     *  \brief Get wlan status: disconnected, scanning, connecting or connected
+     *  \param none
+     *  \return
+     *      WLAN_STATUS_DISCONNECTED, WLAN_STATUS_SCANING, STATUS_CONNECTING or WLAN_STATUS_CONNECTED
+     */
+    int32_t ioctl_statusget(void);
+#else
+    /**
+     *  \brief Connect to AP
+     *  \param ssid        Up to 32 bytes and is ASCII SSID of the AP
+     *  \param ssid_length Length of the SSID
+     *  \return
+     *      On success, zero is returned. On error, negative is returned.
+     */
+    int32_t connect(const uint8_t *ssid, int32_t ssid_length);
+    /**
+     *  \brief When auto start is enabled, the device connects to station from the profiles table.
+     *      If several profiles configured the device choose the highest priority profile.
+     *  \param sec_type                      WLAN_SEC_UNSEC,WLAN_SEC_WEP,WLAN_SEC_WPA,WLAN_SEC_WPA2
+     *  \param ssid                          SSID up to 32 bytes
+     *  \param ssid_length                   SSID length
+     *  \param b_ssid                        bssid 6 bytes
+     *  \param priority                      Profile priority. Lowest priority:0.
+     *  \param pairwise_cipher_or_tx_key_len Key length for WEP security
+     *  \param group_cipher_tx_key_index     Key index
+     *  \param key_mgmt                      KEY management
+     *  \param pf_or_key                     Security key
+     *  \param pass_phrase_length            Security key length for WPA\WPA2
+     *  \return
+     *      On success, zero is returned. On error, -1 is returned
+     */
+    int32_t add_profile(uint32_t sec_type, uint8_t *ssid, uint32_t ssid_length, uint8_t *b_ssid, uint32_t priority,
+                      uint32_t pairwise_cipher_or_tx_key_len, uint32_t group_cipher_tx_key_index, uint32_t key_mgmt,
+                      uint8_t* pf_or_key, uint32_t pass_phrase_length);
+#endif
+#ifndef CC3000_UNENCRYPTED_SMART_CONFIG
+    /**
+     *  \brief Process the acquired data and store it as a profile.
+     *  \param none
+     *  \return
+     *      On success, zero is returned. On error, -1 is returned.
+     */
+    int32_t smart_config_process(void);
+#endif
+    /**
+     *  \brief Disconnect connection from AP.
+     *  \param none
+     *  \return
+     *      0 if disconnected done, other CC3000 already disconnected.
+     */
+    int32_t disconnect();
+    /**
+     *  \brief When auto is enabled, the device tries to connect according the following policy:
+     *      1) If fast connect is enabled and last connection is valid, the device will try to
+     *      connect to it without the scanning procedure (fast). The last connection will be
+     *      marked as invalid, due to adding/removing profile.
+     *      2) If profile exists, the device will try to connect it (Up to seven profiles).
+     *      3) If fast and profiles are not found, and open mode is enabled, the device
+     *      will try to connect to any AP.
+     *      Note that the policy settings are stored in the CC3000 NVMEM.
+     *  \param should_connect_to_open_ap Enable(1), disable(0) connect to any available AP.
+     *  \param use_fast_connect          Enable(1), disable(0). if enabled, tries to
+     *                                   connect to the last connected AP.
+     *  \param use_profiles              Enable(1), disable(0) auto connect after reset.
+     *                                   and periodically reconnect if needed.
+     *  \return
+     *      On success, zero is returned. On error, -1 is returned
+     */
+    int32_t ioctl_set_connection_policy(uint32_t should_connect_to_open_ap, uint32_t use_fast_connect, uint32_t use_profiles);
+    /**
+     *  \brief Delete WLAN profile
+     *  \param index Number of profile to delete
+     *  \return
+     *      On success, zero is returned. On error, -1 is returned
+     */
+    int32_t ioctl_del_profile(uint32_t index);
+    /**
+     *  \brief Mask event according to bit mask. In case that event is
+     *      masked (1), the device will not send the masked event to host.
+     *  \param mask event mask
+     *  \return
+     *      On success, zero is returned. On error, -1 is returned
+     */
+    int32_t set_event_mask(uint32_t mask);
+    /**
+     *  \brief Start to acquire device profile. The device acquire its own
+     *      profile, if profile message is found.
+     *  \param encrypted_flag Indicates whether the information is encrypted
+     *  \return
+     *      On success, zero is returned. On error, -1 is returned.
+     */
+    int32_t smart_config_start(uint32_t encrypted_flag);
+    /**
+     *  \brief Stop the acquire profile procedure.
+     *  \param none
+     *  \return
+     *      On success, zero is returned. On error, -1 is returned
+     */
+    int32_t smart_config_stop(void);
+    /**
+     *  \brief Configure station ssid prefix.
+     *  \param new_prefix 3 bytes identify the SSID prefix for the Smart Config.
+     *  \return
+     *      On success, zero is returned. On error, -1 is returned.
+     */
+    int32_t smart_config_set_prefix(uint8_t *new_prefix);
+private:
+    cc3000_simple_link  &_simple_link;
+    cc3000_event        &_event;
+    cc3000_spi          &_spi;
+    cc3000_hci          &_hci;
+};
+
+/** The main object of cc3000 implementation
+ */
+class cc3000 {
+public:
+    /** status structure */
+    typedef struct {
+        uint8_t socket;
+        bool    dhcp;
+        bool    connected;
+        bool    smart_config_complete;
+        bool    stop_smart_config;
+        bool    dhcp_configured;
+        bool    ok_to_shut_down;
+        bool    enabled;
+    } tStatus;
+    /**
+     *  \brief Ctor.
+     *  \param cc3000_irq IRQ pin
+     *  \param cc3000_en  Enable pin
+     *  \param cc3000_cs  Chip select pin
+     *  \param cc3000_spi SPI interface
+     */
+    cc3000(PinName cc3000_irq, PinName cc3000_en, PinName cc3000_cs, SPI cc3000_spi);
+    /**
+     *  \brief Dtor.
+     */
+    ~cc3000();
+    /**
+     *  \brief Initiate cc3000. It starts the wlan communication.
+     *  \param patch Patch
+     */
+    void start(uint8_t patch);
+    /**
+     *  \brief Stops the wlan communication.
+     */
+    void stop();
+    /**
+     *  \brief Restarts the wlan communication.
+     */
+    void restart(uint8_t patch);
+    /**
+     *  \brief Callback which is called from the event class. This updates status of cc3000.
+     *  \param event_type Type of the event
+     *  \param data       Pointer to data
+     *  \param length     Length of data
+     *  \return none
+     */
+    void usync_callback(int32_t event_type, uint8_t *data, uint8_t length);
+    /**
+     *  \brief Start connection to SSID (open/secured) non-blocking
+     *  \param ssid          SSID name
+     *  \param key           Security key (if key = 0, open connection)
+     *  \param security_mode Security mode
+     *  \return true if connection was established, false otherwise.
+     */
+    bool connect_non_blocking(const uint8_t *ssid, const uint8_t *key, int32_t security_mode);
+    /**
+     *  \brief Connect to SSID (open/secured) with timeout (10s).
+     *  \param ssid          SSID name
+     *  \param key           Security key (if key = 0, open connection)
+     *  \param security_mode Security mode
+     *  \return true if connection was established, false otherwise.
+     */
+    bool connect_to_AP(const uint8_t *ssid, const uint8_t *key, int32_t security_mode);
+    /**
+     *  \brief Connect to SSID which is secured
+     *  \param ssid          SSID name
+     *  \param key           Security key
+     *  \param security_mode Security mode
+     *  \return true if connection was established, false otherwise.
+     */
+    bool connect_secure(const uint8_t *ssid, const uint8_t *key, int32_t security_mode);
+    /**
+     *  \brief Connect to SSID which is open (no security)
+     *  \param ssid          SSID name
+     *  \return true if connection was established, false otherwise.
+     */
+    bool connect_open(const uint8_t *ssid);
+    /**
+     *  \brief Status of the cc3000 module.
+     *  \return true if it's enabled, false otherwise.
+     */
+    bool is_enabled();
+    /**
+     *  \brief Status of the cc3000 connection.
+     *  \return true if it's connected, false otherwise.
+     */
+    bool is_connected();
+    /**
+     *  \brief Status of DHCP.
+     *  \param none
+     *  \return true if DCHP is configured, false otherwise.
+     */
+    bool is_dhcp_configured();
+    /**
+     *  \brief Status of smart confing completation.
+     *  \param none
+     *  \return smart config was set, false otherwise.
+     */
+    bool is_smart_confing_completed();
+    /**
+     *  \brief Return the cc3000's mac address.
+     *  \param address Retreived mac address.
+     *  \return
+     */
+    uint8_t get_mac_address(uint8_t address[6]);
+    /**
+     *  \brief Set the cc3000's mac address.
+     *  \param address Mac address to be set.
+     *  \return
+     */
+    uint8_t set_mac_address(uint8_t address[6]);
+    /**
+     *  \brief Get user file info.
+     *  \param  info_file Pointer where info will be stored.
+     *  \param  size      Available size.
+     *  \return none
+     */
+    void get_user_file_info(uint8_t *info_file, size_t size);
+    /**
+     *  \brief Set user filo info.
+     *  \param info_file Pointer to user's info.
+     *  \return none
+     */
+    void set_user_file_info(uint8_t *info_file, size_t size);
+    /**
+     *  \brief Start smart config.
+     *  \param smart_config_key Pointer to smart config key.
+     *  \return none
+     */
+    void start_smart_config(const uint8_t *smart_config_key);  /* TODO enable AES ? */
+#ifndef CC3000_TINY_DRIVER
+    /**
+     *  \brief Return ip configuration.
+     *  \param ip_config Pointer to ipconfig data.
+     *  \return true if it's connected and info was retrieved, false otherwise.
+     */
+    bool get_ip_config(tNetappIpconfigRetArgs *ip_config);
+#endif
+    /**
+     *  \brief Delete all stored profiles.
+     *  \param none
+     *  \return none
+     */
+    void delete_profiles(void);
+    /**
+     *  \brief Ping an ip address.
+     *  \param ip       Destination IP address
+     *  \param attempts Number of attempts
+     *  \param timeout  Time to wait for a response,in milliseconds.
+     *  \param size     Send buffer size which may be up to 1400 bytes
+     */
+    uint32_t ping(uint32_t ip, uint8_t attempts, uint16_t timeout, uint8_t size);
+    /**
+     *  \brief Returns cc3000 instance. Used in Socket interface.
+     *  \param none
+     *  \return Pointer to cc3000 object
+     */
+    static cc3000* get_instance() {
+        return _inst;
+    }
+#if (CC3000_ETH_COMPAT == 1)
+    /**
+     *  \brief Ctor for EthernetInterface
+     *  \param cc3000_irq   IRQ pin
+     *  \param cc3000_en    Enable pin
+     *  \param cc3000_cs    Chip select pin
+     *  \param cc3000_spi   SPI interface
+     *  \param ssid         SSID
+     *  \param phrase       Password
+     *  \param sec          Security of the AP
+     *  \param smart_config Smart config selection
+     */
+    cc3000(PinName cc3000_irq, PinName cc3000_en, PinName cc3000_cs, SPI cc3000_spi, const char *ssid, const char *phrase, Security sec, bool smart_config);
+    /**
+     *  \brief Disconnect wlan device.
+     *  \param none
+     *  \return 0 if successful, -1 otherwise.
+     */
+    int disconnect();
+    /**
+     *  \brief Initialize the interface with DHCP.
+     *  \param none
+     *  \return none
+     */
+    void init();
+    /**
+     *  \brief Initialize the interface with a static IP address.
+     *  \param ip      the IP address to use.
+     *  \param mask    the IP address mask
+     *  \param gateway the gateway to use
+     *  \return none
+     */
+    void init(const char *ip, const char *mask, const char *gateway);
+    /**
+     *  \brief Connect Bring the interface up.
+     *  \param timeout_ms timeout in ms
+     *  \return 0 if successful, -1 otherwise.
+     */
+    int connect(unsigned int timeout_ms = 20000);
+    /**
+     *  \brief Get the MAC address of your Ethernet interface.
+     *  \param none
+     *  \return
+     *      Pointer to a string containing the MAC address.
+     */
+    char* getMACAddress();
+     /**
+     *  \brief Get the IP address of your Ethernet interface.
+     *  \param none
+     *  \return
+     *      Pointer to a string containing the IP address.
+     */
+    char* getIPAddress();
+     /**
+     *  \brief Get the Gateway address of your Ethernet interface
+     *  \param none
+     *  \return
+     *      Pointer to a string containing the Gateway address
+     */
+    char* getGateway();
+     /**
+     *  \brief Get the Network mask of your Ethernet interface
+     *  \param none
+     *  \return
+     *      Pointer to a string containing the Network mask
+     */
+    char* getNetworkMask();
+#endif
+public:
+    cc3000_simple_link  _simple_link;
+    cc3000_event        _event;
+    cc3000_socket       _socket;
+    cc3000_spi          _spi;
+    cc3000_hci          _hci;
+    cc3000_nvmem        _nvmem;
+    cc3000_netapp       _netapp;
+    cc3000_wlan         _wlan;
+#ifndef CC3000_UNENCRYPTED_SMART_CONFIG
+    cc3000_security     _security;
+#endif
+protected:
+    static cc3000       *_inst;
+private:
+    tStatus                  _status;
+    netapp_pingreport_args_t _ping_report;
+    bool                     _closed_sockets[MAX_SOCKETS];
+#if (CC3000_ETH_COMPAT == 1)
+    uint8_t                  _phrase[30];
+    uint8_t                  _ssid[30];
+    Security                 _sec;
+    bool                     _smart_config;
+#endif
+};
+
+/**
+ * Copy 32 bit to stream while converting to little endian format.
+ * @param  p       pointer to the new stream
+ * @param  u32     pointer to the 32 bit
+ * @return         pointer to the new stream
+ */
+uint8_t *UINT32_TO_STREAM_f (uint8_t *p, uint32_t u32);
+
+/**
+ * Copy 16 bit to stream while converting to little endian format.
+ * @param  p       pointer to the new stream
+ * @param  u32     pointer to the 16 bit
+ * @return         pointer to the new stream
+ */
+uint8_t *UINT16_TO_STREAM_f (uint8_t *p, uint16_t u16);
+
+/**
+ * Copy received stream to 16 bit in little endian format.
+ * @param  p          pointer to the stream
+ * @param  offset     offset in the stream
+ * @return            pointer to the new 16 bit
+ */
+uint16_t STREAM_TO_UINT16_f(uint8_t* p, uint16_t offset);
+
+/**
+ * Copy received stream to 32 bit in little endian format.
+ * @param  p          pointer to the stream
+ * @param  offset     offset in the stream
+ * @return            pointer to the new 32 bit
+ */
+uint32_t STREAM_TO_UINT32_f(uint8_t* p, uint16_t offset);
+
+} /* end of mbed_cc3000 namespace */
+
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/cc3000_common.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,199 @@
+/*****************************************************************************
+*
+*  C++ interface/implementation created by Martin Kojtal (0xc0170). Thanks to
+*  Jim Carver and Frank Vannieuwkerke for their inital cc3000 mbed port and
+*  provided help.
+*
+*  This version of "host driver" uses CC3000 Host Driver Implementation. Thus
+*  read the following copyright:
+*
+*  Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*****************************************************************************/
+#ifndef CC3000_COMMON_H
+#define CC3000_COMMON_H
+
+#include <errno.h>
+
+//#define CC3000_TINY_DRIVER                // Driver for small memory model CPUs
+
+#define ESUCCESS        0
+#define EFAIL          -1
+#define EERROR          EFAIL
+
+#define CC3000_UNENCRYPTED_SMART_CONFIG   // No encryption
+
+#define ERROR_SOCKET_INACTIVE   -57
+
+#define HCI_CC_PAYLOAD_LEN      5
+
+#define WLAN_ENABLE            (1)
+#define WLAN_DISABLE           (0)
+
+#define MAC_ADDR_LEN           (6)
+
+
+/*Defines for minimal and maximal RX buffer size. This size includes the spi
+  header and hci header.
+  maximal buffer size: MTU + HCI header + SPI header + sendto() args size
+  minimum buffer size: HCI header + SPI header + max args size
+
+  This buffer is used for receiving events and data.
+  The packet can not be longer than MTU size and CC3000 does not support
+  fragmentation. Note that the same buffer is used for reception of the data
+  and events from CC3000. That is why the minimum is defined.
+  The calculation for the actual size of buffer for reception is:
+  Given the maximal data size MAX_DATA that is expected to be received by
+  application, the required buffer Using recv() or recvfrom():
+
+    max(CC3000_MINIMAL_RX_SIZE, MAX_DATA + HEADERS_SIZE_DATA + fromlen + ucArgsize + 1)
+
+  Using gethostbyname() with minimal buffer size will limit the host name returned to 99 bytes.
+  The 1 is used for the overrun detection
+*/
+
+#define CC3000_MINIMAL_RX_SIZE      (118 + 1)
+#define CC3000_MAXIMAL_RX_SIZE      (511 + 1)
+
+/*Defines for minimal and maximal TX buffer size.
+  This buffer is used for sending events and data.
+  The packet can not be longer than MTU size and CC3000 does not support
+  fragmentation. Note that the same buffer is used for transmission of the data
+  and commands. That is why the minimum is defined.
+  The calculation for the actual size of buffer for transmission is:
+  Given the maximal data size MAX_DATA, the required buffer is:
+  Using Sendto():
+
+   max(CC3000_MINIMAL_TX_SIZE, MAX_DATA + SPI_HEADER_SIZE
+   + SOCKET_SENDTO_PARAMS_LEN + SIMPLE_LINK_HCI_DATA_HEADER_SIZE + 1)
+
+  Using Send():
+
+   max(CC3000_MINIMAL_TX_SIZE, MAX_DATA + SPI_HEADER_SIZE
+   + HCI_CMND_SEND_ARG_LENGTH + SIMPLE_LINK_HCI_DATA_HEADER_SIZE + 1)
+
+  The 1 is used for the overrun detection */
+
+#define CC3000_MINIMAL_TX_SIZE      (118 + 1)
+#define CC3000_MAXIMAL_TX_SIZE      (1519 + 1)
+
+//TX and RX buffer size - allow to receive and transmit maximum data at lengh 8.
+#ifdef CC3000_TINY_DRIVER
+#define TINY_CC3000_MAXIMAL_RX_SIZE 44
+#define TINY_CC3000_MAXIMAL_TX_SIZE 59
+#endif
+
+/*In order to determine your preferred buffer size,
+  change CC3000_MAXIMAL_RX_SIZE and CC3000_MAXIMAL_TX_SIZE to a value between
+  the minimal and maximal specified above.
+  Note that the buffers are allocated by SPI.
+*/
+
+#ifndef CC3000_TINY_DRIVER
+
+    #define CC3000_RX_BUFFER_SIZE   (CC3000_MAXIMAL_RX_SIZE)
+    #define CC3000_TX_BUFFER_SIZE   (CC3000_MAXIMAL_TX_SIZE)
+    #define SP_PORTION_SIZE         512
+
+//TINY DRIVER: We use smaller rx and tx buffers in order to minimize RAM consumption
+#else
+    #define CC3000_RX_BUFFER_SIZE   (TINY_CC3000_MAXIMAL_RX_SIZE)
+    #define CC3000_TX_BUFFER_SIZE   (TINY_CC3000_MAXIMAL_TX_SIZE)
+    #define SP_PORTION_SIZE         32
+#endif
+
+
+//Copy 8 bit to stream while converting to little endian format.
+#define UINT8_TO_STREAM(_p, _val)    {*(_p)++ = (_val);}
+//Copy 16 bit to stream while converting to little endian format.
+#define UINT16_TO_STREAM(_p, _u16)    (UINT16_TO_STREAM_f(_p, _u16))
+//Copy 32 bit to stream while converting to little endian format.
+#define UINT32_TO_STREAM(_p, _u32)    (UINT32_TO_STREAM_f(_p, _u32))
+//Copy a specified value length bits (l) to stream while converting to little endian format.
+#define ARRAY_TO_STREAM(p, a, l)     {uint32_t _i; for (_i = 0; _i < l; _i++) *(p)++ = ((uint8_t *) a)[_i];}
+//Copy received stream to 8 bit in little endian format.
+#define STREAM_TO_UINT8(_p, _offset, _u8)    {_u8 = (uint8_t)(*(_p + _offset));}
+//Copy received stream to 16 bit in little endian format.
+#define STREAM_TO_UINT16(_p, _offset, _u16)    {_u16 = STREAM_TO_UINT16_f(_p, _offset);}
+//Copy received stream to 32 bit in little endian format.
+#define STREAM_TO_UINT32(_p, _offset, _u32)    {_u32 = STREAM_TO_UINT32_f(_p, _offset);}
+#define STREAM_TO_STREAM(p, a, l)     {uint32_t _i; for (_i = 0; _i < l; _i++) *(a)++= ((uint8_t *) p)[_i];}
+
+typedef struct _sockaddr_t
+{
+    uint16_t  family;
+    uint8_t   data[14];
+} sockaddr;
+
+struct timeval
+{
+    int32_t tv_sec;       /* seconds */
+    int32_t tv_usec;      /* microseconds */
+};
+
+#define SMART_CONFIG_PROFILE_SIZE        67        // 67 = 32 (max ssid) + 32 (max key) + 1 (SSID length) + 1 (security type) + 1 (key length)
+
+/* patches type */
+#define PATCHES_HOST_TYPE_WLAN_DRIVER   0x01
+#define PATCHES_HOST_TYPE_WLAN_FW       0x02
+#define PATCHES_HOST_TYPE_BOOTLOADER    0x03
+
+#define SL_SET_SCAN_PARAMS_INTERVAL_LIST_SIZE    (16)
+#define SL_SIMPLE_CONFIG_PREFIX_LENGTH           (3)
+#define ETH_ALEN                                 (6)
+#define MAXIMAL_SSID_LENGTH                      (32)
+
+#define SL_PATCHES_REQUEST_DEFAULT               (0)
+#define SL_PATCHES_REQUEST_FORCE_HOST            (1)
+#define SL_PATCHES_REQUEST_FORCE_NONE            (2)
+
+
+#define      WLAN_SEC_UNSEC  (0)
+#define      WLAN_SEC_WEP    (1)
+#define      WLAN_SEC_WPA    (2)
+#define      WLAN_SEC_WPA2   (3)
+
+
+#define WLAN_SL_INIT_START_PARAMS_LEN           (1)
+#define WLAN_PATCH_PARAMS_LENGTH                (8)
+#define WLAN_SET_CONNECTION_POLICY_PARAMS_LEN   (12)
+#define WLAN_DEL_PROFILE_PARAMS_LEN             (4)
+#define WLAN_SET_MASK_PARAMS_LEN                (4)
+#define WLAN_SET_SCAN_PARAMS_LEN                (100)
+#define WLAN_GET_SCAN_RESULTS_PARAMS_LEN        (4)
+#define WLAN_ADD_PROFILE_NOSEC_PARAM_LEN        (24)
+#define WLAN_ADD_PROFILE_WEP_PARAM_LEN          (36)
+#define WLAN_ADD_PROFILE_WPA_PARAM_LEN          (44)
+#define WLAN_CONNECT_PARAM_LEN                  (29)
+#define WLAN_SMART_CONFIG_START_PARAMS_LEN      (4)
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/cc3000_event.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,648 @@
+/*****************************************************************************
+*
+*  C++ interface/implementation created by Martin Kojtal (0xc0170). Thanks to
+*  Jim Carver and Frank Vannieuwkerke for their inital cc3000 mbed port and
+*  provided help.
+*
+*  This version of "host driver" uses CC3000 Host Driver Implementation. Thus
+*  read the following copyright:
+*
+*  Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*****************************************************************************/
+#include "cc3000.h"
+#include "cc3000_event.h"
+#include "cc3000_netapp.h"
+
+namespace mbed_cc3000 {
+
+#if (CC3000_DEBUG_HCI_RX == 1)
+const char *HCI_EVENT_STR[] =
+{
+    "Socket",
+    "Bind",
+    "Send",
+    "Recv",
+    "Accept",
+    "Listen",
+    "Connect",
+    "BSD Select",
+    "Set Socket Options",
+    "Get Socket Options",
+    "Close Socket",
+    "Unknown",
+    "Recv From",
+    "Write",
+    "Send To",
+    "Get Hostname",
+    "mDNS Advertise"
+};
+
+const char *HCI_NETAPP_STR[] =
+{
+    "DHCP",
+    "Ping Sent",
+    "Ping Report",
+    "Ping Stop",
+    "IP Config",
+    "ARP Flush",
+    "Unknown",
+    "Set Debug level",
+    "Set Timers"
+};
+
+// from 0-7
+const char *HCI_MISC_STR[] =
+{
+    "BASE - Error?",
+    "Connecting",
+    "Disconnect",
+    "Scan Param",
+    "Connect Policy",
+    "Add Profile",
+    "Del Profile",
+    "Get Scan Res",
+    "Event Mask",
+    "Status Req",
+    "Config Start",
+    "Config Stop",
+    "Config Set Prefix",
+    "Config Patch",
+};
+#endif
+
+cc3000_event::cc3000_event(cc3000_simple_link &simplelink, cc3000_hci &hci, cc3000_spi &spi, cc3000 &cc3000)
+    : socket_active_status(SOCKET_STATUS_INIT_VAL), _simple_link(simplelink), _hci(hci), _spi(spi), _cc3000(cc3000) {
+
+}
+
+cc3000_event::~cc3000_event() {
+
+}
+
+/* TODO removed buffer, set it in init */
+void cc3000_event::received_handler(uint8_t *buffer) {
+    _simple_link.set_data_received_flag(1);
+    _simple_link.set_received_data(buffer);
+
+    hci_unsolicited_event_handler();
+}
+
+void cc3000_event::hci_unsol_handle_patch_request(uint8_t *event_hdr) {
+    uint8_t *params = (uint8_t *)(event_hdr) + HCI_EVENT_HEADER_SIZE;
+    uint32_t length = 0;
+    uint8_t *patch;
+
+    switch (*params)
+    {
+        case HCI_EVENT_PATCHES_DRV_REQ:
+        {
+            tDriverPatches func_pointer = (tDriverPatches)_simple_link.get_func_pointer(DRIVER_PATCHES);
+            if (func_pointer)
+            {
+                patch = func_pointer(&length);
+                if (patch)
+                {
+                    _hci.patch_send(HCI_EVENT_PATCHES_DRV_REQ, _simple_link.get_transmit_buffer(), patch, length);
+                    return;
+                }
+            }
+
+            // Send 0 length Patches response event
+            _hci.patch_send(HCI_EVENT_PATCHES_DRV_REQ, _simple_link.get_transmit_buffer(), 0, 0);
+            break;
+        }
+        case HCI_EVENT_PATCHES_FW_REQ:
+        {
+            tFWPatches func_pointer = (tFWPatches)_simple_link.get_func_pointer(FW_PATCHES);
+            if (func_pointer)
+            {
+                patch = func_pointer(&length);
+                // Build and send a patch
+                if (patch)
+                {
+                    _hci.patch_send(HCI_EVENT_PATCHES_FW_REQ, _simple_link.get_transmit_buffer(), patch, length);
+                    return;
+                }
+            }
+            // Send 0 length Patches response event
+            _hci.patch_send(HCI_EVENT_PATCHES_FW_REQ, _simple_link.get_transmit_buffer(), 0, 0);
+            break;
+        }
+        case HCI_EVENT_PATCHES_BOOTLOAD_REQ:
+        {
+            tBootLoaderPatches func_pointer = (tBootLoaderPatches)_simple_link.get_func_pointer(BOOTLOADER_PATCHES);
+            if (func_pointer)
+            {
+                patch = func_pointer(&length);
+                if (patch)
+                {
+                    _hci.patch_send(HCI_EVENT_PATCHES_BOOTLOAD_REQ, _simple_link.get_transmit_buffer(), patch, length);
+                    return;
+                }
+            }
+            // Send 0 length Patches response event
+            _hci.patch_send(HCI_EVENT_PATCHES_BOOTLOAD_REQ, _simple_link.get_transmit_buffer(), 0, 0);
+            break;
+        }
+    }
+}
+
+static void hci_event_debug_print(uint16_t hciEventNo)
+{
+#if (CC3000_DEBUG_HCI_RX == 1)
+    if ((hciEventNo > HCI_CMND_SOCKET_BASE) && ( hciEventNo <= HCI_CMND_MDNS_ADVERTISE))
+    {
+        DBG_HCI("Event Received : 0x%04X - %s", hciEventNo, HCI_EVENT_STR[hciEventNo-HCI_CMND_SOCKET]);
+    }
+    else if ((hciEventNo > HCI_CMND_NETAPP_BASE) && ( hciEventNo <= HCI_NETAPP_SET_TIMERS))
+    {
+        DBG_HCI("Event Received : 0x%04X - %s", hciEventNo, HCI_NETAPP_STR[hciEventNo-HCI_NETAPP_DHCP]);
+    }
+    else if (hciEventNo < HCI_CMND_WLAN_CONFIGURE_PATCH+1)
+    {
+        DBG_HCI("Event Received : 0x%04X - %s", hciEventNo, HCI_MISC_STR[hciEventNo]);
+    }
+    else
+    {
+        DBG_HCI("Event Received : 0x%04X", hciEventNo);
+    }
+#endif
+}
+
+uint8_t *cc3000_event::hci_event_handler(void *ret_param, uint8_t *from, uint8_t *fromlen) {
+    uint8_t *received_data, argument_size;
+    uint16_t length;
+    uint8_t *pucReceivedParams;
+    uint16_t received_op_code = 0;
+    uint32_t return_value;
+    uint8_t * RecvParams;
+    uint8_t *RetParams;
+
+    while (1)
+    {
+        if (_simple_link.get_data_received_flag() != 0)
+        {
+            received_data = _simple_link.get_received_data();
+            if (*received_data == HCI_TYPE_EVNT)
+            {
+                // Event Received
+                STREAM_TO_UINT16((uint8_t *)received_data, HCI_EVENT_OPCODE_OFFSET,received_op_code);
+                pucReceivedParams = received_data + HCI_EVENT_HEADER_SIZE;
+                RecvParams = pucReceivedParams;
+                RetParams = (uint8_t *)ret_param;
+
+                // unsolicited event received - finish handling
+                if (hci_unsol_event_handler((uint8_t *)received_data) == 0)
+                {
+                    STREAM_TO_UINT8(received_data, HCI_DATA_LENGTH_OFFSET, length);
+
+                    hci_event_debug_print( received_op_code );
+
+                    switch(received_op_code)
+                    {
+                    case HCI_CMND_READ_BUFFER_SIZE:
+                        {
+                            uint16_t temp = _simple_link.get_number_free_buffers();
+                            STREAM_TO_UINT8((uint8_t *)pucReceivedParams, 0, temp);
+                            _simple_link.set_number_free_buffers(temp);
+
+                            temp = _simple_link.get_buffer_length();
+                            STREAM_TO_UINT16((uint8_t *)pucReceivedParams, 1, temp);
+                            _simple_link.set_buffer_length(temp);
+                        }
+                        break;
+
+                    case HCI_CMND_WLAN_CONFIGURE_PATCH:
+                    case HCI_NETAPP_DHCP:
+                    case HCI_NETAPP_PING_SEND:
+                    case HCI_NETAPP_PING_STOP:
+                    case HCI_NETAPP_ARP_FLUSH:
+                    case HCI_NETAPP_SET_DEBUG_LEVEL:
+                    case HCI_NETAPP_SET_TIMERS:
+                    case HCI_EVNT_NVMEM_READ:
+                    case HCI_EVNT_NVMEM_CREATE_ENTRY:
+                    case HCI_CMND_NVMEM_WRITE_PATCH:
+                    case HCI_NETAPP_PING_REPORT:
+                    case HCI_EVNT_MDNS_ADVERTISE:
+
+                        STREAM_TO_UINT8(received_data, HCI_EVENT_STATUS_OFFSET, *(uint8_t *)ret_param);
+                        break;
+
+                    case HCI_CMND_SETSOCKOPT:
+                    case HCI_CMND_WLAN_CONNECT:
+                    case HCI_CMND_WLAN_IOCTL_STATUSGET:
+                    case HCI_EVNT_WLAN_IOCTL_ADD_PROFILE:
+                    case HCI_CMND_WLAN_IOCTL_DEL_PROFILE:
+                    case HCI_CMND_WLAN_IOCTL_SET_CONNECTION_POLICY:
+                    case HCI_CMND_WLAN_IOCTL_SET_SCANPARAM:
+                    case HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_START:
+                    case HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_STOP:
+                    case HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_SET_PREFIX:
+                    case HCI_CMND_EVENT_MASK:
+                    case HCI_EVNT_WLAN_DISCONNECT:
+                    case HCI_EVNT_SOCKET:
+                    case HCI_EVNT_BIND:
+                    case HCI_CMND_LISTEN:
+                    case HCI_EVNT_CLOSE_SOCKET:
+                    case HCI_EVNT_CONNECT:
+                    case HCI_EVNT_NVMEM_WRITE:
+
+                        STREAM_TO_UINT32((uint8_t *)pucReceivedParams,0, *(uint32_t *)ret_param);
+                        break;
+
+                    case HCI_EVNT_READ_SP_VERSION:
+
+                        STREAM_TO_UINT8(received_data, HCI_EVENT_STATUS_OFFSET, *(uint8_t *)ret_param);
+                        ret_param = ((uint8_t *)ret_param) + 1;
+                        STREAM_TO_UINT32((uint8_t *)pucReceivedParams, 0, return_value);
+                        UINT32_TO_STREAM((uint8_t *)ret_param, return_value);
+                        break;
+
+                    case HCI_EVNT_BSD_GETHOSTBYNAME:
+
+                        STREAM_TO_UINT32((uint8_t *)pucReceivedParams,GET_HOST_BY_NAME_RETVAL_OFFSET,*(uint32_t *)ret_param);
+                        ret_param = ((uint8_t *)ret_param) + 4;
+                        STREAM_TO_UINT32((uint8_t *)pucReceivedParams,GET_HOST_BY_NAME_ADDR_OFFSET,*(uint32_t *)ret_param);
+                        break;
+
+                    case HCI_EVNT_ACCEPT:
+                        {
+                            STREAM_TO_UINT32((uint8_t *)pucReceivedParams,ACCEPT_SD_OFFSET,*(uint32_t *)ret_param);
+                            ret_param = ((uint8_t *)ret_param) + 4;
+                            STREAM_TO_UINT32((uint8_t *)pucReceivedParams,ACCEPT_RETURN_STATUS_OFFSET,*(uint32_t *)ret_param);
+                            ret_param = ((uint8_t *)ret_param) + 4;
+
+                            //This argument returns in network order
+                            memcpy((uint8_t *)ret_param, pucReceivedParams + ACCEPT_ADDRESS__OFFSET, sizeof(sockaddr));
+                            break;
+                        }
+
+                    case HCI_EVNT_RECV:
+                    case HCI_EVNT_RECVFROM:
+                        {
+                            STREAM_TO_UINT32((uint8_t *)pucReceivedParams,SL_RECEIVE_SD_OFFSET ,*(uint32_t *)ret_param);
+                            ret_param = ((uint8_t *)ret_param) + 4;
+                            STREAM_TO_UINT32((uint8_t *)pucReceivedParams,SL_RECEIVE_NUM_BYTES_OFFSET,*(uint32_t *)ret_param);
+                            ret_param = ((uint8_t *)ret_param) + 4;
+                            STREAM_TO_UINT32((uint8_t *)pucReceivedParams,SL_RECEIVE__FLAGS__OFFSET,*(uint32_t *)ret_param);
+
+                            if(((tBsdReadReturnParams *)ret_param)->iNumberOfBytes == ERROR_SOCKET_INACTIVE)
+                            {
+                                set_socket_active_status(((tBsdReadReturnParams *)ret_param)->iSocketDescriptor,SOCKET_STATUS_INACTIVE);
+                            }
+                            break;
+                        }
+
+                    case HCI_EVNT_SEND:
+                    case HCI_EVNT_SENDTO:
+                        {
+                            STREAM_TO_UINT32((uint8_t *)pucReceivedParams,SL_RECEIVE_SD_OFFSET ,*(uint32_t *)ret_param);
+                            ret_param = ((uint8_t *)ret_param) + 4;
+                            STREAM_TO_UINT32((uint8_t *)pucReceivedParams,SL_RECEIVE_NUM_BYTES_OFFSET,*(uint32_t *)ret_param);
+                            ret_param = ((uint8_t *)ret_param) + 4;
+
+                            break;
+                        }
+
+                    case HCI_EVNT_SELECT:
+                        {
+                            STREAM_TO_UINT32((uint8_t *)pucReceivedParams,SELECT_STATUS_OFFSET,*(uint32_t *)ret_param);
+                            ret_param = ((uint8_t *)ret_param) + 4;
+                            STREAM_TO_UINT32((uint8_t *)pucReceivedParams,SELECT_READFD_OFFSET,*(uint32_t *)ret_param);
+                            ret_param = ((uint8_t *)ret_param) + 4;
+                            STREAM_TO_UINT32((uint8_t *)pucReceivedParams,SELECT_WRITEFD_OFFSET,*(uint32_t *)ret_param);
+                            ret_param = ((uint8_t *)ret_param) + 4;
+                            STREAM_TO_UINT32((uint8_t *)pucReceivedParams,SELECT_EXFD_OFFSET,*(uint32_t *)ret_param);
+                            break;
+                        }
+
+                    case HCI_CMND_GETSOCKOPT:
+
+                        STREAM_TO_UINT8(received_data, HCI_EVENT_STATUS_OFFSET,((tBsdGetSockOptReturnParams *)ret_param)->iStatus);
+                        //This argument returns in network order
+                        memcpy((uint8_t *)ret_param, pucReceivedParams, 4);
+                        break;
+
+                    case HCI_CMND_WLAN_IOCTL_GET_SCAN_RESULTS:
+
+                        STREAM_TO_UINT32((uint8_t *)pucReceivedParams,GET_SCAN_RESULTS_TABlE_COUNT_OFFSET,*(uint32_t *)ret_param);
+                        ret_param = ((uint8_t *)ret_param) + 4;
+                        STREAM_TO_UINT32((uint8_t *)pucReceivedParams,GET_SCAN_RESULTS_SCANRESULT_STATUS_OFFSET,*(uint32_t *)ret_param);
+                        ret_param = ((uint8_t *)ret_param) + 4;
+                        STREAM_TO_UINT16((uint8_t *)pucReceivedParams,GET_SCAN_RESULTS_ISVALID_TO_SSIDLEN_OFFSET,*(uint32_t *)ret_param);
+                        ret_param = ((uint8_t *)ret_param) + 2;
+                        STREAM_TO_UINT16((uint8_t *)pucReceivedParams,GET_SCAN_RESULTS_FRAME_TIME_OFFSET,*(uint32_t *)ret_param);
+                        ret_param = ((uint8_t *)ret_param) + 2;
+                        memcpy((uint8_t *)ret_param, (uint8_t *)(pucReceivedParams + GET_SCAN_RESULTS_FRAME_TIME_OFFSET + 2), GET_SCAN_RESULTS_SSID_MAC_LENGTH);
+                        break;
+
+                    case HCI_CMND_SIMPLE_LINK_START:
+                        break;
+
+                    case HCI_NETAPP_IPCONFIG:
+
+                        //Read IP address
+                        STREAM_TO_STREAM(RecvParams,RetParams,NETAPP_IPCONFIG_IP_LENGTH);
+                        RecvParams += 4;
+
+                        //Read subnet
+                        STREAM_TO_STREAM(RecvParams,RetParams,NETAPP_IPCONFIG_IP_LENGTH);
+                        RecvParams += 4;
+
+                        //Read default GW
+                        STREAM_TO_STREAM(RecvParams,RetParams,NETAPP_IPCONFIG_IP_LENGTH);
+                        RecvParams += 4;
+
+                        //Read DHCP server
+                        STREAM_TO_STREAM(RecvParams,RetParams,NETAPP_IPCONFIG_IP_LENGTH);
+                        RecvParams += 4;
+
+                        //Read DNS server
+                        STREAM_TO_STREAM(RecvParams,RetParams,NETAPP_IPCONFIG_IP_LENGTH);
+                        RecvParams += 4;
+
+                        //Read Mac address
+                        STREAM_TO_STREAM(RecvParams,RetParams,NETAPP_IPCONFIG_MAC_LENGTH);
+                        RecvParams += 6;
+
+                        //Read SSID
+                        STREAM_TO_STREAM(RecvParams,RetParams,NETAPP_IPCONFIG_SSID_LENGTH);
+                        break;
+
+                    default :
+                        DBG_HCI("UNKNOWN Event Received : 0x%04X ", received_op_code);
+                        break;
+                    }
+
+                }
+                if (received_op_code == _simple_link.get_op_code())
+                {
+                    _simple_link.set_op_code(0);
+                }
+            }
+            else
+            {
+                pucReceivedParams = received_data;
+                STREAM_TO_UINT8((uint8_t *)received_data, HCI_PACKET_ARGSIZE_OFFSET, argument_size);
+
+                STREAM_TO_UINT16((uint8_t *)received_data, HCI_PACKET_LENGTH_OFFSET, length);
+
+                // Data received: note that the only case where from and from length
+                // are not null is in recv from, so fill the args accordingly
+                if (from)
+                {
+                    STREAM_TO_UINT32((uint8_t *)(received_data + HCI_DATA_HEADER_SIZE), BSD_RECV_FROM_FROMLEN_OFFSET, *(uint32_t *)fromlen);
+                    memcpy(from, (received_data + HCI_DATA_HEADER_SIZE + BSD_RECV_FROM_FROM_OFFSET) ,*fromlen);
+                }
+
+                memcpy(ret_param, pucReceivedParams + HCI_DATA_HEADER_SIZE + argument_size, length - argument_size);
+
+                _simple_link.set_pending_data(0);
+            }
+
+            _simple_link.set_data_received_flag(0);
+            _spi.wlan_irq_enable();
+
+            // Since we are going to TX - we need to handle this event after the ResumeSPi since we need interrupts
+            if ((*received_data == HCI_TYPE_EVNT) && (received_op_code == HCI_EVNT_PATCHES_REQ))
+            {
+                hci_unsol_handle_patch_request((uint8_t *)received_data);
+            }
+            if ((_simple_link.get_op_code() == 0) && (_simple_link.get_pending_data() == 0))
+            {
+                return NULL;
+            }
+        }
+    }
+}
+
+int32_t cc3000_event::hci_unsol_event_handler(uint8_t *event_hdr) {
+    uint8_t *data = NULL;
+    int32_t event_type;
+    uint32_t number_of_released_packets;
+    uint32_t number_of_sent_packets;
+
+    STREAM_TO_UINT16(event_hdr, HCI_EVENT_OPCODE_OFFSET,event_type);
+
+    if (event_type & HCI_EVNT_UNSOL_BASE) {
+        switch(event_type) {
+            case HCI_EVNT_DATA_UNSOL_FREE_BUFF:
+            {
+                hci_event_unsol_flowcontrol_handler(event_hdr);
+
+                number_of_released_packets = _simple_link.get_released_packets();
+                number_of_sent_packets = _simple_link.get_sent_packets();
+
+                if (number_of_released_packets == number_of_sent_packets)
+                {
+                    if (_simple_link.get_tx_complete_signal())
+                    {
+                        //tWlanCB func_pointer = (tWlanCB)_simple_link.get_func_pointer(WLAN_CB);
+                        _cc3000.usync_callback(HCI_EVENT_CC3000_CAN_SHUT_DOWN, NULL, 0);
+                    }
+                }
+                return 1;
+            }
+        }
+    }
+
+    if (event_type & HCI_EVNT_WLAN_UNSOL_BASE) {
+        switch(event_type) {
+            case HCI_EVNT_WLAN_KEEPALIVE:
+            case HCI_EVNT_WLAN_UNSOL_CONNECT:
+            case HCI_EVNT_WLAN_UNSOL_DISCONNECT:
+            case HCI_EVNT_WLAN_UNSOL_INIT:
+            case HCI_EVNT_WLAN_ASYNC_SIMPLE_CONFIG_DONE:
+                 _cc3000.usync_callback(event_type, 0, 0);
+                break;
+            case HCI_EVNT_WLAN_UNSOL_DHCP:
+            {
+                uint8_t params[NETAPP_IPCONFIG_MAC_OFFSET + 1]; // extra byte is for the status
+                uint8_t *recParams = params;
+                data = (uint8_t *)(event_hdr) + HCI_EVENT_HEADER_SIZE;
+
+                //Read IP address
+                STREAM_TO_STREAM(data,recParams,NETAPP_IPCONFIG_IP_LENGTH);
+                data += 4;
+                //Read subnet
+                STREAM_TO_STREAM(data,recParams,NETAPP_IPCONFIG_IP_LENGTH);
+                data += 4;
+                //Read default GW
+                STREAM_TO_STREAM(data,recParams,NETAPP_IPCONFIG_IP_LENGTH);
+                data += 4;
+                //Read DHCP server
+                STREAM_TO_STREAM(data,recParams,NETAPP_IPCONFIG_IP_LENGTH);
+                data += 4;
+                //Read DNS server
+                STREAM_TO_STREAM(data,recParams,NETAPP_IPCONFIG_IP_LENGTH);
+                // read the status
+                STREAM_TO_UINT8(event_hdr, HCI_EVENT_STATUS_OFFSET, *recParams);
+
+                _cc3000.usync_callback(event_type, (uint8_t  *)params, sizeof(params));
+
+                break;
+            }
+            case HCI_EVNT_WLAN_ASYNC_PING_REPORT:
+            {
+                netapp_pingreport_args_t params;
+                data = (uint8_t *)(event_hdr) + HCI_EVENT_HEADER_SIZE;
+                STREAM_TO_UINT32(data, NETAPP_PING_PACKETS_SENT_OFFSET, params.packets_sent);
+                STREAM_TO_UINT32(data, NETAPP_PING_PACKETS_RCVD_OFFSET, params.packets_received);
+                STREAM_TO_UINT32(data, NETAPP_PING_MIN_RTT_OFFSET, params.min_round_time);
+                STREAM_TO_UINT32(data, NETAPP_PING_MAX_RTT_OFFSET, params.max_round_time);
+                STREAM_TO_UINT32(data, NETAPP_PING_AVG_RTT_OFFSET, params.avg_round_time);
+
+                _cc3000.usync_callback(event_type, (uint8_t  *)&params, sizeof(params));
+                break;
+            }
+            case HCI_EVNT_BSD_TCP_CLOSE_WAIT:
+            {
+                _cc3000.usync_callback(event_type, NULL, 0);
+                break;
+            }
+
+            //'default' case which means "event not supported"
+            default:
+                return (0);
+        }
+        return(1);
+    }
+
+    if ((event_type == HCI_EVNT_SEND) || (event_type == HCI_EVNT_SENDTO) || (event_type == HCI_EVNT_WRITE)) {
+        uint8_t *pArg;
+        int32_t status;
+        pArg = M_BSD_RESP_PARAMS_OFFSET(event_hdr);
+        STREAM_TO_UINT32(pArg, BSD_RSP_PARAMS_STATUS_OFFSET,status);
+        if (ERROR_SOCKET_INACTIVE == status) {
+            // The only synchronous event that can come from SL device in form of
+            // command complete is "Command Complete" on data sent, in case SL device
+            // was unable to transmit
+            int32_t transmit_error  = _simple_link.get_transmit_error();
+            STREAM_TO_UINT8(event_hdr, HCI_EVENT_STATUS_OFFSET, transmit_error);
+            _simple_link.set_transmit_error(transmit_error);
+            update_socket_active_status(M_BSD_RESP_PARAMS_OFFSET(event_hdr));
+            return (1);
+        }
+        else {
+            return (0);
+        }
+    }
+    return(0);
+}
+
+int32_t cc3000_event::hci_unsolicited_event_handler(void) {
+    uint32_t res = 0;
+    uint8_t *received_data;
+
+    if (_simple_link.get_data_received_flag() != 0) {
+        received_data = (_simple_link.get_received_data());
+
+        if (*received_data == HCI_TYPE_EVNT) {
+            // unsolicited event received - finish handling
+            if (hci_unsol_event_handler((uint8_t *)received_data) == 1) {
+                // An unsolicited event was received:
+                // release the buffer and clean the event received
+                _simple_link.set_data_received_flag(0);
+
+                res = 1;
+                _spi.wlan_irq_enable();
+            }
+        }
+    }
+    return res;
+}
+
+void cc3000_event::set_socket_active_status(int32_t sd, int32_t status) {
+    if (M_IS_VALID_SD(sd) && M_IS_VALID_STATUS(status)) {
+        socket_active_status &= ~(1 << sd);      /* clean socket's mask */
+        socket_active_status |= (status << sd); /* set new socket's mask */
+    }
+}
+
+int32_t cc3000_event::hci_event_unsol_flowcontrol_handler(uint8_t *event) {
+    int32_t temp, value;
+    uint16_t i;
+    uint16_t pusNumberOfHandles=0;
+    uint8_t *pReadPayload;
+
+    STREAM_TO_UINT16((uint8_t *)event,HCI_EVENT_HEADER_SIZE,pusNumberOfHandles);
+    pReadPayload = ((uint8_t *)event + HCI_EVENT_HEADER_SIZE + sizeof(pusNumberOfHandles));
+    temp = 0;
+
+    for(i = 0; i < pusNumberOfHandles; i++) {
+        STREAM_TO_UINT16(pReadPayload, FLOW_CONTROL_EVENT_FREE_BUFFS_OFFSET, value);
+        temp += value;
+        pReadPayload += FLOW_CONTROL_EVENT_SIZE;
+    }
+
+    _simple_link.set_number_free_buffers(_simple_link.get_number_free_buffers() + temp);
+    _simple_link.set_number_of_released_packets(_simple_link.get_released_packets() + temp);
+
+    return(ESUCCESS);
+}
+
+int32_t cc3000_event::get_socket_active_status(int32_t sd) {
+    if (M_IS_VALID_SD(sd)) {
+        return (socket_active_status & (1 << sd)) ? SOCKET_STATUS_INACTIVE : SOCKET_STATUS_ACTIVE;
+    } else {
+        return SOCKET_STATUS_INACTIVE;
+    }
+}
+
+void cc3000_event::update_socket_active_status(uint8_t *resp_params) {
+    int32_t status, sd;
+
+    STREAM_TO_UINT32(resp_params, BSD_RSP_PARAMS_SOCKET_OFFSET,sd);
+    STREAM_TO_UINT32(resp_params, BSD_RSP_PARAMS_STATUS_OFFSET,status);
+
+    if (ERROR_SOCKET_INACTIVE == status) {
+        set_socket_active_status(sd, SOCKET_STATUS_INACTIVE);
+    }
+}
+
+void cc3000_event::simplelink_wait_event(uint16_t op_code, void *ret_param) {
+    // In the blocking implementation the control to caller will be returned only
+    // after the end of current transaction
+    _simple_link.set_op_code(op_code);
+    hci_event_handler(ret_param, 0, 0);
+}
+
+void cc3000_event::simplelink_wait_data(uint8_t *pBuf, uint8_t *from, uint8_t *fromlen) {
+    // In the blocking implementation the control to caller will be returned only
+    // after the end of current transaction, i.e. only after data will be received
+    _simple_link.set_pending_data(1);
+    hci_event_handler(pBuf, from, fromlen);
+}
+
+
+} // end of cc3000
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/cc3000_event.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,144 @@
+/*****************************************************************************
+*
+*  C++ interface/implementation created by Martin Kojtal (0xc0170). Thanks to
+*  Jim Carver and Frank Vannieuwkerke for their inital cc3000 mbed port and
+*  provided help.
+*
+*  This version of "host driver" uses CC3000 Host Driver Implementation. Thus
+*  read the following copyright:
+*
+*  Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*****************************************************************************/
+#ifndef CC3000_EVENT_H
+#define CC3000_EVENT_H
+
+typedef struct _bsd_read_return_t
+{
+    int32_t             iSocketDescriptor;
+    int32_t             iNumberOfBytes;
+    uint32_t    uiFlags;
+} tBsdReadReturnParams;
+
+typedef struct _bsd_getsockopt_return_t
+{
+    uint8_t ucOptValue[4];
+    uint8_t          iStatus;
+} tBsdGetSockOptReturnParams;
+
+typedef struct _bsd_accept_return_t
+{
+    int32_t             iSocketDescriptor;
+    int32_t             iStatus;
+    sockaddr         tSocketAddress;
+
+} tBsdReturnParams;
+
+typedef struct _bsd_select_return_t
+{
+    int32_t            iStatus;
+    uint32_t           uiRdfd;
+    uint32_t           uiWrfd;
+    uint32_t           uiExfd;
+} tBsdSelectRecvParams;
+
+typedef struct _bsd_gethostbyname_return_t
+{
+    int32_t  retVal;
+    int32_t  outputAddress;
+} tBsdGethostbynameParams;
+
+#define FLOW_CONTROL_EVENT_HANDLE_OFFSET        (0)
+#define FLOW_CONTROL_EVENT_BLOCK_MODE_OFFSET    (1)
+#define FLOW_CONTROL_EVENT_FREE_BUFFS_OFFSET    (2)
+#define FLOW_CONTROL_EVENT_SIZE                 (4)
+
+#define BSD_RSP_PARAMS_SOCKET_OFFSET            (0)
+#define BSD_RSP_PARAMS_STATUS_OFFSET            (4)
+
+#define GET_HOST_BY_NAME_RETVAL_OFFSET          (0)
+#define GET_HOST_BY_NAME_ADDR_OFFSET            (4)
+
+#define ACCEPT_SD_OFFSET                        (0)
+#define ACCEPT_RETURN_STATUS_OFFSET             (4)
+#define ACCEPT_ADDRESS__OFFSET                  (8)
+
+#define SL_RECEIVE_SD_OFFSET                    (0)
+#define SL_RECEIVE_NUM_BYTES_OFFSET             (4)
+#define SL_RECEIVE__FLAGS__OFFSET               (8)
+
+
+#define SELECT_STATUS_OFFSET                    (0)
+#define SELECT_READFD_OFFSET                    (4)
+#define SELECT_WRITEFD_OFFSET                   (8)
+#define SELECT_EXFD_OFFSET                      (12)
+
+
+#define NETAPP_IPCONFIG_IP_OFFSET               (0)
+#define NETAPP_IPCONFIG_SUBNET_OFFSET           (4)
+#define NETAPP_IPCONFIG_GW_OFFSET               (8)
+#define NETAPP_IPCONFIG_DHCP_OFFSET             (12)
+#define NETAPP_IPCONFIG_DNS_OFFSET              (16)
+#define NETAPP_IPCONFIG_MAC_OFFSET              (20)
+#define NETAPP_IPCONFIG_SSID_OFFSET             (26)
+
+#define NETAPP_IPCONFIG_IP_LENGTH               (4)
+#define NETAPP_IPCONFIG_MAC_LENGTH              (6)
+#define NETAPP_IPCONFIG_SSID_LENGTH             (32)
+
+
+#define NETAPP_PING_PACKETS_SENT_OFFSET         (0)
+#define NETAPP_PING_PACKETS_RCVD_OFFSET         (4)
+#define NETAPP_PING_MIN_RTT_OFFSET              (8)
+#define NETAPP_PING_MAX_RTT_OFFSET              (12)
+#define NETAPP_PING_AVG_RTT_OFFSET              (16)
+
+#define GET_SCAN_RESULTS_TABlE_COUNT_OFFSET              (0)
+#define GET_SCAN_RESULTS_SCANRESULT_STATUS_OFFSET        (4)
+#define GET_SCAN_RESULTS_ISVALID_TO_SSIDLEN_OFFSET       (8)
+#define GET_SCAN_RESULTS_FRAME_TIME_OFFSET               (10)
+#define GET_SCAN_RESULTS_SSID_MAC_LENGTH                 (38)
+
+#define M_BSD_RESP_PARAMS_OFFSET(hci_event_hdr)((uint8_t *)(hci_event_hdr) + HCI_EVENT_HEADER_SIZE)
+
+#define SOCKET_STATUS_ACTIVE       0
+#define SOCKET_STATUS_INACTIVE     1
+/* Init socket_active_status = 'all ones': init all sockets with SOCKET_STATUS_INACTIVE.
+   Will be changed by 'set_socket_active_status' upon 'connect' and 'accept' calls */
+#define SOCKET_STATUS_INIT_VAL  0xFFFF
+#define M_IS_VALID_SD(sd) ((0 <= (sd)) && ((sd) <= 7))
+#define M_IS_VALID_STATUS(status) (((status) == SOCKET_STATUS_ACTIVE)||((status) == SOCKET_STATUS_INACTIVE))
+
+#define BSD_RECV_FROM_FROMLEN_OFFSET    (4)
+#define BSD_RECV_FROM_FROM_OFFSET       (16)
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/cc3000_hci.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,144 @@
+/*****************************************************************************
+*
+*  C++ interface/implementation created by Martin Kojtal (0xc0170). Thanks to
+*  Jim Carver and Frank Vannieuwkerke for their inital cc3000 mbed port and
+*  provided help.
+*
+*  This version of "host driver" uses CC3000 Host Driver Implementation. Thus
+*  read the following copyright:
+*
+*  Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*****************************************************************************/
+#include "cc3000.h"
+
+namespace mbed_cc3000 {
+
+cc3000_hci::cc3000_hci(cc3000_spi &spi) : _spi(spi) {
+
+}
+
+cc3000_hci::~cc3000_hci() {
+
+}
+
+uint16_t  cc3000_hci::command_send(uint16_t op_code, uint8_t *buffer, uint8_t length) {
+    uint8_t *stream;
+
+    DBG_HCI_CMD("Command Sent : 0x%04X", op_code);
+
+    stream = (buffer + SPI_HEADER_SIZE);
+
+    UINT8_TO_STREAM(stream, HCI_TYPE_CMND);
+    stream = UINT16_TO_STREAM(stream, op_code);
+    UINT8_TO_STREAM(stream, length);
+    //Update the opcode of the event we will be waiting for
+    _spi.write(buffer, length + SIMPLE_LINK_HCI_CMND_HEADER_SIZE);
+    return(0);
+}
+
+uint32_t  cc3000_hci::data_send(uint8_t op_code, uint8_t *args, uint16_t arg_length,
+                    uint16_t data_length, const uint8_t *tail, uint16_t tail_length) {
+    uint8_t *stream;
+
+    stream = ((args) + SPI_HEADER_SIZE);
+
+    UINT8_TO_STREAM(stream, HCI_TYPE_DATA);
+    UINT8_TO_STREAM(stream, op_code);
+    UINT8_TO_STREAM(stream, arg_length);
+    stream = UINT16_TO_STREAM(stream, arg_length + data_length + tail_length);
+
+    // Send the packet
+    _spi.write(args, SIMPLE_LINK_HCI_DATA_HEADER_SIZE + arg_length + data_length + tail_length);
+
+    return 0;
+}
+
+void  cc3000_hci::data_command_send(uint16_t op_code, uint8_t *buffer, uint8_t arg_length, uint16_t data_length) {
+    uint8_t *stream = (buffer + SPI_HEADER_SIZE);
+
+    UINT8_TO_STREAM(stream, HCI_TYPE_DATA);
+    UINT8_TO_STREAM(stream, op_code);
+    UINT8_TO_STREAM(stream, arg_length);
+    stream = UINT16_TO_STREAM(stream, arg_length + data_length);
+
+    // Send the command
+    _spi.write(buffer, arg_length + data_length + SIMPLE_LINK_HCI_DATA_CMND_HEADER_SIZE);
+
+    return;
+}
+
+void  cc3000_hci::patch_send(uint8_t op_code, uint8_t *buffer, uint8_t *patch, uint16_t data_length) {
+    uint16_t usTransLength;
+    uint8_t *stream = (buffer + SPI_HEADER_SIZE);
+    UINT8_TO_STREAM(stream, HCI_TYPE_PATCH);
+    UINT8_TO_STREAM(stream, op_code);
+    stream = UINT16_TO_STREAM(stream, data_length + SIMPLE_LINK_HCI_PATCH_HEADER_SIZE);
+    if (data_length <= SL_PATCH_PORTION_SIZE) {
+        UINT16_TO_STREAM(stream, data_length);
+        stream = UINT16_TO_STREAM(stream, data_length);
+        memcpy((buffer + SPI_HEADER_SIZE) + HCI_PATCH_HEADER_SIZE, patch, data_length);
+        // Update the opcode of the event we will be waiting for
+        _spi.write(buffer, data_length + HCI_PATCH_HEADER_SIZE);
+    } else {
+
+        usTransLength = (data_length/SL_PATCH_PORTION_SIZE);
+        UINT16_TO_STREAM(stream, data_length + SIMPLE_LINK_HCI_PATCH_HEADER_SIZE + usTransLength*SIMPLE_LINK_HCI_PATCH_HEADER_SIZE);
+        stream = UINT16_TO_STREAM(stream, SL_PATCH_PORTION_SIZE);
+        memcpy(buffer + SPI_HEADER_SIZE + HCI_PATCH_HEADER_SIZE, patch, SL_PATCH_PORTION_SIZE);
+        data_length -= SL_PATCH_PORTION_SIZE;
+        patch += SL_PATCH_PORTION_SIZE;
+
+        // Update the opcode of the event we will be waiting for
+        _spi.write(buffer, SL_PATCH_PORTION_SIZE + HCI_PATCH_HEADER_SIZE);
+
+        stream = (buffer + SPI_HEADER_SIZE);
+        while (data_length) {
+            if (data_length <= SL_PATCH_PORTION_SIZE) {
+                usTransLength = data_length;
+                data_length = 0;
+            } else {
+                usTransLength = SL_PATCH_PORTION_SIZE;
+                data_length -= usTransLength;
+            }
+
+            *(uint16_t *)stream = usTransLength;
+            memcpy(stream + SIMPLE_LINK_HCI_PATCH_HEADER_SIZE, patch, usTransLength);
+            patch += usTransLength;
+
+            // Update the opcode of the event we will be waiting for
+            _spi.write((unsigned char *)stream, usTransLength + sizeof(usTransLength));
+        }
+    }
+}
+
+} // mbed_cc3000 namespace
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/cc3000_netapp.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,200 @@
+/*****************************************************************************
+*
+*  C++ interface/implementation created by Martin Kojtal (0xc0170). Thanks to
+*  Jim Carver and Frank Vannieuwkerke for their inital cc3000 mbed port and
+*  provided help.
+*
+*  This version of "host driver" uses CC3000 Host Driver Implementation. Thus
+*  read the following copyright:
+*
+*  Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*****************************************************************************/
+#include "cc3000.h"
+#include "cc3000_netapp.h"
+
+namespace mbed_cc3000 {
+
+cc3000_netapp::cc3000_netapp(cc3000_simple_link &simple_link, cc3000_nvmem &nvmem, cc3000_hci &hci , cc3000_event &event) :
+    _simple_link(simple_link), _nvmem(nvmem), _hci(hci), _event(event) {
+
+}
+
+cc3000_netapp::~cc3000_netapp() {
+
+}
+
+int32_t cc3000_netapp::config_mac_adrress(uint8_t * mac) {
+    return  _nvmem.set_mac_address(mac);
+}
+
+int32_t cc3000_netapp::dhcp(uint32_t *ip, uint32_t *subnet_mask,uint32_t *default_gateway, uint32_t *dns_server) {
+    int8_t scRet;
+    uint8_t *ptr;
+    uint8_t *args;
+
+    scRet = EFAIL;
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_CMD);
+
+    // Fill in temporary command buffer
+    ARRAY_TO_STREAM(args,ip,4);
+    ARRAY_TO_STREAM(args,subnet_mask,4);
+    ARRAY_TO_STREAM(args,default_gateway,4);
+    args = UINT32_TO_STREAM(args, 0);
+    ARRAY_TO_STREAM(args,dns_server,4);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_NETAPP_DHCP, ptr, NETAPP_DHCP_PARAMS_LEN);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_NETAPP_DHCP, &scRet);
+
+    return scRet;
+}
+
+#ifndef CC3000_TINY_DRIVER
+void cc3000_netapp::ipconfig( tNetappIpconfigRetArgs * ipconfig ) {
+    uint8_t *ptr;
+
+    ptr = _simple_link.get_transmit_buffer();
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_NETAPP_IPCONFIG, ptr, 0);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_NETAPP_IPCONFIG, ipconfig );
+}
+
+
+int32_t cc3000_netapp::timeout_values(uint32_t *dhcp, uint32_t *arp,uint32_t *keep_alive, uint32_t *inactivity) {
+    int8_t scRet;
+    uint8_t *ptr;
+    uint8_t *args;
+
+    scRet = EFAIL;
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_CMD);
+
+    // Set minimal values of timers
+    MIN_TIMER_SET(*dhcp)
+    MIN_TIMER_SET(*arp)
+    MIN_TIMER_SET(*keep_alive)
+    MIN_TIMER_SET(*inactivity)
+
+    // Fill in temporary command buffer
+    args = UINT32_TO_STREAM(args, *dhcp);
+    args = UINT32_TO_STREAM(args, *arp);
+    args = UINT32_TO_STREAM(args, *keep_alive);
+    args = UINT32_TO_STREAM(args, *inactivity);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_NETAPP_SET_TIMERS, ptr, NETAPP_SET_TIMER_PARAMS_LEN);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_NETAPP_SET_TIMERS, &scRet);
+
+    return scRet;
+}
+
+int32_t cc3000_netapp::ping_send(uint32_t *ip, uint32_t ping_attempts, uint32_t ping_size, uint32_t ping_timeout) {
+    int8_t scRet;
+    uint8_t *ptr, *args;
+
+    scRet = EFAIL;
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_CMD);
+
+    // Fill in temporary command buffer
+    args = UINT32_TO_STREAM(args, *ip);
+    args = UINT32_TO_STREAM(args, ping_attempts);
+    args = UINT32_TO_STREAM(args, ping_size);
+    args = UINT32_TO_STREAM(args, ping_timeout);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_NETAPP_PING_SEND, ptr, NETAPP_PING_SEND_PARAMS_LEN);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_NETAPP_PING_SEND, &scRet);
+
+    return scRet;
+}
+
+void cc3000_netapp::ping_report() {
+    uint8_t *ptr;
+    int8_t scRet;
+    ptr = _simple_link.get_transmit_buffer();
+
+
+    scRet = EFAIL;
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_NETAPP_PING_REPORT, ptr, 0);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_NETAPP_PING_REPORT, &scRet);
+}
+
+int32_t cc3000_netapp::ping_stop() {
+    int8_t scRet;
+    uint8_t *ptr;
+
+    scRet = EFAIL;
+    ptr = _simple_link.get_transmit_buffer();
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_NETAPP_PING_STOP, ptr, 0);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_NETAPP_PING_STOP, &scRet);
+
+    return scRet;
+}
+
+int32_t cc3000_netapp::arp_flush() {
+    int8_t scRet;
+    uint8_t *ptr;
+
+    scRet = EFAIL;
+    ptr = _simple_link.get_transmit_buffer();
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_NETAPP_ARP_FLUSH, ptr, 0);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_NETAPP_ARP_FLUSH, &scRet);
+
+    return scRet;
+}
+#endif
+
+} // mbed_cc3000
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/cc3000_netapp.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,89 @@
+/*****************************************************************************
+*
+*  C++ interface/implementation created by Martin Kojtal (0xc0170). Thanks to
+*  Jim Carver and Frank Vannieuwkerke for their inital cc3000 mbed port and
+*  provided help.
+*
+*  This version of "host driver" uses CC3000 Host Driver Implementation. Thus
+*  read the following copyright:
+*
+*  Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*****************************************************************************/
+#ifndef CC3000_NETAPP_H
+#define CC3000_NETAPP_H
+
+#define MIN_TIMER_VAL_SECONDS      20
+#define MIN_TIMER_SET(t)    if ((0 != t) && (t < MIN_TIMER_VAL_SECONDS)) \
+                            { \
+                                t = MIN_TIMER_VAL_SECONDS; \
+                            }
+
+
+#define NETAPP_DHCP_PARAMS_LEN                 (20)
+#define NETAPP_SET_TIMER_PARAMS_LEN            (20)
+#define NETAPP_SET_DEBUG_LEVEL_PARAMS_LEN      (4)
+#define NETAPP_PING_SEND_PARAMS_LEN            (16)
+
+
+typedef struct _netapp_dhcp_ret_args_t
+{
+    uint8_t aucIP[4];
+    uint8_t aucSubnetMask[4];
+    uint8_t aucDefaultGateway[4];
+    uint8_t aucDHCPServer[4];
+    uint8_t aucDNSServer[4];
+}tNetappDhcpParams;
+
+typedef struct _netapp_ipconfig_ret_args_t
+{
+    uint8_t aucIP[4];
+    uint8_t aucSubnetMask[4];
+    uint8_t aucDefaultGateway[4];
+    uint8_t aucDHCPServer[4];
+    uint8_t aucDNSServer[4];
+    uint8_t uaMacAddr[6];
+    uint8_t uaSSID[32];
+}tNetappIpconfigRetArgs;
+
+
+/*Ping send report parameters*/
+typedef struct _netapp_pingreport_args
+{
+    uint32_t packets_sent;
+    uint32_t packets_received;
+    uint32_t min_round_time;
+    uint32_t max_round_time;
+    uint32_t avg_round_time;
+} netapp_pingreport_args_t;
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/cc3000_nvmem.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,183 @@
+/*****************************************************************************
+*
+*  C++ interface/implementation created by Martin Kojtal (0xc0170). Thanks to
+*  Jim Carver and Frank Vannieuwkerke for their inital cc3000 mbed port and
+*  provided help.
+*
+*  This version of "host driver" uses CC3000 Host Driver Implementation. Thus
+*  read the following copyright:
+*
+*  Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*****************************************************************************/
+#include "cc3000.h"
+#include "cc3000_nvmem.h"
+#include "cc3000_common.h"
+
+namespace mbed_cc3000 {
+
+cc3000_nvmem::cc3000_nvmem(cc3000_hci &hci, cc3000_event &event, cc3000_simple_link &simple_link)
+        : _hci(hci), _event(event), _simple_link(simple_link) {
+
+}
+
+cc3000_nvmem::~cc3000_nvmem() {
+
+}
+
+int32_t  cc3000_nvmem::read(uint32_t file_id, uint32_t length, uint32_t offset, uint8_t *buff) {
+    uint8_t ucStatus = 0xFF;
+    uint8_t *ptr;
+    uint8_t *args;
+
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_CMD);
+    // Fill in HCI packet structure
+    args = UINT32_TO_STREAM(args, file_id);
+    args = UINT32_TO_STREAM(args, length);
+    args = UINT32_TO_STREAM(args, offset);
+
+    // Initiate HCI command
+    _hci.command_send(HCI_CMND_NVMEM_READ, ptr, NVMEM_READ_PARAMS_LEN);
+    _event.simplelink_wait_event(HCI_CMND_NVMEM_READ, &ucStatus);
+
+    // If data is present, read it even when an error is returned.
+    // Note: It is the users responsibility to ignore the data when an error is returned.
+    // Wait for the data in a synchronous way.
+    //  We assume the buffer is large enough to also store nvmem parameters.
+    _event.simplelink_wait_data(buff, 0, 0);
+
+    return(ucStatus);
+}
+
+int32_t  cc3000_nvmem::write(uint32_t file_id, uint32_t length, uint32_t entry_offset, uint8_t *buff) {
+    int32_t iRes;
+    uint8_t *ptr;
+    uint8_t *args;
+
+    iRes = EFAIL;
+
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + SPI_HEADER_SIZE + HCI_DATA_CMD_HEADER_SIZE);
+
+    // Fill in HCI packet structure
+    args = UINT32_TO_STREAM(args, file_id);
+    args = UINT32_TO_STREAM(args, 12);
+    args = UINT32_TO_STREAM(args, length);
+    args = UINT32_TO_STREAM(args, entry_offset);
+
+    memcpy((ptr + SPI_HEADER_SIZE + HCI_DATA_CMD_HEADER_SIZE +
+                    NVMEM_WRITE_PARAMS_LEN),buff,length);
+
+    // Initiate a HCI command on the data channel
+    _hci.data_command_send(HCI_CMND_NVMEM_WRITE, ptr, NVMEM_WRITE_PARAMS_LEN, length);
+
+    _event.simplelink_wait_event(HCI_EVNT_NVMEM_WRITE, &iRes);
+
+    return(iRes);
+}
+
+uint8_t  cc3000_nvmem::set_mac_address(uint8_t *mac) {
+    return  write(NVMEM_MAC_FILEID, MAC_ADDR_LEN, 0, mac);
+}
+
+uint8_t  cc3000_nvmem::get_mac_address(uint8_t *mac) {
+    return  read(NVMEM_MAC_FILEID, MAC_ADDR_LEN, 0, mac);
+}
+
+uint8_t  cc3000_nvmem::write_patch(uint32_t file_id, uint32_t length, const uint8_t *data) {
+    uint8_t     status = 0;
+    uint16_t    offset = 0;
+    uint8_t*      spDataPtr = (uint8_t*)data;
+
+    while ((status == 0) && (length >= SP_PORTION_SIZE)) {
+        status = write(file_id, SP_PORTION_SIZE, offset, spDataPtr);
+        offset += SP_PORTION_SIZE;
+        length -= SP_PORTION_SIZE;
+        spDataPtr += SP_PORTION_SIZE;
+    }
+
+    if (status !=0) {
+        // NVMEM error occurred
+        return status;
+    }
+
+    if (length != 0) {
+        // If length MOD 512 is nonzero, write the remaining bytes.
+        status = write(file_id, length, offset, spDataPtr);
+    }
+
+    return status;
+}
+
+int32_t  cc3000_nvmem::create_entry(uint32_t file_id, uint32_t new_len) {
+    uint8_t *ptr;
+    uint8_t *args;
+    uint16_t retval;
+
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_CMD);
+
+    // Fill in HCI packet structure
+    args = UINT32_TO_STREAM(args, file_id);
+    args = UINT32_TO_STREAM(args, new_len);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_NVMEM_CREATE_ENTRY,ptr, NVMEM_CREATE_PARAMS_LEN);
+
+    _event.simplelink_wait_event(HCI_CMND_NVMEM_CREATE_ENTRY, &retval);
+
+    return(retval);
+}
+
+#ifndef CC3000_TINY_DRIVER
+uint8_t cc3000_nvmem::read_sp_version(uint8_t* patch_ver) {
+    uint8_t *ptr;
+    // 1st byte is the status and the rest is the SP version
+    uint8_t retBuf[5];
+
+    ptr = _simple_link.get_transmit_buffer();
+
+   // Initiate a HCI command, no args are required
+    _hci.command_send(HCI_CMND_READ_SP_VERSION, ptr, 0);
+    _event.simplelink_wait_event(HCI_CMND_READ_SP_VERSION, retBuf);
+
+    // package ID
+    *patch_ver = retBuf[3];
+    // package build number
+    *(patch_ver+1) = retBuf[4];
+
+    return(retBuf[0]);
+}
+#endif
+
+} // mbed_cc3000 namespace
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/cc3000_nvmem.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,101 @@
+/*****************************************************************************
+*
+*  C++ interface/implementation created by Martin Kojtal (0xc0170). Thanks to
+*  Jim Carver and Frank Vannieuwkerke for their inital cc3000 mbed port and
+*  provided help.
+*
+*  This version of "host driver" uses CC3000 Host Driver Implementation. Thus
+*  read the following copyright:
+*
+*  Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*****************************************************************************/
+#ifndef CC3000_NVMEM_H
+#define CC3000_NVMEM_H
+
+#define NVMEM_READ_PARAMS_LEN       (12)
+#define NVMEM_CREATE_PARAMS_LEN     (8)
+#define NVMEM_WRITE_PARAMS_LEN      (16)
+
+
+/****************************************************************************
+**
+**    Definitions for File IDs
+**
+****************************************************************************/
+/* --------------------------------------------------------- EEPROM FAT table ---------------------------------------------------------
+
+ File ID                            Offset      File Size   Used Size   Parameter
+ #  ID                              address     (bytes)     (bytes)
+ --------------------------------------------------------------------------------------------------------------------------------------
+ 0  NVMEM_NVS_FILEID                0x50        0x1A0       0x1A        RF Calibration results table(generated automatically by TX Bip)
+ 1  NVMEM_NVS_SHADOW_FILEID         0x1F0       0x1A0       0x1A        NVS Shadow
+ 2  NVMEM_WLAN_CONFIG_FILEID        0x390       0x1000      0x64        WLAN configuration
+ 3  NVMEM_WLAN_CONFIG_SHADOW_FILEID 0x1390      0x1000      0x64        WLAN configuration shadow
+ 4  NVMEM_WLAN_DRIVER_SP_FILEID     0x2390      0x2000      variable    WLAN Driver ROM Patches
+ 5  NVMEM_WLAN_FW_SP_FILEID         0x4390      0x2000      variable    WLAN FW Patches
+ 6  NVMEM_MAC_FILEID                0x6390      0x10        0x10        6 bytes of MAC address
+ 7  NVMEM_FRONTEND_VARS_FILEID      0x63A0      0x10        0x10        Frontend Vars
+ 8  NVMEM_IP_CONFIG_FILEID          0x63B0      0x40        0x40        IP configuration
+ 9  NVMEM_IP_CONFIG_SHADOW_FILEID   0x63F0      0x40        0x40        IP configuration shadow
+10  NVMEM_BOOTLOADER_SP_FILEID      0x6430      0x400       variable    Bootloader Patches
+11  NVMEM_RM_FILEID                 0x6830      0x200       0x7F        Radio parameters
+12  NVMEM_AES128_KEY_FILEID         0x6A30      0x10        0x10        AES128 key file
+13  NVMEM_SHARED_MEM_FILEID         0x6A40      0x50        0x44        Host-CC3000 shared memory file
+14  NVMEM_USER_FILE_1_FILEID        0x6A90      variable    variable    1st user file
+15  NVMEM_USER_FILE_2_FILEID        variable    variable    variable    2nd user file
+*/
+/* NVMEM file ID - system files*/
+#define NVMEM_NVS_FILEID                             (0)
+#define NVMEM_NVS_SHADOW_FILEID                      (1)
+#define NVMEM_WLAN_CONFIG_FILEID                     (2)
+#define NVMEM_WLAN_CONFIG_SHADOW_FILEID              (3)
+#define NVMEM_WLAN_DRIVER_SP_FILEID                  (4)
+#define NVMEM_WLAN_FW_SP_FILEID                      (5)
+#define NVMEM_MAC_FILEID                             (6)
+#define NVMEM_FRONTEND_VARS_FILEID                   (7)
+#define NVMEM_IP_CONFIG_FILEID                       (8)
+#define NVMEM_IP_CONFIG_SHADOW_FILEID                (9)
+#define NVMEM_BOOTLOADER_SP_FILEID                   (10)
+#define NVMEM_RM_FILEID                              (11)
+
+/* NVMEM file ID - user files*/
+#define NVMEM_AES128_KEY_FILEID                      (12)
+#define NVMEM_SHARED_MEM_FILEID                      (13)
+#define NVMEM_USER_FILE_1_FILEID                     (14)
+#define NVMEM_USER_FILE_2_FILEID                     (15)
+
+/*  max entry in order to invalid nvmem              */
+#define NVMEM_MAX_ENTRY                              (16)
+
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/cc3000_security.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,382 @@
+/*****************************************************************************
+*
+*  C++ interface/implementation created by Martin Kojtal (0xc0170). Thanks to
+*  Jim Carver and Frank Vannieuwkerke for their inital cc3000 mbed port and
+*  provided help.
+*
+*  This version of "host driver" uses CC3000 Host Driver Implementation. Thus
+*  read the following copyright:
+*
+*  Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*****************************************************************************/
+#include "cc3000.h"
+
+namespace mbed_cc3000 {
+
+#ifndef CC3000_UNENCRYPTED_SMART_CONFIG
+
+// forward sbox
+static const uint8_t sbox[256] =   {
+//0     1    2      3     4    5     6     7      8    9     A      B    C     D     E     F
+0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, //0
+0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, //1
+0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, //2
+0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, //3
+0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, //4
+0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, //5
+0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, //6
+0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, //7
+0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, //8
+0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, //9
+0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, //A
+0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, //B
+0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, //C
+0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, //D
+0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, //E
+0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 }; //F
+// inverse sbox
+static const uint8_t rsbox[256] =
+{ 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb
+, 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb
+, 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e
+, 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25
+, 0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92
+, 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84
+, 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06
+, 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b
+, 0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73
+, 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e
+, 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b
+, 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4
+, 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f
+, 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef
+, 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61
+, 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d };
+// round constant
+static const uint8_t Rcon[11] = {0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36};
+
+void cc3000_security::expandKey(uint8_t *expanded_key, uint8_t *key) {
+  uint16_t ii, buf1;
+  for (ii=0;ii<16;ii++)
+    expanded_key[ii] = key[ii];
+  for (ii=1;ii<11;ii++)
+  {
+    buf1 = expanded_key[ii*16 - 4];
+    expanded_key[ii*16 + 0] = sbox[expanded_key[ii*16 - 3]]^expanded_key[(ii-1)*16 + 0]^Rcon[ii];
+    expanded_key[ii*16 + 1] = sbox[expanded_key[ii*16 - 2]]^expanded_key[(ii-1)*16 + 1];
+    expanded_key[ii*16 + 2] = sbox[expanded_key[ii*16 - 1]]^expanded_key[(ii-1)*16 + 2];
+    expanded_key[ii*16 + 3] = sbox[buf1                  ]^expanded_key[(ii-1)*16 + 3];
+    expanded_key[ii*16 + 4] = expanded_key[(ii-1)*16 + 4]^expanded_key[ii*16 + 0];
+    expanded_key[ii*16 + 5] = expanded_key[(ii-1)*16 + 5]^expanded_key[ii*16 + 1];
+    expanded_key[ii*16 + 6] = expanded_key[(ii-1)*16 + 6]^expanded_key[ii*16 + 2];
+    expanded_key[ii*16 + 7] = expanded_key[(ii-1)*16 + 7]^expanded_key[ii*16 + 3];
+    expanded_key[ii*16 + 8] = expanded_key[(ii-1)*16 + 8]^expanded_key[ii*16 + 4];
+    expanded_key[ii*16 + 9] = expanded_key[(ii-1)*16 + 9]^expanded_key[ii*16 + 5];
+    expanded_key[ii*16 +10] = expanded_key[(ii-1)*16 +10]^expanded_key[ii*16 + 6];
+    expanded_key[ii*16 +11] = expanded_key[(ii-1)*16 +11]^expanded_key[ii*16 + 7];
+    expanded_key[ii*16 +12] = expanded_key[(ii-1)*16 +12]^expanded_key[ii*16 + 8];
+    expanded_key[ii*16 +13] = expanded_key[(ii-1)*16 +13]^expanded_key[ii*16 + 9];
+    expanded_key[ii*16 +14] = expanded_key[(ii-1)*16 +14]^expanded_key[ii*16 +10];
+    expanded_key[ii*16 +15] = expanded_key[(ii-1)*16 +15]^expanded_key[ii*16 +11];
+  }
+}
+
+uint8_t cc3000_security::galois_mul2(uint8_t value) {
+    if (value >> 7) {
+        value = value << 1;
+        return (value ^ 0x1b);
+    } else {
+        return (value << 1);
+    }
+}
+
+void cc3000_security::aes_encr(uint8_t *state, uint8_t *expanded_key) {
+  uint8_t buf1, buf2, buf3, round;
+
+  for (round = 0; round < 9; round ++)
+  {
+    // addroundkey, sbox and shiftrows
+    // row 0
+    state[ 0]  = sbox[(state[ 0] ^ expanded_key[(round*16)     ])];
+    state[ 4]  = sbox[(state[ 4] ^ expanded_key[(round*16) +  4])];
+    state[ 8]  = sbox[(state[ 8] ^ expanded_key[(round*16) +  8])];
+    state[12]  = sbox[(state[12] ^ expanded_key[(round*16) + 12])];
+    // row 1
+    buf1 = state[1] ^ expanded_key[(round*16) + 1];
+    state[ 1]  = sbox[(state[ 5] ^ expanded_key[(round*16) +  5])];
+    state[ 5]  = sbox[(state[ 9] ^ expanded_key[(round*16) +  9])];
+    state[ 9]  = sbox[(state[13] ^ expanded_key[(round*16) + 13])];
+    state[13]  = sbox[buf1];
+    // row 2
+    buf1 = state[2] ^ expanded_key[(round*16) + 2];
+    buf2 = state[6] ^ expanded_key[(round*16) + 6];
+    state[ 2]  = sbox[(state[10] ^ expanded_key[(round*16) + 10])];
+    state[ 6]  = sbox[(state[14] ^ expanded_key[(round*16) + 14])];
+    state[10]  = sbox[buf1];
+    state[14]  = sbox[buf2];
+    // row 3
+    buf1 = state[15] ^ expanded_key[(round*16) + 15];
+    state[15]  = sbox[(state[11] ^ expanded_key[(round*16) + 11])];
+    state[11]  = sbox[(state[ 7] ^ expanded_key[(round*16) +  7])];
+    state[ 7]  = sbox[(state[ 3] ^ expanded_key[(round*16) +  3])];
+    state[ 3]  = sbox[buf1];
+
+    // mixcolums //////////
+    // col1
+    buf1 = state[0] ^ state[1] ^ state[2] ^ state[3];
+    buf2 = state[0];
+    buf3 = state[0]^state[1]; buf3=galois_mul2(buf3); state[0] = state[0] ^ buf3 ^ buf1;
+    buf3 = state[1]^state[2]; buf3=galois_mul2(buf3); state[1] = state[1] ^ buf3 ^ buf1;
+    buf3 = state[2]^state[3]; buf3=galois_mul2(buf3); state[2] = state[2] ^ buf3 ^ buf1;
+    buf3 = state[3]^buf2;     buf3=galois_mul2(buf3); state[3] = state[3] ^ buf3 ^ buf1;
+    // col2
+    buf1 = state[4] ^ state[5] ^ state[6] ^ state[7];
+    buf2 = state[4];
+    buf3 = state[4]^state[5]; buf3=galois_mul2(buf3); state[4] = state[4] ^ buf3 ^ buf1;
+    buf3 = state[5]^state[6]; buf3=galois_mul2(buf3); state[5] = state[5] ^ buf3 ^ buf1;
+    buf3 = state[6]^state[7]; buf3=galois_mul2(buf3); state[6] = state[6] ^ buf3 ^ buf1;
+    buf3 = state[7]^buf2;     buf3=galois_mul2(buf3); state[7] = state[7] ^ buf3 ^ buf1;
+    // col3
+    buf1 = state[8] ^ state[9] ^ state[10] ^ state[11];
+    buf2 = state[8];
+    buf3 = state[8]^state[9];   buf3=galois_mul2(buf3); state[8] = state[8] ^ buf3 ^ buf1;
+    buf3 = state[9]^state[10];  buf3=galois_mul2(buf3); state[9] = state[9] ^ buf3 ^ buf1;
+    buf3 = state[10]^state[11]; buf3=galois_mul2(buf3); state[10] = state[10] ^ buf3 ^ buf1;
+    buf3 = state[11]^buf2;      buf3=galois_mul2(buf3); state[11] = state[11] ^ buf3 ^ buf1;
+    // col4
+    buf1 = state[12] ^ state[13] ^ state[14] ^ state[15];
+    buf2 = state[12];
+    buf3 = state[12]^state[13]; buf3=galois_mul2(buf3); state[12] = state[12] ^ buf3 ^ buf1;
+    buf3 = state[13]^state[14]; buf3=galois_mul2(buf3); state[13] = state[13] ^ buf3 ^ buf1;
+    buf3 = state[14]^state[15]; buf3=galois_mul2(buf3); state[14] = state[14] ^ buf3 ^ buf1;
+    buf3 = state[15]^buf2;      buf3=galois_mul2(buf3); state[15] = state[15] ^ buf3 ^ buf1;
+
+  }
+  // 10th round without mixcols
+  state[ 0]  = sbox[(state[ 0] ^ expanded_key[(round*16)     ])];
+  state[ 4]  = sbox[(state[ 4] ^ expanded_key[(round*16) +  4])];
+  state[ 8]  = sbox[(state[ 8] ^ expanded_key[(round*16) +  8])];
+  state[12]  = sbox[(state[12] ^ expanded_key[(round*16) + 12])];
+  // row 1
+  buf1 = state[1] ^ expanded_key[(round*16) + 1];
+  state[ 1]  = sbox[(state[ 5] ^ expanded_key[(round*16) +  5])];
+  state[ 5]  = sbox[(state[ 9] ^ expanded_key[(round*16) +  9])];
+  state[ 9]  = sbox[(state[13] ^ expanded_key[(round*16) + 13])];
+  state[13]  = sbox[buf1];
+  // row 2
+  buf1 = state[2] ^ expanded_key[(round*16) + 2];
+  buf2 = state[6] ^ expanded_key[(round*16) + 6];
+  state[ 2]  = sbox[(state[10] ^ expanded_key[(round*16) + 10])];
+  state[ 6]  = sbox[(state[14] ^ expanded_key[(round*16) + 14])];
+  state[10]  = sbox[buf1];
+  state[14]  = sbox[buf2];
+  // row 3
+  buf1 = state[15] ^ expanded_key[(round*16) + 15];
+  state[15]  = sbox[(state[11] ^ expanded_key[(round*16) + 11])];
+  state[11]  = sbox[(state[ 7] ^ expanded_key[(round*16) +  7])];
+  state[ 7]  = sbox[(state[ 3] ^ expanded_key[(round*16) +  3])];
+  state[ 3]  = sbox[buf1];
+  // last addroundkey
+  state[ 0]^=expanded_key[160];
+  state[ 1]^=expanded_key[161];
+  state[ 2]^=expanded_key[162];
+  state[ 3]^=expanded_key[163];
+  state[ 4]^=expanded_key[164];
+  state[ 5]^=expanded_key[165];
+  state[ 6]^=expanded_key[166];
+  state[ 7]^=expanded_key[167];
+  state[ 8]^=expanded_key[168];
+  state[ 9]^=expanded_key[169];
+  state[10]^=expanded_key[170];
+  state[11]^=expanded_key[171];
+  state[12]^=expanded_key[172];
+  state[13]^=expanded_key[173];
+  state[14]^=expanded_key[174];
+  state[15]^=expanded_key[175];
+}
+
+void cc3000_security::aes_decr(uint8_t *state, uint8_t *expanded_key) {
+  uint8_t buf1, buf2, buf3;
+  int8_t round;
+  round = 9;
+
+  // initial addroundkey
+  state[ 0]^=expanded_key[160];
+  state[ 1]^=expanded_key[161];
+  state[ 2]^=expanded_key[162];
+  state[ 3]^=expanded_key[163];
+  state[ 4]^=expanded_key[164];
+  state[ 5]^=expanded_key[165];
+  state[ 6]^=expanded_key[166];
+  state[ 7]^=expanded_key[167];
+  state[ 8]^=expanded_key[168];
+  state[ 9]^=expanded_key[169];
+  state[10]^=expanded_key[170];
+  state[11]^=expanded_key[171];
+  state[12]^=expanded_key[172];
+  state[13]^=expanded_key[173];
+  state[14]^=expanded_key[174];
+  state[15]^=expanded_key[175];
+
+  // 10th round without mixcols
+  state[ 0]  = rsbox[state[ 0]] ^ expanded_key[(round*16)     ];
+  state[ 4]  = rsbox[state[ 4]] ^ expanded_key[(round*16) +  4];
+  state[ 8]  = rsbox[state[ 8]] ^ expanded_key[(round*16) +  8];
+  state[12]  = rsbox[state[12]] ^ expanded_key[(round*16) + 12];
+  // row 1
+  buf1 =       rsbox[state[13]] ^ expanded_key[(round*16) +  1];
+  state[13]  = rsbox[state[ 9]] ^ expanded_key[(round*16) + 13];
+  state[ 9]  = rsbox[state[ 5]] ^ expanded_key[(round*16) +  9];
+  state[ 5]  = rsbox[state[ 1]] ^ expanded_key[(round*16) +  5];
+  state[ 1]  = buf1;
+  // row 2
+  buf1 =       rsbox[state[ 2]] ^ expanded_key[(round*16) + 10];
+  buf2 =       rsbox[state[ 6]] ^ expanded_key[(round*16) + 14];
+  state[ 2]  = rsbox[state[10]] ^ expanded_key[(round*16) +  2];
+  state[ 6]  = rsbox[state[14]] ^ expanded_key[(round*16) +  6];
+  state[10]  = buf1;
+  state[14]  = buf2;
+  // row 3
+  buf1 =       rsbox[state[ 3]] ^ expanded_key[(round*16) + 15];
+  state[ 3]  = rsbox[state[ 7]] ^ expanded_key[(round*16) +  3];
+  state[ 7]  = rsbox[state[11]] ^ expanded_key[(round*16) +  7];
+  state[11]  = rsbox[state[15]] ^ expanded_key[(round*16) + 11];
+  state[15]  = buf1;
+
+  for (round = 8; round >= 0; round--)
+  {
+    // barreto
+    //col1
+    buf1 = galois_mul2(galois_mul2(state[0]^state[2]));
+    buf2 = galois_mul2(galois_mul2(state[1]^state[3]));
+    state[0] ^= buf1;     state[1] ^= buf2;    state[2] ^= buf1;    state[3] ^= buf2;
+    //col2
+    buf1 = galois_mul2(galois_mul2(state[4]^state[6]));
+    buf2 = galois_mul2(galois_mul2(state[5]^state[7]));
+    state[4] ^= buf1;    state[5] ^= buf2;    state[6] ^= buf1;    state[7] ^= buf2;
+    //col3
+    buf1 = galois_mul2(galois_mul2(state[8]^state[10]));
+    buf2 = galois_mul2(galois_mul2(state[9]^state[11]));
+    state[8] ^= buf1;    state[9] ^= buf2;    state[10] ^= buf1;    state[11] ^= buf2;
+    //col4
+    buf1 = galois_mul2(galois_mul2(state[12]^state[14]));
+    buf2 = galois_mul2(galois_mul2(state[13]^state[15]));
+    state[12] ^= buf1;    state[13] ^= buf2;    state[14] ^= buf1;    state[15] ^= buf2;
+    // mixcolums //////////
+    // col1
+    buf1 = state[0] ^ state[1] ^ state[2] ^ state[3];
+    buf2 = state[0];
+    buf3 = state[0]^state[1]; buf3=galois_mul2(buf3); state[0] = state[0] ^ buf3 ^ buf1;
+    buf3 = state[1]^state[2]; buf3=galois_mul2(buf3); state[1] = state[1] ^ buf3 ^ buf1;
+    buf3 = state[2]^state[3]; buf3=galois_mul2(buf3); state[2] = state[2] ^ buf3 ^ buf1;
+    buf3 = state[3]^buf2;     buf3=galois_mul2(buf3); state[3] = state[3] ^ buf3 ^ buf1;
+    // col2
+    buf1 = state[4] ^ state[5] ^ state[6] ^ state[7];
+    buf2 = state[4];
+    buf3 = state[4]^state[5]; buf3=galois_mul2(buf3); state[4] = state[4] ^ buf3 ^ buf1;
+    buf3 = state[5]^state[6]; buf3=galois_mul2(buf3); state[5] = state[5] ^ buf3 ^ buf1;
+    buf3 = state[6]^state[7]; buf3=galois_mul2(buf3); state[6] = state[6] ^ buf3 ^ buf1;
+    buf3 = state[7]^buf2;     buf3=galois_mul2(buf3); state[7] = state[7] ^ buf3 ^ buf1;
+    // col3
+    buf1 = state[8] ^ state[9] ^ state[10] ^ state[11];
+    buf2 = state[8];
+    buf3 = state[8]^state[9];   buf3=galois_mul2(buf3); state[8] = state[8] ^ buf3 ^ buf1;
+    buf3 = state[9]^state[10];  buf3=galois_mul2(buf3); state[9] = state[9] ^ buf3 ^ buf1;
+    buf3 = state[10]^state[11]; buf3=galois_mul2(buf3); state[10] = state[10] ^ buf3 ^ buf1;
+    buf3 = state[11]^buf2;      buf3=galois_mul2(buf3); state[11] = state[11] ^ buf3 ^ buf1;
+    // col4
+    buf1 = state[12] ^ state[13] ^ state[14] ^ state[15];
+    buf2 = state[12];
+    buf3 = state[12]^state[13]; buf3=galois_mul2(buf3); state[12] = state[12] ^ buf3 ^ buf1;
+    buf3 = state[13]^state[14]; buf3=galois_mul2(buf3); state[13] = state[13] ^ buf3 ^ buf1;
+    buf3 = state[14]^state[15]; buf3=galois_mul2(buf3); state[14] = state[14] ^ buf3 ^ buf1;
+    buf3 = state[15]^buf2;      buf3=galois_mul2(buf3); state[15] = state[15] ^ buf3 ^ buf1;
+
+    // addroundkey, rsbox and shiftrows
+    // row 0
+    state[ 0]  = rsbox[state[ 0]] ^ expanded_key[(round*16)     ];
+    state[ 4]  = rsbox[state[ 4]] ^ expanded_key[(round*16) +  4];
+    state[ 8]  = rsbox[state[ 8]] ^ expanded_key[(round*16) +  8];
+    state[12]  = rsbox[state[12]] ^ expanded_key[(round*16) + 12];
+    // row 1
+    buf1 =       rsbox[state[13]] ^ expanded_key[(round*16) +  1];
+    state[13]  = rsbox[state[ 9]] ^ expanded_key[(round*16) + 13];
+    state[ 9]  = rsbox[state[ 5]] ^ expanded_key[(round*16) +  9];
+    state[ 5]  = rsbox[state[ 1]] ^ expanded_key[(round*16) +  5];
+    state[ 1]  = buf1;
+    // row 2
+    buf1 =       rsbox[state[ 2]] ^ expanded_key[(round*16) + 10];
+    buf2 =       rsbox[state[ 6]] ^ expanded_key[(round*16) + 14];
+    state[ 2]  = rsbox[state[10]] ^ expanded_key[(round*16) +  2];
+    state[ 6]  = rsbox[state[14]] ^ expanded_key[(round*16) +  6];
+    state[10]  = buf1;
+    state[14]  = buf2;
+    // row 3
+    buf1 =       rsbox[state[ 3]] ^ expanded_key[(round*16) + 15];
+    state[ 3]  = rsbox[state[ 7]] ^ expanded_key[(round*16) +  3];
+    state[ 7]  = rsbox[state[11]] ^ expanded_key[(round*16) +  7];
+    state[11]  = rsbox[state[15]] ^ expanded_key[(round*16) + 11];
+    state[15]  = buf1;
+  }
+}
+
+void cc3000_security::aes_encrypt(uint8_t *state, uint8_t *key) {
+    // expand the key into 176 bytes
+    expandKey(_expanded_key, key);
+    aes_encr(state, _expanded_key);
+}
+
+void cc3000_security::aes_decrypt(uint8_t *state, uint8_t *key) {
+    expandKey(_expanded_key, key);       // expand the key into 176 bytes
+    aes_decr(state, _expanded_key);
+}
+
+int32_t cc3000_security::aes_read_key(uint8_t *key) {
+    int32_t returnValue;
+
+    returnValue = nvmem_read(NVMEM_AES128_KEY_FILEID, AES128_KEY_SIZE, 0, key);
+
+    return returnValue;
+}
+
+int32_t cc3000_security::aes_write_key(uint8_t *key) {
+    int32_t    returnValue;
+
+    returnValue = nvmem_write(NVMEM_AES128_KEY_FILEID, AES128_KEY_SIZE, 0, key);
+
+    return returnValue;
+}
+#endif
+
+} // mbed_cc3000 namespace
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/cc3000_simplelink.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,171 @@
+/*****************************************************************************
+*
+*  C++ interface/implementation created by Martin Kojtal (0xc0170). Thanks to
+*  Jim Carver and Frank Vannieuwkerke for their inital cc3000 mbed port and
+*  provided help.
+*
+*  This version of "host driver" uses CC3000 Host Driver Implementation. Thus
+*  read the following copyright:
+*
+*  Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*****************************************************************************/
+#include "cc3000.h"
+#include "cc3000_common.h"
+
+namespace mbed_cc3000 {
+
+cc3000_simple_link::cc3000_simple_link() {
+    _rx_buffer[CC3000_RX_BUFFER_SIZE - 1] = CC3000_BUFFER_MAGIC_NUMBER;
+    _tx_buffer[CC3000_TX_BUFFER_SIZE - 1] = CC3000_BUFFER_MAGIC_NUMBER;
+}
+
+cc3000_simple_link::~cc3000_simple_link() {
+}
+
+uint8_t cc3000_simple_link::get_data_received_flag() {
+    return _data_received_flag;
+}
+
+void *cc3000_simple_link::get_func_pointer(FunctionNumber function){
+    void *result;
+    /* casting to void *, will be casted back once used */
+    switch(function) {
+        case FW_PATCHES:
+            result = (void *)_fFWPatches;
+            break;
+        case DRIVER_PATCHES:
+            result = (void *)_fDriverPatches;
+            break;
+        case BOOTLOADER_PATCHES:
+            result = (void *)_fBootLoaderPatches;
+            break;
+        default:
+            result = 0;
+         }
+         return result;
+}
+
+uint8_t* cc3000_simple_link::get_transmit_buffer() {
+    return _tx_buffer;
+}
+
+uint8_t* cc3000_simple_link::get_received_buffer() {
+    return _rx_buffer;
+}
+
+void cc3000_simple_link::set_op_code(uint16_t code) {
+    _rx_event_opcode = code;
+}
+
+void cc3000_simple_link::set_pending_data(uint16_t value) {
+    _rx_data_pending = value;
+}
+
+uint16_t cc3000_simple_link::get_pending_data() {
+    return _rx_data_pending;
+}
+
+void cc3000_simple_link::set_number_free_buffers(uint16_t value) {
+    _free_buffers = value;
+}
+
+void cc3000_simple_link::set_number_of_released_packets(uint16_t value) {
+    _released_packets = value;
+}
+
+
+void cc3000_simple_link::set_tx_complete_signal(bool value) {
+    _tx_complete_signal = value;
+}
+
+bool cc3000_simple_link::get_tx_complete_signal() {
+    return _tx_complete_signal;
+}
+
+void cc3000_simple_link::set_data_received_flag(uint8_t value) {
+    _data_received_flag = value;
+}
+
+uint16_t cc3000_simple_link::get_number_free_buffers() {
+    return _free_buffers;
+}
+
+uint16_t cc3000_simple_link::get_buffer_length() {
+    return _buffer_length;
+}
+
+void cc3000_simple_link::set_buffer_length(uint16_t value) {
+    _buffer_length = value;
+}
+
+uint16_t cc3000_simple_link::get_op_code() {
+    return _rx_event_opcode;
+}
+
+uint16_t cc3000_simple_link::get_released_packets() {
+    return _released_packets;
+}
+
+uint16_t cc3000_simple_link::get_sent_packets() {
+    return _sent_packets;
+}
+
+void cc3000_simple_link::set_sent_packets(uint16_t value) {
+    _sent_packets = value;
+}
+
+void cc3000_simple_link::set_transmit_error(int32_t value){
+    _transmit_data_error = value;
+}
+
+int32_t cc3000_simple_link::get_transmit_error(){
+    return _transmit_data_error;
+}
+
+void cc3000_simple_link::set_buffer_size(uint16_t value) {
+    _buffer_size = value;
+}
+
+uint16_t cc3000_simple_link::get_buffer_size(void) {
+    return _buffer_size;
+}
+
+uint8_t *cc3000_simple_link::get_received_data(void) {
+    return _received_data;
+}
+
+void cc3000_simple_link::set_received_data(uint8_t *pointer) {
+    _received_data = pointer;
+}
+
+} // mbed_cc3000 namespace
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/cc3000_simplelink.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,49 @@
+/*****************************************************************************
+*
+*  C++ interface/implementation created by Martin Kojtal (0xc0170). Thanks to
+*  Jim Carver and Frank Vannieuwkerke for their inital cc3000 mbed port and
+*  provided help.
+*
+*  This version of "host driver" uses CC3000 Host Driver Implementation. Thus
+*  read the following copyright:
+*
+*  Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*****************************************************************************/
+#ifndef CC3000_SIMPLELINK_H
+#define CC3000_SIMPLELINK_H
+
+typedef uint8_t *(*tFWPatches)(uint32_t *usLength);
+typedef uint8_t *(*tDriverPatches)(uint32_t *usLength);
+typedef uint8_t *(*tBootLoaderPatches)(uint32_t *usLength);
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/cc3000_socket.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,605 @@
+/*****************************************************************************
+*
+*  C++ interface/implementation created by Martin Kojtal (0xc0170). Thanks to
+*  Jim Carver and Frank Vannieuwkerke for their inital cc3000 mbed port and
+*  provided help.
+*
+*  This version of "host driver" uses CC3000 Host Driver Implementation. Thus
+*  read the following copyright:
+*
+*  Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*****************************************************************************/
+#include "cc3000.h"
+#include "cc3000_socket.h"
+#include "cc3000_event.h" //TODO - remove this
+#include "cc3000_common.h"
+
+namespace mbed_cc3000 {
+
+cc3000_socket::cc3000_socket(cc3000_simple_link &simplelink, cc3000_hci &hci, cc3000_event &event)
+    : _simple_link(simplelink), _hci(hci), _event(event) {
+
+}
+
+cc3000_socket::~cc3000_socket() {
+
+}
+
+int32_t cc3000_socket::HostFlowControlConsumeBuff(int32_t sd) {
+#ifndef SEND_NON_BLOCKING
+    /* wait in busy loop */
+    do {
+        // When the last transmission failed, return the last failure reason.
+        // Note that the buffer will not be allocated in this case
+        if (_simple_link.get_transmit_error() != 0) {
+            errno = _simple_link.get_transmit_error();
+            _simple_link.set_transmit_error(0);
+            return errno;
+        }
+
+        if(SOCKET_STATUS_ACTIVE != _event.get_socket_active_status(sd))
+            return -1;
+    } while (0 == _simple_link.get_number_free_buffers());
+
+    uint16_t free_buffer = _simple_link.get_number_free_buffers();
+    free_buffer--;
+    _simple_link.set_number_free_buffers(free_buffer);
+
+    return 0;
+#else
+
+    // When the last transmission failed, return the last failure reason.
+    // Note that the buffer will not be allocated in this case
+    if (_simple_link.get_transmit_error() != 0) {
+        errno = _simple_link.get_transmit_error();
+        _simple_link.set_transmit_error(0);
+        return errno;
+    }
+    if (SOCKET_STATUS_ACTIVE != _event.get_socket_active_status(sd))
+        return -1;
+
+    // If there are no available buffers, return -2. It is recommended to use
+    // select or receive to see if there is any buffer occupied with received data
+    // If so, call receive() to release the buffer.
+    if (0 == _simple_link.get_number_free_buffers()) {
+        return -2;
+    } else {
+        uint16_t free_buffer = _simple_link.get_number_free_buffers();
+        free_buffer--;
+        _simple_link.set_number_free_buffers(free_buffer);
+        return 0;
+    }
+#endif
+}
+
+int32_t cc3000_socket::socket(int32_t domain, int32_t type, int32_t protocol) {
+    int32_t ret;
+    uint8_t *ptr, *args;
+
+    ret = EFAIL;
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_CMD);
+
+    // Fill in HCI packet structure
+    args = UINT32_TO_STREAM(args, domain);
+    args = UINT32_TO_STREAM(args, type);
+    args = UINT32_TO_STREAM(args, protocol);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_SOCKET, ptr, SOCKET_OPEN_PARAMS_LEN);
+
+    // Since we are in blocking state - wait for event complete
+    _event.simplelink_wait_event(HCI_CMND_SOCKET, &ret);
+
+    // Process the event
+    errno = ret;
+
+    _event.set_socket_active_status(ret, SOCKET_STATUS_ACTIVE);
+
+    return ret;
+}
+
+int32_t cc3000_socket::closesocket(int32_t sd) {
+    int32_t ret;
+    uint8_t *ptr, *args;
+
+    while (_simple_link.get_number_free_buffers() != SOCKET_MAX_FREE_BUFFERS);
+    ret = EFAIL;
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_CMD);
+
+    // Fill in HCI packet structure
+    args = UINT32_TO_STREAM(args, sd);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_CLOSE_SOCKET, ptr, SOCKET_CLOSE_PARAMS_LEN);
+
+    // Since we are in blocking state - wait for event complete
+    _event.simplelink_wait_event(HCI_CMND_CLOSE_SOCKET, &ret);
+    errno = ret;
+
+    // since 'close' call may result in either OK (and then it closed) or error, mark this socket as invalid
+    _event.set_socket_active_status(sd, SOCKET_STATUS_INACTIVE);
+
+    return ret;
+}
+
+int32_t cc3000_socket::accept(int32_t sd, sockaddr *addr, socklen_t *addrlen) {
+    int32_t ret;
+    uint8_t *ptr, *args;
+    tBsdReturnParams tAcceptReturnArguments;
+
+    ret = EFAIL;
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_CMD);
+
+    // Fill in temporary command buffer
+    args = UINT32_TO_STREAM(args, sd);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_ACCEPT, ptr, SOCKET_ACCEPT_PARAMS_LEN);
+
+    // Since we are in blocking state - wait for event complete
+    _event.simplelink_wait_event(HCI_CMND_ACCEPT, &tAcceptReturnArguments);
+
+
+    // need specify return parameters!!!
+    memcpy(addr, &tAcceptReturnArguments.tSocketAddress, ASIC_ADDR_LEN);
+    *addrlen = ASIC_ADDR_LEN;
+    errno = tAcceptReturnArguments.iStatus;
+    ret = errno;
+
+    // if succeeded, iStatus = new socket descriptor. otherwise - error number
+    if(M_IS_VALID_SD(ret)) {
+        _event.set_socket_active_status(ret, SOCKET_STATUS_ACTIVE);
+    } else {
+        _event.set_socket_active_status(sd, SOCKET_STATUS_INACTIVE);
+    }
+
+    return ret;
+}
+
+int32_t cc3000_socket::bind(int32_t sd, const sockaddr *addr, int32_t addrlen) {
+    int32_t ret;
+    uint8_t *ptr, *args;
+
+    ret = EFAIL;
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_CMD);
+
+    addrlen = ASIC_ADDR_LEN;
+
+    // Fill in temporary command buffer
+    args = UINT32_TO_STREAM(args, sd);
+    args = UINT32_TO_STREAM(args, 0x00000008);
+    args = UINT32_TO_STREAM(args, addrlen);
+    ARRAY_TO_STREAM(args, ((uint8_t *)addr), addrlen);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_BIND, ptr, SOCKET_BIND_PARAMS_LEN);
+
+    // Since we are in blocking state - wait for event complete
+    _event.simplelink_wait_event(HCI_CMND_BIND, &ret);
+
+    errno = ret;
+
+    return ret;
+}
+
+int32_t cc3000_socket::listen(int32_t sd, int32_t backlog) {
+    int32_t ret;
+    uint8_t *ptr, *args;
+
+    ret = EFAIL;
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_CMD);
+
+    // Fill in temporary command buffer
+    args = UINT32_TO_STREAM(args, sd);
+    args = UINT32_TO_STREAM(args, backlog);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_LISTEN, ptr, SOCKET_LISTEN_PARAMS_LEN);
+
+    // Since we are in blocking state - wait for event complete
+    _event.simplelink_wait_event(HCI_CMND_LISTEN, &ret);
+    errno = ret;
+
+    return(ret);
+}
+
+int32_t cc3000_socket::connect(int32_t sd, const sockaddr *addr, int32_t addrlen) {
+    int32_t ret;
+    uint8_t *ptr, *args;
+
+    ret = EFAIL;
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + SIMPLE_LINK_HCI_CMND_TRANSPORT_HEADER_SIZE);
+    addrlen = 8;
+
+    // Fill in temporary command buffer
+    args = UINT32_TO_STREAM(args, sd);
+    args = UINT32_TO_STREAM(args, 0x00000008);
+    args = UINT32_TO_STREAM(args, addrlen);
+    ARRAY_TO_STREAM(args, ((uint8_t *)addr), addrlen);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_CONNECT, ptr, SOCKET_CONNECT_PARAMS_LEN);
+
+    // Since we are in blocking state - wait for event complete
+    _event.simplelink_wait_event(HCI_CMND_CONNECT, &ret);
+
+    errno = ret;
+
+    return((int32_t)ret);
+}
+
+int32_t cc3000_socket::select(int32_t nfds, fd_set *readsds, fd_set *writesds, fd_set *exceptsds, struct timeval *timeout) {
+    uint8_t *ptr, *args;
+    tBsdSelectRecvParams tParams;
+    uint32_t is_blocking;
+
+    if (timeout == NULL) {
+        is_blocking = 1; /* blocking , infinity timeout */
+    } else {
+        is_blocking = 0; /* no blocking, timeout */
+    }
+
+    // Fill in HCI packet structure
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_CMD);
+
+    // Fill in temporary command buffer
+    args = UINT32_TO_STREAM(args, nfds);
+    args = UINT32_TO_STREAM(args, 0x00000014);
+    args = UINT32_TO_STREAM(args, 0x00000014);
+    args = UINT32_TO_STREAM(args, 0x00000014);
+    args = UINT32_TO_STREAM(args, 0x00000014);
+    args = UINT32_TO_STREAM(args, is_blocking);
+    args = UINT32_TO_STREAM(args, ((readsds) ? *(uint32_t*)readsds : 0));
+    args = UINT32_TO_STREAM(args, ((writesds) ? *(uint32_t*)writesds : 0));
+    args = UINT32_TO_STREAM(args, ((exceptsds) ? *(uint32_t*)exceptsds : 0));
+
+    if (timeout) {
+        if ( 0 == timeout->tv_sec && timeout->tv_usec < SELECT_TIMEOUT_MIN_MICRO_SECONDS) {
+            timeout->tv_usec = SELECT_TIMEOUT_MIN_MICRO_SECONDS;
+        }
+        args = UINT32_TO_STREAM(args, timeout->tv_sec);
+        args = UINT32_TO_STREAM(args, timeout->tv_usec);
+    }
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_BSD_SELECT, ptr, SOCKET_SELECT_PARAMS_LEN);
+
+    // Since we are in blocking state - wait for event complete
+    _event.simplelink_wait_event(HCI_EVNT_SELECT, &tParams);
+
+    // Update actually read FD
+    if (tParams.iStatus >= 0) {
+        if (readsds) {
+            memcpy(readsds, &tParams.uiRdfd, sizeof(tParams.uiRdfd));
+        }
+
+        if (writesds) {
+            memcpy(writesds, &tParams.uiWrfd, sizeof(tParams.uiWrfd));
+        }
+
+        if (exceptsds) {
+            memcpy(exceptsds, &tParams.uiExfd, sizeof(tParams.uiExfd));
+        }
+
+        return(tParams.iStatus);
+
+    } else {
+        errno = tParams.iStatus;
+        return -1;
+    }
+}
+
+int32_t cc3000_socket::getsockopt (int32_t sd, int32_t level, int32_t optname, void *optval, socklen_t *optlen) {
+    uint8_t *ptr, *args;
+    tBsdGetSockOptReturnParams  tRetParams;
+
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_CMD);
+
+    // Fill in temporary command buffer
+    args = UINT32_TO_STREAM(args, sd);
+    args = UINT32_TO_STREAM(args, level);
+    args = UINT32_TO_STREAM(args, optname);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_GETSOCKOPT, ptr, SOCKET_GET_SOCK_OPT_PARAMS_LEN);
+
+    // Since we are in blocking state - wait for event complete
+    _event.simplelink_wait_event(HCI_CMND_GETSOCKOPT, &tRetParams);
+
+    if (((int8_t)tRetParams.iStatus) >= 0) {
+        *optlen = 4;
+        memcpy(optval, tRetParams.ucOptValue, 4);
+        return (0);
+    } else {
+        errno = tRetParams.iStatus;
+        return errno;
+    }
+}
+
+int32_t cc3000_socket::simple_link_recv(int32_t sd, void *buf, int32_t len, int32_t flags, sockaddr *from, socklen_t *fromlen, int32_t opcode) {
+    uint8_t *ptr, *args;
+    tBsdReadReturnParams tSocketReadEvent;
+
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_CMD);
+
+    // Fill in HCI packet structure
+    args = UINT32_TO_STREAM(args, sd);
+    args = UINT32_TO_STREAM(args, len);
+    args = UINT32_TO_STREAM(args, flags);
+
+    // Generate the read command, and wait for the
+    _hci.command_send(opcode,  ptr, SOCKET_RECV_FROM_PARAMS_LEN);
+
+    // Since we are in blocking state - wait for event complete
+    _event.simplelink_wait_event(opcode, &tSocketReadEvent);
+
+    // In case the number of bytes is more then zero - read data
+    if (tSocketReadEvent.iNumberOfBytes > 0) {
+        // Wait for the data in a synchronous way. Here we assume that the bug is
+        // big enough to store also parameters of receive from too....
+        _event.simplelink_wait_data((uint8_t *)buf, (uint8_t *)from, (uint8_t *)fromlen);
+    }
+
+    errno = tSocketReadEvent.iNumberOfBytes;
+
+    return(tSocketReadEvent.iNumberOfBytes);
+}
+
+int32_t cc3000_socket::recv(int32_t sd, void *buf, int32_t len, int32_t flags) {
+    return(simple_link_recv(sd, buf, len, flags, NULL, NULL, HCI_CMND_RECV));
+}
+
+int32_t cc3000_socket::recvfrom(int32_t sd, void *buf, int32_t len, int32_t flags, sockaddr *from, socklen_t *fromlen) {
+    return(simple_link_recv(sd, buf, len, flags, from, fromlen, HCI_CMND_RECVFROM));
+}
+
+int32_t cc3000_socket::simple_link_send(int32_t sd, const void *buf, int32_t len, int32_t flags, const sockaddr *to, int32_t tolen, int32_t opcode) {
+    uint8_t uArgSize = 0x00,  addrlen = 0x00;
+    uint8_t *ptr, *pDataPtr = NULL, *args;
+    uint32_t addr_offset = 0x00;
+    int32_t res;
+    tBsdReadReturnParams tSocketSendEvent;
+
+    // Check the bsd_arguments
+    if (0 != (res = HostFlowControlConsumeBuff(sd))) {
+        return res;
+    }
+
+    //Update the number of sent packets
+    uint16_t sent_packets = _simple_link.get_sent_packets();
+    sent_packets++;
+    _simple_link.set_sent_packets(sent_packets);
+
+    // Allocate a buffer and construct a packet and send it over spi
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_DATA);
+
+    // Update the offset of data and parameters according to the command
+    switch(opcode)
+    {
+        case HCI_CMND_SENDTO:
+        {
+            addr_offset = len + sizeof(len) + sizeof(len);
+            addrlen = 8;
+            uArgSize = SOCKET_SENDTO_PARAMS_LEN;
+            pDataPtr = ptr + HEADERS_SIZE_DATA + SOCKET_SENDTO_PARAMS_LEN;
+            break;
+        }
+
+        case HCI_CMND_SEND:
+        {
+            tolen = 0;
+            to = NULL;
+            uArgSize = HCI_CMND_SEND_ARG_LENGTH;
+            pDataPtr = ptr + HEADERS_SIZE_DATA + HCI_CMND_SEND_ARG_LENGTH;
+            break;
+        }
+
+        default:
+        {
+            break;
+        }
+    }
+
+    // Fill in temporary command buffer
+    args = UINT32_TO_STREAM(args, sd);
+    args = UINT32_TO_STREAM(args, uArgSize - sizeof(sd));
+    args = UINT32_TO_STREAM(args, len);
+    args = UINT32_TO_STREAM(args, flags);
+
+    if (opcode == HCI_CMND_SENDTO) {
+        args = UINT32_TO_STREAM(args, addr_offset);
+        args = UINT32_TO_STREAM(args, addrlen);
+    }
+
+    // Copy the data received from user into the TX Buffer
+    ARRAY_TO_STREAM(pDataPtr, ((uint8_t *)buf), len);
+
+    // In case we are using SendTo, copy the to parameters
+    if (opcode == HCI_CMND_SENDTO) {
+        ARRAY_TO_STREAM(pDataPtr, ((uint8_t *)to), tolen);
+    }
+
+    // Initiate a HCI command
+    _hci.data_send(opcode, ptr, uArgSize, len,(uint8_t*)to, tolen);
+    if (opcode == HCI_CMND_SENDTO)
+       _event.simplelink_wait_event(HCI_EVNT_SENDTO, &tSocketSendEvent);
+    else
+       _event.simplelink_wait_event(HCI_EVNT_SEND, &tSocketSendEvent);
+
+    return (len);
+}
+
+int32_t cc3000_socket::send(int32_t sd, const void *buf, int32_t len, int32_t flags) {
+    return(simple_link_send(sd, buf, len, flags, NULL, 0, HCI_CMND_SEND));
+}
+
+int32_t cc3000_socket::sendto(int32_t sd, const void *buf, int32_t len, int32_t flags, const sockaddr *to, socklen_t tolen) {
+    return(simple_link_send(sd, buf, len, flags, to, tolen, HCI_CMND_SENDTO));
+}
+
+int32_t cc3000_socket::mdns_advertiser(uint16_t mdns_enabled, uint8_t *device_service_name, uint16_t device_service_name_length) {
+    int32_t ret;
+     uint8_t *pTxBuffer, *pArgs;
+
+    if (device_service_name_length > MDNS_DEVICE_SERVICE_MAX_LENGTH) {
+        return EFAIL;
+    }
+
+    pTxBuffer = _simple_link.get_transmit_buffer();
+    pArgs = (pTxBuffer + SIMPLE_LINK_HCI_CMND_TRANSPORT_HEADER_SIZE);
+
+    // Fill in HCI packet structure
+    pArgs = UINT32_TO_STREAM(pArgs, mdns_enabled);
+    pArgs = UINT32_TO_STREAM(pArgs, 8);
+    pArgs = UINT32_TO_STREAM(pArgs, device_service_name_length);
+    ARRAY_TO_STREAM(pArgs, device_service_name, device_service_name_length);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_MDNS_ADVERTISE, pTxBuffer, SOCKET_MDNS_ADVERTISE_PARAMS_LEN + device_service_name_length);
+
+    // Since we are in blocking state - wait for event complete
+    _event.simplelink_wait_event(HCI_EVNT_MDNS_ADVERTISE, &ret);
+
+    return ret;
+}
+
+
+#ifndef CC3000_TINY_DRIVER
+int32_t cc3000_socket::gethostbyname(uint8_t *hostname, uint16_t name_length, uint32_t *out_ip_addr) {
+    tBsdGethostbynameParams ret;
+    uint8_t *ptr, *args;
+
+    errno = EFAIL;
+
+    if (name_length > HOSTNAME_MAX_LENGTH) {
+        return errno;
+    }
+
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + SIMPLE_LINK_HCI_CMND_TRANSPORT_HEADER_SIZE);
+
+    // Fill in HCI packet structure
+    args = UINT32_TO_STREAM(args, 8);
+    args = UINT32_TO_STREAM(args, name_length);
+    ARRAY_TO_STREAM(args, hostname, name_length);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_GETHOSTNAME, ptr, SOCKET_GET_HOST_BY_NAME_PARAMS_LEN + name_length - 1);
+
+    // Since we are in blocking state - wait for event complete
+    _event.simplelink_wait_event(HCI_EVNT_BSD_GETHOSTBYNAME, &ret);
+
+    errno = ret.retVal;
+
+    (*((int32_t*)out_ip_addr)) = ret.outputAddress;
+
+    return (errno);
+}
+
+int32_t cc3000_socket::setsockopt(int32_t sd, int32_t level, int32_t optname, const void *optval, socklen_t optlen) {
+    int32_t ret;
+    uint8_t *ptr, *args;
+
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_CMD);
+
+    // Fill in temporary command buffer
+    args = UINT32_TO_STREAM(args, sd);
+    args = UINT32_TO_STREAM(args, level);
+    args = UINT32_TO_STREAM(args, optname);
+    args = UINT32_TO_STREAM(args, 0x00000008);
+    args = UINT32_TO_STREAM(args, optlen);
+    ARRAY_TO_STREAM(args, ((uint8_t *)optval), optlen);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_SETSOCKOPT, ptr, SOCKET_SET_SOCK_OPT_PARAMS_LEN  + optlen);
+
+    // Since we are in blocking state - wait for event complete
+    _event.simplelink_wait_event(HCI_CMND_SETSOCKOPT, &ret);
+
+    if (ret >= 0) {
+        return (0);
+    } else {
+        errno = ret;
+        return ret;
+    }
+}
+
+#endif
+
+char* cc3000_socket::inet_ntoa_r(uint32_t s_addr, char *buf, int buflen)
+{
+    char inv[3];
+    char *rp;
+    uint8_t *ap;
+    uint8_t rem;
+    uint8_t n;
+    uint8_t i;
+    int len = 0;
+
+    rp = buf;
+    ap = (uint8_t *)&s_addr;
+    for (n = 0; n < 4; n++) {
+        i = 0;
+        do {
+            rem = *ap % (uint8_t)10;
+            *ap /= (uint8_t)10;
+            inv[i++] = '0' + rem;
+        } while(*ap);
+        while(i--) {
+            if (len++ >= buflen) {
+                return NULL;
+            }
+            *rp++ = inv[i];
+        }
+        if (len++ >= buflen) {
+            return NULL;
+        }
+        *rp++ = '.';
+        ap++;
+    }
+    *--rp = 0;
+    return buf;
+}
+
+} // mbed_cc3000 namespace
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/cc3000_socket.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,230 @@
+/*****************************************************************************
+*
+*  C++ interface/implementation created by Martin Kojtal (0xc0170). Thanks to
+*  Jim Carver and Frank Vannieuwkerke for their inital cc3000 mbed port and
+*  provided help.
+*
+*  This version of "host driver" uses CC3000 Host Driver Implementation. Thus
+*  read the following copyright:
+*
+*  Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*****************************************************************************/
+#ifndef CC3000_SOCKET_H
+#define CC3000_SOCKET_H
+
+#define SOCKET_MAX_FREE_BUFFERS    6
+
+#define SOCKET_STATUS_ACTIVE       0
+#define SOCKET_STATUS_INACTIVE     1
+
+#define SOCKET_STATUS_INIT_VAL  0xFFFF
+#define M_IS_VALID_SD(sd) ((0 <= (sd)) && ((sd) <= 7))
+#define M_IS_VALID_STATUS(status) (((status) == SOCKET_STATUS_ACTIVE)||((status) == SOCKET_STATUS_INACTIVE))
+
+#ifdef _API_USE_BSD_CLOSE
+    #define close(sd) closesocket(sd)
+#endif
+
+//Enable this flag if and only if you must comply with BSD socket read() and
+//write() functions
+#ifdef _API_USE_BSD_READ_WRITE
+    #define read(sd, buf, len, flags) recv(sd, buf, len, flags)
+    #define write(sd, buf, len, flags) send(sd, buf, len, flags)
+#endif
+
+#define SOCKET_OPEN_PARAMS_LEN                 (12)
+#define SOCKET_CLOSE_PARAMS_LEN                (4)
+#define SOCKET_ACCEPT_PARAMS_LEN               (4)
+#define SOCKET_BIND_PARAMS_LEN                 (20)
+#define SOCKET_LISTEN_PARAMS_LEN               (8)
+#define SOCKET_GET_HOST_BY_NAME_PARAMS_LEN     (9)
+#define SOCKET_CONNECT_PARAMS_LEN              (20)
+#define SOCKET_SELECT_PARAMS_LEN               (44)
+#define SOCKET_SET_SOCK_OPT_PARAMS_LEN         (20)
+#define SOCKET_GET_SOCK_OPT_PARAMS_LEN         (12)
+#define SOCKET_RECV_FROM_PARAMS_LEN            (12)
+#define SOCKET_SENDTO_PARAMS_LEN               (24)
+#define SOCKET_MDNS_ADVERTISE_PARAMS_LEN       (12)
+
+//#define NULL 0
+
+// The legnth of arguments for the SEND command: sd + buff_offset + len + flags,
+// while size of each parameter is 32 bit - so the total length is 16 bytes;
+
+#define HCI_CMND_SEND_ARG_LENGTH                    (16)
+#define SELECT_TIMEOUT_MIN_MICRO_SECONDS            5000
+#define HEADERS_SIZE_DATA                           (SPI_HEADER_SIZE + 5)
+#define SIMPLE_LINK_HCI_CMND_TRANSPORT_HEADER_SIZE  (SPI_HEADER_SIZE + SIMPLE_LINK_HCI_CMND_HEADER_SIZE)
+#define MDNS_DEVICE_SERVICE_MAX_LENGTH              (32)
+
+
+#define HOSTNAME_MAX_LENGTH (230)  // 230 bytes + header shouldn't exceed 8 bit value
+
+//--------- Address Families --------
+
+#define  AF_INET                2
+#define  AF_INET6               23
+
+//------------ Socket Types ------------
+
+#define  SOCK_STREAM            1
+#define  SOCK_DGRAM             2
+#define  SOCK_RAW               3           // Raw sockets allow new IPv4 protocols to be implemented in user space. A raw socket receives or sends the raw datagram not including link level headers
+#define  SOCK_RDM               4
+#define  SOCK_SEQPACKET         5
+
+//----------- Socket Protocol ----------
+
+#define IPPROTO_IP              0           // dummy for IP
+#define IPPROTO_ICMP            1           // control message protocol
+#define IPPROTO_IPV4            IPPROTO_IP  // IP inside IP
+#define IPPROTO_TCP             6           // tcp
+#define IPPROTO_UDP             17          // user datagram protocol
+#define IPPROTO_IPV6            41          // IPv6 in IPv6
+#define IPPROTO_NONE            59          // No next header
+#define IPPROTO_RAW             255         // raw IP packet
+#define IPPROTO_MAX             256
+
+//----------- Socket retunr codes  -----------
+
+#define SOC_ERROR                (-1)        // error
+#define SOC_IN_PROGRESS          (-2)        // socket in progress
+
+//----------- Socket Options -----------
+#define  SOL_SOCKET             0xffff       //  socket level
+#define  SOCKOPT_RECV_TIMEOUT   1            //  optname to configure recv and recvfromtimeout
+#define  SOCKOPT_NONBLOCK       2            // accept non block mode set SOCK_ON or SOCK_OFF (default block mode )
+#define  SOCK_ON                0            // socket non-blocking mode    is enabled
+#define  SOCK_OFF               1            // socket blocking mode is enabled
+
+#define  TCP_NODELAY            0x0001
+#define  TCP_BSDURGENT          0x7000
+
+#define  MAX_PACKET_SIZE        1500
+#define  MAX_LISTEN_QUEUE       4
+
+#define  IOCTL_SOCKET_EVENTMASK
+
+#define __FD_SETSIZE            32
+
+#define  ASIC_ADDR_LEN          8
+
+#define NO_QUERY_RECIVED        -3
+
+
+typedef struct _in_addr_t
+{
+    uint32_t s_addr;                   // load with inet_aton()
+} in_addr;
+
+/*typedef struct _sockaddr_t
+{
+    unsigned short int  sa_family;
+    unsigned char       sa_data[14];
+} sockaddr;*/
+
+typedef struct _sockaddr_in_t
+{
+    int16_t  sin_family;            // e.g. AF_INET
+    uint16_t sin_port;              // e.g. htons(3490)
+    in_addr  sin_addr;              // see struct in_addr, below
+    uint8_t  sin_zero[8];           // zero this if you want to
+} sockaddr_in;
+
+typedef uint32_t socklen_t;
+
+// The fd_set member is required to be an array of longs.
+typedef int32_t __fd_mask;
+
+// It's easier to assume 8-bit bytes than to get CHAR_BIT.
+#define __NFDBITS               (8 * sizeof (__fd_mask))
+#define __FDELT(d)              ((d) / __NFDBITS)
+#define __FDMASK(d)             ((__fd_mask) 1 << ((d) % __NFDBITS))
+
+#ifndef FD_SET
+//not used in the current code
+#define ENOBUFS                 55          // No buffer space available
+
+// Access macros for 'fd_set'.
+#define FD_SET(fd, fdsetp)      __FD_SET (fd, fdsetp)
+#define FD_CLR(fd, fdsetp)      __FD_CLR (fd, fdsetp)
+#define FD_ISSET(fd, fdsetp)    __FD_ISSET (fd, fdsetp)
+#define FD_ZERO(fdsetp)         __FD_ZERO (fdsetp)
+
+// fd_set for select and pselect.
+typedef struct
+{
+    __fd_mask fds_bits[__FD_SETSIZE / __NFDBITS];
+#define __FDS_BITS(set)        ((set)->fds_bits)
+} fd_set;
+
+#endif /* FD_SET */
+
+// We don't use `memset' because this would require a prototype and
+//   the array isn't too big.
+#define __FD_ZERO(set)                               \
+  do {                                                \
+    uint32_t __i;                                 \
+    fd_set *__arr = (set);                            \
+    for (__i = 0; __i < sizeof (fd_set) / sizeof (__fd_mask); ++__i) \
+      __FDS_BITS (__arr)[__i] = 0;                    \
+  } while (0)
+#define __FD_SET(d, set)       (__FDS_BITS (set)[__FDELT (d)] |= __FDMASK (d))
+#define __FD_CLR(d, set)       (__FDS_BITS (set)[__FDELT (d)] &= ~__FDMASK (d))
+#define __FD_ISSET(d, set)     (__FDS_BITS (set)[__FDELT (d)] & __FDMASK (d))
+
+//Use in case of Big Endian only
+
+#define htonl(A)    ((((uint32_t)(A) & 0xff000000) >> 24) | \
+                     (((uint32_t)(A) & 0x00ff0000) >> 8) | \
+                     (((uint32_t)(A) & 0x0000ff00) << 8) | \
+                     (((uint32_t)(A) & 0x000000ff) << 24))
+
+#define ntohl                   htonl
+
+//Use in case of Big Endian only
+#define htons(A)     ((((uint32_t)(A) & 0xff00) >> 8) | \
+                      (((uint32_t)(A) & 0x00ff) << 8))
+
+
+#define ntohs                   htons
+
+// mDNS port - 5353    mDNS multicast address - 224.0.0.251
+#define SET_mDNS_ADD(sockaddr) sockaddr.sa_data[0] = 0x14; \
+                               sockaddr.sa_data[1] = 0xe9; \
+                               sockaddr.sa_data[2] = 0xe0; \
+                               sockaddr.sa_data[3] = 0x0;  \
+                               sockaddr.sa_data[4] = 0x0;  \
+                               sockaddr.sa_data[5] = 0xfb;
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/cc3000_spi.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,256 @@
+/*****************************************************************************
+*
+*  C++ interface/implementation created by Martin Kojtal (0xc0170). Thanks to
+*  Jim Carver and Frank Vannieuwkerke for their inital cc3000 mbed port and
+*  provided help.
+*
+*  This version of "host driver" uses CC3000 Host Driver Implementation. Thus
+*  read the following copyright:
+*
+*  Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*****************************************************************************/
+#include "cc3000.h"
+#include "cc3000_spi.h"
+
+namespace mbed_cc3000 {
+
+cc3000_spi::cc3000_spi(PinName cc3000_irq, PinName cc3000_en, PinName cc3000_cs, SPI cc3000_spi, cc3000_event &event, cc3000_simple_link &simple_link)
+  : _wlan_irq(cc3000_irq), _wlan_en(cc3000_en), _wlan_cs(cc3000_cs), _wlan_spi(cc3000_spi), _event(event), _simple_link(simple_link) {
+
+    _wlan_spi.format(8,1);
+    _wlan_spi.frequency(12000000);
+    _wlan_irq.fall(this, &cc3000_spi::WLAN_IRQHandler);
+
+    _wlan_en = 0;
+    _wlan_cs = 1;
+    wait_ms(50); /* mbed board delay */
+}
+
+cc3000_spi::~cc3000_spi() {
+
+}
+
+void cc3000_spi::wlan_irq_enable()
+{
+    _process_irq = true;
+    //_wlan_irq.enable_irq();
+
+    if (wlan_irq_read() == 0) {
+        WLAN_IRQHandler();
+    }
+}
+
+void cc3000_spi::wlan_irq_disable() {
+    _process_irq = false;
+    //_wlan_irq.disable_irq();
+}
+
+uint32_t cc3000_spi::wlan_irq_read() {
+    return _wlan_irq.read();
+}
+
+void cc3000_spi::close() {
+    wlan_irq_disable();
+}
+
+void cc3000_spi::open() {
+   _spi_info.spi_state = eSPI_STATE_POWERUP;
+   _spi_info.tx_packet_length = 0;
+   _spi_info.rx_packet_length = 0;
+    wlan_irq_enable();
+}
+
+uint32_t cc3000_spi::first_write(uint8_t *buffer, uint16_t length) {
+    _wlan_cs = 0;
+    wait_us(50);
+
+    /* first 4 bytes of the data */
+    write_synchronous(buffer, 4);
+    wait_us(50);
+    write_synchronous(buffer + 4, length - 4);
+    _spi_info.spi_state = eSPI_STATE_IDLE;
+    _wlan_cs = 1;
+
+    return 0;
+}
+
+
+uint32_t cc3000_spi::write(uint8_t *buffer, uint16_t length) {
+    uint8_t pad = 0;
+    // check the total length of the packet in order to figure out if padding is necessary
+    if(!(length & 0x0001)) {
+      pad++;
+    }
+    buffer[0] = WRITE;
+    buffer[1] = HI(length + pad);
+    buffer[2] = LO(length + pad);
+    buffer[3] = 0;
+    buffer[4] = 0;
+
+    length += (SPI_HEADER_SIZE + pad);
+
+    // The magic number resides at the end of the TX/RX buffer (1 byte after the allocated size)
+    // If the magic number is overwitten - buffer overrun occurred - we will be stuck here forever!
+    uint8_t *transmit_buffer = _simple_link.get_transmit_buffer();
+    if (transmit_buffer[CC3000_TX_BUFFER_SIZE - 1] != CC3000_BUFFER_MAGIC_NUMBER) {
+        while (1);
+    }
+
+    if (_spi_info.spi_state == eSPI_STATE_POWERUP) {
+        while (_spi_info.spi_state != eSPI_STATE_INITIALIZED);
+    }
+
+    if (_spi_info.spi_state == eSPI_STATE_INITIALIZED) {
+        // TX/RX transaction over SPI after powerup: IRQ is low - send read buffer size command
+        first_write(buffer, length);
+    } else {
+        // Prevent occurence of a race condition when 2 back to back packets are sent to the
+        // device, so the state will move to IDLE and once again to not IDLE due to IRQ
+        wlan_irq_disable();
+
+        while (_spi_info.spi_state != eSPI_STATE_IDLE);
+
+        _spi_info.spi_state = eSPI_STATE_WRITE_IRQ;
+        //_spi_info.pTxPacket = buffer;
+        _spi_info.tx_packet_length = length;
+
+        // Assert the CS line and wait until the IRQ line is active, then initialize the write operation
+        _wlan_cs = 0;
+
+        wlan_irq_enable();
+    }
+
+    // Wait until the transaction ends
+    while (_spi_info.spi_state != eSPI_STATE_IDLE);
+
+    return 0;
+}
+
+void cc3000_spi::write_synchronous(uint8_t *data, uint16_t size) {
+    while(size) {
+        _wlan_spi.write(*data++);
+        size--;
+    }
+}
+
+void cc3000_spi::read_synchronous(uint8_t *data, uint16_t size) {
+    for (uint32_t i = 0; i < size; i++) {
+        data[i] = _wlan_spi.write(0x03);
+    }
+}
+
+uint32_t cc3000_spi::read_data_cont() {
+   int32_t data_to_recv;
+   uint8_t *evnt_buff, type;
+
+   //determine the packet type
+   evnt_buff = _simple_link.get_received_buffer();
+   data_to_recv = 0;
+   STREAM_TO_UINT8((uint8_t *)(evnt_buff + SPI_HEADER_SIZE), HCI_PACKET_TYPE_OFFSET, type);
+
+    switch(type) {
+        case HCI_TYPE_DATA:
+            // Read the remaining data..
+            STREAM_TO_UINT16((uint8_t *)(evnt_buff + SPI_HEADER_SIZE), HCI_DATA_LENGTH_OFFSET, data_to_recv);
+            if (!((HEADERS_SIZE_EVNT + data_to_recv) & 1)) {
+               data_to_recv++;
+            }
+
+            if (data_to_recv) {
+               read_synchronous(evnt_buff + 10, data_to_recv);
+            }
+            break;
+        case HCI_TYPE_EVNT:
+            // Calculate the rest length of the data
+            STREAM_TO_UINT8((char *)(evnt_buff + SPI_HEADER_SIZE), HCI_EVENT_LENGTH_OFFSET, data_to_recv);
+            data_to_recv -= 1;
+            // Add padding byte if needed
+            if ((HEADERS_SIZE_EVNT + data_to_recv) & 1) {
+                 data_to_recv++;
+            }
+
+            if (data_to_recv) {
+               read_synchronous(evnt_buff + 10, data_to_recv);
+            }
+
+            _spi_info.spi_state = eSPI_STATE_READ_EOT;
+            break;
+    }
+    return 0;
+}
+
+void cc3000_spi::set_wlan_en(uint8_t value) {
+    if (value) {
+        _wlan_en = 1;
+    } else {
+        _wlan_en = 0;
+    }
+}
+
+void cc3000_spi::WLAN_IRQHandler() {
+    if (_process_irq) {
+        if (_spi_info.spi_state == eSPI_STATE_POWERUP) {
+            // Inform HCI Layer that IRQ occured after powerup
+            _spi_info.spi_state = eSPI_STATE_INITIALIZED;
+        } else if (_spi_info.spi_state == eSPI_STATE_IDLE) {
+            _spi_info.spi_state = eSPI_STATE_READ_IRQ;
+            /* IRQ line goes low - acknowledge it */
+             _wlan_cs = 0;
+            read_synchronous(_simple_link.get_received_buffer(), 10);
+            _spi_info.spi_state = eSPI_STATE_READ_EOT;
+
+            // The header was read - continue with the payload read
+            if (!read_data_cont()) {
+                // All the data was read - finalize handling by switching to the task
+                // Trigger Rx processing
+                wlan_irq_disable();
+                _wlan_cs = 1;
+                // The magic number resides at the end of the TX/RX buffer (1 byte after the allocated size)
+                // If the magic number is overwitten - buffer overrun occurred - we will be stuck here forever!
+                uint8_t *received_buffer = _simple_link.get_received_buffer();
+                if (received_buffer[CC3000_RX_BUFFER_SIZE - 1] != CC3000_BUFFER_MAGIC_NUMBER) {
+                    while (1);
+                }
+
+                _spi_info.spi_state = eSPI_STATE_IDLE;
+                _event.received_handler(received_buffer + SPI_HEADER_SIZE);
+            }
+        } else if (_spi_info.spi_state == eSPI_STATE_WRITE_IRQ) {
+            write_synchronous(_simple_link.get_transmit_buffer(), _spi_info.tx_packet_length);
+            _spi_info.spi_state = eSPI_STATE_IDLE;
+            _wlan_cs = 1;
+        }
+    }
+}
+
+} // namespace mbed_cc3000
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/cc3000_spi.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,252 @@
+/*****************************************************************************
+*
+*  C++ interface/implementation created by Martin Kojtal (0xc0170). Thanks to
+*  Jim Carver and Frank Vannieuwkerke for their inital cc3000 mbed port and
+*  provided help.
+*
+*  This version of "host driver" uses CC3000 Host Driver Implementation. Thus
+*  read the following copyright:
+*
+*  Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*****************************************************************************/
+#ifndef CC3000_SPI_H
+#define CC3000_SPI_H
+
+typedef struct
+{
+   uint16_t tx_packet_length;
+   uint16_t rx_packet_length;
+   uint32_t spi_state;
+} tSpiInfo;
+
+
+/* ===========================================================================================
+                                              SPI
+   =========================================================================================== */
+#define READ                    3
+#define WRITE                   1
+
+#define HI(value)               (((value) & 0xFF00) >> 8)
+#define LO(value)               ((value) & 0x00FF)
+
+#define HEADERS_SIZE_EVNT    (SPI_HEADER_SIZE + 5)
+
+#define SPI_HEADER_SIZE      (5)
+
+#define  eSPI_STATE_POWERUP             (0)
+#define  eSPI_STATE_INITIALIZED         (1)
+#define  eSPI_STATE_IDLE                (2)
+#define  eSPI_STATE_WRITE_IRQ           (3)
+#define  eSPI_STATE_WRITE_FIRST_PORTION (4)
+#define  eSPI_STATE_WRITE_EOT           (5)
+#define  eSPI_STATE_READ_IRQ            (6)
+#define  eSPI_STATE_READ_FIRST_PORTION  (7)
+#define  eSPI_STATE_READ_EOT            (8)
+
+// The magic number that resides at the end of the TX/RX buffer (1 byte after the allocated size)
+// for the purpose of detection of the overrun. The location of the memory where the magic number
+// resides shall never be written. In case it is written - overrun occured and either recevie function
+// or send function will be stuck forever.
+#define CC3000_BUFFER_MAGIC_NUMBER (0xDE)
+
+/* ===========================================================================================
+                                              HCI
+   =========================================================================================== */
+
+#define SL_PATCH_PORTION_SIZE                        (1000)
+
+#define SPI_HEADER_SIZE                              (5)
+#define SIMPLE_LINK_HCI_CMND_HEADER_SIZE             (4)
+#define HEADERS_SIZE_CMD                             (SPI_HEADER_SIZE + SIMPLE_LINK_HCI_CMND_HEADER_SIZE)
+#define SIMPLE_LINK_HCI_DATA_CMND_HEADER_SIZE        (5)
+#define SIMPLE_LINK_HCI_DATA_HEADER_SIZE             (5)
+#define SIMPLE_LINK_HCI_PATCH_HEADER_SIZE            (2)
+
+// Values that can be used as HCI Commands and HCI Packet header defines
+#define  HCI_TYPE_CMND          0x1
+#define  HCI_TYPE_DATA          0x2
+#define  HCI_TYPE_PATCH         0x3
+#define  HCI_TYPE_EVNT          0x4
+
+
+#define HCI_EVENT_PATCHES_DRV_REQ             (1)
+#define HCI_EVENT_PATCHES_FW_REQ              (2)
+#define HCI_EVENT_PATCHES_BOOTLOAD_REQ        (3)
+
+
+#define  HCI_CMND_WLAN_BASE                              (0x0000)
+#define  HCI_CMND_WLAN_CONNECT                            0x0001
+#define  HCI_CMND_WLAN_DISCONNECT                         0x0002
+#define  HCI_CMND_WLAN_IOCTL_SET_SCANPARAM                0x0003
+#define  HCI_CMND_WLAN_IOCTL_SET_CONNECTION_POLICY        0x0004
+#define  HCI_CMND_WLAN_IOCTL_ADD_PROFILE                  0x0005
+#define  HCI_CMND_WLAN_IOCTL_DEL_PROFILE                  0x0006
+#define  HCI_CMND_WLAN_IOCTL_GET_SCAN_RESULTS             0x0007
+#define  HCI_CMND_EVENT_MASK                              0x0008
+#define  HCI_CMND_WLAN_IOCTL_STATUSGET                    0x0009
+#define  HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_START          0x000A
+#define  HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_STOP           0x000B
+#define  HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_SET_PREFIX     0x000C
+#define  HCI_CMND_WLAN_CONFIGURE_PATCH                    0x000D
+
+
+#define  HCI_CMND_SOCKET_BASE          0x1000
+#define  HCI_CMND_SOCKET               0x1001
+#define  HCI_CMND_BIND                 0x1002
+#define  HCI_CMND_RECV                 0x1004
+#define  HCI_CMND_ACCEPT               0x1005
+#define  HCI_CMND_LISTEN               0x1006
+#define  HCI_CMND_CONNECT              0x1007
+#define  HCI_CMND_BSD_SELECT           0x1008
+#define  HCI_CMND_SETSOCKOPT           0x1009
+#define  HCI_CMND_GETSOCKOPT           0x100A
+#define  HCI_CMND_CLOSE_SOCKET         0x100B
+#define  HCI_CMND_RECVFROM             0x100D
+#define  HCI_CMND_GETHOSTNAME          0x1010
+#define  HCI_CMND_MDNS_ADVERTISE       0x1011
+
+
+#define HCI_DATA_BASE                                0x80
+
+#define HCI_CMND_SEND                               (0x01 + HCI_DATA_BASE)
+#define HCI_CMND_SENDTO                             (0x03 + HCI_DATA_BASE)
+#define HCI_DATA_BSD_RECVFROM                       (0x04 + HCI_DATA_BASE)
+#define HCI_DATA_BSD_RECV                           (0x05 + HCI_DATA_BASE)
+
+
+#define HCI_CMND_NVMEM_CBASE        (0x0200)
+
+
+#define HCI_CMND_NVMEM_CREATE_ENTRY (0x0203)
+#define HCI_CMND_NVMEM_SWAP_ENTRY   (0x0205)
+#define HCI_CMND_NVMEM_READ         (0x0201)
+#define HCI_CMND_NVMEM_WRITE        (0x0090)
+#define HCI_CMND_NVMEM_WRITE_PATCH  (0x0204)
+#define HCI_CMND_READ_SP_VERSION    (0x0207)
+
+#define  HCI_CMND_READ_BUFFER_SIZE  0x400B
+#define  HCI_CMND_SIMPLE_LINK_START 0x4000
+
+#define HCI_CMND_NETAPP_BASE        0x2000
+
+#define HCI_NETAPP_DHCP                    (0x0001 + HCI_CMND_NETAPP_BASE)
+#define HCI_NETAPP_PING_SEND               (0x0002 + HCI_CMND_NETAPP_BASE)
+#define HCI_NETAPP_PING_REPORT             (0x0003 + HCI_CMND_NETAPP_BASE)
+#define HCI_NETAPP_PING_STOP               (0x0004 + HCI_CMND_NETAPP_BASE)
+#define HCI_NETAPP_IPCONFIG                (0x0005 + HCI_CMND_NETAPP_BASE)
+#define HCI_NETAPP_ARP_FLUSH               (0x0006 + HCI_CMND_NETAPP_BASE)
+#define HCI_NETAPP_SET_DEBUG_LEVEL         (0x0008 + HCI_CMND_NETAPP_BASE)
+#define HCI_NETAPP_SET_TIMERS              (0x0009 + HCI_CMND_NETAPP_BASE)
+
+// Values that can be used as HCI Events defines
+#define  HCI_EVNT_WLAN_BASE     0x0000
+#define  HCI_EVNT_WLAN_CONNECT  0x0001
+#define  HCI_EVNT_WLAN_DISCONNECT \
+                                0x0002
+#define  HCI_EVNT_WLAN_IOCTL_ADD_PROFILE  \
+                                0x0005
+
+
+#define  HCI_EVNT_SOCKET              HCI_CMND_SOCKET
+#define  HCI_EVNT_BIND                HCI_CMND_BIND
+#define  HCI_EVNT_RECV                HCI_CMND_RECV
+#define  HCI_EVNT_ACCEPT              HCI_CMND_ACCEPT
+#define  HCI_EVNT_LISTEN              HCI_CMND_LISTEN
+#define  HCI_EVNT_CONNECT             HCI_CMND_CONNECT
+#define  HCI_EVNT_SELECT              HCI_CMND_BSD_SELECT
+#define  HCI_EVNT_CLOSE_SOCKET        HCI_CMND_CLOSE_SOCKET
+#define  HCI_EVNT_RECVFROM            HCI_CMND_RECVFROM
+#define  HCI_EVNT_SETSOCKOPT          HCI_CMND_SETSOCKOPT
+#define  HCI_EVNT_GETSOCKOPT          HCI_CMND_GETSOCKOPT
+#define  HCI_EVNT_BSD_GETHOSTBYNAME   HCI_CMND_GETHOSTNAME
+#define  HCI_EVNT_MDNS_ADVERTISE      HCI_CMND_MDNS_ADVERTISE
+
+#define  HCI_EVNT_SEND                0x1003
+#define  HCI_EVNT_WRITE               0x100E
+#define  HCI_EVNT_SENDTO              0x100F
+
+#define HCI_EVNT_PATCHES_REQ          0x1000
+
+#define HCI_EVNT_UNSOL_BASE           0x4000
+
+#define HCI_EVNT_WLAN_UNSOL_BASE     (0x8000)
+
+#define HCI_EVNT_WLAN_UNSOL_CONNECT             (0x0001 + HCI_EVNT_WLAN_UNSOL_BASE)
+#define HCI_EVNT_WLAN_UNSOL_DISCONNECT          (0x0002 + HCI_EVNT_WLAN_UNSOL_BASE)
+#define HCI_EVNT_WLAN_UNSOL_INIT                (0x0004 + HCI_EVNT_WLAN_UNSOL_BASE)
+#define HCI_EVNT_WLAN_TX_COMPLETE               (0x0008 + HCI_EVNT_WLAN_UNSOL_BASE)
+#define HCI_EVNT_WLAN_UNSOL_DHCP                (0x0010 + HCI_EVNT_WLAN_UNSOL_BASE)
+#define HCI_EVNT_WLAN_ASYNC_PING_REPORT         (0x0040 + HCI_EVNT_WLAN_UNSOL_BASE)
+#define HCI_EVNT_WLAN_ASYNC_SIMPLE_CONFIG_DONE  (0x0080 + HCI_EVNT_WLAN_UNSOL_BASE)
+#define HCI_EVNT_WLAN_KEEPALIVE                 (0x0200  + HCI_EVNT_WLAN_UNSOL_BASE)
+#define    HCI_EVNT_BSD_TCP_CLOSE_WAIT          (0x0800 + HCI_EVNT_WLAN_UNSOL_BASE)
+
+#define HCI_EVNT_DATA_UNSOL_FREE_BUFF \
+                                0x4100
+
+#define HCI_EVNT_NVMEM_CREATE_ENTRY \
+                                HCI_CMND_NVMEM_CREATE_ENTRY
+#define HCI_EVNT_NVMEM_SWAP_ENTRY HCI_CMND_NVMEM_SWAP_ENTRY
+
+#define HCI_EVNT_NVMEM_READ     HCI_CMND_NVMEM_READ
+#define HCI_EVNT_NVMEM_WRITE    (0x0202)
+
+#define HCI_EVNT_READ_SP_VERSION      \
+                HCI_CMND_READ_SP_VERSION
+
+#define  HCI_EVNT_INPROGRESS    0xFFFF
+
+
+#define HCI_DATA_RECVFROM       0x84
+#define HCI_DATA_RECV           0x85
+#define HCI_DATA_NVMEM          0x91
+
+#define HCI_EVENT_CC3000_CAN_SHUT_DOWN 0x99
+
+// Prototypes for the structures for HCI APIs.
+#define HCI_DATA_HEADER_SIZE        (5)
+#define HCI_EVENT_HEADER_SIZE       (5)
+#define HCI_DATA_CMD_HEADER_SIZE    (5)
+#define HCI_PATCH_HEADER_SIZE       (6)
+
+#define HCI_PACKET_TYPE_OFFSET      (0)
+#define HCI_PACKET_ARGSIZE_OFFSET   (2)
+#define HCI_PACKET_LENGTH_OFFSET    (3)
+
+
+#define HCI_EVENT_OPCODE_OFFSET     (1)
+#define HCI_EVENT_LENGTH_OFFSET     (3)
+#define HCI_EVENT_STATUS_OFFSET     (4)
+#define HCI_DATA_LENGTH_OFFSET      (3)
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CC3000/cc3000_wlan.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,659 @@
+/*****************************************************************************
+*
+*  C++ interface/implementation created by Martin Kojtal (0xc0170). Thanks to
+*  Jim Carver and Frank Vannieuwkerke for their inital cc3000 mbed port and
+*  provided help.
+*
+*  This version of "host driver" uses CC3000 Host Driver Implementation. Thus
+*  read the following copyright:
+*
+*  Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*****************************************************************************/
+#include "cc3000.h"
+
+namespace mbed_cc3000 {
+
+cc3000_wlan::cc3000_wlan(cc3000_simple_link &simple_link, cc3000_event &event, cc3000_spi &spi, cc3000_hci &hci) :
+    _simple_link(simple_link), _event(event), _spi(spi), _hci(hci) {
+
+}
+
+cc3000_wlan::~cc3000_wlan() {
+
+}
+
+void cc3000_wlan::simpleLink_init_start(uint16_t patches_available_host) {
+    uint8_t *ptr;
+    uint8_t *args;
+
+    ptr = _simple_link.get_transmit_buffer();
+    args = (uint8_t *)(ptr + HEADERS_SIZE_CMD);
+
+    UINT8_TO_STREAM(args, ((patches_available_host) ? SL_PATCHES_REQUEST_FORCE_HOST : SL_PATCHES_REQUEST_DEFAULT));
+
+    // IRQ Line asserted - send HCI_CMND_SIMPLE_LINK_START to CC3000
+    _hci.command_send(HCI_CMND_SIMPLE_LINK_START, ptr, WLAN_SL_INIT_START_PARAMS_LEN);
+    _event.simplelink_wait_event(HCI_CMND_SIMPLE_LINK_START, 0);
+}
+
+void cc3000_wlan::start(uint16_t patches_available_host) {
+    uint32_t spi_irq_state;
+
+    _simple_link.set_sent_packets(0);
+    _simple_link.set_number_of_released_packets(0);
+    _simple_link.set_op_code(0);
+    _simple_link.set_number_free_buffers(0);
+    _simple_link.set_buffer_length(0);
+    _simple_link.set_buffer_size(0);
+    _simple_link.set_pending_data(0);
+    _simple_link.set_transmit_error(0);
+    _simple_link.set_data_received_flag(0);
+    _simple_link.set_buffer_size(0);
+
+    // init spi
+    _spi.open();
+    // Check the IRQ line
+    spi_irq_state = _spi.wlan_irq_read();
+    // ASIC 1273 chip enable: toggle WLAN EN line
+    _spi.set_wlan_en(WLAN_ENABLE);
+
+    if (spi_irq_state) {
+        // wait till the IRQ line goes low
+        while(_spi.wlan_irq_read() != 0);
+    } else {
+        // wait till the IRQ line goes high and then low
+        while(_spi.wlan_irq_read() == 0);
+        while(_spi.wlan_irq_read() != 0);
+    }
+    simpleLink_init_start(patches_available_host);
+
+    // Read Buffer's size and finish
+    _hci.command_send(HCI_CMND_READ_BUFFER_SIZE, _simple_link.get_transmit_buffer(), 0);
+    _event.simplelink_wait_event(HCI_CMND_READ_BUFFER_SIZE, 0);
+}
+
+
+void cc3000_wlan::stop() {
+    // ASIC 1273 chip disable
+    _spi.set_wlan_en(WLAN_DISABLE);
+
+    // Wait till IRQ line goes high
+    while(_spi.wlan_irq_read() == 0);
+
+    _spi.close();
+}
+
+
+int32_t cc3000_wlan::disconnect() {
+    int32_t ret;
+    uint8_t *ptr;
+
+    ret = EFAIL;
+    ptr = _simple_link.get_transmit_buffer();
+
+    _hci.command_send(HCI_CMND_WLAN_DISCONNECT, ptr, 0);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_CMND_WLAN_DISCONNECT, &ret);
+    errno = ret;
+
+    return ret;
+}
+
+
+int32_t cc3000_wlan::ioctl_set_connection_policy(uint32_t should_connect_to_open_ap,
+                                      uint32_t use_fast_connect,
+                                      uint32_t use_profiles) {
+    int32_t ret;
+    uint8_t *ptr;
+    uint8_t *args;
+
+    ret = EFAIL;
+    ptr = _simple_link.get_transmit_buffer();
+    args = (uint8_t *)(ptr + HEADERS_SIZE_CMD);
+
+    // Fill in HCI packet structure
+    args = UINT32_TO_STREAM(args, should_connect_to_open_ap);
+    args = UINT32_TO_STREAM(args, use_fast_connect);
+    args = UINT32_TO_STREAM(args, use_profiles);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_WLAN_IOCTL_SET_CONNECTION_POLICY, ptr, WLAN_SET_CONNECTION_POLICY_PARAMS_LEN);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_CMND_WLAN_IOCTL_SET_CONNECTION_POLICY, &ret);
+
+    return ret;
+}
+
+
+int32_t cc3000_wlan::ioctl_del_profile(uint32_t index) {
+    int32_t ret;
+    uint8_t *ptr;
+    uint8_t *args;
+
+    ptr = _simple_link.get_transmit_buffer();
+    args = (uint8_t *)(ptr + HEADERS_SIZE_CMD);
+
+    // Fill in HCI packet structure
+    args = UINT32_TO_STREAM(args, index);
+    ret = EFAIL;
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_WLAN_IOCTL_DEL_PROFILE, ptr, WLAN_DEL_PROFILE_PARAMS_LEN);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_CMND_WLAN_IOCTL_DEL_PROFILE, &ret);
+
+    return ret;
+}
+
+int32_t cc3000_wlan::set_event_mask(uint32_t mask) {
+    int32_t ret;
+    uint8_t *ptr;
+    uint8_t *args;
+
+
+    if ((mask & HCI_EVNT_WLAN_TX_COMPLETE) == HCI_EVNT_WLAN_TX_COMPLETE) {
+        _simple_link.set_tx_complete_signal(0);
+
+        // Since an event is a virtual event - i.e. it is not coming from CC3000
+        // there is no need to send anything to the device if it was an only event
+        if (mask == HCI_EVNT_WLAN_TX_COMPLETE) {
+            return 0;
+        }
+
+        mask &= ~HCI_EVNT_WLAN_TX_COMPLETE;
+        mask |= HCI_EVNT_WLAN_UNSOL_BASE;
+    } else {
+        _simple_link.set_tx_complete_signal(1);
+    }
+
+    ret = EFAIL;
+    ptr = _simple_link.get_transmit_buffer();
+    args = (uint8_t *)(ptr + HEADERS_SIZE_CMD);
+
+    // Fill in HCI packet structure
+    args = UINT32_TO_STREAM(args, mask);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_EVENT_MASK, ptr, WLAN_SET_MASK_PARAMS_LEN);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_CMND_EVENT_MASK, &ret);
+
+    return ret;
+}
+
+
+int32_t cc3000_wlan::smart_config_start(uint32_t encrypted_flag) {
+    int32_t ret;
+    uint8_t *ptr;
+    uint8_t *args;
+
+    ret = EFAIL;
+    ptr = _simple_link.get_transmit_buffer();
+    args = (uint8_t *)(ptr + HEADERS_SIZE_CMD);
+
+    // Fill in HCI packet structure
+    args = UINT32_TO_STREAM(args, encrypted_flag);
+    ret = EFAIL;
+
+    _hci.command_send(HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_START, ptr, WLAN_SMART_CONFIG_START_PARAMS_LEN);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_START, &ret);
+
+    return ret;
+}
+
+
+int32_t cc3000_wlan::smart_config_stop(void) {
+    int32_t ret;
+    uint8_t *ptr;
+
+    ret = EFAIL;
+    ptr = _simple_link.get_transmit_buffer();
+
+    _hci.command_send(HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_STOP, ptr, 0);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_STOP, &ret);
+
+    return ret;
+}
+
+int32_t cc3000_wlan::smart_config_set_prefix(uint8_t *new_prefix) {
+    int32_t ret;
+    uint8_t *ptr;
+    uint8_t *args;
+
+    ret = EFAIL;
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_CMD);
+
+    if (new_prefix == NULL) {
+        return ret;
+    } else {
+        // with the new Smart Config, prefix must be TTT
+        *new_prefix = 'T';
+        *(new_prefix + 1) = 'T';
+        *(new_prefix + 2) = 'T';
+    }
+
+    ARRAY_TO_STREAM(args, new_prefix, SL_SIMPLE_CONFIG_PREFIX_LENGTH);
+
+    _hci.command_send(HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_SET_PREFIX, ptr, SL_SIMPLE_CONFIG_PREFIX_LENGTH);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_CMND_WLAN_IOCTL_SIMPLE_CONFIG_SET_PREFIX, &ret);
+
+    return ret;
+}
+
+#ifndef CC3000_TINY_DRIVER
+int32_t cc3000_wlan::connect(uint32_t sec_type, const uint8_t *ssid, int32_t ssid_len, uint8_t *bssid,
+              uint8_t *key, int32_t key_len) {
+    int32_t ret;
+    uint8_t *ptr;
+    uint8_t *args;
+    uint8_t bssid_zero[] = {0, 0, 0, 0, 0, 0};
+
+    ret      = EFAIL;
+    ptr      = _simple_link.get_transmit_buffer();
+    args     = (ptr + HEADERS_SIZE_CMD);
+
+    // Fill in command buffer
+    args = UINT32_TO_STREAM(args, 0x0000001c);
+    args = UINT32_TO_STREAM(args, ssid_len);
+    args = UINT32_TO_STREAM(args, sec_type);
+    args = UINT32_TO_STREAM(args, 0x00000010 + ssid_len);
+    args = UINT32_TO_STREAM(args, key_len);
+    args = UINT16_TO_STREAM(args, 0);
+
+    // padding shall be zeroed
+    if (bssid) {
+        ARRAY_TO_STREAM(args, bssid, ETH_ALEN);
+    } else {
+        ARRAY_TO_STREAM(args, bssid_zero, ETH_ALEN);
+    }
+
+    ARRAY_TO_STREAM(args, ssid, ssid_len);
+
+    if (key_len && key) {
+        ARRAY_TO_STREAM(args, key, key_len);
+    }
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_WLAN_CONNECT, ptr, WLAN_CONNECT_PARAM_LEN + ssid_len + key_len - 1);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_CMND_WLAN_CONNECT, &ret);
+    errno = ret;
+
+    return ret;
+}
+
+int32_t cc3000_wlan::add_profile(uint32_t sec_type,
+                      uint8_t* ssid,
+                      uint32_t ssid_length,
+                      uint8_t *b_ssid,
+                      uint32_t priority,
+                      uint32_t pairwise_cipher_or_tx_key_len,
+                      uint32_t group_cipher_tx_key_index,
+                      uint32_t key_mgmt,
+                      uint8_t* pf_or_key,
+                      uint32_t pass_phrase_len) {
+    uint16_t arg_len = 0x00;
+    int32_t ret;
+    uint8_t *ptr;
+    int32_t i = 0;
+    uint8_t *args;
+    uint8_t bssid_zero[] = {0, 0, 0, 0, 0, 0};
+
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_CMD);
+
+    args = UINT32_TO_STREAM(args, sec_type);
+
+    // Setup arguments in accordance with the security type
+    switch (sec_type)
+    {
+        //OPEN
+        case WLAN_SEC_UNSEC:
+        {
+            args = UINT32_TO_STREAM(args, 0x00000014);
+            args = UINT32_TO_STREAM(args, ssid_length);
+            args = UINT16_TO_STREAM(args, 0);
+            if(b_ssid) {
+                ARRAY_TO_STREAM(args, b_ssid, ETH_ALEN);
+            } else {
+                ARRAY_TO_STREAM(args, bssid_zero, ETH_ALEN);
+            }
+            args = UINT32_TO_STREAM(args, priority);
+            ARRAY_TO_STREAM(args, ssid, ssid_length);
+
+            arg_len = WLAN_ADD_PROFILE_NOSEC_PARAM_LEN + ssid_length;
+        }
+        break;
+
+        //WEP
+        case WLAN_SEC_WEP:
+        {
+            args = UINT32_TO_STREAM(args, 0x00000020);
+            args = UINT32_TO_STREAM(args, ssid_length);
+            args = UINT16_TO_STREAM(args, 0);
+            if (b_ssid) {
+                ARRAY_TO_STREAM(args, b_ssid, ETH_ALEN);
+            } else {
+                ARRAY_TO_STREAM(args, bssid_zero, ETH_ALEN);
+            }
+            args = UINT32_TO_STREAM(args, priority);
+            args = UINT32_TO_STREAM(args, 0x0000000C + ssid_length);
+            args = UINT32_TO_STREAM(args, pairwise_cipher_or_tx_key_len);
+            args = UINT32_TO_STREAM(args, group_cipher_tx_key_index);
+            ARRAY_TO_STREAM(args, ssid, ssid_length);
+
+            for(i = 0; i < 4; i++) {
+                uint8_t *p = &pf_or_key[i * pairwise_cipher_or_tx_key_len];
+
+                ARRAY_TO_STREAM(args, p, pairwise_cipher_or_tx_key_len);
+            }
+
+            arg_len = WLAN_ADD_PROFILE_WEP_PARAM_LEN + ssid_length +
+                pairwise_cipher_or_tx_key_len * 4;
+
+        }
+        break;
+
+        //WPA
+        //WPA2
+        case WLAN_SEC_WPA:
+        case WLAN_SEC_WPA2:
+        {
+            args = UINT32_TO_STREAM(args, 0x00000028);
+            args = UINT32_TO_STREAM(args, ssid_length);
+            args = UINT16_TO_STREAM(args, 0);
+            if (b_ssid) {
+                ARRAY_TO_STREAM(args, b_ssid, ETH_ALEN);
+            } else {
+                ARRAY_TO_STREAM(args, bssid_zero, ETH_ALEN);
+            }
+            args = UINT32_TO_STREAM(args, priority);
+            args = UINT32_TO_STREAM(args, pairwise_cipher_or_tx_key_len);
+            args = UINT32_TO_STREAM(args, group_cipher_tx_key_index);
+            args = UINT32_TO_STREAM(args, key_mgmt);
+            args = UINT32_TO_STREAM(args, 0x00000008 + ssid_length);
+            args = UINT32_TO_STREAM(args, pass_phrase_len);
+            ARRAY_TO_STREAM(args, ssid, ssid_length);
+            ARRAY_TO_STREAM(args, pf_or_key, pass_phrase_len);
+
+            arg_len = WLAN_ADD_PROFILE_WPA_PARAM_LEN + ssid_length + pass_phrase_len;
+        }
+
+        break;
+    }
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_WLAN_IOCTL_ADD_PROFILE, ptr, arg_len);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_CMND_WLAN_IOCTL_ADD_PROFILE, &ret);
+
+    return ret;
+}
+
+int32_t cc3000_wlan::ioctl_get_scan_results(uint32_t scan_timeout, uint8_t *results) {
+    uint8_t *ptr;
+    uint8_t *args;
+
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_CMD);
+
+    // Fill in temporary command buffer
+    args = UINT32_TO_STREAM(args, scan_timeout);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_WLAN_IOCTL_GET_SCAN_RESULTS, ptr, WLAN_GET_SCAN_RESULTS_PARAMS_LEN);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_CMND_WLAN_IOCTL_GET_SCAN_RESULTS, results);
+
+    return 0;
+}
+
+int32_t cc3000_wlan::ioctl_set_scan_params(uint32_t enable,
+                                uint32_t min_dwell_time,
+                                uint32_t max_dwell_time,
+                                uint32_t num_probe_requests,
+                                uint32_t channel_mask,
+                                int32_t rssi_threshold,
+                                uint32_t snr_threshold,
+                                uint32_t default_tx_power,
+                                uint32_t *interval_list) {
+    uint32_t  uiRes;
+    uint8_t *ptr;
+    uint8_t *args;
+
+    ptr = _simple_link.get_transmit_buffer();
+    args = (ptr + HEADERS_SIZE_CMD);
+
+    // Fill in temporary command buffer
+    args = UINT32_TO_STREAM(args, 36);
+    args = UINT32_TO_STREAM(args, enable);
+    args = UINT32_TO_STREAM(args, min_dwell_time);
+    args = UINT32_TO_STREAM(args, max_dwell_time);
+    args = UINT32_TO_STREAM(args, num_probe_requests);
+    args = UINT32_TO_STREAM(args, channel_mask);
+    args = UINT32_TO_STREAM(args, rssi_threshold);
+    args = UINT32_TO_STREAM(args, snr_threshold);
+    args = UINT32_TO_STREAM(args, default_tx_power);
+    ARRAY_TO_STREAM(args, interval_list, sizeof(uint32_t) * SL_SET_SCAN_PARAMS_INTERVAL_LIST_SIZE);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_WLAN_IOCTL_SET_SCANPARAM, ptr, WLAN_SET_SCAN_PARAMS_LEN);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_CMND_WLAN_IOCTL_SET_SCANPARAM, &uiRes);
+
+    return(uiRes);
+}
+
+int32_t cc3000_wlan::ioctl_statusget(void) {
+    int32_t ret;
+    uint8_t *ptr;
+
+    ret = EFAIL;
+    ptr = _simple_link.get_transmit_buffer();
+
+    _hci.command_send(HCI_CMND_WLAN_IOCTL_STATUSGET,ptr, 0);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_CMND_WLAN_IOCTL_STATUSGET, &ret);
+
+    return ret;
+}
+
+#else
+int32_t cc3000_wlan::add_profile(uint32_t sec_type,
+                      uint8_t *ssid,
+                      uint32_t ssid_length,
+                      uint8_t *b_ssid,
+                      uint32_t priority,
+                      uint32_t pairwise_cipher_or_tx_key_len,
+                      uint32_t group_cipher_tx_key_index,
+                      uint32_t key_mgmt,
+                      uint8_t* pf_or_key,
+                      uint32_t pass_phrase_length)
+{
+    return -1;
+}
+
+int32_t cc3000_wlan::connect(const uint8_t *ssid, int32_t ssid_len) {
+    int32_t ret;
+    uint8_t *ptr;
+    uint8_t *args;
+    uint8_t bssid_zero[] = {0, 0, 0, 0, 0, 0};
+
+    ret      = EFAIL;
+    ptr      = _simple_link.get_transmit_buffer();
+    args     = (ptr + HEADERS_SIZE_CMD);
+
+    // Fill in command buffer
+    args = UINT32_TO_STREAM(args, 0x0000001c);
+    args = UINT32_TO_STREAM(args, ssid_len);
+    args = UINT32_TO_STREAM(args, 0);
+    args = UINT32_TO_STREAM(args, 0x00000010 + ssid_len);
+    args = UINT32_TO_STREAM(args, 0);
+    args = UINT16_TO_STREAM(args, 0);
+
+    // padding shall be zeroed
+    ARRAY_TO_STREAM(args, bssid_zero, ETH_ALEN);
+    ARRAY_TO_STREAM(args, ssid, ssid_len);
+
+    // Initiate a HCI command
+    _hci.command_send(HCI_CMND_WLAN_CONNECT, ptr, WLAN_CONNECT_PARAM_LEN + ssid_len  - 1);
+
+    // Wait for command complete event
+    _event.simplelink_wait_event(HCI_CMND_WLAN_CONNECT, &ret);
+    errno = ret;
+
+    return ret;
+}
+#endif
+
+
+
+#ifndef CC3000_UNENCRYPTED_SMART_CONFIG
+int32_t cc3000_wlan::smart_config_process(void) {
+    int32_t  returnValue;
+    uint32_t ssidLen, keyLen;
+    uint8_t *decKeyPtr;
+    uint8_t *ssidPtr;
+
+    // read the key from EEPROM - fileID 12
+    returnValue = aes_read_key(key);
+
+    if (returnValue != 0)
+        return returnValue;
+
+    // read the received data from fileID #13 and parse it according to the followings:
+    // 1) SSID LEN - not encrypted
+    // 2) SSID - not encrypted
+    // 3) KEY LEN - not encrypted. always 32 bytes long
+    // 4) Security type - not encrypted
+    // 5) KEY - encrypted together with true key length as the first byte in KEY
+    //     to elaborate, there are two corner cases:
+    //        1) the KEY is 32 bytes long. In this case, the first byte does not represent KEY length
+    //        2) the KEY is 31 bytes long. In this case, the first byte represent KEY length and equals 31
+    returnValue = nvmem_read(NVMEM_SHARED_MEM_FILEID, SMART_CONFIG_PROFILE_SIZE, 0, profileArray);
+
+    if (returnValue != 0)
+        return returnValue;
+
+    ssidPtr = &profileArray[1];
+
+    ssidLen = profileArray[0];
+
+    decKeyPtr = &profileArray[profileArray[0] + 3];
+
+    aes_decrypt(decKeyPtr, key);
+    if (profileArray[profileArray[0] + 1] > 16)
+        aes_decrypt((uint8_t *)(decKeyPtr + 16), key);
+
+    if (*(uint8_t *)(decKeyPtr +31) != 0) {
+        if (*decKeyPtr == 31) {
+            keyLen = 31;
+            decKeyPtr++;
+        } else {
+            keyLen = 32;
+        }
+    } else {
+        keyLen = *decKeyPtr;
+        decKeyPtr++;
+    }
+
+    // add a profile
+    switch (profileArray[profileArray[0] + 2])
+    {
+    case WLAN_SEC_UNSEC://None
+         {
+            returnValue = wlan_add_profile(profileArray[profileArray[0] + 2],     // security type
+                                           ssidPtr,                               // SSID
+                                           ssidLen,                               // SSID length
+                                           NULL,                                  // BSSID
+                                           1,                                     // Priority
+                                           0, 0, 0, 0, 0);
+
+            break;
+         }
+
+    case WLAN_SEC_WEP://WEP
+        {
+            returnValue = wlan_add_profile(profileArray[profileArray[0] + 2],     // security type
+                                           ssidPtr,                               // SSID
+                                           ssidLen,                               // SSID length
+                                           NULL,                                  // BSSID
+                                           1,                                     // Priority
+                                           keyLen,                                // KEY length
+                                           0,                                     // KEY index
+                                           0,
+                                           decKeyPtr,                             // KEY
+                                           0);
+
+            break;
+        }
+
+    case WLAN_SEC_WPA:  //WPA
+    case WLAN_SEC_WPA2: //WPA2
+        {
+            returnValue = wlan_add_profile(WLAN_SEC_WPA2,     // security type
+                                           ssidPtr,
+                                           ssidLen,
+                                           NULL,              // BSSID
+                                           1,                 // Priority
+                                           0x18,              // PairwiseCipher
+                                           0x1e,              // GroupCipher
+                                           2,                 // KEY management
+                                           decKeyPtr,         // KEY
+                                           keyLen);           // KEY length
+
+            break;
+        }
+    }
+
+    return returnValue;
+}
+#endif
+
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/DHT/DHT.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,200 @@
+#include "DHT.h"
+
+
+#define DHT_DATA_BIT_COUNT 41
+
+DHT::DHT(PinName pin,int DHTtype)
+	: _mutex()
+{
+    _pin = pin;
+    _DHTtype = DHTtype;
+    _firsttime=true;
+}
+
+DHT::~DHT() {
+}
+
+int DHT::readData() 
+{
+
+	
+   int err = ERROR_NONE;
+   Timer tmr;
+
+     DigitalInOut data_pin(_pin);
+		// We make sure we are the only ones
+		// reading data right now.
+	   _mutex.lock();
+	
+    // BUFFER TO RECEIVE
+    uint8_t cnt = 7;
+    uint8_t idx = 0;
+    
+    tmr.stop();
+    tmr.reset();
+ 
+    // EMPTY BUFFER
+    for(int i=0; i< 5; i++) DHT_data[i] = 0;
+ 
+    // REQUEST SAMPLE
+    data_pin.output();
+    data_pin.write(0);
+    wait_ms(18);
+    data_pin.write(1);
+    wait_us(40);
+    data_pin.input();
+ 
+    // ACKNOWLEDGE or TIMEOUT
+    unsigned int loopCnt = 10000;
+    
+    while(!data_pin.read())if(!loopCnt--)
+		{
+			_mutex.unlock();
+			return ERROR_DATA_TIMEOUT;
+		}
+ 
+    loopCnt = 10000;
+    
+    while(data_pin.read())if(!loopCnt--)
+		{
+			_mutex.unlock();
+			return ERROR_DATA_TIMEOUT;
+		}
+ 
+    // READ OUTPUT - 40 BITS => 5 BYTES or TIMEOUT
+    for(int i=0; i<40; i++){
+        
+        loopCnt = 10000;
+        
+        while(!data_pin.read())if(loopCnt-- == 0)
+				{
+					_mutex.unlock();
+					return ERROR_DATA_TIMEOUT;
+				}
+ 
+        //unsigned long t = micros();
+        tmr.start();
+ 
+        loopCnt = 10000;
+        
+        while(data_pin.read())if(!loopCnt--)
+				{
+					_mutex.unlock();
+					return ERROR_DATA_TIMEOUT;
+				}
+ 
+        if(tmr.read_us() > 40) DHT_data[idx] |= (1 << cnt);
+        
+        tmr.stop();
+        tmr.reset();
+        
+        if(cnt == 0){   // next byte?
+        
+            cnt = 7;    // restart at MSB
+            idx++;      // next byte!
+            
+        }else cnt--;
+        
+    }
+ 
+    // WRITE TO RIGHT VARS
+    uint8_t sum = (DHT_data[0] + DHT_data[1] + DHT_data[2] + DHT_data[3]) & 0xFF;  
+ 
+    if(DHT_data[4] != sum)
+		{ 
+			_mutex.unlock();
+			return ERROR_CHECKSUM;
+		}
+        
+    _lastTemperature= CalcTemperature();
+    _lastHumidity= CalcHumidity();
+    
+		_mutex.unlock();
+    return err;
+}
+
+
+float DHT::ReadHumidity() {
+    return _lastHumidity;
+}
+
+float DHT::ConvertCelciustoFarenheit(float celsius) {
+    return celsius * 9 / 5 + 32;
+}
+
+float DHT::ConvertCelciustoKelvin(float celsius) {
+    return celsius + 273.15;
+}
+
+// dewPoint function NOAA
+// reference: http://wahiduddin.net/calc/density_algorithms.htm
+float DHT::CalcdewPoint(float celsius, float humidity) {
+    float A0= 373.15/(273.15 + celsius);
+    float SUM = -7.90298 * (A0-1);
+    SUM += 5.02808 * log10(A0);
+    SUM += -1.3816e-7 * (pow(10, (11.344*(1-1/A0)))-1) ;
+    SUM += 8.1328e-3 * (pow(10,(-3.49149*(A0-1)))-1) ;
+    SUM += log10(1013.246);
+    float VP = pow(10, SUM-3) * humidity;
+    float T = log(VP/0.61078);   // temp var
+    return (241.88 * T) / (17.558-T);
+}
+
+// delta max = 0.6544 wrt dewPoint()
+// 5x faster than dewPoint()
+// reference: http://en.wikipedia.org/wiki/Dew_point
+float DHT::CalcdewPointFast(float celsius, float humidity)
+{
+        float a = 17.271;
+        float b = 237.7;
+        float temp = (a * celsius) / (b + celsius) + log(humidity/100);
+        float Td = (b * temp) / (a - temp);
+        return Td;
+}
+
+float DHT::ReadTemperature(eScale Scale) {
+    if (Scale == FARENHEIT)
+        return ConvertCelciustoFarenheit(_lastTemperature);
+    else if (Scale == KELVIN)
+        return ConvertCelciustoKelvin(_lastTemperature);
+    else
+        return _lastTemperature;
+}
+
+float DHT::CalcTemperature() {
+    int v;
+
+    switch (_DHTtype) {
+        case DHT11:
+            v = DHT_data[2];
+            return float(v);
+        case DHT22:
+            v = DHT_data[2] & 0x7F;
+            v *= 256;
+            v += DHT_data[3];
+            v /= 10;
+            if (DHT_data[2] & 0x80)
+                v *= -1;
+            return float(v);
+    }
+    return 0;
+}
+
+float DHT::CalcHumidity() {
+    int v;
+
+    switch (_DHTtype) {
+        case DHT11:
+            v = DHT_data[0];
+            return float(v);
+        case DHT22:
+            v = DHT_data[0];
+            v *= 256;
+            v += DHT_data[1];
+            v /= 10;
+            return float(v);
+    }
+    return 0;
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/DHT/DHT.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,73 @@
+#ifndef MBED_DHT_H
+#define MBED_DHT_H
+
+#include "mbed.h"
+#include "cmsis_os.h"
+#include "Mutex.h"
+
+using namespace rtos;
+
+enum eType{
+        DHT11     = 11,
+        SEN11301P = 11,
+        RHT01     = 11,
+        DHT22     = 22,
+        AM2302    = 22,
+        SEN51035P = 22,
+        RHT02     = 22,
+        RHT03     = 22
+    } ;
+
+enum eError {
+    ERROR_NONE = 0,
+    BUS_BUSY =1,
+    ERROR_NOT_PRESENT =2 ,
+    ERROR_ACK_TOO_LONG =3 ,
+    ERROR_SYNC_TIMEOUT = 4,
+    ERROR_DATA_TIMEOUT =5 ,
+    ERROR_CHECKSUM = 6,
+    ERROR_NO_PATIENCE =7
+} ;
+
+typedef enum {
+    CELCIUS =0 ,
+    FARENHEIT =1,
+    KELVIN=2
+} eScale;
+
+
+class DHT {
+
+public:
+
+    DHT(PinName pin,int DHTtype);
+    ~DHT();
+
+    int readData(void);
+    float ReadHumidity(void);
+    float ReadTemperature(eScale Scale);
+
+        float CalcdewPoint(float celsius, float humidity);
+        float CalcdewPointFast(float celsius, float humidity);
+
+private:
+    time_t  _lastReadTime;
+    float _lastTemperature;
+    float _lastHumidity;
+
+    PinName _pin;
+    bool _firsttime;
+    int _DHTtype;
+    int DHT_data[6];
+
+    float ConvertCelciustoFarenheit(float celsius);
+    float ConvertCelciustoKelvin(float celsius);
+    float CalcTemperature();
+    float CalcHumidity();
+
+		Mutex _mutex;
+
+};
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/HttpClient.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,357 @@
+#include "HttpClient.h"
+#include "Utility.h"
+#include <string>
+#include <cstring>
+#include <vector>
+
+extern Serial pc;
+
+#if 1
+//Enable debug
+#include <cstdio>
+#define DBG(x, ...) pc.printf("[HTTPClient : DBG]"x"\r\n", ##__VA_ARGS__); 
+#define WARN(x, ...) pc.printf("[HTTPClient : WARN]"x"\r\n", ##__VA_ARGS__); 
+#define ERR(x, ...) pc.printf("[HTTPClient : ERR]"x"\r\n", ##__VA_ARGS__); 
+#else
+//Disable debug
+#define DBG(x, ...) 
+#define WARN(x, ...)
+#define ERR(x, ...) 
+#endif
+
+
+
+
+HttpClient::HttpClient(const char * hostname)
+	: _hostname(hostname)
+{
+}
+
+int HttpClient::get(const char * url, char * buffer, size_t buf_len, HeaderInfo & hinfo, int timeout)
+{
+	char scheme[8];
+  uint16_t port;
+  char host[32];
+  char path[64];
+
+	_timeout = timeout;
+	
+  if(parse_url(url, scheme, sizeof(scheme), host, sizeof(host), &port, path, sizeof(path)))
+  {
+    ERR("Error parsing URL");
+    return -1;
+  }
+
+  if(port == 0) //TODO do handle HTTPS->443
+  {
+    port = 80;
+  }
+
+  DBG("Scheme: %s", scheme);
+  DBG("Host: %s", host);
+  DBG("Port: %d", port);
+  DBG("Path: %s", path);
+	
+	// Connect to server
+  int ret = m_sock.connect(host, port);
+  if (ret < 0)
+  {
+    m_sock.close();
+    ERR("Could not connect");
+    return -1;
+  }
+
+  //Send request
+	std::string req_header = build_http_headers("GET", (const char *) path);
+  ret = send((char *) req_header.c_str(), req_header.size());
+  if(ret)
+  {
+    m_sock.close();
+    ERR("Could not write request\r\n");
+    return -1;
+  }
+	// Process the response
+	// First get the header
+	DBG("Reading HTTP header ...\r\n");
+	char header_buf[512];
+	int header_line = 0, numread = 0;
+	
+	do {
+		memset(header_buf, 0, sizeof(header_buf));
+		numread = recv_until(header_buf, sizeof(header_buf), '\n');
+		// remove trailing \r\n
+		std::string line(header_buf, numread);
+		line = trim(line, " \t\r\n");
+		
+		DBG("Header line [%s]\r\n", line.c_str());
+		parse_headers(line, hinfo, header_line);
+		header_line++;
+	}while(numread > 2); // empty line for \r\n
+	
+	// Show the header information
+	DBG("Http response: %d\r\n", hinfo.http_response);
+	DBG("Http response text: %s\r\n", hinfo.http_response_text.c_str());
+	for(std::map<std::string, std::string>::iterator it = hinfo.http_info.begin();
+		it != hinfo.http_info.end();
+		it++)
+	{
+		DBG("Key [%s] : Value [%s]\r\n", it->first.c_str(), it->second.c_str());
+	}
+	
+	// Read the rest of the data based on content type
+	return read_data(hinfo, buffer, buf_len);
+	
+}
+
+int HttpClient::read_data(HeaderInfo & hinfo, char * buffer, size_t buf_len)
+{
+	int chunk_size = 0;
+	char tmp_buf[10]; // just for reading the \r\n values
+	char * buf_ptr = buffer;
+	int numread = 0;
+	
+	m_sock.set_blocking(false, _timeout);
+	if (hinfo.http_info["Transfer-Encoding"] == "chunked")
+	{
+		do {
+			// read the chunk size
+			DBG("Reading chunk size ...\r\n");
+			if ( m_sock.receive_until(tmp_buf, 10, '\n') > 0)
+			{
+				chunk_size = strtoul(tmp_buf, NULL, 16);
+				DBG("Chunk size: %d\r\n", chunk_size);
+			}else
+				break;
+
+			if (chunk_size > 0)
+			{
+				// read one char at a time untill chunk size
+				int cur_read2 = 0;
+				do {
+						if (m_sock.receive(buf_ptr,1) < 0)
+						{
+							DBG("Error reading chunks with total read [%d]...\r\n", numread);
+							return -1;
+						}
+						cur_read2 ++;
+						buf_ptr ++;
+				}while(cur_read2 < chunk_size);
+				DBG("Read %d chunk\r\n", cur_read2);
+			}
+	
+			numread += chunk_size;
+			DBG("Consuming new lines ...\r\n");
+			// Consume the next new line
+			m_sock.receive_until(tmp_buf, 10, '\n');
+			
+		}while((chunk_size > 0) && ((buf_ptr - buffer) < buf_len)); 
+		
+	}else
+	{
+			DBG("Reading complete data in one go ...\r\n");
+			numread = m_sock.receive_all(buffer, buf_len);
+	}
+	
+	DBG("Read %d bytes", numread);
+	
+	// Finally close the socket
+	m_sock.close();
+		
+	return numread;
+}
+
+int HttpClient::parse_headers(std::string header_line, HeaderInfo & hinfo, int lineno)
+{
+	std::vector<std::string> tokens;
+	// remove the trailing \n
+	
+	if (lineno == 0)
+	{
+		// Tokenize the first line using spaces
+		split(tokens, header_line, " ");
+		if (tokens.size() == 3)
+		{
+			//for(int i=0; i < tokens.size() ; i++)
+			//	pc.printf("Token[%d] = [%s]\r\n", i, tokens[i].c_str());
+			
+			// The second part is the http response
+			hinfo.http_response = atol(tokens[1].c_str());
+			DBG("HTTP response [%d]\r\n", hinfo.http_response);
+			hinfo.http_response_text = trim(tokens[2]);
+			DBG("HTTP text [%s]\r\n", hinfo.http_response_text.c_str());
+		}
+	}else
+	{
+		
+		// Scan for key value pairs
+		split(tokens, header_line, ":");
+		if (tokens.size() == 2)
+		{
+			//for(int i=0; i < tokens.size() ; i++)
+			//	pc.printf("Token[%d] = [%s]\r\n", i, tokens[i].c_str());
+			
+			std::string key = trim(tokens[0]);
+			std::string value = trim(tokens[1]);
+			
+			hinfo.http_info[key] = value;
+		}
+	}
+	
+	return 0;
+}
+
+std::string HttpClient::build_http_headers(std::string type, std::string path)
+{
+	std::string request_hdr = type + " " + path + " " + "HTTP/1.1" + "\r\n";
+	request_hdr += "Host:" + _hostname + "\r\n";
+	request_hdr += "\r\n"; // empty line terminates the header
+	
+	return request_hdr;
+	
+}
+
+int HttpClient::parse_url(const char* url, char* scheme, 
+	size_t scheme_len, 
+	char* host, 
+	size_t host_len, 
+	uint16_t* port, 
+	char* path, 
+	size_t path_len) //Parse URL
+{
+  char* schemePtr = (char*) url;
+  char* hostPtr = (char*) strstr(url, "://");
+  if(hostPtr == NULL)
+	{
+		ERR("Invalid URL [%s]\r\n", url);
+    return -1; //URL is invalid
+	}
+
+  if( scheme_len < hostPtr - schemePtr + 1 ) //including NULL-terminating char
+  {
+    ERR("Scheme str is too small (%d >= %d)\r\n", scheme_len, hostPtr - schemePtr + 1);
+    return -1;
+  }
+  memcpy(scheme, schemePtr, hostPtr - schemePtr);
+  scheme[hostPtr - schemePtr] = '\0';
+
+  hostPtr+=3;
+
+  size_t hostLen = 0;
+
+  char* portPtr = strchr(hostPtr, ':');
+  if( portPtr != NULL )
+  {
+    hostLen = portPtr - hostPtr;
+    portPtr++;
+    if( sscanf(portPtr, "%hu", port) != 1)
+    {
+      ERR("Could not find port\r\n");
+      return -1;
+    }
+  }
+  else
+  {
+    *port=0;
+  }
+  char* pathPtr = strchr(hostPtr, '/');
+  if( hostLen == 0 )
+  {
+    hostLen = pathPtr - hostPtr;
+  }
+
+  if( host_len < hostLen + 1 ) //including NULL-terminating char
+  {
+    ERR("Host str is too small (%d >= %d)\r\n", host_len, hostLen + 1);
+    return -1;
+  }
+  memcpy(host, hostPtr, hostLen);
+  host[hostLen] = '\0';
+
+  size_t pathLen;
+  char* fragmentPtr = strchr(hostPtr, '#');
+  if(fragmentPtr != NULL)
+  {
+    pathLen = fragmentPtr - pathPtr;
+  }
+  else
+  {
+    pathLen = strlen(pathPtr);
+  }
+
+  if( path_len < pathLen + 1 ) //including NULL-terminating char
+  {
+    ERR("Path str is too small (%d >= %d)\r\n", path_len, pathLen + 1);
+    return -1;
+  }
+  memcpy(path, pathPtr, pathLen);
+  path[pathLen] = '\0';
+
+  return 0;
+}
+
+int HttpClient::recv_until(char * buf, size_t len, char term)
+{
+	int numread = 0;
+  if(!m_sock.is_connected())
+  {
+    ERR("Connection was closed by server\r\n");
+    return -1; //Connection was closed by server 
+  }
+  
+  m_sock.set_blocking(false, _timeout);
+  int ret = m_sock.receive_until(buf, len, term);
+  if(ret > 0)
+  {
+    numread += ret;
+  }
+  else if( ret == 0 )
+  {
+    ERR("Connection was closed by server\r\n");
+    return -1; //Connection was closed by server
+  }
+  else
+  {
+    ERR("Connection error (recv returned %d)\r\n", ret);
+    return -1;
+  }
+  
+  DBG("Received %d bytes", numread);
+  return numread;	
+}
+
+int HttpClient::send(char* buf, size_t len) //0 on success, err code on failure
+{
+  if(len == 0)
+  {
+    len = strlen(buf);
+  }
+  //pc.printf("Trying to write %d bytes\r\n", len);
+  size_t writtenLen = 0;
+    
+  if(!m_sock.is_connected())
+  {
+    ERR("Connection was closed by server\r\n");
+    return -1; //Connection was closed by server 
+  }
+  
+  m_sock.set_blocking(false, _timeout);
+  int ret = m_sock.send_all(buf, len);
+  if(ret > 0)
+  {
+    writtenLen += ret;
+  }
+  else if( ret == 0 )
+  {
+    ERR("Connection was closed by server\r\n");
+    return -1; //Connection was closed by server
+  }
+  else
+  {
+    ERR("Connection error (send returned %d)\r\n", ret);
+    return -1;
+  }
+  
+  DBG("Written %d bytes\r\n", writtenLen);
+  return 0;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/HttpClient.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,54 @@
+#ifndef __HTTP_CLIENT_H__
+#define __HTTP_CLIENT_H__
+
+#include "mbed.h"
+#include <string>
+#include <map>
+#include "TCPSocketConnection.h"
+
+enum content_type{
+	CONTENT_TYPE_TEXT,
+	CONTENT_TYPE_APPLICATION,
+	CONTENT_TYPE_IMAGE,
+	CONTENT_TYPE_MESSAGE
+};
+
+
+typedef struct {
+	int http_response;
+	std::string http_response_text;
+	std::map<std::string, std::string> http_info;
+} HeaderInfo;
+
+class HttpClient
+{
+	public:
+		HttpClient(const char * hostname);
+		int get(const char * url, char * buffer, size_t buf_len, HeaderInfo & hinfo, int timeout = 5000);
+	
+	private:
+		std::string build_http_headers(std::string type, std::string path);
+		int parse_url(const char* url, 
+			char* scheme, 
+			size_t scheme_len, 
+			char* host, 
+			size_t host_len, 
+			uint16_t* port, 
+			char* path, size_t max_path);
+			
+			int parse_headers(std::string header_line, HeaderInfo & hinfo, int line);
+			
+		int read_data(HeaderInfo & hinfo, char * buffer, size_t buf_len);
+
+		int send(char* buf, size_t len);
+		// Receive untill a char term is received
+		int recv_until(char * buf, size_t len, char term);
+			
+		std::string _hostname; // The name of this local host
+		int _timeout;
+		TCPSocketConnection m_sock;
+		int _httpResponse;
+};
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ILI9341/Arial12x12.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,107 @@
+
+
+//GLCD FontName : Arial12x12
+//GLCD FontSize : 12 x 12
+
+/** Arial Font with 12*12 matrix to use with SPI_TFT lib
+ */ 
+const unsigned char Arial12x12[] = {
+        25,12,12,2,                                                                           // Length,horz,vert,byte/vert
+        0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char  
+        0x02, 0x00, 0x00, 0x7F, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char !
+        0x03, 0x07, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char "
+        0x07, 0x24, 0x00, 0xA4, 0x01, 0x7C, 0x00, 0xA7, 0x01, 0x7C, 0x00, 0x27, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char #
+        0x06, 0x00, 0x00, 0xCE, 0x00, 0x11, 0x01, 0xFF, 0x03, 0x11, 0x01, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char $
+        0x0A, 0x00, 0x00, 0x0E, 0x00, 0x11, 0x00, 0x11, 0x01, 0xCE, 0x00, 0x38, 0x00, 0xE6, 0x00, 0x11, 0x01, 0x10, 0x01, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char %
+        0x08, 0x00, 0x00, 0xE0, 0x00, 0x1E, 0x01, 0x11, 0x01, 0x29, 0x01, 0xC6, 0x00, 0xA0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char &
+        0x02, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char '
+        0x04, 0x00, 0x00, 0xF8, 0x00, 0x06, 0x03, 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char (
+        0x03, 0x01, 0x04, 0x06, 0x03, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char )
+        0x05, 0x02, 0x00, 0x0A, 0x00, 0x07, 0x00, 0x0A, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char *
+        0x06, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x7C, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char +
+        0x02, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ,
+        0x03, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char -
+        0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char .
+        0x03, 0x80, 0x01, 0x7C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char /
+        0x06, 0x00, 0x00, 0xFE, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 0
+        0x06, 0x00, 0x00, 0x04, 0x00, 0x02, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 1
+        0x06, 0x00, 0x00, 0x02, 0x01, 0x81, 0x01, 0x41, 0x01, 0x31, 0x01, 0x0E, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 2
+        0x06, 0x00, 0x00, 0x82, 0x00, 0x01, 0x01, 0x11, 0x01, 0x11, 0x01, 0xEE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 3
+        0x06, 0x00, 0x00, 0x60, 0x00, 0x58, 0x00, 0x46, 0x00, 0xFF, 0x01, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 4
+        0x06, 0x00, 0x00, 0x9C, 0x00, 0x0B, 0x01, 0x09, 0x01, 0x09, 0x01, 0xF1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 5
+        0x06, 0x00, 0x00, 0xFE, 0x00, 0x11, 0x01, 0x09, 0x01, 0x09, 0x01, 0xF2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 6
+        0x06, 0x00, 0x00, 0x01, 0x00, 0xC1, 0x01, 0x39, 0x00, 0x07, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 7
+        0x06, 0x00, 0x00, 0xEE, 0x00, 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0xEE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 8
+        0x06, 0x00, 0x00, 0x9E, 0x00, 0x21, 0x01, 0x21, 0x01, 0x11, 0x01, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 9
+        0x02, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char :
+        0x02, 0x00, 0x00, 0x40, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ;
+        0x06, 0x00, 0x00, 0x10, 0x00, 0x28, 0x00, 0x28, 0x00, 0x44, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char <
+        0x06, 0x48, 0x00, 0x48, 0x00, 0x48, 0x00, 0x48, 0x00, 0x48, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char =
+        0x06, 0x00, 0x00, 0x44, 0x00, 0x44, 0x00, 0x28, 0x00, 0x28, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char >
+        0x06, 0x00, 0x00, 0x06, 0x00, 0x01, 0x00, 0x61, 0x01, 0x11, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ?
+        0x0C, 0x00, 0x00, 0xF0, 0x01, 0x0C, 0x02, 0xE2, 0x04, 0x12, 0x09, 0x09, 0x09, 0x09, 0x09, 0xF1, 0x09, 0x19, 0x09, 0x02, 0x05, 0x86, 0x04, 0x78, 0x02,  // Code for char @
+        0x07, 0x80, 0x01, 0x70, 0x00, 0x2E, 0x00, 0x21, 0x00, 0x2E, 0x00, 0x70, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char A
+        0x07, 0x00, 0x00, 0xFF, 0x01, 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char B
+        0x08, 0x00, 0x00, 0x7C, 0x00, 0x82, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x82, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char C
+        0x08, 0x00, 0x00, 0xFF, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x82, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char D
+        0x07, 0x00, 0x00, 0xFF, 0x01, 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char E
+        0x06, 0x00, 0x00, 0xFF, 0x01, 0x11, 0x00, 0x11, 0x00, 0x11, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char F
+        0x08, 0x00, 0x00, 0x7C, 0x00, 0x82, 0x00, 0x01, 0x01, 0x01, 0x01, 0x11, 0x01, 0x92, 0x00, 0x74, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char G
+        0x08, 0x00, 0x00, 0xFF, 0x01, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char H
+        0x02, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char I
+        0x05, 0xC0, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char J
+        0x08, 0x00, 0x00, 0xFF, 0x01, 0x20, 0x00, 0x10, 0x00, 0x28, 0x00, 0x44, 0x00, 0x82, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char K
+        0x07, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char L
+        0x08, 0x00, 0x00, 0xFF, 0x01, 0x06, 0x00, 0x78, 0x00, 0x80, 0x01, 0x78, 0x00, 0x06, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char M
+        0x08, 0x00, 0x00, 0xFF, 0x01, 0x02, 0x00, 0x0C, 0x00, 0x10, 0x00, 0x60, 0x00, 0x80, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char N
+        0x08, 0x00, 0x00, 0x7C, 0x00, 0x82, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x82, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char O
+        0x07, 0x00, 0x00, 0xFF, 0x01, 0x11, 0x00, 0x11, 0x00, 0x11, 0x00, 0x11, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char P
+        0x08, 0x00, 0x00, 0x7C, 0x00, 0x82, 0x00, 0x01, 0x01, 0x41, 0x01, 0x41, 0x01, 0x82, 0x00, 0x7C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Q
+        0x08, 0x00, 0x00, 0xFF, 0x01, 0x11, 0x00, 0x11, 0x00, 0x11, 0x00, 0x31, 0x00, 0xD1, 0x00, 0x0E, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char R
+        0x07, 0x00, 0x00, 0xCE, 0x00, 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0xE6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char S
+        0x07, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0xFF, 0x01, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char T
+        0x08, 0x00, 0x00, 0x7F, 0x00, 0x80, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x80, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char U
+        0x07, 0x03, 0x00, 0x1C, 0x00, 0x60, 0x00, 0x80, 0x01, 0x60, 0x00, 0x1C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char V
+        0x0B, 0x07, 0x00, 0x78, 0x00, 0x80, 0x01, 0x70, 0x00, 0x0E, 0x00, 0x01, 0x00, 0x0E, 0x00, 0x70, 0x00, 0x80, 0x01, 0x7C, 0x00, 0x03, 0x00, 0x00, 0x00,  // Code for char W
+        0x07, 0x01, 0x01, 0xC6, 0x00, 0x28, 0x00, 0x10, 0x00, 0x28, 0x00, 0xC6, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char X
+        0x07, 0x01, 0x00, 0x06, 0x00, 0x08, 0x00, 0xF0, 0x01, 0x08, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Y
+        0x07, 0x00, 0x01, 0x81, 0x01, 0x61, 0x01, 0x11, 0x01, 0x0D, 0x01, 0x03, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Z
+        0x03, 0x00, 0x00, 0xFF, 0x07, 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char [
+        0x03, 0x03, 0x00, 0x7C, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char BackSlash
+        0x02, 0x01, 0x04, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ]
+        0x05, 0x18, 0x00, 0x06, 0x00, 0x01, 0x00, 0x06, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ^
+        0x07, 0x00, 0x04, 0x00, 0x04, 0x00, 0x04, 0x00, 0x04, 0x00, 0x04, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char _
+        0x03, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char `
+        0x06, 0x00, 0x00, 0xC8, 0x00, 0x24, 0x01, 0x24, 0x01, 0xA4, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char a
+        0x06, 0x00, 0x00, 0xFF, 0x01, 0x88, 0x00, 0x04, 0x01, 0x04, 0x01, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char b
+        0x05, 0x00, 0x00, 0xF8, 0x00, 0x04, 0x01, 0x04, 0x01, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char c
+        0x06, 0x00, 0x00, 0xF8, 0x00, 0x04, 0x01, 0x04, 0x01, 0x08, 0x01, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char d
+        0x06, 0x00, 0x00, 0xF8, 0x00, 0x24, 0x01, 0x24, 0x01, 0x24, 0x01, 0xB8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char e
+        0x04, 0x04, 0x00, 0xFE, 0x01, 0x05, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char f
+        0x06, 0x00, 0x00, 0xF8, 0x04, 0x04, 0x05, 0x04, 0x05, 0x88, 0x04, 0xFC, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char g
+        0x06, 0x00, 0x00, 0xFF, 0x01, 0x08, 0x00, 0x04, 0x00, 0x04, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char h
+        0x02, 0x00, 0x00, 0xFD, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char i
+        0x02, 0x00, 0x04, 0xFD, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char j
+        0x06, 0x00, 0x00, 0xFF, 0x01, 0x20, 0x00, 0x30, 0x00, 0xC8, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char k
+        0x02, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char l
+        0x0A, 0x00, 0x00, 0xFC, 0x01, 0x08, 0x00, 0x04, 0x00, 0x04, 0x00, 0xF8, 0x01, 0x08, 0x00, 0x04, 0x00, 0x04, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00,  // Code for char m
+        0x06, 0x00, 0x00, 0xFC, 0x01, 0x08, 0x00, 0x04, 0x00, 0x04, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char n
+        0x06, 0x00, 0x00, 0xF8, 0x00, 0x04, 0x01, 0x04, 0x01, 0x04, 0x01, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char o
+        0x06, 0x00, 0x00, 0xFC, 0x07, 0x88, 0x00, 0x04, 0x01, 0x04, 0x01, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char p
+        0x06, 0x00, 0x00, 0xF8, 0x00, 0x04, 0x01, 0x04, 0x01, 0x88, 0x00, 0xFC, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char q
+        0x04, 0x00, 0x00, 0xFC, 0x01, 0x08, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char r
+        0x06, 0x00, 0x00, 0x98, 0x00, 0x24, 0x01, 0x24, 0x01, 0x24, 0x01, 0xC8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char s
+        0x03, 0x04, 0x00, 0xFF, 0x01, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char t
+        0x06, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char u
+        0x05, 0x0C, 0x00, 0x70, 0x00, 0x80, 0x01, 0x70, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char v
+        0x09, 0x0C, 0x00, 0x70, 0x00, 0x80, 0x01, 0x70, 0x00, 0x0C, 0x00, 0x70, 0x00, 0x80, 0x01, 0x70, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char w
+        0x05, 0x04, 0x01, 0xD8, 0x00, 0x20, 0x00, 0xD8, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char x
+        0x05, 0x0C, 0x00, 0x70, 0x04, 0x80, 0x03, 0x70, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char y
+        0x05, 0x04, 0x01, 0xC4, 0x01, 0x24, 0x01, 0x1C, 0x01, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char z
+        0x03, 0x20, 0x00, 0xDE, 0x03, 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char {
+        0x02, 0x00, 0x00, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char |
+        0x04, 0x00, 0x00, 0x01, 0x04, 0xDE, 0x03, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char }
+        0x07, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ~
+        0x08, 0x00, 0x00, 0xFE, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02, 0x01, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00   // Code for char 
+        };
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ILI9341/Arial24x23.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,110 @@
+//Font Generated by MikroElektronika GLCD Font Creator 1.2.0.0
+//MikroElektronika 2011 
+//http://www.mikroe.com 
+
+//GLCD FontName : @Arial_Unicode_MS24x23
+//GLCD FontSize : 24 x 23
+
+/** Arial Font with 24x23 pixel matrix for uas with the SPI_TFT lib
+*/
+const unsigned char Arial24x23[] = {
+        73,24,23,3,
+        0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char  
+        0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x30, 0x01, 0x00, 0x0F, 0x00, 0xE0, 0x03, 0x00, 0x7C, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char !
+        0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x02, 0x00, 0x00, 0x40, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char "
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x98, 0x03, 0x80, 0xF8, 0x01, 0xC0, 0x78, 0x00, 0xC0, 0x1E, 0x00, 0xC0, 0x1F, 0x02, 0xE0, 0x99, 0x03, 0xF8, 0xF8, 0x01, 0xDE, 0x78, 0x00, 0xC6, 0x1E, 0x00, 0xC2, 0x1F, 0x00, 0xE0, 0x19, 0x00, 0xF8, 0x18, 0x00, 0xDE, 0x00, 0x00, 0xC6, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char #
+        0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0xF0, 0x03, 0xE0, 0x80, 0x0B, 0xF8, 0x01, 0x07, 0x9C, 0xC3, 0x03, 0x0C, 0x3B, 0x03, 0x06, 0x87, 0x01, 0xE6, 0x87, 0x01, 0x1E, 0xC6, 0x00, 0x07, 0x7E, 0x00, 0x0E, 0x3C, 0x00, 0x3E, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char $
+        0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x04, 0xE0, 0x01, 0x06, 0xF8, 0x83, 0x03, 0x1C, 0xC2, 0x01, 0x06, 0x62, 0x00, 0x82, 0x31, 0x00, 0xE2, 0x18, 0x00, 0x7E, 0x0C, 0x00, 0x1C, 0xC6, 0x03, 0x80, 0xF3, 0x07, 0xC0, 0x39, 0x04, 0x60, 0x0C, 0x04, 0x30, 0x04, 0x03, 0x18, 0xE4, 0x01, 0x0C, 0xFC, 0x00, 0x06, 0x10, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char %
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0xF0, 0x01, 0x00, 0xF8, 0x03, 0x00, 0x0C, 0x03, 0x00, 0x06, 0x03, 0x60, 0x02, 0x03, 0xF8, 0x03, 0x03, 0xDC, 0x87, 0x01, 0x8C, 0x8F, 0x01, 0xC6, 0xFC, 0x00, 0xC6, 0xF0, 0x00, 0x6E, 0xF0, 0x03, 0x3E, 0x98, 0x01, 0x1C, 0x0C, 0x01, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char &
+        0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char '
+        0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0x00, 0x1F, 0x3C, 0x80, 0x03, 0x10, 0xE0, 0x00, 0x00, 0x30, 0x00, 0x00, 0x18, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x06, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char (
+        0x09, 0x00, 0x00, 0x18, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x06, 0x00, 0x00, 0x03, 0x00, 0xC0, 0x01, 0x02, 0xF0, 0x00, 0x0F, 0x3E, 0x00, 0xFE, 0x0F, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char )
+        0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0x00, 0x00, 0xD8, 0x00, 0x00, 0x58, 0x00, 0x00, 0x30, 0x00, 0x00, 0x3C, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x52, 0x00, 0x00, 0x18, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char *
+        0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0xC6, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x3F, 0x00, 0xE0, 0x07, 0x00, 0xF0, 0x06, 0x00, 0x10, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char +
+        0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x07, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ,
+        0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char -
+        0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char .
+        0x0D, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0xC0, 0x01, 0x00, 0xF0, 0x00, 0x00, 0x38, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x07, 0x00, 0xC0, 0x01, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char /
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0xFF, 0x03, 0xC0, 0x87, 0x03, 0xF0, 0x00, 0x03, 0x38, 0x00, 0x03, 0x0C, 0x00, 0x03, 0x0C, 0x80, 0x01, 0x06, 0xC0, 0x01, 0x06, 0xE0, 0x00, 0x06, 0x38, 0x00, 0x8E, 0x1F, 0x00, 0xFC, 0x07, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 0
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x02, 0x20, 0xC0, 0x03, 0x30, 0xF8, 0x01, 0x10, 0x3F, 0x00, 0xE8, 0x07, 0x00, 0xFC, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 1
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x80, 0x03, 0x00, 0xC0, 0x03, 0x20, 0x60, 0x03, 0x30, 0x30, 0x03, 0x18, 0x30, 0x03, 0x0C, 0x18, 0x03, 0x04, 0x0C, 0x03, 0x06, 0x0C, 0x03, 0x06, 0x06, 0x03, 0x06, 0x03, 0x01, 0x86, 0x01, 0x00, 0xFE, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 2
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xE0, 0x03, 0x20, 0x00, 0x03, 0x30, 0x00, 0x03, 0x18, 0x00, 0x03, 0x0C, 0x03, 0x03, 0x06, 0x03, 0x01, 0x06, 0x83, 0x01, 0x86, 0xE7, 0x00, 0x86, 0x7E, 0x00, 0xFE, 0x1C, 0x00, 0x7C, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 3
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x30, 0x00, 0x00, 0x38, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x36, 0x00, 0x00, 0x33, 0x00, 0x80, 0x31, 0x00, 0xC0, 0x30, 0x02, 0x60, 0xF0, 0x03, 0x30, 0xF8, 0x01, 0x18, 0x3F, 0x00, 0xEC, 0x37, 0x00, 0xFC, 0x30, 0x00, 0x1E, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 4
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xE1, 0x03, 0xC0, 0x01, 0x03, 0xF0, 0x01, 0x03, 0xBE, 0x00, 0x03, 0xCE, 0x00, 0x03, 0xC6, 0x80, 0x01, 0xC6, 0xC0, 0x01, 0xC6, 0xE1, 0x00, 0xC6, 0x7F, 0x00, 0x86, 0x1F, 0x00, 0x06, 0x02, 0x00, 0x06, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 5
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0xFF, 0x01, 0xC0, 0x87, 0x03, 0xF0, 0x02, 0x03, 0x38, 0x03, 0x03, 0x9C, 0x01, 0x03, 0x8C, 0x81, 0x01, 0x86, 0x81, 0x01, 0x86, 0xE3, 0x00, 0x86, 0x7F, 0x00, 0x06, 0x1F, 0x00, 0x1E, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 6
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x80, 0x03, 0x00, 0xE0, 0x01, 0x04, 0x70, 0x00, 0x06, 0x3C, 0x00, 0x06, 0x0E, 0x00, 0x06, 0x07, 0x00, 0x86, 0x01, 0x00, 0xC6, 0x00, 0x00, 0x66, 0x00, 0x00, 0x36, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 7
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0xF8, 0x01, 0x00, 0xFC, 0x03, 0x00, 0x0C, 0x03, 0xE0, 0x06, 0x03, 0xF8, 0x03, 0x03, 0x9C, 0x03, 0x03, 0x0C, 0x83, 0x01, 0x06, 0x83, 0x01, 0x06, 0xE7, 0x00, 0x86, 0x7F, 0x00, 0xFE, 0x3C, 0x00, 0x7C, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 8
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0xC0, 0x01, 0x00, 0x81, 0x03, 0xE0, 0x07, 0x03, 0xF0, 0x0F, 0x03, 0x18, 0x0C, 0x03, 0x0C, 0x0C, 0x03, 0x0C, 0x8C, 0x01, 0x06, 0xC4, 0x00, 0x06, 0x66, 0x00, 0x06, 0x3A, 0x00, 0x8E, 0x1F, 0x00, 0xFC, 0x07, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 9
+        0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0xC0, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char :
+        0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x07, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0xC0, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ;
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x0D, 0x00, 0x80, 0x1D, 0x00, 0x80, 0x19, 0x00, 0xC0, 0x38, 0x00, 0xC0, 0x30, 0x00, 0x40, 0x70, 0x00, 0x60, 0x20, 0x00, 0x60, 0x00, 0x00, 0x30, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char <
+        0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x80, 0x18, 0x00, 0xC0, 0x18, 0x00, 0xC0, 0x18, 0x00, 0xC0, 0x18, 0x00, 0xC0, 0x18, 0x00, 0xC0, 0x18, 0x00, 0xC0, 0x18, 0x00, 0xC0, 0x18, 0x00, 0xC0, 0x18, 0x00, 0xC0, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char =
+        0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x20, 0x00, 0x00, 0x30, 0x00, 0x20, 0x30, 0x00, 0x70, 0x18, 0x00, 0x60, 0x18, 0x00, 0xE0, 0x18, 0x00, 0xC0, 0x0C, 0x00, 0xC0, 0x0D, 0x00, 0x80, 0x05, 0x00, 0x80, 0x07, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char >
+        0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x02, 0x30, 0x20, 0x03, 0x18, 0x38, 0x01, 0x0C, 0x3C, 0x00, 0x04, 0x0C, 0x00, 0x06, 0x06, 0x00, 0x06, 0x03, 0x00, 0x06, 0x01, 0x00, 0x86, 0x01, 0x00, 0xFE, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ?
+        0x17, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x0F, 0x00, 0x3E, 0x1E, 0x00, 0x07, 0x38, 0x80, 0x01, 0x30, 0xC0, 0xC0, 0x70, 0x60, 0xF8, 0x71, 0x30, 0xBC, 0x63, 0x18, 0x06, 0x63, 0x18, 0x03, 0x63, 0x8C, 0x01, 0x61, 0x8C, 0x81, 0x61, 0xC4, 0x80, 0x60, 0xC6, 0xC0, 0x63, 0xC6, 0xE0, 0x63, 0xC6, 0x79, 0x33, 0x86, 0x1F, 0x33, 0x86, 0x87, 0x11, 0xC6, 0x81, 0x18, 0xCE, 0xC0, 0x08, 0x0C, 0x70, 0x0C, 0xFC, 0x3F, 0x04, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0x00,  // Code for char @
+        0x0F, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0xC0, 0x01, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x1E, 0x00, 0x80, 0x1B, 0x00, 0xC0, 0x19, 0x00, 0x60, 0x18, 0x00, 0x38, 0x18, 0x00, 0x1C, 0x18, 0x00, 0x06, 0x18, 0x00, 0xFE, 0xFF, 0x03, 0xFE, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char A
+        0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x03, 0x00, 0x3F, 0x03, 0xE0, 0x07, 0x03, 0xFC, 0x03, 0x03, 0x1E, 0x03, 0x03, 0x06, 0x03, 0x03, 0x06, 0x03, 0x03, 0x06, 0x03, 0x01, 0x06, 0x83, 0x01, 0x06, 0xC7, 0x00, 0x86, 0x7E, 0x00, 0xFE, 0x3C, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char B
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0xFF, 0x01, 0xC0, 0xC7, 0x01, 0xE0, 0x80, 0x03, 0x30, 0x00, 0x03, 0x18, 0x00, 0x03, 0x0C, 0x00, 0x03, 0x0C, 0x00, 0x03, 0x06, 0x80, 0x01, 0x06, 0x80, 0x01, 0x06, 0xC0, 0x00, 0x06, 0xE0, 0x00, 0x06, 0x30, 0x00, 0x1E, 0x10, 0x00, 0x7C, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char C
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x03, 0x00, 0x3F, 0x03, 0xE0, 0x07, 0x03, 0xFC, 0x00, 0x03, 0x1E, 0x00, 0x03, 0x06, 0x00, 0x03, 0x06, 0x00, 0x03, 0x06, 0x80, 0x01, 0x06, 0x80, 0x01, 0x06, 0xC0, 0x00, 0x06, 0x60, 0x00, 0x0E, 0x38, 0x00, 0x9E, 0x1F, 0x00, 0xFC, 0x07, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char D
+        0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x03, 0x00, 0x3F, 0x03, 0xE0, 0x07, 0x03, 0xFC, 0x03, 0x03, 0x1E, 0x03, 0x03, 0x06, 0x03, 0x03, 0x06, 0x03, 0x03, 0x06, 0x03, 0x03, 0x06, 0x03, 0x03, 0x06, 0x03, 0x03, 0x06, 0x03, 0x01, 0x06, 0x03, 0x00, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char E
+        0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xE0, 0x07, 0x00, 0xFC, 0x03, 0x00, 0x1E, 0x03, 0x00, 0x06, 0x03, 0x00, 0x06, 0x03, 0x00, 0x06, 0x03, 0x00, 0x06, 0x03, 0x00, 0x06, 0x03, 0x00, 0x06, 0x03, 0x00, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char F
+        0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0xFF, 0x00, 0xC0, 0xE7, 0x01, 0xE0, 0x80, 0x01, 0x30, 0x80, 0x03, 0x18, 0x00, 0x03, 0x18, 0x00, 0x03, 0x0C, 0x00, 0x03, 0x0C, 0x00, 0x03, 0x06, 0x04, 0x03, 0x06, 0x86, 0x01, 0x06, 0x86, 0x01, 0x06, 0x86, 0x01, 0x06, 0xC6, 0x00, 0x0E, 0xFE, 0x00, 0x1E, 0x3E, 0x00, 0x7C, 0x06, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char G
+        0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xE0, 0x07, 0x00, 0xFC, 0x03, 0x00, 0x1E, 0x03, 0x00, 0x02, 0x03, 0x00, 0x00, 0x03, 0x00, 0x00, 0x03, 0x00, 0x00, 0x03, 0x02, 0x00, 0xC3, 0x03, 0x00, 0xFB, 0x01, 0x00, 0x3F, 0x00, 0xE0, 0x07, 0x00, 0xFC, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char H
+        0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xE0, 0x07, 0x00, 0xFC, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char I
+        0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0xE0, 0x03, 0x00, 0xA0, 0x03, 0x00, 0x00, 0x03, 0x00, 0x00, 0x03, 0x00, 0x80, 0x01, 0x00, 0xC0, 0x01, 0x00, 0x78, 0x00, 0x00, 0x1F, 0x00, 0xE0, 0x07, 0x00, 0xFC, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char J
+        0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xE0, 0x0F, 0x00, 0xFC, 0x0C, 0x00, 0x1E, 0x06, 0x00, 0x02, 0x03, 0x00, 0x80, 0x0F, 0x00, 0x80, 0x1D, 0x00, 0xC0, 0x78, 0x00, 0x60, 0xE0, 0x01, 0x30, 0x80, 0x03, 0x10, 0x00, 0x02, 0x18, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char K
+        0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x03, 0x00, 0x3F, 0x03, 0xE0, 0x07, 0x03, 0xFC, 0x00, 0x03, 0x1E, 0x00, 0x03, 0x02, 0x00, 0x03, 0x00, 0x00, 0x03, 0x00, 0x00, 0x03, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char L
+        0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xE0, 0x07, 0x00, 0xFC, 0x00, 0x00, 0x1E, 0xF0, 0x03, 0xFE, 0xFF, 0x03, 0xFE, 0x8F, 0x03, 0x00, 0xC0, 0x01, 0x00, 0x70, 0x00, 0x00, 0x38, 0x00, 0x00, 0x0E, 0x00, 0x80, 0x07, 0x02, 0xC0, 0xC1, 0x03, 0x70, 0xF8, 0x01, 0x38, 0x3F, 0x00, 0xEE, 0x07, 0x00, 0xFE, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char M
+        0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xE0, 0x07, 0x00, 0xFC, 0x00, 0x00, 0x1E, 0x00, 0x00, 0xFE, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0xFF, 0x01, 0x00, 0xF0, 0x03, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xE0, 0x07, 0x00, 0xFC, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char N
+        0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0xFF, 0x00, 0xC0, 0xC3, 0x01, 0xE0, 0x80, 0x03, 0x30, 0x00, 0x03, 0x18, 0x00, 0x03, 0x0C, 0x00, 0x03, 0x0C, 0x00, 0x03, 0x04, 0x00, 0x03, 0x06, 0x80, 0x01, 0x06, 0x80, 0x01, 0x06, 0xC0, 0x00, 0x06, 0xC0, 0x00, 0x06, 0x70, 0x00, 0x0E, 0x38, 0x00, 0x3C, 0x0E, 0x00, 0xF8, 0x07, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char O
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xE0, 0x07, 0x00, 0xFC, 0x06, 0x00, 0x1E, 0x06, 0x00, 0x06, 0x06, 0x00, 0x06, 0x06, 0x00, 0x06, 0x06, 0x00, 0x06, 0x06, 0x00, 0x06, 0x06, 0x00, 0x06, 0x03, 0x00, 0x86, 0x03, 0x00, 0xFE, 0x01, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char P
+        0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0xFF, 0x00, 0xC0, 0xE7, 0x01, 0xE0, 0x80, 0x03, 0x30, 0x00, 0x03, 0x18, 0x00, 0x03, 0x0C, 0x00, 0x03, 0x0C, 0x40, 0x03, 0x04, 0x60, 0x03, 0x06, 0xC0, 0x01, 0x06, 0xC0, 0x01, 0x06, 0xC0, 0x03, 0x06, 0x60, 0x07, 0x06, 0x70, 0x02, 0x0E, 0x38, 0x00, 0x3C, 0x0E, 0x00, 0xF8, 0x07, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Q
+        0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xE0, 0x07, 0x00, 0xFC, 0x03, 0x00, 0x1E, 0x03, 0x00, 0x06, 0x03, 0x00, 0x06, 0x03, 0x00, 0x06, 0x03, 0x00, 0x06, 0x0F, 0x00, 0x06, 0x7F, 0x00, 0x06, 0xFB, 0x03, 0x86, 0x81, 0x03, 0x86, 0x01, 0x00, 0xFE, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char R
+        0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0xF0, 0x01, 0x00, 0x80, 0x03, 0xE0, 0x00, 0x03, 0xF8, 0x01, 0x03, 0x9C, 0x03, 0x03, 0x0C, 0x03, 0x03, 0x06, 0x03, 0x03, 0x06, 0x83, 0x01, 0x06, 0x87, 0x01, 0x06, 0xC6, 0x00, 0x06, 0x7E, 0x00, 0x3E, 0x3C, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char S
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x06, 0x00, 0x02, 0x06, 0xC0, 0x03, 0x06, 0xF8, 0x01, 0x06, 0x3F, 0x00, 0xE6, 0x07, 0x00, 0xFE, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char T
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0xFF, 0x03, 0xE0, 0x07, 0x03, 0xFC, 0x00, 0x03, 0x1E, 0x00, 0x03, 0x02, 0x00, 0x03, 0x00, 0x00, 0x03, 0x00, 0x00, 0x03, 0x00, 0x80, 0x01, 0x00, 0xE0, 0x00, 0x00, 0x78, 0x00, 0x00, 0x1F, 0x00, 0xE0, 0x07, 0x00, 0xFC, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char U
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x03, 0xFE, 0xFF, 0x03, 0x00, 0x00, 0x03, 0x00, 0xC0, 0x01, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x07, 0x00, 0x80, 0x03, 0x00, 0xC0, 0x01, 0x00, 0x70, 0x00, 0x00, 0x38, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char V
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x03, 0xF0, 0xFF, 0x03, 0xFE, 0xFF, 0x03, 0x0E, 0xC0, 0x01, 0x00, 0x70, 0x00, 0x00, 0x38, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x07, 0x00, 0xC0, 0x01, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0x00, 0x1C, 0xC0, 0x03, 0xFE, 0xFF, 0x03, 0xFE, 0xBF, 0x03, 0x1E, 0xC0, 0x01, 0x00, 0x70, 0x00, 0x00, 0x38, 0x00, 0x00, 0x0E, 0x00, 0x80, 0x07, 0x00, 0xE0, 0x01, 0x00, 0x78, 0x00, 0x00, 0x1E, 0x00, 0x00,  // Code for char W
+        0x16, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x80, 0x01, 0x00, 0xC0, 0x00, 0x00, 0x60, 0x00, 0x00, 0x30, 0x00, 0x06, 0x38, 0x00, 0x1E, 0x18, 0x00, 0xFC, 0x0C, 0x00, 0xE0, 0x07, 0x00, 0x80, 0x1F, 0x00, 0x80, 0x7D, 0x00, 0xC0, 0xF0, 0x01, 0x60, 0xC0, 0x03, 0x30, 0x00, 0x02, 0x30, 0x00, 0x00, 0x18, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char X
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x3E, 0x00, 0x02, 0xF8, 0xC0, 0x03, 0xE0, 0xFB, 0x01, 0x80, 0x3F, 0x00, 0x00, 0x06, 0x00, 0x00, 0x03, 0x00, 0x80, 0x01, 0x00, 0xC0, 0x00, 0x00, 0x60, 0x00, 0x00, 0x30, 0x00, 0x00, 0x18, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Y
+        0x14, 0x00, 0x00, 0x02, 0x00, 0x80, 0x03, 0x00, 0xC0, 0x03, 0x00, 0x60, 0x03, 0x00, 0x60, 0x03, 0x00, 0x30, 0x03, 0x04, 0x18, 0x03, 0x06, 0x0C, 0x03, 0x06, 0x0C, 0x03, 0x06, 0x06, 0x03, 0x06, 0x03, 0x03, 0x86, 0x01, 0x03, 0x86, 0x01, 0x03, 0xC6, 0x00, 0x03, 0x66, 0x00, 0x01, 0x36, 0x00, 0x00, 0x36, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Z
+        0x0C, 0x00, 0x00, 0x78, 0x00, 0x00, 0x7E, 0x00, 0xC0, 0x67, 0x00, 0xF8, 0x61, 0x00, 0x3F, 0x20, 0xE0, 0x07, 0x00, 0xFC, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char [
+        0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x03, 0xFE, 0xFF, 0x03, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char BackSlash
+        0x0B, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x78, 0x00, 0x00, 0x3E, 0x00, 0xC0, 0x07, 0x04, 0xF8, 0x01, 0x06, 0x3F, 0x00, 0xE6, 0x07, 0x00, 0xFE, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ]
+        0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x80, 0x03, 0x00, 0xC0, 0x01, 0x00, 0x60, 0x00, 0x00, 0x38, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x0E, 0x00, 0x00, 0xFE, 0x03, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ^
+        0x15, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char _
+        0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char `
+        0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0xF0, 0x03, 0x00, 0x32, 0x03, 0x00, 0x1B, 0x03, 0x80, 0x19, 0x03, 0xC0, 0x18, 0x01, 0xC0, 0x98, 0x01, 0xC0, 0x8C, 0x00, 0xC0, 0xEC, 0x03, 0xC0, 0xFC, 0x03, 0xC0, 0x3F, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char a
+        0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x01, 0x00, 0xBF, 0x01, 0xE0, 0x07, 0x03, 0xFC, 0x01, 0x03, 0x9E, 0x01, 0x03, 0xC2, 0x00, 0x01, 0xC0, 0x80, 0x01, 0xC0, 0xC0, 0x00, 0xC0, 0x79, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char b
+        0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0xFE, 0x03, 0x00, 0x07, 0x03, 0x80, 0x01, 0x03, 0x80, 0x00, 0x03, 0xC0, 0x80, 0x01, 0xC0, 0xC0, 0x01, 0xC0, 0x41, 0x00, 0xC0, 0x03, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char c
+        0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0xDE, 0x03, 0x00, 0x03, 0x03, 0x80, 0x01, 0x03, 0x80, 0x00, 0x03, 0xC0, 0x80, 0x01, 0xC0, 0x80, 0x02, 0xC0, 0xE0, 0x03, 0xC0, 0xFF, 0x01, 0x00, 0x3F, 0x00, 0xE0, 0x07, 0x00, 0xFC, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char d
+        0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0xFE, 0x03, 0x00, 0x0F, 0x03, 0x80, 0x0D, 0x03, 0x80, 0x0C, 0x03, 0xC0, 0x0C, 0x03, 0xC0, 0x8C, 0x01, 0xC0, 0xCC, 0x00, 0xC0, 0x4D, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char e
+        0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x80, 0xC0, 0x03, 0xC0, 0xF8, 0x01, 0xC0, 0x3F, 0x00, 0xE0, 0x07, 0x00, 0xF8, 0x00, 0x00, 0xDC, 0x00, 0x00, 0xC6, 0x00, 0x00, 0xC6, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char f
+        0x0F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x38, 0x00, 0x00, 0x78, 0x00, 0xF8, 0x61, 0x00, 0xFE, 0x63, 0x00, 0x07, 0x63, 0x80, 0x01, 0x63, 0x80, 0x01, 0x33, 0xC0, 0x00, 0x39, 0xC0, 0x80, 0x1E, 0xC0, 0xE0, 0x07, 0x80, 0xFD, 0x01, 0x00, 0x3F, 0x00, 0xC0, 0x07, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char g
+        0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xE0, 0x07, 0x00, 0xFC, 0x01, 0x00, 0x9E, 0x01, 0x00, 0xC2, 0x00, 0x00, 0xC0, 0x00, 0x02, 0xC0, 0xC0, 0x03, 0xC0, 0xF9, 0x01, 0xC0, 0x3F, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char h
+        0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xC0, 0x07, 0x00, 0xC4, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char i
+        0x09, 0x00, 0x00, 0x38, 0x00, 0x00, 0x1E, 0x00, 0xC0, 0x07, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xC0, 0x07, 0x00, 0xC4, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char j
+        0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xE0, 0x1F, 0x00, 0xFC, 0x18, 0x00, 0x1E, 0x3C, 0x00, 0x02, 0xE6, 0x01, 0x00, 0xC2, 0x03, 0x00, 0x03, 0x02, 0x80, 0x01, 0x00, 0xC0, 0x00, 0x00, 0x40, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char k
+        0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xE0, 0x07, 0x00, 0xFC, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char l
+        0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xC0, 0x07, 0x00, 0xC0, 0x01, 0x00, 0x80, 0x00, 0x00, 0xC0, 0x00, 0x02, 0xC0, 0xC0, 0x03, 0xC0, 0xF8, 0x01, 0xC0, 0x3F, 0x00, 0x80, 0x07, 0x00, 0x80, 0x01, 0x00, 0x80, 0x00, 0x00, 0xC0, 0x00, 0x02, 0xC0, 0xC0, 0x03, 0xC0, 0xF8, 0x01, 0xC0, 0x3F, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char m
+        0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xC0, 0x07, 0x00, 0xC0, 0x01, 0x00, 0x80, 0x01, 0x00, 0xC0, 0x00, 0x00, 0xC0, 0x00, 0x02, 0xC0, 0xC0, 0x03, 0xC0, 0xF9, 0x01, 0xC0, 0x3F, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char n
+        0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0xDE, 0x03, 0x00, 0x03, 0x03, 0x80, 0x01, 0x03, 0x80, 0x00, 0x03, 0xC0, 0x00, 0x01, 0xC0, 0x80, 0x01, 0xC0, 0xC0, 0x00, 0xC0, 0x79, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char o
+        0x0E, 0x00, 0x00, 0x78, 0x00, 0x00, 0x3E, 0x00, 0xC0, 0x07, 0x00, 0xF8, 0x01, 0x00, 0xFF, 0x03, 0xC0, 0x07, 0x03, 0xC0, 0x01, 0x03, 0x80, 0x00, 0x03, 0xC0, 0x00, 0x01, 0xC0, 0x80, 0x01, 0xC0, 0xE0, 0x00, 0xC0, 0x7F, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char p
+        0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0xFE, 0x03, 0x00, 0x07, 0x03, 0x80, 0x01, 0x03, 0x80, 0x00, 0x43, 0xC0, 0x00, 0x71, 0xC0, 0x80, 0x3E, 0xC0, 0xE0, 0x07, 0x80, 0xFF, 0x01, 0x00, 0x3F, 0x00, 0xC0, 0x07, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char q
+        0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xC0, 0x07, 0x00, 0xC0, 0x01, 0x00, 0x80, 0x00, 0x00, 0xC0, 0x00, 0x00, 0xC0, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char r
+        0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x8F, 0x03, 0x80, 0x0F, 0x03, 0x80, 0x1D, 0x03, 0xC0, 0x18, 0x03, 0xC0, 0x98, 0x01, 0xC0, 0xF8, 0x01, 0xC0, 0xF1, 0x00, 0xC0, 0x03, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char s
+        0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0x03, 0xC0, 0xF8, 0x03, 0xC0, 0x3F, 0x03, 0xE0, 0x07, 0x03, 0xF8, 0x00, 0x00, 0xDC, 0x00, 0x00, 0xC0, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char t
+        0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0xF8, 0x03, 0x00, 0xBF, 0x03, 0xC0, 0x07, 0x03, 0xC0, 0x00, 0x03, 0x00, 0x00, 0x01, 0x00, 0x80, 0x01, 0x00, 0x80, 0x02, 0x00, 0xE0, 0x03, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xC0, 0x07, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char u
+        0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0xC0, 0xFF, 0x03, 0x00, 0x80, 0x03, 0x00, 0xC0, 0x01, 0x00, 0x70, 0x00, 0x00, 0x38, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x07, 0x00, 0x80, 0x03, 0x00, 0xC0, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char v
+        0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x03, 0xC0, 0xFF, 0x03, 0xC0, 0x9F, 0x03, 0x00, 0xC0, 0x01, 0x00, 0x70, 0x00, 0x00, 0x38, 0x00, 0x00, 0x0E, 0x00, 0x80, 0x07, 0x00, 0xC0, 0xFD, 0x03, 0xC0, 0xFF, 0x03, 0xC0, 0x9F, 0x03, 0x00, 0xC0, 0x01, 0x00, 0x70, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x0E, 0x00, 0x80, 0x03, 0x00, 0xC0, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char w
+        0x10, 0x00, 0x00, 0x02, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x80, 0x01, 0x40, 0xC0, 0x00, 0xC0, 0x61, 0x00, 0xC0, 0x37, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x78, 0x00, 0x00, 0xEC, 0x03, 0x00, 0x86, 0x03, 0x00, 0x03, 0x02, 0x80, 0x01, 0x00, 0xC0, 0x00, 0x00, 0x40, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char x
+        0x0F, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x60, 0x00, 0x00, 0x38, 0xC0, 0xFF, 0x1F, 0xC0, 0xFF, 0x07, 0x00, 0xF8, 0x03, 0x00, 0xC0, 0x01, 0x00, 0x70, 0x00, 0x00, 0x38, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x07, 0x00, 0x80, 0x03, 0x00, 0xC0, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char y
+        0x0F, 0x00, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x80, 0x03, 0x80, 0xC0, 0x03, 0xC0, 0x60, 0x03, 0xC0, 0x20, 0x03, 0xC0, 0x30, 0x03, 0xC0, 0x18, 0x03, 0xC0, 0x0C, 0x03, 0xC0, 0x04, 0x03, 0xC0, 0x06, 0x03, 0xC0, 0x03, 0x01, 0xC0, 0x01, 0x00, 0xC0, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char z
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x1E, 0x00, 0xFC, 0x3F, 0x00, 0xFE, 0x10, 0x00, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x78, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x06, 0x00, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00,  // Code for char {
+        0x0A, 0x00, 0x00, 0x40, 0x00, 0x00, 0x78, 0x00, 0x00, 0x3E, 0x00, 0xC0, 0x07, 0x00, 0xF8, 0x01, 0x00, 0x3F, 0x00, 0xE0, 0x07, 0x00, 0xFC, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char |
+        0x08, 0x00, 0x00, 0x10, 0x00, 0x00, 0x08, 0x00, 0x00, 0x0F, 0x00, 0xC0, 0x03, 0x00, 0x70, 0x00, 0x82, 0x1B, 0x00, 0xF7, 0x0F, 0x00, 0x3E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char }
+        0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x06, 0x00, 0x00, 0x03, 0x00, 0x00, 0x03, 0x00, 0x00, 0x03, 0x00, 0x00, 0x07, 0x00, 0x00, 0x07, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ~
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00   // Code for char 
+        };
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ILI9341/Arial28x28.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,495 @@
+//Font Generated by MikroElektronika GLCD Font Creator 1.2.0.0
+//MikroElektronika 2011 
+//http://www.mikroe.com 
+
+//GLCD FontName : @Arial_Unicode_MS28x28
+//GLCD FontSize : 28 x 28
+
+/** Arial Font italic with 27*28 pixel matrix for use with SPI_TFT lib
+*/
+__align(2)
+const unsigned char Arial28x28[] = {
+113,28,28,4,
+0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char
+  
+0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x3F, 0x38, 0x00, 0xFE, 0x7F, 0x38, 0x00, 0xFE, 0x3F, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char !
+
+0x09, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 
+0x00, 0xFE, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char "
+
+0x0F, 0x80, 0xC1, 0x00, 0x00, 0x80, 0xC1, 0x38, 0x00, 0x80, 0xC1, 0x3F, 0x00, 0x80, 0xFF, 0x07, 0x00, 0xF8, 0xFF, 0x00, 0x00, 0xFE, 0xC1, 0x00, 0x00, 0x8E, 0xC1, 0x00, 
+0x00, 0x80, 0xC1, 0x00, 0x00, 0x80, 0xC1, 0x38, 0x00, 0x80, 0xC1, 0x3F, 0x00, 0x80, 0xFF, 0x07, 0x00, 0xF8, 0xFF, 0x00, 0x00, 0xFE, 0xC1, 0x00, 0x00, 0x8E, 0xC1, 0x00, 0x00, 
+0x80, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char #
+
+0x0F, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x81, 0x03, 0x00, 0xF8, 0x83, 0x0F, 0x00, 0xFC, 0x87, 0x1F, 0x00, 0x0C, 0x07, 0x1E, 0x00, 0x06, 0x0E, 0x38, 0x00, 0x06, 0x0E, 0x30, 
+0x00, 0xFF, 0xFF, 0xFF, 0x01, 0xFF, 0xFF, 0xFF, 0x01, 0x06, 0x1C, 0x30, 0x00, 0x0E, 0x1C, 0x38, 0x00, 0x1C, 0x38, 0x1C, 0x00, 0x7C, 0xF8, 0x1F, 0x00, 0x78, 0xF0, 0x0F, 0x00, 
+0x60, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char $
+
+0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0x0E, 0x0E, 0x00, 0x00, 0x06, 0x0C, 0x00, 0x00, 0x06, 0x0C, 0x40, 
+0x00, 0x06, 0x0C, 0x70, 0x00, 0x0E, 0x06, 0x3C, 0x00, 0xFC, 0x07, 0x0F, 0x00, 0xF0, 0x81, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 
+0x80, 0x07, 0x00, 0x00, 0xC0, 0x81, 0x0F, 0x00, 0xF0, 0xE0, 0x3F, 0x00, 0x3C, 0x70, 0x70, 0x00, 0x0E, 0x30, 0x60, 0x00, 0x02, 0x30, 0x60, 0x00, 0x00, 0x30, 0x60, 0x00, 0x00, 
+0x70, 0x70, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char %
+
+0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x70, 0xF8, 0x1F, 0x00, 0xFC, 0x39, 0x1C, 0x00, 0xFC, 0x0F, 0x38, 0x00, 0x0E, 0x0F, 0x30, 
+0x00, 0x06, 0x0E, 0x30, 0x00, 0x06, 0x1E, 0x30, 0x00, 0x0E, 0x3B, 0x38, 0x00, 0xFE, 0x73, 0x18, 0x00, 0xFC, 0xE1, 0x1C, 0x00, 0x78, 0xC0, 0x0F, 0x00, 0x00, 0xC0, 0x07, 0x00, 
+0x00, 0xF0, 0x07, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x30, 0x1C, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char &
+
+0x04, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char '
+
+0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 
+0x80, 0xFF, 0x1F, 0x00, 0xE0, 0x03, 0x7C, 0x00, 0x78, 0x00, 0xE0, 0x01, 0x1C, 0x00, 0x80, 0x03, 0x0E, 0x00, 0x00, 0x07, 0x04, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char (
+
+0x05, 0x1C, 0x00, 0x80, 0x03, 0x78, 0x00, 0xE0, 0x01, 0xE0, 0x03, 0x7C, 0x00, 0x80, 0xFF, 0x1F, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char )
+
+0x0A, 0x10, 0x00, 0x00, 0x00, 0x18, 0x01, 0x00, 0x00, 0xB0, 0x03, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 
+0x00, 0xB0, 0x03, 0x00, 0x00, 0x18, 0x01, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char *
+
+0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 
+0x00, 0xE0, 0xFF, 0x07, 0x00, 0xE0, 0xFF, 0x07, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 
+0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char +
+
+0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x02, 0x00, 0x00, 0x38, 0x03, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ,
+
+0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0xE0, 0x00, 
+0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char -
+
+0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char .
+
+0x08, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0xFC, 0x01, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x3E, 0x00, 0x00, 
+0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char /
+
+0x0F, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0xF8, 0xFF, 0x0F, 0x00, 0x7C, 0x00, 0x1F, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0x0E, 0x00, 0x38, 
+0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0x7C, 0x00, 0x1F, 0x00, 0xF8, 0xFF, 0x0F, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0xC0, 0xFF, 0x01, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 0
+
+0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 
+0x00, 0xFC, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 1
+
+0x0F, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x30, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x1C, 0x00, 0x3F, 0x00, 0x0E, 0x80, 0x3B, 0x00, 0x0E, 0xC0, 0x39, 
+0x00, 0x0E, 0xE0, 0x38, 0x00, 0x0E, 0x70, 0x38, 0x00, 0x0E, 0x3C, 0x38, 0x00, 0x1E, 0x1E, 0x38, 0x00, 0xFC, 0x0F, 0x38, 0x00, 0xF8, 0x03, 0x38, 0x00, 0xF0, 0x01, 0x38, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 2
+
+0x0F, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x03, 0x00, 0x78, 0x00, 0x0F, 0x00, 0x7C, 0x00, 0x1F, 0x00, 0x1C, 0x00, 0x1E, 0x00, 0x0E, 0x00, 0x3C, 0x00, 0x0E, 0x1C, 0x38, 
+0x00, 0x0E, 0x1C, 0x38, 0x00, 0x0E, 0x1C, 0x38, 0x00, 0x1E, 0x1E, 0x3C, 0x00, 0xFC, 0x3F, 0x1C, 0x00, 0xF8, 0xF3, 0x1F, 0x00, 0xF0, 0xF1, 0x0F, 0x00, 0x00, 0xC0, 0x03, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 3
+
+0x0F, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0xCE, 0x01, 0x00, 0x00, 0xC7, 0x01, 0x00, 0xC0, 0xC3, 0x01, 0x00, 0xE0, 0xC0, 0x01, 
+0x00, 0x70, 0xC0, 0x01, 0x00, 0x1C, 0xC0, 0x01, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x00, 0xC0, 0x01, 0x00, 
+0x00, 0xC0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 4
+
+0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x03, 0x00, 0xF0, 0x1F, 0x0F, 0x00, 0xFE, 0x1F, 0x1F, 0x00, 0xFE, 0x0E, 0x1E, 0x00, 0x0E, 0x06, 0x38, 0x00, 0x0E, 0x07, 0x38, 
+0x00, 0x0E, 0x07, 0x38, 0x00, 0x0E, 0x07, 0x38, 0x00, 0x0E, 0x0F, 0x3C, 0x00, 0x0E, 0x1E, 0x1E, 0x00, 0x0E, 0xFE, 0x1F, 0x00, 0x0E, 0xFC, 0x07, 0x00, 0x00, 0xF0, 0x03, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 5
+
+0x0F, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0xF8, 0xFF, 0x0F, 0x00, 0x7C, 0x38, 0x1E, 0x00, 0x1C, 0x1C, 0x3C, 0x00, 0x0E, 0x0E, 0x38, 
+0x00, 0x0E, 0x0E, 0x38, 0x00, 0x0E, 0x0E, 0x38, 0x00, 0x0E, 0x1E, 0x3C, 0x00, 0x1E, 0x3E, 0x1E, 0x00, 0x3C, 0xFC, 0x1F, 0x00, 0x38, 0xF8, 0x0F, 0x00, 0x30, 0xE0, 0x03, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 6
+
+0x0F, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x3C, 0x00, 0x0E, 0xC0, 0x3F, 0x00, 0x0E, 0xF8, 0x3F, 
+0x00, 0x0E, 0xFE, 0x03, 0x00, 0x8E, 0x3F, 0x00, 0x00, 0xCE, 0x07, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 7
+
+0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0xF0, 0xE1, 0x0F, 0x00, 0xF8, 0xF7, 0x1F, 0x00, 0xFC, 0x37, 0x1C, 0x00, 0x1E, 0x1E, 0x3C, 0x00, 0x0E, 0x1C, 0x38, 
+0x00, 0x0E, 0x1C, 0x38, 0x00, 0x0E, 0x1C, 0x38, 0x00, 0x1E, 0x3E, 0x38, 0x00, 0xFC, 0x37, 0x1C, 0x00, 0xF8, 0xF7, 0x1F, 0x00, 0xF0, 0xE1, 0x0F, 0x00, 0x00, 0xC0, 0x07, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 8
+
+0x0F, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x06, 0x00, 0xF8, 0x0F, 0x0E, 0x00, 0xFC, 0x1F, 0x1E, 0x00, 0x3C, 0x3E, 0x3C, 0x00, 0x1E, 0x3C, 0x38, 0x00, 0x0E, 0x38, 0x38, 
+0x00, 0x0E, 0x38, 0x38, 0x00, 0x0E, 0x38, 0x38, 0x00, 0x1E, 0x1C, 0x1C, 0x00, 0x3C, 0x0E, 0x1F, 0x00, 0xF8, 0xFF, 0x0F, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0xC0, 0xFF, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 9
+
+0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 0x38, 0x00, 0x80, 0x03, 0x38, 0x00, 0x80, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char :
+
+0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 0x38, 0x02, 0x80, 0x03, 0x38, 0x03, 0x80, 0x03, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ;
+
+0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x63, 0x00, 
+0x00, 0x00, 0x63, 0x00, 0x00, 0x80, 0xC1, 0x00, 0x00, 0x80, 0xC1, 0x00, 0x00, 0xC0, 0x80, 0x01, 0x00, 0xC0, 0x80, 0x01, 0x00, 0x60, 0x00, 0x03, 0x00, 0x60, 0x00, 0x03, 0x00, 
+0x30, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char <
+
+0x0F, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC1, 0x00, 0x00, 0x80, 0xC1, 0x00, 0x00, 0x80, 0xC1, 0x00, 0x00, 0x80, 0xC1, 0x00, 0x00, 0x80, 0xC1, 0x00, 0x00, 0x80, 0xC1, 0x00, 
+0x00, 0x80, 0xC1, 0x00, 0x00, 0x80, 0xC1, 0x00, 0x00, 0x80, 0xC1, 0x00, 0x00, 0x80, 0xC1, 0x00, 0x00, 0x80, 0xC1, 0x00, 0x00, 0x80, 0xC1, 0x00, 0x00, 0x80, 0xC1, 0x00, 0x00, 
+0x80, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char =
+
+0x0F, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x03, 0x00, 0x60, 0x80, 0x01, 0x00, 0x60, 0x80, 0x01, 0x00, 0xC0, 0x80, 0x01, 0x00, 0xC0, 0xC0, 0x00, 0x00, 0x80, 0xC1, 0x00, 
+0x00, 0x80, 0x61, 0x00, 0x00, 0x00, 0x63, 0x00, 0x00, 0x00, 0x63, 0x00, 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 
+0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char >
+
+0x0E, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x06, 0xC0, 0x39, 
+0x00, 0x06, 0xF0, 0x39, 0x00, 0x06, 0x78, 0x38, 0x00, 0x0E, 0x3C, 0x00, 0x00, 0x1C, 0x0E, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ?
+
+0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x07, 0x00, 0x00, 0xFE, 0x3F, 0x00, 0x80, 0x07, 0x78, 0x00, 0xE0, 0x01, 0xE0, 0x00, 0x70, 0x00, 0xC0, 
+0x01, 0x38, 0xE0, 0x87, 0x03, 0x18, 0xF8, 0x0F, 0x07, 0x1C, 0xFE, 0x1F, 0x06, 0x0C, 0x1F, 0x3C, 0x06, 0x0E, 0x07, 0x30, 0x0E, 0x86, 0x03, 0x30, 0x0C, 0x86, 0x01, 0x30, 0x0C, 
+0x86, 0x01, 0x18, 0x0C, 0x86, 0x01, 0x0C, 0x0C, 0x06, 0x03, 0x1F, 0x0C, 0x06, 0xFF, 0x3F, 0x0C, 0x86, 0xFF, 0x3F, 0x0C, 0x8C, 0xFF, 0x31, 0x0C, 0x8C, 0x07, 0x30, 0x04, 0x1C, 
+0x00, 0x18, 0x06, 0x38, 0x00, 0x18, 0x06, 0x70, 0x00, 0x0E, 0x03, 0xE0, 0x81, 0x07, 0x03, 0xC0, 0xFF, 0x81, 0x01, 0x00, 0x7E, 0xC0, 0x00, 0x00, 0x00, 0x40, 0x00,  // Code for char @
+
+0x13, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xE0, 0xFF, 0x00, 
+0x00, 0xF8, 0xE3, 0x00, 0x00, 0x7E, 0xE0, 0x00, 0x00, 0x0E, 0xE0, 0x00, 0x00, 0x7E, 0xE0, 0x00, 0x00, 0xF8, 0xE3, 0x00, 0x00, 0xE0, 0xFF, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 
+0x00, 0xFC, 0x03, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char A
+
+0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x0E, 0x1C, 0x38, 0x00, 0x0E, 0x1C, 0x38, 
+0x00, 0x0E, 0x1C, 0x38, 0x00, 0x0E, 0x1C, 0x38, 0x00, 0x0E, 0x1C, 0x38, 0x00, 0x0E, 0x1C, 0x38, 0x00, 0x0E, 0x1C, 0x38, 0x00, 0x1E, 0x1E, 0x38, 0x00, 0xFC, 0x3F, 0x1C, 0x00, 
+0xF8, 0xF3, 0x1F, 0x00, 0xF0, 0xE1, 0x0F, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char B
+
+0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0xE0, 0xFF, 0x03, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0xF8, 0x80, 0x0F, 0x00, 0x3C, 0x00, 0x1E, 0x00, 0x1C, 0x00, 0x1C, 
+0x00, 0x1E, 0x00, 0x3C, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x1E, 0x00, 0x3C, 0x00, 
+0x1C, 0x00, 0x1E, 0x00, 0x7C, 0x00, 0x0F, 0x00, 0xF8, 0xC0, 0x0F, 0x00, 0xF0, 0xC0, 0x03, 0x00, 0x40, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char C
+
+0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 
+0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x1E, 0x00, 0x1C, 0x00, 
+0x3C, 0x00, 0x1E, 0x00, 0xF8, 0x80, 0x0F, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0xE0, 0xFF, 0x03, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char D
+
+0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x0E, 0x1C, 0x38, 0x00, 0x0E, 0x1C, 0x38, 
+0x00, 0x0E, 0x1C, 0x38, 0x00, 0x0E, 0x1C, 0x38, 0x00, 0x0E, 0x1C, 0x38, 0x00, 0x0E, 0x1C, 0x38, 0x00, 0x0E, 0x1C, 0x38, 0x00, 0x0E, 0x1C, 0x38, 0x00, 0x0E, 0x1C, 0x38, 0x00, 
+0x0E, 0x1C, 0x38, 0x00, 0x0E, 0x1C, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char E
+
+0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x0E, 0x1C, 0x00, 0x00, 0x0E, 0x1C, 0x00, 
+0x00, 0x0E, 0x1C, 0x00, 0x00, 0x0E, 0x1C, 0x00, 0x00, 0x0E, 0x1C, 0x00, 0x00, 0x0E, 0x1C, 0x00, 0x00, 0x0E, 0x1C, 0x00, 0x00, 0x0E, 0x1C, 0x00, 0x00, 0x0E, 0x1C, 0x00, 0x00, 
+0x0E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char F
+
+0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0xF8, 0x80, 0x0F, 0x00, 0x78, 0x00, 0x0F, 0x00, 0x3C, 0x00, 0x1E, 
+0x00, 0x1C, 0x00, 0x1C, 0x00, 0x0E, 0x00, 0x3C, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x38, 0x38, 0x00, 0x0E, 0x38, 0x38, 0x00, 
+0x0E, 0x38, 0x38, 0x00, 0x1E, 0x38, 0x3C, 0x00, 0x1C, 0x38, 0x1C, 0x00, 0x7C, 0x38, 0x1C, 0x00, 0xF8, 0xF8, 0x0F, 0x00, 0xF0, 0xF8, 0x0F, 0x00, 0x40, 0xF8, 0x07, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char G
+
+0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x1C, 0x00, 
+0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 
+0x00, 0x1C, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char H
+
+0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char I
+
+0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 
+0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x3C, 0x00, 0xFE, 0xFF, 0x1F, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char J
+
+0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x1C, 0x00, 
+0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0xC0, 0x79, 0x00, 0x00, 0xE0, 0xF0, 0x00, 0x00, 0x70, 0xC0, 0x01, 0x00, 0x38, 0x80, 0x07, 0x00, 
+0x1C, 0x00, 0x0F, 0x00, 0x0E, 0x00, 0x1E, 0x00, 0x06, 0x00, 0x38, 0x00, 0x02, 0x00, 0x30, 0x00, 0x02, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char K
+
+0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 
+0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 0x00, 
+0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char L
+
+0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x3E, 0x00, 0x00, 0x00, 0xFE, 0x03, 0x00, 
+0x00, 0xF0, 0x3F, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0xF8, 0x3F, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0xF8, 0x3F, 0x00, 
+0x00, 0xFF, 0x03, 0x00, 0xF0, 0x3F, 0x00, 0x00, 0xFE, 0x03, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char M
+
+0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x7C, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 
+0x00, 0xE0, 0x03, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x80, 0x07, 0x00, 
+0x00, 0x00, 0x1E, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char N
+
+0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0xF8, 0x80, 0x0F, 0x00, 0x3C, 0x00, 0x0F, 0x00, 0x1C, 0x00, 0x1C, 
+0x00, 0x1C, 0x00, 0x1C, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 
+0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x3C, 0x00, 0x1E, 0x00, 0xF8, 0x80, 0x0F, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char O
+
+0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x0E, 0x1C, 0x00, 0x00, 0x0E, 0x1C, 0x00, 
+0x00, 0x0E, 0x1C, 0x00, 0x00, 0x0E, 0x1C, 0x00, 0x00, 0x0E, 0x1C, 0x00, 0x00, 0x0E, 0x1C, 0x00, 0x00, 0x0E, 0x1C, 0x00, 0x00, 0x0E, 0x1E, 0x00, 0x00, 0x1E, 0x0E, 0x00, 0x00, 
+0xFC, 0x0F, 0x00, 0x00, 0xF8, 0x07, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char P
+
+0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0xF8, 0x80, 0x0F, 0x00, 0x3C, 0x00, 0x0E, 0x00, 0x1C, 0x00, 0x1C, 
+0x00, 0x1C, 0x00, 0x1C, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x3A, 0x00, 0x0E, 0x00, 0x3B, 0x00, 0x0E, 0x00, 0x3E, 0x00, 
+0x1C, 0x00, 0x1E, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x3C, 0x00, 0x1F, 0x00, 0xF8, 0x80, 0x3F, 0x00, 0xF0, 0xFF, 0x77, 0x00, 0xC0, 0xFF, 0x71, 0x00, 0x00, 0x7F, 0x20, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Q
+
+0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x0E, 0x1C, 0x00, 0x00, 0x0E, 0x1C, 0x00, 
+0x00, 0x0E, 0x1C, 0x00, 0x00, 0x0E, 0x1C, 0x00, 0x00, 0x0E, 0x1C, 0x00, 0x00, 0x0E, 0x1C, 0x00, 0x00, 0x0E, 0x3C, 0x00, 0x00, 0x0E, 0x7C, 0x00, 0x00, 0x0E, 0xFC, 0x00, 0x00, 
+0x1E, 0xDE, 0x01, 0x00, 0x1E, 0xCE, 0x03, 0x00, 0xFC, 0x8F, 0x0F, 0x00, 0xF8, 0x07, 0x1E, 0x00, 0xF0, 0x03, 0x3C, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char R
+
+0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0xF0, 0x81, 0x07, 0x00, 0xF8, 0x83, 0x0F, 0x00, 0xFC, 0x07, 0x1E, 0x00, 0x1C, 0x07, 0x1C, 0x00, 0x0E, 0x0E, 0x3C, 
+0x00, 0x0E, 0x0E, 0x38, 0x00, 0x0E, 0x0E, 0x38, 0x00, 0x0E, 0x1C, 0x38, 0x00, 0x0E, 0x1C, 0x38, 0x00, 0x1E, 0x1C, 0x38, 0x00, 0x1C, 0x38, 0x3C, 0x00, 0x7C, 0x78, 0x1C, 0x00, 
+0x78, 0xF8, 0x1F, 0x00, 0x60, 0xF0, 0x0F, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char S
+
+0x11, 0x0E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 
+0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 
+0x0E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char T
+
+0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x01, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x3C, 
+0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x1C, 0x00, 
+0x00, 0x00, 0x1E, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0xFE, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char U
+
+0x13, 0x02, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0xF8, 0x0F, 
+0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0xFF, 0x01, 0x00, 
+0xE0, 0x3F, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char V
+
+0x1B, 0x0E, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0xFE, 0x3F, 0x00, 0x00, 0xE0, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0x3F, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0x38, 
+0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0xF8, 0x3F, 0x00, 0x80, 0xFF, 0x07, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0xFE, 0x07, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 
+0xFE, 0x01, 0x00, 0x00, 0xFE, 0x3F, 0x00, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 
+0xF8, 0x3F, 0x00, 0x80, 0xFF, 0x07, 0x00, 0xF8, 0x7F, 0x00, 0x00, 0xFE, 0x07, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char W
+
+0x13, 0x00, 0x00, 0x20, 0x00, 0x02, 0x00, 0x30, 0x00, 0x06, 0x00, 0x3C, 0x00, 0x1E, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0x0F, 0x00, 0x78, 0xC0, 0x07, 0x00, 0xF0, 0xE1, 0x01, 
+0x00, 0xC0, 0xFB, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0xC0, 0xFB, 0x00, 0x00, 0xF0, 0xE1, 0x01, 0x00, 0x78, 0xC0, 0x07, 0x00, 
+0x3C, 0x00, 0x0F, 0x00, 0x1E, 0x00, 0x1E, 0x00, 0x06, 0x00, 0x3C, 0x00, 0x02, 0x00, 0x30, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char X
+
+0x13, 0x02, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x07, 0x00, 
+0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x3F, 0x00, 0x00, 0xF8, 0x3F, 0x00, 0x00, 0xFC, 0x3F, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 
+0xF0, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Y
+
+0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x0E, 0x00, 0x3E, 0x00, 0x0E, 0x00, 0x3F, 0x00, 0x0E, 0x80, 0x3B, 0x00, 0x0E, 0xC0, 0x39, 0x00, 0x0E, 0xF0, 0x38, 
+0x00, 0x0E, 0x78, 0x38, 0x00, 0x0E, 0x3C, 0x38, 0x00, 0x0E, 0x1E, 0x38, 0x00, 0x0E, 0x07, 0x38, 0x00, 0x8E, 0x03, 0x38, 0x00, 0xCE, 0x01, 0x38, 0x00, 0xEE, 0x00, 0x38, 0x00, 
+0x7E, 0x00, 0x38, 0x00, 0x3E, 0x00, 0x38, 0x00, 0x1E, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Z
+
+0x07, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x0F, 0xFE, 0xFF, 0xFF, 0x0F, 0xFE, 0xFF, 0xFF, 0x0F, 0x0E, 0x00, 0x00, 0x0E, 0x0E, 0x00, 0x00, 0x0E, 0x0E, 0x00, 0x00, 
+0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char [
+
+0x08, 0x06, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x3E, 
+0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char BackSlash
+
+0x06, 0x0E, 0x00, 0x00, 0x0E, 0x0E, 0x00, 0x00, 0x0E, 0x0E, 0x00, 0x00, 0x0E, 0xFE, 0xFF, 0xFF, 0x0F, 0xFE, 0xFF, 0xFF, 0x0F, 0xFE, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ]
+
+0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 
+0x00, 0x0E, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ^
+
+0x18, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 
+0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 
+0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 
+0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char _
+
+0x06, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char `
+
+0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0F, 0x00, 0x00, 0x8E, 0x1F, 0x00, 0x00, 0x8F, 0x3F, 0x00, 0x00, 0xC3, 0x39, 0x00, 0x80, 0xC1, 0x30, 0x00, 0x80, 0xC1, 0x30, 
+0x00, 0x80, 0xC1, 0x30, 0x00, 0x80, 0xC1, 0x10, 0x00, 0x80, 0x61, 0x18, 0x00, 0x80, 0x63, 0x0C, 0x00, 0x80, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0xFE, 0x3F, 0x00, 
+0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char a
+
+0x0E, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0x07, 0x0C, 0x00, 0x00, 0x03, 0x18, 0x00, 0x80, 0x01, 0x30, 
+0x00, 0x80, 0x01, 0x30, 0x00, 0x80, 0x01, 0x30, 0x00, 0x80, 0x03, 0x38, 0x00, 0x00, 0x07, 0x1C, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0xF8, 0x03, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char b
+
+0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x07, 0x1C, 0x00, 0x80, 0x03, 0x38, 0x00, 0x80, 0x01, 0x30, 
+0x00, 0x80, 0x01, 0x30, 0x00, 0x80, 0x01, 0x30, 0x00, 0x80, 0x03, 0x38, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x0E, 0x0E, 0x00, 0x00, 0x0C, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char c
+
+0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x07, 0x1C, 0x00, 0x80, 0x03, 0x38, 0x00, 0x80, 0x01, 0x30, 
+0x00, 0x80, 0x01, 0x30, 0x00, 0x80, 0x01, 0x30, 0x00, 0x00, 0x03, 0x18, 0x00, 0x00, 0x07, 0x0C, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char d
+
+0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x67, 0x1C, 0x00, 0x80, 0x63, 0x38, 0x00, 0x80, 0x61, 0x30, 
+0x00, 0x80, 0x61, 0x30, 0x00, 0x80, 0x61, 0x30, 0x00, 0x80, 0x63, 0x38, 0x00, 0x00, 0x67, 0x3C, 0x00, 0x00, 0x7F, 0x1E, 0x00, 0x00, 0x7E, 0x0E, 0x00, 0x00, 0x78, 0x06, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char e
+
+0x09, 0x80, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0xF8, 0xFF, 0x3F, 0x00, 0xFC, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x86, 0x01, 0x00, 0x00, 0x86, 0x01, 0x00, 
+0x00, 0x86, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char f
+
+0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x83, 0x01, 0x00, 0xFE, 0x8F, 0x07, 0x00, 0xFF, 0x9F, 0x07, 0x00, 0x07, 0x1C, 0x0E, 0x80, 0x03, 0x38, 0x0C, 0x80, 0x01, 0x30, 
+0x0C, 0x80, 0x01, 0x30, 0x0C, 0x80, 0x01, 0x30, 0x0C, 0x00, 0x03, 0x18, 0x0E, 0x00, 0x06, 0x1C, 0x07, 0x80, 0xFF, 0xFF, 0x07, 0x80, 0xFF, 0xFF, 0x03, 0x80, 0xFF, 0xFF, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char g
+
+0x0E, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x80, 0x01, 0x00, 
+0x00, 0x80, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0xFE, 0x3F, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char h
+
+0x04, 0x00, 0x00, 0x00, 0x00, 0x8E, 0xFF, 0x3F, 0x00, 0x8E, 0xFF, 0x3F, 0x00, 0x8E, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char i
+
+0x04, 0x00, 0x00, 0x00, 0x0C, 0x8E, 0xFF, 0xFF, 0x0F, 0x8E, 0xFF, 0xFF, 0x07, 0x8E, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char j
+
+0x0F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x78, 0x00, 
+0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xCE, 0x03, 0x00, 0x00, 0x8F, 0x07, 0x00, 0x00, 0x07, 0x0F, 0x00, 0x80, 0x03, 0x1E, 0x00, 0x80, 0x01, 0x38, 0x00, 0x80, 0x00, 0x30, 0x00, 
+0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char k
+
+0x04, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char l
+
+0x16, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x80, 0x01, 0x00, 
+0x00, 0x80, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0xFE, 0x3F, 0x00, 0x00, 0x06, 0x00, 0x00, 
+0x00, 0x03, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 
+0xFE, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char m
+
+0x0E, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x80, 0x01, 0x00, 
+0x00, 0x80, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0xFE, 0x3F, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char n
+
+0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x07, 0x1C, 0x00, 0x80, 0x03, 0x38, 0x00, 0x80, 0x01, 0x30, 
+0x00, 0x80, 0x01, 0x30, 0x00, 0x80, 0x01, 0x30, 0x00, 0x80, 0x03, 0x38, 0x00, 0x00, 0x07, 0x1C, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0xF8, 0x03, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char o
+
+0x0E, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x80, 0xFF, 0xFF, 0x0F, 0x80, 0xFF, 0xFF, 0x0F, 0x00, 0x0E, 0x1C, 0x00, 0x00, 0x03, 0x18, 0x00, 0x80, 0x01, 0x30, 
+0x00, 0x80, 0x01, 0x30, 0x00, 0x80, 0x01, 0x30, 0x00, 0x80, 0x03, 0x38, 0x00, 0x00, 0x07, 0x1C, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0xF8, 0x03, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char p
+
+0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x07, 0x1C, 0x00, 0x80, 0x03, 0x38, 0x00, 0x80, 0x01, 0x30, 
+0x00, 0x80, 0x01, 0x30, 0x00, 0x80, 0x01, 0x30, 0x00, 0x00, 0x03, 0x18, 0x00, 0x00, 0x0E, 0x1C, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x80, 0xFF, 0xFF, 0x0F, 0x80, 0xFF, 0xFF, 0x0F, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char q
+
+0x0A, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x80, 0x01, 0x00, 
+0x00, 0x80, 0x01, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char r
+
+0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x06, 0x00, 0x00, 0x3F, 0x1E, 0x00, 0x00, 0x7F, 0x1E, 0x00, 0x80, 0x73, 0x38, 0x00, 0x80, 0xF1, 0x30, 0x00, 0x80, 0xE1, 0x30, 
+0x00, 0x80, 0xE1, 0x31, 0x00, 0x80, 0xC3, 0x31, 0x00, 0x00, 0xCF, 0x39, 0x00, 0x00, 0xCF, 0x1F, 0x00, 0x00, 0x8C, 0x1F, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char s
+
+0x07, 0x80, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0xF8, 0xFF, 0x1F, 0x00, 0xF8, 0xFF, 0x3F, 0x00, 0xFC, 0xFF, 0x3F, 0x00, 0x80, 0x01, 0x30, 0x00, 0x80, 0x01, 0x30, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char t
+
+0x0E, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x80, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x30, 
+0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x80, 0xFF, 0x3F, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char u
+
+0x0F, 0x80, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0xF8, 0x07, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0x3F, 
+0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0xF8, 0x07, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 
+0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char v
+
+0x14, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0xFC, 0x3F, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x38, 
+0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0xC0, 0x3F, 0x00, 
+0x00, 0x00, 0x38, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0xFC, 0x3F, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char w
+
+0x0E, 0x80, 0x00, 0x20, 0x00, 0x80, 0x01, 0x30, 0x00, 0x80, 0x03, 0x38, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x1E, 0x0F, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0xF0, 0x01, 
+0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0x1E, 0x0F, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x80, 0x03, 0x38, 0x00, 0x80, 0x01, 0x30, 0x00, 0x80, 0x00, 0x20, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char x
+
+0x0F, 0x80, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0x0C, 0x80, 0x1F, 0x00, 0x0C, 0x00, 0xFE, 0x00, 0x0C, 0x00, 0xF8, 0x03, 0x0E, 0x00, 0xE0, 0x8F, 0x07, 0x00, 0x80, 0xFF, 
+0x03, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x7F, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 
+0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char y
+
+0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x80, 0x01, 0x3C, 0x00, 0x80, 0x01, 0x3E, 0x00, 0x80, 0x01, 0x3F, 0x00, 0x80, 0x81, 0x33, 0x00, 0x80, 0xC1, 0x31, 
+0x00, 0x80, 0xE1, 0x30, 0x00, 0x80, 0x79, 0x30, 0x00, 0x80, 0x3D, 0x30, 0x00, 0x80, 0x1F, 0x30, 0x00, 0x80, 0x07, 0x30, 0x00, 0x80, 0x03, 0x30, 0x00, 0x80, 0x01, 0x30, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char z
+
+0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 
+0x00, 0xF8, 0x00, 0x00, 0xF0, 0x9F, 0xFF, 0x00, 0xF8, 0x07, 0xFE, 0x01, 0x0C, 0x00, 0x00, 0x03, 0x06, 0x00, 0x00, 0x06, 0x02, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char {
+
+0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x0F, 0xFE, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char |
+
+0x05, 0x0C, 0x00, 0x00, 0x03, 0xF8, 0x0F, 0xFE, 0x01, 0xF0, 0x9F, 0xFF, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char }
+
+0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x1C, 0x00, 
+0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 
+0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ~
+
+0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00   // Code for char };
+
+};
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ILI9341/Arial34x40.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,113 @@
+
+//WARNING: This Font Require X-GLCD Lib.
+//         You can not use it with MikroE GLCD Lib.
+
+//Font Generated by MikroElektronika GLCD Font Creator 1.2.0.0
+//MikroElektronika 2011 
+//http://www.mikroe.com 
+
+//GLCD FontName : Arial34x40
+//GLCD FontSize : 34 x 40
+
+const unsigned char Arial34x40[] = {
+        171,34,40,4,
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char  
+        0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x7C, 0x00, 0xC0, 0xFF, 0xFF, 0x7C, 0x00, 0xC0, 0xFF, 0xFF, 0x7C, 0x00, 0xC0, 0xFF, 0xFF, 0x7C, 0x00, 0xC0, 0xFF, 0x01, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char !
+        0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char "
+        0x13, 0x00, 0xF0, 0xE0, 0x01, 0x00, 0x00, 0xF0, 0xE0, 0x61, 0x00, 0x00, 0xF0, 0xE0, 0x7F, 0x00, 0x00, 0xF0, 0xFC, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xFF, 0xFF, 0x1F, 0x00, 0xC0, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xE7, 0x01, 0x00, 0xC0, 0xFF, 0xE0, 0x01, 0x00, 0xC0, 0xF1, 0xE0, 0x61, 0x00, 0x00, 0xF0, 0xE0, 0x7F, 0x00, 0x00, 0xF0, 0xFC, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xFF, 0xFF, 0x1F, 0x00, 0xC0, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xE7, 0x01, 0x00, 0xC0, 0xFF, 0xE0, 0x01, 0x00, 0xC0, 0xF1, 0xE0, 0x01, 0x00, 0x00, 0xF0, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char #
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0xFC, 0x00, 0x0F, 0x00, 0x00, 0xFF, 0x81, 0x1F, 0x00, 0x80, 0xFF, 0x83, 0x3F, 0x00, 0x80, 0xFF, 0x07, 0x3F, 0x00, 0xC0, 0xC7, 0x0F, 0x7C, 0x00, 0xC0, 0x83, 0x0F, 0x78, 0x00, 0xF0, 0xFF, 0xFF, 0xFF, 0x03, 0xF0, 0xFF, 0xFF, 0xFF, 0x03, 0xC0, 0x03, 0x1F, 0x78, 0x00, 0xC0, 0x0F, 0x3E, 0x78, 0x00, 0x80, 0x1F, 0x3E, 0x3C, 0x00, 0x80, 0x1F, 0xFC, 0x3F, 0x00, 0x00, 0x0F, 0xFC, 0x1F, 0x00, 0x00, 0x0C, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char $
+        0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0xC0, 0x83, 0x07, 0x00, 0x00, 0xC0, 0x01, 0x07, 0x00, 0x00, 0xC0, 0x83, 0x07, 0xC0, 0x00, 0xC0, 0xFF, 0x07, 0xF0, 0x00, 0x80, 0xFF, 0x03, 0xFC, 0x00, 0x00, 0xFF, 0x01, 0x7E, 0x00, 0x00, 0xFE, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x7E, 0xC0, 0x1F, 0x00, 0x80, 0x3F, 0xE0, 0x3F, 0x00, 0xC0, 0x0F, 0xF0, 0x7F, 0x00, 0xC0, 0x03, 0xF8, 0xFF, 0x00, 0xC0, 0x00, 0x78, 0xF0, 0x00, 0x00, 0x00, 0x38, 0xE0, 0x00, 0x00, 0x00, 0x78, 0xF0, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char %
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0x3E, 0xFC, 0x3F, 0x00, 0x00, 0x7F, 0xFC, 0x3F, 0x00, 0x80, 0xFF, 0x3F, 0x7C, 0x00, 0x80, 0xFF, 0x1F, 0x78, 0x00, 0xC0, 0xFF, 0x0F, 0x78, 0x00, 0xC0, 0xE7, 0x0F, 0x78, 0x00, 0xC0, 0x83, 0x3F, 0x78, 0x00, 0xC0, 0xC3, 0x7F, 0x78, 0x00, 0xC0, 0xE7, 0xFF, 0x7C, 0x00, 0xC0, 0xFF, 0xFD, 0x3F, 0x00, 0x80, 0xFF, 0xF9, 0x3F, 0x00, 0x80, 0xFF, 0xF0, 0x1F, 0x00, 0x00, 0x7F, 0xC0, 0x1F, 0x00, 0x00, 0x3E, 0xF0, 0x1F, 0x00, 0x00, 0x00, 0xF8, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0x7E, 0x00, 0x00, 0x00, 0x30, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char &
+        0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char '
+        0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x07, 0x00, 0x00, 0xE0, 0xFF, 0x7F, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0x01, 0x00, 0xFE, 0xFF, 0xFF, 0x07, 0x80, 0xFF, 0xFF, 0xFF, 0x1F, 0xC0, 0xFF, 0x00, 0xF0, 0x3F, 0xC0, 0x0F, 0x00, 0x00, 0x3F, 0xC0, 0x03, 0x00, 0x00, 0x38, 0x40, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char (
+        0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x20, 0xC0, 0x03, 0x00, 0x00, 0x38, 0xC0, 0x0F, 0x00, 0x00, 0x3F, 0xC0, 0xFF, 0x00, 0xF0, 0x3F, 0x80, 0xFF, 0xFF, 0xFF, 0x1F, 0x00, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0xF8, 0xFF, 0xFF, 0x01, 0x00, 0xE0, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0xFE, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char )
+        0x0D, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x01, 0x00, 0x00, 0x00, 0x8E, 0x01, 0x00, 0x00, 0x00, 0xDC, 0x03, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0xDC, 0x03, 0x00, 0x00, 0x00, 0x8E, 0x01, 0x00, 0x00, 0x00, 0x0E, 0x01, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char *
+        0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char +
+        0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x08, 0x00, 0x00, 0x00, 0x7C, 0x1C, 0x00, 0x00, 0x00, 0x7C, 0x0E, 0x00, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ,
+        0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char -
+        0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char .
+        0x0A, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0x1F, 0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char /
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x07, 0x00, 0x00, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x3F, 0x00, 0x80, 0xFF, 0xFF, 0x3F, 0x00, 0xC0, 0x0F, 0x00, 0x7E, 0x00, 0xC0, 0x07, 0x00, 0x7C, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x07, 0x00, 0x7C, 0x00, 0xC0, 0x0F, 0x00, 0x7E, 0x00, 0x80, 0xFF, 0xFF, 0x3F, 0x00, 0x80, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFC, 0xFF, 0x07, 0x00, 0x00, 0xE0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 0
+        0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 1
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x38, 0x00, 0x7C, 0x00, 0x00, 0x3E, 0x00, 0x7E, 0x00, 0x00, 0x3F, 0x80, 0x7F, 0x00, 0x80, 0x3F, 0xC0, 0x7F, 0x00, 0x80, 0x3F, 0xE0, 0x7F, 0x00, 0xC0, 0x07, 0xF0, 0x7F, 0x00, 0xC0, 0x03, 0xF8, 0x7D, 0x00, 0xC0, 0x03, 0xFC, 0x7C, 0x00, 0xC0, 0x03, 0x7E, 0x7C, 0x00, 0xC0, 0x87, 0x3F, 0x7C, 0x00, 0xC0, 0xFF, 0x1F, 0x7C, 0x00, 0x80, 0xFF, 0x0F, 0x7C, 0x00, 0x80, 0xFF, 0x07, 0x7C, 0x00, 0x00, 0xFF, 0x03, 0x7C, 0x00, 0x00, 0xFC, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 2
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0C, 0x80, 0x0F, 0x00, 0x00, 0x1E, 0x80, 0x1F, 0x00, 0x80, 0x1F, 0x80, 0x3F, 0x00, 0x80, 0x1F, 0x80, 0x3F, 0x00, 0xC0, 0x1F, 0x00, 0x7E, 0x00, 0xC0, 0x07, 0x00, 0x7C, 0x00, 0xC0, 0x83, 0x07, 0x78, 0x00, 0xC0, 0x83, 0x07, 0x78, 0x00, 0xC0, 0xC7, 0x07, 0x78, 0x00, 0xC0, 0xFF, 0x0F, 0x7E, 0x00, 0x80, 0xFF, 0xFF, 0x3F, 0x00, 0x80, 0xFF, 0xFE, 0x3F, 0x00, 0x00, 0x7F, 0xFC, 0x1F, 0x00, 0x00, 0x3C, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 3
+        0x12, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0xFE, 0x03, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0xC0, 0xDF, 0x03, 0x00, 0x00, 0xF0, 0xC7, 0x03, 0x00, 0x00, 0xF8, 0xC3, 0x03, 0x00, 0x00, 0xFE, 0xC0, 0x03, 0x00, 0x00, 0x7F, 0xC0, 0x03, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 4
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x86, 0x0F, 0x00, 0x00, 0xE0, 0x8F, 0x1F, 0x00, 0x00, 0xFF, 0x8F, 0x3F, 0x00, 0xC0, 0xFF, 0x8F, 0x3F, 0x00, 0xC0, 0xFF, 0x0F, 0x7E, 0x00, 0xC0, 0xFF, 0x07, 0x7C, 0x00, 0xC0, 0x9F, 0x03, 0x78, 0x00, 0xC0, 0xC7, 0x03, 0x78, 0x00, 0xC0, 0xC7, 0x03, 0x7C, 0x00, 0xC0, 0xC7, 0x0F, 0x7E, 0x00, 0xC0, 0xC7, 0xFF, 0x3F, 0x00, 0xC0, 0x87, 0xFF, 0x3F, 0x00, 0xC0, 0x07, 0xFF, 0x1F, 0x00, 0xC0, 0x07, 0xFE, 0x07, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 5
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x3F, 0x00, 0x80, 0x0F, 0x0F, 0x3E, 0x00, 0xC0, 0x03, 0x07, 0x7C, 0x00, 0xC0, 0x83, 0x07, 0x78, 0x00, 0xC0, 0x83, 0x07, 0x78, 0x00, 0xC0, 0x87, 0x07, 0x78, 0x00, 0xC0, 0x9F, 0x1F, 0x7C, 0x00, 0x80, 0x9F, 0xFF, 0x3F, 0x00, 0x80, 0x1F, 0xFF, 0x3F, 0x00, 0x00, 0x1F, 0xFE, 0x1F, 0x00, 0x00, 0x1C, 0xFC, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 6
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x7C, 0x00, 0xC0, 0x07, 0x80, 0x7F, 0x00, 0xC0, 0x07, 0xF0, 0x7F, 0x00, 0xC0, 0x07, 0xFC, 0x7F, 0x00, 0xC0, 0x07, 0xFF, 0x7F, 0x00, 0xC0, 0xC7, 0xFF, 0x03, 0x00, 0xC0, 0xE7, 0x3F, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 7
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x7C, 0xF0, 0x0F, 0x00, 0x00, 0xFF, 0xF9, 0x1F, 0x00, 0x80, 0xFF, 0xFD, 0x3F, 0x00, 0x80, 0xFF, 0xFF, 0x3F, 0x00, 0xC0, 0xFF, 0x1F, 0x7C, 0x00, 0xC0, 0x87, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x87, 0x0F, 0x78, 0x00, 0xC0, 0xFF, 0x1F, 0x7C, 0x00, 0x80, 0xFF, 0xFF, 0x3F, 0x00, 0x80, 0xFF, 0xFD, 0x3F, 0x00, 0x00, 0xFF, 0xF8, 0x1F, 0x00, 0x00, 0x7C, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 8
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0xFE, 0x07, 0x07, 0x00, 0x00, 0xFF, 0x0F, 0x1F, 0x00, 0x80, 0xFF, 0x1F, 0x3F, 0x00, 0x80, 0xFF, 0x3F, 0x3F, 0x00, 0xC0, 0x07, 0x3F, 0x7F, 0x00, 0xC0, 0x03, 0x3C, 0x7C, 0x00, 0xC0, 0x03, 0x3C, 0x78, 0x00, 0xC0, 0x03, 0x3C, 0x78, 0x00, 0xC0, 0x07, 0x1C, 0x78, 0x00, 0x80, 0x0F, 0x1E, 0x3E, 0x00, 0x80, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0x00, 0xFC, 0xFF, 0x07, 0x00, 0x00, 0xE0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 9
+        0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x7C, 0x00, 0x00, 0xF0, 0x01, 0x7C, 0x00, 0x00, 0xF0, 0x01, 0x7C, 0x00, 0x00, 0xF0, 0x01, 0x7C, 0x00, 0x00, 0xF0, 0x01, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char :
+        0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x7C, 0x08, 0x00, 0xF0, 0x01, 0x7C, 0x1C, 0x00, 0xF0, 0x01, 0x7C, 0x0E, 0x00, 0xF0, 0x01, 0xFC, 0x07, 0x00, 0xF0, 0x01, 0xFC, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ;
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0xC0, 0x7B, 0x00, 0x00, 0x00, 0xC0, 0x7B, 0x00, 0x00, 0x00, 0xC0, 0x71, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0xE0, 0xF0, 0x00, 0x00, 0x00, 0xF0, 0xE0, 0x01, 0x00, 0x00, 0xF0, 0xE0, 0x01, 0x00, 0x00, 0x78, 0xC0, 0x03, 0x00, 0x00, 0x78, 0xC0, 0x03, 0x00, 0x00, 0x38, 0x80, 0x03, 0x00, 0x00, 0x3C, 0x80, 0x07, 0x00, 0x00, 0x3C, 0x80, 0x07, 0x00, 0x00, 0x1E, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char <
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char =
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x0F, 0x00, 0x00, 0x3C, 0x80, 0x07, 0x00, 0x00, 0x3C, 0x80, 0x07, 0x00, 0x00, 0x38, 0x80, 0x03, 0x00, 0x00, 0x78, 0xC0, 0x03, 0x00, 0x00, 0x78, 0xC0, 0x03, 0x00, 0x00, 0xF0, 0xE0, 0x01, 0x00, 0x00, 0xF0, 0xE0, 0x01, 0x00, 0x00, 0xE0, 0xE0, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0xC0, 0x71, 0x00, 0x00, 0x00, 0xC0, 0x7B, 0x00, 0x00, 0x00, 0xC0, 0x3B, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char >
+        0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x07, 0xF0, 0x7C, 0x00, 0xC0, 0x03, 0xF8, 0x7C, 0x00, 0xC0, 0x03, 0xFC, 0x7C, 0x00, 0xC0, 0x03, 0xFE, 0x7C, 0x00, 0xC0, 0x03, 0xFF, 0x7C, 0x00, 0xC0, 0x87, 0x1F, 0x00, 0x00, 0xC0, 0xC7, 0x0F, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ?
+        0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xFF, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x01, 0x00, 0xE0, 0xFF, 0xFF, 0x03, 0x00, 0xF8, 0x0F, 0xF0, 0x0F, 0x00, 0xFC, 0x01, 0xC0, 0x0F, 0x00, 0x7E, 0x00, 0x00, 0x1F, 0x00, 0x3E, 0xF0, 0x07, 0x3E, 0x00, 0x1F, 0xFE, 0x1F, 0x3C, 0x00, 0x8F, 0xFF, 0x3F, 0x7C, 0x80, 0xCF, 0xFF, 0x7F, 0x78, 0x80, 0xE7, 0x0F, 0x7C, 0x78, 0x80, 0xE7, 0x03, 0x78, 0x78, 0xC0, 0xF3, 0x01, 0x78, 0xF0, 0xC0, 0xF3, 0x00, 0x78, 0xF0, 0xC0, 0xF3, 0x00, 0x3C, 0xF0, 0xC0, 0xF3, 0x00, 0x1E, 0xF0, 0xC0, 0xE3, 0x81, 0x3F, 0xF0, 0xC0, 0xC3, 0xFF, 0x7F, 0xF0, 0xC0, 0xE3, 0xFF, 0x7F, 0xF0, 0xC0, 0xF3, 0xFF, 0x7F, 0xF0, 0xC0, 0xF7, 0xFF, 0x7F, 0xF0, 0x80, 0xF7, 0x7F, 0x78, 0xF8, 0x80, 0xF7, 0x03, 0x78, 0x78, 0x80, 0x0F, 0x00, 0x3C, 0x78, 0x00, 0x1F, 0x00, 0x3E, 0x7C, 0x00, 0x3F, 0x00, 0x1F, 0x3E, 0x00, 0xFE, 0xC0, 0x0F, 0x3F, 0x00, 0xFC, 0xFF, 0x87, 0x1F, 0x00, 0xF8, 0xFF, 0x83, 0x0F, 0x00, 0xE0, 0xFF, 0x81, 0x07, 0x00, 0x80, 0x3F, 0x80, 0x03, 0x00, 0x00, 0x00, 0x80, 0x00,  // Code for char @
+        0x17, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0x3F, 0x00, 0x00, 0xF8, 0xFF, 0x07, 0x00, 0x00, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xEF, 0x01, 0x00, 0xC0, 0xFF, 0xE1, 0x01, 0x00, 0xC0, 0x1F, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0xC0, 0x1F, 0xE0, 0x01, 0x00, 0xC0, 0xFF, 0xE1, 0x01, 0x00, 0xC0, 0xFF, 0xEF, 0x01, 0x00, 0x00, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0xF8, 0xFF, 0x07, 0x00, 0x00, 0xC0, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char A
+        0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x87, 0x1F, 0x78, 0x00, 0xC0, 0xFF, 0x3F, 0x7C, 0x00, 0x80, 0xFF, 0xFF, 0x3F, 0x00, 0x80, 0xFF, 0xFD, 0x3F, 0x00, 0x00, 0xFF, 0xF8, 0x1F, 0x00, 0x00, 0x7C, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char B
+        0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x01, 0x00, 0x00, 0xFC, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0x3F, 0x80, 0x1F, 0x00, 0x80, 0x0F, 0x00, 0x3E, 0x00, 0x80, 0x07, 0x00, 0x3C, 0x00, 0xC0, 0x07, 0x00, 0x7C, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x07, 0x00, 0x7C, 0x00, 0xC0, 0x07, 0x00, 0x3E, 0x00, 0x80, 0x1F, 0x00, 0x3F, 0x00, 0x80, 0x3F, 0xC0, 0x3F, 0x00, 0x00, 0x3F, 0x80, 0x1F, 0x00, 0x00, 0x3E, 0x80, 0x0F, 0x00, 0x00, 0x1C, 0x80, 0x07, 0x00, 0x00, 0x10, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char C
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x07, 0x00, 0x78, 0x00, 0xC0, 0x07, 0x00, 0x7C, 0x00, 0x80, 0x0F, 0x00, 0x3E, 0x00, 0x80, 0x3F, 0x80, 0x3F, 0x00, 0x00, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFC, 0xFF, 0x07, 0x00, 0x00, 0xF8, 0xFF, 0x03, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char D
+        0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char E
+        0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0x03, 0x0F, 0x00, 0x00, 0xC0, 0x03, 0x0F, 0x00, 0x00, 0xC0, 0x03, 0x0F, 0x00, 0x00, 0xC0, 0x03, 0x0F, 0x00, 0x00, 0xC0, 0x03, 0x0F, 0x00, 0x00, 0xC0, 0x03, 0x0F, 0x00, 0x00, 0xC0, 0x03, 0x0F, 0x00, 0x00, 0xC0, 0x03, 0x0F, 0x00, 0x00, 0xC0, 0x03, 0x0F, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char F
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x01, 0x00, 0x00, 0xF8, 0xFF, 0x03, 0x00, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0x00, 0x7F, 0xC0, 0x1F, 0x00, 0x80, 0x1F, 0x00, 0x3F, 0x00, 0x80, 0x0F, 0x00, 0x3E, 0x00, 0x80, 0x07, 0x00, 0x3C, 0x00, 0xC0, 0x07, 0x00, 0x7C, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x3C, 0x78, 0x00, 0xC0, 0x03, 0x3C, 0x78, 0x00, 0xC0, 0x03, 0x3C, 0x78, 0x00, 0xC0, 0x07, 0x3C, 0x7C, 0x00, 0x80, 0x0F, 0x3C, 0x3C, 0x00, 0x80, 0x1F, 0x3C, 0x3E, 0x00, 0x80, 0x3F, 0xFC, 0x3F, 0x00, 0x00, 0x3F, 0xFC, 0x1F, 0x00, 0x00, 0x3E, 0xFC, 0x1F, 0x00, 0x00, 0x1C, 0xFC, 0x0F, 0x00, 0x00, 0x18, 0xFC, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char G
+        0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char H
+        0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char I
+        0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0xC0, 0xFF, 0xFF, 0x3F, 0x00, 0xC0, 0xFF, 0xFF, 0x3F, 0x00, 0xC0, 0xFF, 0xFF, 0x1F, 0x00, 0xC0, 0xFF, 0xFF, 0x0F, 0x00, 0xC0, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char J
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xF8, 0x3F, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x00, 0x00, 0x00, 0x7E, 0xFF, 0x01, 0x00, 0x00, 0x3F, 0xFC, 0x07, 0x00, 0x80, 0x1F, 0xF8, 0x1F, 0x00, 0xC0, 0x0F, 0xE0, 0x3F, 0x00, 0xC0, 0x07, 0x80, 0x7F, 0x00, 0xC0, 0x03, 0x00, 0x7F, 0x00, 0xC0, 0x01, 0x00, 0x7C, 0x00, 0xC0, 0x00, 0x00, 0x70, 0x00, 0x40, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char K
+        0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char L
+        0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0xF0, 0xFF, 0x01, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char M
+        0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char N
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x01, 0x00, 0x00, 0xFC, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0x7F, 0xC0, 0x1F, 0x00, 0x80, 0x1F, 0x00, 0x3F, 0x00, 0x80, 0x0F, 0x00, 0x3E, 0x00, 0xC0, 0x07, 0x00, 0x7C, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x07, 0x00, 0x7C, 0x00, 0x80, 0x0F, 0x00, 0x3E, 0x00, 0x80, 0x1F, 0x00, 0x3F, 0x00, 0x00, 0x7F, 0xC0, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0x00, 0xFC, 0xFF, 0x07, 0x00, 0x00, 0xF0, 0xFF, 0x01, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char O
+        0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0x03, 0x3C, 0x00, 0x00, 0xC0, 0x03, 0x3C, 0x00, 0x00, 0xC0, 0x03, 0x3C, 0x00, 0x00, 0xC0, 0x03, 0x3C, 0x00, 0x00, 0xC0, 0x03, 0x3C, 0x00, 0x00, 0xC0, 0x03, 0x3C, 0x00, 0x00, 0xC0, 0x03, 0x3C, 0x00, 0x00, 0xC0, 0x07, 0x3E, 0x00, 0x00, 0xC0, 0x0F, 0x3F, 0x00, 0x00, 0x80, 0xFF, 0x1F, 0x00, 0x00, 0x80, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x07, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char P
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x01, 0x00, 0x00, 0xFC, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0x7F, 0xC0, 0x3F, 0x00, 0x80, 0x1F, 0x00, 0x3E, 0x00, 0x80, 0x07, 0x00, 0x3C, 0x00, 0xC0, 0x07, 0x00, 0x7C, 0x00, 0xC0, 0x03, 0x00, 0x78, 0x00, 0xC0, 0x03, 0x00, 0x79, 0x00, 0xC0, 0x03, 0xC0, 0x7B, 0x00, 0xC0, 0x03, 0xC0, 0x7B, 0x00, 0xC0, 0x03, 0x80, 0x7F, 0x00, 0xC0, 0x07, 0x00, 0x7F, 0x00, 0x80, 0x07, 0x00, 0x3F, 0x00, 0x80, 0x0F, 0x00, 0x3F, 0x00, 0x80, 0x7F, 0xC0, 0x3F, 0x00, 0x00, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x00, 0x00, 0xFC, 0xFF, 0xFB, 0x00, 0x00, 0xF8, 0xFF, 0xF1, 0x01, 0x00, 0xC0, 0x3F, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Q
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x03, 0x3E, 0x00, 0x00, 0xC0, 0x03, 0x3E, 0x00, 0x00, 0xC0, 0x03, 0xFE, 0x00, 0x00, 0xC0, 0x03, 0xFE, 0x01, 0x00, 0xC0, 0x03, 0xFF, 0x03, 0x00, 0xC0, 0x87, 0xEF, 0x0F, 0x00, 0xC0, 0xFF, 0xCF, 0x3F, 0x00, 0x80, 0xFF, 0x8F, 0x7F, 0x00, 0x00, 0xFF, 0x07, 0x7F, 0x00, 0x00, 0xFE, 0x03, 0x7E, 0x00, 0x00, 0xFC, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char R
+        0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x00, 0x7C, 0xC0, 0x07, 0x00, 0x00, 0xFE, 0xC1, 0x0F, 0x00, 0x00, 0xFF, 0xC3, 0x1F, 0x00, 0x80, 0xFF, 0xC3, 0x3F, 0x00, 0x80, 0xFF, 0x07, 0x3F, 0x00, 0xC0, 0xC7, 0x07, 0x7C, 0x00, 0xC0, 0x83, 0x0F, 0x7C, 0x00, 0xC0, 0x83, 0x0F, 0x78, 0x00, 0xC0, 0x83, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x0F, 0x78, 0x00, 0xC0, 0x03, 0x1F, 0x78, 0x00, 0xC0, 0x07, 0x1F, 0x78, 0x00, 0xC0, 0x0F, 0x1F, 0x7C, 0x00, 0x80, 0x3F, 0x3E, 0x3E, 0x00, 0x80, 0x3F, 0xFE, 0x3F, 0x00, 0x00, 0x3F, 0xFC, 0x3F, 0x00, 0x00, 0x3E, 0xFC, 0x1F, 0x00, 0x00, 0x38, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char S
+        0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char T
+        0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0x0F, 0x00, 0xC0, 0xFF, 0xFF, 0x1F, 0x00, 0xC0, 0xFF, 0xFF, 0x3F, 0x00, 0xC0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0xC0, 0xFF, 0xFF, 0x3F, 0x00, 0xC0, 0xFF, 0xFF, 0x3F, 0x00, 0xC0, 0xFF, 0xFF, 0x1F, 0x00, 0xC0, 0xFF, 0xFF, 0x0F, 0x00, 0xC0, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char U
+        0x17, 0x40, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x01, 0x00, 0x00, 0xE0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0xE0, 0xFF, 0x0F, 0x00, 0x00, 0xFC, 0xFF, 0x01, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char V
+        0x21, 0xC0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xFC, 0x7F, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0xF8, 0xFF, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xF8, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0x7F, 0x00, 0x00, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x1F, 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char W
+        0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0xC0, 0x00, 0x00, 0x70, 0x00, 0xC0, 0x01, 0x00, 0x7C, 0x00, 0xC0, 0x07, 0x00, 0x7E, 0x00, 0xC0, 0x0F, 0x80, 0x7F, 0x00, 0xC0, 0x3F, 0xE0, 0x3F, 0x00, 0x80, 0xFF, 0xF0, 0x0F, 0x00, 0x00, 0xFE, 0xFD, 0x07, 0x00, 0x00, 0xF8, 0xFF, 0x01, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0x01, 0x00, 0x00, 0xFE, 0xFD, 0x07, 0x00, 0x80, 0xFF, 0xF0, 0x0F, 0x00, 0xC0, 0x3F, 0xE0, 0x3F, 0x00, 0xC0, 0x0F, 0x80, 0x7F, 0x00, 0xC0, 0x07, 0x00, 0x7E, 0x00, 0xC0, 0x01, 0x00, 0x7C, 0x00, 0xC0, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char X
+        0x17, 0xC0, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x7F, 0x00, 0x00, 0x80, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0xFF, 0x7F, 0x00, 0x00, 0x80, 0xFF, 0x7F, 0x00, 0x00, 0xE0, 0xFF, 0x7F, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Y
+        0x14, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0xC0, 0x03, 0x00, 0x7F, 0x00, 0xC0, 0x03, 0x80, 0x7F, 0x00, 0xC0, 0x03, 0xC0, 0x7F, 0x00, 0xC0, 0x03, 0xF0, 0x7F, 0x00, 0xC0, 0x03, 0xF8, 0x7B, 0x00, 0xC0, 0x03, 0xFC, 0x79, 0x00, 0xC0, 0x03, 0x7E, 0x78, 0x00, 0xC0, 0x03, 0x3F, 0x78, 0x00, 0xC0, 0x83, 0x1F, 0x78, 0x00, 0xC0, 0xE3, 0x0F, 0x78, 0x00, 0xC0, 0xF3, 0x07, 0x78, 0x00, 0xC0, 0xFB, 0x03, 0x78, 0x00, 0xC0, 0xFF, 0x00, 0x78, 0x00, 0xC0, 0x7F, 0x00, 0x78, 0x00, 0xC0, 0x3F, 0x00, 0x78, 0x00, 0xC0, 0x1F, 0x00, 0x78, 0x00, 0xC0, 0x0F, 0x00, 0x78, 0x00, 0xC0, 0x07, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Z
+        0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x3F, 0xC0, 0xFF, 0xFF, 0xFF, 0x3F, 0xC0, 0xFF, 0xFF, 0xFF, 0x3F, 0xC0, 0xFF, 0xFF, 0xFF, 0x3F, 0xC0, 0xFF, 0xFF, 0xFF, 0x3F, 0xC0, 0x03, 0x00, 0x00, 0x3C, 0xC0, 0x03, 0x00, 0x00, 0x3C, 0xC0, 0x03, 0x00, 0x00, 0x3C, 0xC0, 0x03, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char [
+        0x0A, 0xC0, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0x00, 0xC0, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0xF0, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char BackSlash
+        0x09, 0xC0, 0x03, 0x00, 0x00, 0x3C, 0xC0, 0x03, 0x00, 0x00, 0x3C, 0xC0, 0x03, 0x00, 0x00, 0x3C, 0xC0, 0x03, 0x00, 0x00, 0x3C, 0xC0, 0xFF, 0xFF, 0xFF, 0x3F, 0xC0, 0xFF, 0xFF, 0xFF, 0x3F, 0xC0, 0xFF, 0xFF, 0xFF, 0x3F, 0xC0, 0xFF, 0xFF, 0xFF, 0x3F, 0xC0, 0xFF, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ]
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x0F, 0x00, 0x00, 0x00, 0xFF, 0x07, 0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xFC, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ^
+        0x13, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char _
+        0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char `
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0xC1, 0x1F, 0x00, 0x00, 0xC0, 0xE1, 0x3F, 0x00, 0x00, 0xE0, 0xE3, 0x7F, 0x00, 0x00, 0xE0, 0xE3, 0x7F, 0x00, 0x00, 0xF0, 0xF1, 0x7C, 0x00, 0x00, 0xF0, 0x70, 0x78, 0x00, 0x00, 0xF0, 0x70, 0x78, 0x00, 0x00, 0xF0, 0x70, 0x38, 0x00, 0x00, 0xF0, 0x38, 0x3C, 0x00, 0x00, 0xF0, 0x39, 0x1C, 0x00, 0x00, 0xF0, 0xFF, 0x1F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xE0, 0xFF, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0x7F, 0x00, 0x00, 0x80, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char a
+        0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xC0, 0x03, 0x3E, 0x00, 0x00, 0xE0, 0x01, 0x3C, 0x00, 0x00, 0xE0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x01, 0x7C, 0x00, 0x00, 0xF0, 0x03, 0x7E, 0x00, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0xC0, 0xFF, 0x1F, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char b
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0xFF, 0x07, 0x00, 0x00, 0xC0, 0xFF, 0x1F, 0x00, 0x00, 0xC0, 0xFF, 0x1F, 0x00, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0xE0, 0x03, 0x7E, 0x00, 0x00, 0xF0, 0x01, 0x7C, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x7C, 0x00, 0x00, 0xF0, 0x01, 0x7E, 0x00, 0x00, 0xE0, 0x87, 0x3F, 0x00, 0x00, 0xE0, 0x87, 0x3F, 0x00, 0x00, 0xC0, 0x87, 0x1F, 0x00, 0x00, 0x80, 0x03, 0x0F, 0x00, 0x00, 0x00, 0x02, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char c
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0x00, 0x00, 0xC0, 0xFF, 0x1F, 0x00, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0xF0, 0x03, 0x7E, 0x00, 0x00, 0xF0, 0x01, 0x7C, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xE0, 0x00, 0x78, 0x00, 0x00, 0xE0, 0x01, 0x3C, 0x00, 0x00, 0xC0, 0x03, 0x3E, 0x00, 0xC0, 0xFF, 0xFF, 0x1F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char d
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0xFF, 0x07, 0x00, 0x00, 0xC0, 0xFF, 0x1F, 0x00, 0x00, 0xC0, 0xFF, 0x3F, 0x00, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0xF0, 0x73, 0x7E, 0x00, 0x00, 0xF0, 0x71, 0x7C, 0x00, 0x00, 0xF0, 0x70, 0x78, 0x00, 0x00, 0xF0, 0x70, 0x78, 0x00, 0x00, 0xF0, 0x70, 0x78, 0x00, 0x00, 0xF0, 0x71, 0x78, 0x00, 0x00, 0xF0, 0x73, 0x7C, 0x00, 0x00, 0xE0, 0x7F, 0x7C, 0x00, 0x00, 0xC0, 0x7F, 0x3C, 0x00, 0x00, 0xC0, 0x7F, 0x3C, 0x00, 0x00, 0x00, 0x7F, 0x18, 0x00, 0x00, 0x00, 0x7C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char e
+        0x0D, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x7F, 0x00, 0x80, 0xFF, 0xFF, 0x7F, 0x00, 0x80, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xF3, 0x00, 0x00, 0x00, 0xC0, 0xF3, 0x00, 0x00, 0x00, 0xC0, 0xF3, 0x00, 0x00, 0x00, 0xC0, 0xF3, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char f
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0x07, 0x00, 0xC0, 0xFF, 0x1F, 0x0F, 0x00, 0xE0, 0xFF, 0x3F, 0x1F, 0x00, 0xE0, 0xFF, 0x3F, 0x1E, 0x00, 0xF0, 0x03, 0x7E, 0x3E, 0x00, 0xF0, 0x01, 0x7C, 0x3C, 0x00, 0xF0, 0x00, 0x78, 0x3C, 0x00, 0xF0, 0x00, 0x78, 0x3C, 0x00, 0xF0, 0x00, 0x78, 0x3C, 0x00, 0xE0, 0x01, 0x3C, 0x3C, 0x00, 0xE0, 0x03, 0x3E, 0x3E, 0x00, 0x80, 0xFF, 0xFF, 0x3F, 0x00, 0xF0, 0xFF, 0xFF, 0x1F, 0x00, 0xF0, 0xFF, 0xFF, 0x1F, 0x00, 0xF0, 0xFF, 0xFF, 0x0F, 0x00, 0xF0, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char g
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xE0, 0xFF, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0x7F, 0x00, 0x00, 0x80, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char h
+        0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xF3, 0xFF, 0x7F, 0x00, 0xC0, 0xF3, 0xFF, 0x7F, 0x00, 0xC0, 0xF3, 0xFF, 0x7F, 0x00, 0xC0, 0xF3, 0xFF, 0x7F, 0x00, 0xC0, 0xF3, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char i
+        0x07, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3E, 0xC0, 0xF3, 0xFF, 0xFF, 0x3F, 0xC0, 0xF3, 0xFF, 0xFF, 0x3F, 0xC0, 0xF3, 0xFF, 0xFF, 0x1F, 0xC0, 0xF3, 0xFF, 0xFF, 0x1F, 0xC0, 0xF3, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char j
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0xF0, 0xFF, 0x1F, 0x00, 0x00, 0xF0, 0xE3, 0x7F, 0x00, 0x00, 0xF0, 0x81, 0x7F, 0x00, 0x00, 0xF0, 0x00, 0x7E, 0x00, 0x00, 0x30, 0x00, 0x78, 0x00, 0x00, 0x10, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char k
+        0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char l
+        0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0x7F, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xE0, 0xFF, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0x7F, 0x00, 0x00, 0x80, 0xFF, 0x7F, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xE0, 0xFF, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0x7F, 0x00, 0x00, 0x80, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char m
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0x7F, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xE0, 0xFF, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0x7F, 0x00, 0x00, 0x80, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char n
+        0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0xFF, 0x07, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0x00, 0x00, 0xC0, 0xFF, 0x1F, 0x00, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0xE0, 0x07, 0x3F, 0x00, 0x00, 0xF0, 0x01, 0x7C, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x01, 0x7C, 0x00, 0x00, 0xE0, 0x07, 0x3F, 0x00, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0xC0, 0xFF, 0x1F, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char o
+        0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0xFF, 0x3F, 0x00, 0xF0, 0xFF, 0xFF, 0x3F, 0x00, 0xF0, 0xFF, 0xFF, 0x3F, 0x00, 0xF0, 0xFF, 0xFF, 0x3F, 0x00, 0xC0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0x03, 0x1E, 0x00, 0x00, 0xE0, 0x01, 0x3C, 0x00, 0x00, 0xF0, 0x00, 0x38, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x01, 0x7C, 0x00, 0x00, 0xF0, 0x03, 0x7E, 0x00, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0xC0, 0xFF, 0x1F, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char p
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0x00, 0x00, 0xC0, 0xFF, 0x1F, 0x00, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0xF0, 0x03, 0x7E, 0x00, 0x00, 0xF0, 0x01, 0x7C, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x38, 0x00, 0x00, 0xF0, 0x01, 0x3C, 0x00, 0x00, 0xE0, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x3F, 0x00, 0xF0, 0xFF, 0xFF, 0x3F, 0x00, 0xF0, 0xFF, 0xFF, 0x3F, 0x00, 0xF0, 0xFF, 0xFF, 0x3F, 0x00, 0xF0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char q
+        0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0x7F, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char r
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x80, 0x0F, 0x1C, 0x00, 0x00, 0xC0, 0x1F, 0x1E, 0x00, 0x00, 0xE0, 0x3F, 0x3E, 0x00, 0x00, 0xE0, 0x3F, 0x3E, 0x00, 0x00, 0xF0, 0x3F, 0x7C, 0x00, 0x00, 0xF0, 0x7C, 0x78, 0x00, 0x00, 0x70, 0x7C, 0x78, 0x00, 0x00, 0x70, 0x78, 0x78, 0x00, 0x00, 0x70, 0xF8, 0x78, 0x00, 0x00, 0xF0, 0xF8, 0x7C, 0x00, 0x00, 0xF0, 0xF1, 0x7F, 0x00, 0x00, 0xE0, 0xF1, 0x3F, 0x00, 0x00, 0xE0, 0xF1, 0x3F, 0x00, 0x00, 0xC0, 0xE0, 0x1F, 0x00, 0x00, 0x80, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char s
+        0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x3F, 0x00, 0x80, 0xFF, 0xFF, 0x7F, 0x00, 0x80, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char t
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0x00, 0xF0, 0xFF, 0x1F, 0x00, 0x00, 0xF0, 0xFF, 0x3F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0xF0, 0xFF, 0x1F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char u
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0xF0, 0xFF, 0x03, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char v
+        0x1D, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x03, 0x00, 0x00, 0xC0, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0x3F, 0x00, 0x00, 0xF0, 0xFF, 0x03, 0x00, 0x00, 0xF0, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x03, 0x00, 0x00, 0xE0, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0xFC, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0x1F, 0x00, 0x00, 0xF0, 0xFF, 0x03, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char w
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x30, 0x00, 0x70, 0x00, 0x00, 0xF0, 0x00, 0x7C, 0x00, 0x00, 0xF0, 0x01, 0x7E, 0x00, 0x00, 0xF0, 0x87, 0x7F, 0x00, 0x00, 0xF0, 0xDF, 0x3F, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0xCF, 0x3F, 0x00, 0x00, 0xF0, 0x87, 0x7F, 0x00, 0x00, 0xF0, 0x01, 0x7E, 0x00, 0x00, 0x70, 0x00, 0x7C, 0x00, 0x00, 0x30, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char x
+        0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x3C, 0x00, 0xF0, 0x07, 0x00, 0x3C, 0x00, 0xF0, 0x3F, 0x00, 0x3C, 0x00, 0xF0, 0xFF, 0x01, 0x3C, 0x00, 0xC0, 0xFF, 0x07, 0x3E, 0x00, 0x00, 0xFE, 0x3F, 0x3F, 0x00, 0x00, 0xF0, 0xFF, 0x1F, 0x00, 0x00, 0x80, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0xFC, 0x0F, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0xFE, 0x3F, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0xF0, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char y
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xF0, 0x00, 0x7E, 0x00, 0x00, 0xF0, 0x00, 0x7F, 0x00, 0x00, 0xF0, 0x80, 0x7F, 0x00, 0x00, 0xF0, 0xC0, 0x7F, 0x00, 0x00, 0xF0, 0xE0, 0x7B, 0x00, 0x00, 0xF0, 0xF0, 0x79, 0x00, 0x00, 0xF0, 0xF8, 0x78, 0x00, 0x00, 0xF0, 0x7C, 0x78, 0x00, 0x00, 0xF0, 0x3E, 0x78, 0x00, 0x00, 0xF0, 0x1F, 0x78, 0x00, 0x00, 0xF0, 0x0F, 0x78, 0x00, 0x00, 0xF0, 0x07, 0x78, 0x00, 0x00, 0xF0, 0x03, 0x78, 0x00, 0x00, 0xF0, 0x01, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char z
+        0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0x0F, 0x80, 0xFF, 0x9F, 0xFF, 0x1F, 0x80, 0xFF, 0x07, 0xFE, 0x3F, 0xC0, 0x07, 0x00, 0x00, 0x3E, 0xC0, 0x03, 0x00, 0x00, 0x3C, 0xC0, 0x03, 0x00, 0x00, 0x3C, 0xC0, 0x03, 0x00, 0x00, 0x3C, 0xC0, 0x03, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char {
+        0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x7F, 0xC0, 0xFF, 0xFF, 0xFF, 0x7F, 0xC0, 0xFF, 0xFF, 0xFF, 0x7F, 0xC0, 0xFF, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char |
+        0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x3C, 0xC0, 0x03, 0x00, 0x00, 0x3C, 0xC0, 0x03, 0x00, 0x00, 0x3C, 0xC0, 0x03, 0x00, 0x00, 0x3C, 0xC0, 0x07, 0x00, 0x00, 0x3E, 0xC0, 0xFF, 0x07, 0xFE, 0x1F, 0x80, 0xFF, 0x9F, 0xFF, 0x1F, 0x00, 0xFF, 0xFF, 0xFF, 0x0F, 0x00, 0xFE, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char }
+        0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ~
+        0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0xC0, 0xE3, 0x01, 0x00, 0x00, 0xC0, 0xC1, 0x01, 0x00, 0x00, 0xC0, 0xC1, 0x01, 0x00, 0x00, 0xC0, 0xC1, 0x01, 0x00, 0x00, 0xC0, 0xE3, 0x01, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00   // Code for char °
+
+};
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ILI9341/Arial35x38.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,112 @@
+
+//WARNING: This Font Require X-GLCD Lib.
+//         You can not use it with MikroE GLCD Lib.
+
+//Font Generated by MikroElektronika GLCD Font Creator 1.2.0.0
+//MikroElektronika 2011 
+//http://www.mikroe.com 
+
+//GLCD FontName : Arial35x38
+//GLCD FontSize : 35 x 38
+
+const unsigned char Arial35x38[] = {
+        176,35,38,4,
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char  
+        0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x01, 0x38, 0x00, 0xE0, 0xFF, 0xFF, 0x38, 0x00, 0xE0, 0xFF, 0x01, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char !
+        0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char "
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x30, 0x00, 0x00, 0x70, 0xF0, 0x3F, 0x00, 0x00, 0x70, 0xFE, 0x3F, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0x7F, 0x00, 0x00, 0xE0, 0xFF, 0x73, 0x00, 0x00, 0xE0, 0x7F, 0x70, 0x00, 0x00, 0xE0, 0x70, 0x70, 0x38, 0x00, 0x00, 0x70, 0xF0, 0x3F, 0x00, 0x00, 0x70, 0xFE, 0x3F, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0x7F, 0x00, 0x00, 0xE0, 0xFF, 0x73, 0x00, 0x00, 0xE0, 0x7F, 0x70, 0x00, 0x00, 0x60, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char #
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x3E, 0x80, 0x07, 0x00, 0x80, 0xFF, 0x80, 0x0F, 0x00, 0xC0, 0xFF, 0x00, 0x1E, 0x00, 0xC0, 0xE1, 0x01, 0x1C, 0x00, 0xE0, 0xC0, 0x01, 0x38, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xF0, 0xFF, 0xFF, 0xFF, 0x01, 0xF0, 0xFF, 0xFF, 0xFF, 0x01, 0xE0, 0x00, 0x07, 0x38, 0x00, 0xE0, 0x00, 0x07, 0x38, 0x00, 0xC0, 0x01, 0x07, 0x1C, 0x00, 0xC0, 0x07, 0x0E, 0x1E, 0x00, 0x80, 0x07, 0xFE, 0x0F, 0x00, 0x00, 0x06, 0xFC, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char $
+        0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0xE0, 0x81, 0x07, 0x00, 0x00, 0x60, 0x00, 0x06, 0x00, 0x00, 0x60, 0x00, 0x06, 0x00, 0x00, 0x60, 0x00, 0x06, 0x30, 0x00, 0xE0, 0x01, 0x07, 0x3C, 0x00, 0xC0, 0xFF, 0x03, 0x3E, 0x00, 0x80, 0xFF, 0x81, 0x0F, 0x00, 0x00, 0x7E, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x7C, 0xF0, 0x03, 0x00, 0x00, 0x3F, 0xFC, 0x0F, 0x00, 0xC0, 0x0F, 0xFE, 0x1F, 0x00, 0xE0, 0x03, 0x0F, 0x3C, 0x00, 0xE0, 0x00, 0x03, 0x30, 0x00, 0x20, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x0F, 0x38, 0x00, 0x00, 0x00, 0xFE, 0x1F, 0x00, 0x00, 0x00, 0xFC, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char %
+        0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF8, 0x07, 0x00, 0x00, 0x00, 0xFC, 0x0F, 0x00, 0x00, 0x1F, 0x1E, 0x1F, 0x00, 0x80, 0x3F, 0x07, 0x1C, 0x00, 0xC0, 0xFF, 0x07, 0x38, 0x00, 0xE0, 0xF1, 0x03, 0x38, 0x00, 0xE0, 0xC0, 0x03, 0x38, 0x00, 0xE0, 0xC0, 0x07, 0x38, 0x00, 0xE0, 0xE0, 0x1F, 0x38, 0x00, 0xE0, 0xF1, 0x3E, 0x3C, 0x00, 0xC0, 0x7F, 0x78, 0x1C, 0x00, 0x80, 0x3F, 0xF0, 0x1E, 0x00, 0x00, 0x1F, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0x38, 0x3C, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char &
+        0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char '
+        0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x03, 0x00, 0x00, 0xE0, 0xFF, 0x1F, 0x00, 0x00, 0xF8, 0xFF, 0x7F, 0x00, 0x00, 0xFE, 0x00, 0xFC, 0x01, 0x80, 0x0F, 0x00, 0xC0, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x0F, 0xE0, 0x00, 0x00, 0x00, 0x1C, 0x20, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char (
+        0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x10, 0xE0, 0x00, 0x00, 0x00, 0x1C, 0xC0, 0x03, 0x00, 0x00, 0x0F, 0x80, 0x0F, 0x00, 0xC0, 0x07, 0x00, 0xFE, 0x00, 0xFC, 0x01, 0x00, 0xF8, 0xFF, 0x7F, 0x00, 0x00, 0xE0, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char )
+        0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x67, 0x00, 0x00, 0x00, 0x00, 0xF7, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0xF7, 0x00, 0x00, 0x00, 0x00, 0x67, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char *
+        0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x03, 0x00, 0x00, 0xFE, 0xFF, 0x03, 0x00, 0x00, 0xFE, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char +
+        0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x04, 0x00, 0x00, 0x00, 0xF8, 0x07, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ,
+        0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char -
+        0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char .
+        0x0A, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char /
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x03, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x00, 0xC0, 0x0F, 0x80, 0x1F, 0x00, 0xC0, 0x03, 0x00, 0x1E, 0x00, 0xE0, 0x01, 0x00, 0x3C, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x01, 0x00, 0x3C, 0x00, 0xC0, 0x03, 0x00, 0x1E, 0x00, 0xC0, 0x0F, 0x80, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xFE, 0xFF, 0x03, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 0
+        0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 1
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x30, 0x00, 0x00, 0x0F, 0x00, 0x3C, 0x00, 0x80, 0x0F, 0x00, 0x3E, 0x00, 0xC0, 0x03, 0x00, 0x3F, 0x00, 0xC0, 0x01, 0x80, 0x3B, 0x00, 0xE0, 0x01, 0xC0, 0x3B, 0x00, 0xE0, 0x00, 0xE0, 0x39, 0x00, 0xE0, 0x00, 0xE0, 0x38, 0x00, 0xE0, 0x00, 0x70, 0x38, 0x00, 0xE0, 0x00, 0x38, 0x38, 0x00, 0xE0, 0x00, 0x3C, 0x38, 0x00, 0xE0, 0x01, 0x1E, 0x38, 0x00, 0xC0, 0x01, 0x0F, 0x38, 0x00, 0xC0, 0xC3, 0x07, 0x38, 0x00, 0x80, 0xFF, 0x03, 0x38, 0x00, 0x00, 0xFF, 0x00, 0x38, 0x00, 0x00, 0x7E, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 2
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x80, 0x01, 0x00, 0x00, 0x0F, 0x80, 0x07, 0x00, 0x80, 0x0F, 0x80, 0x0F, 0x00, 0xC0, 0x07, 0x00, 0x1F, 0x00, 0xC0, 0x01, 0x00, 0x1C, 0x00, 0xE0, 0x01, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x03, 0x38, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0xC0, 0x03, 0x38, 0x00, 0xC0, 0xC1, 0x03, 0x3C, 0x00, 0xC0, 0xE3, 0x07, 0x1C, 0x00, 0x80, 0xFF, 0x0F, 0x1F, 0x00, 0x80, 0x7F, 0xFE, 0x0F, 0x00, 0x00, 0x1E, 0xFC, 0x07, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 3
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x80, 0xEF, 0x00, 0x00, 0x00, 0xC0, 0xE3, 0x00, 0x00, 0x00, 0xF0, 0xE1, 0x00, 0x00, 0x00, 0xF8, 0xE0, 0x00, 0x00, 0x00, 0x3C, 0xE0, 0x00, 0x00, 0x00, 0x1F, 0xE0, 0x00, 0x00, 0x80, 0x0F, 0xE0, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 4
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x01, 0x00, 0x00, 0xF8, 0x83, 0x07, 0x00, 0x80, 0xFF, 0x83, 0x0F, 0x00, 0xE0, 0xFF, 0x01, 0x1E, 0x00, 0xE0, 0xC7, 0x01, 0x1C, 0x00, 0xE0, 0xC0, 0x00, 0x38, 0x00, 0xE0, 0xE0, 0x00, 0x38, 0x00, 0xE0, 0xE0, 0x00, 0x38, 0x00, 0xE0, 0xE0, 0x00, 0x38, 0x00, 0xE0, 0xE0, 0x00, 0x38, 0x00, 0xE0, 0xE0, 0x00, 0x38, 0x00, 0xE0, 0xE0, 0x01, 0x1C, 0x00, 0xE0, 0xC0, 0x01, 0x1C, 0x00, 0xE0, 0xC0, 0x07, 0x0F, 0x00, 0xE0, 0x80, 0xFF, 0x0F, 0x00, 0xE0, 0x00, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 5
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x03, 0x00, 0x00, 0xFF, 0xFF, 0x07, 0x00, 0x80, 0x1F, 0x0E, 0x0F, 0x00, 0xC0, 0x07, 0x03, 0x1E, 0x00, 0xC0, 0x81, 0x03, 0x1C, 0x00, 0xE0, 0x81, 0x01, 0x38, 0x00, 0xE0, 0xC0, 0x01, 0x38, 0x00, 0xE0, 0xC0, 0x01, 0x38, 0x00, 0xE0, 0xC0, 0x01, 0x38, 0x00, 0xE0, 0xC0, 0x01, 0x38, 0x00, 0xE0, 0xC0, 0x03, 0x3C, 0x00, 0xC0, 0x81, 0x03, 0x1C, 0x00, 0xC0, 0x87, 0x07, 0x1F, 0x00, 0x80, 0x0F, 0xFF, 0x0F, 0x00, 0x00, 0x0F, 0xFE, 0x07, 0x00, 0x00, 0x0C, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 6
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x3C, 0x00, 0xE0, 0x00, 0xC0, 0x3F, 0x00, 0xE0, 0x00, 0xF8, 0x3F, 0x00, 0xE0, 0x00, 0xFE, 0x03, 0x00, 0xE0, 0x80, 0x3F, 0x00, 0x00, 0xE0, 0xC0, 0x07, 0x00, 0x00, 0xE0, 0xF0, 0x01, 0x00, 0x00, 0xE0, 0x78, 0x00, 0x00, 0x00, 0xE0, 0x1C, 0x00, 0x00, 0x00, 0xE0, 0x0E, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 7
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x3E, 0xFC, 0x07, 0x00, 0x80, 0x7F, 0xFE, 0x0F, 0x00, 0xC0, 0xFF, 0x0E, 0x1E, 0x00, 0xC0, 0xE3, 0x07, 0x1C, 0x00, 0xE0, 0xC1, 0x03, 0x3C, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0xC1, 0x07, 0x38, 0x00, 0xC0, 0xE3, 0x07, 0x1C, 0x00, 0x80, 0xFF, 0x0E, 0x1E, 0x00, 0x80, 0x7F, 0xFE, 0x0F, 0x00, 0x00, 0x3E, 0xFC, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 8
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x80, 0x01, 0x00, 0x00, 0xFF, 0x83, 0x07, 0x00, 0x80, 0xFF, 0x87, 0x0F, 0x00, 0xC0, 0x07, 0x0F, 0x1E, 0x00, 0xC0, 0x01, 0x0E, 0x1C, 0x00, 0xE0, 0x01, 0x1E, 0x38, 0x00, 0xE0, 0x00, 0x1C, 0x38, 0x00, 0xE0, 0x00, 0x1C, 0x38, 0x00, 0xE0, 0x00, 0x1C, 0x38, 0x00, 0xE0, 0x00, 0x1C, 0x38, 0x00, 0xE0, 0x00, 0x0C, 0x3C, 0x00, 0xE0, 0x01, 0x0E, 0x1C, 0x00, 0xC0, 0x01, 0x06, 0x1E, 0x00, 0xC0, 0x87, 0xC3, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0xFF, 0x01, 0x00, 0x00, 0xF0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 9
+        0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char :
+        0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x38, 0x04, 0x00, 0x70, 0x00, 0xF8, 0x07, 0x00, 0x70, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ;
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x1D, 0x00, 0x00, 0x00, 0xC0, 0x1D, 0x00, 0x00, 0x00, 0xC0, 0x18, 0x00, 0x00, 0x00, 0xE0, 0x38, 0x00, 0x00, 0x00, 0xE0, 0x38, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x38, 0xE0, 0x00, 0x00, 0x00, 0x38, 0xE0, 0x00, 0x00, 0x00, 0x18, 0xC0, 0x00, 0x00, 0x00, 0x1C, 0xC0, 0x01, 0x00, 0x00, 0x1C, 0xC0, 0x01, 0x00, 0x00, 0x0E, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char <
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char =
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x80, 0x03, 0x00, 0x00, 0x1C, 0xC0, 0x01, 0x00, 0x00, 0x1C, 0xC0, 0x01, 0x00, 0x00, 0x18, 0xC0, 0x00, 0x00, 0x00, 0x38, 0xE0, 0x00, 0x00, 0x00, 0x38, 0xE0, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0xE0, 0x38, 0x00, 0x00, 0x00, 0xE0, 0x38, 0x00, 0x00, 0x00, 0xC0, 0x18, 0x00, 0x00, 0x00, 0xC0, 0x1D, 0x00, 0x00, 0x00, 0xC0, 0x1D, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char >
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x00, 0xF0, 0x38, 0x00, 0xE0, 0x00, 0xFC, 0x38, 0x00, 0xE0, 0x00, 0xFE, 0x38, 0x00, 0xE0, 0x00, 0x1F, 0x00, 0x00, 0xE0, 0x80, 0x07, 0x00, 0x00, 0xE0, 0xC1, 0x03, 0x00, 0x00, 0xC0, 0xE3, 0x01, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ?
+        0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x80, 0xFF, 0x1F, 0x00, 0x00, 0xE0, 0xFF, 0x7F, 0x00, 0x00, 0xF8, 0x03, 0xFC, 0x00, 0x00, 0x7C, 0x00, 0xF0, 0x01, 0x00, 0x1E, 0x00, 0xE0, 0x03, 0x00, 0x0F, 0xF8, 0x81, 0x03, 0x80, 0x07, 0xFE, 0x87, 0x07, 0x80, 0x03, 0xFF, 0x1F, 0x07, 0xC0, 0xC3, 0x0F, 0x1E, 0x0F, 0xC0, 0xC1, 0x03, 0x3C, 0x0E, 0xC0, 0xE1, 0x01, 0x38, 0x0E, 0xE0, 0xF1, 0x00, 0x38, 0x1E, 0xE0, 0x70, 0x00, 0x38, 0x1C, 0xE0, 0x70, 0x00, 0x38, 0x1C, 0xE0, 0x70, 0x00, 0x1C, 0x1C, 0xE0, 0x70, 0x00, 0x1E, 0x1C, 0xE0, 0xE0, 0x00, 0x0F, 0x1C, 0xE0, 0xE0, 0xC1, 0x1F, 0x1C, 0xE0, 0xC0, 0xFF, 0x3F, 0x1C, 0xE0, 0xC1, 0xFF, 0x3F, 0x1C, 0xC0, 0xF1, 0x7F, 0x38, 0x1C, 0xC0, 0xF1, 0x07, 0x38, 0x0E, 0xC0, 0x33, 0x00, 0x3C, 0x0E, 0x80, 0x07, 0x00, 0x1C, 0x0E, 0x80, 0x0F, 0x00, 0x1E, 0x07, 0x00, 0x1F, 0x80, 0x8F, 0x07, 0x00, 0x7E, 0xE0, 0x87, 0x03, 0x00, 0xFC, 0xFF, 0xC3, 0x01, 0x00, 0xF0, 0xFF, 0xE0, 0x00, 0x00, 0xC0, 0x3F, 0x60, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char @
+        0x17, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0xFC, 0x3B, 0x00, 0x00, 0x00, 0xFF, 0x38, 0x00, 0x00, 0xE0, 0x1F, 0x38, 0x00, 0x00, 0xE0, 0x07, 0x38, 0x00, 0x00, 0xE0, 0x00, 0x38, 0x00, 0x00, 0xE0, 0x07, 0x38, 0x00, 0x00, 0xE0, 0x1F, 0x38, 0x00, 0x00, 0x00, 0xFF, 0x38, 0x00, 0x00, 0x00, 0xFC, 0x3B, 0x00, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char A
+        0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0xC1, 0x03, 0x38, 0x00, 0xC0, 0xE3, 0x07, 0x1C, 0x00, 0xC0, 0xFF, 0x0F, 0x1E, 0x00, 0x80, 0x7F, 0xFE, 0x0F, 0x00, 0x00, 0x1E, 0xFC, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char B
+        0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x03, 0x00, 0x00, 0x3F, 0xE0, 0x07, 0x00, 0x80, 0x07, 0x00, 0x0F, 0x00, 0xC0, 0x03, 0x00, 0x1E, 0x00, 0xC0, 0x01, 0x00, 0x1C, 0x00, 0xE0, 0x01, 0x00, 0x3C, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x01, 0x00, 0x38, 0x00, 0xC0, 0x01, 0x00, 0x3C, 0x00, 0xC0, 0x03, 0x00, 0x1E, 0x00, 0x80, 0x0F, 0x00, 0x1F, 0x00, 0x00, 0x1F, 0x80, 0x0F, 0x00, 0x00, 0x1E, 0xE0, 0x07, 0x00, 0x00, 0x08, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char C
+        0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x3C, 0x00, 0xC0, 0x01, 0x00, 0x1C, 0x00, 0xC0, 0x03, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x0F, 0x00, 0x80, 0x1F, 0xC0, 0x0F, 0x00, 0x00, 0xFE, 0xFF, 0x03, 0x00, 0x00, 0xFC, 0xFF, 0x01, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char D
+        0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0x00, 0x07, 0x38, 0x00, 0xE0, 0x00, 0x07, 0x38, 0x00, 0xE0, 0x00, 0x07, 0x38, 0x00, 0xE0, 0x00, 0x07, 0x38, 0x00, 0xE0, 0x00, 0x07, 0x38, 0x00, 0xE0, 0x00, 0x07, 0x38, 0x00, 0xE0, 0x00, 0x07, 0x38, 0x00, 0xE0, 0x00, 0x07, 0x38, 0x00, 0xE0, 0x00, 0x07, 0x38, 0x00, 0xE0, 0x00, 0x07, 0x38, 0x00, 0xE0, 0x00, 0x07, 0x38, 0x00, 0xE0, 0x00, 0x07, 0x38, 0x00, 0xE0, 0x00, 0x07, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char E
+        0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char F
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x03, 0x00, 0x00, 0x3F, 0xE0, 0x07, 0x00, 0x80, 0x0F, 0x80, 0x0F, 0x00, 0x80, 0x03, 0x00, 0x0E, 0x00, 0xC0, 0x03, 0x00, 0x1E, 0x00, 0xC0, 0x01, 0x00, 0x1C, 0x00, 0xE0, 0x01, 0x00, 0x1C, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x0E, 0x38, 0x00, 0xE0, 0x00, 0x0E, 0x38, 0x00, 0xE0, 0x00, 0x0E, 0x38, 0x00, 0xE0, 0x00, 0x0E, 0x38, 0x00, 0xC0, 0x01, 0x0E, 0x3C, 0x00, 0xC0, 0x01, 0x0E, 0x1C, 0x00, 0xC0, 0x03, 0x0E, 0x1E, 0x00, 0x80, 0x0F, 0x0E, 0x0E, 0x00, 0x00, 0x1F, 0xFE, 0x0F, 0x00, 0x00, 0x1E, 0xFE, 0x07, 0x00, 0x00, 0x00, 0xFE, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char G
+        0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char H
+        0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char I
+        0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0xE0, 0xFF, 0xFF, 0x1F, 0x00, 0xE0, 0xFF, 0xFF, 0x0F, 0x00, 0xE0, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char J
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0x3C, 0x1E, 0x00, 0x00, 0x00, 0x1E, 0x3C, 0x00, 0x00, 0x00, 0x0F, 0xF8, 0x00, 0x00, 0x80, 0x07, 0xF0, 0x01, 0x00, 0xC0, 0x03, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x80, 0x0F, 0x00, 0xE0, 0x00, 0x00, 0x1F, 0x00, 0x60, 0x00, 0x00, 0x3C, 0x00, 0x20, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char K
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char L
+        0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xF0, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0x1F, 0x00, 0x00, 0x00, 0xFE, 0x03, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char M
+        0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char N
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x03, 0x00, 0x00, 0x3F, 0xE0, 0x07, 0x00, 0x80, 0x07, 0x80, 0x0F, 0x00, 0x80, 0x03, 0x00, 0x0E, 0x00, 0xC0, 0x01, 0x00, 0x1E, 0x00, 0xC0, 0x01, 0x00, 0x1C, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xC0, 0x01, 0x00, 0x1C, 0x00, 0xC0, 0x03, 0x00, 0x1E, 0x00, 0x80, 0x03, 0x00, 0x0E, 0x00, 0x80, 0x0F, 0x80, 0x0F, 0x00, 0x00, 0x3F, 0xE0, 0x07, 0x00, 0x00, 0xFE, 0xFF, 0x03, 0x00, 0x00, 0xF8, 0xFF, 0x00, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char O
+        0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x01, 0x07, 0x00, 0x00, 0xC0, 0x83, 0x07, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char P
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x03, 0x00, 0x00, 0x3F, 0xE0, 0x07, 0x00, 0x80, 0x07, 0x00, 0x0F, 0x00, 0xC0, 0x03, 0x00, 0x1E, 0x00, 0xC0, 0x01, 0x00, 0x1C, 0x00, 0xC0, 0x01, 0x00, 0x1C, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x39, 0x00, 0xE0, 0x00, 0x80, 0x3B, 0x00, 0xE0, 0x00, 0x80, 0x3B, 0x00, 0xC0, 0x01, 0x00, 0x3F, 0x00, 0xC0, 0x01, 0x00, 0x1F, 0x00, 0xC0, 0x03, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1F, 0x00, 0x00, 0x3F, 0xE0, 0x3F, 0x00, 0x00, 0xFE, 0xFF, 0x7B, 0x00, 0x00, 0xF8, 0xFF, 0x70, 0x00, 0x00, 0xE0, 0x3F, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Q
+        0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x0F, 0x00, 0x00, 0xE0, 0x00, 0x1F, 0x00, 0x00, 0xE0, 0x00, 0x3F, 0x00, 0x00, 0xE0, 0x00, 0xFF, 0x00, 0x00, 0xE0, 0x80, 0xF7, 0x01, 0x00, 0xE0, 0x81, 0xE3, 0x07, 0x00, 0xC0, 0xC3, 0xC3, 0x0F, 0x00, 0xC0, 0xFF, 0x01, 0x3F, 0x00, 0x80, 0xFF, 0x00, 0x3E, 0x00, 0x00, 0x7E, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char R
+        0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x3E, 0xE0, 0x03, 0x00, 0x00, 0xFF, 0xE0, 0x07, 0x00, 0x80, 0xFF, 0x80, 0x0F, 0x00, 0xC0, 0xE3, 0x01, 0x1E, 0x00, 0xC0, 0xC1, 0x01, 0x1C, 0x00, 0xE0, 0x80, 0x03, 0x3C, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0x80, 0x03, 0x38, 0x00, 0xE0, 0x80, 0x07, 0x38, 0x00, 0xE0, 0x00, 0x07, 0x38, 0x00, 0xE0, 0x00, 0x07, 0x38, 0x00, 0xE0, 0x01, 0x07, 0x38, 0x00, 0xC0, 0x01, 0x0F, 0x3C, 0x00, 0xC0, 0x03, 0x0E, 0x1C, 0x00, 0x80, 0x0F, 0x1E, 0x1E, 0x00, 0x00, 0x0F, 0xFC, 0x0F, 0x00, 0x00, 0x0C, 0xF8, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char S
+        0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char T
+        0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x03, 0x00, 0xE0, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0xE0, 0xFF, 0xFF, 0x0F, 0x00, 0xE0, 0xFF, 0xFF, 0x03, 0x00, 0xE0, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char U
+        0x17, 0x60, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char V
+        0x23, 0x60, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xF8, 0x7F, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xF8, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0x3F, 0x00, 0x00, 0x00, 0xFE, 0x07, 0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0xF8, 0x3F, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0xF8, 0x7F, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00,  // Code for char W
+        0x17, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, 0x00, 0x30, 0x00, 0x60, 0x00, 0x00, 0x38, 0x00, 0xE0, 0x00, 0x00, 0x3E, 0x00, 0xE0, 0x03, 0x00, 0x1F, 0x00, 0xC0, 0x07, 0x80, 0x07, 0x00, 0x00, 0x0F, 0xE0, 0x03, 0x00, 0x00, 0x3E, 0xF0, 0x01, 0x00, 0x00, 0x7C, 0x78, 0x00, 0x00, 0x00, 0xF0, 0x3E, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0xF0, 0x3F, 0x00, 0x00, 0x00, 0x7C, 0x78, 0x00, 0x00, 0x00, 0x3E, 0xF0, 0x01, 0x00, 0x00, 0x0F, 0xE0, 0x03, 0x00, 0xC0, 0x07, 0x80, 0x07, 0x00, 0xE0, 0x03, 0x00, 0x1F, 0x00, 0xE0, 0x00, 0x00, 0x3E, 0x00, 0x60, 0x00, 0x00, 0x38, 0x00, 0x20, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char X
+        0x17, 0x20, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0xFE, 0x3F, 0x00, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Y
+        0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0xE0, 0x00, 0x00, 0x3F, 0x00, 0xE0, 0x00, 0xC0, 0x3F, 0x00, 0xE0, 0x00, 0xE0, 0x3B, 0x00, 0xE0, 0x00, 0xF0, 0x38, 0x00, 0xE0, 0x00, 0x7C, 0x38, 0x00, 0xE0, 0x00, 0x3E, 0x38, 0x00, 0xE0, 0x00, 0x0F, 0x38, 0x00, 0xE0, 0xC0, 0x07, 0x38, 0x00, 0xE0, 0xE0, 0x03, 0x38, 0x00, 0xE0, 0xF0, 0x01, 0x38, 0x00, 0xE0, 0x7C, 0x00, 0x38, 0x00, 0xE0, 0x3E, 0x00, 0x38, 0x00, 0xE0, 0x1F, 0x00, 0x38, 0x00, 0xE0, 0x07, 0x00, 0x38, 0x00, 0xE0, 0x03, 0x00, 0x38, 0x00, 0xE0, 0x01, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Z
+        0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0xFF, 0x1F, 0xE0, 0xFF, 0xFF, 0xFF, 0x1F, 0xE0, 0xFF, 0xFF, 0xFF, 0x1F, 0xE0, 0x00, 0x00, 0x00, 0x1C, 0xE0, 0x00, 0x00, 0x00, 0x1C, 0xE0, 0x00, 0x00, 0x00, 0x1C, 0xE0, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char [
+        0x0A, 0x60, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char BackSlash
+        0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x1C, 0xE0, 0x00, 0x00, 0x00, 0x1C, 0xE0, 0x00, 0x00, 0x00, 0x1C, 0xE0, 0x00, 0x00, 0x00, 0x1C, 0xE0, 0xFF, 0xFF, 0xFF, 0x1F, 0xE0, 0xFF, 0xFF, 0xFF, 0x1F, 0xE0, 0xFF, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ]
+        0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ^
+        0x13, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char _
+        0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char `
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x07, 0x00, 0x00, 0xC0, 0xC3, 0x1F, 0x00, 0x00, 0xE0, 0xE3, 0x1F, 0x00, 0x00, 0xE0, 0xE1, 0x3C, 0x00, 0x00, 0xE0, 0x70, 0x38, 0x00, 0x00, 0x70, 0x70, 0x38, 0x00, 0x00, 0x70, 0x70, 0x38, 0x00, 0x00, 0x70, 0x70, 0x38, 0x00, 0x00, 0x70, 0x70, 0x38, 0x00, 0x00, 0x70, 0x78, 0x1C, 0x00, 0x00, 0xF0, 0x38, 0x1C, 0x00, 0x00, 0xF0, 0x38, 0x0E, 0x00, 0x00, 0xE0, 0xFF, 0x1F, 0x00, 0x00, 0xC0, 0xFF, 0x3F, 0x00, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char a
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0xC0, 0x03, 0x0F, 0x00, 0x00, 0xE0, 0x01, 0x1C, 0x00, 0x00, 0xE0, 0x00, 0x1C, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0xF0, 0x00, 0x3C, 0x00, 0x00, 0xE0, 0x00, 0x1E, 0x00, 0x00, 0xE0, 0x03, 0x1F, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char b
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0x03, 0x1F, 0x00, 0x00, 0xE0, 0x00, 0x1C, 0x00, 0x00, 0xF0, 0x00, 0x3C, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0xE0, 0x00, 0x1C, 0x00, 0x00, 0xE0, 0x01, 0x1E, 0x00, 0x00, 0xC0, 0x83, 0x0F, 0x00, 0x00, 0x80, 0x83, 0x07, 0x00, 0x00, 0x00, 0x83, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char c
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0x03, 0x1F, 0x00, 0x00, 0xE0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x3C, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0xE0, 0x00, 0x1C, 0x00, 0x00, 0xE0, 0x00, 0x1C, 0x00, 0x00, 0xC0, 0x03, 0x0F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char d
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0x39, 0x1F, 0x00, 0x00, 0xE0, 0x38, 0x1C, 0x00, 0x00, 0xF0, 0x38, 0x3C, 0x00, 0x00, 0x70, 0x38, 0x38, 0x00, 0x00, 0x70, 0x38, 0x38, 0x00, 0x00, 0x70, 0x38, 0x38, 0x00, 0x00, 0x70, 0x38, 0x38, 0x00, 0x00, 0x70, 0x38, 0x38, 0x00, 0x00, 0xE0, 0x38, 0x1C, 0x00, 0x00, 0xE0, 0x39, 0x1E, 0x00, 0x00, 0xC0, 0x3F, 0x0F, 0x00, 0x00, 0x80, 0x3F, 0x07, 0x00, 0x00, 0x00, 0x3E, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char e
+        0x0B, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x3F, 0x00, 0xC0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0x71, 0x00, 0x00, 0x00, 0xE0, 0x70, 0x00, 0x00, 0x00, 0xE0, 0x70, 0x00, 0x00, 0x00, 0xE0, 0x70, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char f
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x80, 0x03, 0x00, 0x80, 0xFF, 0x87, 0x07, 0x00, 0xC0, 0xFF, 0x8F, 0x0F, 0x00, 0xE0, 0x03, 0x1F, 0x0F, 0x00, 0xE0, 0x00, 0x1C, 0x1E, 0x00, 0xF0, 0x00, 0x3C, 0x1C, 0x00, 0x70, 0x00, 0x38, 0x1C, 0x00, 0x70, 0x00, 0x38, 0x1C, 0x00, 0x70, 0x00, 0x38, 0x1C, 0x00, 0x70, 0x00, 0x38, 0x1C, 0x00, 0xE0, 0x00, 0x3C, 0x1C, 0x00, 0xE0, 0x00, 0x1C, 0x0E, 0x00, 0xC0, 0x03, 0x0F, 0x0F, 0x00, 0xF0, 0xFF, 0xFF, 0x07, 0x00, 0xF0, 0xFF, 0xFF, 0x03, 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char g
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0xC0, 0xFF, 0x3F, 0x00, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char h
+        0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xF0, 0xFF, 0x3F, 0x00, 0xE0, 0xF0, 0xFF, 0x3F, 0x00, 0xE0, 0xF0, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char i
+        0x06, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1E, 0xE0, 0xF0, 0xFF, 0xFF, 0x1F, 0xE0, 0xF0, 0xFF, 0xFF, 0x0F, 0xE0, 0xF0, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char j
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x01, 0x00, 0x00, 0xC0, 0xE3, 0x03, 0x00, 0x00, 0xE0, 0x81, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x1F, 0x00, 0x00, 0x70, 0x00, 0x3E, 0x00, 0x00, 0x30, 0x00, 0x38, 0x00, 0x00, 0x10, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char k
+        0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char l
+        0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x3F, 0x00, 0x00, 0xF0, 0xFF, 0x3F, 0x00, 0x00, 0xF0, 0xFF, 0x3F, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0xC0, 0xFF, 0x3F, 0x00, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char m
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x3F, 0x00, 0x00, 0xF0, 0xFF, 0x3F, 0x00, 0x00, 0xF0, 0xFF, 0x3F, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0xC0, 0xFF, 0x3F, 0x00, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char n
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0x03, 0x1F, 0x00, 0x00, 0xE0, 0x00, 0x1C, 0x00, 0x00, 0xF0, 0x00, 0x3C, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0xF0, 0x00, 0x3C, 0x00, 0x00, 0xE0, 0x00, 0x1C, 0x00, 0x00, 0xE0, 0x03, 0x1F, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char o
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0xFF, 0x1F, 0x00, 0xF0, 0xFF, 0xFF, 0x1F, 0x00, 0xF0, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0x03, 0x0F, 0x00, 0x00, 0xE0, 0x01, 0x1C, 0x00, 0x00, 0xE0, 0x00, 0x1C, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0xF0, 0x00, 0x3C, 0x00, 0x00, 0xE0, 0x00, 0x1C, 0x00, 0x00, 0xE0, 0x03, 0x1F, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char p
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0x03, 0x1F, 0x00, 0x00, 0xE0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x3C, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0xE0, 0x00, 0x1C, 0x00, 0x00, 0xE0, 0x01, 0x1C, 0x00, 0x00, 0x80, 0x03, 0x0F, 0x00, 0x00, 0xF0, 0xFF, 0xFF, 0x1F, 0x00, 0xF0, 0xFF, 0xFF, 0x1F, 0x00, 0xF0, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char q
+        0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x3F, 0x00, 0x00, 0xF0, 0xFF, 0x3F, 0x00, 0x00, 0xF0, 0xFF, 0x3F, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char r
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x03, 0x00, 0x00, 0xC0, 0x0F, 0x07, 0x00, 0x00, 0xE0, 0x1F, 0x0F, 0x00, 0x00, 0xE0, 0x1C, 0x1E, 0x00, 0x00, 0x70, 0x3C, 0x1C, 0x00, 0x00, 0x70, 0x3C, 0x38, 0x00, 0x00, 0x70, 0x38, 0x38, 0x00, 0x00, 0x70, 0x78, 0x38, 0x00, 0x00, 0x70, 0x78, 0x38, 0x00, 0x00, 0x70, 0x78, 0x38, 0x00, 0x00, 0x70, 0x70, 0x38, 0x00, 0x00, 0xE0, 0x70, 0x3C, 0x00, 0x00, 0xE0, 0xF1, 0x1C, 0x00, 0x00, 0xC0, 0xF1, 0x1F, 0x00, 0x00, 0x80, 0xE1, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char s
+        0x0A, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0xC0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char t
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0xF0, 0xFF, 0x3F, 0x00, 0x00, 0xF0, 0xFF, 0x3F, 0x00, 0x00, 0xF0, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char u
+        0x11, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char v
+        0x19, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0xFC, 0x0F, 0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char w
+        0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x00, 0x30, 0x00, 0x30, 0x00, 0x00, 0xF0, 0x00, 0x38, 0x00, 0x00, 0xF0, 0x01, 0x3E, 0x00, 0x00, 0xE0, 0x03, 0x1F, 0x00, 0x00, 0x80, 0xCF, 0x07, 0x00, 0x00, 0x00, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x03, 0x00, 0x00, 0x80, 0xCF, 0x07, 0x00, 0x00, 0xC0, 0x07, 0x1F, 0x00, 0x00, 0xE0, 0x03, 0x3E, 0x00, 0x00, 0xF0, 0x00, 0x3C, 0x00, 0x00, 0x70, 0x00, 0x30, 0x00, 0x00, 0x10, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char x
+        0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x1C, 0x00, 0xF0, 0x07, 0x00, 0x1C, 0x00, 0xE0, 0x3F, 0x00, 0x1C, 0x00, 0x00, 0xFF, 0x01, 0x1E, 0x00, 0x00, 0xF8, 0x8F, 0x0F, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xFE, 0x03, 0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0xFF, 0x03, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char y
+        0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x3E, 0x00, 0x00, 0x70, 0x00, 0x3F, 0x00, 0x00, 0x70, 0x80, 0x3F, 0x00, 0x00, 0x70, 0xC0, 0x3B, 0x00, 0x00, 0x70, 0xE0, 0x39, 0x00, 0x00, 0x70, 0xF0, 0x38, 0x00, 0x00, 0x70, 0x78, 0x38, 0x00, 0x00, 0x70, 0x3C, 0x38, 0x00, 0x00, 0x70, 0x1F, 0x38, 0x00, 0x00, 0xF0, 0x07, 0x38, 0x00, 0x00, 0xF0, 0x03, 0x38, 0x00, 0x00, 0xF0, 0x01, 0x38, 0x00, 0x00, 0xF0, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char z
+        0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0xEE, 0x00, 0x00, 0x80, 0xFF, 0xEF, 0xFF, 0x03, 0xC0, 0xFF, 0xC7, 0xFF, 0x0F, 0xC0, 0xFF, 0x01, 0xFF, 0x0F, 0xE0, 0x01, 0x00, 0x00, 0x1E, 0xE0, 0x00, 0x00, 0x00, 0x1C, 0xE0, 0x00, 0x00, 0x00, 0x1C, 0xE0, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char {
+        0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0xFF, 0x3F, 0xE0, 0xFF, 0xFF, 0xFF, 0x3F, 0xE0, 0xFF, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char |
+        0x1A, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0x3C, 0xE0, 0x01, 0x00, 0x00, 0x0E, 0x80, 0x03, 0x00, 0x00, 0x07, 0x00, 0x07, 0x00, 0x80, 0x03, 0x00, 0x0E, 0x00, 0x80, 0xC1, 0x1F, 0x0C, 0x00, 0xC0, 0xF0, 0x7F, 0x18, 0x00, 0xC0, 0x78, 0xF0, 0x18, 0x00, 0xE0, 0x18, 0xC0, 0x38, 0x00, 0x60, 0x1C, 0x80, 0x31, 0x00, 0x60, 0x0C, 0x80, 0x31, 0x00, 0x60, 0x0C, 0x80, 0x31, 0x00, 0x60, 0x0C, 0x80, 0x31, 0x00, 0x60, 0x0C, 0x80, 0x31, 0x00, 0x60, 0x1C, 0xC0, 0x30, 0x00, 0xE0, 0x38, 0xF0, 0x38, 0x00, 0xC0, 0x70, 0x78, 0x18, 0x00, 0xC0, 0x20, 0x10, 0x18, 0x00, 0x80, 0x01, 0x00, 0x0C, 0x00, 0x80, 0x03, 0x00, 0x0E, 0x00, 0x00, 0x07, 0x00, 0x07, 0x00, 0x00, 0x0E, 0x80, 0x03, 0x00, 0x00, 0x3C, 0xE0, 0x01, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char }
+        0x1A, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0x3C, 0xE0, 0x01, 0x00, 0x00, 0x0E, 0x80, 0x03, 0x00, 0x00, 0x07, 0x00, 0x07, 0x00, 0x80, 0x03, 0x00, 0x0E, 0x00, 0x80, 0x01, 0x00, 0x0C, 0x00, 0xC0, 0xFC, 0xFF, 0x19, 0x00, 0xC0, 0xFC, 0xFF, 0x19, 0x00, 0xE0, 0x0C, 0x06, 0x38, 0x00, 0x60, 0x0C, 0x06, 0x30, 0x00, 0x60, 0x0C, 0x06, 0x30, 0x00, 0x60, 0x0C, 0x0E, 0x30, 0x00, 0x60, 0x0C, 0x1E, 0x30, 0x00, 0x60, 0x0C, 0x3E, 0x30, 0x00, 0x60, 0x1C, 0x77, 0x30, 0x00, 0xE0, 0xF8, 0xE3, 0x39, 0x00, 0xC0, 0xF0, 0x81, 0x19, 0x00, 0xC0, 0x00, 0x00, 0x19, 0x00, 0x80, 0x01, 0x00, 0x0C, 0x00, 0x80, 0x03, 0x00, 0x0E, 0x00, 0x00, 0x07, 0x00, 0x07, 0x00, 0x00, 0x0E, 0x80, 0x03, 0x00, 0x00, 0x3C, 0xE0, 0x01, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ~
+        0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xE0, 0x38, 0x00, 0x00, 0x00, 0x60, 0x30, 0x00, 0x00, 0x00, 0x60, 0x30, 0x00, 0x00, 0x00, 0x60, 0x30, 0x00, 0x00, 0x00, 0xE0, 0x38, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 
+        };
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ILI9341/Arial48x51.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,161 @@
+
+//WARNING: This Font Require X-GLCD Lib.
+//         You can not use it with MikroE GLCD Lib.
+
+//Font Generated by MikroElektronika GLCD Font Creator 1.2.0.0
+//MikroElektronika 2011 
+//http://www.mikroe.com 
+
+//GLCD FontName : Arial48x51
+//GLCD FontSize : 48 x 51
+
+const unsigned char Arial48x51[] = {
+        337,48,51,6,
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char  
+        0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x7F, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xE1, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xE1, 0x01, 0x00, 0xC0, 0xFF, 0x7F, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char !
+        0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char "
+        0x1A, 0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0xC0, 0x01, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x8F, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xF0, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0xF0, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x0F, 0xF0, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x0F, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0xC0, 0x01, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x8F, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x7F, 0xF0, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0xF0, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x0F, 0xF0, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x0F, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char #
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x80, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x0F, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0xFE, 0x1F, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x7F, 0x00, 0x00, 0x80, 0x1F, 0x7E, 0x00, 0xFC, 0x00, 0x00, 0x80, 0x0F, 0x78, 0x00, 0xF8, 0x00, 0x00, 0xC0, 0x07, 0xF8, 0x00, 0xF0, 0x01, 0x00, 0xC0, 0x03, 0xF0, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xF0, 0x00, 0xE0, 0x01, 0x00, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0x1F, 0x00, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0x1F, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x07, 0xC0, 0x03, 0xF0, 0x01, 0x00, 0x80, 0x0F, 0xC0, 0x03, 0xF0, 0x00, 0x00, 0x80, 0x1F, 0xC0, 0x07, 0xF8, 0x00, 0x00, 0x00, 0x7F, 0x80, 0x0F, 0x7E, 0x00, 0x00, 0x00, 0x7E, 0x80, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x3C, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x30, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char $
+        0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0F, 0xF8, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x01, 0xC0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x01, 0xC0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x01, 0xC0, 0x01, 0x00, 0x01, 0x00, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0x00, 0x80, 0x03, 0xE0, 0x00, 0xF0, 0x01, 0x00, 0x80, 0x0F, 0xF8, 0x00, 0xF8, 0x01, 0x00, 0x00, 0xFF, 0x7F, 0x00, 0x7E, 0x00, 0x00, 0x00, 0xFE, 0x3F, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0x7E, 0x00, 0xFE, 0x3F, 0x00, 0x00, 0x80, 0x1F, 0x00, 0xFF, 0x7F, 0x00, 0x00, 0xC0, 0x0F, 0x80, 0x0F, 0xF8, 0x00, 0x00, 0xC0, 0x03, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0xC0, 0x00, 0xC0, 0x01, 0xC0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x01, 0xC0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x01, 0xC0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x01, 0xC0, 0x01, 0x00, 0x00, 0x00, 0x80, 0x03, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0F, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char %
+        0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0xF8, 0x80, 0x1F, 0x7E, 0x00, 0x00, 0x00, 0xFE, 0x83, 0x07, 0xF8, 0x00, 0x00, 0x00, 0xFF, 0xC7, 0x03, 0xF0, 0x00, 0x00, 0x00, 0xFF, 0xCF, 0x03, 0xF0, 0x01, 0x00, 0x80, 0x0F, 0xFF, 0x01, 0xE0, 0x01, 0x00, 0x80, 0x07, 0xFE, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xFC, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xF8, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xF8, 0x07, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xF8, 0x0F, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xBC, 0x1F, 0xF0, 0x01, 0x00, 0xC0, 0x07, 0x1E, 0x3F, 0xF0, 0x00, 0x00, 0x80, 0x0F, 0x1F, 0xFC, 0xF8, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0xF8, 0x7D, 0x00, 0x00, 0x00, 0xFF, 0x07, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0xFE, 0x03, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0xF8, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x0C, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char &
+        0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char '
+        0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0xF0, 0x3F, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x80, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x03, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x07, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char (
+        0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0xC0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0x80, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x7F, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0xFC, 0x03, 0x00, 0x80, 0x7F, 0x00, 0x00, 0xF0, 0x3F, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char )
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB8, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xF7, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB8, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char *
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char +
+        0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ,
+        0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char -
+        0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char .
+        0x0E, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char /
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0xFF, 0x01, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0xF0, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0xF0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x07, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x80, 0x07, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0xFF, 0x01, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 0
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 1
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x00, 0xE0, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0xFE, 0x01, 0x00, 0xFC, 0x01, 0x00, 0x00, 0xFF, 0x01, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x3F, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x80, 0x0F, 0x00, 0x80, 0xEF, 0x01, 0x00, 0x80, 0x07, 0x00, 0xC0, 0xE7, 0x01, 0x00, 0xC0, 0x07, 0x00, 0xE0, 0xE3, 0x01, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0xE1, 0x01, 0x00, 0xC0, 0x03, 0x00, 0xF0, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x7C, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x3E, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x1F, 0xE0, 0x01, 0x00, 0xC0, 0x07, 0x80, 0x0F, 0xE0, 0x01, 0x00, 0x80, 0x07, 0xC0, 0x07, 0xE0, 0x01, 0x00, 0x80, 0x0F, 0xF0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x3F, 0xF8, 0x01, 0xE0, 0x01, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xE0, 0x07, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 2
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x78, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0xF0, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xF0, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xF0, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xF0, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xF0, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xF8, 0x00, 0xE0, 0x01, 0x00, 0x80, 0x07, 0xF8, 0x00, 0xE0, 0x01, 0x00, 0x80, 0x0F, 0xFC, 0x00, 0xF0, 0x00, 0x00, 0x80, 0x1F, 0xDE, 0x01, 0xF8, 0x00, 0x00, 0x00, 0xFF, 0xDF, 0x03, 0x7C, 0x00, 0x00, 0x00, 0xFE, 0xCF, 0x07, 0x7E, 0x00, 0x00, 0x00, 0xFC, 0x87, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0x01, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 3
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xEF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xE7, 0x01, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xE1, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x7F, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x80, 0x1F, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xF8, 0x01, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xFE, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x3F, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 4
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x81, 0x3F, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x01, 0x7E, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0xF8, 0x00, 0x00, 0xC0, 0xFF, 0x79, 0x00, 0xF0, 0x00, 0x00, 0xC0, 0x1F, 0x3C, 0x00, 0xF0, 0x01, 0x00, 0xC0, 0x03, 0x1C, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0xF0, 0x01, 0x00, 0xC0, 0x03, 0x3E, 0x00, 0xF0, 0x00, 0x00, 0xC0, 0x03, 0x3C, 0x00, 0xF8, 0x00, 0x00, 0xC0, 0x03, 0x7C, 0x00, 0x7C, 0x00, 0x00, 0xC0, 0x03, 0xF8, 0x01, 0x7F, 0x00, 0x00, 0xC0, 0x03, 0xF0, 0xFF, 0x3F, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 5
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0xFE, 0xC1, 0x03, 0x3F, 0x00, 0x00, 0x00, 0x7F, 0xE0, 0x01, 0x7C, 0x00, 0x00, 0x00, 0x1F, 0xF0, 0x00, 0xF8, 0x00, 0x00, 0x80, 0x0F, 0x78, 0x00, 0xF0, 0x00, 0x00, 0x80, 0x07, 0x78, 0x00, 0xF0, 0x00, 0x00, 0xC0, 0x07, 0x38, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x3C, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x3C, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x3C, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x3C, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x3C, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x07, 0x3C, 0x00, 0xE0, 0x01, 0x00, 0x80, 0x07, 0x78, 0x00, 0xF0, 0x00, 0x00, 0x80, 0x0F, 0xF8, 0x00, 0xF8, 0x00, 0x00, 0x80, 0x3F, 0xF8, 0x01, 0x7C, 0x00, 0x00, 0x00, 0x7F, 0xF0, 0x03, 0x7F, 0x00, 0x00, 0x00, 0x7E, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x7C, 0xC0, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x60, 0x80, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 6
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xF0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xFF, 0x01, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0xFF, 0x01, 0x00, 0xC0, 0x03, 0x00, 0xFC, 0xFF, 0x01, 0x00, 0xC0, 0x03, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0xC0, 0x03, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xF0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xFC, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xFE, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x83, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xC3, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xE3, 0x03, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xF3, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x7B, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 7
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x00, 0xF0, 0x03, 0xFE, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x07, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0xFE, 0x8F, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0xFF, 0xDF, 0x0F, 0x7E, 0x00, 0x00, 0x80, 0x1F, 0xFE, 0x03, 0xF8, 0x00, 0x00, 0x80, 0x0F, 0xFC, 0x01, 0xF0, 0x00, 0x00, 0x80, 0x07, 0xF8, 0x01, 0xF0, 0x00, 0x00, 0xC0, 0x03, 0xF0, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xF0, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xF0, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xF0, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xF0, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xF0, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xF0, 0x00, 0xE0, 0x01, 0x00, 0x80, 0x07, 0xF8, 0x01, 0xF0, 0x00, 0x00, 0x80, 0x0F, 0xF8, 0x01, 0xF0, 0x00, 0x00, 0x80, 0x1F, 0xFE, 0x03, 0xF8, 0x00, 0x00, 0x00, 0xFF, 0xDF, 0x0F, 0x7E, 0x00, 0x00, 0x00, 0xFE, 0x9F, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0xFC, 0x0F, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0xF0, 0x03, 0xFE, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 8
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0x00, 0x03, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x01, 0x1F, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x03, 0x3F, 0x00, 0x00, 0x00, 0x7F, 0xE0, 0x07, 0x7F, 0x00, 0x00, 0x80, 0x1F, 0x80, 0x0F, 0xFC, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x0F, 0xF8, 0x00, 0x00, 0x80, 0x07, 0x00, 0x1F, 0xF0, 0x01, 0x00, 0xC0, 0x07, 0x00, 0x1E, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x1E, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x1E, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x1E, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x1E, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x1E, 0xE0, 0x01, 0x00, 0x80, 0x03, 0x00, 0x0E, 0xF0, 0x00, 0x00, 0x80, 0x07, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x80, 0x07, 0x80, 0x07, 0x78, 0x00, 0x00, 0x00, 0x1F, 0xC0, 0x03, 0x7E, 0x00, 0x00, 0x00, 0x3E, 0xE0, 0xC1, 0x3F, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 9
+        0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char :
+        0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0xE0, 0x41, 0x00, 0x00, 0x80, 0x07, 0x00, 0xE0, 0xF1, 0x00, 0x00, 0x80, 0x07, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x80, 0x07, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ;
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x03, 0x80, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char <
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char =
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x03, 0x80, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x1E, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char >
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xF0, 0xE1, 0x01, 0x00, 0xC0, 0x03, 0x00, 0xFC, 0xE1, 0x01, 0x00, 0xC0, 0x03, 0x00, 0xFE, 0xE1, 0x01, 0x00, 0xC0, 0x03, 0x00, 0xFF, 0xE1, 0x01, 0x00, 0xC0, 0x03, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x07, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x80, 0x0F, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x0F, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ?
+        0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x07, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFE, 0x01, 0xFC, 0x03, 0x00, 0x00, 0x80, 0x3F, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x80, 0x1F, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x3E, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x3C, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x7C, 0x00, 0xFC, 0x03, 0xF8, 0x00, 0x00, 0x3E, 0x80, 0xFF, 0x0F, 0xF0, 0x00, 0x00, 0x1E, 0xE0, 0xFF, 0x3F, 0xF0, 0x01, 0x00, 0x1F, 0xF8, 0xFF, 0x7F, 0xE0, 0x01, 0x00, 0x0F, 0xFC, 0x03, 0xFE, 0xE0, 0x01, 0x80, 0x0F, 0xFE, 0x00, 0xF8, 0xC0, 0x03, 0x80, 0x07, 0x3F, 0x00, 0xF0, 0xC1, 0x03, 0x80, 0x87, 0x0F, 0x00, 0xE0, 0xC1, 0x03, 0x80, 0x87, 0x07, 0x00, 0xE0, 0xC1, 0x03, 0xC0, 0xC3, 0x07, 0x00, 0xE0, 0x81, 0x07, 0xC0, 0xC3, 0x03, 0x00, 0xE0, 0x81, 0x07, 0xC0, 0xC3, 0x03, 0x00, 0xF0, 0x80, 0x07, 0xC0, 0xC3, 0x03, 0x00, 0xF0, 0x80, 0x07, 0xC0, 0xC3, 0x03, 0x00, 0x78, 0x80, 0x07, 0xC0, 0xC3, 0x03, 0x00, 0x3C, 0x80, 0x07, 0xC0, 0x83, 0x07, 0x00, 0x1E, 0x80, 0x07, 0xC0, 0x83, 0x0F, 0x80, 0x7F, 0x80, 0x07, 0xC0, 0x03, 0x3F, 0xE0, 0xFF, 0x80, 0x07, 0xC0, 0x03, 0xFE, 0xFF, 0xFF, 0x81, 0x07, 0x80, 0x07, 0xFE, 0xFF, 0xFF, 0x81, 0x07, 0x80, 0x87, 0xFF, 0xFF, 0xE0, 0xC1, 0x03, 0x80, 0x87, 0xFF, 0x07, 0xE0, 0xC1, 0x03, 0x80, 0x8F, 0x3F, 0x00, 0xE0, 0xC1, 0x03, 0x00, 0x8F, 0x01, 0x00, 0xE0, 0xE0, 0x03, 0x00, 0x1F, 0x00, 0x00, 0xF0, 0xE0, 0x01, 0x00, 0x3E, 0x00, 0x00, 0xF8, 0xE0, 0x01, 0x00, 0x3C, 0x00, 0x00, 0x7C, 0xF0, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x3E, 0xF8, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x1F, 0x78, 0x00, 0x00, 0xF0, 0x03, 0x80, 0x0F, 0x3C, 0x00, 0x00, 0xC0, 0x1F, 0xF0, 0x07, 0x3E, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x01, 0x1F, 0x00, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x1F, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char @
+        0x1F, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x3C, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x1F, 0x3C, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x03, 0x3C, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x3C, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x03, 0x3C, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x1F, 0x3C, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char A
+        0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x07, 0xF0, 0x01, 0xE0, 0x01, 0x00, 0x80, 0x07, 0xF0, 0x03, 0xF0, 0x00, 0x00, 0x80, 0x0F, 0xF8, 0x03, 0xF0, 0x00, 0x00, 0x80, 0x1F, 0xFC, 0x07, 0xF8, 0x00, 0x00, 0x00, 0xFF, 0xBF, 0x0F, 0x7E, 0x00, 0x00, 0x00, 0xFE, 0x3F, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0xFC, 0x0F, 0xFE, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0x03, 0xFC, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char B
+        0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x07, 0xF0, 0x1F, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0xF0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x03, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x07, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x80, 0x0F, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0xFC, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0xF0, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char C
+        0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x80, 0x07, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0xFC, 0x03, 0xF0, 0x1F, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char D
+        0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char E
+        0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char F
+        0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xFC, 0x07, 0xF0, 0x1F, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0xF0, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0xF0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x80, 0x07, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x80, 0x07, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x80, 0x07, 0xC0, 0x03, 0x00, 0xE0, 0x03, 0x80, 0x07, 0xE0, 0x03, 0x00, 0xC0, 0x03, 0x80, 0x07, 0xE0, 0x01, 0x00, 0xC0, 0x07, 0x80, 0x07, 0xE0, 0x01, 0x00, 0xC0, 0x07, 0x80, 0x07, 0xF0, 0x01, 0x00, 0x80, 0x0F, 0x80, 0x07, 0xF0, 0x00, 0x00, 0x80, 0x1F, 0x80, 0x07, 0xF8, 0x00, 0x00, 0x00, 0xFF, 0x80, 0x07, 0x7C, 0x00, 0x00, 0x00, 0xFE, 0x80, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0xF8, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x80, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char G
+        0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char H
+        0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char I
+        0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char J
+        0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xEF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x87, 0x1F, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0xFE, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x7E, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0x3F, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x80, 0x1F, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x7F, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0xFC, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xF8, 0x01, 0x00, 0xC0, 0x01, 0x00, 0x00, 0xF0, 0x01, 0x00, 0xC0, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char K
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char L
+        0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char M
+        0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char N
+        0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x07, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0xF0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xE0, 0x03, 0x00, 0x00, 0xE0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x03, 0x00, 0x00, 0xE0, 0x03, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x07, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0xFC, 0x07, 0xF0, 0x1F, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char O
+        0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x0F, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char P
+        0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x07, 0xF0, 0x1F, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0xF0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC4, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC7, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xCF, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xCF, 0x03, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xFE, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xFE, 0x01, 0x00, 0xC0, 0x07, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x80, 0x0F, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0xFE, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x00, 0xFC, 0x07, 0xF0, 0xFF, 0x03, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0xCF, 0x07, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x87, 0x07, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x01, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Q
+        0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0xFD, 0x00, 0x00, 0x00, 0xC0, 0x07, 0xF0, 0xF9, 0x03, 0x00, 0x00, 0x80, 0x07, 0xF0, 0xF0, 0x07, 0x00, 0x00, 0x80, 0x0F, 0xF8, 0xC0, 0x1F, 0x00, 0x00, 0x80, 0x1F, 0x7C, 0x80, 0x3F, 0x00, 0x00, 0x00, 0xFF, 0x7F, 0x00, 0xFF, 0x00, 0x00, 0x00, 0xFE, 0x3F, 0x00, 0xFC, 0x01, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0xF0, 0x01, 0x00, 0x00, 0xF0, 0x07, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char R
+        0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x03, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x0F, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x7F, 0x00, 0x00, 0x80, 0x0F, 0x7E, 0x00, 0xFC, 0x00, 0x00, 0xC0, 0x07, 0x7C, 0x00, 0xF8, 0x00, 0x00, 0xC0, 0x03, 0xFC, 0x00, 0xF0, 0x01, 0x00, 0xC0, 0x03, 0xF8, 0x00, 0xE0, 0x01, 0x00, 0xE0, 0x01, 0xF8, 0x00, 0xE0, 0x01, 0x00, 0xE0, 0x01, 0xF8, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0xF0, 0x01, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0xF0, 0x01, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0xF0, 0x01, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0xF0, 0x01, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0xE0, 0x03, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0xE0, 0x03, 0xC0, 0x03, 0x00, 0xE0, 0x03, 0xE0, 0x03, 0xC0, 0x03, 0x00, 0xC0, 0x03, 0xC0, 0x07, 0xE0, 0x03, 0x00, 0xC0, 0x07, 0xC0, 0x07, 0xE0, 0x01, 0x00, 0xC0, 0x07, 0xC0, 0x0F, 0xF0, 0x01, 0x00, 0x80, 0x1F, 0x80, 0x0F, 0xF0, 0x00, 0x00, 0x00, 0x7F, 0x80, 0x3F, 0xFC, 0x00, 0x00, 0x00, 0x7E, 0x00, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x7C, 0x00, 0xFE, 0x3F, 0x00, 0x00, 0x00, 0x70, 0x00, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char S
+        0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char T
+        0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char U
+        0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char V
+        0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char W
+        0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xF8, 0x01, 0x00, 0xC0, 0x07, 0x00, 0x00, 0xFE, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x80, 0x3F, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x7E, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x01, 0xF8, 0x03, 0x00, 0x00, 0x00, 0xF0, 0x03, 0xFC, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x9F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x9F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x03, 0xFC, 0x01, 0x00, 0x00, 0x00, 0xFC, 0x01, 0xF8, 0x03, 0x00, 0x00, 0x00, 0x7E, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x80, 0x3F, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x3F, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0xFE, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xF8, 0x01, 0x00, 0xC0, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char X
+        0x1E, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Y
+        0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xFC, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x00, 0xFF, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x80, 0xFF, 0x01, 0x00, 0xC0, 0x03, 0x00, 0xC0, 0xEF, 0x01, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0xE7, 0x01, 0x00, 0xC0, 0x03, 0x00, 0xF8, 0xE1, 0x01, 0x00, 0xC0, 0x03, 0x00, 0xFC, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x7E, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x00, 0x3F, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xC0, 0x0F, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xE0, 0x07, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xF0, 0x03, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0xFC, 0x01, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x7E, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x03, 0x3F, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x83, 0x1F, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0xE3, 0x07, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0xF3, 0x03, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0xFB, 0x01, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0xE0, 0x01, 0x00, 0xC0, 0x07, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Z
+        0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char [
+        0x0E, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char BackSlash
+        0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ]
+        0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ^
+        0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char _
+        0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char `
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x30, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x3C, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x7E, 0xF8, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x7F, 0xF8, 0xF8, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x7C, 0xF0, 0x01, 0x00, 0x00, 0x80, 0x0F, 0x3C, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x07, 0x3C, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x3C, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x3C, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0xF0, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0xF0, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x1E, 0xF8, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x0F, 0x7C, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x0F, 0x3E, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char a
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0xF0, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char b
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0xF0, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xF0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x07, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x80, 0x0F, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char c
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0xF0, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xF0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x07, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x3F, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char d
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x1E, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1E, 0x7C, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x1E, 0xF8, 0x00, 0x00, 0x00, 0x80, 0x07, 0x1E, 0xF0, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x1E, 0xF0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x07, 0x1E, 0xF0, 0x01, 0x00, 0x00, 0x80, 0x0F, 0x1E, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1E, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x1E, 0x7E, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x1F, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x1F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x1F, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char e
+        0x0F, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0x87, 0x07, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x83, 0x07, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x83, 0x07, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x83, 0x07, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x83, 0x07, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char f
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x07, 0x38, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x1F, 0xF8, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0xF0, 0x01, 0x00, 0x00, 0x7F, 0x00, 0x7F, 0xF0, 0x03, 0x00, 0x80, 0x1F, 0x00, 0xFC, 0xE0, 0x03, 0x00, 0x80, 0x0F, 0x00, 0xF8, 0xC0, 0x03, 0x00, 0xC0, 0x07, 0x00, 0xF0, 0x80, 0x07, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x81, 0x07, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x81, 0x07, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x81, 0x07, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x81, 0x07, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x81, 0x07, 0x00, 0xC0, 0x07, 0x00, 0xE0, 0x81, 0x07, 0x00, 0x80, 0x07, 0x00, 0xF0, 0xC0, 0x07, 0x00, 0x80, 0x0F, 0x00, 0xF8, 0xC0, 0x03, 0x00, 0x00, 0x1F, 0x00, 0x7C, 0xE0, 0x03, 0x00, 0x00, 0x7E, 0x00, 0x3F, 0xF8, 0x01, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char g
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char h
+        0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x83, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0x83, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0x83, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0x83, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char i
+        0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0xC0, 0x83, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0xC0, 0x83, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0xC0, 0x83, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0xC0, 0x83, 0xFF, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char j
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x7E, 0xF0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x80, 0x03, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char k
+        0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char l
+        0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char m
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char n
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0xF0, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0xF0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x07, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char o
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0xFC, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0xF0, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xF0, 0x01, 0x00, 0x00, 0xC0, 0x07, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char p
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0xF8, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0xF0, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xF0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x07, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char q
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char r
+        0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x03, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x07, 0x7F, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0xFC, 0x00, 0x00, 0x00, 0x80, 0x8F, 0x0F, 0xF8, 0x00, 0x00, 0x00, 0xC0, 0x87, 0x0F, 0xF0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x1F, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x1F, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x1F, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x3E, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x3E, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x03, 0x3E, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0x07, 0x7C, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x0F, 0x7C, 0xF0, 0x00, 0x00, 0x00, 0x80, 0x3F, 0xFC, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xF8, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x1E, 0xF8, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x18, 0xF0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char s
+        0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char t
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char u
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char v
+        0x21, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x1F, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char w
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x80, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0xC0, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x80, 0x0F, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x80, 0x1F, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xE3, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xF7, 0x03, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xE3, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xC1, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x80, 0x03, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char x
+        0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x80, 0x01, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x80, 0x07, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x80, 0x07, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x80, 0x07, 0x00, 0x00, 0xF8, 0x7F, 0x00, 0x80, 0x07, 0x00, 0x00, 0xE0, 0xFF, 0x03, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xF8, 0x7F, 0xFC, 0x03, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char y
+        0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x80, 0x07, 0x80, 0xFF, 0x01, 0x00, 0x00, 0x80, 0x07, 0xC0, 0xE7, 0x01, 0x00, 0x00, 0x80, 0x07, 0xF0, 0xE3, 0x01, 0x00, 0x00, 0x80, 0x07, 0xF8, 0xE1, 0x01, 0x00, 0x00, 0x80, 0x07, 0xFC, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x07, 0x7E, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x07, 0x1F, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x87, 0x0F, 0xE0, 0x01, 0x00, 0x00, 0x80, 0xE7, 0x07, 0xE0, 0x01, 0x00, 0x00, 0x80, 0xF7, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x80, 0xFF, 0x01, 0xE0, 0x01, 0x00, 0x00, 0x80, 0xFF, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x3F, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x1F, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x0F, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x80, 0x07, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char z
+        0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0xE7, 0xFF, 0x7F, 0x00, 0x00, 0xFF, 0xFF, 0xC7, 0xFF, 0xFF, 0x01, 0x80, 0xFF, 0xFF, 0x81, 0xFF, 0xFF, 0x03, 0x80, 0xFF, 0x7F, 0x00, 0xFE, 0xFF, 0x03, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char {
+        0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char |
+        0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x80, 0xFF, 0x7F, 0x00, 0xFE, 0xFF, 0x03, 0x80, 0xFF, 0xFF, 0x81, 0xFF, 0xFF, 0x03, 0x00, 0xFF, 0xFF, 0xE3, 0xFF, 0xFF, 0x01, 0x00, 0xFC, 0xFF, 0xE7, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char }
+        0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ~
+        0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char €
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ‚
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ƒ
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char „
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char …
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char †
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ‡
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ˆ
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ‰
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Å 
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ‹
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Œ
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Ž
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 
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+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ’
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char “
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ”
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+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char –
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char —
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ˜
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+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Å¡
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ›
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char œ
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ž
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Ÿ
+        0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char  
+        0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0xFE, 0xFF, 0x03, 0x00, 0x80, 0x87, 0xFF, 0xFF, 0xFF, 0x03, 0x00, 0x80, 0x87, 0xFF, 0xFF, 0xFF, 0x03, 0x00, 0x80, 0x07, 0x00, 0xFE, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ¡
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x3F, 0x00, 0x02, 0x00, 0x00, 0xFF, 0x00, 0x7F, 0xE0, 0x03, 0x00, 0x00, 0x1F, 0x00, 0xFC, 0xFC, 0x03, 0x00, 0x80, 0x0F, 0x00, 0xF8, 0xFF, 0x01, 0x00, 0x80, 0x07, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0xC0, 0x07, 0x00, 0xFF, 0x03, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0xFF, 0x01, 0x00, 0x00, 0xC0, 0x03, 0xFE, 0xE7, 0x01, 0x00, 0x00, 0xC0, 0xC3, 0xFF, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0xFF, 0x1F, 0xE0, 0x01, 0x00, 0x00, 0xC0, 0xFF, 0x01, 0xE0, 0x01, 0x00, 0x00, 0xF0, 0x3F, 0x00, 0xF0, 0x01, 0x00, 0x00, 0xFF, 0x07, 0x00, 0xF0, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0xF8, 0x00, 0x00, 0xC0, 0x0F, 0x7F, 0x00, 0x7E, 0x00, 0x00, 0x80, 0x00, 0x7F, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ¢
+        0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x70, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xF8, 0x01, 0x00, 0x00, 0xF0, 0xC7, 0x03, 0xF8, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x03, 0xFE, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x03, 0xFF, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x1F, 0xF8, 0xFF, 0x7B, 0x00, 0x00, 0x80, 0x0F, 0xC0, 0xFF, 0x78, 0x00, 0x00, 0x80, 0x07, 0xC0, 0x3F, 0x78, 0x00, 0x00, 0xC0, 0x07, 0xC0, 0x03, 0x78, 0x00, 0x00, 0xC0, 0x03, 0xC0, 0x03, 0x78, 0x00, 0x00, 0xC0, 0x03, 0xC0, 0x03, 0x78, 0x00, 0x00, 0xC0, 0x03, 0xC0, 0x03, 0xF0, 0x00, 0x00, 0xC0, 0x03, 0xC0, 0x03, 0xF0, 0x00, 0x00, 0xC0, 0x03, 0xC0, 0x03, 0xF0, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x80, 0x07, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x80, 0x0F, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x3F, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0xFE, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char £
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0xC0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0xE1, 0xC3, 0x01, 0x00, 0x00, 0x00, 0xE0, 0xFB, 0xEF, 0x03, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0F, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x80, 0x07, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0F, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xE0, 0xFB, 0xEF, 0x03, 0x00, 0x00, 0x00, 0xC0, 0xE1, 0xC3, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x01, 0xC0, 0x01, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ¤
+        0x1A, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x80, 0x87, 0x07, 0x00, 0x00, 0xC0, 0x07, 0x80, 0x87, 0x07, 0x00, 0x00, 0xC0, 0x1F, 0x80, 0x87, 0x07, 0x00, 0x00, 0x80, 0x7F, 0x80, 0x87, 0x07, 0x00, 0x00, 0x00, 0xFE, 0x80, 0x87, 0x07, 0x00, 0x00, 0x00, 0xFC, 0x83, 0x87, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x8F, 0x87, 0x07, 0x00, 0x00, 0x00, 0xC0, 0xBF, 0x87, 0x07, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x87, 0x07, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x87, 0x07, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFE, 0x87, 0x07, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x87, 0x07, 0x00, 0x00, 0x00, 0xC0, 0xBF, 0x87, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x8F, 0x87, 0x07, 0x00, 0x00, 0x00, 0xFC, 0x83, 0x87, 0x07, 0x00, 0x00, 0x00, 0xFE, 0x80, 0x87, 0x07, 0x00, 0x00, 0x80, 0x7F, 0x80, 0x87, 0x07, 0x00, 0x00, 0xC0, 0x1F, 0x80, 0x87, 0x07, 0x00, 0x00, 0xC0, 0x07, 0x80, 0x87, 0x07, 0x00, 0x00, 0xC0, 0x01, 0x80, 0x87, 0x07, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ¥
+        0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0x07, 0xC0, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0x07, 0xC0, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0x07, 0xC0, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ¦
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x0C, 0x00, 0x00, 0xF8, 0xE0, 0x7F, 0x00, 0x3C, 0x00, 0x00, 0xFE, 0xF3, 0xFF, 0x00, 0x7E, 0x00, 0x00, 0xFF, 0x77, 0xF8, 0x01, 0xFE, 0x00, 0x80, 0xFF, 0x3F, 0xE0, 0x01, 0xFC, 0x01, 0x80, 0x8F, 0x1F, 0xE0, 0x03, 0xF0, 0x01, 0xC0, 0x07, 0x1F, 0xC0, 0x07, 0xE0, 0x03, 0xC0, 0x07, 0x3E, 0x80, 0x07, 0xC0, 0x03, 0xC0, 0x03, 0x7C, 0x80, 0x0F, 0xC0, 0x03, 0xC0, 0x03, 0x7C, 0x00, 0x0F, 0xC0, 0x03, 0xC0, 0x03, 0xF8, 0x00, 0x1F, 0xC0, 0x03, 0xC0, 0x03, 0xF0, 0x00, 0x3E, 0xC0, 0x03, 0xC0, 0x03, 0xF0, 0x01, 0x3E, 0xC0, 0x03, 0xC0, 0x07, 0xE0, 0x01, 0x7C, 0xE0, 0x03, 0x80, 0x07, 0xE0, 0x03, 0xF8, 0xE0, 0x01, 0x80, 0x1F, 0xC0, 0x07, 0xFC, 0xF1, 0x01, 0x00, 0x7F, 0xC0, 0x0F, 0xFE, 0xFF, 0x00, 0x00, 0x7E, 0x80, 0x1F, 0xEF, 0xFF, 0x00, 0x00, 0x3C, 0x00, 0xFF, 0xC7, 0x7F, 0x00, 0x00, 0x30, 0x00, 0xFE, 0x07, 0x1F, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char §
+        0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ¨
+        0x23, 0x00, 0x00, 0xF8, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x07, 0xF8, 0x03, 0x00, 0x00, 0x00, 0xF8, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x07, 0xF8, 0x07, 0x38, 0x00, 0x00, 0x80, 0x03, 0xFE, 0x3F, 0x70, 0x00, 0x00, 0x80, 0x83, 0xFF, 0x7F, 0x70, 0x00, 0x00, 0xC0, 0xC1, 0x0F, 0xF8, 0xE0, 0x00, 0x00, 0xC0, 0xE1, 0x03, 0xE0, 0xE1, 0x00, 0x00, 0xE0, 0xE1, 0x00, 0xC0, 0xE1, 0x01, 0x00, 0xE0, 0xF0, 0x00, 0xC0, 0xC3, 0x01, 0x00, 0xE0, 0x70, 0x00, 0x80, 0xC3, 0x01, 0x00, 0xE0, 0x70, 0x00, 0x80, 0xC3, 0x01, 0x00, 0xE0, 0x70, 0x00, 0x80, 0xC3, 0x01, 0x00, 0xE0, 0x70, 0x00, 0x80, 0xC3, 0x01, 0x00, 0xE0, 0x70, 0x00, 0xC0, 0xC3, 0x01, 0x00, 0xE0, 0xF0, 0x00, 0xC0, 0xC1, 0x01, 0x00, 0xE0, 0xE1, 0x01, 0xE0, 0xE1, 0x01, 0x00, 0xC0, 0xE1, 0x03, 0xF8, 0xE0, 0x00, 0x00, 0xC0, 0xC1, 0x07, 0xFC, 0xE0, 0x00, 0x00, 0x80, 0x83, 0x07, 0x3C, 0xF0, 0x00, 0x00, 0x80, 0x03, 0x02, 0x18, 0x70, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0xF8, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x07, 0xF8, 0x03, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ©
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x87, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x80, 0xCF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x80, 0xCF, 0xF1, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xC3, 0xE1, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xC1, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xE1, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xE1, 0x60, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xE1, 0x70, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xE3, 0x78, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ª
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xE7, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xC3, 0x1F, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x18, 0x78, 0x00, 0x00, 0x00, 0x00, 0x06, 0x3C, 0x60, 0x00, 0x00, 0x00, 0x00, 0x02, 0x7E, 0x40, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xE7, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xC3, 0x1F, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char «
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ¬
+        0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ­
+        0x23, 0x00, 0x00, 0xF8, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x07, 0xF8, 0x03, 0x00, 0x00, 0x00, 0xF8, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x38, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x70, 0x00, 0x00, 0x80, 0xF3, 0xFF, 0xFF, 0x73, 0x00, 0x00, 0xC0, 0xF1, 0xFF, 0xFF, 0xE3, 0x00, 0x00, 0xC0, 0xF1, 0xFF, 0xFF, 0xE3, 0x00, 0x00, 0xE0, 0x71, 0xC0, 0x01, 0xE0, 0x01, 0x00, 0xE0, 0x70, 0xC0, 0x01, 0xC0, 0x01, 0x00, 0xE0, 0x70, 0xC0, 0x01, 0xC0, 0x01, 0x00, 0xE0, 0x70, 0xC0, 0x03, 0xC0, 0x01, 0x00, 0xE0, 0x70, 0xC0, 0x03, 0xC0, 0x01, 0x00, 0xE0, 0x70, 0xC0, 0x07, 0xC0, 0x01, 0x00, 0xE0, 0x70, 0xC0, 0x1F, 0xC0, 0x01, 0x00, 0xE0, 0xF0, 0xE0, 0x3D, 0xC0, 0x01, 0x00, 0xE0, 0xE1, 0xF1, 0xF8, 0xE0, 0x01, 0x00, 0xC0, 0xE1, 0xFF, 0xF0, 0xE3, 0x00, 0x00, 0xC0, 0xC1, 0x7F, 0xC0, 0xE3, 0x00, 0x00, 0x80, 0x03, 0x1F, 0x80, 0xF3, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x72, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0xF8, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x07, 0xF8, 0x03, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ®
+        0x1B, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ¯
+        0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC7, 0x03, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x83, 0x07, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x07, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x07, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x07, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x83, 0x07, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC7, 0x03, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00   // Code for char °
+        };
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ILI9341/Arial_9.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,106 @@
+
+
+//GLCD FontName : Arial11x11
+//GLCD FontSize : 11 x 11
+
+const unsigned char Arial_9[] = {
+        // Length,horz,vert,byte/vert
+        23,11,11,2,
+        0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char  
+        0x02, 0x00, 0x00, 0x7F, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char !
+        0x03, 0x07, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char "
+        0x07, 0x20, 0x00, 0xA4, 0x01, 0x7C, 0x00, 0xA7, 0x01, 0x7C, 0x00, 0x27, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char #
+        0x06, 0x00, 0x00, 0xCE, 0x00, 0x11, 0x01, 0xFF, 0x03, 0x11, 0x01, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char $
+        0x0A, 0x00, 0x00, 0x0E, 0x00, 0x11, 0x00, 0x11, 0x01, 0xCE, 0x00, 0x38, 0x00, 0xE6, 0x00, 0x11, 0x01, 0x10, 0x01, 0xE0, 0x00, 0x00, 0x00,  // Code for char %
+        0x08, 0x00, 0x00, 0xE0, 0x00, 0x1E, 0x01, 0x11, 0x01, 0x29, 0x01, 0xC6, 0x00, 0xA0, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char &
+        0x02, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char '
+        0x04, 0x00, 0x00, 0xF8, 0x00, 0x06, 0x03, 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char (
+        0x04, 0x00, 0x00, 0x01, 0x04, 0x06, 0x03, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char )
+        0x05, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x38, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char *
+        0x06, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, 0xF8, 0x00, 0x20, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char +
+        0x02, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ,
+        0x03, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char -
+        0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char .
+        0x03, 0x80, 0x01, 0x7C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char /
+        0x06, 0x00, 0x00, 0xFE, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 0
+        0x04, 0x00, 0x00, 0x04, 0x00, 0x02, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 1
+        0x06, 0x00, 0x00, 0x02, 0x01, 0x81, 0x01, 0x41, 0x01, 0x31, 0x01, 0x0E, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 2
+        0x06, 0x00, 0x00, 0x82, 0x00, 0x01, 0x01, 0x11, 0x01, 0x11, 0x01, 0xEE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 3
+        0x06, 0x00, 0x00, 0x60, 0x00, 0x58, 0x00, 0x46, 0x00, 0xFF, 0x01, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 4
+        0x06, 0x00, 0x00, 0x9C, 0x00, 0x0B, 0x01, 0x09, 0x01, 0x09, 0x01, 0xF1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 5
+        0x06, 0x00, 0x00, 0xFE, 0x00, 0x11, 0x01, 0x09, 0x01, 0x09, 0x01, 0xF2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 6
+        0x06, 0x00, 0x00, 0x01, 0x00, 0xC1, 0x01, 0x39, 0x00, 0x07, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 7
+        0x06, 0x00, 0x00, 0xEE, 0x00, 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0xEE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 8
+        0x06, 0x00, 0x00, 0x9E, 0x00, 0x21, 0x01, 0x21, 0x01, 0x11, 0x01, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 9
+        0x02, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char :
+        0x02, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ;
+        0x06, 0x00, 0x00, 0x10, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char <
+        0x06, 0x48, 0x00, 0x48, 0x00, 0x48, 0x00, 0x48, 0x00, 0x48, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char =
+        0x06, 0x00, 0x00, 0x44, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char >
+        0x06, 0x00, 0x00, 0x06, 0x00, 0x01, 0x00, 0x61, 0x01, 0x11, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ?
+        0x0B, 0x00, 0x00, 0xF0, 0x01, 0x18, 0x02, 0xCC, 0x04, 0x24, 0x05, 0x14, 0x05, 0xF4, 0x05, 0x04, 0x05, 0x8C, 0x05, 0xF8, 0x04, 0x00, 0x02,  // Code for char @
+        0x08, 0x00, 0x00, 0x80, 0x01, 0x70, 0x00, 0x2E, 0x00, 0x21, 0x00, 0x2E, 0x00, 0x70, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char A
+        0x07, 0x00, 0x00, 0xFF, 0x01, 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char B
+        0x08, 0x00, 0x00, 0x7C, 0x00, 0x82, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x82, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char C
+        0x08, 0x00, 0x00, 0xFF, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x82, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char D
+        0x07, 0x00, 0x00, 0xFF, 0x01, 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char E
+        0x06, 0x00, 0x00, 0xFF, 0x01, 0x11, 0x00, 0x11, 0x00, 0x11, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char F
+        0x08, 0x00, 0x00, 0x7C, 0x00, 0x82, 0x00, 0x01, 0x01, 0x01, 0x01, 0x11, 0x01, 0x92, 0x00, 0x74, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char G
+        0x08, 0x00, 0x00, 0xFF, 0x01, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char H
+        0x02, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char I
+        0x06, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char J
+        0x08, 0x00, 0x00, 0xFF, 0x01, 0x20, 0x00, 0x10, 0x00, 0x28, 0x00, 0x44, 0x00, 0x82, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char K
+        0x07, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char L
+        0x08, 0x00, 0x00, 0xFF, 0x01, 0x06, 0x00, 0x78, 0x00, 0x80, 0x01, 0x78, 0x00, 0x06, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char M
+        0x08, 0x00, 0x00, 0xFF, 0x01, 0x02, 0x00, 0x0C, 0x00, 0x10, 0x00, 0x60, 0x00, 0x80, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char N
+        0x08, 0x00, 0x00, 0x7C, 0x00, 0x82, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x82, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char O
+        0x07, 0x00, 0x00, 0xFF, 0x01, 0x11, 0x00, 0x11, 0x00, 0x11, 0x00, 0x11, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char P
+        0x08, 0x00, 0x00, 0x7C, 0x00, 0x82, 0x00, 0x01, 0x01, 0x41, 0x01, 0x41, 0x01, 0x82, 0x00, 0x7C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Q
+        0x08, 0x00, 0x00, 0xFF, 0x01, 0x11, 0x00, 0x11, 0x00, 0x11, 0x00, 0x31, 0x00, 0xD1, 0x00, 0x0E, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char R
+        0x07, 0x00, 0x00, 0xCE, 0x00, 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0xE6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char S
+        0x07, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0xFF, 0x01, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char T
+        0x08, 0x00, 0x00, 0x7F, 0x00, 0x80, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x80, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char U
+        0x08, 0x00, 0x00, 0x03, 0x00, 0x1C, 0x00, 0x60, 0x00, 0x80, 0x01, 0x60, 0x00, 0x1C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char V
+        0x0B, 0x07, 0x00, 0x78, 0x00, 0x80, 0x01, 0x70, 0x00, 0x0E, 0x00, 0x01, 0x00, 0x0E, 0x00, 0x70, 0x00, 0x80, 0x01, 0x7C, 0x00, 0x03, 0x00,  // Code for char W
+        0x08, 0x00, 0x00, 0x01, 0x01, 0xC6, 0x00, 0x28, 0x00, 0x10, 0x00, 0x28, 0x00, 0xC6, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char X
+        0x08, 0x00, 0x00, 0x01, 0x00, 0x06, 0x00, 0x08, 0x00, 0xF0, 0x01, 0x08, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Y
+        0x08, 0x00, 0x00, 0x00, 0x01, 0x81, 0x01, 0x61, 0x01, 0x11, 0x01, 0x0D, 0x01, 0x03, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Z
+        0x03, 0x00, 0x00, 0xFF, 0x07, 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char [
+        0x03, 0x03, 0x00, 0x7C, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char BackSlash
+        0x02, 0x01, 0x04, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ]
+        0x05, 0x10, 0x00, 0x0E, 0x00, 0x01, 0x00, 0x0E, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ^
+        0x07, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char _
+        0x03, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char `
+        0x06, 0x00, 0x00, 0xC8, 0x00, 0x24, 0x01, 0x24, 0x01, 0xA4, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char a
+        0x06, 0x00, 0x00, 0xFF, 0x01, 0x88, 0x00, 0x04, 0x01, 0x04, 0x01, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char b
+        0x06, 0x00, 0x00, 0xF8, 0x00, 0x04, 0x01, 0x04, 0x01, 0x04, 0x01, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char c
+        0x06, 0x00, 0x00, 0xF8, 0x00, 0x04, 0x01, 0x04, 0x01, 0x08, 0x01, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char d
+        0x06, 0x00, 0x00, 0xF8, 0x00, 0x24, 0x01, 0x24, 0x01, 0x24, 0x01, 0xB8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char e
+        0x05, 0x00, 0x00, 0x04, 0x00, 0xFE, 0x01, 0x05, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char f
+        0x06, 0x00, 0x00, 0xF8, 0x04, 0x04, 0x05, 0x04, 0x05, 0x88, 0x04, 0xFC, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char g
+        0x06, 0x00, 0x00, 0xFF, 0x01, 0x08, 0x00, 0x04, 0x00, 0x04, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char h
+        0x02, 0x00, 0x00, 0xFD, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char i
+        0x03, 0x00, 0x00, 0x00, 0x04, 0xFD, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char j
+        0x06, 0x00, 0x00, 0xFF, 0x01, 0x20, 0x00, 0x30, 0x00, 0xC8, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char k
+        0x02, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char l
+        0x0A, 0x00, 0x00, 0xFC, 0x01, 0x08, 0x00, 0x04, 0x00, 0x04, 0x00, 0xF8, 0x01, 0x08, 0x00, 0x04, 0x00, 0x04, 0x00, 0xF8, 0x01, 0x00, 0x00,  // Code for char m
+        0x06, 0x00, 0x00, 0xFC, 0x01, 0x08, 0x00, 0x04, 0x00, 0x04, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char n
+        0x06, 0x00, 0x00, 0xF8, 0x00, 0x04, 0x01, 0x04, 0x01, 0x04, 0x01, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char o
+        0x06, 0x00, 0x00, 0xFC, 0x07, 0x88, 0x00, 0x04, 0x01, 0x04, 0x01, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char p
+        0x06, 0x00, 0x00, 0xF8, 0x00, 0x04, 0x01, 0x04, 0x01, 0x88, 0x00, 0xFC, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char q
+        0x04, 0x00, 0x00, 0xFC, 0x01, 0x08, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char r
+        0x06, 0x00, 0x00, 0x98, 0x00, 0x24, 0x01, 0x24, 0x01, 0x24, 0x01, 0xC8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char s
+        0x04, 0x00, 0x00, 0x04, 0x00, 0xFF, 0x01, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char t
+        0x06, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char u
+        0x06, 0x00, 0x00, 0x0C, 0x00, 0x70, 0x00, 0x80, 0x01, 0x70, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char v
+        0x0A, 0x00, 0x00, 0x0C, 0x00, 0x70, 0x00, 0x80, 0x01, 0x70, 0x00, 0x0C, 0x00, 0x70, 0x00, 0x80, 0x01, 0x70, 0x00, 0x0C, 0x00, 0x00, 0x00,  // Code for char w
+        0x06, 0x00, 0x00, 0x04, 0x01, 0xD8, 0x00, 0x20, 0x00, 0xD8, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char x
+        0x06, 0x00, 0x00, 0x0C, 0x00, 0x70, 0x04, 0x80, 0x03, 0x70, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char y
+        0x06, 0x00, 0x00, 0x04, 0x01, 0xC4, 0x01, 0x24, 0x01, 0x1C, 0x01, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char z
+        0x04, 0x00, 0x00, 0x20, 0x00, 0xDE, 0x03, 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char {
+        0x02, 0x00, 0x00, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char |
+        0x04, 0x00, 0x00, 0x01, 0x04, 0xDE, 0x03, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char }
+        0x07, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ~
+        0x03, 0xFE, 0x03, 0x02, 0x02, 0xFE, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00   // Code for char 
+        };
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ILI9341/GraphicsDisplay.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,177 @@
+/* mbed GraphicsDisplay Display Library Base Class
+ * Copyright (c) 2007-2009 sford
+ * Released under the MIT License: http://mbed.org/license/mit
+ */
+ 
+#include "GraphicsDisplay.h"
+
+const unsigned char FONT8x8[97][8] = {
+0x08,0x08,0x08,0x00,0x00,0x00,0x00,0x00, // columns, rows, num_bytes_per_char
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // space 0x20
+0x30,0x78,0x78,0x30,0x30,0x00,0x30,0x00, // !
+0x6C,0x6C,0x6C,0x00,0x00,0x00,0x00,0x00, // "
+0x6C,0x6C,0xFE,0x6C,0xFE,0x6C,0x6C,0x00, // #
+0x18,0x3E,0x60,0x3C,0x06,0x7C,0x18,0x00, // $
+0x00,0x63,0x66,0x0C,0x18,0x33,0x63,0x00, // %
+0x1C,0x36,0x1C,0x3B,0x6E,0x66,0x3B,0x00, // &
+0x30,0x30,0x60,0x00,0x00,0x00,0x00,0x00, // '
+0x0C,0x18,0x30,0x30,0x30,0x18,0x0C,0x00, // (
+0x30,0x18,0x0C,0x0C,0x0C,0x18,0x30,0x00, // )
+0x00,0x66,0x3C,0xFF,0x3C,0x66,0x00,0x00, // *
+0x00,0x30,0x30,0xFC,0x30,0x30,0x00,0x00, // +
+0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x30, // ,
+0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0x00, // -
+0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00, // .
+0x03,0x06,0x0C,0x18,0x30,0x60,0x40,0x00, // / (forward slash)
+0x3E,0x63,0x63,0x6B,0x63,0x63,0x3E,0x00, // 0 0x30
+0x18,0x38,0x58,0x18,0x18,0x18,0x7E,0x00, // 1
+0x3C,0x66,0x06,0x1C,0x30,0x66,0x7E,0x00, // 2
+0x3C,0x66,0x06,0x1C,0x06,0x66,0x3C,0x00, // 3
+0x0E,0x1E,0x36,0x66,0x7F,0x06,0x0F,0x00, // 4
+0x7E,0x60,0x7C,0x06,0x06,0x66,0x3C,0x00, // 5
+0x1C,0x30,0x60,0x7C,0x66,0x66,0x3C,0x00, // 6
+0x7E,0x66,0x06,0x0C,0x18,0x18,0x18,0x00, // 7
+0x3C,0x66,0x66,0x3C,0x66,0x66,0x3C,0x00, // 8
+0x3C,0x66,0x66,0x3E,0x06,0x0C,0x38,0x00, // 9
+0x00,0x18,0x18,0x00,0x00,0x18,0x18,0x00, // :
+0x00,0x18,0x18,0x00,0x00,0x18,0x18,0x30, // ;
+0x0C,0x18,0x30,0x60,0x30,0x18,0x0C,0x00, // <
+0x00,0x00,0x7E,0x00,0x00,0x7E,0x00,0x00, // =
+0x30,0x18,0x0C,0x06,0x0C,0x18,0x30,0x00, // >
+0x3C,0x66,0x06,0x0C,0x18,0x00,0x18,0x00, // ?
+0x3E,0x63,0x6F,0x69,0x6F,0x60,0x3E,0x00, // @ 0x40
+0x18,0x3C,0x66,0x66,0x7E,0x66,0x66,0x00, // A
+0x7E,0x33,0x33,0x3E,0x33,0x33,0x7E,0x00, // B
+0x1E,0x33,0x60,0x60,0x60,0x33,0x1E,0x00, // C
+0x7C,0x36,0x33,0x33,0x33,0x36,0x7C,0x00, // D
+0x7F,0x31,0x34,0x3C,0x34,0x31,0x7F,0x00, // E
+0x7F,0x31,0x34,0x3C,0x34,0x30,0x78,0x00, // F
+0x1E,0x33,0x60,0x60,0x67,0x33,0x1F,0x00, // G
+0x66,0x66,0x66,0x7E,0x66,0x66,0x66,0x00, // H
+0x3C,0x18,0x18,0x18,0x18,0x18,0x3C,0x00, // I
+0x0F,0x06,0x06,0x06,0x66,0x66,0x3C,0x00, // J
+0x73,0x33,0x36,0x3C,0x36,0x33,0x73,0x00, // K
+0x78,0x30,0x30,0x30,0x31,0x33,0x7F,0x00, // L
+0x63,0x77,0x7F,0x7F,0x6B,0x63,0x63,0x00, // M
+0x63,0x73,0x7B,0x6F,0x67,0x63,0x63,0x00, // N
+0x3E,0x63,0x63,0x63,0x63,0x63,0x3E,0x00, // O
+0x7E,0x33,0x33,0x3E,0x30,0x30,0x78,0x00, // P 0x50
+0x3C,0x66,0x66,0x66,0x6E,0x3C,0x0E,0x00, // Q
+0x7E,0x33,0x33,0x3E,0x36,0x33,0x73,0x00, // R
+0x3C,0x66,0x30,0x18,0x0C,0x66,0x3C,0x00, // S
+0x7E,0x5A,0x18,0x18,0x18,0x18,0x3C,0x00, // T
+0x66,0x66,0x66,0x66,0x66,0x66,0x7E,0x00, // U
+0x66,0x66,0x66,0x66,0x66,0x3C,0x18,0x00, // V
+0x63,0x63,0x63,0x6B,0x7F,0x77,0x63,0x00, // W
+0x63,0x63,0x36,0x1C,0x1C,0x36,0x63,0x00, // X
+0x66,0x66,0x66,0x3C,0x18,0x18,0x3C,0x00, // Y
+0x7F,0x63,0x46,0x0C,0x19,0x33,0x7F,0x00, // Z
+0x3C,0x30,0x30,0x30,0x30,0x30,0x3C,0x00, // [
+0x60,0x30,0x18,0x0C,0x06,0x03,0x01,0x00, // \ (back slash)
+0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3C,0x00, // ]
+0x08,0x1C,0x36,0x63,0x00,0x00,0x00,0x00, // ^
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF, // _
+0x18,0x18,0x0C,0x00,0x00,0x00,0x00,0x00, // ` 0x60
+0x00,0x00,0x3C,0x06,0x3E,0x66,0x3B,0x00, // a
+0x70,0x30,0x3E,0x33,0x33,0x33,0x6E,0x00, // b
+0x00,0x00,0x3C,0x66,0x60,0x66,0x3C,0x00, // c
+0x0E,0x06,0x3E,0x66,0x66,0x66,0x3B,0x00, // d
+0x00,0x00,0x3C,0x66,0x7E,0x60,0x3C,0x00, // e
+0x1C,0x36,0x30,0x78,0x30,0x30,0x78,0x00, // f
+0x00,0x00,0x3B,0x66,0x66,0x3E,0x06,0x7C, // g
+0x70,0x30,0x36,0x3B,0x33,0x33,0x73,0x00, // h
+0x18,0x00,0x38,0x18,0x18,0x18,0x3C,0x00, // i
+0x06,0x00,0x06,0x06,0x06,0x66,0x66,0x3C, // j
+0x70,0x30,0x33,0x36,0x3C,0x36,0x73,0x00, // k
+0x38,0x18,0x18,0x18,0x18,0x18,0x3C,0x00, // l
+0x00,0x00,0x66,0x7F,0x7F,0x6B,0x63,0x00, // m
+0x00,0x00,0x7C,0x66,0x66,0x66,0x66,0x00, // n
+0x00,0x00,0x3C,0x66,0x66,0x66,0x3C,0x00, // o
+0x00,0x00,0x6E,0x33,0x33,0x3E,0x30,0x78, // p
+0x00,0x00,0x3B,0x66,0x66,0x3E,0x06,0x0F, // q
+0x00,0x00,0x6E,0x3B,0x33,0x30,0x78,0x00, // r
+0x00,0x00,0x3E,0x60,0x3C,0x06,0x7C,0x00, // s
+0x08,0x18,0x3E,0x18,0x18,0x1A,0x0C,0x00, // t
+0x00,0x00,0x66,0x66,0x66,0x66,0x3B,0x00, // u
+0x00,0x00,0x66,0x66,0x66,0x3C,0x18,0x00, // v
+0x00,0x00,0x63,0x6B,0x7F,0x7F,0x36,0x00, // w
+0x00,0x00,0x63,0x36,0x1C,0x36,0x63,0x00, // x
+0x00,0x00,0x66,0x66,0x66,0x3E,0x06,0x7C, // y
+0x00,0x00,0x7E,0x4C,0x18,0x32,0x7E,0x00, // z
+0x0E,0x18,0x18,0x70,0x18,0x18,0x0E,0x00, // {
+0x0C,0x0C,0x0C,0x00,0x0C,0x0C,0x0C,0x00, // |
+0x70,0x18,0x18,0x0E,0x18,0x18,0x70,0x00, // }
+0x3B,0x6E,0x00,0x00,0x00,0x00,0x00,0x00, // ~
+0x1C,0x36,0x36,0x1C,0x00,0x00,0x00,0x00}; // DEL
+    
+GraphicsDisplay::GraphicsDisplay(const char *name):TextDisplay(name) {
+    foreground(0xFFFF);
+    background(0x0000);
+}
+    
+void GraphicsDisplay::character(int column, int row, int value) { 
+    blitbit(column * 8, row * 8, 8, 8, (char*)&(FONT8x8[value - 0x1F][0]));
+}
+
+void GraphicsDisplay::window(unsigned int x,unsigned  int y,unsigned  int w,unsigned  int h) {
+    // current pixel location
+    _x = x;
+    _y = y;
+    // window settings
+    _x1 = x;
+    _x2 = x + w - 1;
+    _y1 = y;
+    _y2 = y + h - 1;
+}
+    
+void GraphicsDisplay::putp(int colour) {
+    // put pixel at current pixel location
+    pixel(_x, _y, colour);
+    // update pixel location based on window settings
+    _x++;
+    if(_x > _x2) {
+        _x = _x1;
+        _y++;
+        if(_y > _y2) {
+            _y = _y1;
+        }
+    }
+}
+
+void GraphicsDisplay::fill(int x, int y, int w, int h, int colour) { 
+    window(x, y, w, h);
+    for(int i=0; i<w*h; i++) {
+        putp(colour);
+    }
+}
+    
+void GraphicsDisplay::cls() {
+    fill(0, 0, width(), height(), _background);
+}
+    
+void GraphicsDisplay::blit(int x, int y, int w, int h, const int *colour) { 
+    window(x, y, w, h);
+    for(int i=0; i<w*h; i++) {
+        putp(colour[i]);
+    }
+}
+    
+void GraphicsDisplay::blitbit(int x, int y, int w, int h, const char* colour) {
+    window(x, y, w, h);
+    for(int i = 0; i < w*h; i++) {
+        char byte = colour[i >> 3];
+        int offset = i & 0x7;
+        int c = ((byte << offset) & 0x80) ? _foreground : _background;
+        putp(c);
+    }
+}
+    
+int GraphicsDisplay::columns() { 
+    return width() / 8; 
+}
+
+int GraphicsDisplay::rows() { 
+    return height() / 8; 
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ILI9341/GraphicsDisplay.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,56 @@
+/* mbed GraphicsDisplay Display Library Base Class
+ * Copyright (c) 2007-2009 sford
+ * Released under the MIT License: http://mbed.org/license/mit
+ *
+ * A library for providing a common base class for Graphics displays
+ * To port a new display, derive from this class and implement
+ * the constructor (setup the display), pixel (put a pixel
+ * at a location), width and height functions. Everything else
+ * (locate, printf, putc, cls, window, putp, fill, blit, blitbit) 
+ * will come for free. You can also provide a specialised implementation
+ * of window and putp to speed up the results
+ */
+
+#ifndef MBED_GRAPHICSDISPLAY_H
+#define MBED_GRAPHICSDISPLAY_H
+
+#include "TextDisplay.h"
+
+class GraphicsDisplay : public TextDisplay {
+
+public:         
+          
+    GraphicsDisplay(const char* name);
+     
+    virtual void pixel(int x, int y, int colour) = 0;
+    virtual int width() = 0;
+    virtual int height() = 0;
+        
+    virtual void window(unsigned int x,unsigned int y,unsigned int w,unsigned int h);
+    virtual void putp(int colour);
+    
+    virtual void cls();
+    virtual void fill(int x, int y, int w, int h, int colour);
+    virtual void blit(int x, int y, int w, int h, const int *colour);    
+    virtual void blitbit(int x, int y, int w, int h, const char* colour);
+    
+    virtual void character(int column, int row, int value);
+    virtual int columns();
+    virtual int rows();
+    
+protected:
+
+    // pixel location
+    short _x;
+    short _y;
+    
+    // window location
+    short _x1;
+    short _x2;
+    short _y1;
+    short _y2;
+
+};
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ILI9341/SPI_TFT_ILI9341.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,807 @@
+/* mbed library for 240*320 pixel display TFT based on ILI9341 LCD Controller
+ * Copyright (c) 2013 Peter Drescher - DC2PD
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+ 
+// 12.06.13 fork from SPI_TFT code because controller is different ...
+// 14.07.13 Test with real display and bugfix 
+// 18.10.13 Better Circle function from Michael Ammann
+// 22.10.13 Fixes for Kinetis Board - 8 bit spi
+// 26.01.14 Change interface for BMP_16 to also use SD-cards
+// 23.06.14 switch back to old Version - fork for L152 
+// 24.06.14 Add compiler flag for optimized L152 version
+// 25.06.14 Add optimized F103 version
+
+// exclude this file for platforms with optimized version
+#if defined TARGET_NUCLEO_L152RE || defined TARGET_NUCLEO_F103RB || defined TARGET_LPC1768
+// this platforms are supported by special version in different source file
+#else
+
+#include "SPI_TFT_ILI9341.h"
+#include "mbed.h"
+
+#define BPP         16                  // Bits per pixel    
+         
+//extern Serial pc;
+//extern DigitalOut xx;     // debug !!
+
+SPI_TFT_ILI9341::SPI_TFT_ILI9341(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset, PinName dc, const char *name)
+    : GraphicsDisplay(name), SPI(mosi, miso, sclk,NC), _cs(cs), _reset(reset), _dc(dc)
+{
+    
+    orientation = 0;
+    char_x = 0;
+    SPI::format(8,3);                  // 8 bit spi mode 3
+    SPI::frequency(10000000);          // 10 Mhz SPI clock
+    tft_reset();
+}
+
+int SPI_TFT_ILI9341::width()
+{
+    if (orientation == 0 || orientation == 2) return 240;
+    else return 320;
+}
+
+
+int SPI_TFT_ILI9341::height()
+{
+    if (orientation == 0 || orientation == 2) return 320;
+    else return 240;
+}
+
+
+void SPI_TFT_ILI9341::set_orientation(unsigned int o)
+{
+    orientation = o;
+    wr_cmd(0x36);                     // MEMORY_ACCESS_CONTROL
+    switch (orientation) {
+        case 0:
+            SPI::write(0x48);
+            break;
+        case 1:
+            SPI::write(0x28);
+            break;
+        case 2:
+            SPI::write(0x88);
+            break;
+        case 3:
+            SPI::write(0xE8);
+            break;
+    }
+    _cs = 1; 
+    WindowMax();
+} 
+
+
+// write command to tft register
+
+void SPI_TFT_ILI9341::wr_cmd(unsigned char cmd)
+{
+    _dc = 0;
+    _cs = 0;
+    SPI::write(cmd);      // mbed lib
+    _dc = 1;
+}
+
+
+
+void SPI_TFT_ILI9341::wr_dat(unsigned char dat)
+{
+   SPI::write(dat);      // mbed lib
+}
+
+
+
+// the ILI9341 can read 
+
+char SPI_TFT_ILI9341::rd_byte(unsigned char cmd)
+{
+    char r;
+    _dc = 0;
+    _cs = 0;
+    SPI::write(cmd);      // mbed lib
+    _cs = 1;
+    r = SPI::write(0xff);
+    _cs = 1;    
+    return(r);
+}
+
+// read 32 bit
+int SPI_TFT_ILI9341::rd_32(unsigned char cmd)
+{
+    int d;
+    char r;
+    _dc = 0;
+    _cs = 0;
+    d = cmd;
+    d = d << 1;
+    SPI::format(9,3);    // we have to add a dummy clock cycle
+    SPI::write(d);
+    SPI::format(8,3);   
+    _dc = 1;
+    r = SPI::write(0xff);
+    d = r;
+    r = SPI::write(0xff);
+    d = (d << 8) | r;
+    r = SPI::write(0xff);
+    d = (d << 8) | r;
+    r = SPI::write(0xff);
+    d = (d << 8) | r;
+    _cs = 1;    
+    return(d);
+}
+
+int  SPI_TFT_ILI9341::Read_ID(void){
+    int r;
+    r = rd_byte(0x0A);
+    r = rd_byte(0x0A);
+    r = rd_byte(0x0A);
+    r = rd_byte(0x0A);
+    return(r);
+}
+
+
+// Init code based on MI0283QT datasheet
+
+void SPI_TFT_ILI9341::tft_reset()
+{
+    _cs = 1;                           // cs high
+    _dc = 1;                           // dc high 
+    _reset = 0;                        // display reset
+
+    wait_us(50);
+    _reset = 1;                       // end hardware reset
+    wait_ms(5);
+     
+    wr_cmd(0x01);                     // SW reset  
+    wait_ms(5);
+    wr_cmd(0x28);                     // display off  
+
+    /* Start Initial Sequence ----------------------------------------------------*/
+     wr_cmd(0xCF);                     
+     SPI::write(0x00);
+     SPI::write(0x83);
+     SPI::write(0x30);
+     _cs = 1;
+     
+     wr_cmd(0xED);                     
+     SPI::write(0x64);
+     SPI::write(0x03);
+     SPI::write(0x12);
+     SPI::write(0x81);
+     _cs = 1;
+     
+     wr_cmd(0xE8);                     
+     SPI::write(0x85);
+     SPI::write(0x01);
+     SPI::write(0x79);
+     _cs = 1;
+     
+     wr_cmd(0xCB);                     
+     SPI::write(0x39);
+     SPI::write(0x2C);
+     SPI::write(0x00);
+     SPI::write(0x34);
+     SPI::write(0x02);
+     _cs = 1;
+           
+     wr_cmd(0xF7);                     
+     SPI::write(0x20);
+     _cs = 1;
+           
+     wr_cmd(0xEA);                     
+     SPI::write(0x00);
+     SPI::write(0x00);
+     _cs = 1;
+     
+     wr_cmd(0xC0);                     // POWER_CONTROL_1
+     SPI::write(0x26);
+     _cs = 1;
+ 
+     wr_cmd(0xC1);                     // POWER_CONTROL_2
+     SPI::write(0x11);
+     _cs = 1;
+     
+     wr_cmd(0xC5);                     // VCOM_CONTROL_1
+     SPI::write(0x35);
+     SPI::write(0x3E);
+     _cs = 1;
+     
+     wr_cmd(0xC7);                     // VCOM_CONTROL_2
+     SPI::write(0xBE);
+     _cs = 1; 
+     
+     wr_cmd(0x36);                     // MEMORY_ACCESS_CONTROL
+     SPI::write(0x48);
+     _cs = 1; 
+     
+     wr_cmd(0x3A);                     // COLMOD_PIXEL_FORMAT_SET
+     SPI::write(0x55);                 // 16 bit pixel 
+     _cs = 1;
+     
+     wr_cmd(0xB1);                     // Frame Rate
+     SPI::write(0x00);
+     SPI::write(0x1B);               
+     _cs = 1;
+     
+     wr_cmd(0xF2);                     // Gamma Function Disable
+     SPI::write(0x08);
+     _cs = 1; 
+     
+     wr_cmd(0x26);                     
+     SPI::write(0x01);                 // gamma set for curve 01/2/04/08
+     _cs = 1; 
+     
+     wr_cmd(0xE0);                     // positive gamma correction
+     SPI::write(0x1F); 
+     SPI::write(0x1A); 
+     SPI::write(0x18); 
+     SPI::write(0x0A); 
+     SPI::write(0x0F); 
+     SPI::write(0x06); 
+     SPI::write(0x45); 
+     SPI::write(0x87); 
+     SPI::write(0x32); 
+     SPI::write(0x0A); 
+     SPI::write(0x07); 
+     SPI::write(0x02); 
+     SPI::write(0x07);
+     SPI::write(0x05); 
+     SPI::write(0x00);
+     _cs = 1;
+     
+     wr_cmd(0xE1);                     // negativ gamma correction
+     SPI::write(0x00); 
+     SPI::write(0x25); 
+     SPI::write(0x27); 
+     SPI::write(0x05); 
+     SPI::write(0x10); 
+     SPI::write(0x09); 
+     SPI::write(0x3A); 
+     SPI::write(0x78); 
+     SPI::write(0x4D); 
+     SPI::write(0x05); 
+     SPI::write(0x18); 
+     SPI::write(0x0D); 
+     SPI::write(0x38);
+     SPI::write(0x3A); 
+     SPI::write(0x1F);
+     _cs = 1;
+     
+     WindowMax ();
+     
+     //wr_cmd(0x34);                     // tearing effect off
+     //_cs = 1;
+     
+     //wr_cmd(0x35);                     // tearing effect on
+     //_cs = 1;
+      
+     wr_cmd(0xB7);                       // entry mode
+     SPI::write(0x07);
+     _cs = 1;
+     
+     wr_cmd(0xB6);                       // display function control
+     SPI::write(0x0A);
+     SPI::write(0x82);
+     SPI::write(0x27);
+     SPI::write(0x00);
+     _cs = 1;
+     
+     wr_cmd(0x11);                     // sleep out
+     _cs = 1;
+     
+     wait_ms(100);
+     
+     wr_cmd(0x29);                     // display on
+     _cs = 1;
+     
+     wait_ms(100);
+     
+ }
+
+
+void SPI_TFT_ILI9341::pixel(int x, int y, int color)
+{
+    wr_cmd(0x2A);
+    SPI::write(x >> 8);
+    SPI::write(x);
+    _cs = 1;
+    wr_cmd(0x2B);
+    SPI::write(y >> 8);
+    SPI::write(y);
+    _cs = 1;
+    wr_cmd(0x2C);  // send pixel
+    #if defined TARGET_KL25Z  // 8 Bit SPI
+    SPI::write(color >> 8);
+    SPI::write(color & 0xff);
+    #else 
+    SPI::format(16,3);                            // switch to 16 bit Mode 3
+    SPI::write(color);                              // Write D0..D15
+    SPI::format(8,3);
+    #endif
+    _cs = 1;
+}
+
+
+void SPI_TFT_ILI9341::window (unsigned int x, unsigned int y, unsigned int w, unsigned int h)
+{
+    wr_cmd(0x2A);
+    SPI::write(x >> 8);
+    SPI::write(x);
+    SPI::write((x+w-1) >> 8);
+    SPI::write(x+w-1);
+    
+    _cs = 1;
+    wr_cmd(0x2B);
+    SPI::write(y >> 8);
+    SPI::write(y);
+    SPI::write((y+h-1) >> 8);
+    SPI::write(y+h-1);
+    _cs = 1;
+}
+
+
+void SPI_TFT_ILI9341::WindowMax (void)
+{
+    window (0, 0, width(),  height());
+}
+
+
+
+void SPI_TFT_ILI9341::cls (void)
+{
+   // we can use the fillrect function 
+   fillrect(0,0,width()-1,height()-1,_background);
+}
+
+
+void SPI_TFT_ILI9341::circle(int x0, int y0, int r, int color)
+{
+
+    int x = -r, y = 0, err = 2-2*r, e2;
+    do {
+        pixel(x0-x, y0+y,color);
+        pixel(x0+x, y0+y,color);
+        pixel(x0+x, y0-y,color);
+        pixel(x0-x, y0-y,color);
+        e2 = err;
+        if (e2 <= y) {
+            err += ++y*2+1;
+            if (-x == y && e2 <= x) e2 = 0;
+        }
+        if (e2 > x) err += ++x*2+1;
+    } while (x <= 0);
+
+}
+
+void SPI_TFT_ILI9341::fillcircle(int x0, int y0, int r, int color)
+{
+    int x = -r, y = 0, err = 2-2*r, e2;
+    do {
+        vline(x0-x, y0-y, y0+y, color);
+        vline(x0+x, y0-y, y0+y, color);
+        e2 = err;
+        if (e2 <= y) {
+            err += ++y*2+1;
+            if (-x == y && e2 <= x) e2 = 0;
+        }
+        if (e2 > x) err += ++x*2+1;
+    } while (x <= 0);
+}
+
+
+void SPI_TFT_ILI9341::hline(int x0, int x1, int y, int color)
+{
+    int w;
+    w = x1 - x0 + 1;
+    window(x0,y,w,1);
+    wr_cmd(0x2C);  // send pixel
+    #if defined TARGET_KL25Z  // 8 Bit SPI
+    int j;
+    for (j=0; j<w; j++) {
+        SPI::write(color >> 8);
+        SPI::write(color & 0xff);
+    } 
+    #else 
+    SPI::format(16,3);                            // switch to 16 bit Mode 3
+    int j;
+    for (j=0; j<w; j++) {
+        SPI::write(color);
+    }
+    SPI::format(8,3);
+    #endif
+    _cs = 1;
+    WindowMax();
+    return;
+}
+
+void SPI_TFT_ILI9341::vline(int x, int y0, int y1, int color)
+{
+    int h;
+    h = y1 - y0 + 1;
+    window(x,y0,1,h);
+    wr_cmd(0x2C);  // send pixel
+    #if defined TARGET_KL25Z  // 8 Bit SPI
+    for (int y=0; y<h; y++) {
+        SPI::write(color >> 8);
+        SPI::write(color & 0xff);
+    } 
+    #else 
+    SPI::format(16,3);                            // switch to 16 bit Mode 3
+    for (int y=0; y<h; y++) {
+        SPI::write(color);
+    }
+    SPI::format(8,3);
+    #endif
+    _cs = 1;
+    WindowMax();
+    return;
+}
+
+
+
+void SPI_TFT_ILI9341::line(int x0, int y0, int x1, int y1, int color)
+{
+    //WindowMax();
+    int   dx = 0, dy = 0;
+    int   dx_sym = 0, dy_sym = 0;
+    int   dx_x2 = 0, dy_x2 = 0;
+    int   di = 0;
+
+    dx = x1-x0;
+    dy = y1-y0;
+
+    if (dx == 0) {        /* vertical line */
+        if (y1 > y0) vline(x0,y0,y1,color);
+        else vline(x0,y1,y0,color);
+        return;
+    }
+
+    if (dx > 0) {
+        dx_sym = 1;
+    } else {
+        dx_sym = -1;
+    }
+    if (dy == 0) {        /* horizontal line */
+        if (x1 > x0) hline(x0,x1,y0,color);
+        else  hline(x1,x0,y0,color);
+        return;
+    }
+
+    if (dy > 0) {
+        dy_sym = 1;
+    } else {
+        dy_sym = -1;
+    }
+
+    dx = dx_sym*dx;
+    dy = dy_sym*dy;
+
+    dx_x2 = dx*2;
+    dy_x2 = dy*2;
+
+    if (dx >= dy) {
+        di = dy_x2 - dx;
+        while (x0 != x1) {
+
+            pixel(x0, y0, color);
+            x0 += dx_sym;
+            if (di<0) {
+                di += dy_x2;
+            } else {
+                di += dy_x2 - dx_x2;
+                y0 += dy_sym;
+            }
+        }
+        pixel(x0, y0, color);
+    } else {
+        di = dx_x2 - dy;
+        while (y0 != y1) {
+            pixel(x0, y0, color);
+            y0 += dy_sym;
+            if (di < 0) {
+                di += dx_x2;
+            } else {
+                di += dx_x2 - dy_x2;
+                x0 += dx_sym;
+            }
+        }
+        pixel(x0, y0, color);
+    }
+    return;
+}
+
+
+void SPI_TFT_ILI9341::rect(int x0, int y0, int x1, int y1, int color)
+{
+
+    if (x1 > x0) hline(x0,x1,y0,color);
+    else  hline(x1,x0,y0,color);
+
+    if (y1 > y0) vline(x0,y0,y1,color);
+    else vline(x0,y1,y0,color);
+
+    if (x1 > x0) hline(x0,x1,y1,color);
+    else  hline(x1,x0,y1,color);
+
+    if (y1 > y0) vline(x1,y0,y1,color);
+    else vline(x1,y1,y0,color);
+
+    return;
+}
+
+
+
+void SPI_TFT_ILI9341::fillrect(int x0, int y0, int x1, int y1, int color)
+{
+
+    int h = y1 - y0 + 1;
+    int w = x1 - x0 + 1;
+    int pixel = h * w;
+    window(x0,y0,w,h);
+    wr_cmd(0x2C);  // send pixel 
+    #if defined TARGET_KL25Z  // 8 Bit SPI
+    for (int p=0; p<pixel; p++) {
+        SPI::write(color >> 8);
+        SPI::write(color & 0xff);
+    }
+   #else
+    SPI::format(16,3);                            // switch to 16 bit Mode 3
+    for (int p=0; p<pixel; p++) {
+        SPI::write(color);
+    }
+    SPI::format(8,3);
+    #endif
+    _cs = 1;
+    WindowMax();
+    return;
+}
+
+
+void SPI_TFT_ILI9341::locate(int x, int y)
+{
+    char_x = x;
+    char_y = y;
+}
+
+
+
+int SPI_TFT_ILI9341::columns()
+{
+    return width() / font[1];
+}
+
+
+
+int SPI_TFT_ILI9341::rows()
+{
+    return height() / font[2];
+}
+
+
+
+int SPI_TFT_ILI9341::_putc(int value)
+{
+    if (value == '\n') {    // new line
+        char_x = 0;
+        char_y = char_y + font[2];
+        if (char_y >= height() - font[2]) {
+            char_y = 0;
+        }
+    } else {
+        character(char_x, char_y, value);
+    }
+    return value;
+}
+
+
+void SPI_TFT_ILI9341::character(int x, int y, int c)
+{
+    unsigned int hor,vert,offset,bpl,j,i,b;
+    unsigned char* zeichen;
+    unsigned char z,w;
+
+    if ((c < 31) || (c > 127)) return;   // test char range
+
+    // read font parameter from start of array
+    offset = font[0];                    // bytes / char
+    hor = font[1];                       // get hor size of font
+    vert = font[2];                      // get vert size of font
+    bpl = font[3];                       // bytes per line
+
+    if (char_x + hor > width()) {
+        char_x = 0;
+        char_y = char_y + vert;
+        if (char_y >= height() - font[2]) {
+            char_y = 0;
+        }
+    }
+    window(char_x, char_y,hor,vert); // char box
+    wr_cmd(0x2C);  // send pixel
+    #ifndef TARGET_KL25Z  // 16 Bit SPI 
+    SPI::format(16,3);   
+    #endif                         // switch to 16 bit Mode 3
+    zeichen = &font[((c -32) * offset) + 4]; // start of char bitmap
+    w = zeichen[0];                          // width of actual char
+     for (j=0; j<vert; j++) {  //  vert line
+        for (i=0; i<hor; i++) {   //  horz line
+            z =  zeichen[bpl * i + ((j & 0xF8) >> 3)+1];
+            b = 1 << (j & 0x07);
+            if (( z & b ) == 0x00) {
+               #ifndef TARGET_KL25Z  // 16 Bit SPI 
+                SPI::write(_background);
+               #else
+                SPI::write(_background >> 8);
+                SPI::write(_background & 0xff);
+                #endif
+            } else {
+                #ifndef TARGET_KL25Z  // 16 Bit SPI
+                SPI::write(_foreground);
+                #else
+                SPI::write(_foreground >> 8);
+                SPI::write(_foreground & 0xff);
+                #endif
+            }
+        }
+    }
+    _cs = 1;
+    #ifndef TARGET_KL25Z  // 16 Bit SPI
+    SPI::format(8,3);
+    #endif
+    WindowMax();
+    if ((w + 2) < hor) {                   // x offset to next char
+        char_x += w + 2;
+    } else char_x += hor;
+}
+
+
+void SPI_TFT_ILI9341::set_font(unsigned char* f)
+{
+    font = f;
+}
+
+
+
+void SPI_TFT_ILI9341::Bitmap(unsigned int x, unsigned int y, unsigned int w, unsigned int h,unsigned char *bitmap)
+{
+    unsigned int  j;
+    int padd;
+    unsigned short *bitmap_ptr = (unsigned short *)bitmap;
+    #if defined TARGET_KL25Z  // 8 Bit SPI
+        unsigned short pix_temp;
+    #endif
+    
+    unsigned int i;
+    
+    // the lines are padded to multiple of 4 bytes in a bitmap
+    padd = -1;
+    do {
+        padd ++;
+    } while (2*(w + padd)%4 != 0);
+    window(x, y, w, h);
+    bitmap_ptr += ((h - 1)* (w + padd));
+    wr_cmd(0x2C);  // send pixel
+    #ifndef TARGET_KL25Z  // 16 Bit SPI 
+    SPI::format(16,3);
+    #endif                            // switch to 16 bit Mode 3
+    for (j = 0; j < h; j++) {         //Lines
+        for (i = 0; i < w; i++) {     // one line
+            #if defined TARGET_KL25Z  // 8 Bit SPI
+                pix_temp = *bitmap_ptr;
+                SPI::write(pix_temp >> 8);
+                SPI::write(pix_temp);
+                bitmap_ptr++;
+            #else
+                SPI::write(*bitmap_ptr);    // one line
+                bitmap_ptr++;
+            #endif
+        }
+        bitmap_ptr -= 2*w;
+        bitmap_ptr -= padd;
+    }
+    _cs = 1;
+    #ifndef TARGET_KL25Z  // 16 Bit SPI 
+    SPI::format(8,3);
+    #endif
+    WindowMax();
+}
+
+
+// local filesystem is not implemented in kinetis board , but you can add a SD card
+
+int SPI_TFT_ILI9341::BMP_16(unsigned int x, unsigned int y, const char *Name_BMP)
+{
+
+#define OffsetPixelWidth    18
+#define OffsetPixelHeigh    22
+#define OffsetFileSize      34
+#define OffsetPixData       10
+#define OffsetBPP           28
+
+    char filename[50];
+    unsigned char BMP_Header[54];
+    unsigned short BPP_t;
+    unsigned int PixelWidth,PixelHeigh,start_data;
+    unsigned int    i,off;
+    int padd,j;
+    unsigned short *line;
+
+    // get the filename
+    i=0;
+    while (*Name_BMP!='\0') {
+        filename[i++]=*Name_BMP++;
+    }
+    filename[i] = 0;  
+    
+    FILE *Image = fopen((const char *)&filename[0], "rb");  // open the bmp file
+    if (!Image) {
+        return(0);      // error file not found !
+    }
+
+    fread(&BMP_Header[0],1,54,Image);      // get the BMP Header
+
+    if (BMP_Header[0] != 0x42 || BMP_Header[1] != 0x4D) {  // check magic byte
+        fclose(Image);
+        return(-1);     // error no BMP file
+    }
+
+    BPP_t = BMP_Header[OffsetBPP] + (BMP_Header[OffsetBPP + 1] << 8);
+    if (BPP_t != 0x0010) {
+        fclose(Image);
+        return(-2);     // error no 16 bit BMP
+    }
+
+    PixelHeigh = BMP_Header[OffsetPixelHeigh] + (BMP_Header[OffsetPixelHeigh + 1] << 8) + (BMP_Header[OffsetPixelHeigh + 2] << 16) + (BMP_Header[OffsetPixelHeigh + 3] << 24);
+    PixelWidth = BMP_Header[OffsetPixelWidth] + (BMP_Header[OffsetPixelWidth + 1] << 8) + (BMP_Header[OffsetPixelWidth + 2] << 16) + (BMP_Header[OffsetPixelWidth + 3] << 24);
+    if (PixelHeigh > height() + y || PixelWidth > width() + x) {
+        fclose(Image);
+        return(-3);      // to big
+    }
+
+    start_data = BMP_Header[OffsetPixData] + (BMP_Header[OffsetPixData + 1] << 8) + (BMP_Header[OffsetPixData + 2] << 16) + (BMP_Header[OffsetPixData + 3] << 24);
+
+    line = (unsigned short *) malloc (2 * PixelWidth); // we need a buffer for a line
+    if (line == NULL) {
+        return(-4);         // error no memory
+    }
+
+    // the bmp lines are padded to multiple of 4 bytes
+    padd = -1;
+    do {
+        padd ++;
+    } while ((PixelWidth * 2 + padd)%4 != 0);
+
+    window(x, y,PixelWidth ,PixelHeigh);
+    wr_cmd(0x2C);  // send pixel
+    #ifndef TARGET_KL25Z // only 8 Bit SPI 
+    SPI::format(16,3);  
+    #endif                          // switch to 16 bit Mode 3
+    for (j = PixelHeigh - 1; j >= 0; j--) {               //Lines bottom up
+        off = j * (PixelWidth  * 2 + padd) + start_data;   // start of line
+        fseek(Image, off ,SEEK_SET);
+        fread(line,1,PixelWidth * 2,Image);       // read a line - slow 
+        for (i = 0; i < PixelWidth; i++) {        // copy pixel data to TFT
+        #ifndef TARGET_KL25Z // only 8 Bit SPI
+            SPI::write(line[i]);                  // one 16 bit pixel
+        #else  
+            SPI::write(line[i] >> 8);
+            SPI::write(line[i]);
+        #endif    
+        } 
+     }
+    _cs = 1;
+    SPI::format(8,3);
+    free (line);
+    fclose(Image);
+    WindowMax();
+    return(1);
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ILI9341/SPI_TFT_ILI9341.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,411 @@
+/* mbed library for 240*320 pixel display TFT based on ILI9341 LCD Controller
+ * Copyright (c) 2013 Peter Drescher - DC2PD
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+ 
+ /* change the char position handling
+  * use pixel (x,y) instadt of colum row */
+ 
+#ifndef MBED_SPI_TFT_ILI9341_H
+#define MBED_SPI_TFT_ILI9341_H
+
+#include "mbed.h"
+#include "GraphicsDisplay.h"
+
+#define RGB(r,g,b)  (((r&0xF8)<<8)|((g&0xFC)<<3)|((b&0xF8)>>3)) //5 red | 6 green | 5 blue
+
+
+/* some RGB color definitions                                                 */
+#define Black           0x0000      /*   0,   0,   0 */
+#define Navy            0x000F      /*   0,   0, 128 */
+#define DarkGreen       0x03E0      /*   0, 128,   0 */
+#define DarkCyan        0x03EF      /*   0, 128, 128 */
+#define Maroon          0x7800      /* 128,   0,   0 */
+#define Purple          0x780F      /* 128,   0, 128 */
+#define Olive           0x7BE0      /* 128, 128,   0 */
+#define LightGrey       0xC618      /* 192, 192, 192 */
+#define DarkGrey        0x7BEF      /* 128, 128, 128 */
+#define Blue            0x001F      /*   0,   0, 255 */
+#define Green           0x07E0      /*   0, 255,   0 */
+#define Cyan            0x07FF      /*   0, 255, 255 */
+#define Red             0xF800      /* 255,   0,   0 */
+#define Magenta         0xF81F      /* 255,   0, 255 */
+#define Yellow          0xFFE0      /* 255, 255,   0 */
+#define White           0xFFFF      /* 255, 255, 255 */
+#define Orange          0xFD20      /* 255, 165,   0 */
+#define GreenYellow     0xAFE5      /* 173, 255,  47 */
+
+
+/** Display control class, based on GraphicsDisplay and TextDisplay
+ *
+ * Example:
+ * @code
+ * #include "stdio.h"
+ * #include "mbed.h"
+ * #include "SPI_TFT_ILI9341.h"
+ * #include "string"
+ * #include "Arial12x12.h"
+ * #include "Arial24x23.h"
+ * 
+ *
+ *
+ * // the TFT is connected to SPI pin 5-7 and IO's 8-10
+ * SPI_TFT_ILI9341 TFT(p5, p6, p7, p8, p9, p10,"TFT"); // mosi, miso, sclk, cs, reset, dc
+ * If your display need a signal for switch the backlight use a aditional IO pin in your program 
+ *
+ * int main() {
+ *     TFT.claim(stdout);      // send stdout to the TFT display 
+ *     //TFT.claim(stderr);      // send stderr to the TFT display
+ *
+ *     TFT.background(Black);    // set background to black
+ *     TFT.foreground(White);    // set chars to white
+ *     TFT.cls();                // clear the screen
+ *     TFT.set_font((unsigned char*) Arial12x12);  // select the font
+ *     
+ *     TFT.set_orientation(0);
+ *     printf("  Hello Mbed 0");
+ *     TFT.set_font((unsigned char*) Arial24x23);  // select font 2
+ *     TFT.locate(48,115);
+ *     TFT.printf("Bigger Font");
+ *  }
+ * @endcode
+ */
+ class SPI_TFT_ILI9341 : public GraphicsDisplay , public SPI {
+ public:
+
+  /** Create a SPI_TFT object connected to SPI and three pins
+   *
+   * @param mosi pin connected to SDO of display
+   * @param miso pin connected to SDI of display
+   * @param sclk pin connected to RS of display 
+   * @param cs pin connected to CS of display
+   * @param reset pin connected to RESET of display
+   * @param dc pin connected to WR of display
+   * the IM pins have to be set to 1110 (3-0) 
+   */ 
+  SPI_TFT_ILI9341(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset, PinName dc, const char* name ="TFT");
+    
+  /** Get the width of the screen in pixel
+   *
+   * @returns width of screen in pixel
+   *
+   */    
+  virtual int width();
+
+  /** Get the height of the screen in pixel
+   *
+   * @returns height of screen in pixel 
+   *
+   */     
+  virtual int height();
+    
+  /** Draw a pixel at x,y with color 
+   *  
+   * @param x horizontal position
+   * @param y vertical position
+   * @param color 16 bit pixel color
+   */    
+  virtual void pixel(int x, int y,int colour);
+    
+  /** draw a circle
+   *
+   * @param x0,y0 center
+   * @param r radius
+   * @param color 16 bit color                                                                 *
+   *
+   */    
+  void circle(int x, int y, int r, int colour); 
+  
+  /** draw a filled circle
+   *
+   * @param x0,y0 center
+   * @param r radius
+   * @param color 16 bit color                                                                 *
+   */    
+  void fillcircle(int x, int y, int r, int colour); 
+ 
+    
+  /** draw a 1 pixel line
+   *
+   * @param x0,y0 start point
+   * @param x1,y1 stop point
+   * @param color 16 bit color
+   *
+   */    
+  void line(int x0, int y0, int x1, int y1, int colour);
+    
+  /** draw a rect
+   *
+   * @param x0,y0 top left corner
+   * @param x1,y1 down right corner
+   * @param color 16 bit color
+   *                                                   *
+   */    
+  void rect(int x0, int y0, int x1, int y1, int colour);
+    
+  /** draw a filled rect
+   *
+   * @param x0,y0 top left corner
+   * @param x1,y1 down right corner
+   * @param color 16 bit color
+   *
+   */    
+  void fillrect(int x0, int y0, int x1, int y1, int colour);
+    
+  /** setup cursor position
+   *
+   * @param x x-position (top left)
+   * @param y y-position 
+   */   
+  virtual void locate(int x, int y);
+    
+  /** Fill the screen with _backgroun color
+   *
+   */   
+  virtual void cls (void);   
+    
+  /** calculate the max number of char in a line
+   *
+   * @returns max columns
+   * depends on actual font size
+   *
+   */    
+  virtual int columns(void);
+    
+  /** calculate the max number of columns
+   *
+   * @returns max column
+   * depends on actual font size
+   *
+   */   
+  virtual int rows(void);
+    
+  /** put a char on the screen
+   *
+   * @param value char to print
+   * @returns printed char
+   *
+   */
+  virtual int _putc(int value);
+    
+  /** draw a character on given position out of the active font to the TFT
+   *
+   * @param x x-position of char (top left) 
+   * @param y y-position
+   * @param c char to print
+   *
+   */    
+  virtual void character(int x, int y, int c);
+    
+  /** paint a bitmap on the TFT 
+   *
+   * @param x,y : upper left corner 
+   * @param w width of bitmap
+   * @param h high of bitmap
+   * @param *bitmap pointer to the bitmap data
+   *
+   *   bitmap format: 16 bit R5 G6 B5
+   * 
+   *   use Gimp to create / load , save as BMP, option 16 bit R5 G6 B5            
+   *   use winhex to load this file and mark data stating at offset 0x46 to end
+   *   use edit -> copy block -> C Source to export C array
+   *   paste this array into your program
+   * 
+   *   define the array as static const unsigned char to put it into flash memory
+   *   cast the pointer to (unsigned char *) :
+   *   tft.Bitmap(10,40,309,50,(unsigned char *)scala);
+   */    
+  void Bitmap(unsigned int x, unsigned int y, unsigned int w, unsigned int h,unsigned char *bitmap);
+    
+    
+   /** paint a 16 bit BMP from filesytem on the TFT (slow) 
+   *
+   * @param x,y : position of upper left corner 
+   * @param *Name_BMP name of the BMP file with drive: "/local/test.bmp"
+   *
+   * @returns 1 if bmp file was found and painted
+   * @returns  0 if bmp file was found not found
+   * @returns -1 if file is no bmp
+   * @returns -2 if bmp file is no 16 bit bmp
+   * @returns -3 if bmp file is to big for screen 
+   * @returns -4 if buffer malloc go wrong
+   *
+   *   bitmap format: 16 bit R5 G6 B5
+   * 
+   *   use Gimp to create / load , save as BMP, option 16 bit R5 G6 B5
+   *   copy to internal file system or SD card           
+   */      
+    
+  int BMP_16(unsigned int x, unsigned int y, const char *Name_BMP);  
+    
+    
+    
+  /** select the font to use
+   *
+   * @param f pointer to font array 
+   *                                                                              
+   *   font array can created with GLCD Font Creator from http://www.mikroe.com
+   *   you have to add 4 parameter at the beginning of the font array to use: 
+   *   - the number of byte / char
+   *   - the vertial size in pixel
+   *   - the horizontal size in pixel
+   *   - the number of byte per vertical line
+   *   you also have to change the array to char[]
+   *
+   */  
+  void set_font(unsigned char* f);
+   
+  /** Set the orientation of the screen
+   *  x,y: 0,0 is always top left 
+   *
+   * @param o direction to use the screen (0-3)  
+   *
+   */  
+  void set_orientation(unsigned int o);
+  
+  
+  /** read out the manufacturer ID of the LCD
+   *  can used for checking the connection to the display
+   *  @returns ID
+   */ 
+  int Read_ID(void);
+  
+  DigitalOut _cs; 
+  DigitalOut _reset;
+  DigitalOut _dc;
+  unsigned char* font;
+  
+  
+  
+   
+protected:
+
+  /** Set draw window region to whole screen
+   *
+   */  
+  void WindowMax (void);
+
+
+  /** draw a horizontal line
+   *
+   * @param x0 horizontal start
+   * @param x1 horizontal stop
+   * @param y vertical position
+   * @param color 16 bit color                                               
+   *
+   */
+  void hline(int x0, int x1, int y, int colour);
+    
+  /** draw a vertical line
+   *
+   * @param x horizontal position
+   * @param y0 vertical start 
+   * @param y1 vertical stop
+   * @param color 16 bit color
+   */
+  void vline(int y0, int y1, int x, int colour);
+    
+  /** Set draw window region
+   *
+   * @param x horizontal position
+   * @param y vertical position
+   * @param w window width in pixel
+   * @param h window height in pixels
+   */    
+  virtual void window (unsigned int x,unsigned int y, unsigned int w, unsigned int h);
+    
+ 
+    
+  /** Init the ILI9341 controller 
+   *
+   */    
+  void tft_reset();
+    
+   /** Write data to the LCD controller
+   *
+   * @param dat data written to LCD controller
+   * 
+   */   
+  //void wr_dat(unsigned int value);
+  void wr_dat(unsigned char value);
+    
+  /** Write a command the LCD controller 
+   *
+   * @param cmd: command to be written   
+   *
+   */   
+  void wr_cmd(unsigned char value);
+    
+   /** Start data sequence to the LCD controller
+   * 
+   */   
+  //void wr_dat_start();
+    
+  /** Stop of data writing to the LCD controller
+   *   
+   */  
+  //void wr_dat_stop();
+    
+  /** write data to the LCD controller
+   *
+   * @param data to be written 
+   *                                           *
+   */    
+  //void wr_dat_only(unsigned short dat);
+    
+  /** Read byte from the LCD controller
+   *
+   * @param cmd comand to controller
+   * @returns data from LCD controller
+   *  
+   */    
+   char rd_byte(unsigned char cmd);
+    
+  
+  int rd_32(unsigned char cmd);  
+    
+    
+  /** Write a value to the to a LCD register
+   *
+   * @param reg register to be written
+   * @param val data to be written
+   */   
+  //void wr_reg (unsigned char reg, unsigned char val);
+    
+  /** Read a LCD register
+   *
+   * @param reg register to be read
+   * @returns value of the register 
+   */    
+  //unsigned short rd_reg (unsigned char reg);
+    
+  #if defined TARGET_NUCLEO_L152RE || defined TARGET_NUCLEO_F103RB || defined TARGET_LPC1768
+  /** fast SPI write function for optimized versions 
+   *
+   * @param data  data written to SPI
+   *
+   */
+  virtual void f_write(int data);
+  virtual void spi_bsy(void);
+  virtual void spi_16(bool s);
+  
+  #endif  
+    
+  unsigned char spi_port; 
+  unsigned int orientation;
+  unsigned int char_x;
+  unsigned int char_y;
+  unsigned char spi_num;
+  
+    
+};
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ILI9341/SPI_TFT_ILI9341_NUCLEO.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1050 @@
+/* mbed library for 240*320 pixel display TFT based on ILI9341 LCD Controller
+ * Copyright (c) 2013, 2014 Peter Drescher - DC2PD
+ * Special version for STM Nucleo -L152
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+ // 24.06.14   initial version
+ // 25.06.14   add Nucleo F103RB 
+
+// only include this file if target is L152 or F103RB : 
+#if defined TARGET_NUCLEO_L152RE || defined TARGET_NUCLEO_F103RB
+
+#include "SPI_TFT_ILI9341.h"
+#include "mbed.h"
+
+#if defined TARGET_NUCLEO_L152RE
+#include "stm32l1xx_dma.h"
+#define use_ram
+#endif
+
+#if defined TARGET_NUCLEO_F103RB
+#include "stm32f10x_dma.h"
+#endif
+
+
+#define BPP         16                  // Bits per pixel
+
+//extern Serial pc;
+//extern DigitalOut xx;     // debug !!
+
+DMA_InitTypeDef DMA_InitStructure; 
+
+
+SPI_TFT_ILI9341::SPI_TFT_ILI9341(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset, PinName dc, const char *name)
+    : GraphicsDisplay(name), SPI(mosi,miso,sclk,NC), _cs(cs), _reset(reset), _dc(dc)
+{
+
+    format(8,3);                 // 8 bit spi mode 3
+    frequency(10000000);         // 10 Mhz SPI clock : result 2 / 4 = 8
+    orientation = 0;
+    char_x = 0;
+    if(_spi.spi == SPI_1){       // test which SPI is in use
+         spi_num = 1;
+    }
+    if(_spi.spi == SPI_2){
+         spi_num = 2;
+    }
+    #ifdef SPI_3                // there is no SPI 3 on all devices
+    if(_spi.spi == SPI_3){
+         spi_num = 3;
+    }
+    #endif
+    tft_reset();
+}
+
+// we define a fast write to the SPI port
+// we use the bit banding address to get the flag without masking
+
+#define bit_SPI1_txe  *((volatile unsigned int *)0x42260104)
+#define SPI1_DR       *((volatile unsigned int *)0x4001300C)
+#define bit_SPI2_txe  *((volatile unsigned int *)0x42070104)
+#define SPI2_DR       *((volatile unsigned int *)0x4000380C)
+#define bit_SPI3_txe  *((volatile unsigned int *)0x42078104)
+#define SPI3_DR       *((volatile unsigned int *)0x40003C0C)
+
+void SPI_TFT_ILI9341::f_write(int data){
+
+switch(spi_num){  // used SPI port
+case (1):
+    while(bit_SPI1_txe == 0);  // wait for SPI1->SR TXE flag
+    SPI1_DR = data;
+    break;
+
+case (2):
+    while( bit_SPI2_txe  == 0);  // wait for SPI2->SR TXE flag
+    SPI2_DR = data;
+    break;
+
+case (3):
+    while( bit_SPI3_txe == 0);  // wait for SPI3->SR TXE flag
+    SPI3_DR = data;
+    break;
+
+    }
+}
+
+// wait for SPI not busy
+// we have to wait for the last bit to switch the cs off
+// we use the bit banding address to get the flag without masking
+
+#define bit_SPI1_bsy  *((volatile unsigned int *)0x4226011C)
+#define bit_SPI2_bsy  *((volatile unsigned int *)0x4207011C)
+#define bit_SPI3_bsy  *((volatile unsigned int *)0x4207811C)
+
+void inline SPI_TFT_ILI9341::spi_bsy(void){    
+switch(spi_num){        // decide which SPI is to use
+case (1):
+    while(bit_SPI1_bsy == 1);   // SPI1->SR bit 7
+    break;
+
+case (2):
+    while(bit_SPI2_bsy == 1);   // SPI2->SR bit 7
+    break;
+
+case (3):
+    while(bit_SPI3_bsy == 1);   // SPI2->SR bit 7
+    break;
+    }
+}
+
+
+// switch fast between 8 and 16 bit mode
+#define bit_SPI1_dff  *((volatile unsigned int *)0x4226002C)
+#define bit_SPI2_dff  *((volatile unsigned int *)0x4207002C)
+#define bit_SPI3_dff  *((volatile unsigned int *)0x4207802C)
+void SPI_TFT_ILI9341::spi_16(bool s){
+switch(spi_num){        // decide which SPI is to use
+case(1):
+    if(s) bit_SPI1_dff = 1; // switch to 16 bit Mode
+    else  bit_SPI1_dff = 0; // switch to 8  bit Mode
+    break;
+
+case(2):
+    if(s) bit_SPI2_dff = 1; // switch to 16 bit Mode
+    else  bit_SPI2_dff = 0; // switch to 8  bit Mode
+    break;
+
+case(3):
+    if(s) bit_SPI3_dff = 1; // switch to 16 bit Mode
+    else  bit_SPI3_dff = 0; // switch to 8  bit Mode
+    break;
+    }
+}
+
+
+int SPI_TFT_ILI9341::width()
+{
+    if (orientation == 0 || orientation == 2) return 240;
+    else return 320;
+}
+
+
+int SPI_TFT_ILI9341::height()
+{
+    if (orientation == 0 || orientation == 2) return 320;
+    else return 240;
+}
+
+
+void SPI_TFT_ILI9341::set_orientation(unsigned int o)
+{
+    orientation = o;
+    wr_cmd(0x36);                     // MEMORY_ACCESS_CONTROL
+    switch (orientation) {
+        case 0:
+            f_write(0x48);
+            break;
+        case 1:
+            f_write(0x28);
+            break;
+        case 2:
+            f_write(0x88);
+            break;
+        case 3:
+            f_write(0xE8);
+            break;
+    }
+    spi_bsy();    // wait for end of transfer
+    _cs = 1;
+    WindowMax();
+}
+
+
+// write command to tft register
+// use fast command
+void SPI_TFT_ILI9341::wr_cmd(unsigned char cmd)
+{
+    _dc = 0;
+    _cs = 0;
+    f_write(cmd);
+    spi_bsy();
+    _dc = 1;
+}
+
+void SPI_TFT_ILI9341::wr_dat(unsigned char dat)
+{
+   f_write(dat);
+   spi_bsy();  // wait for SPI send
+}
+
+// the ILI9341 can read
+char SPI_TFT_ILI9341::rd_byte(unsigned char cmd)
+{
+    // has to change !!
+    return(0);
+}
+
+// read 32 bit
+int SPI_TFT_ILI9341::rd_32(unsigned char cmd)
+{
+    // has to change !!!
+    return(0);
+}
+
+int  SPI_TFT_ILI9341::Read_ID(void){
+    int r;
+    r = rd_byte(0x0A);
+    r = rd_byte(0x0A);
+    r = rd_byte(0x0A);
+    r = rd_byte(0x0A);
+    return(r);
+}
+
+
+// Init code based on MI0283QT datasheet
+// this code is called only at start
+// no need to be optimized
+
+void SPI_TFT_ILI9341::tft_reset()
+{
+    _cs = 1;                           // cs high
+    _dc = 1;                           // dc high
+    _reset = 0;                        // display reset
+
+    wait_us(50);
+    _reset = 1;                       // end hardware reset
+    wait_ms(5);
+
+    wr_cmd(0x01);                     // SW reset
+    wait_ms(5);
+    wr_cmd(0x28);                     // display off
+
+    /* Start Initial Sequence ----------------------------------------------------*/
+    wr_cmd(0xCF);
+    f_write(0x00);
+    f_write(0x83);
+    f_write(0x30);
+    spi_bsy();
+     _cs = 1;
+
+     wr_cmd(0xED);
+     f_write(0x64);
+     f_write(0x03);
+     f_write(0x12);
+     f_write(0x81);
+     spi_bsy();
+     _cs = 1;
+
+     wr_cmd(0xE8);
+     f_write(0x85);
+     f_write(0x01);
+     f_write(0x79);
+     spi_bsy();
+     _cs = 1;
+
+     wr_cmd(0xCB);
+     f_write(0x39);
+     f_write(0x2C);
+     f_write(0x00);
+     f_write(0x34);
+     f_write(0x02);
+     spi_bsy();
+     _cs = 1;
+
+     wr_cmd(0xF7);
+     f_write(0x20);
+     spi_bsy();
+     _cs = 1;
+
+     wr_cmd(0xEA);
+     f_write(0x00);
+     f_write(0x00);
+     spi_bsy();
+     _cs = 1;
+
+     wr_cmd(0xC0);                     // POWER_CONTROL_1
+     f_write(0x26);
+     spi_bsy();
+     _cs = 1;
+
+     wr_cmd(0xC1);                     // POWER_CONTROL_2
+     f_write(0x11);
+     spi_bsy();
+     _cs = 1;
+
+     wr_cmd(0xC5);                     // VCOM_CONTROL_1
+     f_write(0x35);
+     f_write(0x3E);
+     spi_bsy();
+     _cs = 1;
+
+     wr_cmd(0xC7);                     // VCOM_CONTROL_2
+     f_write(0xBE);
+     spi_bsy();
+     _cs = 1;
+
+     wr_cmd(0x36);                     // MEMORY_ACCESS_CONTROL
+     f_write(0x48);
+     spi_bsy();
+     _cs = 1;
+
+     wr_cmd(0x3A);                     // COLMOD_PIXEL_FORMAT_SET
+     f_write(0x55);                 // 16 bit pixel
+     spi_bsy();
+     _cs = 1;
+
+     wr_cmd(0xB1);                     // Frame Rate
+     f_write(0x00);
+     f_write(0x1B);
+     spi_bsy();
+     _cs = 1;
+
+     wr_cmd(0xF2);                     // Gamma Function Disable
+     f_write(0x08);
+     spi_bsy();
+     _cs = 1;
+
+     wr_cmd(0x26);
+     f_write(0x01);                 // gamma set for curve 01/2/04/08
+     spi_bsy();
+     _cs = 1;
+
+     wr_cmd(0xE0);                     // positive gamma correction
+     f_write(0x1F);
+     f_write(0x1A);
+     f_write(0x18);
+     f_write(0x0A);
+     f_write(0x0F);
+     f_write(0x06);
+     f_write(0x45);
+     f_write(0x87);
+     f_write(0x32);
+     f_write(0x0A);
+     f_write(0x07);
+     f_write(0x02);
+     f_write(0x07);
+     f_write(0x05);
+     f_write(0x00);
+     spi_bsy();
+     _cs = 1;
+
+     wr_cmd(0xE1);                     // negativ gamma correction
+     f_write(0x00);
+     f_write(0x25);
+     f_write(0x27);
+     f_write(0x05);
+     f_write(0x10);
+     f_write(0x09);
+     f_write(0x3A);
+     f_write(0x78);
+     f_write(0x4D);
+     f_write(0x05);
+     f_write(0x18);
+     f_write(0x0D);
+     f_write(0x38);
+     f_write(0x3A);
+     f_write(0x1F);
+     spi_bsy();
+     _cs = 1;
+
+     WindowMax ();
+
+     //wr_cmd(0x34);                     // tearing effect off
+     //_cs = 1;
+
+     //wr_cmd(0x35);                     // tearing effect on
+     //_cs = 1;
+
+     wr_cmd(0xB7);                       // entry mode
+     f_write(0x07);
+     spi_bsy();
+     _cs = 1;
+
+     wr_cmd(0xB6);                       // display function control
+     f_write(0x0A);
+     f_write(0x82);
+     f_write(0x27);
+     f_write(0x00);
+     spi_bsy();
+     _cs = 1;
+
+     wr_cmd(0x11);                     // sleep out
+     spi_bsy();
+     _cs = 1;
+
+     wait_ms(100);
+
+     wr_cmd(0x29);                     // display on
+     spi_bsy();
+     _cs = 1;
+
+     wait_ms(100);
+
+    //    Configure the DMA controller init-structure
+    DMA_StructInit(&DMA_InitStructure);
+    switch(spi_num){        // decide which SPI is to use
+    case (1):
+        RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);    // SPI1 and SPI2 are using DMA 1
+        DMA_InitStructure.DMA_PeripheralBaseAddr  = (uint32_t) &(SPI1->DR);
+        break;
+    case (2):
+        RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);    // SPI1 and SPI2 are using DMA 1
+        DMA_InitStructure.DMA_PeripheralBaseAddr  = (uint32_t) &(SPI2->DR);
+        break;
+    case (3):
+        RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE);    // SPI3 is using DMA 2
+        DMA_InitStructure.DMA_PeripheralBaseAddr  = (uint32_t) &(SPI3->DR);
+        break;
+    }
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+    DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+    DMA_InitStructure.DMA_BufferSize  = 0;
+    DMA_InitStructure.DMA_PeripheralInc  = DMA_PeripheralInc_Disable;
+    DMA_InitStructure.DMA_PeripheralDataSize  = DMA_PeripheralDataSize_HalfWord;
+    DMA_InitStructure.DMA_MemoryDataSize  = DMA_MemoryDataSize_HalfWord;
+    DMA_InitStructure.DMA_Mode  = DMA_Mode_Normal;
+    DMA_InitStructure.DMA_Priority  = DMA_Priority_High;
+ }
+
+
+// speed optimized
+// write direct to SPI1 register !
+void SPI_TFT_ILI9341::pixel(int x, int y, int color)
+{
+    wr_cmd(0x2A);
+    spi_16(1);         // switch to 8 bit Mode
+    f_write(x);
+    spi_bsy();
+    _cs = 1;
+
+    spi_16(0);        // switch to 8 bit Mode
+    wr_cmd(0x2B);
+    spi_16(1);
+    f_write(y);
+    spi_bsy();
+    _cs = 1;
+    spi_16(0);
+
+    wr_cmd(0x2C); // send pixel
+    spi_16(1);
+    f_write(color);
+    spi_bsy();
+    _cs = 1;
+    spi_16(0);
+}
+
+// optimized
+// write direct to SPI1 register !
+void SPI_TFT_ILI9341::window (unsigned int x, unsigned int y, unsigned int w, unsigned int h)
+{
+    wr_cmd(0x2A);
+    spi_16(1);
+    f_write(x);
+    f_write(x+w-1);
+    spi_bsy();
+    _cs = 1;
+    spi_16(0);
+
+    wr_cmd(0x2B);
+    spi_16(1);
+    f_write(y) ;
+    f_write(y+h-1);
+    spi_bsy();
+    _cs = 1;
+    spi_16(0);
+}
+
+
+void SPI_TFT_ILI9341::WindowMax (void)
+{
+    window (0, 0, width(),  height());
+}
+
+// optimized
+// use DMA to transfer pixel data to the screen
+void SPI_TFT_ILI9341::cls (void)
+{
+    // we can use the fillrect function 
+   fillrect(0,0,width()-1,height()-1,_background);
+}    
+
+void SPI_TFT_ILI9341::circle(int x0, int y0, int r, int color)
+{
+
+    int x = -r, y = 0, err = 2-2*r, e2;
+    do {
+        pixel(x0-x, y0+y,color);
+        pixel(x0+x, y0+y,color);
+        pixel(x0+x, y0-y,color);
+        pixel(x0-x, y0-y,color);
+        e2 = err;
+        if (e2 <= y) {
+            err += ++y*2+1;
+            if (-x == y && e2 <= x) e2 = 0;
+        }
+        if (e2 > x) err += ++x*2+1;
+    } while (x <= 0);
+}
+
+void SPI_TFT_ILI9341::fillcircle(int x0, int y0, int r, int color)
+{
+    int x = -r, y = 0, err = 2-2*r, e2;
+    do {
+        vline(x0-x, y0-y, y0+y, color);
+        vline(x0+x, y0-y, y0+y, color);
+        e2 = err;
+        if (e2 <= y) {
+            err += ++y*2+1;
+            if (-x == y && e2 <= x) e2 = 0;
+        }
+        if (e2 > x) err += ++x*2+1;
+    } while (x <= 0);
+}
+
+
+// optimized for speed
+void SPI_TFT_ILI9341::hline(int x0, int x1, int y, int color)
+{
+    int w,j;
+    w = x1 - x0 + 1;
+    window(x0,y,w,1);
+    _dc = 0;
+    _cs = 0;
+    f_write(0x2C); // send pixel
+    spi_bsy();
+    _dc = 1;
+    spi_16(1);
+
+    for (j=0; j<w; j++) {
+        f_write(color);
+    }
+    spi_bsy();
+    spi_16(0);
+    _cs = 1;
+    WindowMax();
+    return;
+}
+
+// optimized for speed
+void SPI_TFT_ILI9341::vline(int x, int y0, int y1, int color)
+{
+    int h,y;
+    h = y1 - y0 + 1;
+    window(x,y0,1,h);
+    _dc = 0;
+    _cs = 0;
+    f_write(0x2C); // send pixel
+    spi_bsy();
+    _dc = 1;
+    spi_16(1);
+                // switch to 16 bit Mode 3
+    for (y=0; y<h; y++) {
+        f_write(color);
+    }
+    spi_bsy();
+    spi_16(0);
+    _cs = 1;
+    WindowMax();
+    return;
+}
+
+
+void SPI_TFT_ILI9341::line(int x0, int y0, int x1, int y1, int color)
+{
+    //WindowMax();
+    int   dx = 0, dy = 0;
+    int   dx_sym = 0, dy_sym = 0;
+    int   dx_x2 = 0, dy_x2 = 0;
+    int   di = 0;
+
+    dx = x1-x0;
+    dy = y1-y0;
+
+    if (dx == 0) {        /* vertical line */
+        if (y1 > y0) vline(x0,y0,y1,color);
+        else vline(x0,y1,y0,color);
+        return;
+    }
+
+    if (dx > 0) {
+        dx_sym = 1;
+    } else {
+        dx_sym = -1;
+    }
+    if (dy == 0) {        /* horizontal line */
+        if (x1 > x0) hline(x0,x1,y0,color);
+        else  hline(x1,x0,y0,color);
+        return;
+    }
+
+    if (dy > 0) {
+        dy_sym = 1;
+    } else {
+        dy_sym = -1;
+    }
+
+    dx = dx_sym*dx;
+    dy = dy_sym*dy;
+
+    dx_x2 = dx*2;
+    dy_x2 = dy*2;
+
+    if (dx >= dy) {
+        di = dy_x2 - dx;
+        while (x0 != x1) {
+
+            pixel(x0, y0, color);
+            x0 += dx_sym;
+            if (di<0) {
+                di += dy_x2;
+            } else {
+                di += dy_x2 - dx_x2;
+                y0 += dy_sym;
+            }
+        }
+        pixel(x0, y0, color);
+    } else {
+        di = dx_x2 - dy;
+        while (y0 != y1) {
+            pixel(x0, y0, color);
+            y0 += dy_sym;
+            if (di < 0) {
+                di += dx_x2;
+            } else {
+                di += dx_x2 - dy_x2;
+                x0 += dx_sym;
+            }
+        }
+        pixel(x0, y0, color);
+    }
+    return;
+}
+
+
+void SPI_TFT_ILI9341::rect(int x0, int y0, int x1, int y1, int color)
+{
+
+    if (x1 > x0) hline(x0,x1,y0,color);
+    else  hline(x1,x0,y0,color);
+
+    if (y1 > y0) vline(x0,y0,y1,color);
+    else vline(x0,y1,y0,color);
+
+    if (x1 > x0) hline(x0,x1,y1,color);
+    else  hline(x1,x0,y1,color);
+
+    if (y1 > y0) vline(x1,y0,y1,color);
+    else vline(x1,y1,y0,color);
+
+    return;
+}
+
+
+
+// optimized for speed
+// use DMA
+void SPI_TFT_ILI9341::fillrect(int x0, int y0, int x1, int y1, int color)
+{
+
+    int h = y1 - y0 + 1;
+    int w = x1 - x0 + 1;
+    int pixel = h * w;
+    unsigned int dma_transfer;
+    window(x0,y0,w,h);
+
+    wr_cmd(0x2C);  // send pixel
+    spi_16(1);
+    DMA_InitStructure.DMA_MemoryBaseAddr  = (uint32_t) &color;
+    DMA_InitStructure.DMA_MemoryInc  = DMA_MemoryInc_Disable;
+
+    switch(spi_num){        // decide which SPI is to use
+    case (1):
+        DMA_Init(DMA1_Channel3, &DMA_InitStructure);  // init the DMA
+        do{
+            if(pixel < 0x10000) {
+                dma_transfer = pixel;
+                pixel = 0;
+            }
+            else {
+                dma_transfer = 0xffff;
+                pixel = pixel - 0xffff;
+            }
+            DMA_SetCurrDataCounter(DMA1_Channel3, dma_transfer);
+            SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Tx,ENABLE);
+            DMA_Cmd(DMA1_Channel3, ENABLE);
+            while(DMA_GetCurrDataCounter(DMA1_Channel3) != 0);     // wait for end of transfer
+            DMA_Cmd(DMA1_Channel3, DISABLE);
+        }while(pixel > 0);
+        break;
+
+    case (2):
+        DMA_Init(DMA1_Channel5, &DMA_InitStructure);  // init the DMA
+        do{
+            if(pixel < 0x10000) {
+                dma_transfer = pixel;
+                pixel = 0;
+            }
+            else {
+                dma_transfer = 0xffff;
+                pixel = pixel - 0xffff;
+            }
+            DMA_SetCurrDataCounter(DMA1_Channel5, dma_transfer);
+            SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx,ENABLE);
+            DMA_Cmd(DMA1_Channel5, ENABLE);
+            while(DMA_GetCurrDataCounter(DMA1_Channel5) != 0);     // wait for end of transfer
+            DMA_Cmd(DMA1_Channel5, DISABLE);
+        }while(pixel > 0);
+        break;
+
+    case (3):
+        DMA_Init(DMA2_Channel2, &DMA_InitStructure);  // init the DMA
+        do{
+            if(pixel < 0x10000) {
+                dma_transfer = pixel;
+                pixel = 0;
+            }
+            else {
+                dma_transfer = 0xffff;
+                pixel = pixel - 0xffff;
+            }
+            DMA_SetCurrDataCounter(DMA2_Channel2, dma_transfer);
+            SPI_I2S_DMACmd(SPI3, SPI_I2S_DMAReq_Tx,ENABLE);
+            DMA_Cmd(DMA2_Channel2, ENABLE);
+            while(DMA_GetCurrDataCounter(DMA2_Channel2) != 0);     // wait for end of transfer
+            DMA_Cmd(DMA2_Channel2, DISABLE);
+        }while(pixel > 0);
+        break;
+    }
+    spi_bsy();
+    spi_16(0);
+    _cs = 1;
+    WindowMax();
+    return;
+}
+
+void SPI_TFT_ILI9341::locate(int x, int y)
+{
+    char_x = x;
+    char_y = y;
+}
+
+int SPI_TFT_ILI9341::columns()
+{
+    return width() / font[1];
+}
+
+
+int SPI_TFT_ILI9341::rows()
+{
+    return height() / font[2];
+}
+
+
+int SPI_TFT_ILI9341::_putc(int value)
+{
+    if (value == '\n') {    // new line
+        char_x = 0;
+        char_y = char_y + font[2];
+        if (char_y >= height() - font[2]) {
+            char_y = 0;
+        }
+    } else {
+        character(char_x, char_y, value);
+    }
+    return value;
+}
+
+
+// speed optimized
+// will use dma
+void SPI_TFT_ILI9341::character(int x, int y, int c)
+{
+    unsigned int hor,vert,offset,bpl,j,i,b;
+    unsigned char* zeichen;
+    unsigned char z,w;
+    #ifdef use_ram
+    unsigned int pixel;
+    unsigned int p;
+    unsigned int dma_count,dma_off;
+    uint16_t *buffer;
+    #endif
+
+    if ((c < 31) || (c > 127)) return;   // test char range
+
+    // read font parameter from start of array
+    offset = font[0];                    // bytes / char
+    hor = font[1];                       // get hor size of font
+    vert = font[2];                      // get vert size of font
+    bpl = font[3];                       // bytes per line
+
+    if (char_x + hor > width()) {
+        char_x = 0;
+        char_y = char_y + vert;
+        if (char_y >= height() - font[2]) {
+            char_y = 0;
+        }
+    }
+    window(char_x, char_y,hor,vert);           // setup char box
+    wr_cmd(0x2C);
+    spi_16(1);                                 // switch to 16 bit Mode
+    #ifdef use_ram
+    pixel = hor * vert;                        // calculate buffer size
+    buffer = (uint16_t *) malloc (2*pixel);    // we need a buffer for the font
+    if(buffer != NULL) {                       // there is memory space -> use dma
+        zeichen = &font[((c -32) * offset) + 4]; // start of char bitmap
+        w = zeichen[0];                          // width of actual char
+        p = 0;
+        // construct the font into the buffer
+        for (j=0; j<vert; j++) {            //  vert line
+            for (i=0; i<hor; i++) {         //  horz line
+                z =  zeichen[bpl * i + ((j & 0xF8) >> 3)+1];
+                b = 1 << (j & 0x07);
+                if (( z & b ) == 0x00) {
+                    buffer[p] = _background;
+                } else {
+                    buffer[p] = _foreground;
+                }
+                p++;
+            }
+        }
+        // copy the buffer with DMA SPI to display
+        dma_off = 0;  // offset for DMA transfer
+        DMA_InitStructure.DMA_MemoryBaseAddr  = (uint32_t)  (buffer + dma_off);
+        DMA_InitStructure.DMA_MemoryInc  = DMA_MemoryInc_Enable;
+
+        switch(spi_num){        // decide which SPI is to use
+        case (1):
+        DMA_Init(DMA1_Channel3, &DMA_InitStructure);  // init the DMA
+        // start DMA
+         do {
+            if (pixel > 0X10000) {         // this is a giant font !
+                dma_count = 0Xffff;
+                pixel = pixel - 0Xffff;
+            } else {
+                dma_count = pixel;
+                pixel = 0;
+            }
+            DMA_SetCurrDataCounter(DMA1_Channel3, dma_count);
+            SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Tx,ENABLE);
+            DMA_Cmd(DMA1_Channel3, ENABLE);
+            while(DMA_GetCurrDataCounter(DMA1_Channel3) != 0);     // wait for end of transfer
+            DMA_Cmd(DMA1_Channel3, DISABLE);
+        }while(pixel > 0);
+        break;
+
+        case (2):
+        DMA_Init(DMA1_Channel5, &DMA_InitStructure);  // init the DMA
+        // start DMA
+         do {
+            if (pixel > 0X10000) {         // this is a giant font !
+                dma_count = 0Xffff;
+                pixel = pixel - 0Xffff;
+            } else {
+                dma_count = pixel;
+                pixel = 0;
+            }
+            DMA_SetCurrDataCounter(DMA1_Channel5, dma_count);
+            SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx,ENABLE);
+            DMA_Cmd(DMA1_Channel5, ENABLE);
+            while(DMA_GetCurrDataCounter(DMA1_Channel5) != 0);     // wait for end of transfer
+            DMA_Cmd(DMA1_Channel5, DISABLE);
+        }while(pixel > 0);
+        break;
+
+        case (3):
+        DMA_Init(DMA2_Channel2, &DMA_InitStructure);  // init the DMA
+        // start DMA
+         do {
+            if (pixel > 0X10000) {         // this is a giant font !
+                dma_count = 0Xffff;
+                pixel = pixel - 0Xffff;
+            } else {
+                dma_count = pixel;
+                pixel = 0;
+            }
+            DMA_SetCurrDataCounter(DMA2_Channel2, dma_count);
+            SPI_I2S_DMACmd(SPI3, SPI_I2S_DMAReq_Tx,ENABLE);
+            DMA_Cmd(DMA2_Channel2, ENABLE);
+            while(DMA_GetCurrDataCounter(DMA2_Channel2) != 0);     // wait for end of transfer
+            DMA_Cmd(DMA2_Channel2, DISABLE);
+        }while(pixel > 0);
+        break;
+
+        }
+        spi_bsy();
+        free ((uint16_t *) buffer);
+        spi_16(0);
+    }
+    
+    else{
+        #endif
+        zeichen = &font[((c -32) * offset) + 4]; // start of char bitmap
+        w = zeichen[0];                          // width of actual char
+        for (j=0; j<vert; j++) {  //  vert line
+            for (i=0; i<hor; i++) {   //  horz line
+                z =  zeichen[bpl * i + ((j & 0xF8) >> 3)+1];
+                b = 1 << (j & 0x07);
+                if (( z & b ) == 0x00) {
+                  f_write(_background);
+                } else {
+                  f_write(_foreground);
+                }
+            }
+        }
+        spi_bsy();
+        _cs = 1;
+        spi_16(0);
+    #ifdef use_ram   
+    }
+    #endif    
+    _cs = 1;
+    WindowMax();
+    if ((w + 2) < hor) {                   // x offset to next char
+        char_x += w + 2;
+    } else char_x += hor;
+}
+
+
+void SPI_TFT_ILI9341::set_font(unsigned char* f)
+{
+    font = f;
+}
+
+
+void SPI_TFT_ILI9341::Bitmap(unsigned int x, unsigned int y, unsigned int w, unsigned int h,unsigned char *bitmap)
+{
+    unsigned int  j;
+    int padd;
+    unsigned short *bitmap_ptr = (unsigned short *)bitmap;
+
+    unsigned int i;
+
+    // the lines are padded to multiple of 4 bytes in a bitmap
+    padd = -1;
+    do {
+        padd ++;
+    } while (2*(w + padd)%4 != 0);
+    window(x, y, w, h);
+    bitmap_ptr += ((h - 1)* (w + padd));
+    wr_cmd(0x2C);  // send pixel
+    spi_16(1);
+    for (j = 0; j < h; j++) {         //Lines
+        for (i = 0; i < w; i++) {     // one line
+                f_write(*bitmap_ptr);    // one line
+                bitmap_ptr++;
+        }
+        bitmap_ptr -= 2*w;
+        bitmap_ptr -= padd;
+    }
+    spi_bsy();
+    _cs = 1;
+    spi_16(0);
+    WindowMax();
+}
+
+
+// local filesystem is not implemented but you can add a SD card to a different SPI
+
+int SPI_TFT_ILI9341::BMP_16(unsigned int x, unsigned int y, const char *Name_BMP)
+{
+
+#define OffsetPixelWidth    18
+#define OffsetPixelHeigh    22
+#define OffsetFileSize      34
+#define OffsetPixData       10
+#define OffsetBPP           28
+
+    char filename[50];
+    unsigned char BMP_Header[54];
+    unsigned short BPP_t;
+    unsigned int PixelWidth,PixelHeigh,start_data;
+    unsigned int    i,off;
+    int padd,j;
+    unsigned short *line;
+
+    // get the filename
+    i=0;
+    while (*Name_BMP!='\0') {
+        filename[i++]=*Name_BMP++;
+    }
+    filename[i] = 0;
+
+    FILE *Image = fopen((const char *)&filename[0], "rb");  // open the bmp file
+    if (!Image) {
+        return(0);      // error file not found !
+    }
+
+    fread(&BMP_Header[0],1,54,Image);      // get the BMP Header
+
+    if (BMP_Header[0] != 0x42 || BMP_Header[1] != 0x4D) {  // check magic byte
+        fclose(Image);
+        return(-1);     // error no BMP file
+    }
+
+    BPP_t = BMP_Header[OffsetBPP] + (BMP_Header[OffsetBPP + 1] << 8);
+    if (BPP_t != 0x0010) {
+        fclose(Image);
+        return(-2);     // error no 16 bit BMP
+    }
+
+    PixelHeigh = BMP_Header[OffsetPixelHeigh] + (BMP_Header[OffsetPixelHeigh + 1] << 8) + (BMP_Header[OffsetPixelHeigh + 2] << 16) + (BMP_Header[OffsetPixelHeigh + 3] << 24);
+    PixelWidth = BMP_Header[OffsetPixelWidth] + (BMP_Header[OffsetPixelWidth + 1] << 8) + (BMP_Header[OffsetPixelWidth + 2] << 16) + (BMP_Header[OffsetPixelWidth + 3] << 24);
+    if (PixelHeigh > height() + y || PixelWidth > width() + x) {
+        fclose(Image);
+        return(-3);      // to big
+    }
+
+    start_data = BMP_Header[OffsetPixData] + (BMP_Header[OffsetPixData + 1] << 8) + (BMP_Header[OffsetPixData + 2] << 16) + (BMP_Header[OffsetPixData + 3] << 24);
+
+    line = (unsigned short *) malloc (2 * PixelWidth); // we need a buffer for a line
+    if (line == NULL) {
+        return(-4);         // error no memory
+    }
+
+    // the bmp lines are padded to multiple of 4 bytes
+    padd = -1;
+    do {
+        padd ++;
+    } while ((PixelWidth * 2 + padd)%4 != 0);
+
+    window(x, y,PixelWidth ,PixelHeigh);
+    wr_cmd(0x2C);  // send pixel
+    spi_16(1);
+    for (j = PixelHeigh - 1; j >= 0; j--) {               //Lines bottom up
+        off = j * (PixelWidth  * 2 + padd) + start_data;   // start of line
+        fseek(Image, off ,SEEK_SET);
+        fread(line,1,PixelWidth * 2,Image);       // read a line - slow
+        for (i = 0; i < PixelWidth; i++) {        // copy pixel data to TFT
+            f_write(line[i]);                  // one 16 bit pixel
+        }
+     }
+    spi_bsy();
+    _cs = 1;
+    spi_16(0);
+    free (line);
+    fclose(Image);
+    WindowMax();
+    return(1);
+}
+
+#endif
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ILI9341/SPI_TFT_ILI9341_NXP.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,915 @@
+/* mbed library for 240*320 pixel display TFT based on ILI9341 LCD Controller
+ * Copyright (c) 2014 Peter Drescher - DC2PD
+ * Special version for NXP LPC1768
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+// 25.06.14   initial version
+
+// only include this file if target is LPC1768
+#if defined TARGET_LPC1768
+
+#include "SPI_TFT_ILI9341.h"
+#include "mbed.h"
+
+#if defined TARGET_LPC1768
+#define use_ram
+#endif
+
+// some defines for the DMA use
+#define DMA_CHANNEL_ENABLE      1
+#define DMA_TRANSFER_TYPE_M2P   (1UL << 11)
+#define DMA_CHANNEL_TCIE        (1UL << 31)
+#define DMA_CHANNEL_SRC_INC     (1UL << 26)
+#define DMA_MASK_IE             (1UL << 14)
+#define DMA_MASK_ITC            (1UL << 15)
+#define DMA_SSP1_TX             (1UL << 2)
+#define DMA_SSP0_TX             (0)
+#define DMA_DEST_SSP1_TX        (2UL << 6)
+#define DMA_DEST_SSP0_TX        (0UL << 6)
+
+#define BPP         16                  // Bits per pixel
+
+//extern Serial pc;
+//extern DigitalOut xx;     // debug !!
+
+
+SPI_TFT_ILI9341::SPI_TFT_ILI9341(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset, PinName dc, const char *name)
+    : GraphicsDisplay(name), SPI(mosi,miso,sclk), _cs(cs), _reset(reset), _dc(dc)
+{
+
+    format(8,3);                 // 8 bit spi mode 3
+    frequency(10000000);         // 10 Mhz SPI clock : result 2 / 4 = 8
+    orientation = 0;
+    char_x = 0;
+    if((int)_spi.spi == SPI_0) {      // test which SPI is in use
+        spi_num = 0;
+    }
+    if((int)_spi.spi == SPI_1) {
+        spi_num = 1;
+    }
+    tft_reset();
+}
+
+// we define a fast write to the SPI port
+void inline SPI_TFT_ILI9341::f_write(int data)
+{
+    while(((_spi.spi->SR) & 0x02) == 0);
+    _spi.spi->DR = data;
+}
+
+// wait for SPI not busy
+// we have to wait for the last bit to switch the cs off
+void inline SPI_TFT_ILI9341::spi_bsy(void)
+{
+    while ((_spi.spi->SR & 0x10) == 0x10);       // SPI not idle
+}
+
+
+// switch fast between 8 and 16 bit mode
+void SPI_TFT_ILI9341::spi_16(bool s)
+{
+    if(s) _spi.spi->CR0 |= 0x08;  // switch to 16 bit Mode
+    else  _spi.spi->CR0 &= ~(0x08);  // switch to 8  bit Mode
+
+}
+
+
+int SPI_TFT_ILI9341::width()
+{
+    if (orientation == 0 || orientation == 2) return 240;
+    else return 320;
+}
+
+
+int SPI_TFT_ILI9341::height()
+{
+    if (orientation == 0 || orientation == 2) return 320;
+    else return 240;
+}
+
+
+void SPI_TFT_ILI9341::set_orientation(unsigned int o)
+{
+    orientation = o;
+    wr_cmd(0x36);                     // MEMORY_ACCESS_CONTROL
+    switch (orientation) {
+        case 0:
+            f_write(0x48);
+            break;
+        case 1:
+            f_write(0x28);
+            break;
+        case 2:
+            f_write(0x88);
+            break;
+        case 3:
+            f_write(0xE8);
+            break;
+    }
+    spi_bsy();    // wait for end of transfer
+    _cs = 1;
+    WindowMax();
+}
+
+
+// write command to tft register
+// use fast command
+void SPI_TFT_ILI9341::wr_cmd(unsigned char cmd)
+{
+    _dc = 0;
+    _cs = 0;
+    f_write(cmd);
+    spi_bsy();
+    _dc = 1;
+}
+
+void SPI_TFT_ILI9341::wr_dat(unsigned char dat)
+{
+    f_write(dat);
+    spi_bsy();  // wait for SPI send
+}
+
+// the ILI9341 can read
+char SPI_TFT_ILI9341::rd_byte(unsigned char cmd)
+{
+    // has to change !!
+    return(0);
+}
+
+// read 32 bit
+int SPI_TFT_ILI9341::rd_32(unsigned char cmd)
+{
+    // has to change !!!
+    return(0);
+}
+
+int  SPI_TFT_ILI9341::Read_ID(void)
+{
+    int r;
+    r = rd_byte(0x0A);
+    r = rd_byte(0x0A);
+    r = rd_byte(0x0A);
+    r = rd_byte(0x0A);
+    return(r);
+}
+
+
+// Init code based on MI0283QT datasheet
+// this code is called only at start
+// no need to be optimized
+
+void SPI_TFT_ILI9341::tft_reset()
+{
+    _cs = 1;                           // cs high
+    _dc = 1;                           // dc high
+    _reset = 0;                        // display reset
+
+    wait_us(50);
+    _reset = 1;                       // end hardware reset
+    wait_ms(5);
+
+    wr_cmd(0x01);                     // SW reset
+    wait_ms(5);
+    wr_cmd(0x28);                     // display off
+
+    /* Start Initial Sequence ----------------------------------------------------*/
+    wr_cmd(0xCF);
+    f_write(0x00);
+    f_write(0x83);
+    f_write(0x30);
+    spi_bsy();
+    _cs = 1;
+
+    wr_cmd(0xED);
+    f_write(0x64);
+    f_write(0x03);
+    f_write(0x12);
+    f_write(0x81);
+    spi_bsy();
+    _cs = 1;
+
+    wr_cmd(0xE8);
+    f_write(0x85);
+    f_write(0x01);
+    f_write(0x79);
+    spi_bsy();
+    _cs = 1;
+
+    wr_cmd(0xCB);
+    f_write(0x39);
+    f_write(0x2C);
+    f_write(0x00);
+    f_write(0x34);
+    f_write(0x02);
+    spi_bsy();
+    _cs = 1;
+
+    wr_cmd(0xF7);
+    f_write(0x20);
+    spi_bsy();
+    _cs = 1;
+
+    wr_cmd(0xEA);
+    f_write(0x00);
+    f_write(0x00);
+    spi_bsy();
+    _cs = 1;
+
+    wr_cmd(0xC0);                     // POWER_CONTROL_1
+    f_write(0x26);
+    spi_bsy();
+    _cs = 1;
+
+    wr_cmd(0xC1);                     // POWER_CONTROL_2
+    f_write(0x11);
+    spi_bsy();
+    _cs = 1;
+
+    wr_cmd(0xC5);                     // VCOM_CONTROL_1
+    f_write(0x35);
+    f_write(0x3E);
+    spi_bsy();
+    _cs = 1;
+
+    wr_cmd(0xC7);                     // VCOM_CONTROL_2
+    f_write(0xBE);
+    spi_bsy();
+    _cs = 1;
+
+    wr_cmd(0x36);                     // MEMORY_ACCESS_CONTROL
+    f_write(0x48);
+    spi_bsy();
+    _cs = 1;
+
+    wr_cmd(0x3A);                     // COLMOD_PIXEL_FORMAT_SET
+    f_write(0x55);                 // 16 bit pixel
+    spi_bsy();
+    _cs = 1;
+
+    wr_cmd(0xB1);                     // Frame Rate
+    f_write(0x00);
+    f_write(0x1B);
+    spi_bsy();
+    _cs = 1;
+
+    wr_cmd(0xF2);                     // Gamma Function Disable
+    f_write(0x08);
+    spi_bsy();
+    _cs = 1;
+
+    wr_cmd(0x26);
+    f_write(0x01);                 // gamma set for curve 01/2/04/08
+    spi_bsy();
+    _cs = 1;
+
+    wr_cmd(0xE0);                     // positive gamma correction
+    f_write(0x1F);
+    f_write(0x1A);
+    f_write(0x18);
+    f_write(0x0A);
+    f_write(0x0F);
+    f_write(0x06);
+    f_write(0x45);
+    f_write(0x87);
+    f_write(0x32);
+    f_write(0x0A);
+    f_write(0x07);
+    f_write(0x02);
+    f_write(0x07);
+    f_write(0x05);
+    f_write(0x00);
+    spi_bsy();
+    _cs = 1;
+
+    wr_cmd(0xE1);                     // negativ gamma correction
+    f_write(0x00);
+    f_write(0x25);
+    f_write(0x27);
+    f_write(0x05);
+    f_write(0x10);
+    f_write(0x09);
+    f_write(0x3A);
+    f_write(0x78);
+    f_write(0x4D);
+    f_write(0x05);
+    f_write(0x18);
+    f_write(0x0D);
+    f_write(0x38);
+    f_write(0x3A);
+    f_write(0x1F);
+    spi_bsy();
+    _cs = 1;
+
+    WindowMax ();
+
+    //wr_cmd(0x34);                     // tearing effect off
+    //_cs = 1;
+
+    //wr_cmd(0x35);                     // tearing effect on
+    //_cs = 1;
+
+    wr_cmd(0xB7);                       // entry mode
+    f_write(0x07);
+    spi_bsy();
+    _cs = 1;
+
+    wr_cmd(0xB6);                       // display function control
+    f_write(0x0A);
+    f_write(0x82);
+    f_write(0x27);
+    f_write(0x00);
+    spi_bsy();
+    _cs = 1;
+
+    wr_cmd(0x11);                     // sleep out
+    spi_bsy();
+    _cs = 1;
+
+    wait_ms(100);
+
+    wr_cmd(0x29);                     // display on
+    spi_bsy();
+    _cs = 1;
+
+    wait_ms(100);
+
+    // setup DMA channel 0
+    LPC_SC->PCONP |= (1UL << 29);       // Power up the GPDMA.
+    LPC_GPDMA->DMACConfig = 1;          // enable DMA controller
+    LPC_GPDMA->DMACIntTCClear = 0x1;    // Reset the Interrupt status
+    LPC_GPDMA->DMACIntErrClr = 0x1;
+    LPC_GPDMACH0->DMACCLLI   = 0;
+}
+
+
+// speed optimized
+// write direct to SPI1 register !
+void SPI_TFT_ILI9341::pixel(int x, int y, int color)
+{
+    wr_cmd(0x2A);
+    spi_16(1);         // switch to 8 bit Mode
+    f_write(x);
+    spi_bsy();
+    _cs = 1;
+
+    spi_16(0);        // switch to 8 bit Mode
+    wr_cmd(0x2B);
+    spi_16(1);
+    f_write(y);
+    spi_bsy();
+    _cs = 1;
+    spi_16(0);
+
+    wr_cmd(0x2C); // send pixel
+    spi_16(1);
+    f_write(color);
+    spi_bsy();
+    _cs = 1;
+    spi_16(0);
+}
+
+// optimized
+// write direct to SPI1 register !
+void SPI_TFT_ILI9341::window (unsigned int x, unsigned int y, unsigned int w, unsigned int h)
+{
+    wr_cmd(0x2A);
+    spi_16(1);
+    f_write(x);
+    f_write(x+w-1);
+    spi_bsy();
+    _cs = 1;
+    spi_16(0);
+
+    wr_cmd(0x2B);
+    spi_16(1);
+    f_write(y) ;
+    f_write(y+h-1);
+    spi_bsy();
+    _cs = 1;
+    spi_16(0);
+}
+
+
+void SPI_TFT_ILI9341::WindowMax (void)
+{
+    window (0, 0, width(),  height());
+}
+
+// optimized
+// use DMA to transfer pixel data to the screen
+void SPI_TFT_ILI9341::cls (void)
+{
+    // we can use the fillrect function
+    fillrect(0,0,width()-1,height()-1,_background);
+}
+
+void SPI_TFT_ILI9341::circle(int x0, int y0, int r, int color)
+{
+
+    int x = -r, y = 0, err = 2-2*r, e2;
+    do {
+        pixel(x0-x, y0+y,color);
+        pixel(x0+x, y0+y,color);
+        pixel(x0+x, y0-y,color);
+        pixel(x0-x, y0-y,color);
+        e2 = err;
+        if (e2 <= y) {
+            err += ++y*2+1;
+            if (-x == y && e2 <= x) e2 = 0;
+        }
+        if (e2 > x) err += ++x*2+1;
+    } while (x <= 0);
+}
+
+void SPI_TFT_ILI9341::fillcircle(int x0, int y0, int r, int color)
+{
+    int x = -r, y = 0, err = 2-2*r, e2;
+    do {
+        vline(x0-x, y0-y, y0+y, color);
+        vline(x0+x, y0-y, y0+y, color);
+        e2 = err;
+        if (e2 <= y) {
+            err += ++y*2+1;
+            if (-x == y && e2 <= x) e2 = 0;
+        }
+        if (e2 > x) err += ++x*2+1;
+    } while (x <= 0);
+}
+
+
+// optimized for speed
+void SPI_TFT_ILI9341::hline(int x0, int x1, int y, int color)
+{
+    int w,j;
+    w = x1 - x0 + 1;
+    window(x0,y,w,1);
+    _dc = 0;
+    _cs = 0;
+    f_write(0x2C); // send pixel
+    spi_bsy();
+    _dc = 1;
+    spi_16(1);
+
+    for (j=0; j<w; j++) {
+        f_write(color);
+    }
+    spi_bsy();
+    spi_16(0);
+    _cs = 1;
+    WindowMax();
+    return;
+}
+
+// optimized for speed
+void SPI_TFT_ILI9341::vline(int x, int y0, int y1, int color)
+{
+    int h,y;
+    h = y1 - y0 + 1;
+    window(x,y0,1,h);
+    _dc = 0;
+    _cs = 0;
+    f_write(0x2C); // send pixel
+    spi_bsy();
+    _dc = 1;
+    spi_16(1);
+    // switch to 16 bit Mode 3
+    for (y=0; y<h; y++) {
+        f_write(color);
+    }
+    spi_bsy();
+    spi_16(0);
+    _cs = 1;
+    WindowMax();
+    return;
+}
+
+
+void SPI_TFT_ILI9341::line(int x0, int y0, int x1, int y1, int color)
+{
+    //WindowMax();
+    int   dx = 0, dy = 0;
+    int   dx_sym = 0, dy_sym = 0;
+    int   dx_x2 = 0, dy_x2 = 0;
+    int   di = 0;
+
+    dx = x1-x0;
+    dy = y1-y0;
+
+    if (dx == 0) {        /* vertical line */
+        if (y1 > y0) vline(x0,y0,y1,color);
+        else vline(x0,y1,y0,color);
+        return;
+    }
+
+    if (dx > 0) {
+        dx_sym = 1;
+    } else {
+        dx_sym = -1;
+    }
+    if (dy == 0) {        /* horizontal line */
+        if (x1 > x0) hline(x0,x1,y0,color);
+        else  hline(x1,x0,y0,color);
+        return;
+    }
+
+    if (dy > 0) {
+        dy_sym = 1;
+    } else {
+        dy_sym = -1;
+    }
+
+    dx = dx_sym*dx;
+    dy = dy_sym*dy;
+
+    dx_x2 = dx*2;
+    dy_x2 = dy*2;
+
+    if (dx >= dy) {
+        di = dy_x2 - dx;
+        while (x0 != x1) {
+
+            pixel(x0, y0, color);
+            x0 += dx_sym;
+            if (di<0) {
+                di += dy_x2;
+            } else {
+                di += dy_x2 - dx_x2;
+                y0 += dy_sym;
+            }
+        }
+        pixel(x0, y0, color);
+    } else {
+        di = dx_x2 - dy;
+        while (y0 != y1) {
+            pixel(x0, y0, color);
+            y0 += dy_sym;
+            if (di < 0) {
+                di += dx_x2;
+            } else {
+                di += dx_x2 - dy_x2;
+                x0 += dx_sym;
+            }
+        }
+        pixel(x0, y0, color);
+    }
+    return;
+}
+
+
+void SPI_TFT_ILI9341::rect(int x0, int y0, int x1, int y1, int color)
+{
+
+    if (x1 > x0) hline(x0,x1,y0,color);
+    else  hline(x1,x0,y0,color);
+
+    if (y1 > y0) vline(x0,y0,y1,color);
+    else vline(x0,y1,y0,color);
+
+    if (x1 > x0) hline(x0,x1,y1,color);
+    else  hline(x1,x0,y1,color);
+
+    if (y1 > y0) vline(x1,y0,y1,color);
+    else vline(x1,y1,y0,color);
+
+    return;
+}
+
+
+
+// optimized for speed
+// use DMA
+void SPI_TFT_ILI9341::fillrect(int x0, int y0, int x1, int y1, int color)
+{
+    int h = y1 - y0 + 1;
+    int w = x1 - x0 + 1;
+    int pixel = h * w;
+    unsigned int dma_count;
+    window(x0,y0,w,h);
+
+    wr_cmd(0x2C);  // send pixel
+    spi_16(1);
+
+    LPC_GPDMACH0->DMACCSrcAddr = (uint32_t)&color;
+
+    switch(spi_num) {       // decide which SPI is to use
+        case (0):
+            LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP0->DR; // we send to SSP0
+            LPC_SSP0->DMACR = 0x2;
+            break;
+        case (1):
+            LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP1->DR; // we send to SSP1
+            LPC_SSP1->DMACR = 0x2;
+            break;
+    }
+
+    // start DMA
+    do {
+        if (pixel > 4095) {
+            dma_count = 4095;
+            pixel = pixel - 4095;
+        } else {
+            dma_count = pixel;
+            pixel = 0;
+        }
+        LPC_GPDMA->DMACIntTCClear = 0x1;
+        LPC_GPDMA->DMACIntErrClr = 0x1;
+        LPC_GPDMACH0->DMACCControl = dma_count | (1UL << 18) | (1UL << 21) | (1UL << 31) ; // 16 bit transfer , no address increment, interrupt
+        LPC_GPDMACH0->DMACCConfig  = DMA_CHANNEL_ENABLE | DMA_TRANSFER_TYPE_M2P | (spi_num ? DMA_DEST_SSP1_TX : DMA_DEST_SSP0_TX);
+        LPC_GPDMA->DMACSoftSReq = 0x1;   // DMA request
+        do {
+        } while ((LPC_GPDMA->DMACRawIntTCStat & 0x01) == 0); // DMA is running
+    } while (pixel > 0);
+
+    spi_bsy();    // wait for end of transfer
+    spi_16(0);
+    _cs = 1;
+    WindowMax();
+    return;
+}
+
+void SPI_TFT_ILI9341::locate(int x, int y)
+{
+    char_x = x;
+    char_y = y;
+}
+
+int SPI_TFT_ILI9341::columns()
+{
+    return width() / font[1];
+}
+
+
+int SPI_TFT_ILI9341::rows()
+{
+    return height() / font[2];
+}
+
+
+int SPI_TFT_ILI9341::_putc(int value)
+{
+    if (value == '\n') {    // new line
+        char_x = 0;
+        char_y = char_y + font[2];
+        if (char_y >= height() - font[2]) {
+            char_y = 0;
+        }
+    } else {
+        character(char_x, char_y, value);
+    }
+    return value;
+}
+
+
+// speed optimized
+// will use dma
+void SPI_TFT_ILI9341::character(int x, int y, int c)
+{
+    unsigned int hor,vert,offset,bpl,j,i,b;
+    unsigned char* zeichen;
+    unsigned char z,w;
+#ifdef use_ram
+    unsigned int pixel;
+    unsigned int p;
+    unsigned int dma_count,dma_off;
+    uint16_t *buffer;
+#endif
+
+    if ((c < 31) || (c > 127)) return;   // test char range
+
+    // read font parameter from start of array
+    offset = font[0];                    // bytes / char
+    hor = font[1];                       // get hor size of font
+    vert = font[2];                      // get vert size of font
+    bpl = font[3];                       // bytes per line
+
+    if (char_x + hor > width()) {
+        char_x = 0;
+        char_y = char_y + vert;
+        if (char_y >= height() - font[2]) {
+            char_y = 0;
+        }
+    }
+    window(char_x, char_y,hor,vert);           // setup char box
+    wr_cmd(0x2C);
+    spi_16(1);                                 // switch to 16 bit Mode
+#ifdef use_ram
+    pixel = hor * vert;                        // calculate buffer size
+    buffer = (uint16_t *) malloc (2*pixel);    // we need a buffer for the font
+    if(buffer != NULL) {                       // there is memory space -> use dma
+        zeichen = &font[((c -32) * offset) + 4]; // start of char bitmap
+        w = zeichen[0];                          // width of actual char
+        p = 0;
+        // construct the font into the buffer
+        for (j=0; j<vert; j++) {            //  vert line
+            for (i=0; i<hor; i++) {         //  horz line
+                z =  zeichen[bpl * i + ((j & 0xF8) >> 3)+1];
+                b = 1 << (j & 0x07);
+                if (( z & b ) == 0x00) {
+                    buffer[p] = _background;
+                } else {
+                    buffer[p] = _foreground;
+                }
+                p++;
+            }
+        }
+        // copy the buffer with DMA SPI to display
+        dma_off = 0;  // offset for DMA transfer
+
+        switch(spi_num) {       // decide which SPI is to use
+            case (0):
+                LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP0->DR; // we send to SSP0
+                LPC_SSP0->DMACR = 0x2;
+                break;
+            case (1):
+                LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP1->DR; // we send to SSP1
+                LPC_SSP1->DMACR = 0x2;
+                break;
+        }
+        // start DMA
+        do {
+            if (pixel > 4095) {         // this is a giant font !
+                dma_count = 4095;
+                pixel = pixel - 4095;
+            } else {
+                dma_count = pixel;
+                pixel = 0;
+            }
+            LPC_GPDMA->DMACIntTCClear = 0x1;
+            LPC_GPDMA->DMACIntErrClr = 0x1;
+            LPC_GPDMACH0->DMACCSrcAddr = (uint32_t) (buffer + dma_off);
+            LPC_GPDMACH0->DMACCControl = dma_count | (1UL << 18) | (1UL << 21) | (1UL << 31) |  DMA_CHANNEL_SRC_INC ; // 16 bit transfer , address increment, interrupt
+            LPC_GPDMACH0->DMACCConfig  = DMA_CHANNEL_ENABLE | DMA_TRANSFER_TYPE_M2P | (spi_num ? DMA_DEST_SSP1_TX : DMA_DEST_SSP0_TX);
+            LPC_GPDMA->DMACSoftSReq = 0x1;
+            do {
+            } while ((LPC_GPDMA->DMACRawIntTCStat & 0x01) == 0); // DMA is running
+            dma_off = dma_off + dma_count;
+        } while (pixel > 0);
+
+
+        spi_bsy();
+        free ((uint16_t *) buffer);
+        spi_16(0);
+    }
+
+    else {
+#endif
+        zeichen = &font[((c -32) * offset) + 4]; // start of char bitmap
+        w = zeichen[0];                          // width of actual char
+        for (j=0; j<vert; j++) {  //  vert line
+            for (i=0; i<hor; i++) {   //  horz line
+                z =  zeichen[bpl * i + ((j & 0xF8) >> 3)+1];
+                b = 1 << (j & 0x07);
+                if (( z & b ) == 0x00) {
+                    f_write(_background);
+                } else {
+                    f_write(_foreground);
+                }
+            }
+        }
+        spi_bsy();
+        _cs = 1;
+        spi_16(0);
+#ifdef use_ram
+    }
+#endif
+    _cs = 1;
+    WindowMax();
+    if ((w + 2) < hor) {                   // x offset to next char
+        char_x += w + 2;
+    } else char_x += hor;
+}
+
+
+void SPI_TFT_ILI9341::set_font(unsigned char* f)
+{
+    font = f;
+}
+
+
+void SPI_TFT_ILI9341::Bitmap(unsigned int x, unsigned int y, unsigned int w, unsigned int h,unsigned char *bitmap)
+{
+    unsigned int  j;
+    int padd;
+    unsigned short *bitmap_ptr = (unsigned short *)bitmap;
+
+    unsigned int i;
+
+    // the lines are padded to multiple of 4 bytes in a bitmap
+    padd = -1;
+    do {
+        padd ++;
+    } while (2*(w + padd)%4 != 0);
+    window(x, y, w, h);
+    bitmap_ptr += ((h - 1)* (w + padd));
+    wr_cmd(0x2C);  // send pixel
+    spi_16(1);
+    for (j = 0; j < h; j++) {         //Lines
+        for (i = 0; i < w; i++) {     // one line
+            f_write(*bitmap_ptr);    // one line
+            bitmap_ptr++;
+        }
+        bitmap_ptr -= 2*w;
+        bitmap_ptr -= padd;
+    }
+    spi_bsy();
+    _cs = 1;
+    spi_16(0);
+    WindowMax();
+}
+
+
+// local filesystem is not implemented but you can add a SD card to a different SPI
+
+int SPI_TFT_ILI9341::BMP_16(unsigned int x, unsigned int y, const char *Name_BMP)
+{
+
+#define OffsetPixelWidth    18
+#define OffsetPixelHeigh    22
+#define OffsetFileSize      34
+#define OffsetPixData       10
+#define OffsetBPP           28
+
+    char filename[50];
+    unsigned char BMP_Header[54];
+    unsigned short BPP_t;
+    unsigned int PixelWidth,PixelHeigh,start_data;
+    unsigned int    i,off;
+    int padd,j;
+    unsigned short *line;
+
+    // get the filename
+    i=0;
+    while (*Name_BMP!='\0') {
+        filename[i++]=*Name_BMP++;
+    }
+    filename[i] = 0;
+
+    FILE *Image = fopen((const char *)&filename[0], "rb");  // open the bmp file
+    if (!Image) {
+        return(0);      // error file not found !
+    }
+
+    fread(&BMP_Header[0],1,54,Image);      // get the BMP Header
+
+    if (BMP_Header[0] != 0x42 || BMP_Header[1] != 0x4D) {  // check magic byte
+        fclose(Image);
+        return(-1);     // error no BMP file
+    }
+
+    BPP_t = BMP_Header[OffsetBPP] + (BMP_Header[OffsetBPP + 1] << 8);
+    if (BPP_t != 0x0010) {
+        fclose(Image);
+        return(-2);     // error no 16 bit BMP
+    }
+
+    PixelHeigh = BMP_Header[OffsetPixelHeigh] + (BMP_Header[OffsetPixelHeigh + 1] << 8) + (BMP_Header[OffsetPixelHeigh + 2] << 16) + (BMP_Header[OffsetPixelHeigh + 3] << 24);
+    PixelWidth = BMP_Header[OffsetPixelWidth] + (BMP_Header[OffsetPixelWidth + 1] << 8) + (BMP_Header[OffsetPixelWidth + 2] << 16) + (BMP_Header[OffsetPixelWidth + 3] << 24);
+    if (PixelHeigh > height() + y || PixelWidth > width() + x) {
+        fclose(Image);
+        return(-3);      // to big
+    }
+
+    start_data = BMP_Header[OffsetPixData] + (BMP_Header[OffsetPixData + 1] << 8) + (BMP_Header[OffsetPixData + 2] << 16) + (BMP_Header[OffsetPixData + 3] << 24);
+
+    line = (unsigned short *) malloc (2 * PixelWidth); // we need a buffer for a line
+    if (line == NULL) {
+        return(-4);         // error no memory
+    }
+
+    // the bmp lines are padded to multiple of 4 bytes
+    padd = -1;
+    do {
+        padd ++;
+    } while ((PixelWidth * 2 + padd)%4 != 0);
+
+    window(x, y,PixelWidth ,PixelHeigh);
+    wr_cmd(0x2C);  // send pixel
+    spi_16(1);
+    for (j = PixelHeigh - 1; j >= 0; j--) {               //Lines bottom up
+        off = j * (PixelWidth  * 2 + padd) + start_data;   // start of line
+        fseek(Image, off ,SEEK_SET);
+        fread(line,1,PixelWidth * 2,Image);       // read a line - slow
+        for (i = 0; i < PixelWidth; i++) {        // copy pixel data to TFT
+            f_write(line[i]);                  // one 16 bit pixel
+        }
+    }
+    spi_bsy();
+    _cs = 1;
+    spi_16(0);
+    free (line);
+    fclose(Image);
+    WindowMax();
+    return(1);
+}
+
+#endif
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ILI9341/Small_6.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,101 @@
+
+
+const unsigned char Small_6[] = {
+        9,8,8,1,                                    // Length,horz,vert,byte/vert
+        0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char  
+        0x02, 0x00, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char !
+        0x04, 0x00, 0x03, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00,  // Code for char "
+        0x06, 0x00, 0x12, 0x3F, 0x12, 0x3F, 0x12, 0x00, 0x00,  // Code for char #
+        0x04, 0x00, 0x26, 0x7F, 0x32, 0x00, 0x00, 0x00, 0x00,  // Code for char $
+        0x05, 0x00, 0x13, 0x0B, 0x34, 0x32, 0x00, 0x00, 0x00,  // Code for char %
+        0x05, 0x00, 0x1A, 0x25, 0x1A, 0x28, 0x00, 0x00, 0x00,  // Code for char &
+        0x02, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char '
+        0x03, 0x00, 0x7E, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char (
+        0x03, 0x00, 0x81, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char )
+        0x03, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char *
+        0x04, 0x00, 0x08, 0x1C, 0x08, 0x00, 0x00, 0x00, 0x00,  // Code for char +
+        0x02, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ,
+        0x03, 0x00, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char -
+        0x02, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char .
+        0x03, 0x00, 0x38, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char /
+        0x05, 0x00, 0x1E, 0x21, 0x21, 0x1E, 0x00, 0x00, 0x00,  // Code for char 0
+        0x05, 0x00, 0x02, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 1
+        0x05, 0x00, 0x32, 0x29, 0x29, 0x26, 0x00, 0x00, 0x00,  // Code for char 2
+        0x05, 0x00, 0x12, 0x21, 0x25, 0x1A, 0x00, 0x00, 0x00,  // Code for char 3
+        0x05, 0x00, 0x18, 0x16, 0x3F, 0x10, 0x00, 0x00, 0x00,  // Code for char 4
+        0x05, 0x00, 0x27, 0x25, 0x19, 0x00, 0x00, 0x00, 0x00,  // Code for char 5
+        0x05, 0x00, 0x1E, 0x25, 0x25, 0x18, 0x00, 0x00, 0x00,  // Code for char 6
+        0x05, 0x00, 0x01, 0x3D, 0x03, 0x00, 0x00, 0x00, 0x00,  // Code for char 7
+        0x05, 0x00, 0x1A, 0x25, 0x25, 0x1A, 0x00, 0x00, 0x00,  // Code for char 8
+        0x05, 0x00, 0x12, 0x25, 0x25, 0x1E, 0x00, 0x00, 0x00,  // Code for char 9
+        0x02, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char :
+        0x02, 0x00, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ;
+        0x04, 0x00, 0x08, 0x14, 0x22, 0x00, 0x00, 0x00, 0x00,  // Code for char <
+        0x04, 0x00, 0x14, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00,  // Code for char =
+        0x04, 0x00, 0x22, 0x14, 0x08, 0x00, 0x00, 0x00, 0x00,  // Code for char >
+        0x05, 0x00, 0x02, 0x29, 0x05, 0x02, 0x00, 0x00, 0x00,  // Code for char ?
+        0x08, 0x00, 0x1C, 0x22, 0x49, 0x55, 0x59, 0x12, 0x0C,  // Code for char @
+        0x06, 0x00, 0x30, 0x0C, 0x0B, 0x0C, 0x30, 0x00, 0x00,  // Code for char A
+        0x06, 0x00, 0x3F, 0x25, 0x25, 0x25, 0x1A, 0x00, 0x00,  // Code for char B
+        0x06, 0x00, 0x1E, 0x21, 0x21, 0x21, 0x12, 0x00, 0x00,  // Code for char C
+        0x06, 0x00, 0x3F, 0x21, 0x21, 0x21, 0x1E, 0x00, 0x00,  // Code for char D
+        0x05, 0x00, 0x3F, 0x25, 0x25, 0x21, 0x00, 0x00, 0x00,  // Code for char E
+        0x05, 0x00, 0x3F, 0x05, 0x05, 0x01, 0x00, 0x00, 0x00,  // Code for char F
+        0x06, 0x00, 0x1E, 0x21, 0x21, 0x29, 0x3A, 0x00, 0x00,  // Code for char G
+        0x05, 0x00, 0x3F, 0x04, 0x04, 0x3F, 0x00, 0x00, 0x00,  // Code for char H
+        0x02, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char I
+        0x04, 0x00, 0x30, 0x20, 0x1F, 0x00, 0x00, 0x00, 0x00,  // Code for char J
+        0x05, 0x00, 0x3F, 0x0C, 0x12, 0x21, 0x00, 0x00, 0x00,  // Code for char K
+        0x04, 0x00, 0x3F, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00,  // Code for char L
+        0x08, 0x00, 0x3F, 0x03, 0x0C, 0x30, 0x0C, 0x03, 0x3F,  // Code for char M
+        0x06, 0x00, 0x3F, 0x03, 0x0C, 0x30, 0x3F, 0x00, 0x00,  // Code for char N
+        0x06, 0x00, 0x1E, 0x21, 0x21, 0x21, 0x1E, 0x00, 0x00,  // Code for char O
+        0x05, 0x00, 0x3F, 0x09, 0x09, 0x06, 0x00, 0x00, 0x00,  // Code for char P
+        0x06, 0x00, 0x1E, 0x21, 0x29, 0x11, 0x2E, 0x00, 0x00,  // Code for char Q
+        0x06, 0x00, 0x3F, 0x09, 0x09, 0x09, 0x36, 0x00, 0x00,  // Code for char R
+        0x05, 0x00, 0x12, 0x25, 0x29, 0x12, 0x00, 0x00, 0x00,  // Code for char S
+        0x06, 0x00, 0x01, 0x01, 0x3F, 0x01, 0x01, 0x00, 0x00,  // Code for char T
+        0x06, 0x00, 0x1F, 0x20, 0x20, 0x20, 0x1F, 0x00, 0x00,  // Code for char U
+        0x06, 0x00, 0x03, 0x0C, 0x30, 0x0C, 0x03, 0x00, 0x00,  // Code for char V
+        0x08, 0x00, 0x03, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x03,  // Code for char W
+        0x06, 0x00, 0x21, 0x12, 0x0C, 0x12, 0x21, 0x00, 0x00,  // Code for char X
+        0x06, 0x00, 0x01, 0x02, 0x3C, 0x02, 0x01, 0x00, 0x00,  // Code for char Y
+        0x05, 0x00, 0x31, 0x29, 0x25, 0x23, 0x00, 0x00, 0x00,  // Code for char Z
+        0x03, 0x00, 0x7F, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char [
+        0x03, 0x00, 0x07, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char BackSlash
+        0x03, 0x00, 0x41, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ]
+        0x04, 0x00, 0x02, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00,  // Code for char ^
+        0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00,  // Code for char _
+        0x03, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char `
+        0x04, 0x00, 0x14, 0x24, 0x38, 0x00, 0x00, 0x00, 0x00,  // Code for char a
+        0x05, 0x00, 0x3F, 0x24, 0x24, 0x18, 0x00, 0x00, 0x00,  // Code for char b
+        0x04, 0x00, 0x18, 0x24, 0x24, 0x00, 0x00, 0x00, 0x00,  // Code for char c
+        0x05, 0x00, 0x18, 0x24, 0x24, 0x3F, 0x00, 0x00, 0x00,  // Code for char d
+        0x04, 0x00, 0x18, 0x34, 0x28, 0x00, 0x00, 0x00, 0x00,  // Code for char e
+        0x03, 0x00, 0x3E, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char f
+        0x05, 0x00, 0x18, 0xA4, 0xA4, 0x7C, 0x00, 0x00, 0x00,  // Code for char g
+        0x04, 0x00, 0x3F, 0x04, 0x38, 0x00, 0x00, 0x00, 0x00,  // Code for char h
+        0x02, 0x00, 0x3D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char i
+        0x02, 0x00, 0xFD, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char j
+        0x04, 0x00, 0x3F, 0x08, 0x34, 0x00, 0x00, 0x00, 0x00,  // Code for char k
+        0x02, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char l
+        0x06, 0x00, 0x3C, 0x04, 0x3C, 0x04, 0x38, 0x00, 0x00,  // Code for char m
+        0x04, 0x00, 0x3C, 0x04, 0x38, 0x00, 0x00, 0x00, 0x00,  // Code for char n
+        0x05, 0x00, 0x18, 0x24, 0x24, 0x18, 0x00, 0x00, 0x00,  // Code for char o
+        0x05, 0x00, 0xFC, 0x24, 0x24, 0x18, 0x00, 0x00, 0x00,  // Code for char p
+        0x05, 0x00, 0x18, 0x24, 0x24, 0xFC, 0x00, 0x00, 0x00,  // Code for char q
+        0x03, 0x00, 0x3C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char r
+        0x04, 0x00, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00,  // Code for char s
+        0x03, 0x00, 0x1E, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char t
+        0x04, 0x00, 0x1C, 0x20, 0x3C, 0x00, 0x00, 0x00, 0x00,  // Code for char u
+        0x04, 0x00, 0x0C, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00,  // Code for char v
+        0x06, 0x00, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x00, 0x00,  // Code for char w
+        0x04, 0x00, 0x24, 0x18, 0x24, 0x00, 0x00, 0x00, 0x00,  // Code for char x
+        0x04, 0x00, 0x9C, 0x60, 0x1C, 0x00, 0x00, 0x00, 0x00,  // Code for char y
+        0x04, 0x00, 0x34, 0x24, 0x2C, 0x00, 0x00, 0x00, 0x00,  // Code for char z
+        0x03, 0x00, 0x08, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char {
+        0x02, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char |
+        0x03, 0x00, 0x77, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char }
+        0x04, 0x02, 0x01, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00,  // Code for char ~
+        0x02, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00   // Code for char 
+        };

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ILI9341/Small_7.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,105 @@
+#ifndef small_7
+#define small_7
+
+const unsigned char Small_7[] = {
+        19,9,9,2,                                    // Length,horz,vert,byte/vert    
+        0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char  
+        0x02, 0x00, 0x00, 0x9E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char !
+        0x04, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char "
+        0x06, 0x00, 0x00, 0x50, 0x00, 0xF8, 0x00, 0x50, 0x00, 0xF8, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char #
+        0x06, 0x00, 0x00, 0x8C, 0x00, 0x92, 0x00, 0xFE, 0x01, 0xA2, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char $
+        0x07, 0x1E, 0x00, 0x92, 0x00, 0x5E, 0x00, 0x20, 0x00, 0xF8, 0x00, 0x94, 0x00, 0xF2, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char %
+        0x07, 0x00, 0x00, 0x64, 0x00, 0x9A, 0x00, 0xAA, 0x00, 0xCC, 0x00, 0x60, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char &
+        0x02, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char '
+        0x03, 0x00, 0x00, 0x7C, 0x00, 0x83, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char (
+        0x03, 0x00, 0x00, 0x83, 0x01, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char )
+        0x04, 0x00, 0x00, 0x30, 0x00, 0x78, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char *
+        0x05, 0x10, 0x00, 0x10, 0x00, 0x7C, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char +
+        0x02, 0x00, 0x01, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ,
+        0x04, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char -
+        0x02, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char .
+        0x04, 0x00, 0x01, 0xE0, 0x00, 0x1C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char /
+        0x05, 0x00, 0x00, 0x7C, 0x00, 0x82, 0x00, 0x82, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 0
+        0x05, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 1
+        0x05, 0x00, 0x00, 0x84, 0x00, 0xC2, 0x00, 0xA2, 0x00, 0x9C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 2
+        0x05, 0x00, 0x00, 0x82, 0x00, 0x92, 0x00, 0x92, 0x00, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 3
+        0x05, 0x00, 0x00, 0x38, 0x00, 0x2C, 0x00, 0x22, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 4
+        0x05, 0x00, 0x00, 0x9E, 0x00, 0x92, 0x00, 0x92, 0x00, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 5
+        0x05, 0x00, 0x00, 0x7C, 0x00, 0x92, 0x00, 0x92, 0x00, 0x74, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 6
+        0x05, 0x00, 0x00, 0x02, 0x00, 0xC2, 0x00, 0x32, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 7
+        0x05, 0x00, 0x00, 0x6C, 0x00, 0x92, 0x00, 0x92, 0x00, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 8
+        0x05, 0x00, 0x00, 0x9C, 0x00, 0x92, 0x00, 0x92, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 9
+        0x02, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char :
+        0x02, 0x00, 0x01, 0xC8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ;
+        0x05, 0x10, 0x00, 0x10, 0x00, 0x28, 0x00, 0x28, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char <
+        0x05, 0x00, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char =
+        0x05, 0x00, 0x00, 0x44, 0x00, 0x28, 0x00, 0x28, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char >
+        0x05, 0x00, 0x00, 0x02, 0x00, 0xB2, 0x00, 0x12, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ?
+        0x09, 0x00, 0x00, 0xF8, 0x00, 0x84, 0x01, 0x72, 0x01, 0x4A, 0x01, 0x4A, 0x01, 0x7A, 0x01, 0x42, 0x00, 0x3C, 0x00,  // Code for char @
+        0x06, 0x00, 0x00, 0xF8, 0x00, 0x24, 0x00, 0x22, 0x00, 0x24, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char A
+        0x06, 0x00, 0x00, 0xFE, 0x00, 0x92, 0x00, 0x92, 0x00, 0x92, 0x00, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char B
+        0x06, 0x00, 0x00, 0x7C, 0x00, 0x82, 0x00, 0x82, 0x00, 0x82, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char C
+        0x06, 0x00, 0x00, 0xFE, 0x00, 0x82, 0x00, 0x82, 0x00, 0xC6, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char D
+        0x05, 0x00, 0x00, 0xFE, 0x00, 0x92, 0x00, 0x92, 0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char E
+        0x05, 0x00, 0x00, 0xFE, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char F
+        0x06, 0x00, 0x00, 0x7C, 0x00, 0xC6, 0x00, 0x82, 0x00, 0x92, 0x00, 0xF6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char G
+        0x06, 0x00, 0x00, 0xFE, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char H
+        0x02, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char I
+        0x04, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char J
+        0x05, 0x00, 0x00, 0xFE, 0x00, 0x10, 0x00, 0x2C, 0x00, 0xC2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char K
+        0x05, 0x00, 0x00, 0xFE, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char L
+        0x08, 0x00, 0x00, 0xFE, 0x00, 0x06, 0x00, 0x18, 0x00, 0xE0, 0x00, 0x18, 0x00, 0x06, 0x00, 0xFE, 0x00, 0x00, 0x00,  // Code for char M
+        0x06, 0x00, 0x00, 0xFE, 0x00, 0x06, 0x00, 0x18, 0x00, 0x60, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char N
+        0x06, 0x00, 0x00, 0x7C, 0x00, 0x82, 0x00, 0x82, 0x00, 0x82, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char O
+        0x05, 0x00, 0x00, 0xFE, 0x00, 0x12, 0x00, 0x12, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char P
+        0x07, 0x00, 0x00, 0x7C, 0x00, 0x82, 0x00, 0x82, 0x00, 0xC2, 0x00, 0xFC, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,  // Code for char Q
+        0x05, 0x00, 0x00, 0xFE, 0x00, 0x12, 0x00, 0x12, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char R
+        0x05, 0x00, 0x00, 0xCC, 0x00, 0x92, 0x00, 0x92, 0x00, 0x66, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char S
+        0x06, 0x00, 0x00, 0x02, 0x00, 0x02, 0x00, 0xFE, 0x00, 0x02, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char T
+        0x06, 0x00, 0x00, 0x7E, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char U
+        0x07, 0x00, 0x00, 0x06, 0x00, 0x3C, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0x1C, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char V
+        0x06, 0x00, 0x00, 0x1E, 0x00, 0xE0, 0x00, 0x3E, 0x00, 0xE0, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char W
+        0x06, 0x00, 0x00, 0x82, 0x00, 0x64, 0x00, 0x38, 0x00, 0x6C, 0x00, 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char X
+        0x06, 0x00, 0x00, 0x02, 0x00, 0x0C, 0x00, 0xF0, 0x00, 0x0C, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Y
+        0x06, 0x00, 0x00, 0x82, 0x00, 0xE2, 0x00, 0x92, 0x00, 0x8E, 0x00, 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Z
+        0x03, 0x00, 0x00, 0xFF, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char [
+        0x04, 0x01, 0x00, 0x0E, 0x00, 0x70, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char BackSlash
+        0x02, 0x01, 0x01, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ]
+        0x04, 0x00, 0x00, 0x18, 0x00, 0x0C, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ^
+        0x06, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char _
+        0x03, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char `
+        0x05, 0x00, 0x00, 0xE8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char a
+        0x05, 0x00, 0x00, 0xFE, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char b
+        0x05, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char c
+        0x05, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, 0x88, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char d
+        0x05, 0x00, 0x00, 0x70, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xB0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char e
+        0x04, 0x08, 0x00, 0xFE, 0x00, 0x0A, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char f
+        0x05, 0x00, 0x00, 0x30, 0x00, 0x48, 0x01, 0x48, 0x01, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char g
+        0x05, 0x00, 0x00, 0xFE, 0x00, 0x08, 0x00, 0x08, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char h
+        0x02, 0x00, 0x00, 0xFA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char i
+        0x02, 0x00, 0x01, 0xFA, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char j
+        0x05, 0x00, 0x00, 0xFE, 0x00, 0x20, 0x00, 0x50, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char k
+        0x02, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char l
+        0x06, 0x00, 0x00, 0xF8, 0x00, 0x08, 0x00, 0xF8, 0x00, 0x08, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char m
+        0x05, 0x00, 0x00, 0xF8, 0x00, 0x08, 0x00, 0x08, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char n
+        0x05, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char o
+        0x05, 0x00, 0x00, 0xF8, 0x01, 0x48, 0x00, 0x48, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char p
+        0x05, 0x00, 0x00, 0x30, 0x00, 0x48, 0x00, 0x48, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char q
+        0x04, 0x00, 0x00, 0xF8, 0x00, 0x08, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char r
+        0x04, 0x00, 0x00, 0x98, 0x00, 0xA8, 0x00, 0xE8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char s
+        0x04, 0x00, 0x00, 0x08, 0x00, 0xFC, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char t
+        0x05, 0x00, 0x00, 0x78, 0x00, 0x80, 0x00, 0x80, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char u
+        0x04, 0x00, 0x00, 0x38, 0x00, 0xC0, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char v
+        0x06, 0x00, 0x00, 0x78, 0x00, 0xC0, 0x00, 0x38, 0x00, 0xC0, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char w
+        0x05, 0x00, 0x00, 0x88, 0x00, 0x70, 0x00, 0x70, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char x
+        0x05, 0x00, 0x00, 0x38, 0x00, 0x40, 0x01, 0x40, 0x01, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char y
+        0x05, 0x00, 0x00, 0xC8, 0x00, 0xE8, 0x00, 0xB8, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char z
+        0x04, 0x10, 0x00, 0x38, 0x00, 0xEF, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char {
+        0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char |
+        0x04, 0x01, 0x01, 0xC7, 0x01, 0x38, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char }
+        0x05, 0x0C, 0x00, 0x04, 0x00, 0x0C, 0x00, 0x08, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ~
+        0x03, 0xFE, 0x01, 0x02, 0x01, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00   // Code for char 
+        };
+        
+#endif        
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ILI9341/TextDisplay.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,78 @@
+/* mbed TextDisplay Display Library Base Class
+ * Copyright (c) 2007-2009 sford
+ * Released under the MIT License: http://mbed.org/license/mit
+ */
+ 
+#include "TextDisplay.h"
+
+TextDisplay::TextDisplay(const char *name) : Stream(name){
+    _row = 0;
+    _column = 0;
+    if (name == NULL) {
+        _path = NULL;
+    } else {
+        _path = new char[strlen(name) + 2];
+        sprintf(_path, "/%s", name);
+    }
+}
+    
+int TextDisplay::_putc(int value) {
+    if(value == '\n') {
+        _column = 0;
+        _row++;
+        if(_row >= rows()) {
+            _row = 0;
+        }
+    } else {
+        character(_column, _row, value);
+        _column++;
+        if(_column >= columns()) {
+            _column = 0;
+            _row++;
+            if(_row >= rows()) {
+                _row = 0;
+            }
+        }
+    }
+    return value;
+}
+
+// crude cls implementation, should generally be overwritten in derived class
+void TextDisplay::cls() {
+    locate(0, 0);
+    for(int i=0; i<columns()*rows(); i++) {
+        putc(' ');
+    }
+}
+
+void TextDisplay::locate(int column, int row) {
+    _column = column;
+    _row = row;
+}
+
+int TextDisplay::_getc() {
+    return -1;
+}
+        
+void TextDisplay::foreground(uint16_t colour) {
+    _foreground = colour;
+}
+
+void TextDisplay::background(uint16_t colour) {
+    _background = colour;
+}
+
+bool TextDisplay::claim (FILE *stream) {
+    if ( _path == NULL) {
+        fprintf(stderr, "claim requires a name to be given in the instantioator of the TextDisplay instance!\r\n");
+        return false;
+    }
+    if (freopen(_path, "w", stream) == NULL) {
+        // Failed, should not happen
+        return false;
+    }
+    // make sure we use line buffering
+    setvbuf(stdout, NULL, _IOLBF, columns());
+    return true;
+} 
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ILI9341/TextDisplay.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,81 @@
+/* mbed TextDisplay Library Base Class
+ * Copyright (c) 2007-2009 sford
+ * Released under the MIT License: http://mbed.org/license/mit
+ *
+ * A common base class for Text displays
+ * To port a new display, derive from this class and implement
+ * the constructor (setup the display), character (put a character
+ * at a location), rows and columns (number of rows/cols) functions.
+ * Everything else (locate, printf, putc, cls) will come for free
+ *
+ * The model is the display will wrap at the right and bottom, so you can
+ * keep writing and will always get valid characters. The location is 
+ * maintained internally to the class to make this easy
+ */
+
+#ifndef MBED_TEXTDISPLAY_H
+#define MBED_TEXTDISPLAY_H
+
+#include "mbed.h"
+
+class TextDisplay : public Stream {
+public:
+
+  // functions needing implementation in derived implementation class
+  /** Create a TextDisplay interface
+     *
+     * @param name The name used in the path to access the strean through the filesystem
+     */
+    TextDisplay(const char *name = NULL);
+
+    /** output a character at the given position
+     *
+     * @param column column where charater must be written
+     * @param  row where character must be written
+     * @param c the character to be written to the TextDisplay
+     */
+    virtual void character(int column, int row, int c) = 0;
+
+    /** return number if rows on TextDisplay
+     * @result number of rows
+     */
+    virtual int rows() = 0;
+
+    /** return number if columns on TextDisplay
+    * @result number of rows
+    */
+    virtual int columns() = 0;
+    
+    // functions that come for free, but can be overwritten
+
+    /** redirect output from a stream (stoud, sterr) to  display
+    * @param stream stream that shall be redirected to the TextDisplay
+    */
+    virtual bool claim (FILE *stream);
+
+    /** clear screen
+    */
+    virtual void cls();
+    virtual void locate(int column, int row);
+    virtual void foreground(uint16_t colour);
+    virtual void background(uint16_t colour);
+    // putc (from Stream)
+    // printf (from Stream)
+    
+protected:
+
+    virtual int _putc(int value);
+    virtual int _getc();
+
+    // character location
+    uint16_t _column;
+    uint16_t _row;
+
+    // colours
+    uint16_t _foreground;
+    uint16_t _background;
+    char *_path;
+};
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ILI9341/font_big.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,113 @@
+//Font Generated by MikroElektronika GLCD Font Creator 1.2.0.0
+//MikroElektronika 2011 
+//http://www.mikroe.com 
+
+//GLCD FontName : Neu42x35
+//GLCD FontSize : 42 x 35
+
+/** big font 42*35 pixel matrix for use with the SPI_TFT lib
+*/
+__align(2)
+const unsigned char Neu42x35[] = {
+        211,42,35,5,
+        0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char  
+        0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0xFF, 0x7F, 0x1E, 0x00, 0x80, 0xFF, 0xFF, 0x1E, 0x00, 0x80, 0xFF, 0xFF, 0x1E, 0x00, 0x00, 0xFF, 0x7F, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char !
+        0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char "
+        0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0xC0, 0x78, 0x00, 0x00, 0x00, 0xE0, 0x79, 0x0C, 0x00, 0x00, 0xE0, 0x79, 0x1F, 0x00, 0x00, 0xE0, 0xF9, 0x1F, 0x00, 0x00, 0xE0, 0xFD, 0x0F, 0x00, 0x00, 0xE0, 0xFF, 0x03, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0xFC, 0x7F, 0x00, 0x00, 0x00, 0xFE, 0x7B, 0x0C, 0x00, 0x00, 0xFF, 0x79, 0x1E, 0x00, 0x00, 0xFF, 0xF9, 0x1F, 0x00, 0x00, 0xEE, 0xF9, 0x0F, 0x00, 0x00, 0xE0, 0xFD, 0x07, 0x00, 0x00, 0xE0, 0xFF, 0x01, 0x00, 0x00, 0xF8, 0x7F, 0x00, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x00, 0x00, 0xFF, 0x7B, 0x00, 0x00, 0x00, 0xFF, 0x79, 0x00, 0x00, 0x00, 0xEE, 0x79, 0x00, 0x00, 0x00, 0xE0, 0x79, 0x00, 0x00, 0x00, 0xE0, 0x31, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char #
+        0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x0C, 0x00, 0x00, 0xFC, 0x03, 0x1E, 0x00, 0x00, 0xFE, 0x07, 0x1E, 0x00, 0x00, 0xFF, 0x07, 0x1E, 0x00, 0x80, 0x87, 0x07, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0xC0, 0xFF, 0xFF, 0x3F, 0x00, 0xE0, 0xFF, 0xFF, 0x7F, 0x00, 0xE0, 0xFF, 0xFF, 0x7F, 0x00, 0xC0, 0xFF, 0xFF, 0x3F, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x00, 0x03, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x1F, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x07, 0x00, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char $
+        0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0x80, 0xEF, 0x03, 0x08, 0x00, 0x80, 0xC7, 0x03, 0x1C, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1F, 0x00, 0x80, 0xC7, 0x83, 0x1F, 0x00, 0x80, 0xC7, 0xC3, 0x0F, 0x00, 0x80, 0xC7, 0xE3, 0x07, 0x00, 0x80, 0xEF, 0xF3, 0x03, 0x00, 0x80, 0xFF, 0xF9, 0x01, 0x00, 0x00, 0xFF, 0xFD, 0x00, 0x00, 0x00, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0xFE, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0xEF, 0x0F, 0x00, 0x00, 0xE0, 0xF7, 0x1F, 0x00, 0x00, 0xF0, 0xF3, 0x1F, 0x00, 0x00, 0xF8, 0xF9, 0x3F, 0x00, 0x00, 0xFC, 0xF8, 0x3E, 0x00, 0x00, 0x7C, 0x78, 0x3C, 0x00, 0x00, 0x3E, 0x78, 0x3C, 0x00, 0x00, 0x1F, 0x78, 0x3C, 0x00, 0x80, 0x0F, 0x78, 0x3C, 0x00, 0x80, 0x07, 0x78, 0x3C, 0x00, 0x80, 0x03, 0x78, 0x3C, 0x00, 0x80, 0x01, 0x78, 0x1E, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0xF0, 0x1F, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char %
+        0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0xF8, 0x07, 0x00, 0x00, 0x38, 0xFC, 0x07, 0x00, 0x00, 0xFE, 0xFC, 0x0F, 0x00, 0x00, 0xFF, 0x1C, 0x0F, 0x00, 0x00, 0xFF, 0x1F, 0x1E, 0x00, 0x80, 0xCF, 0x0F, 0x1E, 0x00, 0x80, 0x87, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x07, 0x1E, 0x00, 0x80, 0x07, 0x07, 0x1E, 0x00, 0x80, 0x07, 0x0E, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x1F, 0x1E, 0x00, 0x80, 0x07, 0x1F, 0x1E, 0x00, 0x80, 0x07, 0x3F, 0x1E, 0x00, 0x80, 0x87, 0x3B, 0x1E, 0x00, 0x80, 0x87, 0x7B, 0x1E, 0x00, 0x80, 0xCF, 0xF1, 0x1E, 0x00, 0x00, 0xFF, 0xE1, 0x1E, 0x00, 0x00, 0xFF, 0xE0, 0x1F, 0x00, 0x00, 0xFE, 0xC0, 0x1F, 0x00, 0x00, 0x7C, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x1F, 0x00, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char &
+        0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char '
+        0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0x01, 0x00, 0x00, 0xFC, 0xFF, 0x03, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0x0F, 0x00, 0x1F, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x03, 0x00, 0x1C, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char (
+        0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x80, 0x03, 0x00, 0x1C, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x0F, 0x00, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFC, 0xFF, 0x03, 0x00, 0x00, 0xF8, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char )
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x78, 0x1E, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0xFC, 0x3F, 0x00, 0x00, 0x00, 0xFC, 0x3F, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0x78, 0x1E, 0x00, 0x00, 0x00, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char *
+        0x0E, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char +
+        0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ,
+        0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char -
+        0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char .
+        0x19, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char /
+        0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0x03, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x80, 0x0F, 0x00, 0x1F, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x0F, 0x00, 0x1E, 0x00, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xF8, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 0
+        0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 1
+        0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0xFE, 0x1F, 0x00, 0x00, 0x00, 0xFE, 0x1F, 0x00, 0x00, 0x00, 0x1E, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x03, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x8F, 0x07, 0x1E, 0x00, 0x00, 0xFF, 0x07, 0x1E, 0x00, 0x00, 0xFF, 0x07, 0x1E, 0x00, 0x00, 0xFE, 0x03, 0x1E, 0x00, 0x00, 0xFC, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 2
+        0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x0C, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x03, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x8F, 0x1F, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFC, 0xF8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 3
+        0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x7F, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 4
+        0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x0C, 0x00, 0x80, 0xFF, 0x03, 0x1E, 0x00, 0x80, 0xFF, 0x03, 0x1E, 0x00, 0x80, 0xFF, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x00, 0xC3, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x07, 0x1E, 0x00, 0x00, 0x80, 0x07, 0x0F, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 5
+        0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x01, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xCF, 0x03, 0x0F, 0x00, 0x80, 0xC7, 0x03, 0x1F, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x00, 0xC3, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x03, 0x1E, 0x00, 0x00, 0xC0, 0x07, 0x1F, 0x00, 0x00, 0x80, 0x07, 0x0F, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 6
+        0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x08, 0x00, 0x80, 0x07, 0x00, 0x1C, 0x00, 0x80, 0x07, 0x00, 0x1F, 0x00, 0x80, 0x07, 0x80, 0x1F, 0x00, 0x80, 0x07, 0xC0, 0x0F, 0x00, 0x80, 0x07, 0xE0, 0x03, 0x00, 0x80, 0x07, 0xF0, 0x01, 0x00, 0x80, 0x07, 0xF8, 0x00, 0x00, 0x80, 0x07, 0x7C, 0x00, 0x00, 0x80, 0x07, 0x3E, 0x00, 0x00, 0x80, 0x87, 0x1F, 0x00, 0x00, 0x80, 0xC7, 0x07, 0x00, 0x00, 0x80, 0xE7, 0x03, 0x00, 0x00, 0x80, 0xF7, 0x01, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 7
+        0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xF0, 0x03, 0x00, 0x00, 0xFE, 0xFB, 0x07, 0x00, 0x00, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x8F, 0x1F, 0x0F, 0x00, 0x80, 0x0F, 0x0F, 0x1F, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x0F, 0x1F, 0x1F, 0x00, 0x00, 0x8F, 0x1F, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0xF9, 0x07, 0x00, 0x00, 0xFC, 0xF0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 8
+        0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x07, 0x00, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x1F, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x80, 0x07, 0x3E, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x0C, 0x00, 0x80, 0x07, 0x3C, 0x1E, 0x00, 0x80, 0x07, 0x3C, 0x1E, 0x00, 0x80, 0x07, 0x3C, 0x1E, 0x00, 0x80, 0x07, 0x3C, 0x1E, 0x00, 0x80, 0x07, 0x3C, 0x1E, 0x00, 0x80, 0x07, 0x3C, 0x1E, 0x00, 0x80, 0x07, 0x3C, 0x1E, 0x00, 0x80, 0x07, 0x3C, 0x1E, 0x00, 0x80, 0x0F, 0x3C, 0x1E, 0x00, 0x00, 0x0F, 0x3C, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xF8, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char 9
+        0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x00, 0x1E, 0x1E, 0x00, 0x00, 0x00, 0x1E, 0x1E, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char :
+        0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x0C, 0xFF, 0x00, 0x00, 0x00, 0x1E, 0xFF, 0x00, 0x00, 0x00, 0x1E, 0xFF, 0x00, 0x00, 0x00, 0x1E, 0x07, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ;
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x19, 0x00, 0x00, 0x00, 0x80, 0x19, 0x00, 0x00, 0x00, 0xC0, 0x39, 0x00, 0x00, 0x00, 0xC0, 0x30, 0x00, 0x00, 0x00, 0xE0, 0x70, 0x00, 0x00, 0x00, 0x60, 0x60, 0x00, 0x00, 0x00, 0x70, 0xE0, 0x00, 0x00, 0x00, 0x70, 0xE0, 0x00, 0x00, 0x00, 0x30, 0xC0, 0x00, 0x00, 0x00, 0x38, 0xC0, 0x01, 0x00, 0x00, 0x18, 0x80, 0x01, 0x00, 0x00, 0x18, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char <
+        0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE7, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x80, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char =
+        0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x80, 0x01, 0x00, 0x00, 0x18, 0x80, 0x01, 0x00, 0x00, 0x38, 0xC0, 0x01, 0x00, 0x00, 0x30, 0xC0, 0x00, 0x00, 0x00, 0x70, 0xE0, 0x00, 0x00, 0x00, 0x70, 0x60, 0x00, 0x00, 0x00, 0x60, 0x60, 0x00, 0x00, 0x00, 0xE0, 0x70, 0x00, 0x00, 0x00, 0xC0, 0x30, 0x00, 0x00, 0x00, 0xC0, 0x39, 0x00, 0x00, 0x00, 0x80, 0x19, 0x00, 0x00, 0x00, 0x80, 0x19, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char >
+        0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0xF8, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x1E, 0x00, 0x00, 0x00, 0x7E, 0x0C, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x03, 0x1E, 0x00, 0x00, 0x80, 0x07, 0x1E, 0x00, 0x00, 0x80, 0x07, 0x1E, 0x00, 0x00, 0x80, 0x07, 0x1E, 0x00, 0x00, 0x80, 0x07, 0x1E, 0x00, 0x00, 0x80, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x07, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ?
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x80, 0xFF, 0xFF, 0x03, 0x00, 0xC0, 0xFF, 0xFF, 0x03, 0x00, 0xC0, 0x01, 0x00, 0x07, 0x00, 0xC0, 0x00, 0x0F, 0x06, 0x00, 0xC0, 0x80, 0x1F, 0x06, 0x00, 0xC0, 0xC0, 0x1F, 0x06, 0x00, 0xC0, 0xC0, 0x30, 0x06, 0x00, 0xC0, 0xD8, 0x30, 0x06, 0x00, 0xC0, 0xD8, 0x30, 0x06, 0x00, 0xC0, 0xD8, 0x30, 0x06, 0x00, 0xC0, 0xD8, 0x30, 0x00, 0x00, 0xC0, 0xD8, 0x30, 0x00, 0x00, 0xC0, 0xF8, 0x3F, 0x00, 0x00, 0xC0, 0xF0, 0x3F, 0x00, 0x00, 0xC0, 0xE0, 0x3F, 0x00, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x00, 0xC0, 0x01, 0x30, 0x00, 0x00, 0xC0, 0xFF, 0x3F, 0x00, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char @
+        0x1F, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x00, 0xF0, 0xF7, 0x00, 0x00, 0x00, 0xF8, 0xF1, 0x00, 0x00, 0x00, 0xFE, 0xF0, 0x00, 0x00, 0x00, 0x3F, 0xF0, 0x00, 0x00, 0x80, 0x1F, 0xF0, 0x00, 0x00, 0x80, 0x07, 0xF0, 0x00, 0x00, 0x80, 0x0F, 0xF0, 0x00, 0x00, 0x80, 0x3F, 0xF0, 0x00, 0x00, 0x00, 0x7E, 0xF0, 0x00, 0x00, 0x00, 0xFC, 0xF1, 0x00, 0x00, 0x00, 0xF0, 0xF3, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char A
+        0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x00, 0x8F, 0x1F, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xF8, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char B
+        0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x03, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0x0F, 0x00, 0x1F, 0x00, 0x80, 0x07, 0x00, 0x1F, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x00, 0x03, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char C
+        0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x0F, 0x00, 0x1F, 0x00, 0x80, 0x0F, 0x00, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFC, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char D
+        0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0x03, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x0F, 0x0F, 0x0F, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x00, 0x03, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x06, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char E
+        0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x0F, 0x00, 0x00, 0xFE, 0xFF, 0x1F, 0x00, 0x00, 0xFE, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x0F, 0x0F, 0x00, 0x00, 0x80, 0x0F, 0x0F, 0x00, 0x00, 0x80, 0x07, 0x0F, 0x00, 0x00, 0x80, 0x07, 0x0F, 0x00, 0x00, 0x80, 0x07, 0x0F, 0x00, 0x00, 0x80, 0x07, 0x0F, 0x00, 0x00, 0x80, 0x07, 0x0F, 0x00, 0x00, 0x80, 0x07, 0x0F, 0x00, 0x00, 0x80, 0x07, 0x0F, 0x00, 0x00, 0x00, 0x03, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char F
+        0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x03, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x80, 0x0F, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x00, 0x03, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x06, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1F, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFF, 0x07, 0x00, 0x00, 0x00, 0xFF, 0x03, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char G
+        0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char H
+        0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char I
+        0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x07, 0x00, 0x80, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char J
+        0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0xE0, 0x3D, 0x00, 0x00, 0x00, 0xE0, 0x79, 0x00, 0x00, 0x00, 0xF0, 0x78, 0x00, 0x00, 0x00, 0xF0, 0xF0, 0x00, 0x00, 0x00, 0x78, 0xF0, 0x00, 0x00, 0x00, 0x78, 0xE0, 0x01, 0x00, 0x00, 0x3C, 0xE0, 0x03, 0x00, 0x00, 0x3C, 0xC0, 0x03, 0x00, 0x00, 0x1E, 0x80, 0x07, 0x00, 0x00, 0x1F, 0x80, 0x07, 0x00, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x80, 0x0F, 0x00, 0x0F, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x03, 0x00, 0x1E, 0x00, 0x80, 0x03, 0x00, 0x1C, 0x00, 0x00, 0x01, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char K
+        0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x03, 0x00, 0x80, 0xFF, 0xFF, 0x07, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char L
+        0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char M
+        0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char N
+        0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0x01, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x80, 0x0F, 0x00, 0x1F, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x0F, 0x00, 0x1F, 0x00, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFC, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char O
+        0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3C, 0x00, 0x00, 0x80, 0x07, 0x3E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char P
+        0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x01, 0x00, 0x00, 0xFE, 0xFF, 0x07, 0x00, 0x00, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x80, 0x0F, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x3E, 0x00, 0x80, 0x07, 0x00, 0x7E, 0x00, 0x80, 0x0F, 0x00, 0x7F, 0x00, 0x80, 0x0F, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0xFF, 0xFF, 0xE7, 0x00, 0x00, 0xFE, 0xFF, 0x47, 0x00, 0x00, 0xFC, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Q
+        0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0x07, 0x1E, 0x00, 0x00, 0x80, 0x07, 0x3E, 0x00, 0x00, 0x80, 0x07, 0x3E, 0x00, 0x00, 0x80, 0x07, 0x7E, 0x00, 0x00, 0x80, 0x07, 0x7E, 0x00, 0x00, 0x80, 0x07, 0x7E, 0x00, 0x00, 0x80, 0x07, 0xFE, 0x00, 0x00, 0x80, 0x07, 0xFE, 0x00, 0x00, 0x80, 0x07, 0xFE, 0x01, 0x00, 0x80, 0x07, 0xDE, 0x01, 0x00, 0x80, 0x07, 0xDE, 0x03, 0x00, 0x80, 0x07, 0x9E, 0x03, 0x00, 0x80, 0x07, 0x9E, 0x03, 0x00, 0x80, 0x07, 0x9E, 0x07, 0x00, 0x80, 0x07, 0x1E, 0x07, 0x00, 0x80, 0x07, 0x1E, 0x0F, 0x00, 0x80, 0x07, 0x1E, 0x0E, 0x00, 0x80, 0x07, 0x1E, 0x1E, 0x00, 0x00, 0x0F, 0x0F, 0x1E, 0x00, 0x00, 0xFF, 0x0F, 0x1C, 0x00, 0x00, 0xFF, 0x0F, 0x1C, 0x00, 0x00, 0xFE, 0x07, 0x08, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char R
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x0C, 0x00, 0x00, 0xFE, 0x01, 0x1E, 0x00, 0x00, 0xFF, 0x03, 0x1E, 0x00, 0x00, 0xFF, 0x07, 0x1E, 0x00, 0x80, 0xCF, 0x07, 0x1E, 0x00, 0x80, 0x87, 0x07, 0x1E, 0x00, 0x80, 0x87, 0x07, 0x1E, 0x00, 0x80, 0x87, 0x07, 0x1E, 0x00, 0x80, 0x87, 0x07, 0x1E, 0x00, 0x80, 0x87, 0x07, 0x1E, 0x00, 0x80, 0x87, 0x07, 0x1E, 0x00, 0x80, 0x87, 0x07, 0x1E, 0x00, 0x00, 0x83, 0x07, 0x1E, 0x00, 0x00, 0x80, 0x07, 0x1E, 0x00, 0x00, 0x80, 0x07, 0x1E, 0x00, 0x00, 0x80, 0x07, 0x1E, 0x00, 0x00, 0x80, 0x07, 0x1E, 0x00, 0x00, 0x80, 0x07, 0x1E, 0x00, 0x00, 0x80, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1F, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x07, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char S
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char T
+        0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x03, 0x00, 0x80, 0xFF, 0xFF, 0x07, 0x00, 0x80, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x07, 0x00, 0x80, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char U
+        0x20, 0x00, 0x01, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char V
+        0x2A, 0x00, 0x01, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0xFC, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x03, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0xFE, 0x03, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x03, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x03, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x03, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x00, 0x00, 0xE0, 0x3F, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x03, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,  // Code for char W
+        0x1C, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x1C, 0x00, 0x80, 0x03, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1F, 0x00, 0x80, 0x0F, 0x00, 0x0F, 0x00, 0x00, 0x1F, 0x80, 0x0F, 0x00, 0x00, 0x3E, 0xC0, 0x07, 0x00, 0x00, 0x7C, 0xE0, 0x03, 0x00, 0x00, 0x78, 0xF0, 0x01, 0x00, 0x00, 0xF0, 0xF8, 0x00, 0x00, 0x00, 0xF0, 0x79, 0x00, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0xF0, 0xF9, 0x00, 0x00, 0x00, 0xF8, 0xF0, 0x01, 0x00, 0x00, 0x7C, 0xE0, 0x01, 0x00, 0x00, 0x3E, 0xC0, 0x03, 0x00, 0x00, 0x1E, 0x80, 0x07, 0x00, 0x00, 0x0F, 0x80, 0x0F, 0x00, 0x80, 0x0F, 0x00, 0x1F, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x03, 0x00, 0x1C, 0x00, 0x00, 0x01, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char X
+        0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0xFF, 0x1F, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Y
+        0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0xF0, 0x1E, 0x00, 0x00, 0x00, 0x78, 0x1E, 0x00, 0x00, 0x03, 0x7C, 0x1E, 0x00, 0x80, 0x07, 0x3E, 0x1E, 0x00, 0x80, 0x07, 0x1E, 0x1E, 0x00, 0x80, 0x07, 0x0F, 0x1E, 0x00, 0x80, 0x87, 0x07, 0x1E, 0x00, 0x80, 0xC7, 0x03, 0x1E, 0x00, 0x80, 0xE7, 0x03, 0x1E, 0x00, 0x80, 0xF7, 0x01, 0x1E, 0x00, 0x80, 0xFF, 0x00, 0x1E, 0x00, 0x80, 0x7F, 0x00, 0x1E, 0x00, 0x80, 0x3F, 0x00, 0x1E, 0x00, 0x80, 0x3F, 0x00, 0x1E, 0x00, 0x80, 0x1F, 0x00, 0x1E, 0x00, 0x80, 0x0F, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x00, 0x03, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char Z
+        0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x00, 0x03, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char [
+        0x18, 0x00, 0x01, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char BackSlash
+        0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x0C, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ]
+        0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ^
+        0x1B, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char _
+        0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char `
+        0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0x00, 0xFE, 0x0F, 0x00, 0x00, 0x00, 0x1F, 0x0F, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x00, 0x0F, 0x1E, 0x00, 0x00, 0x30, 0x0F, 0x1E, 0x00, 0x00, 0x78, 0x0F, 0x1E, 0x00, 0x00, 0x78, 0x0F, 0x1E, 0x00, 0x00, 0x78, 0x0F, 0x1E, 0x00, 0x00, 0x78, 0x0F, 0x1E, 0x00, 0x00, 0x78, 0x0F, 0x1E, 0x00, 0x00, 0x78, 0x0F, 0x1E, 0x00, 0x00, 0x78, 0x0F, 0x1E, 0x00, 0x00, 0xF0, 0x0F, 0x1F, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0xFF, 0x07, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char a
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x03, 0x00, 0x80, 0xFF, 0xFF, 0x07, 0x00, 0x80, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x1F, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x01, 0x1F, 0x00, 0x00, 0xE0, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0xFF, 0x0F, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char b
+        0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0xE0, 0xFF, 0x07, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xF8, 0x00, 0x1F, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char c
+        0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0xE0, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0x01, 0x1F, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x0F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x07, 0x00, 0x80, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char d
+        0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0xE0, 0xFF, 0x07, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0x78, 0x1F, 0x00, 0x00, 0x78, 0x78, 0x1E, 0x00, 0x00, 0x78, 0x78, 0x1E, 0x00, 0x00, 0x78, 0x78, 0x1E, 0x00, 0x00, 0x78, 0x78, 0x1E, 0x00, 0x00, 0x78, 0x78, 0x1E, 0x00, 0x00, 0x78, 0x78, 0x1E, 0x00, 0x00, 0x78, 0x78, 0x1E, 0x00, 0x00, 0x78, 0x78, 0x0C, 0x00, 0x00, 0x78, 0x78, 0x00, 0x00, 0x00, 0x78, 0x78, 0x00, 0x00, 0x00, 0x78, 0x78, 0x00, 0x00, 0x00, 0x78, 0x78, 0x00, 0x00, 0x00, 0xF8, 0x78, 0x00, 0x00, 0x00, 0xF8, 0x78, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0xE0, 0x7F, 0x00, 0x00, 0x00, 0xC0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char e
+        0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0x0F, 0x00, 0x00, 0xFE, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x80, 0xF7, 0x00, 0x00, 0x00, 0x00, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char f
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0xC0, 0xFF, 0x07, 0x00, 0x00, 0xE0, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0x01, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x9E, 0x01, 0x00, 0xF0, 0x00, 0xDE, 0x03, 0x00, 0xF0, 0x00, 0xDE, 0x03, 0x00, 0xF0, 0x00, 0xDE, 0x03, 0x00, 0xF0, 0x00, 0xDE, 0x03, 0x00, 0xF0, 0x00, 0xDE, 0x03, 0x00, 0xF0, 0x00, 0xDE, 0x03, 0x00, 0xE0, 0x01, 0xDE, 0x03, 0x00, 0xE0, 0x01, 0xFE, 0x01, 0x00, 0xE0, 0xFF, 0xFF, 0x01, 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x00, 0x00, 0x80, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char g
+        0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0xFF, 0x1F, 0x00, 0x00, 0xC0, 0xFF, 0x1F, 0x00, 0x00, 0x80, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char h
+        0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0xE7, 0xFF, 0x0F, 0x00, 0x80, 0xF7, 0xFF, 0x1F, 0x00, 0x80, 0xF7, 0xFF, 0x1F, 0x00, 0x00, 0xE3, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char i
+        0x0C, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x01, 0x00, 0x03, 0x00, 0xF0, 0x01, 0x80, 0xE7, 0xFF, 0xFF, 0x00, 0x80, 0xF7, 0xFF, 0xFF, 0x00, 0x80, 0xF7, 0xFF, 0x7F, 0x00, 0x00, 0xE3, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char j
+        0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0xEF, 0x01, 0x00, 0x00, 0x00, 0xE7, 0x01, 0x00, 0x00, 0x80, 0xC7, 0x03, 0x00, 0x00, 0x80, 0xC3, 0x03, 0x00, 0x00, 0xC0, 0x83, 0x07, 0x00, 0x00, 0xC0, 0x81, 0x07, 0x00, 0x00, 0xE0, 0x01, 0x0F, 0x00, 0x00, 0xE0, 0x00, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0x70, 0x00, 0x1E, 0x00, 0x00, 0x70, 0x00, 0x1C, 0x00, 0x00, 0x20, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char k
+        0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char l
+        0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0xFF, 0x1F, 0x00, 0x00, 0xF0, 0xFF, 0x1F, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0xFF, 0x1F, 0x00, 0x00, 0xF0, 0xFF, 0x1F, 0x00, 0x00, 0xF8, 0xFF, 0x0F, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0xFF, 0x1F, 0x00, 0x00, 0xE0, 0xFF, 0x1F, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char m
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0xFF, 0x1F, 0x00, 0x00, 0xF0, 0xFF, 0x1F, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0xFF, 0x1F, 0x00, 0x00, 0xE0, 0xFF, 0x1F, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char n
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x03, 0x00, 0x00, 0xE0, 0xFF, 0x07, 0x00, 0x00, 0xE0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x0F, 0x00, 0x00, 0xF8, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1F, 0x00, 0x00, 0xF8, 0x00, 0x1F, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0xFF, 0x07, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char o
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0x01, 0x00, 0xE0, 0xFF, 0xFF, 0x03, 0x00, 0xF0, 0xFF, 0xFF, 0x03, 0x00, 0xF0, 0xFF, 0xFF, 0x01, 0x00, 0xF8, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0xF8, 0x00, 0x1F, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0xFF, 0x07, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char p
+        0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x03, 0x00, 0x00, 0xE0, 0xFF, 0x07, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x1F, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x00, 0xF8, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0xFF, 0xFF, 0x03, 0x00, 0xF0, 0xFF, 0xFF, 0x03, 0x00, 0xE0, 0xFF, 0xFF, 0x03, 0x00, 0xC0, 0xFF, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char q
+        0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0xFF, 0x1F, 0x00, 0x00, 0xF0, 0xFF, 0x1F, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char r
+        0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x0C, 0x00, 0x00, 0xE0, 0x0F, 0x1E, 0x00, 0x00, 0xF0, 0x1F, 0x1E, 0x00, 0x00, 0xF0, 0x1F, 0x1E, 0x00, 0x00, 0x78, 0x3E, 0x1E, 0x00, 0x00, 0x78, 0x3C, 0x1E, 0x00, 0x00, 0x78, 0x3C, 0x1E, 0x00, 0x00, 0x78, 0x3C, 0x1E, 0x00, 0x00, 0x78, 0x3C, 0x1E, 0x00, 0x00, 0x78, 0x3C, 0x1E, 0x00, 0x00, 0x78, 0x3C, 0x1E, 0x00, 0x00, 0x78, 0x3C, 0x1E, 0x00, 0x00, 0x30, 0x3C, 0x1E, 0x00, 0x00, 0x00, 0x3C, 0x1E, 0x00, 0x00, 0x00, 0x3C, 0x1E, 0x00, 0x00, 0x00, 0x3C, 0x1E, 0x00, 0x00, 0x00, 0x3C, 0x1F, 0x00, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xF8, 0x07, 0x00, 0x00, 0x00, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char s
+        0x0E, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x80, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char t
+        0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x03, 0x00, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0xE0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0x00, 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char u
+        0x1D, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0xF8, 0x01, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char v
+        0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x00, 0xF8, 0x07, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x00, 0xF8, 0x07, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x03, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char w
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x08, 0x00, 0x00, 0x70, 0x00, 0x1C, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x01, 0x0F, 0x00, 0x00, 0xE0, 0x01, 0x0F, 0x00, 0x00, 0xC0, 0x83, 0x07, 0x00, 0x00, 0x80, 0xC7, 0x03, 0x00, 0x00, 0x80, 0xEF, 0x03, 0x00, 0x00, 0x00, 0xEF, 0x01, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xEF, 0x01, 0x00, 0x00, 0x80, 0xC7, 0x03, 0x00, 0x00, 0xC0, 0xC3, 0x07, 0x00, 0x00, 0xE0, 0x83, 0x07, 0x00, 0x00, 0xE0, 0x01, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0x70, 0x00, 0x1C, 0x00, 0x00, 0x20, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char x
+        0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0x03, 0x00, 0x00, 0xF0, 0xFF, 0x07, 0x00, 0x00, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0xE0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x9E, 0x01, 0x00, 0x00, 0x00, 0xDE, 0x03, 0x00, 0x00, 0x00, 0xDE, 0x03, 0x00, 0x00, 0x00, 0xDE, 0x03, 0x00, 0x00, 0x00, 0xDE, 0x03, 0x00, 0x00, 0x00, 0xDE, 0x03, 0x00, 0x00, 0x00, 0xDE, 0x03, 0x00, 0x00, 0x00, 0xDE, 0x03, 0x00, 0x00, 0x00, 0xDE, 0x03, 0x00, 0xE0, 0xFF, 0xFF, 0x01, 0x00, 0xF0, 0xFF, 0xFF, 0x01, 0x00, 0xF0, 0xFF, 0xFF, 0x00, 0x00, 0xE0, 0xFF, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char y
+        0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0xE0, 0x1E, 0x00, 0x00, 0x60, 0xF0, 0x1E, 0x00, 0x00, 0xF0, 0x70, 0x1E, 0x00, 0x00, 0xF0, 0x38, 0x1E, 0x00, 0x00, 0xF0, 0x3C, 0x1E, 0x00, 0x00, 0xF0, 0x1C, 0x1E, 0x00, 0x00, 0xF0, 0x1E, 0x1E, 0x00, 0x00, 0xF0, 0x0F, 0x1E, 0x00, 0x00, 0xF0, 0x07, 0x1E, 0x00, 0x00, 0xF0, 0x07, 0x1E, 0x00, 0x00, 0xF0, 0x03, 0x1E, 0x00, 0x00, 0xF0, 0x01, 0x1E, 0x00, 0x00, 0xF0, 0x01, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x00, 0x70, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char z
+        0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0xF0, 0xFF, 0xFF, 0x7F, 0x00, 0xF8, 0xFF, 0xFD, 0xFF, 0x00, 0xF8, 0x3F, 0xE0, 0xFF, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x30, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char {
+        0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x01, 0xE0, 0xFF, 0xFF, 0xFF, 0x03, 0xE0, 0xFF, 0xFF, 0xFF, 0x03, 0xC0, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char |
+        0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x60, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0xF8, 0x3F, 0xE0, 0xFF, 0x00, 0xF8, 0xFF, 0xFD, 0xFF, 0x00, 0xF0, 0xFF, 0xFF, 0x7F, 0x00, 0xE0, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char }
+        0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x03, 0x00, 0x00, 0x00, 0xFC, 0x07, 0x00, 0x00, 0x00, 0xF8, 0x07, 0x00, 0x00, 0x00, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0xF8, 0x07, 0x00, 0x00, 0x00, 0xF8, 0x03, 0x00, 0x00, 0x00, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  // Code for char ~
+        0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x0F, 0x00, 0xFF, 0xFF, 0xFF, 0x1F, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0xFF, 0xFF, 0xFF, 0x1F, 0x00, 0xFE, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00   // Code for char 
+        };
+        
+        
+        
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/JsonParser.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,297 @@
+/*
+ *
+ *	Compact JSON format parsing lib (native cross-platform c++)
+ *
+ *	Copyright (C) 2013 Victor Laskin (victor.laskin@gmail.com)
+ *	Details: http://vitiy.info/?p=102
+ *
+ *	Redistribution and use in source and binary forms, with or without
+ *	modification, are permitted provided that the following conditions
+ *	are met:
+ *	1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  3. The names of the authors may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ *	THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS
+ *	OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *	WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *	ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ *	DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *	DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ *	GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ *	IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *	OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ *	IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "JsonParser.h"
+
+namespace JSON {
+
+
+MVJSONReader::MVJSONReader(const string & source) {
+	root = parse(source);
+}
+
+MVJSONReader::~MVJSONReader() {
+	if (root != NULL)
+		delete root;
+}
+
+MVJSONNode::~MVJSONNode() {
+	if (values.size() > 0)
+		for (int i = 0; i < values.size(); i++)
+			delete values.at(i);
+}
+
+
+
+MVJSONNode* MVJSONReader::parse(string text)
+{
+	string s = trim(text);
+	if (s.length() < 2) return NULL;
+
+	// object
+	if ((s[0] == '{') && (s[s.length() - 1] == '}'))
+	{
+		// erase last and first symbols
+		s.erase(0, 1);
+		s.erase(s.length() - 1, 1);
+
+		vector<string> parts;
+		splitList(s, parts);
+
+		MVJSONNode* node = new MVJSONNode();
+
+		for (int i = 0; i < parts.size(); i++)
+			node->values.push_back(parseValue(parts.at(i), false));
+
+		return node;
+	}
+
+	return NULL;
+}
+
+
+
+
+MVJSONValue* MVJSONReader::parseValue(string text, bool hasNoName)
+{
+	string key;
+	string s;
+	splitInHalf(text, ":", key, s);
+	key = trim(key);
+	s = trim(s);
+	if (key.length() > 2)
+	{
+		// strip "
+		key.erase(0, 1);
+		key.erase(key.length() - 1, 1);
+	}
+
+	if (hasNoName)
+	{
+		s = text;
+		key = "";
+	}
+
+
+	if (s == "false") // bool
+		return new MVJSONValue(key, false);
+
+	if (s == "true")  // bool
+		return new MVJSONValue(key, true);
+
+	if (s == "null") // null
+		return new MVJSONValue(key, MVJSON_TYPE_NULL);
+
+	char first = s[0];
+
+	if (first == '"') // string
+		return new MVJSONValue(key, s.substr(1, s.length() - 2));
+
+	if (first == '{') // object
+		return new MVJSONValue(key, parse(s));
+
+	if (first == '[') // array
+	{
+		s.erase(0, 1);
+		s.erase(s.length() - 1, 1);
+		vector<string> parts;
+		splitList(s, parts);
+
+		MVJSONValue* val = new MVJSONValue(key, MVJSON_TYPE_ARRAY);
+		for (int i = 0; i < parts.size(); i++)
+			val->arrayValue.push_back(parseValue(parts.at(i), true));
+		return val;
+	}
+
+	// else its number!
+	if (s.find(".") == string::npos)
+		return new MVJSONValue(key, stringToInt(s));
+	else
+		return new MVJSONValue(key, stringToDouble(s));
+
+}
+
+MVJSONValue::~MVJSONValue()
+{
+	if (objValue != NULL)
+		delete objValue;
+	if (arrayValue.size() > 0)
+		for (int i = 0; i < arrayValue.size(); i++)
+			delete arrayValue.at(i);
+}
+
+void MVJSONValue::init(MVJSON_TYPE valueType)
+{
+	this->valueType = valueType;
+	objValue = NULL;
+	name = "";
+}
+
+MVJSONValue::MVJSONValue(string name, MVJSON_TYPE valueType)
+{
+	init(valueType);
+	this->name = name;
+}
+
+MVJSONValue::MVJSONValue(string name, bool value)
+{
+	init(MVJSON_TYPE_BOOL);
+	this->name = name;
+	boolValue = value;
+}
+
+MVJSONValue::MVJSONValue(string name, string value)
+{
+	init(MVJSON_TYPE_STRING);
+	this->name = name;
+
+	stringValue = value;
+
+	// here we switch back special chars
+	//	\"	\\	\/	\b	\f	\n	\r	\t	\u four-hex-digits
+	replace(stringValue, "\\\"", "\"");
+	replace(stringValue, "\\\\", "\\");
+	replace(stringValue, "\\/", "/");
+	replace(stringValue, "\\b", "\b");
+	replace(stringValue, "\\f", "\f");
+	replace(stringValue, "\\n", "\n");
+	replace(stringValue, "\\r", "\r");
+	replace(stringValue, "\\t", "\t");
+
+	// TODO - \u four-hex-digits
+	// SS::replace(stringValue, "\\\\", "\\");
+
+}
+
+MVJSONValue::MVJSONValue(string name, int value)
+{
+	init(MVJSON_TYPE_INT);
+	this->name = name;
+	intValue = value;
+}
+
+MVJSONValue::MVJSONValue(string name, double value)
+{
+	init(MVJSON_TYPE_DOUBLE);
+	this->name = name;
+	doubleValue = value;
+}
+
+MVJSONValue::MVJSONValue(string name, MVJSONNode* value)
+{
+	init(MVJSON_TYPE_OBJECT);
+	this->name = name;
+	objValue = value;
+}
+
+bool MVJSONNode::hasField(string name)
+{
+	if (values.size() == 0) return false;
+	for (int i = 0; i < values.size(); i++)
+		if (values.at(i)->name == name)
+			return true;
+	return false;
+}
+
+MVJSONValue* MVJSONNode::getField(string name)
+{
+	if (values.size() == 0) return NULL;
+	for (int i = 0; i < values.size(); i++)
+		if (values.at(i)->name == name)
+			return values.at(i);
+	return NULL;
+}
+
+
+double MVJSONNode::getFieldDouble(string name)
+{
+	MVJSONValue* value = getField(name);
+	if (value == NULL) return 0;
+	if (value->valueType == MVJSON_TYPE_INT) return value->intValue;
+	if (value->valueType == MVJSON_TYPE_DOUBLE) return value->doubleValue;
+	return 0;
+}
+
+int MVJSONNode::getFieldInt(string name)
+{
+	MVJSONValue* value = getField(name);
+	if (value == NULL) return 0;
+	if (value->valueType == MVJSON_TYPE_INT) return value->intValue;
+	return 0;
+}
+
+string MVJSONNode::getFieldString(string name)
+{
+	MVJSONValue* value = getField(name);
+	if (value == NULL) return "";
+	if (value->valueType == MVJSON_TYPE_STRING) return value->stringValue;
+	return "";
+}
+
+bool MVJSONNode::getFieldBool(string name)
+{
+	MVJSONValue* value = getField(name);
+	if (value == NULL) return false;
+	if (value->valueType == MVJSON_TYPE_INT) return (bool)value->intValue;
+	if (value->valueType == MVJSON_TYPE_BOOL) return value->boolValue;
+	return false;
+}
+
+double MVJSONValue::getFieldDouble(string name)
+{
+	if (objValue == NULL) return 0;
+	return objValue->getFieldDouble(name);
+}
+
+int MVJSONValue::getFieldInt(string name)
+{
+	if (objValue == NULL) return 0;
+	return objValue->getFieldInt(name);
+}
+
+string MVJSONValue::getFieldString(string name)
+{
+	if (objValue == NULL) return "";
+	return objValue->getFieldString(name);
+}
+
+bool MVJSONValue::getFieldBool(string name)
+{
+	if (objValue == NULL) return false;
+	return objValue->getFieldBool(name);
+}
+
+
+} /* namespace F2 */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/JsonParser.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,261 @@
+/*
+ *
+ *	Compact JSON format parsing lib (native cross-platform c++)
+ *
+ *	Copyright (C) 2013 Victor Laskin (victor.laskin@gmail.com)
+ *	Details: http://vitiy.info/?p=102
+ *
+ *	Redistribution and use in source and binary forms, with or without
+ *	modification, are permitted provided that the following conditions
+ *	are met:
+ *	1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  3. The names of the authors may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ *	THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS
+ *	OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ *	WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *	ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ *	DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *	DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ *	GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ *	IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *	OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ *	IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+
+#include <string>
+#include <vector>
+#include <stdlib.h>
+
+#ifndef MVJSON_H_
+#define MVJSON_H_
+
+using namespace std;
+
+namespace JSON {
+
+/// JSON node types
+enum MVJSON_TYPE
+{
+	MVJSON_TYPE_NULL,
+	MVJSON_TYPE_OBJECT,
+	MVJSON_TYPE_ARRAY,
+	MVJSON_TYPE_STRING,
+	MVJSON_TYPE_INT,
+	MVJSON_TYPE_DOUBLE,
+	MVJSON_TYPE_BOOL
+};
+
+class MVJSONUtils {
+protected:
+
+	// string parsing functions
+	inline static int stringToInt(const string & s);											///< convert string to int
+	inline static double stringToDouble(const string & s);										///< convert string to float
+	inline static bool symbolToBeTrimmed(const char& c);										///< check if symbol is space, tab or new line break
+	inline static string trim(const string & text);												///< trim spaces, tabs and line break
+	inline static void replace(string & target, const string & oldStr, const string & newStr);  ///< replace all occurrences of substring
+	inline static void splitInHalf(const string & s, const string & separator, string & begin, string & end);	///< second half (output)
+	inline static void splitList(const string & s,  vector<string> & parts);
+};
+
+
+class MVJSONNode;
+
+/// JSON Value
+class MVJSONValue : public MVJSONUtils {
+public:
+	MVJSONValue(string name, MVJSON_TYPE valueType);
+	MVJSONValue(string name, bool value);
+	MVJSONValue(string name, string value);
+	MVJSONValue(string name, int value);
+	MVJSONValue(string name, double value);
+	MVJSONValue(string name, MVJSONNode* value);
+	virtual ~MVJSONValue();
+
+	string name;							///< value name [optional]
+	MVJSON_TYPE valueType;					///< type of node
+
+	string stringValue;						///< value if data has string type
+	bool boolValue;							///< value if data has bool type
+	int intValue;							///< value if data has int type
+	double doubleValue;						///< value if data has double type
+	MVJSONNode* objValue;					///< value if data has object type
+
+	vector<MVJSONValue*> arrayValue;		///< array of values
+
+	double getFieldDouble(string name);		///< get value of double field of VALUE OBJECT (objValue)
+	int getFieldInt(string name);			///< get value of int field of VALUE OBJECT (objValue)
+	string getFieldString(string name);		///< get value of string field of VALUE OBJECT (objValue)
+	bool getFieldBool(string name);			///< get value of bool field of VALUE OBJECT (objValue)
+
+	inline MVJSONValue* at(unsigned int i){ return arrayValue.at(i); }
+	inline int size() { if (valueType == MVJSON_TYPE_ARRAY) return arrayValue.size(); else return 1; }
+private:
+	void init(MVJSON_TYPE valueType);
+};
+
+/// JSON Node (Object)
+class MVJSONNode {
+public:
+
+	virtual ~MVJSONNode();
+
+	vector<MVJSONValue*> values; 			///< values (props)
+
+	bool hasField(string name);				///< check that object has field
+	MVJSONValue* getField(string name);		///< get field by name
+
+	double getFieldDouble(string name);		///< get value of double field
+	int getFieldInt(string name);			///< get value of int field
+	string getFieldString(string name);		///< get value of string field
+	bool getFieldBool(string name);			///< get value of bool field
+};
+
+/// Compact JSON parser (based on specification: http://www.json.org/)
+class MVJSONReader : public MVJSONUtils {
+public:
+	MVJSONReader(const string & source);	///< constructor from json source
+	virtual ~MVJSONReader();
+
+	MVJSONNode* root;						///< root object (if its null - parsing was failed)
+
+private:
+	MVJSONValue* parseValue(string text, bool hasNoName);					///< parse value
+	MVJSONNode* parse(string text);											///< parse node
+
+
+};
+
+
+
+// ------------------- inlined string processing functions ------------->
+
+
+inline int MVJSONUtils::stringToInt(const string & s)
+{
+	return atoi(s.c_str());
+}
+
+
+inline double MVJSONUtils::stringToDouble(const string & s)
+{
+	return atof(s.c_str());
+}
+
+
+inline bool MVJSONUtils::symbolToBeTrimmed(const char& c   ///< the char to test
+)
+{
+	if (c == ' ') return true;
+	if (c == '\n') return true;
+	if (c == '\r') return true;
+	if (c == '\t') return true;
+	return false;
+}
+
+
+inline string  MVJSONUtils::trim(const string & text  ///< the text to trim
+)
+{
+	if (text.length() == 0) return "";
+	int start = 0;
+	while ((start < text.length()) && (symbolToBeTrimmed(text[start]))) start++;
+	int end = text.length() - 1;
+	while ((end > 0) && (symbolToBeTrimmed(text[end]))) end--;
+	if (start > end) return "";
+
+	return text.substr(start, end - start + 1);
+}
+
+inline void MVJSONUtils::splitInHalf(const string & s,						///< source string to split up
+									  const string & separator,				///< separator string)
+									  string & begin,						///< first part (output)
+									  string & end							///< second half (output)
+)
+{
+	int pos = s.find(separator);
+	if (pos == string::npos) { begin = s; end = ""; return; }
+
+	begin = s.substr(0, pos);
+	end = s.substr(pos + separator.length(), s.length() - pos - separator.length());
+}
+
+/// split string by "," - ignore content inside of "{", "}", "[", "]" and quotations "...."
+/// also take \" into account
+/// (Code should be cleared of comments beforehand)
+inline void MVJSONUtils::splitList(const string & s,				///< string to be splitted
+									vector<string> & parts			///< result parts
+)
+{
+
+	bool isNotInQuotes = true;
+	int b1 = 0;
+	int b2 = 0;
+	int lastPos = 0;
+
+	const char* start = s.c_str();
+	const char* ps = start;
+
+	while (*ps) // *ps != 0
+	{
+		if ((*ps == ',') && (isNotInQuotes) && (b1 == 0) && (b2 == 0))
+		{
+			parts.push_back(s.substr(lastPos, ps - start - lastPos));
+			lastPos = ps - start + 1;
+		}
+
+		if (isNotInQuotes)
+		{
+			if (*ps == '{') b1++;
+			if (*ps == '}') b1--;
+			if (*ps == '[') b2++;
+			if (*ps == ']') b2--;
+		}
+
+		if (*ps == '"')
+		{
+			isNotInQuotes = !isNotInQuotes;
+			if (ps != start)
+				if (*(ps-1) == '\\')
+					isNotInQuotes = !isNotInQuotes;
+		}
+
+		ps++;
+	}
+
+	parts.push_back(s.substr(lastPos, s.length() - lastPos));
+}
+
+inline void MVJSONUtils::replace(string & target,			///< text to be modified
+								  const string & oldStr,		///< old string
+								  const string & newStr		///< new string
+)
+{
+	unsigned int pos = 0;
+	unsigned int oldLen = oldStr.length();
+	unsigned int newLen = newStr.length();
+
+	for (;;)
+	{
+		pos = target.find(oldStr, pos);
+		if (pos == string::npos) break;
+		target.replace(pos, oldLen, newStr);
+		pos += newLen;
+	}
+}
+
+
+} /* namespace F2 */
+#endif /* MVJSON_H_ */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Nucleo_blink_led.uvgui.Vergil	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,2672 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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+
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+      <ViewName>Watch 1</ViewName>
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+      <TableColWidths>133 133 133</TableColWidths>
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--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Nucleo_blink_led.uvgui_Vergil.bak	Wed Oct 08 11:00:24 2014 +0000
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--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Nucleo_blink_led.uvproj	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,6073 @@
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+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
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+  <SchemaVersion>1.1</SchemaVersion>
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+  <Header>### uVision Project, (C) Keil Software</Header>
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+          <Cmp></Cmp>
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+          </TargetStatus>
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+              <FilePath>.\mbed-rtos\rtos\Thread.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>HAL_CM.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\HAL_CM.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_CMSIS.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_CMSIS.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_Event.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_Event.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_List.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_List.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_Mailbox.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_Mailbox.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_MemBox.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_MemBox.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_Mutex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_Mutex.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_Robin.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_Robin.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_Semaphore.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_Semaphore.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_System.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_System.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_Task.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_Task.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_Time.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_Time.c</FilePath>
+            </File>
+            <File>
+              <FileName>RTX_Conf_CM.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\RTX_Conf_CM.c</FilePath>
+            </File>
+            <File>
+              <FileName>HAL_CM4.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\TARGET_M4\TOOLCHAIN_ARM\HAL_CM4.c</FilePath>
+            </File>
+            <File>
+              <FileName>SVC_Table.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\mbed-rtos\rtx\TARGET_M4\TOOLCHAIN_ARM\SVC_Table.s</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>SDFileSystem</GroupName>
+          <Files>
+            <File>
+              <FileName>SDFileSystem.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\SDFileSystem\SDFileSystem.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>FATDirHandle.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\SDFileSystem\FATFileSystem\FATDirHandle.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>FATFileHandle.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\SDFileSystem\FATFileSystem\FATFileHandle.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>FATFileSystem.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\SDFileSystem\FATFileSystem\FATFileSystem.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>ccsbcs.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\SDFileSystem\FATFileSystem\ChaN\ccsbcs.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>diskio.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\SDFileSystem\FATFileSystem\ChaN\diskio.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>ff.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\SDFileSystem\FATFileSystem\ChaN\ff.cpp</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CC3000</GroupName>
+          <Files>
+            <File>
+              <FileName>cc3000.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>cc3000_event.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000_event.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>cc3000_hci.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000_hci.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>cc3000_netapp.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000_netapp.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>cc3000_nvmem.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000_nvmem.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>cc3000_security.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000_security.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>cc3000_socket.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000_socket.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>cc3000_spi.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000_spi.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>cc3000_wlan.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000_wlan.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>Endpoint.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\Socket\Endpoint.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>Socket.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\Socket\Socket.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>TCPSocketConnection.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\Socket\TCPSocketConnection.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>TCPSocketServer.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\Socket\TCPSocketServer.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>UDPSocket.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\Socket\UDPSocket.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>cc3000_simplelink.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000_simplelink.cpp</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>ILI9341</GroupName>
+          <Files>
+            <File>
+              <FileName>GraphicsDisplay.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\ILI9341\GraphicsDisplay.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>SPI_TFT_ILI9341.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\ILI9341\SPI_TFT_ILI9341.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>SPI_TFT_ILI9341_NUCLEO.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\ILI9341\SPI_TFT_ILI9341_NUCLEO.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>SPI_TFT_ILI9341_NXP.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\ILI9341\SPI_TFT_ILI9341_NXP.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>TextDisplay.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\ILI9341\TextDisplay.cpp</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Nucleo_blink_led_mbed NUCLEO_F401RE.dep	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,10994 @@
+Dependencies for Project 'Nucleo_blink_led', Target 'mbed NUCLEO_F401RE': (DO NOT MODIFY !)
+F (main.cpp)(0x53FDA45E)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\main.o --omf_browse .\build\main.crf --depend .\build\main.d)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (mbed-rtos/rtx/cmsis_os.h)(0x53F6BCA0)
+I (mbed-rtos/rtx/os_tcb.h)(0x53F6BCA0)
+I (DHT\DHT.h)(0x53FB4593)
+I (mbed-rtos/rtos/Mutex.h)(0x53F6BCA0)
+I (SDFileSystem\SDFileSystem.h)(0x53F6BCA0)
+I (SDFileSystem/FATFileSystem/FATFileSystem.h)(0x53FA33B1)
+I (mbed-src/api/FileSystemLike.h)(0x53F945A0)
+I (mbed-src/api/DirHandle.h)(0x53F945A0)
+I (SDFileSystem/FATFileSystem/ChaN/ff.h)(0x53F6BCA0)
+I (SDFileSystem/FATFileSystem/ChaN/integer.h)(0x53F6BCA0)
+I (SDFileSystem/FATFileSystem/ChaN/ffconf.h)(0x53F6BCA0)
+I (CC3000\cc3000.h)(0x53F6BCA0)
+I (CC3000\cc3000_common.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\errno.h)(0x53463A44)
+I (CC3000\cc3000_spi.h)(0x53F6BCA0)
+I (CC3000\cc3000_simplelink.h)(0x53F6BCA0)
+I (CC3000\cc3000_netapp.h)(0x53F6BCA0)
+I (CC3000\cc3000_nvmem.h)(0x53F6BCA0)
+I (CC3000\cc3000_socket.h)(0x53F6BCA0)
+I (ILI9341\SPI_TFT_ILI9341.h)(0x53F6BCA0)
+I (ILI9341\GraphicsDisplay.h)(0x53F6BCA0)
+I (ILI9341\TextDisplay.h)(0x53F6BCA0)
+I (ILI9341\Arial12x12.h)(0x53FA99A0)
+I (ILI9341\Arial24x23.h)(0x53FA99A0)
+I (ILI9341\Arial28x28.h)(0x53FCC3D4)
+I (ILI9341\font_big.h)(0x53FCC3D4)
+I (Shell.h)(0x53FD7822)
+I (ini.h)(0x52B349DF)
+I (Utility.h)(0x53FDA38A)
+I (C:\Keil_v5\ARM\ARMCC\include\string)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\iosfwd)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_defs.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_config.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\config.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cwchar)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\wchar.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\limits)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cmath)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cfloat)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\float.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\climits)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\limits.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_algobase.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\utility)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_iterator.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_iterbase.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_strref.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\memory)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\new)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\exception)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_mutex.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_traits.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_error.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\vector)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_dispatch.h)(0x53463A44)
+I (HttpClient.h)(0x53FCB215)
+I (C:\Keil_v5\ARM\ARMCC\include\map)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\functional)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_tree.h)(0x53463A44)
+I (CC3000/Socket/TCPSocketConnection.h)(0x53F78B04)
+I (CC3000/Socket/Socket.h)(0x53F6BCA0)
+I (CC3000/Socket/Endpoint.h)(0x53F6BCA0)
+I (JsonParser.h)(0x53FCCD11)
+I (CC3000/Socket/TCPSocketServer.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\string.CC)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_tree.CC)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\vector.CC)(0x53463A44)
+F (.\Shell.cpp)(0x53FD7965)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\shell.o --omf_browse .\build\shell.crf --depend .\build\shell.d)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
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+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
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+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
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+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
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+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (mbed-rtos/rtx/cmsis_os.h)(0x53F6BCA0)
+I (mbed-rtos/rtx/os_tcb.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\vector)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\limits)(0x53463A44)
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+I (C:\Keil_v5\ARM\ARMCC\include\rw\_config.h)(0x53463A44)
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+I (C:\Keil_v5\ARM\ARMCC\include\rw\_math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cmath)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cfloat)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\float.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\climits)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\limits.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\memory)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\new)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\exception)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\utility)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_iterbase.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_mutex.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_algobase.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_iterator.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_dispatch.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_error.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\iosfwd)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cwchar)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\wchar.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_strref.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_traits.h)(0x53463A44)
+I (Shell.h)(0x53FD7822)
+I (Utility.h)(0x53FDA38A)
+I (DHT\DHT.h)(0x53FB4593)
+I (mbed-rtos/rtos/Mutex.h)(0x53F6BCA0)
+I (SDFileSystem\SDFileSystem.h)(0x53F6BCA0)
+I (SDFileSystem/FATFileSystem/FATFileSystem.h)(0x53FA33B1)
+I (mbed-src/api/FileSystemLike.h)(0x53F945A0)
+I (mbed-src/api/DirHandle.h)(0x53F945A0)
+I (SDFileSystem/FATFileSystem/ChaN/ff.h)(0x53F6BCA0)
+I (SDFileSystem/FATFileSystem/ChaN/integer.h)(0x53F6BCA0)
+I (SDFileSystem/FATFileSystem/ChaN/ffconf.h)(0x53F6BCA0)
+I (ILI9341\SPI_TFT_ILI9341.h)(0x53F6BCA0)
+I (ILI9341\GraphicsDisplay.h)(0x53F6BCA0)
+I (ILI9341\TextDisplay.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\string.CC)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\vector.CC)(0x53463A44)
+F (.\Utility.cpp)(0x53FDA3C9)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\utility.o --omf_browse .\build\utility.crf --depend .\build\utility.d)
+I (Utility.h)(0x53FDA38A)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\string)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\iosfwd)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_defs.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_config.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\config.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cwchar)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\wchar.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\limits)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cmath)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cfloat)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\float.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\climits)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\limits.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_algobase.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\utility)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_iterator.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_iterbase.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_strref.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\memory)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\new)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\exception)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_mutex.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_traits.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_error.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\vector)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_dispatch.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdarg.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cctype)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\ctype.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\algorithm)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.CC)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\vector.CC)(0x53463A44)
+F (.\ini.c)(0x52B3496D)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\ini.o --omf_browse .\build\ini.crf --depend .\build\ini.d)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\ctype.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (ini.h)(0x52B349DF)
+F (.\HttpClient.cpp)(0x53FD7D68)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\httpclient.o --omf_browse .\build\httpclient.crf --depend .\build\httpclient.d)
+I (HttpClient.h)(0x53FCB215)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\string)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\iosfwd)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_defs.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_config.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\config.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cwchar)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\wchar.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\limits)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cmath)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cfloat)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\float.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\climits)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\limits.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_algobase.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\utility)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_iterator.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_iterbase.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_strref.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\memory)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\new)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\exception)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_mutex.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_traits.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_error.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\map)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\functional)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_tree.h)(0x53463A44)
+I (CC3000/Socket/TCPSocketConnection.h)(0x53F78B04)
+I (CC3000/Socket/Socket.h)(0x53F6BCA0)
+I (CC3000\cc3000.h)(0x53F6BCA0)
+I (CC3000\cc3000_common.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\errno.h)(0x53463A44)
+I (CC3000\cc3000_spi.h)(0x53F6BCA0)
+I (CC3000\cc3000_simplelink.h)(0x53F6BCA0)
+I (CC3000\cc3000_netapp.h)(0x53F6BCA0)
+I (CC3000\cc3000_nvmem.h)(0x53F6BCA0)
+I (CC3000\cc3000_socket.h)(0x53F6BCA0)
+I (CC3000/Socket/Endpoint.h)(0x53F6BCA0)
+I (Utility.h)(0x53FDA38A)
+I (C:\Keil_v5\ARM\ARMCC\include\vector)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_dispatch.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.CC)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_tree.CC)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\vector.CC)(0x53463A44)
+F (.\JsonParser.cpp)(0x53FCCD6E)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\jsonparser.o --omf_browse .\build\jsonparser.crf --depend .\build\jsonparser.d)
+I (JsonParser.h)(0x53FCCD11)
+I (C:\Keil_v5\ARM\ARMCC\include\string)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\iosfwd)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_defs.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_config.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\config.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cwchar)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\wchar.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\limits)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cmath)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cfloat)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\float.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\climits)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\limits.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_algobase.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\utility)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_iterator.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_iterbase.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_strref.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\memory)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\new)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\exception)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_mutex.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_traits.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_error.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\vector)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_dispatch.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.CC)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\vector.CC)(0x53463A44)
+F (DHT/DHT.cpp)(0x53FB4593)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\dht.o --omf_browse .\build\dht.crf --depend .\build\dht.d)
+I (DHT/DHT.h)(0x53FB4593)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (mbed-rtos/rtx/cmsis_os.h)(0x53F6BCA0)
+I (mbed-rtos/rtx/os_tcb.h)(0x53F6BCA0)
+I (mbed-rtos/rtos/Mutex.h)(0x53F6BCA0)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/startup_stm32f401xe.s)(0x53FABF37)(--cpu Cortex-M4.fp -g --apcs=interwork 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include



--list .\build\startup_stm32f401xe.lst --xref -o .\build\startup_stm32f401xe.o --depend .\build\startup_stm32f401xe.d)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_iwdg.o --omf_browse .\build\stm32f4xx_hal_iwdg.crf --depend .\build\stm32f4xx_hal_iwdg.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_sdram.o --omf_browse .\build\stm32f4xx_hal_sdram.crf --depend .\build\stm32f4xx_hal_sdram.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_ll_sdmmc.o --omf_browse .\build\stm32f4xx_ll_sdmmc.crf --depend .\build\stm32f4xx_ll_sdmmc.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_dma_ex.o --omf_browse .\build\stm32f4xx_hal_dma_ex.crf --depend .\build\stm32f4xx_hal_dma_ex.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\system_stm32f4xx.o --omf_browse .\build\system_stm32f4xx.crf --depend .\build\system_stm32f4xx.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/hal_tick.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_can.o --omf_browse .\build\stm32f4xx_hal_can.crf --depend .\build\stm32f4xx_hal_can.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_hcd.o --omf_browse .\build\stm32f4xx_hal_hcd.crf --depend .\build\stm32f4xx_hal_hcd.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_sai.o --omf_browse .\build\stm32f4xx_hal_sai.crf --depend .\build\stm32f4xx_hal_sai.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_nor.o --omf_browse .\build\stm32f4xx_hal_nor.crf --depend .\build\stm32f4xx_hal_nor.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_dac.o --omf_browse .\build\stm32f4xx_hal_dac.crf --depend .\build\stm32f4xx_hal_dac.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_i2c_ex.o --omf_browse .\build\stm32f4xx_hal_i2c_ex.crf --depend .\build\stm32f4xx_hal_i2c_ex.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rng.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_rng.o --omf_browse .\build\stm32f4xx_hal_rng.crf --depend .\build\stm32f4xx_hal_rng.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_crc.o --omf_browse .\build\stm32f4xx_hal_crc.crf --depend .\build\stm32f4xx_hal_crc.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/hal_tick.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\hal_tick.o --omf_browse .\build\hal_tick.crf --depend .\build\hal_tick.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/hal_tick.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\cmsis_nvic.o --omf_browse .\build\cmsis_nvic.crf --depend .\build\cmsis_nvic.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_irda.o --omf_browse .\build\stm32f4xx_hal_irda.crf --depend .\build\stm32f4xx_hal_irda.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_pwr.o --omf_browse .\build\stm32f4xx_hal_pwr.crf --depend .\build\stm32f4xx_hal_pwr.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_flash.o --omf_browse .\build\stm32f4xx_hal_flash.crf --depend .\build\stm32f4xx_hal_flash.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_adc.o --omf_browse .\build\stm32f4xx_hal_adc.crf --depend .\build\stm32f4xx_hal_adc.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_ltdc.o --omf_browse .\build\stm32f4xx_hal_ltdc.crf --depend .\build\stm32f4xx_hal_ltdc.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_adc_ex.o --omf_browse .\build\stm32f4xx_hal_adc_ex.crf --depend .\build\stm32f4xx_hal_adc_ex.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_usart.o --omf_browse .\build\stm32f4xx_hal_usart.crf --depend .\build\stm32f4xx_hal_usart.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_flash_ex.o --omf_browse .\build\stm32f4xx_hal_flash_ex.crf --depend .\build\stm32f4xx_hal_flash_ex.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_wwdg.o --omf_browse .\build\stm32f4xx_hal_wwdg.crf --depend .\build\stm32f4xx_hal_wwdg.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_cryp.o --omf_browse .\build\stm32f4xx_hal_cryp.crf --depend .\build\stm32f4xx_hal_cryp.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_tim_ex.o --omf_browse .\build\stm32f4xx_hal_tim_ex.crf --depend .\build\stm32f4xx_hal_tim_ex.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal.o --omf_browse .\build\stm32f4xx_hal.crf --depend .\build\stm32f4xx_hal.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_sram.o --omf_browse .\build\stm32f4xx_hal_sram.crf --depend .\build\stm32f4xx_hal_sram.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_rtc_ex.o --omf_browse .\build\stm32f4xx_hal_rtc_ex.crf --depend .\build\stm32f4xx_hal_rtc_ex.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_i2s_ex.o --omf_browse .\build\stm32f4xx_hal_i2s_ex.crf --depend .\build\stm32f4xx_hal_i2s_ex.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_dcmi.o --omf_browse .\build\stm32f4xx_hal_dcmi.crf --depend .\build\stm32f4xx_hal_dcmi.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_dma.o --omf_browse .\build\stm32f4xx_hal_dma.crf --depend .\build\stm32f4xx_hal_dma.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_hash.o --omf_browse .\build\stm32f4xx_hal_hash.crf --depend .\build\stm32f4xx_hal_hash.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_i2s.o --omf_browse .\build\stm32f4xx_hal_i2s.crf --depend .\build\stm32f4xx_hal_i2s.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_rcc_ex.o --omf_browse .\build\stm32f4xx_hal_rcc_ex.crf --depend .\build\stm32f4xx_hal_rcc_ex.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_eth.o --omf_browse .\build\stm32f4xx_hal_eth.crf --depend .\build\stm32f4xx_hal_eth.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_fsmc.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_ll_fsmc.o --omf_browse .\build\stm32f4xx_ll_fsmc.crf --depend .\build\stm32f4xx_ll_fsmc.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_i2c.o --omf_browse .\build\stm32f4xx_hal_i2c.crf --depend .\build\stm32f4xx_hal_i2c.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac_ex.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_dac_ex.o --omf_browse .\build\stm32f4xx_hal_dac_ex.crf --depend .\build\stm32f4xx_hal_dac_ex.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_smartcard.o --omf_browse .\build\stm32f4xx_hal_smartcard.crf --depend .\build\stm32f4xx_hal_smartcard.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_sd.o --omf_browse .\build\stm32f4xx_hal_sd.crf --depend .\build\stm32f4xx_hal_sd.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_pccard.o --omf_browse .\build\stm32f4xx_hal_pccard.crf --depend .\build\stm32f4xx_hal_pccard.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_cortex.o --omf_browse .\build\stm32f4xx_hal_cortex.crf --depend .\build\stm32f4xx_hal_cortex.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_uart.o --omf_browse .\build\stm32f4xx_hal_uart.crf --depend .\build\stm32f4xx_hal_uart.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_gpio.o --omf_browse .\build\stm32f4xx_hal_gpio.crf --depend .\build\stm32f4xx_hal_gpio.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_pcd.o --omf_browse .\build\stm32f4xx_hal_pcd.crf --depend .\build\stm32f4xx_hal_pcd.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_tim.o --omf_browse .\build\stm32f4xx_hal_tim.crf --depend .\build\stm32f4xx_hal_tim.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_nand.o --omf_browse .\build\stm32f4xx_hal_nand.crf --depend .\build\stm32f4xx_hal_nand.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_ll_usb.o --omf_browse .\build\stm32f4xx_ll_usb.crf --depend .\build\stm32f4xx_ll_usb.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_spi.o --omf_browse .\build\stm32f4xx_hal_spi.crf --depend .\build\stm32f4xx_hal_spi.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_pwr_ex.o --omf_browse .\build\stm32f4xx_hal_pwr_ex.crf --depend .\build\stm32f4xx_hal_pwr_ex.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash_ex.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_hash_ex.o --omf_browse .\build\stm32f4xx_hal_hash_ex.crf --depend .\build\stm32f4xx_hal_hash_ex.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_rcc.o --omf_browse .\build\stm32f4xx_hal_rcc.crf --depend .\build\stm32f4xx_hal_rcc.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_rtc.o --omf_browse .\build\stm32f4xx_hal_rtc.crf --depend .\build\stm32f4xx_hal_rtc.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_dma2d.o --omf_browse .\build\stm32f4xx_hal_dma2d.crf --depend .\build\stm32f4xx_hal_dma2d.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_fmc.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_ll_fmc.o --omf_browse .\build\stm32f4xx_ll_fmc.crf --depend .\build\stm32f4xx_ll_fmc.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp_ex.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stm32f4xx_hal_cryp_ex.o --omf_browse .\build\stm32f4xx_hal_cryp_ex.crf --depend .\build\stm32f4xx_hal_cryp_ex.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+F (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/spi_api.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\spi_api.o --omf_browse .\build\spi_api.crf --depend .\build\spi_api.d)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (mbed-src/hal/pinmap.h)(0x53F945A0)
+F (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/analogin_api.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\analogin_api.o --omf_browse .\build\analogin_api.crf --depend .\build\analogin_api.d)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/pinmap.h)(0x53F945A0)
+F (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_api.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\gpio_api.o --omf_browse .\build\gpio_api.crf --depend .\build\gpio_api.d)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/hal/pinmap.h)(0x53F945A0)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+F (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/rtc_api.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\rtc_api.o --omf_browse .\build\rtc_api.crf --depend .\build\rtc_api.d)
+I (mbed-src/hal/rtc_api.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+F (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_irq_api.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\gpio_irq_api.o --omf_browse .\build\gpio_irq_api.crf --depend .\build\gpio_irq_api.d)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (mbed-src/hal/pinmap.h)(0x53F945A0)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+F (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/serial_api.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\serial_api.o --omf_browse .\build\serial_api.crf --depend .\build\serial_api.d)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/hal/pinmap.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+F (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/mbed_overrides.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\mbed_overrides.o --omf_browse .\build\mbed_overrides.crf --depend .\build\mbed_overrides.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+F (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/pwmout_api.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\pwmout_api.o --omf_browse .\build\pwmout_api.crf --depend .\build\pwmout_api.d)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (mbed-src/hal/pinmap.h)(0x53F945A0)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+F (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/i2c_api.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\i2c_api.o --omf_browse .\build\i2c_api.crf --depend .\build\i2c_api.d)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/hal/pinmap.h)(0x53F945A0)
+F (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/sleep.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\sleep.o --omf_browse .\build\sleep.crf --depend .\build\sleep.d)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+F (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/pinmap.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\pinmap.o --omf_browse .\build\pinmap.crf --depend .\build\pinmap.d)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (mbed-src/hal/pinmap.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+F (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/us_ticker.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\us_ticker.o --omf_browse .\build\us_ticker.crf --depend .\build\us_ticker.d)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+F (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/port_api.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\port_api.o --omf_browse .\build\port_api.crf --depend .\build\port_api.d)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (mbed-src/hal/pinmap.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+F (mbed-src/common/board.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\board.o --omf_browse .\build\board.crf --depend .\build\board.d)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/api/toolchain.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\rt_sys.h)(0x53463A44)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+F (mbed-src/common/assert.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\assert.o --omf_browse .\build\assert.crf --depend .\build\assert.d)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+F (mbed-src/common/mbed_interface.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\mbed_interface.o --omf_browse .\build\mbed_interface.crf --depend .\build\mbed_interface.d)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
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+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/api/semihost_api.h)(0x53F945A0)
+I (mbed-src/api/toolchain.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\rt_sys.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+F (mbed-src/common/us_ticker_api.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\us_ticker_api.o --omf_browse .\build\us_ticker_api.crf --depend .\build\us_ticker_api.d)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+F (mbed-src/common/exit.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\exit.o --omf_browse .\build\exit.crf --depend .\build\exit.d)
+I (mbed-src/api/semihost_api.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (mbed-src/api/toolchain.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\rt_sys.h)(0x53463A44)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+F (mbed-src/common/rtc_time.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\rtc_time.o --omf_browse .\build\rtc_time.crf --depend .\build\rtc_time.d)
+I (mbed-src/hal/rtc_api.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+F (mbed-src/common/pinmap_common.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\pinmap_common.o --omf_browse .\build\pinmap_common.crf --depend .\build\pinmap_common.d)
+I (mbed-src/hal/pinmap.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+F (mbed-src/common/error.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\error.o --omf_browse .\build\error.crf --depend .\build\error.d)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdarg.h)(0x53463A44)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (mbed-src/api/toolchain.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\rt_sys.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+F (mbed-src/common/gpio.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\gpio.o --omf_browse .\build\gpio.crf --depend .\build\gpio.d)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+F (mbed-src/common/semihost_api.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\semihost_api.o --omf_browse .\build\semihost_api.crf --depend .\build\semihost_api.d)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/api/semihost_api.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (mbed-src/api/toolchain.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\rt_sys.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+F (mbed-src/common/wait_api.c)(0x53F945A2)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\wait_api.o --omf_browse .\build\wait_api.crf --depend .\build\wait_api.d)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+F (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/sys.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\sys.o --omf_browse .\build\sys.crf --depend .\build\sys.d)
+I (C:\Keil_v5\ARM\ARMCC\include\rt_misc.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+F (mbed-src/common/RawSerial.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\rawserial.o --omf_browse .\build\rawserial.crf --depend .\build\rawserial.d)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdarg)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdarg.h)(0x53463A44)
+F (mbed-src/common/Ticker.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\ticker.o --omf_browse .\build\ticker.crf --depend .\build\ticker.d)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+F (mbed-src/common/FilePath.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\filepath.o --omf_browse .\build\filepath.crf --depend .\build\filepath.d)
+I (mbed-src/api/FilePath.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/api/FileSystemLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/DirHandle.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+F (mbed-src/common/I2C.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\i2c.o --omf_browse .\build\i2c.crf --depend .\build\i2c.d)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+F (mbed-src/common/FileBase.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\filebase.o --omf_browse .\build\filebase.crf --depend .\build\filebase.d)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+F (mbed-src/common/retarget.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\retarget.o --omf_browse .\build\retarget.crf --depend .\build\retarget.d)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/FileSystemLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/DirHandle.h)(0x53F945A0)
+I (mbed-src/api/FilePath.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/toolchain.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\rt_sys.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\errno.h)(0x53463A44)
+F (mbed-src/common/Serial.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\serial.o --omf_browse .\build\serial.crf --depend .\build\serial.d)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+F (mbed-src/common/Stream.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\stream.o --omf_browse .\build\stream.crf --depend .\build\stream.d)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdarg)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdarg.h)(0x53463A44)
+F (mbed-src/common/FileSystemLike.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\filesystemlike.o --omf_browse .\build\filesystemlike.crf --depend .\build\filesystemlike.d)
+I (mbed-src/api/FileSystemLike.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/DirHandle.h)(0x53F945A0)
+F (mbed-src/common/CallChain.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\callchain.o --omf_browse .\build\callchain.crf --depend .\build\callchain.d)
+I (mbed-src/api/CallChain.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+F (mbed-src/common/InterruptManager.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\interruptmanager.o --omf_browse .\build\interruptmanager.crf --depend .\build\interruptmanager.d)
+I (mbed-src/api/InterruptManager.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/api/CallChain.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+F (mbed-src/common/SerialBase.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\serialbase.o --omf_browse .\build\serialbase.crf --depend .\build\serialbase.d)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+F (mbed-src/common/BusInOut.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\businout.o --omf_browse .\build\businout.crf --depend .\build\businout.d)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+F (mbed-src/common/SPISlave.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\spislave.o --omf_browse .\build\spislave.crf --depend .\build\spislave.d)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+F (mbed-src/common/I2CSlave.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\i2cslave.o --omf_browse .\build\i2cslave.crf --depend .\build\i2cslave.d)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+F (mbed-src/common/FunctionPointer.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\functionpointer.o --omf_browse .\build\functionpointer.crf --depend .\build\functionpointer.d)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+F (mbed-src/common/Timer.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\timer.o --omf_browse .\build\timer.crf --depend .\build\timer.d)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+F (mbed-src/common/SPI.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\spi.o --omf_browse .\build\spi.crf --depend .\build\spi.d)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+F (mbed-src/common/Timeout.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\timeout.o --omf_browse .\build\timeout.crf --depend .\build\timeout.d)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+F (mbed-src/common/Ethernet.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\ethernet.o --omf_browse .\build\ethernet.crf --depend .\build\ethernet.d)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+F (mbed-src/common/TimerEvent.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\timerevent.o --omf_browse .\build\timerevent.crf --depend .\build\timerevent.d)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+F (mbed-src/common/CAN.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\can.o --omf_browse .\build\can.crf --depend .\build\can.d)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+F (mbed-src/common/BusOut.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\busout.o --omf_browse .\build\busout.crf --depend .\build\busout.d)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+F (mbed-src/common/FileLike.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\filelike.o --omf_browse .\build\filelike.crf --depend .\build\filelike.d)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+F (mbed-src/common/BusIn.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\busin.o --omf_browse .\build\busin.crf --depend .\build\busin.d)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+F (mbed-src/common/InterruptIn.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\interruptin.o --omf_browse .\build\interruptin.crf --depend .\build\interruptin.d)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+F (mbed-src/common/LocalFileSystem.cpp)(0x53F945A2)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\localfilesystem.o --omf_browse .\build\localfilesystem.crf --depend .\build\localfilesystem.d)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+F (.\mbed-rtos\rtos\Mutex.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\mutex.o --omf_browse .\build\mutex.crf --depend .\build\mutex.d)
+I (mbed-rtos\rtos\Mutex.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-rtos/rtx/cmsis_os.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (mbed-rtos/rtx/os_tcb.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+F (.\mbed-rtos\rtos\RtosTimer.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\rtostimer.o --omf_browse .\build\rtostimer.crf --depend .\build\rtostimer.d)
+I (mbed-rtos\rtos\RtosTimer.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-rtos/rtx/cmsis_os.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (mbed-rtos/rtx/os_tcb.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+F (.\mbed-rtos\rtos\Semaphore.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\semaphore.o --omf_browse .\build\semaphore.crf --depend .\build\semaphore.d)
+I (mbed-rtos\rtos\Semaphore.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-rtos/rtx/cmsis_os.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (mbed-rtos/rtx/os_tcb.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+F (.\mbed-rtos\rtos\Thread.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\thread.o --omf_browse .\build\thread.crf --depend .\build\thread.d)
+I (mbed-rtos\rtos\Thread.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-rtos/rtx/cmsis_os.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (mbed-rtos/rtx/os_tcb.h)(0x53F6BCA0)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+F (.\mbed-rtos\rtx\HAL_CM.c)(0x53F6BCA0)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\hal_cm.o --omf_browse .\build\hal_cm.crf --depend .\build\hal_cm.d)
+I (mbed-rtos\rtx\rt_TypeDef.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\os_tcb.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\RTX_Conf.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_HAL_CM.h)(0x53F6BCA0)
+F (.\mbed-rtos\rtx\rt_CMSIS.c)(0x53F6BCA0)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\rt_cmsis.o --omf_browse .\build\rt_cmsis.crf --depend .\build\rt_cmsis.d)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-rtos\rtx\rt_TypeDef.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\os_tcb.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\RTX_Conf.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_System.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Task.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Event.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_List.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Time.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Mutex.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Semaphore.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Mailbox.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_MemBox.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_HAL_CM.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\cmsis_os.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+F (.\mbed-rtos\rtx\rt_Event.c)(0x53F6BCA0)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\rt_event.o --omf_browse .\build\rt_event.crf --depend .\build\rt_event.d)
+I (mbed-rtos\rtx\rt_TypeDef.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\os_tcb.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\RTX_Conf.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_System.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Event.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_List.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Task.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_HAL_CM.h)(0x53F6BCA0)
+F (.\mbed-rtos\rtx\rt_List.c)(0x53F6BCA0)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\rt_list.o --omf_browse .\build\rt_list.crf --depend .\build\rt_list.d)
+I (mbed-rtos\rtx\rt_TypeDef.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\os_tcb.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\RTX_Conf.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_System.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_List.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Task.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Time.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_HAL_CM.h)(0x53F6BCA0)
+F (.\mbed-rtos\rtx\rt_Mailbox.c)(0x53F6BCA0)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\rt_mailbox.o --omf_browse .\build\rt_mailbox.crf --depend .\build\rt_mailbox.d)
+I (mbed-rtos\rtx\rt_TypeDef.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\os_tcb.h)(0x53F6BCA0)
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+I (mbed-rtos\rtx\rt_Mailbox.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_MemBox.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Task.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_HAL_CM.h)(0x53F6BCA0)
+F (.\mbed-rtos\rtx\rt_MemBox.c)(0x53F6BCA0)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\rt_membox.o --omf_browse .\build\rt_membox.crf --depend .\build\rt_membox.d)
+I (mbed-rtos\rtx\rt_TypeDef.h)(0x53F6BCA0)
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+I (mbed-rtos\rtx\RTX_Conf.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_System.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_MemBox.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_HAL_CM.h)(0x53F6BCA0)
+F (.\mbed-rtos\rtx\rt_Mutex.c)(0x53F6BCA0)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\rt_mutex.o --omf_browse .\build\rt_mutex.crf --depend .\build\rt_mutex.d)
+I (mbed-rtos\rtx\rt_TypeDef.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\os_tcb.h)(0x53F6BCA0)
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+I (mbed-rtos\rtx\rt_List.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Task.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Mutex.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_HAL_CM.h)(0x53F6BCA0)
+F (.\mbed-rtos\rtx\rt_Robin.c)(0x53F6BCA0)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\rt_robin.o --omf_browse .\build\rt_robin.crf --depend .\build\rt_robin.d)
+I (mbed-rtos\rtx\rt_TypeDef.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\os_tcb.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\RTX_Conf.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_List.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Task.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Time.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Robin.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_HAL_CM.h)(0x53F6BCA0)
+F (.\mbed-rtos\rtx\rt_Semaphore.c)(0x53F6BCA0)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\rt_semaphore.o --omf_browse .\build\rt_semaphore.crf --depend .\build\rt_semaphore.d)
+I (mbed-rtos\rtx\rt_TypeDef.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\os_tcb.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\RTX_Conf.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_System.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_List.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Task.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Semaphore.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_HAL_CM.h)(0x53F6BCA0)
+F (.\mbed-rtos\rtx\rt_System.c)(0x53F6BCA0)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\rt_system.o --omf_browse .\build\rt_system.crf --depend .\build\rt_system.d)
+I (mbed-rtos\rtx\rt_TypeDef.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\os_tcb.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\RTX_Conf.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Task.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_System.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Event.h)(0x53F6BCA0)
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+I (mbed-rtos\rtx\rt_Mailbox.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Semaphore.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Time.h)(0x53F6BCA0)
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-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\rt_task.o --omf_browse .\build\rt_task.crf --depend .\build\rt_task.d)
+I (mbed-rtos\rtx\rt_TypeDef.h)(0x53F6BCA0)
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+I (mbed-rtos\rtx\rt_MemBox.h)(0x53F6BCA0)
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+I (mbed-rtos\rtx\rt_HAL_CM.h)(0x53F6BCA0)
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-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\rt_time.o --omf_browse .\build\rt_time.crf --depend .\build\rt_time.d)
+I (mbed-rtos\rtx\rt_TypeDef.h)(0x53F6BCA0)
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+I (mbed-rtos\rtx\RTX_Conf.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Task.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\rt_Time.h)(0x53F6BCA0)
+F (.\mbed-rtos\rtx\RTX_Conf_CM.c)(0x53F6BCA0)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\rtx_conf_cm.o --omf_browse .\build\rtx_conf_cm.crf --depend .\build\rtx_conf_cm.d)
+I (mbed-rtos\rtx\cmsis_os.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (mbed-rtos\rtx\os_tcb.h)(0x53F6BCA0)
+I (mbed-rtos\rtx\RTX_CM_lib.h)(0x53F6BCA0)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+F (.\mbed-rtos\rtx\TARGET_M4\TOOLCHAIN_ARM\HAL_CM4.c)(0x53F6BCA0)(-c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\hal_cm4.o --omf_browse .\build\hal_cm4.crf --depend .\build\hal_cm4.d)
+I (mbed-rtos/rtx/rt_TypeDef.h)(0x53F6BCA0)
+I (mbed-rtos/rtx/os_tcb.h)(0x53F6BCA0)
+I (mbed-rtos/rtx/RTX_Conf.h)(0x53F6BCA0)
+I (mbed-rtos/rtx/rt_System.h)(0x53F6BCA0)
+I (mbed-rtos/rtx/rt_HAL_CM.h)(0x53F6BCA0)
+I (mbed-rtos/rtx/rt_Task.h)(0x53F6BCA0)
+I (mbed-rtos/rtx/rt_MemBox.h)(0x53F6BCA0)
+F (.\mbed-rtos\rtx\TARGET_M4\TOOLCHAIN_ARM\SVC_Table.s)(0x53F6BCA0)(--cpu Cortex-M4.fp -g --apcs=interwork 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include



--list .\build\svc_table.lst --xref -o .\build\svc_table.o --depend .\build\svc_table.d)
+F (.\SDFileSystem\SDFileSystem.cpp)(0x53FC07A9)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\sdfilesystem.o --omf_browse .\build\sdfilesystem.crf --depend .\build\sdfilesystem.d)
+I (SDFileSystem\SDFileSystem.h)(0x53F6BCA0)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (SDFileSystem/FATFileSystem/FATFileSystem.h)(0x53FA33B1)
+I (mbed-src/api/FileSystemLike.h)(0x53F945A0)
+I (mbed-src/api/DirHandle.h)(0x53F945A0)
+I (SDFileSystem/FATFileSystem/ChaN/ff.h)(0x53F6BCA0)
+I (SDFileSystem/FATFileSystem/ChaN/integer.h)(0x53F6BCA0)
+I (SDFileSystem/FATFileSystem/ChaN/ffconf.h)(0x53F6BCA0)
+I (mbed-src/api/mbed_debug.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdarg.h)(0x53463A44)
+F (.\SDFileSystem\FATFileSystem\FATDirHandle.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\fatdirhandle.o --omf_browse .\build\fatdirhandle.crf --depend .\build\fatdirhandle.d)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (SDFileSystem/FATFileSystem/ChaN/ff.h)(0x53F6BCA0)
+I (SDFileSystem/FATFileSystem/ChaN/integer.h)(0x53F6BCA0)
+I (SDFileSystem/FATFileSystem/ChaN/ffconf.h)(0x53F6BCA0)
+I (SDFileSystem\FATFileSystem\FATDirHandle.h)(0x53F6BCA0)
+I (mbed-src/api/DirHandle.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+F (.\SDFileSystem\FATFileSystem\FATFileHandle.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\fatfilehandle.o --omf_browse .\build\fatfilehandle.crf --depend .\build\fatfilehandle.d)
+I (SDFileSystem/FATFileSystem/ChaN/ff.h)(0x53F6BCA0)
+I (SDFileSystem/FATFileSystem/ChaN/integer.h)(0x53F6BCA0)
+I (SDFileSystem/FATFileSystem/ChaN/ffconf.h)(0x53F6BCA0)
+I (mbed-src/api/mbed_debug.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdarg.h)(0x53463A44)
+I (SDFileSystem\FATFileSystem\FATFileHandle.h)(0x53F6BCA0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+F (.\SDFileSystem\FATFileSystem\FATFileSystem.cpp)(0x53FA349B)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\fatfilesystem.o --omf_browse .\build\fatfilesystem.crf --depend .\build\fatfilesystem.d)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (SDFileSystem/FATFileSystem/ChaN/ffconf.h)(0x53F6BCA0)
+I (mbed-src/api/mbed_debug.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdarg.h)(0x53463A44)
+I (SDFileSystem\FATFileSystem\FATFileSystem.h)(0x53FA33B1)
+I (mbed-src/api/FileSystemLike.h)(0x53F945A0)
+I (mbed-src/api/DirHandle.h)(0x53F945A0)
+I (SDFileSystem/FATFileSystem/ChaN/ff.h)(0x53F6BCA0)
+I (SDFileSystem/FATFileSystem/ChaN/integer.h)(0x53F6BCA0)
+I (SDFileSystem\FATFileSystem\FATFileHandle.h)(0x53F6BCA0)
+I (SDFileSystem\FATFileSystem\FATDirHandle.h)(0x53F6BCA0)
+F (.\SDFileSystem\FATFileSystem\ChaN\ccsbcs.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\ccsbcs.o --omf_browse .\build\ccsbcs.crf --depend .\build\ccsbcs.d)
+I (SDFileSystem\FATFileSystem\ChaN\ff.h)(0x53F6BCA0)
+I (SDFileSystem\FATFileSystem\ChaN\integer.h)(0x53F6BCA0)
+I (SDFileSystem\FATFileSystem\ChaN\ffconf.h)(0x53F6BCA0)
+F (.\SDFileSystem\FATFileSystem\ChaN\diskio.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\diskio.o --omf_browse .\build\diskio.crf --depend .\build\diskio.d)
+I (SDFileSystem\FATFileSystem\ChaN\ffconf.h)(0x53F6BCA0)
+I (SDFileSystem\FATFileSystem\ChaN\diskio.h)(0x53F6BCA0)
+I (SDFileSystem\FATFileSystem\ChaN\integer.h)(0x53F6BCA0)
+I (mbed-src/api/mbed_debug.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdarg.h)(0x53463A44)
+I (SDFileSystem/FATFileSystem/FATFileSystem.h)(0x53FA33B1)
+I (mbed-src/api/FileSystemLike.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/DirHandle.h)(0x53F945A0)
+I (SDFileSystem/FATFileSystem/ChaN/ff.h)(0x53F6BCA0)
+F (.\SDFileSystem\FATFileSystem\ChaN\ff.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\ff.o --omf_browse .\build\ff.crf --depend .\build\ff.d)
+I (SDFileSystem\FATFileSystem\ChaN\ff.h)(0x53F6BCA0)
+I (SDFileSystem\FATFileSystem\ChaN\integer.h)(0x53F6BCA0)
+I (SDFileSystem\FATFileSystem\ChaN\ffconf.h)(0x53F6BCA0)
+I (SDFileSystem\FATFileSystem\ChaN\diskio.h)(0x53F6BCA0)
+F (.\CC3000\cc3000.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\cc3000.o --omf_browse .\build\cc3000.crf --depend .\build\cc3000.d)
+I (CC3000\cc3000.h)(0x53F6BCA0)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (CC3000\cc3000_common.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\errno.h)(0x53463A44)
+I (CC3000\cc3000_spi.h)(0x53F6BCA0)
+I (CC3000\cc3000_simplelink.h)(0x53F6BCA0)
+I (CC3000\cc3000_netapp.h)(0x53F6BCA0)
+I (CC3000\cc3000_nvmem.h)(0x53F6BCA0)
+I (CC3000\cc3000_socket.h)(0x53F6BCA0)
+I (CC3000\cc3000_event.h)(0x53F6BCA0)
+F (.\CC3000\cc3000_event.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\cc3000_event.o --omf_browse .\build\cc3000_event.crf --depend .\build\cc3000_event.d)
+I (CC3000\cc3000.h)(0x53F6BCA0)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (CC3000\cc3000_common.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\errno.h)(0x53463A44)
+I (CC3000\cc3000_spi.h)(0x53F6BCA0)
+I (CC3000\cc3000_simplelink.h)(0x53F6BCA0)
+I (CC3000\cc3000_netapp.h)(0x53F6BCA0)
+I (CC3000\cc3000_nvmem.h)(0x53F6BCA0)
+I (CC3000\cc3000_socket.h)(0x53F6BCA0)
+I (CC3000\cc3000_event.h)(0x53F6BCA0)
+F (.\CC3000\cc3000_hci.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\cc3000_hci.o --omf_browse .\build\cc3000_hci.crf --depend .\build\cc3000_hci.d)
+I (CC3000\cc3000.h)(0x53F6BCA0)
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+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (CC3000\cc3000_common.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\errno.h)(0x53463A44)
+I (CC3000\cc3000_spi.h)(0x53F6BCA0)
+I (CC3000\cc3000_simplelink.h)(0x53F6BCA0)
+I (CC3000\cc3000_netapp.h)(0x53F6BCA0)
+I (CC3000\cc3000_nvmem.h)(0x53F6BCA0)
+I (CC3000\cc3000_socket.h)(0x53F6BCA0)
+F (.\CC3000\cc3000_netapp.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\cc3000_netapp.o --omf_browse .\build\cc3000_netapp.crf --depend .\build\cc3000_netapp.d)
+I (CC3000\cc3000.h)(0x53F6BCA0)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (CC3000\cc3000_common.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\errno.h)(0x53463A44)
+I (CC3000\cc3000_spi.h)(0x53F6BCA0)
+I (CC3000\cc3000_simplelink.h)(0x53F6BCA0)
+I (CC3000\cc3000_netapp.h)(0x53F6BCA0)
+I (CC3000\cc3000_nvmem.h)(0x53F6BCA0)
+I (CC3000\cc3000_socket.h)(0x53F6BCA0)
+F (.\CC3000\cc3000_nvmem.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\cc3000_nvmem.o --omf_browse .\build\cc3000_nvmem.crf --depend .\build\cc3000_nvmem.d)
+I (CC3000\cc3000.h)(0x53F6BCA0)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
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+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
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+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
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+I (mbed-src/api/PortOut.h)(0x53F945A0)
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+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
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+I (mbed-src/api/Ticker.h)(0x53F945A0)
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+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
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+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (CC3000\cc3000_common.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\errno.h)(0x53463A44)
+I (CC3000\cc3000_spi.h)(0x53F6BCA0)
+I (CC3000\cc3000_simplelink.h)(0x53F6BCA0)
+I (CC3000\cc3000_netapp.h)(0x53F6BCA0)
+I (CC3000\cc3000_nvmem.h)(0x53F6BCA0)
+I (CC3000\cc3000_socket.h)(0x53F6BCA0)
+F (.\CC3000\cc3000_security.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\cc3000_security.o --omf_browse .\build\cc3000_security.crf --depend .\build\cc3000_security.d)
+I (CC3000\cc3000.h)(0x53F6BCA0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (CC3000\cc3000_common.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\errno.h)(0x53463A44)
+I (CC3000\cc3000_spi.h)(0x53F6BCA0)
+I (CC3000\cc3000_simplelink.h)(0x53F6BCA0)
+I (CC3000\cc3000_netapp.h)(0x53F6BCA0)
+I (CC3000\cc3000_nvmem.h)(0x53F6BCA0)
+I (CC3000\cc3000_socket.h)(0x53F6BCA0)
+F (.\CC3000\cc3000_socket.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\cc3000_socket.o --omf_browse .\build\cc3000_socket.crf --depend .\build\cc3000_socket.d)
+I (CC3000\cc3000.h)(0x53F6BCA0)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (CC3000\cc3000_common.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\errno.h)(0x53463A44)
+I (CC3000\cc3000_spi.h)(0x53F6BCA0)
+I (CC3000\cc3000_simplelink.h)(0x53F6BCA0)
+I (CC3000\cc3000_netapp.h)(0x53F6BCA0)
+I (CC3000\cc3000_nvmem.h)(0x53F6BCA0)
+I (CC3000\cc3000_socket.h)(0x53F6BCA0)
+I (CC3000\cc3000_event.h)(0x53F6BCA0)
+F (.\CC3000\cc3000_spi.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\cc3000_spi.o --omf_browse .\build\cc3000_spi.crf --depend .\build\cc3000_spi.d)
+I (CC3000\cc3000.h)(0x53F6BCA0)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (CC3000\cc3000_common.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\errno.h)(0x53463A44)
+I (CC3000\cc3000_spi.h)(0x53F6BCA0)
+I (CC3000\cc3000_simplelink.h)(0x53F6BCA0)
+I (CC3000\cc3000_netapp.h)(0x53F6BCA0)
+I (CC3000\cc3000_nvmem.h)(0x53F6BCA0)
+I (CC3000\cc3000_socket.h)(0x53F6BCA0)
+F (.\CC3000\cc3000_wlan.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\cc3000_wlan.o --omf_browse .\build\cc3000_wlan.crf --depend .\build\cc3000_wlan.d)
+I (CC3000\cc3000.h)(0x53F6BCA0)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
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+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
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+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
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+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
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+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
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+I (mbed-src/api/SerialBase.h)(0x53F945A0)
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+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
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+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (CC3000\cc3000_common.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\errno.h)(0x53463A44)
+I (CC3000\cc3000_spi.h)(0x53F6BCA0)
+I (CC3000\cc3000_simplelink.h)(0x53F6BCA0)
+I (CC3000\cc3000_netapp.h)(0x53F6BCA0)
+I (CC3000\cc3000_nvmem.h)(0x53F6BCA0)
+I (CC3000\cc3000_socket.h)(0x53F6BCA0)
+F (.\CC3000\Socket\Endpoint.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\endpoint.o --omf_browse .\build\endpoint.crf --depend .\build\endpoint.d)
+I (CC3000\Socket/Socket.h)(0x53F6BCA0)
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+I (mbed-src/api/platform.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
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+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
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+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
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+I (mbed-src/hal/spi_api.h)(0x53F945A0)
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+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (CC3000\cc3000_common.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\errno.h)(0x53463A44)
+I (CC3000\cc3000_spi.h)(0x53F6BCA0)
+I (CC3000\cc3000_simplelink.h)(0x53F6BCA0)
+I (CC3000\cc3000_netapp.h)(0x53F6BCA0)
+I (CC3000\cc3000_nvmem.h)(0x53F6BCA0)
+I (CC3000\cc3000_socket.h)(0x53F6BCA0)
+I (CC3000\Socket/Endpoint.h)(0x53F6BCA0)
+I (CC3000\Helper/def.h)(0x53F6BCA0)
+F (.\CC3000\Socket\Socket.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\socket.o --omf_browse .\build\socket.crf --depend .\build\socket.d)
+I (CC3000\Socket\Socket.h)(0x53F6BCA0)
+I (CC3000\cc3000.h)(0x53F6BCA0)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (CC3000\cc3000_common.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\errno.h)(0x53463A44)
+I (CC3000\cc3000_spi.h)(0x53F6BCA0)
+I (CC3000\cc3000_simplelink.h)(0x53F6BCA0)
+I (CC3000\cc3000_netapp.h)(0x53F6BCA0)
+I (CC3000\cc3000_nvmem.h)(0x53F6BCA0)
+I (CC3000\cc3000_socket.h)(0x53F6BCA0)
+F (.\CC3000\Socket\TCPSocketConnection.cpp)(0x53F78E4B)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\tcpsocketconnection.o --omf_browse .\build\tcpsocketconnection.crf --depend .\build\tcpsocketconnection.d)
+I (CC3000\Socket\TCPSocketConnection.h)(0x53F78B04)
+I (CC3000\Socket\Socket.h)(0x53F6BCA0)
+I (CC3000\cc3000.h)(0x53F6BCA0)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (CC3000\cc3000_common.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\errno.h)(0x53463A44)
+I (CC3000\cc3000_spi.h)(0x53F6BCA0)
+I (CC3000\cc3000_simplelink.h)(0x53F6BCA0)
+I (CC3000\cc3000_netapp.h)(0x53F6BCA0)
+I (CC3000\cc3000_nvmem.h)(0x53F6BCA0)
+I (CC3000\cc3000_socket.h)(0x53F6BCA0)
+I (CC3000\Socket\Endpoint.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\algorithm)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\memory)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\new)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\exception)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\utility)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_defs.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_config.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\config.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_iterbase.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_mutex.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_algobase.h)(0x53463A44)
+F (.\CC3000\Socket\TCPSocketServer.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\tcpsocketserver.o --omf_browse .\build\tcpsocketserver.crf --depend .\build\tcpsocketserver.d)
+I (CC3000\Socket\TCPSocketServer.h)(0x53F6BCA0)
+I (CC3000\Socket/Socket.h)(0x53F6BCA0)
+I (CC3000\cc3000.h)(0x53F6BCA0)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (CC3000\cc3000_common.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\errno.h)(0x53463A44)
+I (CC3000\cc3000_spi.h)(0x53F6BCA0)
+I (CC3000\cc3000_simplelink.h)(0x53F6BCA0)
+I (CC3000\cc3000_netapp.h)(0x53F6BCA0)
+I (CC3000\cc3000_nvmem.h)(0x53F6BCA0)
+I (CC3000\cc3000_socket.h)(0x53F6BCA0)
+I (CC3000\Socket\TCPSocketConnection.h)(0x53F78B04)
+I (CC3000\Socket\Endpoint.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\string)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\iosfwd)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_defs.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_config.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\config.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cwchar)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\wchar.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\limits)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cmath)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cfloat)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\float.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\climits)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\limits.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_algobase.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\utility)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_iterator.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_iterbase.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_strref.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\memory)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\new)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\exception)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_mutex.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_traits.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_error.h)(0x53463A44)
+F (.\CC3000\Socket\UDPSocket.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\udpsocket.o --omf_browse .\build\udpsocket.crf --depend .\build\udpsocket.d)
+I (CC3000\Socket\UDPSocket.h)(0x53F6BCA0)
+I (CC3000\Socket\Endpoint.h)(0x53F6BCA0)
+I (CC3000\cc3000.h)(0x53F6BCA0)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (CC3000\cc3000_common.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\errno.h)(0x53463A44)
+I (CC3000\cc3000_spi.h)(0x53F6BCA0)
+I (CC3000\cc3000_simplelink.h)(0x53F6BCA0)
+I (CC3000\cc3000_netapp.h)(0x53F6BCA0)
+I (CC3000\cc3000_nvmem.h)(0x53F6BCA0)
+I (CC3000\cc3000_socket.h)(0x53F6BCA0)
+I (CC3000\Socket\Socket.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdint)(0x53463A44)
+I (CC3000/Helper/def.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\string)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\iosfwd)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_defs.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_config.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\config.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cwchar)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\wchar.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\limits)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cmath)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cfloat)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\float.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\climits)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\limits.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_algobase.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\utility)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_iterator.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_iterbase.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_strref.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\memory)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\new)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\exception)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_mutex.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_traits.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\rw\_error.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\algorithm)(0x53463A44)
+F (.\CC3000\cc3000_simplelink.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\cc3000_simplelink.o --omf_browse .\build\cc3000_simplelink.crf --depend .\build\cc3000_simplelink.d)
+I (CC3000\cc3000.h)(0x53F6BCA0)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (CC3000\cc3000_common.h)(0x53F6BCA0)
+I (C:\Keil_v5\ARM\ARMCC\include\errno.h)(0x53463A44)
+I (CC3000\cc3000_spi.h)(0x53F6BCA0)
+I (CC3000\cc3000_simplelink.h)(0x53F6BCA0)
+I (CC3000\cc3000_netapp.h)(0x53F6BCA0)
+I (CC3000\cc3000_nvmem.h)(0x53F6BCA0)
+I (CC3000\cc3000_socket.h)(0x53F6BCA0)
+F (.\ILI9341\GraphicsDisplay.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\graphicsdisplay.o --omf_browse .\build\graphicsdisplay.crf --depend .\build\graphicsdisplay.d)
+I (ILI9341\GraphicsDisplay.h)(0x53F6BCA0)
+I (ILI9341\TextDisplay.h)(0x53F6BCA0)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+F (.\ILI9341\SPI_TFT_ILI9341.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\spi_tft_ili9341.o --omf_browse .\build\spi_tft_ili9341.crf --depend .\build\spi_tft_ili9341.d)
+I (ILI9341\SPI_TFT_ILI9341.h)(0x53F6BCA0)
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+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+I (ILI9341\GraphicsDisplay.h)(0x53F6BCA0)
+I (ILI9341\TextDisplay.h)(0x53F6BCA0)
+F (.\ILI9341\SPI_TFT_ILI9341_NUCLEO.cpp)(0x53F759B8)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\spi_tft_ili9341_nucleo.o --omf_browse .\build\spi_tft_ili9341_nucleo.crf --depend .\build\spi_tft_ili9341_nucleo.d)
+F (.\ILI9341\SPI_TFT_ILI9341_NXP.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\spi_tft_ili9341_nxp.o --omf_browse .\build\spi_tft_ili9341_nxp.crf --depend .\build\spi_tft_ili9341_nxp.d)
+F (.\ILI9341\TextDisplay.cpp)(0x53F6BCA0)(--cpp -c --cpu Cortex-M4.fp -g -O0 --apcs=interwork -I. -IDHT -Imbed-src -Imbed-src/hal -Imbed-src/api -Imbed-src/targets -Imbed-src/targets/hal -Imbed-src/targets/hal/TARGET_STM -Imbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis -Imbed-src/targets/cmsis/TARGET_STM -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE -Imbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO -Imbed-src/common -Imbed-rtos/rtos -Imbed-rtos/rtx -ISDFileSystem -ISDFileSystem/FATFileSystem -ISDFileSystem/FATFileSystem/ChaN -ICC3000 -ICC3000/Socket -ICC3000/Helper -IILI9341 --gnu 

-I C:\Keil_v5\ARM\RV31\INC

-I C:\Keil_v5\ARM\PACK\ARM\CMSIS\4.1.1\CMSIS\Include

-I C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Device\Include

-DSTM32F401xx -DTARGET_NUCLEO_F401RE -DTARGET_M4 -DTARGET_STM -DTARGET_STM32F4 -DTARGET_STM32F401RE -DTOOLCHAIN_ARM_MICRO -DTOOLCHAIN_ARM -D__CORTEX_M4 -DARM_MATH_CM4 -D__FPU_PRESENT="1" -DMBED_BUILD_TIMESTAMP="1408874015.43" -D__MBED__="1" -DTARGET_FF_ARDUINO -DTARGET_FF_MORPHO -D__ASSERT_MSG -DSTM32F401xx

-o .\build\textdisplay.o --omf_browse .\build\textdisplay.crf --depend .\build\textdisplay.d)
+I (ILI9341\TextDisplay.h)(0x53F6BCA0)
+I (mbed-src/api/mbed.h)(0x53F945A0)
+I (mbed-src/api/platform.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44)
+I (mbed-src/targets/cmsis/core_cmInstr.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cmFunc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/core_cm4_simd.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h)(0x53F945A0)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h)(0x53F945A2)
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+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h)(0x53F945A2)
+I (mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h)(0x53F945A0)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h)(0x53F945A2)
+I (mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h)(0x53F945A2)
+I (mbed-src/api/mbed_assert.h)(0x53F945A0)
+I (C:\Keil_v5\ARM\ARMCC\include\cstddef)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stddef.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdlib)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstdio)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\cstring)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x53463A44)
+I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x53463A44)
+I (mbed-src/api/mbed_error.h)(0x53F945A0)
+I (mbed-src/api/mbed_interface.h)(0x53F945A0)
+I (mbed-src/api/DigitalIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_api.h)(0x53F945A0)
+I (mbed-src/api/DigitalOut.h)(0x53F945A0)
+I (mbed-src/api/DigitalInOut.h)(0x53F945A0)
+I (mbed-src/api/BusIn.h)(0x53F945A0)
+I (mbed-src/api/BusOut.h)(0x53F945A0)
+I (mbed-src/api/BusInOut.h)(0x53F945A0)
+I (mbed-src/api/PortIn.h)(0x53F945A0)
+I (mbed-src/hal/port_api.h)(0x53F945A0)
+I (mbed-src/api/PortInOut.h)(0x53F945A0)
+I (mbed-src/api/PortOut.h)(0x53F945A0)
+I (mbed-src/api/AnalogIn.h)(0x53F945A0)
+I (mbed-src/hal/analogin_api.h)(0x53F945A0)
+I (mbed-src/api/AnalogOut.h)(0x53F945A0)
+I (mbed-src/api/PwmOut.h)(0x53F945A0)
+I (mbed-src/hal/pwmout_api.h)(0x53F945A0)
+I (mbed-src/api/Serial.h)(0x53F945A0)
+I (mbed-src/api/Stream.h)(0x53F945A0)
+I (mbed-src/api/FileLike.h)(0x53F945A0)
+I (mbed-src/api/FileBase.h)(0x53F945A0)
+I (mbed-src/api/FileHandle.h)(0x53F945A0)
+I (mbed-src/api/SerialBase.h)(0x53F945A0)
+I (mbed-src/api/FunctionPointer.h)(0x53F945A0)
+I (mbed-src/hal/serial_api.h)(0x53F945A0)
+I (mbed-src/api/SPI.h)(0x53F945A0)
+I (mbed-src/hal/spi_api.h)(0x53F945A0)
+I (mbed-src/api/SPISlave.h)(0x53F945A0)
+I (mbed-src/api/I2C.h)(0x53F945A0)
+I (mbed-src/hal/i2c_api.h)(0x53F945A0)
+I (mbed-src/api/I2CSlave.h)(0x53F945A0)
+I (mbed-src/api/Ethernet.h)(0x53F945A0)
+I (mbed-src/api/CAN.h)(0x53F945A0)
+I (mbed-src/api/RawSerial.h)(0x53F945A0)
+I (mbed-src/api/Timer.h)(0x53F945A0)
+I (mbed-src/api/Ticker.h)(0x53F945A0)
+I (mbed-src/api/TimerEvent.h)(0x53F945A0)
+I (mbed-src/hal/us_ticker_api.h)(0x53F945A0)
+I (mbed-src/api/Timeout.h)(0x53F945A0)
+I (mbed-src/api/LocalFileSystem.h)(0x53F945A0)
+I (mbed-src/api/InterruptIn.h)(0x53F945A0)
+I (mbed-src/hal/gpio_irq_api.h)(0x53F945A0)
+I (mbed-src/api/wait_api.h)(0x53F945A0)
+I (mbed-src/hal/sleep_api.h)(0x53F945A0)
+I (mbed-src/api/rtc_time.h)(0x53F945A0)
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Nucleo_blink_led_uvopt.bak	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,2449 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
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+
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+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
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+    <ToolsetName>ARM-ADS</ToolsetName>
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+        </Book>
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+          <Path>C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Documents\DM00093902.pdf</Path>
+        </Book>
+        <Book>
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+          <Title>Bill of Materials (STM32F401C-Discovery)</Title>
+          <Path>C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Documents\stm32f401c-disco_bom.zip</Path>
+        </Book>
+        <Book>
+          <Number>3</Number>
+          <Title>Gerber Files (STM32F401C-Discovery)</Title>
+          <Path>C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Documents\stm32f401c-disco_gerber.zip</Path>
+        </Book>
+        <Book>
+          <Number>4</Number>
+          <Title>Schematics (STM32F401C-Discovery)</Title>
+          <Path>C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\1.0.8\Documents\stm32f401c-disco_sch.zip</Path>
+        </Book>
+        <Book>
+          <Number>5</Number>
+          <Title>User Manual (NUCLEO-F401RE)</Title>
+          <Path>C:\Keil_v5\ARM\PACK\Keil\STM32NUCLEO_BSP\1.1.0\Documents\DM00105823.pdf</Path>
+        </Book>
+        <Book>
+          <Number>6</Number>
+          <Title>Getting started (NUCLEO-F401RE)</Title>
+          <Path>C:\Keil_v5\ARM\PACK\Keil\STM32NUCLEO_BSP\1.1.0\Documents\DM00105925.pdf</Path>
+        </Book>
+        <Book>
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+          <Path>C:\Keil_v5\ARM\PACK\Keil\STM32NUCLEO_BSP\1.1.0\Documents\MB1136.pdf</Path>
+        </Book>
+        <Book>
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+          <Title>STM32F401C-Discovery Web Page (STM32F401C-Discovery)</Title>
+          <Path>http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259098</Path>
+        </Book>
+        <Book>
+          <Number>9</Number>
+          <Title>Nucleo STM32 F4 series development board (NUCLEO-F401RE)</Title>
+          <Path>http://www.st.com/web/en/catalog/tools/PF260000</Path>
+        </Book>
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--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Nucleo_blink_led_uvproj.bak	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,6073 @@
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+  <Header>### uVision Project, (C) Keil Software</Header>
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+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>2</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <useXO>2</useXO>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>InterruptIn.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>mbed-src/common/InterruptIn.cpp</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>0</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>0</AssembleAssemblyFile>
+                  <PublicsOnly>0</PublicsOnly>
+                  <StopOnExitCode>3</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>2</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <useXO>2</useXO>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>LocalFileSystem.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>mbed-src/common/LocalFileSystem.cpp</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>0</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>0</AssembleAssemblyFile>
+                  <PublicsOnly>0</PublicsOnly>
+                  <StopOnExitCode>3</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>2</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <useXO>2</useXO>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>mbed-rtos</GroupName>
+          <Files>
+            <File>
+              <FileName>Mutex.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\mbed-rtos\rtos\Mutex.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>RtosTimer.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\mbed-rtos\rtos\RtosTimer.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>Semaphore.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\mbed-rtos\rtos\Semaphore.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>Thread.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\mbed-rtos\rtos\Thread.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>HAL_CM.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\HAL_CM.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_CMSIS.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_CMSIS.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_Event.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_Event.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_List.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_List.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_Mailbox.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_Mailbox.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_MemBox.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_MemBox.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_Mutex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_Mutex.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_Robin.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_Robin.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_Semaphore.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_Semaphore.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_System.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_System.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_Task.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_Task.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_Time.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\rt_Time.c</FilePath>
+            </File>
+            <File>
+              <FileName>RTX_Conf_CM.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\RTX_Conf_CM.c</FilePath>
+            </File>
+            <File>
+              <FileName>HAL_CM4.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\mbed-rtos\rtx\TARGET_M4\TOOLCHAIN_ARM\HAL_CM4.c</FilePath>
+            </File>
+            <File>
+              <FileName>SVC_Table.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\mbed-rtos\rtx\TARGET_M4\TOOLCHAIN_ARM\SVC_Table.s</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>SDFileSystem</GroupName>
+          <Files>
+            <File>
+              <FileName>SDFileSystem.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\SDFileSystem\SDFileSystem.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>FATDirHandle.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\SDFileSystem\FATFileSystem\FATDirHandle.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>FATFileHandle.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\SDFileSystem\FATFileSystem\FATFileHandle.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>FATFileSystem.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\SDFileSystem\FATFileSystem\FATFileSystem.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>ccsbcs.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\SDFileSystem\FATFileSystem\ChaN\ccsbcs.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>diskio.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\SDFileSystem\FATFileSystem\ChaN\diskio.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>ff.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\SDFileSystem\FATFileSystem\ChaN\ff.cpp</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CC3000</GroupName>
+          <Files>
+            <File>
+              <FileName>cc3000.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>cc3000_event.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000_event.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>cc3000_hci.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000_hci.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>cc3000_netapp.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000_netapp.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>cc3000_nvmem.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000_nvmem.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>cc3000_security.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000_security.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>cc3000_socket.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000_socket.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>cc3000_spi.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000_spi.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>cc3000_wlan.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000_wlan.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>Endpoint.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\Socket\Endpoint.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>Socket.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\Socket\Socket.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>TCPSocketConnection.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\Socket\TCPSocketConnection.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>TCPSocketServer.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\Socket\TCPSocketServer.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>UDPSocket.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\Socket\UDPSocket.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>cc3000_simplelink.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\CC3000\cc3000_simplelink.cpp</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>ILI9341</GroupName>
+          <Files>
+            <File>
+              <FileName>GraphicsDisplay.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\ILI9341\GraphicsDisplay.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>SPI_TFT_ILI9341.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\ILI9341\SPI_TFT_ILI9341.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>SPI_TFT_ILI9341_NUCLEO.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\ILI9341\SPI_TFT_ILI9341_NUCLEO.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>SPI_TFT_ILI9341_NXP.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\ILI9341\SPI_TFT_ILI9341_NXP.cpp</FilePath>
+            </File>
+            <File>
+              <FileName>TextDisplay.cpp</FileName>
+              <FileType>8</FileType>
+              <FilePath>.\ILI9341\TextDisplay.cpp</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/README.md	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1 @@
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/SDFileSystem/FATFileSystem/ChaN/ccsbcs.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,541 @@
+/*------------------------------------------------------------------------*/
+/* Unicode - Local code bidirectional converter  (C)ChaN, 2009            */
+/* (SBCS code pages)                                                      */
+/*------------------------------------------------------------------------*/
+/*  437   U.S. (OEM)
+/   720   Arabic (OEM)
+/   1256  Arabic (Windows)
+/   737   Greek (OEM)
+/   1253  Greek (Windows)
+/   1250  Central Europe (Windows)
+/   775   Baltic (OEM)
+/   1257  Baltic (Windows)
+/   850   Multilingual Latin 1 (OEM)
+/   852   Latin 2 (OEM)
+/   1252  Latin 1 (Windows)
+/   855   Cyrillic (OEM)
+/   1251  Cyrillic (Windows)
+/   866   Russian (OEM)
+/   857   Turkish (OEM)
+/   1254  Turkish (Windows)
+/   858   Multilingual Latin 1 + Euro (OEM)
+/   862   Hebrew (OEM)
+/   1255  Hebrew (Windows)
+/   874   Thai (OEM, Windows)
+/   1258  Vietnam (OEM, Windows)
+*/
+
+#include "ff.h"
+
+
+#if _CODE_PAGE == 437
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP437(0x80-0xFF) to Unicode conversion table */
+    0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
+    0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+    0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
+    0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
+    0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
+    0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+    0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+    0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+    0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+    0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4,
+    0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+    0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248,
+    0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 720
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP720(0x80-0xFF) to Unicode conversion table */
+    0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7,
+    0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9,
+    0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627,
+    0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F,
+    0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+    0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+    0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+    0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+    0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642,
+    0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A,
+    0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0xO650, 0x2248,
+    0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 737
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP737(0x80-0xFF) to Unicode conversion table */
+    0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398,
+    0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0,
+    0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9,
+    0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8,
+    0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0,
+    0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+    0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+    0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+    0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+    0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD,
+    0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E,
+    0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248,
+    0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 775
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP775(0x80-0xFF) to Unicode conversion table */
+    0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107,
+    0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5,
+    0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A,
+    0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4,
+    0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6,
+    0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118,
+    0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D,
+    0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B,
+    0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+    0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144,
+    0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019,
+    0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E,
+    0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 850
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP850(0x80-0xFF) to Unicode conversion table */
+    0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
+    0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+    0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
+    0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
+    0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
+    0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
+    0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+    0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE,
+    0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
+    0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE,
+    0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
+    0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
+    0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 852
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP852(0x80-0xFF) to Unicode conversion table */
+    0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7,
+    0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106,
+    0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A,
+    0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D,
+    0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E,
+    0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A,
+    0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+    0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE,
+    0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580,
+    0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161,
+    0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4,
+    0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8,
+    0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 855
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP855(0x80-0xFF) to Unicode conversion table */
+    0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404,
+    0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408,
+    0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C,
+    0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A,
+    0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414,
+    0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438,
+    0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+    0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E,
+    0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580,
+    0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443,
+    0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116,
+    0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D,
+    0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 857
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP857(0x80-0xFF) to Unicode conversion table */
+    0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
+    0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5,
+    0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
+    0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F,
+    0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F,
+    0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
+    0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+    0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE,
+    0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
+    0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000,
+    0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4,
+    0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
+    0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 858
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP858(0x80-0xFF) to Unicode conversion table */
+    0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
+    0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+    0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
+    0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
+    0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
+    0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
+    0x00A9, 0x2563, 0x2551, 0x2557, 0x2550, 0x00A2, 0x00A5, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+    0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x20AC, 0x00CD, 0x00CE,
+    0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00C6, 0x00CC, 0x2580,
+    0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE,
+    0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
+    0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
+    0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 862
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP862(0x80-0xFF) to Unicode conversion table */
+    0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7,
+    0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
+    0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7,
+    0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
+    0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
+    0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+    0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+    0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+    0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+    0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4,
+    0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+    0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248,
+    0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 866
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP866(0x80-0xFF) to Unicode conversion table */
+    0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417,
+    0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
+    0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427,
+    0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
+    0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437,
+    0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
+    0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+    0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+    0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+    0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+    0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+    0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+    0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447,
+    0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F,
+    0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E,
+    0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 874
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP874(0x80-0xFF) to Unicode conversion table */
+    0x20AC, 0x0000, 0x0000, 0x0000, 0x0000, 0x2026, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x00A0, 0x0E01, 0x0E02, 0x0E03, 0x0E04, 0x0E05, 0x0E06, 0x0E07,
+    0x0E08, 0x0E09, 0x0E0A, 0x0E0B, 0x0E0C, 0x0E0D, 0x0E0E, 0x0E0F,
+    0x0E10, 0x0E11, 0x0E12, 0x0E13, 0x0E14, 0x0E15, 0x0E16, 0x0E17,
+    0x0E18, 0x0E19, 0x0E1A, 0x0E1B, 0x0E1C, 0x0E1D, 0x0E1E, 0x0E1F,
+    0x0E20, 0x0E21, 0x0E22, 0x0E23, 0x0E24, 0x0E25, 0x0E26, 0x0E27,
+    0x0E28, 0x0E29, 0x0E2A, 0x0E2B, 0x0E2C, 0x0E2D, 0x0E2E, 0x0E2F,
+    0x0E30, 0x0E31, 0x0E32, 0x0E33, 0x0E34, 0x0E35, 0x0E36, 0x0E37,
+    0x0E38, 0x0E39, 0x0E3A, 0x0000, 0x0000, 0x0000, 0x0000, 0x0E3F,
+    0x0E40, 0x0E41, 0x0E42, 0x0E43, 0x0E44, 0x0E45, 0x0E46, 0x0E47,
+    0x0E48, 0x0E49, 0x0E4A, 0x0E4B, 0x0E4C, 0x0E4D, 0x0E4E, 0x0E4F,
+    0x0E50, 0x0E51, 0x0E52, 0x0E53, 0x0E54, 0x0E55, 0x0E56, 0x0E57,
+    0x0E58, 0x0E59, 0x0E5A, 0x0E5B, 0x0000, 0x0000, 0x0000, 0x0000
+};
+
+#elif _CODE_PAGE == 1250
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP1250(0x80-0xFF) to Unicode conversion table */
+    0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x0000, 0x2030, 0x0160, 0x2039, 0x015A, 0x0164, 0x017D, 0x0179,
+    0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x0000, 0x2122, 0x0161, 0x203A, 0x015B, 0x0165, 0x017E, 0x017A,
+    0x00A0, 0x02C7, 0x02D8, 0x0141, 0x00A4, 0x0104, 0x00A6, 0x00A7,
+    0x00A8, 0x00A9, 0x015E, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x017B,
+    0x00B0, 0x00B1, 0x02DB, 0x0142, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+    0x00B8, 0x0105, 0x015F, 0x00BB, 0x013D, 0x02DD, 0x013E, 0x017C,
+    0x0154, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x0139, 0x0106, 0x00C7,
+    0x010C, 0x00C9, 0x0118, 0x00CB, 0x011A, 0x00CD, 0x00CE, 0x010E,
+    0x0110, 0x0143, 0x0147, 0x00D3, 0x00D4, 0x0150, 0x00D6, 0x00D7,
+    0x0158, 0x016E, 0x00DA, 0x0170, 0x00DC, 0x00DD, 0x0162, 0x00DF,
+    0x0155, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x013A, 0x0107, 0x00E7,
+    0x010D, 0x00E9, 0x0119, 0x00EB, 0x011B, 0x00ED, 0x00EE, 0x010F,
+    0x0111, 0x0144, 0x0148, 0x00F3, 0x00F4, 0x0151, 0x00F6, 0x00F7,
+    0x0159, 0x016F, 0x00FA, 0x0171, 0x00FC, 0x00FD, 0x0163, 0x02D9
+};
+
+#elif _CODE_PAGE == 1251
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP1251(0x80-0xFF) to Unicode conversion table */
+    0x0402, 0x0403, 0x201A, 0x0453, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x20AC, 0x2030, 0x0409, 0x2039, 0x040A, 0x040C, 0x040B, 0x040F,
+    0x0452, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x0000, 0x2111, 0x0459, 0x203A, 0x045A, 0x045C, 0x045B, 0x045F,
+    0x00A0, 0x040E, 0x045E, 0x0408, 0x00A4, 0x0490, 0x00A6, 0x00A7,
+    0x0401, 0x00A9, 0x0404, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x0407,
+    0x00B0, 0x00B1, 0x0406, 0x0456, 0x0491, 0x00B5, 0x00B6, 0x00B7,
+    0x0451, 0x2116, 0x0454, 0x00BB, 0x0458, 0x0405, 0x0455, 0x0457,
+    0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417,
+    0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
+    0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427,
+    0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
+    0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437,
+    0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
+    0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447,
+    0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F
+};
+
+#elif _CODE_PAGE == 1252
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP1252(0x80-0xFF) to Unicode conversion table */
+    0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x017D, 0x0000,
+    0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x017E, 0x0178,
+    0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+    0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+    0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+    0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
+    0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
+    0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF,
+    0x00D0, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7,
+    0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x00DD, 0x00DE, 0x00DF,
+    0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
+    0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF,
+    0x00F0, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7,
+    0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x00FD, 0x00FE, 0x00FF
+};
+
+#elif _CODE_PAGE == 1253
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP1253(0x80-0xFF) to Unicode conversion table */
+    0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x0000, 0x2030, 0x0000, 0x2039, 0x000C, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x00A0, 0x0385, 0x0386, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+    0x00A8, 0x00A9, 0x0000, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x2015,
+    0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x0384, 0x00B5, 0x00B6, 0x00B7,
+    0x0388, 0x0389, 0x038A, 0x00BB, 0x038C, 0x00BD, 0x038E, 0x038F,
+    0x0390, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397,
+    0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F,
+    0x03A0, 0x03A1, 0x0000, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7,
+    0x03A8, 0x03A9, 0x03AA, 0x03AD, 0x03AC, 0x03AD, 0x03AE, 0x03AF,
+    0x03B0, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7,
+    0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF,
+    0x03C0, 0x03C1, 0x03C2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7,
+    0x03C8, 0x03C9, 0x03CA, 0x03CB, 0x03CC, 0x03CD, 0x03CE, 0x0000
+};
+
+#elif _CODE_PAGE == 1254
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP1254(0x80-0xFF) to Unicode conversion table */
+    0x20AC, 0x0000, 0x210A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178,
+    0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+    0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+    0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+    0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
+    0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
+    0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF,
+    0x011E, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7,
+    0x00D8, 0x00D9, 0x00DA, 0x00BD, 0x00DC, 0x0130, 0x015E, 0x00DF,
+    0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
+    0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF,
+    0x011F, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7,
+    0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x0131, 0x015F, 0x00FF
+};
+
+#elif _CODE_PAGE == 1255
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP1255(0x80-0xFF) to Unicode conversion table */
+    0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x02C6, 0x2030, 0x0000, 0x2039, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x02DC, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+    0x00A8, 0x00A9, 0x00D7, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+    0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+    0x00B8, 0x00B9, 0x00F7, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
+    0x05B0, 0x05B1, 0x05B2, 0x05B3, 0x05B4, 0x05B5, 0x05B6, 0x05B7,
+    0x05B8, 0x05B9, 0x0000, 0x05BB, 0x05BC, 0x05BD, 0x05BE, 0x05BF,
+    0x05C0, 0x05C1, 0x05C2, 0x05C3, 0x05F0, 0x05F1, 0x05F2, 0x05F3,
+    0x05F4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7,
+    0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
+    0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7,
+    0x05E8, 0x05E9, 0x05EA, 0x0000, 0x0000, 0x200E, 0x200F, 0x0000
+};
+
+#elif _CODE_PAGE == 1256
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP1256(0x80-0xFF) to Unicode conversion table */
+    0x20AC, 0x067E, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x02C6, 0x2030, 0x0679, 0x2039, 0x0152, 0x0686, 0x0698, 0x0688,
+    0x06AF, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x06A9, 0x2122, 0x0691, 0x203A, 0x0153, 0x200C, 0x200D, 0x06BA,
+    0x00A0, 0x060C, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+    0x00A8, 0x00A9, 0x06BE, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+    0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+    0x00B8, 0x00B9, 0x061B, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x061F,
+    0x06C1, 0x0621, 0x0622, 0x0623, 0x0624, 0x0625, 0x0626, 0x0627,
+    0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F,
+    0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x0636, 0x00D7,
+    0x0637, 0x0638, 0x0639, 0x063A, 0x0640, 0x0640, 0x0642, 0x0643,
+    0x00E0, 0x0644, 0x00E2, 0x0645, 0x0646, 0x0647, 0x0648, 0x00E7,
+    0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0649, 0x064A, 0x00EE, 0x00EF,
+    0x064B, 0x064C, 0x064D, 0x064E, 0x00F4, 0x064F, 0x0650, 0x00F7,
+    0x0651, 0x00F9, 0x0652, 0x00FB, 0x00FC, 0x200E, 0x200F, 0x06D2
+}
+
+#elif _CODE_PAGE == 1257
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP1257(0x80-0xFF) to Unicode conversion table */
+    0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x0000, 0x2030, 0x0000, 0x2039, 0x0000, 0x00A8, 0x02C7, 0x00B8,
+    0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x00AF, 0x02DB, 0x0000,
+    0x00A0, 0x0000, 0x00A2, 0x00A3, 0x00A4, 0x0000, 0x00A6, 0x00A7,
+    0x00D8, 0x00A9, 0x0156, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+    0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+    0x00B8, 0x00B9, 0x0157, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00E6,
+    0x0104, 0x012E, 0x0100, 0x0106, 0x00C4, 0x00C5, 0x0118, 0x0112,
+    0x010C, 0x00C9, 0x0179, 0x0116, 0x0122, 0x0136, 0x012A, 0x013B,
+    0x0160, 0x0143, 0x0145, 0x00D3, 0x014C, 0x00D5, 0x00D6, 0x00D7,
+    0x0172, 0x0141, 0x015A, 0x016A, 0x00DC, 0x017B, 0x017D, 0x00DF,
+    0x0105, 0x012F, 0x0101, 0x0107, 0x00E4, 0x00E5, 0x0119, 0x0113,
+    0x010D, 0x00E9, 0x017A, 0x0117, 0x0123, 0x0137, 0x012B, 0x013C,
+    0x0161, 0x0144, 0x0146, 0x00F3, 0x014D, 0x00F5, 0x00F6, 0x00F7,
+    0x0173, 0x014E, 0x015B, 0x016B, 0x00FC, 0x017C, 0x017E, 0x02D9
+};
+
+#elif _CODE_PAGE == 1258
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = {   /*  CP1258(0x80-0xFF) to Unicode conversion table */
+    0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x02C6, 0x2030, 0x0000, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x02DC, 0x2122, 0x0000, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178,
+    0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+    0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+    0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+    0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
+    0x00C0, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
+    0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x0300, 0x00CD, 0x00CE, 0x00CF,
+    0x0110, 0x00D1, 0x0309, 0x00D3, 0x00D4, 0x01A0, 0x00D6, 0x00D7,
+    0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x01AF, 0x0303, 0x00DF,
+    0x00E0, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
+    0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0301, 0x00ED, 0x00EE, 0x00EF,
+    0x0111, 0x00F1, 0x0323, 0x00F3, 0x00F4, 0x01A1, 0x00F6, 0x00F7,
+    0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x01B0, 0x20AB, 0x00FF
+};
+
+#endif
+
+
+#if !_TBLDEF || !_USE_LFN
+#error This file is not needed in current configuration. Remove from the project.
+#endif
+
+
+WCHAR ff_convert (  /* Converted character, Returns zero on error */
+    WCHAR   src,    /* Character code to be converted */
+    UINT    dir     /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */
+)
+{
+    WCHAR c;
+
+
+    if (src < 0x80) {   /* ASCII */
+        c = src;
+
+    } else {
+        if (dir) {      /* OEMCP to Unicode */
+            c = (src >= 0x100) ? 0 : Tbl[src - 0x80];
+
+        } else {        /* Unicode to OEMCP */
+            for (c = 0; c < 0x80; c++) {
+                if (src == Tbl[c]) break;
+            }
+            c = (c + 0x80) & 0xFF;
+        }
+    }
+
+    return c;
+}
+
+
+WCHAR ff_wtoupper ( /* Upper converted character */
+    WCHAR chr       /* Input character */
+)
+{
+    static const WCHAR tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 };
+    static const WCHAR tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 };
+    int i;
+
+
+    for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ;
+
+    return tbl_lower[i] ? tbl_upper[i] : chr;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/SDFileSystem/FATFileSystem/ChaN/diskio.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,105 @@
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for FatFs     (C)ChaN, 2007        */
+/*-----------------------------------------------------------------------*/
+/* This is a stub disk I/O module that acts as front end of the existing */
+/* disk I/O modules and attach it to FatFs module with common interface. */
+/*-----------------------------------------------------------------------*/
+#include "ffconf.h"
+#include "diskio.h"
+
+#include "mbed_debug.h"
+#include "FATFileSystem.h"
+
+using namespace mbed;
+
+DSTATUS disk_initialize (
+    BYTE drv                /* Physical drive nmuber (0..) */
+) 
+{
+    debug_if(FFS_DBG, "disk_initialize on drv [%d]\n", drv);
+    return (DSTATUS)FATFileSystem::_ffs[drv]->disk_initialize();
+}
+
+DSTATUS disk_status (
+    BYTE drv        /* Physical drive nmuber (0..) */
+) 
+{
+    debug_if(FFS_DBG, "disk_status on drv [%d]\n", drv);
+    return (DSTATUS)FATFileSystem::_ffs[drv]->disk_status();
+}
+
+DRESULT disk_read (
+    BYTE drv,        /* Physical drive nmuber (0..) */
+    BYTE *buff,        /* Data buffer to store read data */
+    DWORD sector,    /* Sector address (LBA) */
+    BYTE count        /* Number of sectors to read (1..255) */
+)
+{
+    debug_if(FFS_DBG, "disk_read(sector %d, count %d) on drv [%d]\n", sector, count, drv);
+    for(DWORD s=sector; s<sector+count; s++) {
+        debug_if(FFS_DBG, " disk_read(sector %d)\n", s);
+        int res = FATFileSystem::_ffs[drv]->disk_read((uint8_t*)buff, s);
+        if(res) {
+            return RES_PARERR;
+        }
+        buff += 512;
+    }
+    return RES_OK;
+}
+
+#if _READONLY == 0
+DRESULT disk_write (
+    BYTE drv,            /* Physical drive nmuber (0..) */
+    const BYTE *buff,    /* Data to be written */
+    DWORD sector,        /* Sector address (LBA) */
+    BYTE count            /* Number of sectors to write (1..255) */
+)
+{
+    debug_if(FFS_DBG, "disk_write(sector %d, count %d) on drv [%d]\n", sector, count, drv);
+    for(DWORD s = sector; s < sector + count; s++) {
+        debug_if(FFS_DBG, " disk_write(sector %d)\n", s);
+        int res = FATFileSystem::_ffs[drv]->disk_write((uint8_t*)buff, s);
+        if(res) {
+            return RES_PARERR;
+        }
+        buff += 512;
+    }
+    return RES_OK;
+}
+#endif /* _READONLY */
+
+DRESULT disk_ioctl (
+    BYTE drv,        /* Physical drive nmuber (0..) */
+    BYTE ctrl,        /* Control code */
+    void *buff        /* Buffer to send/receive control data */
+)
+{
+    debug_if(FFS_DBG, "disk_ioctl(%d)\n", ctrl);
+    switch(ctrl) {
+        case CTRL_SYNC:
+            if(FATFileSystem::_ffs[drv] == NULL) {
+                return RES_NOTRDY;
+            } else if(FATFileSystem::_ffs[drv]->disk_sync()) {
+                return RES_ERROR;
+            }
+            return RES_OK;
+        case GET_SECTOR_COUNT:
+            if(FATFileSystem::_ffs[drv] == NULL) {
+                return RES_NOTRDY;
+            } else {
+                DWORD res = FATFileSystem::_ffs[drv]->disk_sectors();
+                if(res > 0) {
+                    *((DWORD*)buff) = res; // minimum allowed
+                    return RES_OK;
+                } else {
+                    return RES_ERROR;
+                }
+            }
+        case GET_BLOCK_SIZE:
+            *((DWORD*)buff) = 1; // default when not known
+            return RES_OK;
+
+    }
+    return RES_PARERR;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/SDFileSystem/FATFileSystem/ChaN/diskio.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,77 @@
+//-----------------------------------------------------------------------
+//  Low level disk interface modlue include file
+//-----------------------------------------------------------------------
+
+#ifndef _DISKIO
+
+#define _READONLY    0   // 1: Remove write functions
+#define _USE_IOCTL   1   // 1: Use disk_ioctl fucntion
+
+#include "integer.h"
+
+
+// Status of Disk Functions
+typedef BYTE    DSTATUS;
+
+// Results of Disk Functions
+typedef enum {
+    RES_OK = 0, // 0: Successful
+    RES_ERROR,  // 1: R/W Error
+    RES_WRPRT,  // 2: Write Protected
+    RES_NOTRDY, // 3: Not Ready
+    RES_PARERR  // 4: Invalid Parameter
+} DRESULT;
+
+
+// Prototypes for disk control functions
+
+int assign_drives (int, int);
+DSTATUS disk_initialize (BYTE);
+DSTATUS disk_status (BYTE);
+DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE);
+#if    _READONLY == 0
+DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE);
+#endif
+DRESULT disk_ioctl (BYTE, BYTE, void*);
+
+
+
+// Disk Status Bits (DSTATUS)
+#define STA_NOINIT  0x01    // Drive not initialized
+#define STA_NODISK  0x02    // No medium in the drive
+#define STA_PROTECT 0x04    // Write protected
+
+
+// Command code for disk_ioctrl fucntion
+
+// Generic command (defined for FatFs)
+#define CTRL_SYNC           0    // Flush disk cache (for write functions)
+#define GET_SECTOR_COUNT    1    // Get media size (for only f_mkfs())
+#define GET_SECTOR_SIZE     2    // Get sector size (for multiple sector size (_MAX_SS >= 1024))
+#define GET_BLOCK_SIZE      3    // Get erase block size (for only f_mkfs())
+#define CTRL_ERASE_SECTOR   4    // Force erased a block of sectors (for only _USE_ERASE)
+
+// Generic command
+#define CTRL_POWER          5    // Get/Set power status
+#define CTRL_LOCK           6    // Lock/Unlock media removal
+#define CTRL_EJECT          7    // Eject media
+
+// MMC/SDC specific ioctl command
+#define MMC_GET_TYPE        10    // Get card type
+#define MMC_GET_CSD         11    // Get CSD
+#define MMC_GET_CID         12    // Get CID
+#define MMC_GET_OCR         13    // Get OCR
+#define MMC_GET_SDSTAT      14    // Get SD status
+
+// ATA/CF specific ioctl command
+#define ATA_GET_REV         20    // Get F/W revision
+#define ATA_GET_MODEL       21    // Get model name
+#define ATA_GET_SN          22    // Get serial number
+
+// NAND specific ioctl command
+#define NAND_FORMAT         30    // Create physical format
+
+
+#define _DISKIO
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/SDFileSystem/FATFileSystem/ChaN/ff.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,4229 @@
+/*----------------------------------------------------------------------------/
+/  FatFs - FAT file system module  R0.09a                 (C)ChaN, 2012
+/-----------------------------------------------------------------------------/
+/ FatFs module is a generic FAT file system module for small embedded systems.
+/ This is a free software that opened for education, research and commercial
+/ developments under license policy of following terms.
+/
+/  Copyright (C) 2012, ChaN, all right reserved.
+/
+/ * The FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/-----------------------------------------------------------------------------/
+/ Feb 26,'06 R0.00  Prototype.
+/
+/ Apr 29,'06 R0.01  First stable version.
+/
+/ Jun 01,'06 R0.02  Added FAT12 support.
+/                   Removed unbuffered mode.
+/                   Fixed a problem on small (<32M) partition.
+/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM).
+/
+/ Sep 22,'06 R0.03  Added f_rename().
+/                   Changed option _FS_MINIMUM to _FS_MINIMIZE.
+/ Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast.
+/                   Fixed f_mkdir() creates incorrect directory on FAT32.
+/
+/ Feb 04,'07 R0.04  Supported multiple drive system.
+/                   Changed some interfaces for multiple drive system.
+/                   Changed f_mountdrv() to f_mount().
+/                   Added f_mkfs().
+/ Apr 01,'07 R0.04a Supported multiple partitions on a physical drive.
+/                   Added a capability of extending file size to f_lseek().
+/                   Added minimization level 3.
+/                   Fixed an endian sensitive code in f_mkfs().
+/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG.
+/                   Added FSInfo support.
+/                   Fixed DBCS name can result FR_INVALID_NAME.
+/                   Fixed short seek (<= csize) collapses the file object.
+/
+/ Aug 25,'07 R0.05  Changed arguments of f_read(), f_write() and f_mkfs().
+/                   Fixed f_mkfs() on FAT32 creates incorrect FSInfo.
+/                   Fixed f_mkdir() on FAT32 creates incorrect directory.
+/ Feb 03,'08 R0.05a Added f_truncate() and f_utime().
+/                   Fixed off by one error at FAT sub-type determination.
+/                   Fixed btr in f_read() can be mistruncated.
+/                   Fixed cached sector is not flushed when create and close without write.
+/
+/ Apr 01,'08 R0.06  Added fputc(), fputs(), fprintf() and fgets().
+/                   Improved performance of f_lseek() on moving to the same or following cluster.
+/
+/ Apr 01,'09 R0.07  Merged Tiny-FatFs as a configuration option. (_FS_TINY)
+/                   Added long file name feature.
+/                   Added multiple code page feature.
+/                   Added re-entrancy for multitask operation.
+/                   Added auto cluster size selection to f_mkfs().
+/                   Added rewind option to f_readdir().
+/                   Changed result code of critical errors.
+/                   Renamed string functions to avoid name collision.
+/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg.
+/                   Added multiple sector size feature.
+/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error.
+/                   Fixed wrong cache control in f_lseek().
+/                   Added relative path feature.
+/                   Added f_chdir() and f_chdrive().
+/                   Added proper case conversion to extended char.
+/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h.
+/                   Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH.
+/                   Fixed name matching error on the 13 char boundary.
+/                   Added a configuration option, _LFN_UNICODE.
+/                   Changed f_readdir() to return the SFN with always upper case on non-LFN cfg.
+/
+/ May 15,'10 R0.08  Added a memory configuration option. (_USE_LFN = 3)
+/                   Added file lock feature. (_FS_SHARE)
+/                   Added fast seek feature. (_USE_FASTSEEK)
+/                   Changed some types on the API, XCHAR->TCHAR.
+/                   Changed fname member in the FILINFO structure on Unicode cfg.
+/                   String functions support UTF-8 encoding files on Unicode cfg.
+/ Aug 16,'10 R0.08a Added f_getcwd(). (_FS_RPATH = 2)
+/                   Added sector erase feature. (_USE_ERASE)
+/                   Moved file lock semaphore table from fs object to the bss.
+/                   Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'.
+/                   Fixed f_mkfs() creates wrong FAT32 volume.
+/ Jan 15,'11 R0.08b Fast seek feature is also applied to f_read() and f_write().
+/                   f_lseek() reports required table size on creating CLMP.
+/                   Extended format syntax of f_printf function.
+/                   Ignores duplicated directory separators in given path name.
+/
+/ Sep 06,'11 R0.09  f_mkfs() supports multiple partition to finish the multiple partition feature.
+/                   Added f_fdisk(). (_MULTI_PARTITION = 2)
+/ Aug 27,'12 R0.09a Fixed assertion failure due to OS/2 EA on FAT12/16 volume.
+/                   Changed f_open() and f_opendir reject null object pointer to avoid crash.
+/                   Changed option name _FS_SHARE to _FS_LOCK.
+/---------------------------------------------------------------------------*/
+
+#include "ff.h"         /* FatFs configurations and declarations */
+#include "diskio.h"     /* Declarations of low level disk I/O functions */
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+#if _FATFS != 4004  /* Revision ID */
+#error Wrong include file (ff.h).
+#endif
+
+
+/* Definitions on sector size */
+#if _MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096
+#error Wrong sector size.
+#endif
+#if _MAX_SS != 512
+#define SS(fs)  ((fs)->ssize)   /* Variable sector size */
+#else
+#define SS(fs)  512U            /* Fixed sector size */
+#endif
+
+
+/* Reentrancy related */
+#if _FS_REENTRANT
+#if _USE_LFN == 1
+#error Static LFN work area must not be used in re-entrant configuration.
+#endif
+#define ENTER_FF(fs)        { if (!lock_fs(fs)) return FR_TIMEOUT; }
+#define LEAVE_FF(fs, res)   { unlock_fs(fs, res); return res; }
+#else
+#define ENTER_FF(fs)
+#define LEAVE_FF(fs, res)   return res
+#endif
+
+#define ABORT(fs, res)      { fp->flag |= FA__ERROR; LEAVE_FF(fs, res); }
+
+
+/* File access control feature */
+#if _FS_LOCK
+#if _FS_READONLY
+#error _FS_LOCK must be 0 on read-only cfg.
+#endif
+typedef struct {
+    FATFS *fs;              /* File ID 1, volume (NULL:blank entry) */
+    DWORD clu;              /* File ID 2, directory */
+    WORD idx;               /* File ID 3, directory index */
+    WORD ctr;               /* File open counter, 0:none, 0x01..0xFF:read open count, 0x100:write mode */
+} FILESEM;
+#endif
+
+
+
+/* DBCS code ranges and SBCS extend char conversion table */
+
+#if _CODE_PAGE == 932   /* Japanese Shift-JIS */
+#define _DF1S   0x81    /* DBC 1st byte range 1 start */
+#define _DF1E   0x9F    /* DBC 1st byte range 1 end */
+#define _DF2S   0xE0    /* DBC 1st byte range 2 start */
+#define _DF2E   0xFC    /* DBC 1st byte range 2 end */
+#define _DS1S   0x40    /* DBC 2nd byte range 1 start */
+#define _DS1E   0x7E    /* DBC 2nd byte range 1 end */
+#define _DS2S   0x80    /* DBC 2nd byte range 2 start */
+#define _DS2E   0xFC    /* DBC 2nd byte range 2 end */
+
+#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */
+#define _DF1S   0x81
+#define _DF1E   0xFE
+#define _DS1S   0x40
+#define _DS1E   0x7E
+#define _DS2S   0x80
+#define _DS2E   0xFE
+
+#elif _CODE_PAGE == 949 /* Korean */
+#define _DF1S   0x81
+#define _DF1E   0xFE
+#define _DS1S   0x41
+#define _DS1E   0x5A
+#define _DS2S   0x61
+#define _DS2E   0x7A
+#define _DS3S   0x81
+#define _DS3E   0xFE
+
+#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */
+#define _DF1S   0x81
+#define _DF1E   0xFE
+#define _DS1S   0x40
+#define _DS1E   0x7E
+#define _DS2S   0xA1
+#define _DS2E   0xFE
+
+#elif _CODE_PAGE == 437 /* U.S. (OEM) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+                0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 720 /* Arabic (OEM) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+                0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 737 /* Greek (OEM) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+                0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 775 /* Baltic (OEM) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+                0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+                0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 852 /* Latin 2 (OEM) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \
+                0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 855 /* Cyrillic (OEM) */
+#define _DF1S   0
+#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+                0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+                0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 857 /* Turkish (OEM) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+                0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+                0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 862 /* Hebrew (OEM) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+                0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 866 /* Russian (OEM) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+                0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+                0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+                0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+                0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF}
+
+#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \
+                0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1253 /* Greek (Windows) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+                0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \
+                0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF}
+
+#elif _CODE_PAGE == 1254 /* Turkish (Windows) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+                0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+                0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1256 /* Arabic (Windows) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+                0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1257 /* Baltic (Windows) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+                0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */
+#define _DF1S   0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \
+                0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+                0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F}
+
+#elif _CODE_PAGE == 1   /* ASCII (for only non-LFN cfg) */
+#if _USE_LFN
+#error Cannot use LFN feature without valid code page.
+#endif
+#define _DF1S   0
+
+#else
+#error Unknown code page
+
+#endif
+
+
+/* Character code support macros */
+#define IsUpper(c)  (((c)>='A')&&((c)<='Z'))
+#define IsLower(c)  (((c)>='a')&&((c)<='z'))
+#define IsDigit(c)  (((c)>='0')&&((c)<='9'))
+
+#if _DF1S       /* Code page is DBCS */
+
+#ifdef _DF2S    /* Two 1st byte areas */
+#define IsDBCS1(c)  (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
+#else           /* One 1st byte area */
+#define IsDBCS1(c)  ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
+#endif
+
+#ifdef _DS3S    /* Three 2nd byte areas */
+#define IsDBCS2(c)  (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
+#else           /* Two 2nd byte areas */
+#define IsDBCS2(c)  (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
+#endif
+
+#else           /* Code page is SBCS */
+
+#define IsDBCS1(c)  0
+#define IsDBCS2(c)  0
+
+#endif /* _DF1S */
+
+
+/* Name status flags */
+#define NS          11      /* Index of name status byte in fn[] */
+#define NS_LOSS     0x01    /* Out of 8.3 format */
+#define NS_LFN      0x02    /* Force to create LFN entry */
+#define NS_LAST     0x04    /* Last segment */
+#define NS_BODY     0x08    /* Lower case flag (body) */
+#define NS_EXT      0x10    /* Lower case flag (ext) */
+#define NS_DOT      0x20    /* Dot entry */
+
+
+/* FAT sub-type boundaries */
+/* Note that the FAT spec by Microsoft says 4085 but Windows works with 4087! */
+#define MIN_FAT16   4086    /* Minimum number of clusters for FAT16 */
+#define MIN_FAT32   65526   /* Minimum number of clusters for FAT32 */
+
+
+/* FatFs refers the members in the FAT structures as byte array instead of
+/ structure member because the structure is not binary compatible between
+/ different platforms */
+
+#define BS_jmpBoot          0   /* Jump instruction (3) */
+#define BS_OEMName          3   /* OEM name (8) */
+#define BPB_BytsPerSec      11  /* Sector size [byte] (2) */
+#define BPB_SecPerClus      13  /* Cluster size [sector] (1) */
+#define BPB_RsvdSecCnt      14  /* Size of reserved area [sector] (2) */
+#define BPB_NumFATs         16  /* Number of FAT copies (1) */
+#define BPB_RootEntCnt      17  /* Number of root dir entries for FAT12/16 (2) */
+#define BPB_TotSec16        19  /* Volume size [sector] (2) */
+#define BPB_Media           21  /* Media descriptor (1) */
+#define BPB_FATSz16         22  /* FAT size [sector] (2) */
+#define BPB_SecPerTrk       24  /* Track size [sector] (2) */
+#define BPB_NumHeads        26  /* Number of heads (2) */
+#define BPB_HiddSec         28  /* Number of special hidden sectors (4) */
+#define BPB_TotSec32        32  /* Volume size [sector] (4) */
+#define BS_DrvNum           36  /* Physical drive number (2) */
+#define BS_BootSig          38  /* Extended boot signature (1) */
+#define BS_VolID            39  /* Volume serial number (4) */
+#define BS_VolLab           43  /* Volume label (8) */
+#define BS_FilSysType       54  /* File system type (1) */
+#define BPB_FATSz32         36  /* FAT size [sector] (4) */
+#define BPB_ExtFlags        40  /* Extended flags (2) */
+#define BPB_FSVer           42  /* File system version (2) */
+#define BPB_RootClus        44  /* Root dir first cluster (4) */
+#define BPB_FSInfo          48  /* Offset of FSInfo sector (2) */
+#define BPB_BkBootSec       50  /* Offset of backup boot sector (2) */
+#define BS_DrvNum32         64  /* Physical drive number (2) */
+#define BS_BootSig32        66  /* Extended boot signature (1) */
+#define BS_VolID32          67  /* Volume serial number (4) */
+#define BS_VolLab32         71  /* Volume label (8) */
+#define BS_FilSysType32     82  /* File system type (1) */
+#define FSI_LeadSig         0   /* FSI: Leading signature (4) */
+#define FSI_StrucSig        484 /* FSI: Structure signature (4) */
+#define FSI_Free_Count      488 /* FSI: Number of free clusters (4) */
+#define FSI_Nxt_Free        492 /* FSI: Last allocated cluster (4) */
+#define MBR_Table           446 /* MBR: Partition table offset (2) */
+#define SZ_PTE              16  /* MBR: Size of a partition table entry */
+#define BS_55AA             510 /* Boot sector signature (2) */
+
+#define DIR_Name            0   /* Short file name (11) */
+#define DIR_Attr            11  /* Attribute (1) */
+#define DIR_NTres           12  /* NT flag (1) */
+#define DIR_CrtTimeTenth    13  /* Created time sub-second (1) */
+#define DIR_CrtTime         14  /* Created time (2) */
+#define DIR_CrtDate         16  /* Created date (2) */
+#define DIR_LstAccDate      18  /* Last accessed date (2) */
+#define DIR_FstClusHI       20  /* Higher 16-bit of first cluster (2) */
+#define DIR_WrtTime         22  /* Modified time (2) */
+#define DIR_WrtDate         24  /* Modified date (2) */
+#define DIR_FstClusLO       26  /* Lower 16-bit of first cluster (2) */
+#define DIR_FileSize        28  /* File size (4) */
+#define LDIR_Ord            0   /* LFN entry order and LLE flag (1) */
+#define LDIR_Attr           11  /* LFN attribute (1) */
+#define LDIR_Type           12  /* LFN type (1) */
+#define LDIR_Chksum         13  /* Sum of corresponding SFN entry */
+#define LDIR_FstClusLO      26  /* Filled by zero (0) */
+#define SZ_DIR              32      /* Size of a directory entry */
+#define LLE                 0x40    /* Last long entry flag in LDIR_Ord */
+#define DDE                 0xE5    /* Deleted directory entry mark in DIR_Name[0] */
+#define NDDE                0x05    /* Replacement of the character collides with DDE */
+
+
+/*------------------------------------------------------------*/
+/* Module private work area                                   */
+/*------------------------------------------------------------*/
+/* Note that uninitialized variables with static duration are
+/  zeroed/nulled at start-up. If not, the compiler or start-up
+/  routine is out of ANSI-C standard.
+*/
+
+#if _VOLUMES
+static
+FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */
+#else
+#error Number of volumes must not be 0.
+#endif
+
+static
+WORD Fsid;              /* File system mount ID */
+
+#if _FS_RPATH
+static
+BYTE CurrVol;           /* Current drive */
+#endif
+
+#if _FS_LOCK
+static
+FILESEM Files[_FS_LOCK];    /* File lock semaphores */
+#endif
+
+#if _USE_LFN == 0           /* No LFN feature */
+#define DEF_NAMEBUF         BYTE sfn[12]
+#define INIT_BUF(dobj)      (dobj).fn = sfn
+#define FREE_BUF()
+
+#elif _USE_LFN == 1         /* LFN feature with static working buffer */
+static WCHAR LfnBuf[_MAX_LFN+1];
+#define DEF_NAMEBUF         BYTE sfn[12]
+#define INIT_BUF(dobj)      { (dobj).fn = sfn; (dobj).lfn = LfnBuf; }
+#define FREE_BUF()
+
+#elif _USE_LFN == 2         /* LFN feature with dynamic working buffer on the stack */
+#define DEF_NAMEBUF         BYTE sfn[12]; WCHAR lbuf[_MAX_LFN+1]
+#define INIT_BUF(dobj)      { (dobj).fn = sfn; (dobj).lfn = lbuf; }
+#define FREE_BUF()
+
+#elif _USE_LFN == 3         /* LFN feature with dynamic working buffer on the heap */
+#define DEF_NAMEBUF         BYTE sfn[12]; WCHAR *lfn
+#define INIT_BUF(dobj)      { lfn = ff_memalloc((_MAX_LFN + 1) * 2); \
+                              if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); \
+                              (dobj).lfn = lfn; (dobj).fn = sfn; }
+#define FREE_BUF()          ff_memfree(lfn)
+
+#else
+#error Wrong LFN configuration.
+#endif
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Functions
+
+---------------------------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------------------*/
+/* String functions                                                      */
+/*-----------------------------------------------------------------------*/
+
+/* Copy memory to memory */
+static
+void mem_cpy (void* dst, const void* src, UINT cnt)
+{
+    BYTE *d = (BYTE*)dst;
+    const BYTE *s = (const BYTE*)src;
+
+#if _WORD_ACCESS == 1
+    while (cnt >= sizeof (int)) {
+        *(int*)d = *(int*)s;
+        d += sizeof (int);
+        s += sizeof (int);
+        cnt -= sizeof (int);
+    }
+#endif
+    while (cnt--)
+        *d++ = *s++;
+}
+
+/* Fill memory */
+static
+void mem_set (void* dst, int val, UINT cnt)
+{
+    BYTE *d = (BYTE*)dst;
+
+    while (cnt--)
+        *d++ = (BYTE)val;
+}
+
+/* Compare memory to memory */
+static
+int mem_cmp (const void* dst, const void* src, UINT cnt)
+{
+    const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src;
+    int r = 0;
+
+    while (cnt-- && (r = *d++ - *s++) == 0) ;
+    return r;
+}
+
+/* Check if chr is contained in the string */
+static
+int chk_chr (const char* str, int chr)
+{
+    while (*str && *str != chr) str++;
+    return *str;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Request/Release grant to access the volume                            */
+/*-----------------------------------------------------------------------*/
+#if _FS_REENTRANT
+
+static
+int lock_fs (
+    FATFS *fs       /* File system object */
+)
+{
+    return ff_req_grant(fs->sobj);
+}
+
+
+static
+void unlock_fs (
+    FATFS *fs,      /* File system object */
+    FRESULT res     /* Result code to be returned */
+)
+{
+    if (fs &&
+            res != FR_NOT_ENABLED &&
+            res != FR_INVALID_DRIVE &&
+            res != FR_INVALID_OBJECT &&
+            res != FR_TIMEOUT) {
+        ff_rel_grant(fs->sobj);
+    }
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* File lock control functions                                           */
+/*-----------------------------------------------------------------------*/
+#if _FS_LOCK
+
+static
+FRESULT chk_lock (  /* Check if the file can be accessed */
+    DIR* dj,        /* Directory object pointing the file to be checked */
+    int acc         /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
+)
+{
+    UINT i, be;
+
+    /* Search file semaphore table */
+    for (i = be = 0; i < _FS_LOCK; i++) {
+        if (Files[i].fs) {  /* Existing entry */
+            if (Files[i].fs == dj->fs &&        /* Check if the file matched with an open file */
+                    Files[i].clu == dj->sclust &&
+                    Files[i].idx == dj->index) break;
+        } else {            /* Blank entry */
+            be++;
+        }
+    }
+    if (i == _FS_LOCK)  /* The file is not opened */
+        return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES;   /* Is there a blank entry for new file? */
+
+    /* The file has been opened. Reject any open against writing file and all write mode open */
+    return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK;
+}
+
+
+static
+int enq_lock (void) /* Check if an entry is available for a new file */
+{
+    UINT i;
+
+    for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+    return (i == _FS_LOCK) ? 0 : 1;
+}
+
+
+static
+UINT inc_lock ( /* Increment file open counter and returns its index (0:int error) */
+    DIR* dj,    /* Directory object pointing the file to register or increment */
+    int acc     /* Desired access mode (0:Read, !0:Write) */
+)
+{
+    UINT i;
+
+
+    for (i = 0; i < _FS_LOCK; i++) {    /* Find the file */
+        if (Files[i].fs == dj->fs &&
+                Files[i].clu == dj->sclust &&
+                Files[i].idx == dj->index) break;
+    }
+
+    if (i == _FS_LOCK) {                /* Not opened. Register it as new. */
+        for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+        if (i == _FS_LOCK) return 0;    /* No space to register (int err) */
+        Files[i].fs = dj->fs;
+        Files[i].clu = dj->sclust;
+        Files[i].idx = dj->index;
+        Files[i].ctr = 0;
+    }
+
+    if (acc && Files[i].ctr) return 0;  /* Access violation (int err) */
+
+    Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1;  /* Set semaphore value */
+
+    return i + 1;
+}
+
+
+static
+FRESULT dec_lock (  /* Decrement file open counter */
+    UINT i          /* Semaphore index */
+)
+{
+    WORD n;
+    FRESULT res;
+
+
+    if (--i < _FS_LOCK) {
+        n = Files[i].ctr;
+        if (n == 0x100) n = 0;
+        if (n) n--;
+        Files[i].ctr = n;
+        if (!n) Files[i].fs = 0;
+        res = FR_OK;
+    } else {
+        res = FR_INT_ERR;
+    }
+    return res;
+}
+
+
+static
+void clear_lock (   /* Clear lock entries of the volume */
+    FATFS *fs
+)
+{
+    UINT i;
+
+    for (i = 0; i < _FS_LOCK; i++) {
+        if (Files[i].fs == fs) Files[i].fs = 0;
+    }
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change window offset                                                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT move_window (
+    FATFS *fs,      /* File system object */
+    DWORD sector    /* Sector number to make appearance in the fs->win[] */
+)                   /* Move to zero only writes back dirty window */
+{
+    DWORD wsect;
+
+
+    wsect = fs->winsect;
+    if (wsect != sector) {  /* Changed current window */
+#if !_FS_READONLY
+        if (fs->wflag) {    /* Write back dirty window if needed */
+            if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK)
+                return FR_DISK_ERR;
+            fs->wflag = 0;
+            if (wsect < (fs->fatbase + fs->fsize)) {    /* In FAT area */
+                BYTE nf;
+                for (nf = fs->n_fats; nf > 1; nf--) {   /* Reflect the change to all FAT copies */
+                    wsect += fs->fsize;
+                    disk_write(fs->drv, fs->win, wsect, 1);
+                }
+            }
+        }
+#endif
+        if (sector) {
+            if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK)
+                return FR_DISK_ERR;
+            fs->winsect = sector;
+        }
+    }
+
+    return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Clean-up cached data                                                  */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT sync (  /* FR_OK: successful, FR_DISK_ERR: failed */
+    FATFS *fs   /* File system object */
+)
+{
+    FRESULT res;
+
+
+    res = move_window(fs, 0);
+    if (res == FR_OK) {
+        /* Update FSInfo sector if needed */
+        if (fs->fs_type == FS_FAT32 && fs->fsi_flag) {
+            fs->winsect = 0;
+            /* Create FSInfo structure */
+            mem_set(fs->win, 0, 512);
+            ST_WORD(fs->win+BS_55AA, 0xAA55);
+            ST_DWORD(fs->win+FSI_LeadSig, 0x41615252);
+            ST_DWORD(fs->win+FSI_StrucSig, 0x61417272);
+            ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust);
+            ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust);
+            /* Write it into the FSInfo sector */
+            disk_write(fs->drv, fs->win, fs->fsi_sector, 1);
+            fs->fsi_flag = 0;
+        }
+        /* Make sure that no pending write process in the physical drive */
+        if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK)
+            res = FR_DISK_ERR;
+    }
+
+    return res;
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster#                                             */
+/*-----------------------------------------------------------------------*/
+
+
+DWORD clust2sect (  /* !=0: Sector number, 0: Failed - invalid cluster# */
+    FATFS *fs,      /* File system object */
+    DWORD clst      /* Cluster# to be converted */
+)
+{
+    clst -= 2;
+    if (clst >= (fs->n_fatent - 2)) return 0;       /* Invalid cluster# */
+    return clst * fs->csize + fs->database;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of a FAT entry                                */
+/*-----------------------------------------------------------------------*/
+
+
+DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */
+    FATFS *fs,  /* File system object */
+    DWORD clst  /* Cluster# to get the link information */
+)
+{
+    UINT wc, bc;
+    BYTE *p;
+
+
+    if (clst < 2 || clst >= fs->n_fatent)   /* Check range */
+        return 1;
+
+    switch (fs->fs_type) {
+        case FS_FAT12 :
+            bc = (UINT)clst;
+            bc += bc / 2;
+            if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break;
+            wc = fs->win[bc % SS(fs)];
+            bc++;
+            if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break;
+            wc |= fs->win[bc % SS(fs)] << 8;
+            return (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+
+        case FS_FAT16 :
+            if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)))) break;
+            p = &fs->win[clst * 2 % SS(fs)];
+            return LD_WORD(p);
+
+        case FS_FAT32 :
+            if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)))) break;
+            p = &fs->win[clst * 4 % SS(fs)];
+            return LD_DWORD(p) & 0x0FFFFFFF;
+    }
+
+    return 0xFFFFFFFF;  /* An error occurred at the disk I/O layer */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Change value of a FAT entry                              */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+
+FRESULT put_fat (
+    FATFS *fs,  /* File system object */
+    DWORD clst, /* Cluster# to be changed in range of 2 to fs->n_fatent - 1 */
+    DWORD val   /* New value to mark the cluster */
+)
+{
+    UINT bc;
+    BYTE *p;
+    FRESULT res;
+
+
+    if (clst < 2 || clst >= fs->n_fatent) { /* Check range */
+        res = FR_INT_ERR;
+
+    } else {
+        switch (fs->fs_type) {
+            case FS_FAT12 :
+                bc = (UINT)clst;
+                bc += bc / 2;
+                res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+                if (res != FR_OK) break;
+                p = &fs->win[bc % SS(fs)];
+                *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
+                bc++;
+                fs->wflag = 1;
+                res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+                if (res != FR_OK) break;
+                p = &fs->win[bc % SS(fs)];
+                *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
+                break;
+
+            case FS_FAT16 :
+                res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)));
+                if (res != FR_OK) break;
+                p = &fs->win[clst * 2 % SS(fs)];
+                ST_WORD(p, (WORD)val);
+                break;
+
+            case FS_FAT32 :
+                res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)));
+                if (res != FR_OK) break;
+                p = &fs->win[clst * 4 % SS(fs)];
+                val |= LD_DWORD(p) & 0xF0000000;
+                ST_DWORD(p, val);
+                break;
+
+            default :
+                res = FR_INT_ERR;
+        }
+        fs->wflag = 1;
+    }
+
+    return res;
+}
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Remove a cluster chain                                 */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT remove_chain (
+    FATFS *fs,          /* File system object */
+    DWORD clst          /* Cluster# to remove a chain from */
+)
+{
+    FRESULT res;
+    DWORD nxt;
+#if _USE_ERASE
+    DWORD scl = clst, ecl = clst, rt[2];
+#endif
+
+    if (clst < 2 || clst >= fs->n_fatent) { /* Check range */
+        res = FR_INT_ERR;
+
+    } else {
+        res = FR_OK;
+        while (clst < fs->n_fatent) {           /* Not a last link? */
+            nxt = get_fat(fs, clst);            /* Get cluster status */
+            if (nxt == 0) break;                /* Empty cluster? */
+            if (nxt == 1) {
+                res = FR_INT_ERR;    /* Internal error? */
+                break;
+            }
+            if (nxt == 0xFFFFFFFF) {
+                res = FR_DISK_ERR;    /* Disk error? */
+                break;
+            }
+            res = put_fat(fs, clst, 0);         /* Mark the cluster "empty" */
+            if (res != FR_OK) break;
+            if (fs->free_clust != 0xFFFFFFFF) { /* Update FSInfo */
+                fs->free_clust++;
+                fs->fsi_flag = 1;
+            }
+#if _USE_ERASE
+            if (ecl + 1 == nxt) {   /* Is next cluster contiguous? */
+                ecl = nxt;
+            } else {                /* End of contiguous clusters */
+                rt[0] = clust2sect(fs, scl);                    /* Start sector */
+                rt[1] = clust2sect(fs, ecl) + fs->csize - 1;    /* End sector */
+                disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, rt);     /* Erase the block */
+                scl = ecl = nxt;
+            }
+#endif
+            clst = nxt; /* Next cluster */
+        }
+    }
+
+    return res;
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Stretch or Create a cluster chain                      */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+DWORD create_chain (    /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */
+    FATFS *fs,          /* File system object */
+    DWORD clst          /* Cluster# to stretch. 0 means create a new chain. */
+)
+{
+    DWORD cs, ncl, scl;
+    FRESULT res;
+
+
+    if (clst == 0) {        /* Create a new chain */
+        scl = fs->last_clust;           /* Get suggested start point */
+        if (!scl || scl >= fs->n_fatent) scl = 1;
+    } else {                /* Stretch the current chain */
+        cs = get_fat(fs, clst);         /* Check the cluster status */
+        if (cs < 2) return 1;           /* It is an invalid cluster */
+        if (cs < fs->n_fatent) return cs;   /* It is already followed by next cluster */
+        scl = clst;
+    }
+
+    ncl = scl;              /* Start cluster */
+    for (;;) {
+        ncl++;                          /* Next cluster */
+        if (ncl >= fs->n_fatent) {      /* Wrap around */
+            ncl = 2;
+            if (ncl > scl) return 0;    /* No free cluster */
+        }
+        cs = get_fat(fs, ncl);          /* Get the cluster status */
+        if (cs == 0) break;             /* Found a free cluster */
+        if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */
+            return cs;
+        if (ncl == scl) return 0;       /* No free cluster */
+    }
+
+    res = put_fat(fs, ncl, 0x0FFFFFFF); /* Mark the new cluster "last link" */
+    if (res == FR_OK && clst != 0) {
+        res = put_fat(fs, clst, ncl);   /* Link it to the previous one if needed */
+    }
+    if (res == FR_OK) {
+        fs->last_clust = ncl;           /* Update FSINFO */
+        if (fs->free_clust != 0xFFFFFFFF) {
+            fs->free_clust--;
+            fs->fsi_flag = 1;
+        }
+    } else {
+        ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1;
+    }
+
+    return ncl;     /* Return new cluster number or error code */
+}
+#endif /* !_FS_READONLY */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Convert offset into cluster with link map table        */
+/*-----------------------------------------------------------------------*/
+
+#if _USE_FASTSEEK
+static
+DWORD clmt_clust (  /* <2:Error, >=2:Cluster number */
+    FIL* fp,        /* Pointer to the file object */
+    DWORD ofs       /* File offset to be converted to cluster# */
+)
+{
+    DWORD cl, ncl, *tbl;
+
+
+    tbl = fp->cltbl + 1;    /* Top of CLMT */
+    cl = ofs / SS(fp->fs) / fp->fs->csize;  /* Cluster order from top of the file */
+    for (;;) {
+        ncl = *tbl++;           /* Number of cluters in the fragment */
+        if (!ncl) return 0;     /* End of table? (error) */
+        if (cl < ncl) break;    /* In this fragment? */
+        cl -= ncl;
+        tbl++;       /* Next fragment */
+    }
+    return cl + *tbl;   /* Return the cluster number */
+}
+#endif  /* _USE_FASTSEEK */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Set directory index                              */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_sdi (
+    FATFS_DIR *dj,        /* Pointer to directory object */
+    WORD idx        /* Index of directory table */
+)
+{
+    DWORD clst;
+    WORD ic;
+
+
+    dj->index = idx;
+    clst = dj->sclust;
+    if (clst == 1 || clst >= dj->fs->n_fatent)  /* Check start cluster range */
+        return FR_INT_ERR;
+    if (!clst && dj->fs->fs_type == FS_FAT32)   /* Replace cluster# 0 with root cluster# if in FAT32 */
+        clst = dj->fs->dirbase;
+
+    if (clst == 0) {    /* Static table (root-dir in FAT12/16) */
+        dj->clust = clst;
+        if (idx >= dj->fs->n_rootdir)       /* Index is out of range */
+            return FR_INT_ERR;
+        dj->sect = dj->fs->dirbase + idx / (SS(dj->fs) / SZ_DIR);   /* Sector# */
+    } else {            /* Dynamic table (sub-dirs or root-dir in FAT32) */
+        ic = SS(dj->fs) / SZ_DIR * dj->fs->csize;   /* Entries per cluster */
+        while (idx >= ic) { /* Follow cluster chain */
+            clst = get_fat(dj->fs, clst);               /* Get next cluster */
+            if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */
+            if (clst < 2 || clst >= dj->fs->n_fatent)   /* Reached to end of table or int error */
+                return FR_INT_ERR;
+            idx -= ic;
+        }
+        dj->clust = clst;
+        dj->sect = clust2sect(dj->fs, clst) + idx / (SS(dj->fs) / SZ_DIR);  /* Sector# */
+    }
+
+    dj->dir = dj->fs->win + (idx % (SS(dj->fs) / SZ_DIR)) * SZ_DIR; /* Ptr to the entry in the sector */
+
+    return FR_OK;   /* Seek succeeded */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory table index next                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next (  /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:EOT and could not stretch */
+    FATFS_DIR *dj,        /* Pointer to directory object */
+    int stretch     /* 0: Do not stretch table, 1: Stretch table if needed */
+)
+{
+    DWORD clst;
+    WORD i;
+
+
+    stretch = stretch;      /* To suppress warning on read-only cfg. */
+    i = dj->index + 1;
+    if (!i || !dj->sect)    /* Report EOT when index has reached 65535 */
+        return FR_NO_FILE;
+
+    if (!(i % (SS(dj->fs) / SZ_DIR))) { /* Sector changed? */
+        dj->sect++;                 /* Next sector */
+
+        if (dj->clust == 0) {   /* Static table */
+            if (i >= dj->fs->n_rootdir) /* Report EOT when end of table */
+                return FR_NO_FILE;
+        } else {                /* Dynamic table */
+            if (((i / (SS(dj->fs) / SZ_DIR)) & (dj->fs->csize - 1)) == 0) { /* Cluster changed? */
+                clst = get_fat(dj->fs, dj->clust);              /* Get next cluster */
+                if (clst <= 1) return FR_INT_ERR;
+                if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
+                if (clst >= dj->fs->n_fatent) {                 /* When it reached end of dynamic table */
+#if !_FS_READONLY
+                    BYTE c;
+                    if (!stretch) return FR_NO_FILE;            /* When do not stretch, report EOT */
+                    clst = create_chain(dj->fs, dj->clust);     /* Stretch cluster chain */
+                    if (clst == 0) return FR_DENIED;            /* No free cluster */
+                    if (clst == 1) return FR_INT_ERR;
+                    if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
+                    /* Clean-up stretched table */
+                    if (move_window(dj->fs, 0)) return FR_DISK_ERR; /* Flush active window */
+                    mem_set(dj->fs->win, 0, SS(dj->fs));            /* Clear window buffer */
+                    dj->fs->winsect = clust2sect(dj->fs, clst); /* Cluster start sector */
+                    for (c = 0; c < dj->fs->csize; c++) {       /* Fill the new cluster with 0 */
+                        dj->fs->wflag = 1;
+                        if (move_window(dj->fs, 0)) return FR_DISK_ERR;
+                        dj->fs->winsect++;
+                    }
+                    dj->fs->winsect -= c;                       /* Rewind window address */
+#else
+                    return FR_NO_FILE;          /* Report EOT */
+#endif
+                }
+                dj->clust = clst;               /* Initialize data for new cluster */
+                dj->sect = clust2sect(dj->fs, clst);
+            }
+        }
+    }
+
+    dj->index = i;
+    dj->dir = dj->fs->win + (i % (SS(dj->fs) / SZ_DIR)) * SZ_DIR;
+
+    return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Load/Store start cluster number                  */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD ld_clust (
+    FATFS *fs,  /* Pointer to the fs object */
+    BYTE *dir   /* Pointer to the directory entry */
+)
+{
+    DWORD cl;
+
+    cl = LD_WORD(dir+DIR_FstClusLO);
+    if (fs->fs_type == FS_FAT32)
+        cl |= (DWORD)LD_WORD(dir+DIR_FstClusHI) << 16;
+
+    return cl;
+}
+
+
+#if !_FS_READONLY
+static
+void st_clust (
+    BYTE *dir,  /* Pointer to the directory entry */
+    DWORD cl    /* Value to be set */
+)
+{
+    ST_WORD(dir+DIR_FstClusLO, cl);
+    ST_WORD(dir+DIR_FstClusHI, cl >> 16);
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry   */
+/*-----------------------------------------------------------------------*/
+#if _USE_LFN
+static
+const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30};  /* Offset of LFN chars in the directory entry */
+
+
+static
+int cmp_lfn (           /* 1:Matched, 0:Not matched */
+    WCHAR *lfnbuf,      /* Pointer to the LFN to be compared */
+    BYTE *dir           /* Pointer to the directory entry containing a part of LFN */
+)
+{
+    UINT i, s;
+    WCHAR wc, uc;
+
+
+    i = ((dir[LDIR_Ord] & ~LLE) - 1) * 13;  /* Get offset in the LFN buffer */
+    s = 0;
+    wc = 1;
+    do {
+        uc = LD_WORD(dir+LfnOfs[s]);    /* Pick an LFN character from the entry */
+        if (wc) {   /* Last char has not been processed */
+            wc = ff_wtoupper(uc);       /* Convert it to upper case */
+            if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++]))    /* Compare it */
+                return 0;               /* Not matched */
+        } else {
+            if (uc != 0xFFFF) return 0; /* Check filler */
+        }
+    } while (++s < 13);             /* Repeat until all chars in the entry are checked */
+
+    if ((dir[LDIR_Ord] & LLE) && wc && lfnbuf[i])   /* Last segment matched but different length */
+        return 0;
+
+    return 1;                       /* The part of LFN matched */
+}
+
+
+
+static
+int pick_lfn (          /* 1:Succeeded, 0:Buffer overflow */
+    WCHAR *lfnbuf,      /* Pointer to the Unicode-LFN buffer */
+    BYTE *dir           /* Pointer to the directory entry */
+)
+{
+    UINT i, s;
+    WCHAR wc, uc;
+
+
+    i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13;  /* Offset in the LFN buffer */
+
+    s = 0;
+    wc = 1;
+    do {
+        uc = LD_WORD(dir+LfnOfs[s]);        /* Pick an LFN character from the entry */
+        if (wc) {   /* Last char has not been processed */
+            if (i >= _MAX_LFN) return 0;    /* Buffer overflow? */
+            lfnbuf[i++] = wc = uc;          /* Store it */
+        } else {
+            if (uc != 0xFFFF) return 0;     /* Check filler */
+        }
+    } while (++s < 13);                     /* Read all character in the entry */
+
+    if (dir[LDIR_Ord] & LLE) {              /* Put terminator if it is the last LFN part */
+        if (i >= _MAX_LFN) return 0;        /* Buffer overflow? */
+        lfnbuf[i] = 0;
+    }
+
+    return 1;
+}
+
+
+#if !_FS_READONLY
+static
+void fit_lfn (
+    const WCHAR *lfnbuf,    /* Pointer to the LFN buffer */
+    BYTE *dir,              /* Pointer to the directory entry */
+    BYTE ord,               /* LFN order (1-20) */
+    BYTE sum                /* SFN sum */
+)
+{
+    UINT i, s;
+    WCHAR wc;
+
+
+    dir[LDIR_Chksum] = sum;         /* Set check sum */
+    dir[LDIR_Attr] = AM_LFN;        /* Set attribute. LFN entry */
+    dir[LDIR_Type] = 0;
+    ST_WORD(dir+LDIR_FstClusLO, 0);
+
+    i = (ord - 1) * 13;             /* Get offset in the LFN buffer */
+    s = wc = 0;
+    do {
+        if (wc != 0xFFFF) wc = lfnbuf[i++]; /* Get an effective char */
+        ST_WORD(dir+LfnOfs[s], wc); /* Put it */
+        if (!wc) wc = 0xFFFF;       /* Padding chars following last char */
+    } while (++s < 13);
+    if (wc == 0xFFFF || !lfnbuf[i]) ord |= LLE; /* Bottom LFN part is the start of LFN sequence */
+    dir[LDIR_Ord] = ord;            /* Set the LFN order */
+}
+
+#endif
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create numbered name                                                  */
+/*-----------------------------------------------------------------------*/
+#if _USE_LFN
+void gen_numname (
+    BYTE *dst,          /* Pointer to generated SFN */
+    const BYTE *src,    /* Pointer to source SFN to be modified */
+    const WCHAR *lfn,   /* Pointer to LFN */
+    WORD seq            /* Sequence number */
+)
+{
+    BYTE ns[8], c;
+    UINT i, j;
+
+
+    mem_cpy(dst, src, 11);
+
+    if (seq > 5) {  /* On many collisions, generate a hash number instead of sequential number */
+        do seq = (seq >> 1) + (seq << 15) + (WORD)*lfn++;
+        while (*lfn);
+    }
+
+    /* itoa (hexdecimal) */
+    i = 7;
+    do {
+        c = (seq % 16) + '0';
+        if (c > '9') c += 7;
+        ns[i--] = c;
+        seq /= 16;
+    } while (seq);
+    ns[i] = '~';
+
+    /* Append the number */
+    for (j = 0; j < i && dst[j] != ' '; j++) {
+        if (IsDBCS1(dst[j])) {
+            if (j == i - 1) break;
+            j++;
+        }
+    }
+    do {
+        dst[j++] = (i < 8) ? ns[i++] : ' ';
+    } while (j < 8);
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Calculate sum of an SFN                                               */
+/*-----------------------------------------------------------------------*/
+#if _USE_LFN
+static
+BYTE sum_sfn (
+    const BYTE *dir     /* Ptr to directory entry */
+)
+{
+    BYTE sum = 0;
+    UINT n = 11;
+
+    do sum = (sum >> 1) + (sum << 7) + *dir++;
+    while (--n);
+    return sum;
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (
+    FATFS_DIR *dj         /* Pointer to the directory object linked to the file name */
+)
+{
+    FRESULT res;
+    BYTE c, *dir;
+#if _USE_LFN
+    BYTE a, ord, sum;
+#endif
+
+    res = dir_sdi(dj, 0);           /* Rewind directory object */
+    if (res != FR_OK) return res;
+
+#if _USE_LFN
+    ord = sum = 0xFF;
+#endif
+    do {
+        res = move_window(dj->fs, dj->sect);
+        if (res != FR_OK) break;
+        dir = dj->dir;                  /* Ptr to the directory entry of current index */
+        c = dir[DIR_Name];
+        if (c == 0) {
+            res = FR_NO_FILE;    /* Reached to end of table */
+            break;
+        }
+#if _USE_LFN    /* LFN configuration */
+        a = dir[DIR_Attr] & AM_MASK;
+        if (c == DDE || ((a & AM_VOL) && a != AM_LFN)) {    /* An entry without valid data */
+            ord = 0xFF;
+        } else {
+            if (a == AM_LFN) {          /* An LFN entry is found */
+                if (dj->lfn) {
+                    if (c & LLE) {      /* Is it start of LFN sequence? */
+                        sum = dir[LDIR_Chksum];
+                        c &= ~LLE;
+                        ord = c; /* LFN start order */
+                        dj->lfn_idx = dj->index;
+                    }
+                    /* Check validity of the LFN entry and compare it with given name */
+                    ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF;
+                }
+            } else {                    /* An SFN entry is found */
+                if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */
+                ord = 0xFF;
+                dj->lfn_idx = 0xFFFF;   /* Reset LFN sequence */
+                if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break;    /* SFN matched? */
+            }
+        }
+#else       /* Non LFN configuration */
+        if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */
+            break;
+#endif
+        res = dir_next(dj, 0);      /* Next entry */
+    } while (res == FR_OK);
+
+    return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory                                     */
+/*-----------------------------------------------------------------------*/
+#if _FS_MINIMIZE <= 1
+static
+FRESULT dir_read (
+    FATFS_DIR *dj         /* Pointer to the directory object that pointing the entry to be read */
+)
+{
+    FRESULT res;
+    BYTE c, *dir;
+#if _USE_LFN
+    BYTE a, ord = 0xFF, sum = 0xFF;
+#endif
+
+    res = FR_NO_FILE;
+    while (dj->sect) {
+        res = move_window(dj->fs, dj->sect);
+        if (res != FR_OK) break;
+        dir = dj->dir;                  /* Ptr to the directory entry of current index */
+        c = dir[DIR_Name];
+        if (c == 0) {
+            res = FR_NO_FILE;    /* Reached to end of table */
+            break;
+        }
+#if _USE_LFN    /* LFN configuration */
+        a = dir[DIR_Attr] & AM_MASK;
+        if (c == DDE || (!_FS_RPATH && c == '.') || ((a & AM_VOL) && a != AM_LFN)) {    /* An entry without valid data */
+            ord = 0xFF;
+        } else {
+            if (a == AM_LFN) {          /* An LFN entry is found */
+                if (c & LLE) {          /* Is it start of LFN sequence? */
+                    sum = dir[LDIR_Chksum];
+                    c &= ~LLE;
+                    ord = c;
+                    dj->lfn_idx = dj->index;
+                }
+                /* Check LFN validity and capture it */
+                ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF;
+            } else {                    /* An SFN entry is found */
+                if (ord || sum != sum_sfn(dir)) /* Is there a valid LFN? */
+                    dj->lfn_idx = 0xFFFF;       /* It has no LFN. */
+                break;
+            }
+        }
+#else       /* Non LFN configuration */
+        if (c != DDE && (_FS_RPATH || c != '.') && !(dir[DIR_Attr] & AM_VOL))   /* Is it a valid entry? */
+            break;
+#endif
+        res = dir_next(dj, 0);              /* Next entry */
+        if (res != FR_OK) break;
+    }
+
+    if (res != FR_OK) dj->sect = 0;
+
+    return res;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Register an object to the directory                                   */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT dir_register (  /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */
+    FATFS_DIR *dj             /* Target directory with object name to be created */
+)
+{
+    FRESULT res;
+    BYTE c, *dir;
+#if _USE_LFN    /* LFN configuration */
+    WORD n, ne, is;
+    BYTE sn[12], *fn, sum;
+    WCHAR *lfn;
+
+
+    fn = dj->fn;
+    lfn = dj->lfn;
+    mem_cpy(sn, fn, 12);
+
+    if (_FS_RPATH && (sn[NS] & NS_DOT))     /* Cannot create dot entry */
+        return FR_INVALID_NAME;
+
+    if (sn[NS] & NS_LOSS) {         /* When LFN is out of 8.3 format, generate a numbered name */
+        fn[NS] = 0;
+        dj->lfn = 0;            /* Find only SFN */
+        for (n = 1; n < 100; n++) {
+            gen_numname(fn, sn, lfn, n);    /* Generate a numbered name */
+            res = dir_find(dj);             /* Check if the name collides with existing SFN */
+            if (res != FR_OK) break;
+        }
+        if (n == 100) return FR_DENIED;     /* Abort if too many collisions */
+        if (res != FR_NO_FILE) return res;  /* Abort if the result is other than 'not collided' */
+        fn[NS] = sn[NS];
+        dj->lfn = lfn;
+    }
+
+    if (sn[NS] & NS_LFN) {          /* When LFN is to be created, reserve an SFN + LFN entries. */
+        for (ne = 0; lfn[ne]; ne++) ;
+        ne = (ne + 25) / 13;
+    } else {                        /* Otherwise reserve only an SFN entry. */
+        ne = 1;
+    }
+
+    /* Reserve contiguous entries */
+    res = dir_sdi(dj, 0);
+    if (res != FR_OK) return res;
+    n = is = 0;
+    do {
+        res = move_window(dj->fs, dj->sect);
+        if (res != FR_OK) break;
+        c = *dj->dir;               /* Check the entry status */
+        if (c == DDE || c == 0) {   /* Is it a blank entry? */
+            if (n == 0) is = dj->index; /* First index of the contiguous entry */
+            if (++n == ne) break;   /* A contiguous entry that required count is found */
+        } else {
+            n = 0;                  /* Not a blank entry. Restart to search */
+        }
+        res = dir_next(dj, 1);      /* Next entry with table stretch */
+    } while (res == FR_OK);
+
+    if (res == FR_OK && ne > 1) {   /* Initialize LFN entry if needed */
+        res = dir_sdi(dj, is);
+        if (res == FR_OK) {
+            sum = sum_sfn(dj->fn);  /* Sum of the SFN tied to the LFN */
+            ne--;
+            do {                    /* Store LFN entries in bottom first */
+                res = move_window(dj->fs, dj->sect);
+                if (res != FR_OK) break;
+                fit_lfn(dj->lfn, dj->dir, (BYTE)ne, sum);
+                dj->fs->wflag = 1;
+                res = dir_next(dj, 0);  /* Next entry */
+            } while (res == FR_OK && --ne);
+        }
+    }
+
+#else   /* Non LFN configuration */
+    res = dir_sdi(dj, 0);
+    if (res == FR_OK) {
+        do {    /* Find a blank entry for the SFN */
+            res = move_window(dj->fs, dj->sect);
+            if (res != FR_OK) break;
+            c = *dj->dir;
+            if (c == DDE || c == 0) break;  /* Is it a blank entry? */
+            res = dir_next(dj, 1);          /* Next entry with table stretch */
+        } while (res == FR_OK);
+    }
+#endif
+
+    if (res == FR_OK) {     /* Initialize the SFN entry */
+        res = move_window(dj->fs, dj->sect);
+        if (res == FR_OK) {
+            dir = dj->dir;
+            mem_set(dir, 0, SZ_DIR);    /* Clean the entry */
+            mem_cpy(dir, dj->fn, 11);   /* Put SFN */
+#if _USE_LFN
+            dir[DIR_NTres] = *(dj->fn+NS) & (NS_BODY | NS_EXT); /* Put NT flag */
+#endif
+            dj->fs->wflag = 1;
+        }
+    }
+
+    return res;
+}
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Remove an object from the directory                                   */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY && !_FS_MINIMIZE
+static
+FRESULT dir_remove (    /* FR_OK: Successful, FR_DISK_ERR: A disk error */
+    FATFS_DIR *dj             /* Directory object pointing the entry to be removed */
+)
+{
+    FRESULT res;
+#if _USE_LFN    /* LFN configuration */
+    WORD i;
+
+    i = dj->index;  /* SFN index */
+    res = dir_sdi(dj, (WORD)((dj->lfn_idx == 0xFFFF) ? i : dj->lfn_idx));   /* Goto the SFN or top of the LFN entries */
+    if (res == FR_OK) {
+        do {
+            res = move_window(dj->fs, dj->sect);
+            if (res != FR_OK) break;
+            *dj->dir = DDE;         /* Mark the entry "deleted" */
+            dj->fs->wflag = 1;
+            if (dj->index >= i) break;  /* When reached SFN, all entries of the object has been deleted. */
+            res = dir_next(dj, 0);      /* Next entry */
+        } while (res == FR_OK);
+        if (res == FR_NO_FILE) res = FR_INT_ERR;
+    }
+
+#else           /* Non LFN configuration */
+    res = dir_sdi(dj, dj->index);
+    if (res == FR_OK) {
+        res = move_window(dj->fs, dj->sect);
+        if (res == FR_OK) {
+            *dj->dir = DDE;         /* Mark the entry "deleted" */
+            dj->fs->wflag = 1;
+        }
+    }
+#endif
+
+    return res;
+}
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a segment and create the object name in directory form           */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT create_name (
+    FATFS_DIR *dj,            /* Pointer to the directory object */
+    const TCHAR **path  /* Pointer to pointer to the segment in the path string */
+)
+{
+#ifdef _EXCVT
+    static const BYTE excvt[] = _EXCVT; /* Upper conversion table for extended chars */
+#endif
+
+#if _USE_LFN    /* LFN configuration */
+    BYTE b, cf;
+    WCHAR w, *lfn;
+    UINT i, ni, si, di;
+    const TCHAR *p;
+
+    /* Create LFN in Unicode */
+    for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */
+    lfn = dj->lfn;
+    si = di = 0;
+    for (;;) {
+        w = p[si++];                    /* Get a character */
+        if (w < ' ' || w == '/' || w == '\\') break;    /* Break on end of segment */
+        if (di >= _MAX_LFN)             /* Reject too long name */
+            return FR_INVALID_NAME;
+#if !_LFN_UNICODE
+        w &= 0xFF;
+        if (IsDBCS1(w)) {               /* Check if it is a DBC 1st byte (always false on SBCS cfg) */
+            b = (BYTE)p[si++];          /* Get 2nd byte */
+            if (!IsDBCS2(b))
+                return FR_INVALID_NAME; /* Reject invalid sequence */
+            else
+                w = (w << 8) + b;           /* Create a DBC */
+        }
+        w = ff_convert(w, 1);           /* Convert ANSI/OEM to Unicode */
+        if (!w) return FR_INVALID_NAME; /* Reject invalid code */
+#endif
+        if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal chars for LFN */
+            return FR_INVALID_NAME;
+        lfn[di++] = w;                  /* Store the Unicode char */
+    }
+    *path = &p[si];                     /* Return pointer to the next segment */
+    cf = (w < ' ') ? NS_LAST : 0;       /* Set last segment flag if end of path */
+#if _FS_RPATH
+    if ((di == 1 && lfn[di-1] == '.') || /* Is this a dot entry? */
+            (di == 2 && lfn[di-1] == '.' && lfn[di-2] == '.')) {
+        lfn[di] = 0;
+        for (i = 0; i < 11; i++)
+            dj->fn[i] = (i < di) ? '.' : ' ';
+        dj->fn[i] = cf | NS_DOT;        /* This is a dot entry */
+        return FR_OK;
+    }
+#endif
+    while (di) {                        /* Strip trailing spaces and dots */
+        w = lfn[di-1];
+        if (w != ' ' && w != '.') break;
+        di--;
+    }
+    if (!di) return FR_INVALID_NAME;    /* Reject nul string */
+
+    lfn[di] = 0;                        /* LFN is created */
+
+    /* Create SFN in directory form */
+    mem_set(dj->fn, ' ', 11);
+    for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ;  /* Strip leading spaces and dots */
+    if (si) cf |= NS_LOSS | NS_LFN;
+    while (di && lfn[di - 1] != '.') di--;  /* Find extension (di<=si: no extension) */
+
+    b = i = 0;
+    ni = 8;
+    for (;;) {
+        w = lfn[si++];                  /* Get an LFN char */
+        if (!w) break;                  /* Break on end of the LFN */
+        if (w == ' ' || (w == '.' && si != di)) {   /* Remove spaces and dots */
+            cf |= NS_LOSS | NS_LFN;
+            continue;
+        }
+
+        if (i >= ni || si == di) {      /* Extension or end of SFN */
+            if (ni == 11) {             /* Long extension */
+                cf |= NS_LOSS | NS_LFN;
+                break;
+            }
+            if (si != di) cf |= NS_LOSS | NS_LFN;   /* Out of 8.3 format */
+            if (si > di) break;         /* No extension */
+            si = di;
+            i = 8;
+            ni = 11;    /* Enter extension section */
+            b <<= 2;
+            continue;
+        }
+
+        if (w >= 0x80) {                /* Non ASCII char */
+#ifdef _EXCVT
+            w = ff_convert(w, 0);       /* Unicode -> OEM code */
+            if (w) w = excvt[w - 0x80]; /* Convert extended char to upper (SBCS) */
+#else
+            w = ff_convert(ff_wtoupper(w), 0);  /* Upper converted Unicode -> OEM code */
+#endif
+            cf |= NS_LFN;               /* Force create LFN entry */
+        }
+
+        if (_DF1S && w >= 0x100) {      /* Double byte char (always false on SBCS cfg) */
+            if (i >= ni - 1) {
+                cf |= NS_LOSS | NS_LFN;
+                i = ni;
+                continue;
+            }
+            dj->fn[i++] = (BYTE)(w >> 8);
+        } else {                        /* Single byte char */
+            if (!w || chk_chr("+,;=[]", w)) {   /* Replace illegal chars for SFN */
+                w = '_';
+                cf |= NS_LOSS | NS_LFN;/* Lossy conversion */
+            } else {
+                if (IsUpper(w)) {       /* ASCII large capital */
+                    b |= 2;
+                } else {
+                    if (IsLower(w)) {   /* ASCII small capital */
+                        b |= 1;
+                        w -= 0x20;
+                    }
+                }
+            }
+        }
+        dj->fn[i++] = (BYTE)w;
+    }
+
+    if (dj->fn[0] == DDE) dj->fn[0] = NDDE; /* If the first char collides with deleted mark, replace it with 0x05 */
+
+    if (ni == 8) b <<= 2;
+    if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03)   /* Create LFN entry when there are composite capitals */
+        cf |= NS_LFN;
+    if (!(cf & NS_LFN)) {                       /* When LFN is in 8.3 format without extended char, NT flags are created */
+        if ((b & 0x03) == 0x01) cf |= NS_EXT;   /* NT flag (Extension has only small capital) */
+        if ((b & 0x0C) == 0x04) cf |= NS_BODY;  /* NT flag (Filename has only small capital) */
+    }
+
+    dj->fn[NS] = cf;    /* SFN is created */
+
+    return FR_OK;
+
+
+#else   /* Non-LFN configuration */
+    BYTE b, c, d, *sfn;
+    UINT ni, si, i;
+    const char *p;
+
+    /* Create file name in directory form */
+    for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */
+    sfn = dj->fn;
+    mem_set(sfn, ' ', 11);
+    si = i = b = 0;
+    ni = 8;
+#if _FS_RPATH
+    if (p[si] == '.') { /* Is this a dot entry? */
+        for (;;) {
+            c = (BYTE)p[si++];
+            if (c != '.' || si >= 3) break;
+            sfn[i++] = c;
+        }
+        if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME;
+        *path = &p[si];                                 /* Return pointer to the next segment */
+        sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT;   /* Set last segment flag if end of path */
+        return FR_OK;
+    }
+#endif
+    for (;;) {
+        c = (BYTE)p[si++];
+        if (c <= ' ' || c == '/' || c == '\\') break;   /* Break on end of segment */
+        if (c == '.' || i >= ni) {
+            if (ni != 8 || c != '.') return FR_INVALID_NAME;
+            i = 8;
+            ni = 11;
+            b <<= 2;
+            continue;
+        }
+        if (c >= 0x80) {                /* Extended char? */
+            b |= 3;                     /* Eliminate NT flag */
+#ifdef _EXCVT
+            c = excvt[c - 0x80];        /* Upper conversion (SBCS) */
+#else
+#if !_DF1S  /* ASCII only cfg */
+            return FR_INVALID_NAME;
+#endif
+#endif
+        }
+        if (IsDBCS1(c)) {               /* Check if it is a DBC 1st byte (always false on SBCS cfg) */
+            d = (BYTE)p[si++];          /* Get 2nd byte */
+            if (!IsDBCS2(d) || i >= ni - 1) /* Reject invalid DBC */
+                return FR_INVALID_NAME;
+            sfn[i++] = c;
+            sfn[i++] = d;
+        } else {                        /* Single byte code */
+            if (chk_chr("\"*+,:;<=>\?[]|\x7F", c))  /* Reject illegal chrs for SFN */
+                return FR_INVALID_NAME;
+            if (IsUpper(c)) {           /* ASCII large capital? */
+                b |= 2;
+            } else {
+                if (IsLower(c)) {       /* ASCII small capital? */
+                    b |= 1;
+                    c -= 0x20;
+                }
+            }
+            sfn[i++] = c;
+        }
+    }
+    *path = &p[si];                     /* Return pointer to the next segment */
+    c = (c <= ' ') ? NS_LAST : 0;       /* Set last segment flag if end of path */
+
+    if (!i) return FR_INVALID_NAME;     /* Reject nul string */
+    if (sfn[0] == DDE) sfn[0] = NDDE;   /* When first char collides with DDE, replace it with 0x05 */
+
+    if (ni == 8) b <<= 2;
+    if ((b & 0x03) == 0x01) c |= NS_EXT;    /* NT flag (Name extension has only small capital) */
+    if ((b & 0x0C) == 0x04) c |= NS_BODY;   /* NT flag (Name body has only small capital) */
+
+    sfn[NS] = c;        /* Store NT flag, File name is created */
+
+    return FR_OK;
+#endif
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry                             */
+/*-----------------------------------------------------------------------*/
+#if _FS_MINIMIZE <= 1
+static
+void get_fileinfo (     /* No return code */
+    FATFS_DIR *dj,            /* Pointer to the directory object */
+    FILINFO *fno        /* Pointer to the file information to be filled */
+)
+{
+    UINT i;
+    BYTE nt, *dir;
+    TCHAR *p, c;
+
+
+    p = fno->fname;
+    if (dj->sect) {
+        dir = dj->dir;
+        nt = dir[DIR_NTres];        /* NT flag */
+        for (i = 0; i < 8; i++) {   /* Copy name body */
+            c = dir[i];
+            if (c == ' ') break;
+            if (c == NDDE) c = (TCHAR)DDE;
+            if (_USE_LFN && (nt & NS_BODY) && IsUpper(c)) c += 0x20;
+#if _LFN_UNICODE
+            if (IsDBCS1(c) && i < 7 && IsDBCS2(dir[i+1]))
+                c = (c << 8) | dir[++i];
+            c = ff_convert(c, 1);
+            if (!c) c = '?';
+#endif
+            *p++ = c;
+        }
+        if (dir[8] != ' ') {        /* Copy name extension */
+            *p++ = '.';
+            for (i = 8; i < 11; i++) {
+                c = dir[i];
+                if (c == ' ') break;
+                if (_USE_LFN && (nt & NS_EXT) && IsUpper(c)) c += 0x20;
+#if _LFN_UNICODE
+                if (IsDBCS1(c) && i < 10 && IsDBCS2(dir[i+1]))
+                    c = (c << 8) | dir[++i];
+                c = ff_convert(c, 1);
+                if (!c) c = '?';
+#endif
+                *p++ = c;
+            }
+        }
+        fno->fattrib = dir[DIR_Attr];               /* Attribute */
+        fno->fsize = LD_DWORD(dir+DIR_FileSize);    /* Size */
+        fno->fdate = LD_WORD(dir+DIR_WrtDate);      /* Date */
+        fno->ftime = LD_WORD(dir+DIR_WrtTime);      /* Time */
+    }
+    *p = 0;     /* Terminate SFN str by a \0 */
+
+#if _USE_LFN
+    if (fno->lfname && fno->lfsize) {
+        TCHAR *tp = fno->lfname;
+        WCHAR w, *lfn;
+
+        i = 0;
+        if (dj->sect && dj->lfn_idx != 0xFFFF) {/* Get LFN if available */
+            lfn = dj->lfn;
+            while ((w = *lfn++) != 0) {         /* Get an LFN char */
+#if !_LFN_UNICODE
+                w = ff_convert(w, 0);           /* Unicode -> OEM conversion */
+                if (!w) {
+                    i = 0;    /* Could not convert, no LFN */
+                    break;
+                }
+                if (_DF1S && w >= 0x100)        /* Put 1st byte if it is a DBC (always false on SBCS cfg) */
+                    tp[i++] = (TCHAR)(w >> 8);
+#endif
+                if (i >= fno->lfsize - 1) {
+                    i = 0;    /* Buffer overflow, no LFN */
+                    break;
+                }
+                tp[i++] = (TCHAR)w;
+            }
+        }
+        tp[i] = 0;  /* Terminate the LFN str by a \0 */
+    }
+#endif
+}
+#endif /* _FS_MINIMIZE <= 1 */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path                                                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path (   /* FR_OK(0): successful, !=0: error code */
+    FATFS_DIR *dj,            /* Directory object to return last directory and found object */
+    const TCHAR *path   /* Full-path string to find a file or directory */
+)
+{
+    FRESULT res;
+    BYTE *dir, ns;
+
+
+#if _FS_RPATH
+    if (*path == '/' || *path == '\\') { /* There is a heading separator */
+        path++;
+        dj->sclust = 0;     /* Strip it and start from the root dir */
+    } else {                            /* No heading separator */
+        dj->sclust = dj->fs->cdir;  /* Start from the current dir */
+    }
+#else
+    if (*path == '/' || *path == '\\')  /* Strip heading separator if exist */
+        path++;
+    dj->sclust = 0;                     /* Start from the root dir */
+#endif
+
+    if ((UINT)*path < ' ') {            /* Nul path means the start directory itself */
+        res = dir_sdi(dj, 0);
+        dj->dir = 0;
+    } else {                            /* Follow path */
+        for (;;) {
+            res = create_name(dj, &path);   /* Get a segment */
+            if (res != FR_OK) break;
+            res = dir_find(dj);             /* Find it */
+            ns = *(dj->fn+NS);
+            if (res != FR_OK) {             /* Failed to find the object */
+                if (res != FR_NO_FILE) break;   /* Abort if any hard error occurred */
+                /* Object not found */
+                if (_FS_RPATH && (ns & NS_DOT)) {   /* If dot entry is not exit */
+                    dj->sclust = 0;
+                    dj->dir = 0;    /* It is the root dir */
+                    res = FR_OK;
+                    if (!(ns & NS_LAST)) continue;
+                } else {                            /* Could not find the object */
+                    if (!(ns & NS_LAST)) res = FR_NO_PATH;
+                }
+                break;
+            }
+            if (ns & NS_LAST) break;            /* Last segment match. Function completed. */
+            dir = dj->dir;                      /* There is next segment. Follow the sub directory */
+            if (!(dir[DIR_Attr] & AM_DIR)) {    /* Cannot follow because it is a file */
+                res = FR_NO_PATH;
+                break;
+            }
+            dj->sclust = ld_clust(dj->fs, dir);
+        }
+    }
+
+    return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Load a sector and check if it is an FAT Volume Boot Record            */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs ( /* 0:FAT-VBR, 1:Any BR but not FAT, 2:Not a BR, 3:Disk error */
+    FATFS *fs,  /* File system object */
+    DWORD sect  /* Sector# (lba) to check if it is an FAT boot record or not */
+)
+{
+    if (disk_read(fs->drv, fs->win, sect, 1) != RES_OK) /* Load boot record */
+        return 3;
+    if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55)       /* Check record signature (always placed at offset 510 even if the sector size is >512) */
+        return 2;
+
+    if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */
+        return 0;
+    if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146)
+        return 0;
+
+    return 1;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check if the file system object is valid or not                       */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT chk_mounted (   /* FR_OK(0): successful, !=0: any error occurred */
+    const TCHAR **path, /* Pointer to pointer to the path name (drive number) */
+    FATFS **rfs,        /* Pointer to pointer to the found file system object */
+    BYTE wmode          /* !=0: Check write protection for write access */
+)
+{
+    BYTE fmt, b, pi, *tbl;
+    UINT vol;
+    DSTATUS stat;
+    DWORD bsect, fasize, tsect, sysect, nclst, szbfat;
+    WORD nrsv;
+    const TCHAR *p = *path;
+    FATFS *fs;
+
+
+    /* Get logical drive number from the path name */
+    vol = p[0] - '0';                   /* Is there a drive number? */
+    if (vol <= 9 && p[1] == ':') {      /* Found a drive number, get and strip it */
+        p += 2;
+        *path = p;              /* Return pointer to the path name */
+    } else {                            /* No drive number is given */
+#if _FS_RPATH
+        vol = CurrVol;                  /* Use current drive */
+#else
+        vol = 0;                        /* Use drive 0 */
+#endif
+    }
+
+    /* Check if the file system object is valid or not */
+    *rfs = 0;
+    if (vol >= _VOLUMES)                /* Is the drive number valid? */
+        return FR_INVALID_DRIVE;
+    fs = FatFs[vol];                    /* Get corresponding file system object */
+    if (!fs) return FR_NOT_ENABLED;     /* Is the file system object available? */
+
+    ENTER_FF(fs);                       /* Lock file system */
+
+    *rfs = fs;                          /* Return pointer to the corresponding file system object */
+    if (fs->fs_type) {                  /* If the volume has been mounted */
+        stat = disk_status(fs->drv);
+        if (!(stat & STA_NOINIT)) {     /* and the physical drive is kept initialized (has not been changed), */
+            if (!_FS_READONLY && wmode && (stat & STA_PROTECT)) /* Check write protection if needed */
+                return FR_WRITE_PROTECTED;
+            return FR_OK;               /* The file system object is valid */
+        }
+    }
+
+    /* The file system object is not valid. */
+    /* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */
+
+    fs->fs_type = 0;                    /* Clear the file system object */
+    fs->drv = LD2PD(vol);               /* Bind the logical drive and a physical drive */
+    stat = disk_initialize(fs->drv);    /* Initialize the physical drive */
+    if (stat & STA_NOINIT)              /* Check if the initialization succeeded */
+        return FR_NOT_READY;            /* Failed to initialize due to no medium or hard error */
+    if (!_FS_READONLY && wmode && (stat & STA_PROTECT)) /* Check disk write protection if needed */
+        return FR_WRITE_PROTECTED;
+#if _MAX_SS != 512                      /* Get disk sector size (variable sector size cfg only) */
+    if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &fs->ssize) != RES_OK)
+        return FR_DISK_ERR;
+#endif
+    /* Search FAT partition on the drive. Supports only generic partitions, FDISK and SFD. */
+    fmt = check_fs(fs, bsect = 0);      /* Load sector 0 and check if it is an FAT-VBR (in SFD) */
+    if (LD2PT(vol) && !fmt) fmt = 1;    /* Force non-SFD if the volume is forced partition */
+    if (fmt == 1) {                     /* Not an FAT-VBR, the physical drive can be partitioned */
+        /* Check the partition listed in the partition table */
+        pi = LD2PT(vol);
+        if (pi) pi--;
+        tbl = &fs->win[MBR_Table + pi * SZ_PTE];/* Partition table */
+        if (tbl[4]) {                       /* Is the partition existing? */
+            bsect = LD_DWORD(&tbl[8]);      /* Partition offset in LBA */
+            fmt = check_fs(fs, bsect);      /* Check the partition */
+        }
+    }
+    if (fmt == 3) return FR_DISK_ERR;
+    if (fmt) return FR_NO_FILESYSTEM;       /* No FAT volume is found */
+
+    /* An FAT volume is found. Following code initializes the file system object */
+
+    if (LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs))      /* (BPB_BytsPerSec must be equal to the physical sector size) */
+        return FR_NO_FILESYSTEM;
+
+    fasize = LD_WORD(fs->win+BPB_FATSz16);              /* Number of sectors per FAT */
+    if (!fasize) fasize = LD_DWORD(fs->win+BPB_FATSz32);
+    fs->fsize = fasize;
+
+    fs->n_fats = b = fs->win[BPB_NumFATs];              /* Number of FAT copies */
+    if (b != 1 && b != 2) return FR_NO_FILESYSTEM;      /* (Must be 1 or 2) */
+    fasize *= b;                                        /* Number of sectors for FAT area */
+
+    fs->csize = b = fs->win[BPB_SecPerClus];            /* Number of sectors per cluster */
+    if (!b || (b & (b - 1))) return FR_NO_FILESYSTEM;   /* (Must be power of 2) */
+
+    fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt);    /* Number of root directory entries */
+    if (fs->n_rootdir % (SS(fs) / SZ_DIR)) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be sector aligned) */
+
+    tsect = LD_WORD(fs->win+BPB_TotSec16);              /* Number of sectors on the volume */
+    if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32);
+
+    nrsv = LD_WORD(fs->win+BPB_RsvdSecCnt);             /* Number of reserved sectors */
+    if (!nrsv) return FR_NO_FILESYSTEM;                 /* (BPB_RsvdSecCnt must not be 0) */
+
+    /* Determine the FAT sub type */
+    sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZ_DIR); /* RSV+FAT+DIR */
+    if (tsect < sysect) return FR_NO_FILESYSTEM;        /* (Invalid volume size) */
+    nclst = (tsect - sysect) / fs->csize;               /* Number of clusters */
+    if (!nclst) return FR_NO_FILESYSTEM;                /* (Invalid volume size) */
+    fmt = FS_FAT12;
+    if (nclst >= MIN_FAT16) fmt = FS_FAT16;
+    if (nclst >= MIN_FAT32) fmt = FS_FAT32;
+
+    /* Boundaries and Limits */
+    fs->n_fatent = nclst + 2;                           /* Number of FAT entries */
+    fs->database = bsect + sysect;                      /* Data start sector */
+    fs->fatbase = bsect + nrsv;                         /* FAT start sector */
+    if (fmt == FS_FAT32) {
+        if (fs->n_rootdir) return FR_NO_FILESYSTEM;     /* (BPB_RootEntCnt must be 0) */
+        fs->dirbase = LD_DWORD(fs->win+BPB_RootClus);   /* Root directory start cluster */
+        szbfat = fs->n_fatent * 4;                      /* (Required FAT size) */
+    } else {
+        if (!fs->n_rootdir) return FR_NO_FILESYSTEM;    /* (BPB_RootEntCnt must not be 0) */
+        fs->dirbase = fs->fatbase + fasize;             /* Root directory start sector */
+        szbfat = (fmt == FS_FAT16) ?                    /* (Required FAT size) */
+                 fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
+    }
+    if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs))   /* (BPB_FATSz must not be less than required) */
+        return FR_NO_FILESYSTEM;
+
+#if !_FS_READONLY
+    /* Initialize cluster allocation information */
+    fs->free_clust = 0xFFFFFFFF;
+    fs->last_clust = 0;
+
+    /* Get fsinfo if available */
+    if (fmt == FS_FAT32) {
+        fs->fsi_flag = 0;
+        fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo);
+        if (disk_read(fs->drv, fs->win, fs->fsi_sector, 1) == RES_OK &&
+                LD_WORD(fs->win+BS_55AA) == 0xAA55 &&
+                LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 &&
+                LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) {
+            fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free);
+            fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count);
+        }
+    }
+#endif
+    fs->fs_type = fmt;      /* FAT sub-type */
+    fs->id = ++Fsid;        /* File system mount ID */
+    fs->winsect = 0;        /* Invalidate sector cache */
+    fs->wflag = 0;
+#if _FS_RPATH
+    fs->cdir = 0;           /* Current directory (root dir) */
+#endif
+#if _FS_LOCK                /* Clear file lock semaphores */
+    clear_lock(fs);
+#endif
+
+    return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check if the file/dir object is valid or not                          */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT validate (  /* FR_OK(0): The object is valid, !=0: Invalid */
+    void* obj       /* Pointer to the object FIL/DIR to check validity */
+)
+{
+    FIL *fil;
+
+
+    fil = (FIL*)obj;    /* Assuming offset of fs and id in the FIL/DIR is identical */
+    if (!fil->fs || !fil->fs->fs_type || fil->fs->id != fil->id)
+        return FR_INVALID_OBJECT;
+
+    ENTER_FF(fil->fs);      /* Lock file system */
+
+    if (disk_status(fil->fs->drv) & STA_NOINIT)
+        return FR_NOT_READY;
+
+    return FR_OK;
+}
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Public Functions
+
+--------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Logical Drive                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mount (
+    BYTE vol,       /* Logical drive number to be mounted/unmounted */
+    FATFS *fs       /* Pointer to new file system object (NULL for unmount)*/
+)
+{
+    FATFS *rfs;
+
+
+    if (vol >= _VOLUMES)        /* Check if the drive number is valid */
+        return FR_INVALID_DRIVE;
+    rfs = FatFs[vol];           /* Get current fs object */
+
+    if (rfs) {
+#if _FS_LOCK
+        clear_lock(rfs);
+#endif
+#if _FS_REENTRANT               /* Discard sync object of the current volume */
+        if (!ff_del_syncobj(rfs->sobj)) return FR_INT_ERR;
+#endif
+        rfs->fs_type = 0;       /* Clear old fs object */
+    }
+
+    if (fs) {
+        fs->fs_type = 0;        /* Clear new fs object */
+#if _FS_REENTRANT               /* Create sync object for the new volume */
+        if (!ff_cre_syncobj(vol, &fs->sobj)) return FR_INT_ERR;
+#endif
+    }
+    FatFs[vol] = fs;            /* Register new fs object */
+
+    return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_open (
+    FIL *fp,            /* Pointer to the blank file object */
+    const TCHAR *path,  /* Pointer to the file name */
+    BYTE mode           /* Access mode and file open mode flags */
+)
+{
+    FRESULT res;
+    FATFS_DIR dj;
+    BYTE *dir;
+    DEF_NAMEBUF;
+
+
+    if (!fp) return FR_INVALID_OBJECT;
+    fp->fs = 0;         /* Clear file object */
+
+#if !_FS_READONLY
+    mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW;
+    res = chk_mounted(&path, &dj.fs, (BYTE)(mode & ~FA_READ));
+#else
+    mode &= FA_READ;
+    res = chk_mounted(&path, &dj.fs, 0);
+#endif
+    if (res == FR_OK) {
+        INIT_BUF(dj);
+        res = follow_path(&dj, path);   /* Follow the file path */
+        dir = dj.dir;
+#if !_FS_READONLY   /* R/W configuration */
+        if (res == FR_OK) {
+            if (!dir)   /* Current dir itself */
+                res = FR_INVALID_NAME;
+#if _FS_LOCK
+            else
+                res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+#endif
+        }
+        /* Create or Open a file */
+        if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) {
+            DWORD dw, cl;
+
+            if (res != FR_OK) {                 /* No file, create new */
+                if (res == FR_NO_FILE)          /* There is no file to open, create a new entry */
+#if _FS_LOCK
+                    res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
+#else
+                    res = dir_register(&dj);
+#endif
+                mode |= FA_CREATE_ALWAYS;       /* File is created */
+                dir = dj.dir;                   /* New entry */
+            } else {                            /* Any object is already existing */
+                if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) {    /* Cannot overwrite it (R/O or DIR) */
+                    res = FR_DENIED;
+                } else {
+                    if (mode & FA_CREATE_NEW)   /* Cannot create as new file */
+                        res = FR_EXIST;
+                }
+            }
+            if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) {    /* Truncate it if overwrite mode */
+                dw = get_fattime();                 /* Created time */
+                ST_DWORD(dir+DIR_CrtTime, dw);
+                dir[DIR_Attr] = 0;                  /* Reset attribute */
+                ST_DWORD(dir+DIR_FileSize, 0);      /* size = 0 */
+                cl = ld_clust(dj.fs, dir);          /* Get start cluster */
+                st_clust(dir, 0);                   /* cluster = 0 */
+                dj.fs->wflag = 1;
+                if (cl) {                           /* Remove the cluster chain if exist */
+                    dw = dj.fs->winsect;
+                    res = remove_chain(dj.fs, cl);
+                    if (res == FR_OK) {
+                        dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */
+                        res = move_window(dj.fs, dw);
+                    }
+                }
+            }
+        } else { /* Open an existing file */
+            if (res == FR_OK) {                     /* Follow succeeded */
+                if (dir[DIR_Attr] & AM_DIR) {       /* It is a directory */
+                    res = FR_NO_FILE;
+                } else {
+                    if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */
+                        res = FR_DENIED;
+                }
+            }
+        }
+        if (res == FR_OK) {
+            if (mode & FA_CREATE_ALWAYS)            /* Set file change flag if created or overwritten */
+                mode |= FA__WRITTEN;
+            fp->dir_sect = dj.fs->winsect;          /* Pointer to the directory entry */
+            fp->dir_ptr = dir;
+#if _FS_LOCK
+            fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+            if (!fp->lockid) res = FR_INT_ERR;
+#endif
+        }
+
+#else               /* R/O configuration */
+        if (res == FR_OK) {                 /* Follow succeeded */
+            dir = dj.dir;
+            if (!dir) {                     /* Current dir itself */
+                res = FR_INVALID_NAME;
+            } else {
+                if (dir[DIR_Attr] & AM_DIR) /* It is a directory */
+                    res = FR_NO_FILE;
+            }
+        }
+#endif
+        FREE_BUF();
+
+        if (res == FR_OK) {
+            fp->flag = mode;                    /* File access mode */
+            fp->sclust = ld_clust(dj.fs, dir);  /* File start cluster */
+            fp->fsize = LD_DWORD(dir+DIR_FileSize); /* File size */
+            fp->fptr = 0;                       /* File pointer */
+            fp->dsect = 0;
+#if _USE_FASTSEEK
+            fp->cltbl = 0;                      /* Normal seek mode */
+#endif
+            fp->fs = dj.fs;
+            fp->id = dj.fs->id; /* Validate file object */
+        }
+    }
+
+    LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File                                                             */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_read (
+    FIL *fp,        /* Pointer to the file object */
+    void *buff,     /* Pointer to data buffer */
+    UINT btr,       /* Number of bytes to read */
+    UINT *br        /* Pointer to number of bytes read */
+)
+{
+    FRESULT res;
+    DWORD clst, sect, remain;
+    UINT rcnt, cc;
+    BYTE csect, *rbuff = (BYTE *)buff;
+
+
+    *br = 0;    /* Clear read byte counter */
+
+    res = validate(fp);                         /* Check validity */
+    if (res != FR_OK) LEAVE_FF(fp->fs, res);
+    if (fp->flag & FA__ERROR)                   /* Aborted file? */
+        LEAVE_FF(fp->fs, FR_INT_ERR);
+    if (!(fp->flag & FA_READ))                  /* Check access mode */
+        LEAVE_FF(fp->fs, FR_DENIED);
+    remain = fp->fsize - fp->fptr;
+    if (btr > remain) btr = (UINT)remain;       /* Truncate btr by remaining bytes */
+
+    for ( ;  btr;                               /* Repeat until all data read */
+            rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) {
+        if ((fp->fptr % SS(fp->fs)) == 0) {     /* On the sector boundary? */
+            csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1));    /* Sector offset in the cluster */
+            if (!csect) {                       /* On the cluster boundary? */
+                if (fp->fptr == 0) {            /* On the top of the file? */
+                    clst = fp->sclust;          /* Follow from the origin */
+                } else {                        /* Middle or end of the file */
+#if _USE_FASTSEEK
+                    if (fp->cltbl)
+                        clst = clmt_clust(fp, fp->fptr);    /* Get cluster# from the CLMT */
+                    else
+#endif
+                        clst = get_fat(fp->fs, fp->clust);  /* Follow cluster chain on the FAT */
+                }
+                if (clst < 2) ABORT(fp->fs, FR_INT_ERR);
+                if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+                fp->clust = clst;               /* Update current cluster */
+            }
+            sect = clust2sect(fp->fs, fp->clust);   /* Get current sector */
+            if (!sect) ABORT(fp->fs, FR_INT_ERR);
+            sect += csect;
+            cc = btr / SS(fp->fs);              /* When remaining bytes >= sector size, */
+            if (cc) {                           /* Read maximum contiguous sectors directly */
+                if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */
+                    cc = fp->fs->csize - csect;
+                if (disk_read(fp->fs->drv, rbuff, sect, (BYTE)cc) != RES_OK)
+                    ABORT(fp->fs, FR_DISK_ERR);
+#if !_FS_READONLY && _FS_MINIMIZE <= 2          /* Replace one of the read sectors with cached data if it contains a dirty sector */
+#if _FS_TINY
+                if (fp->fs->wflag && fp->fs->winsect - sect < cc)
+                    mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs));
+#else
+                if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc)
+                    mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs));
+#endif
+#endif
+                rcnt = SS(fp->fs) * cc;         /* Number of bytes transferred */
+                continue;
+            }
+#if !_FS_TINY
+            if (fp->dsect != sect) {            /* Load data sector if not in cache */
+#if !_FS_READONLY
+                if (fp->flag & FA__DIRTY) {     /* Write-back dirty sector cache */
+                    if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+                        ABORT(fp->fs, FR_DISK_ERR);
+                    fp->flag &= ~FA__DIRTY;
+                }
+#endif
+                if (disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) /* Fill sector cache */
+                    ABORT(fp->fs, FR_DISK_ERR);
+            }
+#endif
+            fp->dsect = sect;
+        }
+        rcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs));  /* Get partial sector data from sector buffer */
+        if (rcnt > btr) rcnt = btr;
+#if _FS_TINY
+        if (move_window(fp->fs, fp->dsect))     /* Move sector window */
+            ABORT(fp->fs, FR_DISK_ERR);
+        mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt);  /* Pick partial sector */
+#else
+        mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt);  /* Pick partial sector */
+#endif
+    }
+
+    LEAVE_FF(fp->fs, FR_OK);
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Write File                                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_write (
+    FIL *fp,            /* Pointer to the file object */
+    const void *buff,   /* Pointer to the data to be written */
+    UINT btw,           /* Number of bytes to write */
+    UINT *bw            /* Pointer to number of bytes written */
+)
+{
+    FRESULT res;
+    DWORD clst, sect;
+    UINT wcnt, cc;
+    const BYTE *wbuff = (const BYTE *)buff;
+    BYTE csect;
+
+
+    *bw = 0;    /* Clear write byte counter */
+
+    res = validate(fp);                     /* Check validity */
+    if (res != FR_OK) LEAVE_FF(fp->fs, res);
+    if (fp->flag & FA__ERROR)               /* Aborted file? */
+        LEAVE_FF(fp->fs, FR_INT_ERR);
+    if (!(fp->flag & FA_WRITE))             /* Check access mode */
+        LEAVE_FF(fp->fs, FR_DENIED);
+    if ((DWORD)(fp->fsize + btw) < fp->fsize) btw = 0;  /* File size cannot reach 4GB */
+
+    for ( ;  btw;                           /* Repeat until all data written */
+            wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) {
+        if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */
+            csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1));    /* Sector offset in the cluster */
+            if (!csect) {                   /* On the cluster boundary? */
+                if (fp->fptr == 0) {        /* On the top of the file? */
+                    clst = fp->sclust;      /* Follow from the origin */
+                    if (clst == 0)          /* When no cluster is allocated, */
+                        fp->sclust = clst = create_chain(fp->fs, 0);    /* Create a new cluster chain */
+                } else {                    /* Middle or end of the file */
+#if _USE_FASTSEEK
+                    if (fp->cltbl)
+                        clst = clmt_clust(fp, fp->fptr);    /* Get cluster# from the CLMT */
+                    else
+#endif
+                        clst = create_chain(fp->fs, fp->clust); /* Follow or stretch cluster chain on the FAT */
+                }
+                if (clst == 0) break;       /* Could not allocate a new cluster (disk full) */
+                if (clst == 1) ABORT(fp->fs, FR_INT_ERR);
+                if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+                fp->clust = clst;           /* Update current cluster */
+            }
+#if _FS_TINY
+            if (fp->fs->winsect == fp->dsect && move_window(fp->fs, 0)) /* Write-back sector cache */
+                ABORT(fp->fs, FR_DISK_ERR);
+#else
+            if (fp->flag & FA__DIRTY) {     /* Write-back sector cache */
+                if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+                    ABORT(fp->fs, FR_DISK_ERR);
+                fp->flag &= ~FA__DIRTY;
+            }
+#endif
+            sect = clust2sect(fp->fs, fp->clust);   /* Get current sector */
+            if (!sect) ABORT(fp->fs, FR_INT_ERR);
+            sect += csect;
+            cc = btw / SS(fp->fs);          /* When remaining bytes >= sector size, */
+            if (cc) {                       /* Write maximum contiguous sectors directly */
+                if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */
+                    cc = fp->fs->csize - csect;
+                if (disk_write(fp->fs->drv, wbuff, sect, (BYTE)cc) != RES_OK)
+                    ABORT(fp->fs, FR_DISK_ERR);
+#if _FS_TINY
+                if (fp->fs->winsect - sect < cc) {  /* Refill sector cache if it gets invalidated by the direct write */
+                    mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs));
+                    fp->fs->wflag = 0;
+                }
+#else
+                if (fp->dsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
+                    mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs));
+                    fp->flag &= ~FA__DIRTY;
+                }
+#endif
+                wcnt = SS(fp->fs) * cc;     /* Number of bytes transferred */
+                continue;
+            }
+#if _FS_TINY
+            if (fp->fptr >= fp->fsize) {    /* Avoid silly cache filling at growing edge */
+                if (move_window(fp->fs, 0)) ABORT(fp->fs, FR_DISK_ERR);
+                fp->fs->winsect = sect;
+            }
+#else
+            if (fp->dsect != sect) {        /* Fill sector cache with file data */
+                if (fp->fptr < fp->fsize &&
+                        disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK)
+                    ABORT(fp->fs, FR_DISK_ERR);
+            }
+#endif
+            fp->dsect = sect;
+        }
+        wcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */
+        if (wcnt > btw) wcnt = btw;
+#if _FS_TINY
+        if (move_window(fp->fs, fp->dsect)) /* Move sector window */
+            ABORT(fp->fs, FR_DISK_ERR);
+        mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt);  /* Fit partial sector */
+        fp->fs->wflag = 1;
+#else
+        mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt);  /* Fit partial sector */
+        fp->flag |= FA__DIRTY;
+#endif
+    }
+
+    if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */
+    fp->flag |= FA__WRITTEN;                        /* Set file change flag */
+
+    LEAVE_FF(fp->fs, FR_OK);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Synchronize the File Object                                           */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_sync (
+    FIL *fp     /* Pointer to the file object */
+)
+{
+    FRESULT res;
+    DWORD tim;
+    BYTE *dir;
+
+
+    res = validate(fp);                 /* Check validity of the object */
+    if (res == FR_OK) {
+        if (fp->flag & FA__WRITTEN) {   /* Has the file been written? */
+#if !_FS_TINY   /* Write-back dirty buffer */
+            if (fp->flag & FA__DIRTY) {
+                if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+                    LEAVE_FF(fp->fs, FR_DISK_ERR);
+                fp->flag &= ~FA__DIRTY;
+            }
+#endif
+            /* Update the directory entry */
+            res = move_window(fp->fs, fp->dir_sect);
+            if (res == FR_OK) {
+                dir = fp->dir_ptr;
+                dir[DIR_Attr] |= AM_ARC;                    /* Set archive bit */
+                ST_DWORD(dir+DIR_FileSize, fp->fsize);      /* Update file size */
+                st_clust(dir, fp->sclust);                  /* Update start cluster */
+                tim = get_fattime();                        /* Update updated time */
+                ST_DWORD(dir+DIR_WrtTime, tim);
+                ST_WORD(dir+DIR_LstAccDate, 0);
+                fp->flag &= ~FA__WRITTEN;
+                fp->fs->wflag = 1;
+                res = sync(fp->fs);
+            }
+        }
+    }
+
+    LEAVE_FF(fp->fs, res);
+}
+
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Close File                                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_close (
+    FIL *fp     /* Pointer to the file object to be closed */
+)
+{
+    FRESULT res;
+
+
+#if _FS_READONLY
+    res = validate(fp);
+    {
+#if _FS_REENTRANT
+        FATFS *fs = fp->fs;
+#endif
+        if (res == FR_OK) fp->fs = 0;   /* Discard file object */
+        LEAVE_FF(fs, res);
+    }
+#else
+    res = f_sync(fp);       /* Flush cached data */
+#if _FS_LOCK
+    if (res == FR_OK) {     /* Decrement open counter */
+#if _FS_REENTRANT
+        FATFS *fs = fp->fs;;
+        res = validate(fp);
+        if (res == FR_OK) {
+            res = dec_lock(fp->lockid);
+            unlock_fs(fs, FR_OK);
+        }
+#else
+        res = dec_lock(fp->lockid);
+#endif
+    }
+#endif
+    if (res == FR_OK) fp->fs = 0;   /* Discard file object */
+    return res;
+#endif
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Current Drive/Directory Handlings                                     */
+/*-----------------------------------------------------------------------*/
+
+#if _FS_RPATH >= 1
+
+FRESULT f_chdrive (
+    BYTE drv        /* Drive number */
+)
+{
+    if (drv >= _VOLUMES) return FR_INVALID_DRIVE;
+
+    CurrVol = drv;
+
+    return FR_OK;
+}
+
+
+
+FRESULT f_chdir (
+    const TCHAR *path   /* Pointer to the directory path */
+)
+{
+    FRESULT res;
+    DIR dj;
+    DEF_NAMEBUF;
+
+
+    res = chk_mounted(&path, &dj.fs, 0);
+    if (res == FR_OK) {
+        INIT_BUF(dj);
+        res = follow_path(&dj, path);       /* Follow the path */
+        FREE_BUF();
+        if (res == FR_OK) {                 /* Follow completed */
+            if (!dj.dir) {
+                dj.fs->cdir = dj.sclust;    /* Start directory itself */
+            } else {
+                if (dj.dir[DIR_Attr] & AM_DIR)  /* Reached to the directory */
+                    dj.fs->cdir = ld_clust(dj.fs, dj.dir);
+                else
+                    res = FR_NO_PATH;       /* Reached but a file */
+            }
+        }
+        if (res == FR_NO_FILE) res = FR_NO_PATH;
+    }
+
+    LEAVE_FF(dj.fs, res);
+}
+
+
+#if _FS_RPATH >= 2
+FRESULT f_getcwd (
+    TCHAR *path,    /* Pointer to the directory path */
+    UINT sz_path    /* Size of path */
+)
+{
+    FRESULT res;
+    DIR dj;
+    UINT i, n;
+    DWORD ccl;
+    TCHAR *tp;
+    FILINFO fno;
+    DEF_NAMEBUF;
+
+
+    *path = 0;
+    res = chk_mounted((const TCHAR**)&path, &dj.fs, 0); /* Get current volume */
+    if (res == FR_OK) {
+        INIT_BUF(dj);
+        i = sz_path;        /* Bottom of buffer (dir stack base) */
+        dj.sclust = dj.fs->cdir;            /* Start to follow upper dir from current dir */
+        while ((ccl = dj.sclust) != 0) {    /* Repeat while current dir is a sub-dir */
+            res = dir_sdi(&dj, 1);          /* Get parent dir */
+            if (res != FR_OK) break;
+            res = dir_read(&dj);
+            if (res != FR_OK) break;
+            dj.sclust = ld_clust(dj.fs, dj.dir);    /* Goto parent dir */
+            res = dir_sdi(&dj, 0);
+            if (res != FR_OK) break;
+            do {                            /* Find the entry links to the child dir */
+                res = dir_read(&dj);
+                if (res != FR_OK) break;
+                if (ccl == ld_clust(dj.fs, dj.dir)) break;  /* Found the entry */
+                res = dir_next(&dj, 0);
+            } while (res == FR_OK);
+            if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
+            if (res != FR_OK) break;
+#if _USE_LFN
+            fno.lfname = path;
+            fno.lfsize = i;
+#endif
+            get_fileinfo(&dj, &fno);        /* Get the dir name and push it to the buffer */
+            tp = fno.fname;
+            if (_USE_LFN && *path) tp = path;
+            for (n = 0; tp[n]; n++) ;
+            if (i < n + 3) {
+                res = FR_NOT_ENOUGH_CORE;
+                break;
+            }
+            while (n) path[--i] = tp[--n];
+            path[--i] = '/';
+        }
+        tp = path;
+        if (res == FR_OK) {
+            *tp++ = '0' + CurrVol;          /* Put drive number */
+            *tp++ = ':';
+            if (i == sz_path) {             /* Root-dir */
+                *tp++ = '/';
+            } else {                        /* Sub-dir */
+                do      /* Add stacked path str */
+                    *tp++ = path[i++];
+                while (i < sz_path);
+            }
+        }
+        *tp = 0;
+        FREE_BUF();
+    }
+
+    LEAVE_FF(dj.fs, res);
+}
+#endif /* _FS_RPATH >= 2 */
+#endif /* _FS_RPATH >= 1 */
+
+
+
+#if _FS_MINIMIZE <= 2
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_lseek (
+    FIL *fp,        /* Pointer to the file object */
+    DWORD ofs       /* File pointer from top of file */
+)
+{
+    FRESULT res;
+
+
+    res = validate(fp);                 /* Check validity of the object */
+    if (res != FR_OK) LEAVE_FF(fp->fs, res);
+    if (fp->flag & FA__ERROR)           /* Check abort flag */
+        LEAVE_FF(fp->fs, FR_INT_ERR);
+
+#if _USE_FASTSEEK
+    if (fp->cltbl) {    /* Fast seek */
+        DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl;
+
+        if (ofs == CREATE_LINKMAP) {    /* Create CLMT */
+            tbl = fp->cltbl;
+            tlen = *tbl++;
+            ulen = 2;    /* Given table size and required table size */
+            cl = fp->sclust;            /* Top of the chain */
+            if (cl) {
+                do {
+                    /* Get a fragment */
+                    tcl = cl;
+                    ncl = 0;
+                    ulen += 2;   /* Top, length and used items */
+                    do {
+                        pcl = cl;
+                        ncl++;
+                        cl = get_fat(fp->fs, cl);
+                        if (cl <= 1) ABORT(fp->fs, FR_INT_ERR);
+                        if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+                    } while (cl == pcl + 1);
+                    if (ulen <= tlen) {     /* Store the length and top of the fragment */
+                        *tbl++ = ncl;
+                        *tbl++ = tcl;
+                    }
+                } while (cl < fp->fs->n_fatent);    /* Repeat until end of chain */
+            }
+            *fp->cltbl = ulen;  /* Number of items used */
+            if (ulen <= tlen)
+                *tbl = 0;       /* Terminate table */
+            else
+                res = FR_NOT_ENOUGH_CORE;   /* Given table size is smaller than required */
+
+        } else {                        /* Fast seek */
+            if (ofs > fp->fsize)        /* Clip offset at the file size */
+                ofs = fp->fsize;
+            fp->fptr = ofs;             /* Set file pointer */
+            if (ofs) {
+                fp->clust = clmt_clust(fp, ofs - 1);
+                dsc = clust2sect(fp->fs, fp->clust);
+                if (!dsc) ABORT(fp->fs, FR_INT_ERR);
+                dsc += (ofs - 1) / SS(fp->fs) & (fp->fs->csize - 1);
+                if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) {    /* Refill sector cache if needed */
+#if !_FS_TINY
+#if !_FS_READONLY
+                    if (fp->flag & FA__DIRTY) {     /* Write-back dirty sector cache */
+                        if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+                            ABORT(fp->fs, FR_DISK_ERR);
+                        fp->flag &= ~FA__DIRTY;
+                    }
+#endif
+                    if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK)  /* Load current sector */
+                        ABORT(fp->fs, FR_DISK_ERR);
+#endif
+                    fp->dsect = dsc;
+                }
+            }
+        }
+    } else
+#endif
+
+        /* Normal Seek */
+    {
+        DWORD clst, bcs, nsect, ifptr;
+
+        if (ofs > fp->fsize                 /* In read-only mode, clip offset with the file size */
+#if !_FS_READONLY
+                && !(fp->flag & FA_WRITE)
+#endif
+           ) ofs = fp->fsize;
+
+        ifptr = fp->fptr;
+        fp->fptr = nsect = 0;
+        if (ofs) {
+            bcs = (DWORD)fp->fs->csize * SS(fp->fs);    /* Cluster size (byte) */
+            if (ifptr > 0 &&
+                    (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */
+                fp->fptr = (ifptr - 1) & ~(bcs - 1);    /* start from the current cluster */
+                ofs -= fp->fptr;
+                clst = fp->clust;
+            } else {                                    /* When seek to back cluster, */
+                clst = fp->sclust;                      /* start from the first cluster */
+#if !_FS_READONLY
+                if (clst == 0) {                        /* If no cluster chain, create a new chain */
+                    clst = create_chain(fp->fs, 0);
+                    if (clst == 1) ABORT(fp->fs, FR_INT_ERR);
+                    if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+                    fp->sclust = clst;
+                }
+#endif
+                fp->clust = clst;
+            }
+            if (clst != 0) {
+                while (ofs > bcs) {                     /* Cluster following loop */
+#if !_FS_READONLY
+                    if (fp->flag & FA_WRITE) {          /* Check if in write mode or not */
+                        clst = create_chain(fp->fs, clst);  /* Force stretch if in write mode */
+                        if (clst == 0) {                /* When disk gets full, clip file size */
+                            ofs = bcs;
+                            break;
+                        }
+                    } else
+#endif
+                        clst = get_fat(fp->fs, clst);   /* Follow cluster chain if not in write mode */
+                    if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+                    if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR);
+                    fp->clust = clst;
+                    fp->fptr += bcs;
+                    ofs -= bcs;
+                }
+                fp->fptr += ofs;
+                if (ofs % SS(fp->fs)) {
+                    nsect = clust2sect(fp->fs, clst);   /* Current sector */
+                    if (!nsect) ABORT(fp->fs, FR_INT_ERR);
+                    nsect += ofs / SS(fp->fs);
+                }
+            }
+        }
+        if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) {  /* Fill sector cache if needed */
+#if !_FS_TINY
+#if !_FS_READONLY
+            if (fp->flag & FA__DIRTY) {         /* Write-back dirty sector cache */
+                if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+                    ABORT(fp->fs, FR_DISK_ERR);
+                fp->flag &= ~FA__DIRTY;
+            }
+#endif
+            if (disk_read(fp->fs->drv, fp->buf, nsect, 1) != RES_OK)    /* Fill sector cache */
+                ABORT(fp->fs, FR_DISK_ERR);
+#endif
+            fp->dsect = nsect;
+        }
+#if !_FS_READONLY
+        if (fp->fptr > fp->fsize) {         /* Set file change flag if the file size is extended */
+            fp->fsize = fp->fptr;
+            fp->flag |= FA__WRITTEN;
+        }
+#endif
+    }
+
+    LEAVE_FF(fp->fs, res);
+}
+
+
+
+#if _FS_MINIMIZE <= 1
+/*-----------------------------------------------------------------------*/
+/* Create a Directory Object                                             */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_opendir (
+    FATFS_DIR *dj,            /* Pointer to directory object to create */
+    const TCHAR *path   /* Pointer to the directory path */
+)
+{
+    FRESULT res;
+    FATFS *fs;
+    DEF_NAMEBUF;
+
+
+    if (!dj) return FR_INVALID_OBJECT;
+
+    res = chk_mounted(&path, &dj->fs, 0);
+    fs = dj->fs;
+    if (res == FR_OK) {
+        INIT_BUF(*dj);
+        res = follow_path(dj, path);            /* Follow the path to the directory */
+        FREE_BUF();
+        if (res == FR_OK) {                     /* Follow completed */
+            if (dj->dir) {                      /* It is not the root dir */
+                if (dj->dir[DIR_Attr] & AM_DIR) {   /* The object is a directory */
+                    dj->sclust = ld_clust(fs, dj->dir);
+                } else {                        /* The object is not a directory */
+                    res = FR_NO_PATH;
+                }
+            }
+            if (res == FR_OK) {
+                dj->id = fs->id;
+                res = dir_sdi(dj, 0);           /* Rewind dir */
+            }
+        }
+        if (res == FR_NO_FILE) res = FR_NO_PATH;
+        if (res != FR_OK) dj->fs = 0;           /* Invalidate the dir object if function faild */
+    } else {
+        dj->fs = 0;
+    }
+
+    LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entry in Sequence                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_readdir (
+    FATFS_DIR *dj,            /* Pointer to the open directory object */
+    FILINFO *fno        /* Pointer to file information to return */
+)
+{
+    FRESULT res;
+    DEF_NAMEBUF;
+
+
+    res = validate(dj);                     /* Check validity of the object */
+    if (res == FR_OK) {
+        if (!fno) {
+            res = dir_sdi(dj, 0);           /* Rewind the directory object */
+        } else {
+            INIT_BUF(*dj);
+            res = dir_read(dj);             /* Read an directory item */
+            if (res == FR_NO_FILE) {        /* Reached end of dir */
+                dj->sect = 0;
+                res = FR_OK;
+            }
+            if (res == FR_OK) {             /* A valid entry is found */
+                get_fileinfo(dj, fno);      /* Get the object information */
+                res = dir_next(dj, 0);      /* Increment index for next */
+                if (res == FR_NO_FILE) {
+                    dj->sect = 0;
+                    res = FR_OK;
+                }
+            }
+            FREE_BUF();
+        }
+    }
+
+    LEAVE_FF(dj->fs, res);
+}
+
+
+
+#if _FS_MINIMIZE == 0
+/*-----------------------------------------------------------------------*/
+/* Get File Status                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_stat (
+    const TCHAR *path,  /* Pointer to the file path */
+    FILINFO *fno        /* Pointer to file information to return */
+)
+{
+    FRESULT res;
+    FATFS_DIR dj;
+    DEF_NAMEBUF;
+
+
+    res = chk_mounted(&path, &dj.fs, 0);
+    if (res == FR_OK) {
+        INIT_BUF(dj);
+        res = follow_path(&dj, path);   /* Follow the file path */
+        if (res == FR_OK) {             /* Follow completed */
+            if (dj.dir)     /* Found an object */
+                get_fileinfo(&dj, fno);
+            else            /* It is root dir */
+                res = FR_INVALID_NAME;
+        }
+        FREE_BUF();
+    }
+
+    LEAVE_FF(dj.fs, res);
+}
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Get Number of Free Clusters                                           */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getfree (
+    const TCHAR *path,  /* Pointer to the logical drive number (root dir) */
+    DWORD *nclst,       /* Pointer to the variable to return number of free clusters */
+    FATFS **fatfs       /* Pointer to pointer to corresponding file system object to return */
+)
+{
+    FRESULT res;
+    FATFS *fs;
+    DWORD n, clst, sect, stat;
+    UINT i;
+    BYTE fat, *p;
+
+
+    /* Get drive number */
+    res = chk_mounted(&path, fatfs, 0);
+    fs = *fatfs;
+    if (res == FR_OK) {
+        /* If free_clust is valid, return it without full cluster scan */
+        if (fs->free_clust <= fs->n_fatent - 2) {
+            *nclst = fs->free_clust;
+        } else {
+            /* Get number of free clusters */
+            fat = fs->fs_type;
+            n = 0;
+            if (fat == FS_FAT12) {
+                clst = 2;
+                do {
+                    stat = get_fat(fs, clst);
+                    if (stat == 0xFFFFFFFF) {
+                        res = FR_DISK_ERR;
+                        break;
+                    }
+                    if (stat == 1) {
+                        res = FR_INT_ERR;
+                        break;
+                    }
+                    if (stat == 0) n++;
+                } while (++clst < fs->n_fatent);
+            } else {
+                clst = fs->n_fatent;
+                sect = fs->fatbase;
+                i = 0;
+                p = 0;
+                do {
+                    if (!i) {
+                        res = move_window(fs, sect++);
+                        if (res != FR_OK) break;
+                        p = fs->win;
+                        i = SS(fs);
+                    }
+                    if (fat == FS_FAT16) {
+                        if (LD_WORD(p) == 0) n++;
+                        p += 2;
+                        i -= 2;
+                    } else {
+                        if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++;
+                        p += 4;
+                        i -= 4;
+                    }
+                } while (--clst);
+            }
+            fs->free_clust = n;
+            if (fat == FS_FAT32) fs->fsi_flag = 1;
+            *nclst = n;
+        }
+    }
+    LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Truncate File                                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_truncate (
+    FIL *fp     /* Pointer to the file object */
+)
+{
+    FRESULT res;
+    DWORD ncl;
+
+
+    if (!fp) return FR_INVALID_OBJECT;
+
+    res = validate(fp);                     /* Check validity of the object */
+    if (res == FR_OK) {
+        if (fp->flag & FA__ERROR) {         /* Check abort flag */
+            res = FR_INT_ERR;
+        } else {
+            if (!(fp->flag & FA_WRITE))     /* Check access mode */
+                res = FR_DENIED;
+        }
+    }
+    if (res == FR_OK) {
+        if (fp->fsize > fp->fptr) {
+            fp->fsize = fp->fptr;   /* Set file size to current R/W point */
+            fp->flag |= FA__WRITTEN;
+            if (fp->fptr == 0) {    /* When set file size to zero, remove entire cluster chain */
+                res = remove_chain(fp->fs, fp->sclust);
+                fp->sclust = 0;
+            } else {                /* When truncate a part of the file, remove remaining clusters */
+                ncl = get_fat(fp->fs, fp->clust);
+                res = FR_OK;
+                if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR;
+                if (ncl == 1) res = FR_INT_ERR;
+                if (res == FR_OK && ncl < fp->fs->n_fatent) {
+                    res = put_fat(fp->fs, fp->clust, 0x0FFFFFFF);
+                    if (res == FR_OK) res = remove_chain(fp->fs, ncl);
+                }
+            }
+        }
+        if (res != FR_OK) fp->flag |= FA__ERROR;
+    }
+
+    LEAVE_FF(fp->fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Delete a File or Directory                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_unlink (
+    const TCHAR *path       /* Pointer to the file or directory path */
+)
+{
+    FRESULT res;
+    FATFS_DIR dj, sdj;
+    BYTE *dir;
+    DWORD dclst;
+    DEF_NAMEBUF;
+
+
+    res = chk_mounted(&path, &dj.fs, 1);
+    if (res == FR_OK) {
+        INIT_BUF(dj);
+        res = follow_path(&dj, path);       /* Follow the file path */
+        if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
+            res = FR_INVALID_NAME;          /* Cannot remove dot entry */
+#if _FS_LOCK
+        if (res == FR_OK) res = chk_lock(&dj, 2);   /* Cannot remove open file */
+#endif
+        if (res == FR_OK) {                 /* The object is accessible */
+            dir = dj.dir;
+            if (!dir) {
+                res = FR_INVALID_NAME;      /* Cannot remove the start directory */
+            } else {
+                if (dir[DIR_Attr] & AM_RDO)
+                    res = FR_DENIED;        /* Cannot remove R/O object */
+            }
+            dclst = ld_clust(dj.fs, dir);
+            if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */
+                if (dclst < 2) {
+                    res = FR_INT_ERR;
+                } else {
+                    mem_cpy(&sdj, &dj, sizeof (FATFS_DIR));   /* Check if the sub-dir is empty or not */
+                    sdj.sclust = dclst;
+                    res = dir_sdi(&sdj, 2);     /* Exclude dot entries */
+                    if (res == FR_OK) {
+                        res = dir_read(&sdj);
+                        if (res == FR_OK        /* Not empty dir */
+#if _FS_RPATH
+                                || dclst == dj.fs->cdir /* Current dir */
+#endif
+                           ) res = FR_DENIED;
+                        if (res == FR_NO_FILE) res = FR_OK; /* Empty */
+                    }
+                }
+            }
+            if (res == FR_OK) {
+                res = dir_remove(&dj);      /* Remove the directory entry */
+                if (res == FR_OK) {
+                    if (dclst)              /* Remove the cluster chain if exist */
+                        res = remove_chain(dj.fs, dclst);
+                    if (res == FR_OK) res = sync(dj.fs);
+                }
+            }
+        }
+        FREE_BUF();
+    }
+    LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directory                                                    */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mkdir (
+    const TCHAR *path       /* Pointer to the directory path */
+)
+{
+    FRESULT res;
+    FATFS_DIR dj;
+    BYTE *dir, n;
+    DWORD dsc, dcl, pcl, tim = get_fattime();
+    DEF_NAMEBUF;
+
+
+    res = chk_mounted(&path, &dj.fs, 1);
+    if (res == FR_OK) {
+        INIT_BUF(dj);
+        res = follow_path(&dj, path);           /* Follow the file path */
+        if (res == FR_OK) res = FR_EXIST;       /* Any object with same name is already existing */
+        if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT))
+            res = FR_INVALID_NAME;
+        if (res == FR_NO_FILE) {                /* Can create a new directory */
+            dcl = create_chain(dj.fs, 0);       /* Allocate a cluster for the new directory table */
+            res = FR_OK;
+            if (dcl == 0) res = FR_DENIED;      /* No space to allocate a new cluster */
+            if (dcl == 1) res = FR_INT_ERR;
+            if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
+            if (res == FR_OK)                   /* Flush FAT */
+                res = move_window(dj.fs, 0);
+            if (res == FR_OK) {                 /* Initialize the new directory table */
+                dsc = clust2sect(dj.fs, dcl);
+                dir = dj.fs->win;
+                mem_set(dir, 0, SS(dj.fs));
+                mem_set(dir+DIR_Name, ' ', 8+3);    /* Create "." entry */
+                dir[DIR_Name] = '.';
+                dir[DIR_Attr] = AM_DIR;
+                ST_DWORD(dir+DIR_WrtTime, tim);
+                st_clust(dir, dcl);
+                mem_cpy(dir+SZ_DIR, dir, SZ_DIR);   /* Create ".." entry */
+                dir[33] = '.';
+                pcl = dj.sclust;
+                if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase)
+                    pcl = 0;
+                st_clust(dir+SZ_DIR, pcl);
+                for (n = dj.fs->csize; n; n--) {    /* Write dot entries and clear following sectors */
+                    dj.fs->winsect = dsc++;
+                    dj.fs->wflag = 1;
+                    res = move_window(dj.fs, 0);
+                    if (res != FR_OK) break;
+                    mem_set(dir, 0, SS(dj.fs));
+                }
+            }
+            if (res == FR_OK) res = dir_register(&dj);  /* Register the object to the directoy */
+            if (res != FR_OK) {
+                remove_chain(dj.fs, dcl);           /* Could not register, remove cluster chain */
+            } else {
+                dir = dj.dir;
+                dir[DIR_Attr] = AM_DIR;             /* Attribute */
+                ST_DWORD(dir+DIR_WrtTime, tim);     /* Created time */
+                st_clust(dir, dcl);                 /* Table start cluster */
+                dj.fs->wflag = 1;
+                res = sync(dj.fs);
+            }
+        }
+        FREE_BUF();
+    }
+
+    LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change Attribute                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_chmod (
+    const TCHAR *path,  /* Pointer to the file path */
+    BYTE value,         /* Attribute bits */
+    BYTE mask           /* Attribute mask to change */
+)
+{
+    FRESULT res;
+    FATFS_DIR dj;
+    BYTE *dir;
+    DEF_NAMEBUF;
+
+
+    res = chk_mounted(&path, &dj.fs, 1);
+    if (res == FR_OK) {
+        INIT_BUF(dj);
+        res = follow_path(&dj, path);       /* Follow the file path */
+        FREE_BUF();
+        if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
+            res = FR_INVALID_NAME;
+        if (res == FR_OK) {
+            dir = dj.dir;
+            if (!dir) {                     /* Is it a root directory? */
+                res = FR_INVALID_NAME;
+            } else {                        /* File or sub directory */
+                mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC;    /* Valid attribute mask */
+                dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */
+                dj.fs->wflag = 1;
+                res = sync(dj.fs);
+            }
+        }
+    }
+
+    LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change Timestamp                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_utime (
+    const TCHAR *path,  /* Pointer to the file/directory name */
+    const FILINFO *fno  /* Pointer to the time stamp to be set */
+)
+{
+    FRESULT res;
+    FATFS_DIR dj;
+    BYTE *dir;
+    DEF_NAMEBUF;
+
+
+    res = chk_mounted(&path, &dj.fs, 1);
+    if (res == FR_OK) {
+        INIT_BUF(dj);
+        res = follow_path(&dj, path);   /* Follow the file path */
+        FREE_BUF();
+        if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
+            res = FR_INVALID_NAME;
+        if (res == FR_OK) {
+            dir = dj.dir;
+            if (!dir) {                 /* Root directory */
+                res = FR_INVALID_NAME;
+            } else {                    /* File or sub-directory */
+                ST_WORD(dir+DIR_WrtTime, fno->ftime);
+                ST_WORD(dir+DIR_WrtDate, fno->fdate);
+                dj.fs->wflag = 1;
+                res = sync(dj.fs);
+            }
+        }
+    }
+
+    LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Rename File/Directory                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_rename (
+    const TCHAR *path_old,  /* Pointer to the old name */
+    const TCHAR *path_new   /* Pointer to the new name */
+)
+{
+    FRESULT res;
+    FATFS_DIR djo, djn;
+    BYTE buf[21], *dir;
+    DWORD dw;
+    DEF_NAMEBUF;
+
+
+    res = chk_mounted(&path_old, &djo.fs, 1);
+    if (res == FR_OK) {
+        djn.fs = djo.fs;
+        INIT_BUF(djo);
+        res = follow_path(&djo, path_old);      /* Check old object */
+        if (_FS_RPATH && res == FR_OK && (djo.fn[NS] & NS_DOT))
+            res = FR_INVALID_NAME;
+#if _FS_LOCK
+        if (res == FR_OK) res = chk_lock(&djo, 2);
+#endif
+        if (res == FR_OK) {                     /* Old object is found */
+            if (!djo.dir) {                     /* Is root dir? */
+                res = FR_NO_FILE;
+            } else {
+                mem_cpy(buf, djo.dir+DIR_Attr, 21);     /* Save the object information except for name */
+                mem_cpy(&djn, &djo, sizeof (FATFS_DIR));      /* Check new object */
+                res = follow_path(&djn, path_new);
+                if (res == FR_OK) res = FR_EXIST;       /* The new object name is already existing */
+                if (res == FR_NO_FILE) {                /* Is it a valid path and no name collision? */
+                    /* Start critical section that an interruption or error can cause cross-link */
+                    res = dir_register(&djn);           /* Register the new entry */
+                    if (res == FR_OK) {
+                        dir = djn.dir;                  /* Copy object information except for name */
+                        mem_cpy(dir+13, buf+2, 19);
+                        dir[DIR_Attr] = buf[0] | AM_ARC;
+                        djo.fs->wflag = 1;
+                        if (djo.sclust != djn.sclust && (dir[DIR_Attr] & AM_DIR)) {     /* Update .. entry in the directory if needed */
+                            dw = clust2sect(djo.fs, ld_clust(djo.fs, dir));
+                            if (!dw) {
+                                res = FR_INT_ERR;
+                            } else {
+                                res = move_window(djo.fs, dw);
+                                dir = djo.fs->win+SZ_DIR;   /* .. entry */
+                                if (res == FR_OK && dir[1] == '.') {
+                                    dw = (djo.fs->fs_type == FS_FAT32 && djn.sclust == djo.fs->dirbase) ? 0 : djn.sclust;
+                                    st_clust(dir, dw);
+                                    djo.fs->wflag = 1;
+                                }
+                            }
+                        }
+                        if (res == FR_OK) {
+                            res = dir_remove(&djo);     /* Remove old entry */
+                            if (res == FR_OK)
+                                res = sync(djo.fs);
+                        }
+                    }
+                    /* End critical section */
+                }
+            }
+        }
+        FREE_BUF();
+    }
+    LEAVE_FF(djo.fs, res);
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _FS_MINIMIZE == 0 */
+#endif /* _FS_MINIMIZE <= 1 */
+#endif /* _FS_MINIMIZE <= 2 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Forward data to the stream directly (available on only tiny cfg)      */
+/*-----------------------------------------------------------------------*/
+#if _USE_FORWARD && _FS_TINY
+
+FRESULT f_forward (
+    FIL *fp,                        /* Pointer to the file object */
+    UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */
+    UINT btr,                       /* Number of bytes to forward */
+    UINT *bf                        /* Pointer to number of bytes forwarded */
+)
+{
+    FRESULT res;
+    DWORD remain, clst, sect;
+    UINT rcnt;
+    BYTE csect;
+
+
+    *bf = 0;    /* Clear transfer byte counter */
+
+    if (!fp) return FR_INVALID_OBJECT;
+
+    res = validate(fp);                             /* Check validity of the object */
+    if (res != FR_OK) LEAVE_FF(fp->fs, res);
+    if (fp->flag & FA__ERROR)                       /* Check error flag */
+        LEAVE_FF(fp->fs, FR_INT_ERR);
+    if (!(fp->flag & FA_READ))                      /* Check access mode */
+        LEAVE_FF(fp->fs, FR_DENIED);
+
+    remain = fp->fsize - fp->fptr;
+    if (btr > remain) btr = (UINT)remain;           /* Truncate btr by remaining bytes */
+
+    for ( ;  btr && (*func)(0, 0);                  /* Repeat until all data transferred or stream becomes busy */
+            fp->fptr += rcnt, *bf += rcnt, btr -= rcnt) {
+        csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1));    /* Sector offset in the cluster */
+        if ((fp->fptr % SS(fp->fs)) == 0) {         /* On the sector boundary? */
+            if (!csect) {                           /* On the cluster boundary? */
+                clst = (fp->fptr == 0) ?            /* On the top of the file? */
+                       fp->sclust : get_fat(fp->fs, fp->clust);
+                if (clst <= 1) ABORT(fp->fs, FR_INT_ERR);
+                if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+                fp->clust = clst;                   /* Update current cluster */
+            }
+        }
+        sect = clust2sect(fp->fs, fp->clust);       /* Get current data sector */
+        if (!sect) ABORT(fp->fs, FR_INT_ERR);
+        sect += csect;
+        if (move_window(fp->fs, sect))              /* Move sector window */
+            ABORT(fp->fs, FR_DISK_ERR);
+        fp->dsect = sect;
+        rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs));  /* Forward data from sector window */
+        if (rcnt > btr) rcnt = btr;
+        rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt);
+        if (!rcnt) ABORT(fp->fs, FR_INT_ERR);
+    }
+
+    LEAVE_FF(fp->fs, FR_OK);
+}
+#endif /* _USE_FORWARD */
+
+
+
+#if _USE_MKFS && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Create File System on the Drive                                       */
+/*-----------------------------------------------------------------------*/
+#define N_ROOTDIR   512     /* Number of root dir entries for FAT12/16 */
+#define N_FATS      1       /* Number of FAT copies (1 or 2) */
+
+
+FRESULT f_mkfs (
+    BYTE drv,       /* Logical drive number */
+    BYTE sfd,       /* Partitioning rule 0:FDISK, 1:SFD */
+    UINT au         /* Allocation unit size [bytes] */
+)
+{
+    static const WORD vst[] = { 1024,   512,  256,  128,   64,    32,   16,    8,    4,    2,   0};
+    static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512};
+    BYTE fmt, md, sys, *tbl, pdrv, part;
+    DWORD n_clst, vs, n, wsect;
+    UINT i;
+    DWORD b_vol, b_fat, b_dir, b_data;  /* LBA */
+    DWORD n_vol, n_rsv, n_fat, n_dir;   /* Size */
+    FATFS *fs;
+    DSTATUS stat;
+
+
+    /* Check mounted drive and clear work area */
+    if (drv >= _VOLUMES) return FR_INVALID_DRIVE;
+    if (sfd > 1) return FR_INVALID_PARAMETER;
+    if (au & (au - 1)) return FR_INVALID_PARAMETER;
+    fs = FatFs[drv];
+    if (!fs) return FR_NOT_ENABLED;
+    fs->fs_type = 0;
+    pdrv = LD2PD(drv);  /* Physical drive */
+    part = LD2PT(drv);  /* Partition (0:auto detect, 1-4:get from partition table)*/
+
+    /* Get disk statics */
+    stat = disk_initialize(pdrv);
+    if (stat & STA_NOINIT) return FR_NOT_READY;
+    if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+#if _MAX_SS != 512                  /* Get disk sector size */
+    if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > _MAX_SS)
+        return FR_DISK_ERR;
+#endif
+    if (_MULTI_PARTITION && part) {
+        /* Get partition information from partition table in the MBR */
+        if (disk_read(pdrv, fs->win, 0, 1) != RES_OK) return FR_DISK_ERR;
+        if (LD_WORD(fs->win+BS_55AA) != 0xAA55) return FR_MKFS_ABORTED;
+        tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE];
+        if (!tbl[4]) return FR_MKFS_ABORTED;    /* No partition? */
+        b_vol = LD_DWORD(tbl+8);    /* Volume start sector */
+        n_vol = LD_DWORD(tbl+12);   /* Volume size */
+    } else {
+        /* Create a partition in this function */
+        if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &n_vol) != RES_OK || n_vol < 128)
+            return FR_DISK_ERR;
+        b_vol = (sfd) ? 0 : 63;     /* Volume start sector */
+        n_vol -= b_vol;             /* Volume size */
+    }
+
+    if (!au) {              /* AU auto selection */
+        vs = n_vol / (2000 / (SS(fs) / 512));
+        for (i = 0; vs < vst[i]; i++) ;
+        au = cst[i];
+    }
+    au /= SS(fs);       /* Number of sectors per cluster */
+    if (au == 0) au = 1;
+    if (au > 128) au = 128;
+
+    /* Pre-compute number of clusters and FAT sub-type */
+    n_clst = n_vol / au;
+    fmt = FS_FAT12;
+    if (n_clst >= MIN_FAT16) fmt = FS_FAT16;
+    if (n_clst >= MIN_FAT32) fmt = FS_FAT32;
+
+    /* Determine offset and size of FAT structure */
+    if (fmt == FS_FAT32) {
+        n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs);
+        n_rsv = 32;
+        n_dir = 0;
+    } else {
+        n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4;
+        n_fat = (n_fat + SS(fs) - 1) / SS(fs);
+        n_rsv = 1;
+        n_dir = (DWORD)N_ROOTDIR * SZ_DIR / SS(fs);
+    }
+    b_fat = b_vol + n_rsv;              /* FAT area start sector */
+    b_dir = b_fat + n_fat * N_FATS;     /* Directory area start sector */
+    b_data = b_dir + n_dir;             /* Data area start sector */
+    if (n_vol < b_data + au - b_vol) return FR_MKFS_ABORTED;    /* Too small volume */
+
+    /* Align data start sector to erase block boundary (for flash memory media) */
+    if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &n) != RES_OK || !n || n > 32768) n = 1;
+    n = (b_data + n - 1) & ~(n - 1);    /* Next nearest erase block from current data start */
+    n = (n - b_data) / N_FATS;
+    if (fmt == FS_FAT32) {      /* FAT32: Move FAT offset */
+        n_rsv += n;
+        b_fat += n;
+    } else {                    /* FAT12/16: Expand FAT size */
+        n_fat += n;
+    }
+
+    /* Determine number of clusters and final check of validity of the FAT sub-type */
+    n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au;
+    if (   (fmt == FS_FAT16 && n_clst < MIN_FAT16)
+            || (fmt == FS_FAT32 && n_clst < MIN_FAT32))
+        return FR_MKFS_ABORTED;
+
+    switch (fmt) {  /* Determine system ID for partition table */
+        case FS_FAT12:
+            sys = 0x01;
+            break;
+        case FS_FAT16:
+            sys = (n_vol < 0x10000) ? 0x04 : 0x06;
+            break;
+        default:
+            sys = 0x0C;
+    }
+
+    if (_MULTI_PARTITION && part) {
+        /* Update system ID in the partition table */
+        tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE];
+        tbl[4] = sys;
+        if (disk_write(pdrv, fs->win, 0, 1) != RES_OK) return FR_DISK_ERR;
+        md = 0xF8;
+    } else {
+        if (sfd) {  /* No partition table (SFD) */
+            md = 0xF0;
+        } else {    /* Create partition table (FDISK) */
+            mem_set(fs->win, 0, SS(fs));
+            tbl = fs->win+MBR_Table;    /* Create partition table for single partition in the drive */
+            tbl[1] = 1;                     /* Partition start head */
+            tbl[2] = 1;                     /* Partition start sector */
+            tbl[3] = 0;                     /* Partition start cylinder */
+            tbl[4] = sys;                   /* System type */
+            tbl[5] = 254;                   /* Partition end head */
+            n = (b_vol + n_vol) / 63 / 255;
+            tbl[6] = (BYTE)((n >> 2) | 63); /* Partition end sector */
+            tbl[7] = (BYTE)n;               /* End cylinder */
+            ST_DWORD(tbl+8, 63);            /* Partition start in LBA */
+            ST_DWORD(tbl+12, n_vol);        /* Partition size in LBA */
+            ST_WORD(fs->win+BS_55AA, 0xAA55);   /* MBR signature */
+            if (disk_write(pdrv, fs->win, 0, 1) != RES_OK)  /* Write it to the MBR sector */
+                return FR_DISK_ERR;
+            md = 0xF8;
+        }
+    }
+
+    /* Create BPB in the VBR */
+    tbl = fs->win;                          /* Clear sector */
+    mem_set(tbl, 0, SS(fs));
+    mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code, OEM name */
+    i = SS(fs);                             /* Sector size */
+    ST_WORD(tbl+BPB_BytsPerSec, i);
+    tbl[BPB_SecPerClus] = (BYTE)au;         /* Sectors per cluster */
+    ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv);     /* Reserved sectors */
+    tbl[BPB_NumFATs] = N_FATS;              /* Number of FATs */
+    i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR;  /* Number of rootdir entries */
+    ST_WORD(tbl+BPB_RootEntCnt, i);
+    if (n_vol < 0x10000) {                  /* Number of total sectors */
+        ST_WORD(tbl+BPB_TotSec16, n_vol);
+    } else {
+        ST_DWORD(tbl+BPB_TotSec32, n_vol);
+    }
+    tbl[BPB_Media] = md;                    /* Media descriptor */
+    ST_WORD(tbl+BPB_SecPerTrk, 63);         /* Number of sectors per track */
+    ST_WORD(tbl+BPB_NumHeads, 255);         /* Number of heads */
+    ST_DWORD(tbl+BPB_HiddSec, b_vol);       /* Hidden sectors */
+    n = get_fattime();                      /* Use current time as VSN */
+    if (fmt == FS_FAT32) {
+        ST_DWORD(tbl+BS_VolID32, n);        /* VSN */
+        ST_DWORD(tbl+BPB_FATSz32, n_fat);   /* Number of sectors per FAT */
+        ST_DWORD(tbl+BPB_RootClus, 2);      /* Root directory start cluster (2) */
+        ST_WORD(tbl+BPB_FSInfo, 1);         /* FSInfo record offset (VBR+1) */
+        ST_WORD(tbl+BPB_BkBootSec, 6);      /* Backup boot record offset (VBR+6) */
+        tbl[BS_DrvNum32] = 0x80;            /* Drive number */
+        tbl[BS_BootSig32] = 0x29;           /* Extended boot signature */
+        mem_cpy(tbl+BS_VolLab32, "NO NAME    " "FAT32   ", 19); /* Volume label, FAT signature */
+    } else {
+        ST_DWORD(tbl+BS_VolID, n);          /* VSN */
+        ST_WORD(tbl+BPB_FATSz16, n_fat);    /* Number of sectors per FAT */
+        tbl[BS_DrvNum] = 0x80;              /* Drive number */
+        tbl[BS_BootSig] = 0x29;             /* Extended boot signature */
+        mem_cpy(tbl+BS_VolLab, "NO NAME    " "FAT     ", 19);   /* Volume label, FAT signature */
+    }
+    ST_WORD(tbl+BS_55AA, 0xAA55);           /* Signature (Offset is fixed here regardless of sector size) */
+    if (disk_write(pdrv, tbl, b_vol, 1) != RES_OK)  /* Write it to the VBR sector */
+        return FR_DISK_ERR;
+    if (fmt == FS_FAT32)                            /* Write backup VBR if needed (VBR+6) */
+        disk_write(pdrv, tbl, b_vol + 6, 1);
+
+    /* Initialize FAT area */
+    wsect = b_fat;
+    for (i = 0; i < N_FATS; i++) {      /* Initialize each FAT copy */
+        mem_set(tbl, 0, SS(fs));            /* 1st sector of the FAT  */
+        n = md;                             /* Media descriptor byte */
+        if (fmt != FS_FAT32) {
+            n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00;
+            ST_DWORD(tbl+0, n);             /* Reserve cluster #0-1 (FAT12/16) */
+        } else {
+            n |= 0xFFFFFF00;
+            ST_DWORD(tbl+0, n);             /* Reserve cluster #0-1 (FAT32) */
+            ST_DWORD(tbl+4, 0xFFFFFFFF);
+            ST_DWORD(tbl+8, 0x0FFFFFFF);    /* Reserve cluster #2 for root dir */
+        }
+        if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
+            return FR_DISK_ERR;
+        mem_set(tbl, 0, SS(fs));            /* Fill following FAT entries with zero */
+        for (n = 1; n < n_fat; n++) {       /* This loop may take a time on FAT32 volume due to many single sector writes */
+            if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
+                return FR_DISK_ERR;
+        }
+    }
+
+    /* Initialize root directory */
+    i = (fmt == FS_FAT32) ? au : n_dir;
+    do {
+        if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
+            return FR_DISK_ERR;
+    } while (--i);
+
+#if _USE_ERASE  /* Erase data area if needed */
+    {
+        DWORD eb[2];
+
+        eb[0] = wsect;
+        eb[1] = wsect + (n_clst - ((fmt == FS_FAT32) ? 1 : 0)) * au - 1;
+        disk_ioctl(pdrv, CTRL_ERASE_SECTOR, eb);
+    }
+#endif
+
+    /* Create FSInfo if needed */
+    if (fmt == FS_FAT32) {
+        ST_DWORD(tbl+FSI_LeadSig, 0x41615252);
+        ST_DWORD(tbl+FSI_StrucSig, 0x61417272);
+        ST_DWORD(tbl+FSI_Free_Count, n_clst - 1);   /* Number of free clusters */
+        ST_DWORD(tbl+FSI_Nxt_Free, 2);              /* Last allocated cluster# */
+        ST_WORD(tbl+BS_55AA, 0xAA55);
+        disk_write(pdrv, tbl, b_vol + 1, 1);    /* Write original (VBR+1) */
+        disk_write(pdrv, tbl, b_vol + 7, 1);    /* Write backup (VBR+7) */
+    }
+
+    return (disk_ioctl(pdrv, CTRL_SYNC, 0) == RES_OK) ? FR_OK : FR_DISK_ERR;
+}
+
+
+#if _MULTI_PARTITION == 2
+/*-----------------------------------------------------------------------*/
+/* Divide Physical Drive                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_fdisk (
+    BYTE pdrv,          /* Physical drive number */
+    const DWORD szt[],  /* Pointer to the size table for each partitions */
+    void* work          /* Pointer to the working buffer */
+)
+{
+    UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl;
+    BYTE s_hd, e_hd, *p, *buf = (BYTE*)work;
+    DSTATUS stat;
+    DWORD sz_disk, sz_part, s_part;
+
+
+    stat = disk_initialize(pdrv);
+    if (stat & STA_NOINIT) return FR_NOT_READY;
+    if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+    if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR;
+
+    /* Determine CHS in the table regardless of the drive geometry */
+    for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ;
+    if (n == 256) n--;
+    e_hd = n - 1;
+    sz_cyl = 63 * n;
+    tot_cyl = sz_disk / sz_cyl;
+
+    /* Create partition table */
+    mem_set(buf, 0, _MAX_SS);
+    p = buf + MBR_Table;
+    b_cyl = 0;
+    for (i = 0; i < 4; i++, p += SZ_PTE) {
+        p_cyl = (szt[i] <= 100) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl;
+        if (!p_cyl) continue;
+        s_part = (DWORD)sz_cyl * b_cyl;
+        sz_part = (DWORD)sz_cyl * p_cyl;
+        if (i == 0) {   /* Exclude first track of cylinder 0 */
+            s_hd = 1;
+            s_part += 63;
+            sz_part -= 63;
+        } else {
+            s_hd = 0;
+        }
+        e_cyl = b_cyl + p_cyl - 1;
+        if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER;
+
+        /* Set partition table */
+        p[1] = s_hd;                        /* Start head */
+        p[2] = (BYTE)((b_cyl >> 2) + 1);    /* Start sector */
+        p[3] = (BYTE)b_cyl;                 /* Start cylinder */
+        p[4] = 0x06;                        /* System type (temporary setting) */
+        p[5] = e_hd;                        /* End head */
+        p[6] = (BYTE)((e_cyl >> 2) + 63);   /* End sector */
+        p[7] = (BYTE)e_cyl;                 /* End cylinder */
+        ST_DWORD(p + 8, s_part);            /* Start sector in LBA */
+        ST_DWORD(p + 12, sz_part);          /* Partition size */
+
+        /* Next partition */
+        b_cyl += p_cyl;
+    }
+    ST_WORD(p, 0xAA55);
+
+    /* Write it to the MBR */
+    return (disk_write(pdrv, buf, 0, 1) || disk_ioctl(pdrv, CTRL_SYNC, 0)) ? FR_DISK_ERR : FR_OK;
+}
+
+
+#endif /* _MULTI_PARTITION == 2 */
+#endif /* _USE_MKFS && !_FS_READONLY */
+
+
+
+
+#if _USE_STRFUNC
+/*-----------------------------------------------------------------------*/
+/* Get a string from the file                                            */
+/*-----------------------------------------------------------------------*/
+TCHAR* f_gets (
+    TCHAR* buff,    /* Pointer to the string buffer to read */
+    int len,        /* Size of string buffer (characters) */
+    FIL* fil        /* Pointer to the file object */
+)
+{
+    int n = 0;
+    TCHAR c, *p = buff;
+    BYTE s[2];
+    UINT rc;
+
+
+    while (n < len - 1) {           /* Read bytes until buffer gets filled */
+        f_read(fil, s, 1, &rc);
+        if (rc != 1) break;         /* Break on EOF or error */
+        c = s[0];
+#if _LFN_UNICODE                    /* Read a character in UTF-8 encoding */
+        if (c >= 0x80) {
+            if (c < 0xC0) continue; /* Skip stray trailer */
+            if (c < 0xE0) {         /* Two-byte sequence */
+                f_read(fil, s, 1, &rc);
+                if (rc != 1) break;
+                c = ((c & 0x1F) << 6) | (s[0] & 0x3F);
+                if (c < 0x80) c = '?';
+            } else {
+                if (c < 0xF0) {     /* Three-byte sequence */
+                    f_read(fil, s, 2, &rc);
+                    if (rc != 2) break;
+                    c = (c << 12) | ((s[0] & 0x3F) << 6) | (s[1] & 0x3F);
+                    if (c < 0x800) c = '?';
+                } else {            /* Reject four-byte sequence */
+                    c = '?';
+                }
+            }
+        }
+#endif
+#if _USE_STRFUNC >= 2
+        if (c == '\r') continue;    /* Strip '\r' */
+#endif
+        *p++ = c;
+        n++;
+        if (c == '\n') break;       /* Break on EOL */
+    }
+    *p = 0;
+    return n ? buff : 0;            /* When no data read (eof or error), return with error. */
+}
+
+
+
+#if !_FS_READONLY
+#include <stdarg.h>
+/*-----------------------------------------------------------------------*/
+/* Put a character to the file                                           */
+/*-----------------------------------------------------------------------*/
+int f_putc (
+    TCHAR c,    /* A character to be output */
+    FIL* fil    /* Pointer to the file object */
+)
+{
+    UINT bw, btw;
+    BYTE s[3];
+
+
+#if _USE_STRFUNC >= 2
+    if (c == '\n') f_putc ('\r', fil);  /* LF -> CRLF conversion */
+#endif
+
+#if _LFN_UNICODE    /* Write the character in UTF-8 encoding */
+    if (c < 0x80) {         /* 7-bit */
+        s[0] = (BYTE)c;
+        btw = 1;
+    } else {
+        if (c < 0x800) {    /* 11-bit */
+            s[0] = (BYTE)(0xC0 | (c >> 6));
+            s[1] = (BYTE)(0x80 | (c & 0x3F));
+            btw = 2;
+        } else {            /* 16-bit */
+            s[0] = (BYTE)(0xE0 | (c >> 12));
+            s[1] = (BYTE)(0x80 | ((c >> 6) & 0x3F));
+            s[2] = (BYTE)(0x80 | (c & 0x3F));
+            btw = 3;
+        }
+    }
+#else               /* Write the character without conversion */
+    s[0] = (BYTE)c;
+    btw = 1;
+#endif
+    f_write(fil, s, btw, &bw);      /* Write the char to the file */
+    return (bw == btw) ? 1 : EOF;   /* Return the result */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a string to the file                                              */
+/*-----------------------------------------------------------------------*/
+int f_puts (
+    const TCHAR* str,   /* Pointer to the string to be output */
+    FIL* fil            /* Pointer to the file object */
+)
+{
+    int n;
+
+
+    for (n = 0; *str; str++, n++) {
+        if (f_putc(*str, fil) == EOF) return EOF;
+    }
+    return n;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a formatted string to the file                                    */
+/*-----------------------------------------------------------------------*/
+int f_printf (
+    FIL* fil,           /* Pointer to the file object */
+    const TCHAR* str,   /* Pointer to the format string */
+    ...                 /* Optional arguments... */
+)
+{
+    va_list arp;
+    BYTE f, r;
+    UINT i, j, w;
+    ULONG v;
+    TCHAR c, d, s[16], *p;
+    int res, chc, cc;
+
+
+    va_start(arp, str);
+
+    for (cc = res = 0; cc != EOF; res += cc) {
+        c = *str++;
+        if (c == 0) break;          /* End of string */
+        if (c != '%') {             /* Non escape character */
+            cc = f_putc(c, fil);
+            if (cc != EOF) cc = 1;
+            continue;
+        }
+        w = f = 0;
+        c = *str++;
+        if (c == '0') {             /* Flag: '0' padding */
+            f = 1;
+            c = *str++;
+        } else {
+            if (c == '-') {         /* Flag: left justified */
+                f = 2;
+                c = *str++;
+            }
+        }
+        while (IsDigit(c)) {        /* Precision */
+            w = w * 10 + c - '0';
+            c = *str++;
+        }
+        if (c == 'l' || c == 'L') { /* Prefix: Size is long int */
+            f |= 4;
+            c = *str++;
+        }
+        if (!c) break;
+        d = c;
+        if (IsLower(d)) d -= 0x20;
+        switch (d) {                /* Type is... */
+            case 'S' :                  /* String */
+                p = va_arg(arp, TCHAR*);
+                for (j = 0; p[j]; j++) ;
+                chc = 0;
+                if (!(f & 2)) {
+                    while (j++ < w) chc += (cc = f_putc(' ', fil));
+                }
+                chc += (cc = f_puts(p, fil));
+                while (j++ < w) chc += (cc = f_putc(' ', fil));
+                if (cc != EOF) cc = chc;
+                continue;
+            case 'C' :                  /* Character */
+                cc = f_putc((TCHAR)va_arg(arp, int), fil);
+                continue;
+            case 'B' :                  /* Binary */
+                r = 2;
+                break;
+            case 'O' :                  /* Octal */
+                r = 8;
+                break;
+            case 'D' :                  /* Signed decimal */
+            case 'U' :                  /* Unsigned decimal */
+                r = 10;
+                break;
+            case 'X' :                  /* Hexdecimal */
+                r = 16;
+                break;
+            default:                    /* Unknown type (pass-through) */
+                cc = f_putc(c, fil);
+                continue;
+        }
+
+        /* Get an argument and put it in numeral */
+        v = (f & 4) ? (ULONG)va_arg(arp, long) : ((d == 'D') ? (ULONG)(long)va_arg(arp, int) : (ULONG)va_arg(arp, unsigned int));
+        if (d == 'D' && (v & 0x80000000)) {
+            v = 0 - v;
+            f |= 8;
+        }
+        i = 0;
+        do {
+            d = (TCHAR)(v % r);
+            v /= r;
+            if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
+            s[i++] = d + '0';
+        } while (v && i < sizeof s / sizeof s[0]);
+        if (f & 8) s[i++] = '-';
+        j = i;
+        d = (f & 1) ? '0' : ' ';
+        res = 0;
+        while (!(f & 2) && j++ < w) res += (cc = f_putc(d, fil));
+        do res += (cc = f_putc(s[--i], fil));
+        while(i);
+        while (j++ < w) res += (cc = f_putc(' ', fil));
+        if (cc != EOF) cc = res;
+    }
+
+    va_end(arp);
+    return (cc == EOF) ? cc : res;
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _USE_STRFUNC */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/SDFileSystem/FATFileSystem/ChaN/ff.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,338 @@
+/*---------------------------------------------------------------------------/
+/  FatFs - FAT file system module include file  R0.09a    (C)ChaN, 2012
+/----------------------------------------------------------------------------/
+/ FatFs module is a generic FAT file system module for small embedded systems.
+/ This is a free software that opened for education, research and commercial
+/ developments under license policy of following terms.
+/
+/  Copyright (C) 2012, ChaN, all right reserved.
+/
+/ * The FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/----------------------------------------------------------------------------*/
+
+#ifndef _FATFS
+#define _FATFS  4004    /* Revision ID */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "integer.h"    /* Basic integer types */
+#include "ffconf.h"     /* FatFs configuration options */
+
+#if _FATFS != _FFCONF
+#error Wrong configuration file (ffconf.h).
+#endif
+
+
+
+/* Definitions of volume management */
+
+#if _MULTI_PARTITION        /* Multiple partition configuration */
+typedef struct {
+    BYTE pd;    /* Physical drive number */
+    BYTE pt;    /* Partition: 0:Auto detect, 1-4:Forced partition) */
+} PARTITION;
+extern PARTITION VolToPart[];   /* Volume - Partition resolution table */
+#define LD2PD(vol) (VolToPart[vol].pd)  /* Get physical drive number */
+#define LD2PT(vol) (VolToPart[vol].pt)  /* Get partition index */
+
+#else                           /* Single partition configuration */
+#define LD2PD(vol) (BYTE)(vol)  /* Each logical drive is bound to the same physical drive number */
+#define LD2PT(vol) 0            /* Always mounts the 1st partition or in SFD */
+
+#endif
+
+
+
+/* Type of path name strings on FatFs API */
+
+#if _LFN_UNICODE            /* Unicode string */
+#if !_USE_LFN
+#error _LFN_UNICODE must be 0 in non-LFN cfg.
+#endif
+#ifndef _INC_TCHAR
+typedef WCHAR TCHAR;
+#define _T(x) L ## x
+#define _TEXT(x) L ## x
+#endif
+
+#else                       /* ANSI/OEM string */
+#ifndef _INC_TCHAR
+typedef char TCHAR;
+#define _T(x) x
+#define _TEXT(x) x
+#endif
+
+#endif
+
+
+
+/* File system object structure (FATFS) */
+
+typedef struct {
+    BYTE    fs_type;        /* FAT sub-type (0:Not mounted) */
+    BYTE    drv;            /* Physical drive number */
+    BYTE    csize;          /* Sectors per cluster (1,2,4...128) */
+    BYTE    n_fats;         /* Number of FAT copies (1,2) */
+    BYTE    wflag;          /* win[] dirty flag (1:must be written back) */
+    BYTE    fsi_flag;       /* fsinfo dirty flag (1:must be written back) */
+    WORD    id;             /* File system mount ID */
+    WORD    n_rootdir;      /* Number of root directory entries (FAT12/16) */
+#if _MAX_SS != 512
+    WORD    ssize;          /* Bytes per sector (512, 1024, 2048 or 4096) */
+#endif
+#if _FS_REENTRANT
+    _SYNC_t sobj;           /* Identifier of sync object */
+#endif
+#if !_FS_READONLY
+    DWORD   last_clust;     /* Last allocated cluster */
+    DWORD   free_clust;     /* Number of free clusters */
+    DWORD   fsi_sector;     /* fsinfo sector (FAT32) */
+#endif
+#if _FS_RPATH
+    DWORD   cdir;           /* Current directory start cluster (0:root) */
+#endif
+    DWORD   n_fatent;       /* Number of FAT entries (= number of clusters + 2) */
+    DWORD   fsize;          /* Sectors per FAT */
+    DWORD   fatbase;        /* FAT start sector */
+    DWORD   dirbase;        /* Root directory start sector (FAT32:Cluster#) */
+    DWORD   database;       /* Data start sector */
+    DWORD   winsect;        /* Current sector appearing in the win[] */
+    BYTE    win[_MAX_SS];   /* Disk access window for Directory, FAT (and Data on tiny cfg) */
+} FATFS;
+
+
+
+/* File object structure (FIL) */
+
+typedef struct {
+    FATFS*  fs;             /* Pointer to the related file system object */
+    WORD    id;             /* File system mount ID of the related file system object */
+    BYTE    flag;           /* File status flags */
+    BYTE    pad1;
+    DWORD   fptr;           /* File read/write pointer (0ed on file open) */
+    DWORD   fsize;          /* File size */
+    DWORD   sclust;         /* File data start cluster (0:no data cluster, always 0 when fsize is 0) */
+    DWORD   clust;          /* Current cluster of fpter */
+    DWORD   dsect;          /* Current data sector of fpter */
+#if !_FS_READONLY
+    DWORD   dir_sect;       /* Sector containing the directory entry */
+    BYTE*   dir_ptr;        /* Pointer to the directory entry in the window */
+#endif
+#if _USE_FASTSEEK
+    DWORD*  cltbl;          /* Pointer to the cluster link map table (null on file open) */
+#endif
+#if _FS_LOCK
+    UINT    lockid;         /* File lock ID (index of file semaphore table Files[]) */
+#endif
+#if !_FS_TINY
+    BYTE    buf[_MAX_SS];   /* File data read/write buffer */
+#endif
+} FIL;
+
+
+
+/* Directory object structure (DIR) */
+
+typedef struct {
+    FATFS*  fs;             /* Pointer to the owner file system object */
+    WORD    id;             /* Owner file system mount ID */
+    WORD    index;          /* Current read/write index number */
+    DWORD   sclust;         /* Table start cluster (0:Root dir) */
+    DWORD   clust;          /* Current cluster */
+    DWORD   sect;           /* Current sector */
+    BYTE*   dir;            /* Pointer to the current SFN entry in the win[] */
+    BYTE*   fn;             /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
+#if _USE_LFN
+    WCHAR*  lfn;            /* Pointer to the LFN working buffer */
+    WORD    lfn_idx;        /* Last matched LFN index number (0xFFFF:No LFN) */
+#endif
+} FATFS_DIR;
+
+
+
+/* File status structure (FILINFO) */
+
+typedef struct {
+    DWORD   fsize;          /* File size */
+    WORD    fdate;          /* Last modified date */
+    WORD    ftime;          /* Last modified time */
+    BYTE    fattrib;        /* Attribute */
+    TCHAR   fname[13];      /* Short file name (8.3 format) */
+#if _USE_LFN
+    TCHAR*  lfname;         /* Pointer to the LFN buffer */
+    UINT    lfsize;         /* Size of LFN buffer in TCHAR */
+#endif
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+    FR_OK = 0,              /* (0) Succeeded */
+    FR_DISK_ERR,            /* (1) A hard error occurred in the low level disk I/O layer */
+    FR_INT_ERR,             /* (2) Assertion failed */
+    FR_NOT_READY,           /* (3) The physical drive cannot work */
+    FR_NO_FILE,             /* (4) Could not find the file */
+    FR_NO_PATH,             /* (5) Could not find the path */
+    FR_INVALID_NAME,        /* (6) The path name format is invalid */
+    FR_DENIED,              /* (7) Access denied due to prohibited access or directory full */
+    FR_EXIST,               /* (8) Access denied due to prohibited access */
+    FR_INVALID_OBJECT,      /* (9) The file/directory object is invalid */
+    FR_WRITE_PROTECTED,     /* (10) The physical drive is write protected */
+    FR_INVALID_DRIVE,       /* (11) The logical drive number is invalid */
+    FR_NOT_ENABLED,         /* (12) The volume has no work area */
+    FR_NO_FILESYSTEM,       /* (13) There is no valid FAT volume */
+    FR_MKFS_ABORTED,        /* (14) The f_mkfs() aborted due to any parameter error */
+    FR_TIMEOUT,             /* (15) Could not get a grant to access the volume within defined period */
+    FR_LOCKED,              /* (16) The operation is rejected according to the file sharing policy */
+    FR_NOT_ENOUGH_CORE,     /* (17) LFN working buffer could not be allocated */
+    FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > _FS_SHARE */
+    FR_INVALID_PARAMETER    /* (19) Given parameter is invalid */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* FatFs module application interface                           */
+
+FRESULT f_mount (BYTE, FATFS*);                     /* Mount/Unmount a logical drive */
+FRESULT f_open (FIL*, const TCHAR*, BYTE);          /* Open or create a file */
+FRESULT f_read (FIL*, void*, UINT, UINT*);          /* Read data from a file */
+FRESULT f_lseek (FIL*, DWORD);                      /* Move file pointer of a file object */
+FRESULT f_close (FIL*);                             /* Close an open file object */
+FRESULT f_opendir (FATFS_DIR*, const TCHAR*);             /* Open an existing directory */
+FRESULT f_readdir (FATFS_DIR*, FILINFO*);                 /* Read a directory item */
+FRESULT f_stat (const TCHAR*, FILINFO*);            /* Get file status */
+FRESULT f_write (FIL*, const void*, UINT, UINT*);   /* Write data to a file */
+FRESULT f_getfree (const TCHAR*, DWORD*, FATFS**);  /* Get number of free clusters on the drive */
+FRESULT f_truncate (FIL*);                          /* Truncate file */
+FRESULT f_sync (FIL*);                              /* Flush cached data of a writing file */
+FRESULT f_unlink (const TCHAR*);                    /* Delete an existing file or directory */
+FRESULT f_mkdir (const TCHAR*);                     /* Create a new directory */
+FRESULT f_chmod (const TCHAR*, BYTE, BYTE);         /* Change attribute of the file/dir */
+FRESULT f_utime (const TCHAR*, const FILINFO*);     /* Change times-tamp of the file/dir */
+FRESULT f_rename (const TCHAR*, const TCHAR*);      /* Rename/Move a file or directory */
+FRESULT f_chdrive (BYTE);                           /* Change current drive */
+FRESULT f_chdir (const TCHAR*);                     /* Change current directory */
+FRESULT f_getcwd (TCHAR*, UINT);                    /* Get current directory */
+FRESULT f_forward (FIL*, UINT(*)(const BYTE*,UINT), UINT, UINT*);   /* Forward data to the stream */
+FRESULT f_mkfs (BYTE, BYTE, UINT);                  /* Create a file system on the drive */
+FRESULT f_fdisk (BYTE, const DWORD[], void*);       /* Divide a physical drive into some partitions */
+int f_putc (TCHAR, FIL*);                           /* Put a character to the file */
+int f_puts (const TCHAR*, FIL*);                    /* Put a string to the file */
+int f_printf (FIL*, const TCHAR*, ...);             /* Put a formatted string to the file */
+TCHAR* f_gets (TCHAR*, int, FIL*);                  /* Get a string from the file */
+
+#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0)
+#define f_error(fp) (((fp)->flag & FA__ERROR) ? 1 : 0)
+#define f_tell(fp) ((fp)->fptr)
+#define f_size(fp) ((fp)->fsize)
+
+#ifndef EOF
+#define EOF (-1)
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Additional user defined functions                            */
+
+/* RTC function */
+#if !_FS_READONLY
+DWORD get_fattime (void);
+#endif
+
+/* Unicode support functions */
+#if _USE_LFN                        /* Unicode - OEM code conversion */
+WCHAR ff_convert (WCHAR, UINT);     /* OEM-Unicode bidirectional conversion */
+WCHAR ff_wtoupper (WCHAR);          /* Unicode upper-case conversion */
+#if _USE_LFN == 3                   /* Memory functions */
+void* ff_memalloc (UINT);           /* Allocate memory block */
+void ff_memfree (void*);            /* Free memory block */
+#endif
+#endif
+
+/* Sync functions */
+#if _FS_REENTRANT
+int ff_cre_syncobj (BYTE, _SYNC_t*);/* Create a sync object */
+int ff_req_grant (_SYNC_t);         /* Lock sync object */
+void ff_rel_grant (_SYNC_t);        /* Unlock sync object */
+int ff_del_syncobj (_SYNC_t);       /* Delete a sync object */
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address                                     */
+
+
+/* File access control and file status flags (FIL.flag) */
+
+#define FA_READ             0x01
+#define FA_OPEN_EXISTING    0x00
+#define FA__ERROR           0x80
+
+#if !_FS_READONLY
+#define FA_WRITE            0x02
+#define FA_CREATE_NEW       0x04
+#define FA_CREATE_ALWAYS    0x08
+#define FA_OPEN_ALWAYS      0x10
+#define FA__WRITTEN         0x20
+#define FA__DIRTY           0x40
+#endif
+
+
+/* FAT sub type (FATFS.fs_type) */
+
+#define FS_FAT12    1
+#define FS_FAT16    2
+#define FS_FAT32    3
+
+
+/* File attribute bits for directory entry */
+
+#define AM_RDO  0x01    /* Read only */
+#define AM_HID  0x02    /* Hidden */
+#define AM_SYS  0x04    /* System */
+#define AM_VOL  0x08    /* Volume label */
+#define AM_LFN  0x0F    /* LFN entry */
+#define AM_DIR  0x10    /* Directory */
+#define AM_ARC  0x20    /* Archive */
+#define AM_MASK 0x3F    /* Mask of defined bits */
+
+
+/* Fast seek feature */
+#define CREATE_LINKMAP  0xFFFFFFFF
+
+
+
+/*--------------------------------*/
+/* Multi-byte word access macros  */
+
+#if _WORD_ACCESS == 1   /* Enable word access to the FAT structure */
+#define LD_WORD(ptr)        (WORD)(*(WORD*)(BYTE*)(ptr))
+#define LD_DWORD(ptr)       (DWORD)(*(DWORD*)(BYTE*)(ptr))
+#define ST_WORD(ptr,val)    *(WORD*)(BYTE*)(ptr)=(WORD)(val)
+#define ST_DWORD(ptr,val)   *(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
+#else                   /* Use byte-by-byte access to the FAT structure */
+#define LD_WORD(ptr)        (WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
+#define LD_DWORD(ptr)       (DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr))
+#define ST_WORD(ptr,val)    *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8)
+#define ST_DWORD(ptr,val)   *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FATFS */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/SDFileSystem/FATFileSystem/ChaN/ffconf.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,192 @@
+/*---------------------------------------------------------------------------/
+/  FatFs - FAT file system module configuration file  R0.09a (C)ChaN, 2012
+/----------------------------------------------------------------------------/
+/
+/ CAUTION! Do not forget to make clean the project after any changes to
+/ the configuration options.
+/
+/----------------------------------------------------------------------------*/
+#ifndef _FFCONF
+#define _FFCONF 4004    /* Revision ID */
+
+#define FFS_DBG     0
+
+/*---------------------------------------------------------------------------/
+/ Functions and Buffer Configurations
+/----------------------------------------------------------------------------*/
+
+#define _FS_TINY        0   /* 0:Normal or 1:Tiny */
+/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system
+/  object instead of the sector buffer in the individual file object for file
+/  data transfer. This reduces memory consumption 512 bytes each file object. */
+
+
+#define _FS_READONLY    0   /* 0:Read/Write or 1:Read only */
+/* Setting _FS_READONLY to 1 defines read only configuration. This removes
+/  writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename,
+/  f_truncate and useless f_getfree. */
+
+
+#define _FS_MINIMIZE    0   /* 0 to 3 */
+/* The _FS_MINIMIZE option defines minimization level to remove some functions.
+/
+/   0: Full function.
+/   1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename
+/      are removed.
+/   2: f_opendir and f_readdir are removed in addition to 1.
+/   3: f_lseek is removed in addition to 2. */
+
+
+#define _USE_STRFUNC    0   /* 0:Disable or 1-2:Enable */
+/* To enable string functions, set _USE_STRFUNC to 1 or 2. */
+
+
+#define _USE_MKFS       1   /* 0:Disable or 1:Enable */
+/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */
+
+
+#define _USE_FORWARD    0   /* 0:Disable or 1:Enable */
+/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */
+
+
+#define _USE_FASTSEEK   0   /* 0:Disable or 1:Enable */
+/* To enable fast seek feature, set _USE_FASTSEEK to 1. */
+
+
+
+/*---------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/----------------------------------------------------------------------------*/
+
+#define _CODE_PAGE  858
+/* The _CODE_PAGE specifies the OEM code page to be used on the target system.
+/  Incorrect setting of the code page can cause a file open failure.
+/
+/   932  - Japanese Shift-JIS (DBCS, OEM, Windows)
+/   936  - Simplified Chinese GBK (DBCS, OEM, Windows)
+/   949  - Korean (DBCS, OEM, Windows)
+/   950  - Traditional Chinese Big5 (DBCS, OEM, Windows)
+/   1250 - Central Europe (Windows)
+/   1251 - Cyrillic (Windows)
+/   1252 - Latin 1 (Windows)
+/   1253 - Greek (Windows)
+/   1254 - Turkish (Windows)
+/   1255 - Hebrew (Windows)
+/   1256 - Arabic (Windows)
+/   1257 - Baltic (Windows)
+/   1258 - Vietnam (OEM, Windows)
+/   437  - U.S. (OEM)
+/   720  - Arabic (OEM)
+/   737  - Greek (OEM)
+/   775  - Baltic (OEM)
+/   850  - Multilingual Latin 1 (OEM)
+/   858  - Multilingual Latin 1 + Euro (OEM)
+/   852  - Latin 2 (OEM)
+/   855  - Cyrillic (OEM)
+/   866  - Russian (OEM)
+/   857  - Turkish (OEM)
+/   862  - Hebrew (OEM)
+/   874  - Thai (OEM, Windows)
+/   1    - ASCII only (Valid for non LFN cfg.)
+*/
+
+
+#define _USE_LFN    1       /* 0 to 3 */
+#define _MAX_LFN    255     /* Maximum LFN length to handle (12 to 255) */
+/* The _USE_LFN option switches the LFN support.
+/
+/   0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect.
+/   1: Enable LFN with static working buffer on the BSS. Always NOT reentrant.
+/   2: Enable LFN with dynamic working buffer on the STACK.
+/   3: Enable LFN with dynamic working buffer on the HEAP.
+/
+/  The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN,
+/  Unicode handling functions ff_convert() and ff_wtoupper() must be added
+/  to the project. When enable to use heap, memory control functions
+/  ff_memalloc() and ff_memfree() must be added to the project. */
+
+
+#define _LFN_UNICODE    0   /* 0:ANSI/OEM or 1:Unicode */
+/* To switch the character code set on FatFs API to Unicode,
+/  enable LFN feature and set _LFN_UNICODE to 1. */
+
+
+#define _FS_RPATH       0   /* 0 to 2 */
+/* The _FS_RPATH option configures relative path feature.
+/
+/   0: Disable relative path feature and remove related functions.
+/   1: Enable relative path. f_chdrive() and f_chdir() are available.
+/   2: f_getcwd() is available in addition to 1.
+/
+/  Note that output of the f_readdir fnction is affected by this option. */
+
+
+
+/*---------------------------------------------------------------------------/
+/ Physical Drive Configurations
+/----------------------------------------------------------------------------*/
+
+#define _VOLUMES    1
+/* Number of volumes (logical drives) to be used. */
+
+
+#define _MAX_SS     512     /* 512, 1024, 2048 or 4096 */
+/* Maximum sector size to be handled.
+/  Always set 512 for memory card and hard disk but a larger value may be
+/  required for on-board flash memory, floppy disk and optical disk.
+/  When _MAX_SS is larger than 512, it configures FatFs to variable sector size
+/  and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */
+
+
+#define _MULTI_PARTITION    0   /* 0:Single partition, 1/2:Enable multiple partition */
+/* When set to 0, each volume is bound to the same physical drive number and
+/ it can mount only first primaly partition. When it is set to 1, each volume
+/ is tied to the partitions listed in VolToPart[]. */
+
+
+#define _USE_ERASE  0   /* 0:Disable or 1:Enable */
+/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command
+/  should be added to the disk_ioctl functio. */
+
+
+
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/----------------------------------------------------------------------------*/
+
+#define _WORD_ACCESS    0   /* 0 or 1 */
+/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS
+/  option defines which access method is used to the word data on the FAT volume.
+/
+/   0: Byte-by-byte access.
+/   1: Word access. Do not choose this unless following condition is met.
+/
+/  When the byte order on the memory is big-endian or address miss-aligned word
+/  access results incorrect behavior, the _WORD_ACCESS must be set to 0.
+/  If it is not the case, the value can also be set to 1 to improve the
+/  performance and code size.
+*/
+
+
+/* A header file that defines sync object types on the O/S, such as
+/  windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */
+
+#define _FS_REENTRANT   0       /* 0:Disable or 1:Enable */
+#define _FS_TIMEOUT     1000    /* Timeout period in unit of time ticks */
+#define _SYNC_t         HANDLE  /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */
+
+/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module.
+/
+/   0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect.
+/   1: Enable reentrancy. Also user provided synchronization handlers,
+/      ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj
+/      function must be added to the project. */
+
+
+#define _FS_LOCK    0   /* 0:Disable or >=1:Enable */
+/* To enable file lock control feature, set _FS_LOCK to 1 or greater.
+   The value defines how many files can be opened simultaneously. */
+
+
+#endif /* _FFCONFIG */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/SDFileSystem/FATFileSystem/ChaN/integer.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,38 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef _INTEGER
+#define _INTEGER
+
+#ifdef _WIN32    /* FatFs development platform */
+
+#include <windows.h>
+#include <tchar.h>
+
+#else            /* Embedded platform */
+
+/* These types must be 16-bit, 32-bit or larger integer */
+typedef int             INT;
+typedef unsigned int    UINT;
+
+/* These types must be 8-bit integer */
+typedef char            CHAR;
+typedef unsigned char   UCHAR;
+typedef unsigned char   BYTE;
+
+/* These types must be 16-bit integer */
+typedef short           SHORT;
+typedef unsigned short  USHORT;
+typedef unsigned short  WORD;
+typedef unsigned short  WCHAR;
+
+/* These types must be 32-bit integer */
+typedef long            LONG;
+typedef unsigned long   ULONG;
+typedef unsigned long   DWORD;
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/SDFileSystem/FATFileSystem/FATDirHandle.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,79 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include <string.h>
+#include "ff.h"
+#include "FATDirHandle.h"
+
+using namespace mbed;
+
+FATDirHandle::FATDirHandle(const FATFS_DIR &the_dir) {
+    dir = the_dir;
+}
+
+int FATDirHandle::closedir() {
+    delete this;
+    return 0;
+}
+
+struct dirent *FATDirHandle::readdir() {
+    FILINFO finfo;
+
+#if _USE_LFN
+    finfo.lfname = cur_entry.d_name;
+    finfo.lfsize = sizeof(cur_entry.d_name);
+#endif // _USE_LFN
+
+    FRESULT res = f_readdir(&dir, &finfo);
+
+#if _USE_LFN
+    if(res != 0 || finfo.fname[0]==0) {
+        return NULL;
+    } else {
+        if(cur_entry.d_name[0]==0) {
+            // No long filename so use short filename.
+            memcpy(cur_entry.d_name, finfo.fname, sizeof(finfo.fname));
+        }
+        return &cur_entry;
+    }
+#else
+    if(res != 0 || finfo.fname[0]==0) {
+        return NULL;
+    } else {
+        memcpy(cur_entry.d_name, finfo.fname, sizeof(finfo.fname));
+        return &cur_entry;
+    }
+#endif /* _USE_LFN */
+}
+
+void FATDirHandle::rewinddir() {
+    dir.index = 0;
+}
+
+off_t FATDirHandle::telldir() {
+    return dir.index;
+}
+
+void FATDirHandle::seekdir(off_t location) {
+    dir.index = location;
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/SDFileSystem/FATFileSystem/FATDirHandle.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_FATDIRHANDLE_H
+#define MBED_FATDIRHANDLE_H
+
+#include "DirHandle.h"
+
+using namespace mbed;
+
+class FATDirHandle : public DirHandle {
+
+ public:
+    FATDirHandle(const FATFS_DIR &the_dir);
+    virtual int closedir();
+    virtual struct dirent *readdir();
+    virtual void rewinddir();
+    virtual off_t telldir();
+    virtual void seekdir(off_t location);
+
+ private:
+    FATFS_DIR dir;
+    struct dirent cur_entry;
+
+};
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/SDFileSystem/FATFileSystem/FATFileHandle.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,91 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "ff.h"
+#include "ffconf.h"
+#include "mbed_debug.h"
+
+#include "FATFileHandle.h"
+
+FATFileHandle::FATFileHandle(FIL fh) {
+    _fh = fh;
+}
+
+int FATFileHandle::close() {
+    int retval = f_close(&_fh);
+    delete this;
+    return retval;
+}
+
+ssize_t FATFileHandle::write(const void* buffer, size_t length) {
+    UINT n;
+    FRESULT res = f_write(&_fh, buffer, length, &n);
+    if (res) { 
+        debug_if(FFS_DBG, "f_write() failed: %d", res);
+        return -1;
+    }
+    return n;
+}
+        
+ssize_t FATFileHandle::read(void* buffer, size_t length) {
+    debug_if(FFS_DBG, "read(%d)\n", length);
+    UINT n;
+    FRESULT res = f_read(&_fh, buffer, length, &n);
+    if (res) {
+        debug_if(FFS_DBG, "f_read() failed: %d\n", res);
+        return -1;
+    }
+    return n;
+}
+
+int FATFileHandle::isatty() {
+    return 0;
+}
+
+off_t FATFileHandle::lseek(off_t position, int whence) {
+    if (whence == SEEK_END) {
+        position += _fh.fsize;
+    } else if(whence==SEEK_CUR) {
+        position += _fh.fptr;
+    }
+    FRESULT res = f_lseek(&_fh, position);
+    if (res) {
+        debug_if(FFS_DBG, "lseek failed: %d\n", res);
+        return -1;
+    } else {
+        debug_if(FFS_DBG, "lseek OK, returning %i\n", _fh.fptr);
+        return _fh.fptr;
+    }
+}
+
+int FATFileHandle::fsync() {
+    FRESULT res = f_sync(&_fh);
+    if (res) {
+        debug_if(FFS_DBG, "f_sync() failed: %d\n", res);
+        return -1;
+    }
+    return 0;
+}
+
+off_t FATFileHandle::flen() {
+    return _fh.fsize;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/SDFileSystem/FATFileSystem/FATFileHandle.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_FATFILEHANDLE_H
+#define MBED_FATFILEHANDLE_H
+
+#include "FileHandle.h"
+
+using namespace mbed;
+
+class FATFileHandle : public FileHandle {
+public:
+
+    FATFileHandle(FIL fh);
+    virtual int close();
+    virtual ssize_t write(const void* buffer, size_t length);
+    virtual ssize_t read(void* buffer, size_t length);
+    virtual int isatty();
+    virtual off_t lseek(off_t position, int whence);
+    virtual int fsync();
+    virtual off_t flen();
+
+protected:
+
+    FIL _fh;
+
+};
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/SDFileSystem/FATFileSystem/FATFileSystem.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,148 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "mbed.h"
+
+#include "ffconf.h"
+#include "mbed_debug.h"
+
+#include "FATFileSystem.h"
+#include "FATFileHandle.h"
+#include "FATDirHandle.h"
+
+DWORD get_fattime(void) {
+    time_t rawtime;
+    time(&rawtime);
+    struct tm *ptm = localtime(&rawtime);
+    return (DWORD)(ptm->tm_year - 80) << 25
+         | (DWORD)(ptm->tm_mon + 1  ) << 21
+         | (DWORD)(ptm->tm_mday     ) << 16
+         | (DWORD)(ptm->tm_hour     ) << 11
+         | (DWORD)(ptm->tm_min      ) << 5
+         | (DWORD)(ptm->tm_sec/2    );
+}
+
+FATFileSystem *FATFileSystem::_ffs[_VOLUMES] = {0};
+
+FATFileSystem::FATFileSystem(const char* n) : FileSystemLike(n) {
+    debug_if(FFS_DBG, "FATFileSystem(%s)\n", n);
+    for(int i=0; i<_VOLUMES; i++) {
+        if(_ffs[i] == 0) {
+            _ffs[i] = this;
+            _fsid = i;
+            debug_if(FFS_DBG, "Mounting [%s] on ffs drive [%d]\n", _name, _fsid);
+            f_mount(i, &_fs);
+            return;
+        }
+    }
+    error("Couldn't create %s in FATFileSystem::FATFileSystem\n", n);
+}
+
+FATFileSystem::~FATFileSystem() {
+    for (int i=0; i<_VOLUMES; i++) {
+        if (_ffs[i] == this) {
+            _ffs[i] = 0;
+            f_mount(i, NULL);
+        }
+    }
+}
+
+FileHandle *FATFileSystem::open(const char* name, int flags) {
+    debug_if(FFS_DBG, "open(%s) on filesystem [%s], drv [%d]\n", name, _name, _fsid);
+    char n[64];
+    sprintf(n, "%d:/%s", _fsid, name);
+    
+    /* POSIX flags -> FatFS open mode */
+    BYTE openmode;
+    if (flags & O_RDWR) {
+        openmode = FA_READ|FA_WRITE;
+    } else if(flags & O_WRONLY) {
+        openmode = FA_WRITE;
+    } else {
+        openmode = FA_READ;
+    }
+    if(flags & O_CREAT) {
+        if(flags & O_TRUNC) {
+            openmode |= FA_CREATE_ALWAYS;
+        } else {
+            openmode |= FA_OPEN_ALWAYS;
+        }
+    }
+    
+    FIL fh;
+    FRESULT res = f_open(&fh, n, openmode);
+    if (res) { 
+        debug_if(FFS_DBG, "f_open('w') failed: %d\n", res);
+        return NULL;
+    }
+    if (flags & O_APPEND) {
+        f_lseek(&fh, fh.fsize);
+    }
+    return new FATFileHandle(fh);
+}
+
+int FATFileSystem::stat(const char * name, FILINFO * info)
+{
+    char n[64];
+    sprintf(n, "%d:/%s", _fsid, name);
+	
+    FRESULT res = f_stat(n, info);	
+		if (res)
+		{
+			debug_if(FFS_DBG, "f_stat() failed: %d\n", res);
+			return -1;
+		}
+		
+		return 0;
+}
+    
+int FATFileSystem::remove(const char *filename) {
+    FRESULT res = f_unlink(filename);
+    if (res) { 
+        debug_if(FFS_DBG, "f_unlink() failed: %d\n", res);
+        return -1;
+    }
+    return 0;
+}
+
+int FATFileSystem::format() {
+    FRESULT res = f_mkfs(_fsid, 0, 512); // Logical drive number, Partitioning rule, Allocation unit size (bytes per cluster)
+    if (res) {
+        debug_if(FFS_DBG, "f_mkfs() failed: %d\n", res);
+        return -1;
+    }
+    return 0;
+}
+
+DirHandle *FATFileSystem::opendir(const char *name) {
+    FATFS_DIR dir;
+    FRESULT res = f_opendir(&dir, name);
+    if (res != 0) {
+        return NULL;
+    }
+    return new FATDirHandle(dir);
+}
+
+int FATFileSystem::mkdir(const char *name, mode_t mode) {
+    FRESULT res = f_mkdir(name);
+    return res == 0 ? 0 : -1;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/SDFileSystem/FATFileSystem/FATFileSystem.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,85 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_FATFILESYSTEM_H
+#define MBED_FATFILESYSTEM_H
+
+#include "FileSystemLike.h"
+#include "FileHandle.h"
+#include "ff.h"
+#include <stdint.h>
+
+using namespace mbed;
+
+/**
+  * FATFileSystem based on ChaN's Fat Filesystem library v0.8 
+  */
+class FATFileSystem : public FileSystemLike {
+public:
+
+    FATFileSystem(const char* n);
+    virtual ~FATFileSystem();
+
+    static FATFileSystem * _ffs[_VOLUMES];   // FATFileSystem objects, as parallel to FatFs drives array
+    FATFS _fs;                               // Work area (file system object) for logical drive
+    int _fsid;
+    
+    /**
+      * Opens a file on the filesystem
+      */
+    virtual FileHandle *open(const char* name, int flags);
+
+		/**
+			* Gets information on a file
+			*/
+		virtual int stat(const char * name, FILINFO *);
+    
+    /**
+     * Removes a file path
+     */
+    virtual int remove(const char *filename);
+
+    /**
+     * Formats a logical drive, FDISK artitioning rule, 512 bytes per cluster
+     */
+    virtual int format();
+
+    /**
+      * Opens a directory on the filesystem
+      */
+    virtual DirHandle *opendir(const char *name);
+    
+    /**
+     * Creates a directory path
+     */
+    virtual int mkdir(const char *name, mode_t mode);
+
+    virtual int disk_initialize() { return 0; }
+    virtual int disk_status() { return 0; }
+    virtual int disk_read(uint8_t * buffer, uint64_t sector) = 0;
+    virtual int disk_write(const uint8_t * buffer, uint64_t sector) = 0;
+    virtual int disk_sync() { return 0; }
+    virtual uint64_t disk_sectors() = 0;
+
+};
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/SDFileSystem/FATFileSystem/MemFileSystem.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library - MemFileSystem
+ * Copyright (c) 2008, sford
+ */
+
+
+#ifndef MBED_MEMFILESYSTEM_H
+#define MBED_MEMFILESYSTEM_H
+
+#include "FATFileSystem.h"
+
+namespace mbed
+{
+
+    class MemFileSystem : public FATFileSystem
+    {
+    public:
+    
+        // 2000 sectors, each 512 bytes (malloced as required)
+        char *sectors[2000];
+    
+        MemFileSystem(const char* name) : FATFileSystem(name) {
+            memset(sectors, 0, sizeof(sectors));
+        }
+    
+        virtual ~MemFileSystem() {
+            for(int i = 0; i < 2000; i++) {
+                if(sectors[i]) {
+                    free(sectors[i]);
+                }
+            }
+        }
+    
+        // read a sector in to the buffer, return 0 if ok
+        virtual int disk_read(char *buffer, int sector) {
+            if(sectors[sector] == 0) {
+                // nothing allocated means sector is empty
+                memset(buffer, 0, 512);
+            } else {
+                memcpy(buffer, sectors[sector], 512);
+            }
+            return 0;
+        }
+    
+        // write a sector from the buffer, return 0 if ok
+        virtual int disk_write(const char *buffer, int sector) {
+            // if buffer is zero deallocate sector
+            char zero[512];
+            memset(zero, 0, 512);
+            if(memcmp(zero, buffer, 512)==0) {
+                if(sectors[sector] != 0) {
+                    free(sectors[sector]);
+                    sectors[sector] = 0;
+                }
+                return 0;
+            }
+            // else allocate a sector if needed, and write
+            if(sectors[sector] == 0) {
+                char *sec = (char*)malloc(512);
+                if(sec==0) {
+                    return 1; // out of memory
+                }
+                sectors[sector] = sec;
+            }
+            memcpy(sectors[sector], buffer, 512);
+            return 0;
+        }
+    
+        // return the number of sectors
+        virtual int disk_sectors() {
+            return sizeof(sectors)/sizeof(sectors[0]);
+        }
+    
+    };
+
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/SDFileSystem/SDFileSystem.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,481 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/* Introduction
+ * ------------
+ * SD and MMC cards support a number of interfaces, but common to them all
+ * is one based on SPI. This is the one I'm implmenting because it means
+ * it is much more portable even though not so performant, and we already
+ * have the mbed SPI Interface!
+ *
+ * The main reference I'm using is Chapter 7, "SPI Mode" of:
+ *  http://www.sdcard.org/developers/tech/sdcard/pls/Simplified_Physical_Layer_Spec.pdf
+ *
+ * SPI Startup
+ * -----------
+ * The SD card powers up in SD mode. The SPI interface mode is selected by
+ * asserting CS low and sending the reset command (CMD0). The card will
+ * respond with a (R1) response.
+ *
+ * CMD8 is optionally sent to determine the voltage range supported, and
+ * indirectly determine whether it is a version 1.x SD/non-SD card or
+ * version 2.x. I'll just ignore this for now.
+ *
+ * ACMD41 is repeatedly issued to initialise the card, until "in idle"
+ * (bit 0) of the R1 response goes to '0', indicating it is initialised.
+ *
+ * You should also indicate whether the host supports High Capicity cards,
+ * and check whether the card is high capacity - i'll also ignore this
+ *
+ * SPI Protocol
+ * ------------
+ * The SD SPI protocol is based on transactions made up of 8-bit words, with
+ * the host starting every bus transaction by asserting the CS signal low. The
+ * card always responds to commands, data blocks and errors.
+ *
+ * The protocol supports a CRC, but by default it is off (except for the
+ * first reset CMD0, where the CRC can just be pre-calculated, and CMD8)
+ * I'll leave the CRC off I think!
+ *
+ * Standard capacity cards have variable data block sizes, whereas High
+ * Capacity cards fix the size of data block to 512 bytes. I'll therefore
+ * just always use the Standard Capacity cards with a block size of 512 bytes.
+ * This is set with CMD16.
+ *
+ * You can read and write single blocks (CMD17, CMD25) or multiple blocks
+ * (CMD18, CMD25). For simplicity, I'll just use single block accesses. When
+ * the card gets a read command, it responds with a response token, and then
+ * a data token or an error.
+ *
+ * SPI Command Format
+ * ------------------
+ * Commands are 6-bytes long, containing the command, 32-bit argument, and CRC.
+ *
+ * +---------------+------------+------------+-----------+----------+--------------+
+ * | 01 | cmd[5:0] | arg[31:24] | arg[23:16] | arg[15:8] | arg[7:0] | crc[6:0] | 1 |
+ * +---------------+------------+------------+-----------+----------+--------------+
+ *
+ * As I'm not using CRC, I can fix that byte to what is needed for CMD0 (0x95)
+ *
+ * All Application Specific commands shall be preceded with APP_CMD (CMD55).
+ *
+ * SPI Response Format
+ * -------------------
+ * The main response format (R1) is a status byte (normally zero). Key flags:
+ *  idle - 1 if the card is in an idle state/initialising
+ *  cmd  - 1 if an illegal command code was detected
+ *
+ *    +-------------------------------------------------+
+ * R1 | 0 | arg | addr | seq | crc | cmd | erase | idle |
+ *    +-------------------------------------------------+
+ *
+ * R1b is the same, except it is followed by a busy signal (zeros) until
+ * the first non-zero byte when it is ready again.
+ *
+ * Data Response Token
+ * -------------------
+ * Every data block written to the card is acknowledged by a byte
+ * response token
+ *
+ * +----------------------+
+ * | xxx | 0 | status | 1 |
+ * +----------------------+
+ *              010 - OK!
+ *              101 - CRC Error
+ *              110 - Write Error
+ *
+ * Single Block Read and Write
+ * ---------------------------
+ *
+ * Block transfers have a byte header, followed by the data, followed
+ * by a 16-bit CRC. In our case, the data will always be 512 bytes.
+ *
+ * +------+---------+---------+- -  - -+---------+-----------+----------+
+ * | 0xFE | data[0] | data[1] |        | data[n] | crc[15:8] | crc[7:0] |
+ * +------+---------+---------+- -  - -+---------+-----------+----------+
+ */
+#include "SDFileSystem.h"
+#include "mbed.h"
+#include "mbed_debug.h"
+
+#define SD_COMMAND_TIMEOUT 5000
+
+#define SD_DBG             0
+
+SDFileSystem::SDFileSystem(PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name) :
+    FATFileSystem(name), _spi(mosi, miso, sclk), _cs(cs) {
+    _cs = 1;
+}
+
+#define R1_IDLE_STATE           (1 << 0)
+#define R1_ERASE_RESET          (1 << 1)
+#define R1_ILLEGAL_COMMAND      (1 << 2)
+#define R1_COM_CRC_ERROR        (1 << 3)
+#define R1_ERASE_SEQUENCE_ERROR (1 << 4)
+#define R1_ADDRESS_ERROR        (1 << 5)
+#define R1_PARAMETER_ERROR      (1 << 6)
+
+// Types
+#define SDCARD_FAIL 0 //!< v1.x Standard Capacity
+#define SDCARD_V1   1 //!< v2.x Standard Capacity
+#define SDCARD_V2   2 //!< v2.x High Capacity
+#define SDCARD_V2HC 3 //!< Not recognised as an SD Card
+
+int SDFileSystem::initialise_card() 
+{
+		int numtries = 3;
+		int res = 0;
+		
+		debug("Initializing SD/MMC card ...\r\n");
+		while (numtries > 0)
+		{
+			// Set to 100kHz for initialisation, and clock card with cs = 1
+			_spi.frequency(100000);
+			_cs = 1;
+			for (int i = 0; i < 16; i++) {
+        _spi.write(0xFF);
+			}
+    
+			// send CMD0, should return with all zeros except IDLE STATE set (bit 0)
+			res = _cmd(0, 0); // software reset
+			if (res == R1_IDLE_STATE) break;
+			
+			
+			// Retry ... wait another 500 ms
+			debug("Retrying ...\r\n");
+			wait(0.5);
+		}
+		if (res != R1_IDLE_STATE) 
+		{
+					debug("No disk, or could not put SD card in to SPI idle state\r\n");
+					return SDCARD_FAIL;
+		}
+	
+    
+    // send CMD8 to determine whther it is ver 2.x
+    int r = _cmd8();
+    if (r == R1_IDLE_STATE) {
+        return initialise_card_v2();
+    } else if (r == (R1_IDLE_STATE | R1_ILLEGAL_COMMAND)) {
+        return initialise_card_v1();
+    } else {
+        debug("Not in idle state after sending CMD8 (not an SD card?)\r\n");
+        return SDCARD_FAIL;
+    }
+}
+
+int SDFileSystem::initialise_card_v1() {
+    for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
+        _cmd(55, 0);
+        if (_cmd(41, 0) == 0) {
+            cdv = 512;
+            debug_if(SD_DBG, "\n\rInit: SEDCARD_V1\n\r");
+            return SDCARD_V1;
+        }
+    }
+    
+    debug("Timeout waiting for v1.x card\n");
+    return SDCARD_FAIL;
+}
+
+int SDFileSystem::initialise_card_v2() {
+    for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
+        wait_ms(50);
+        _cmd58();
+        _cmd(55, 0);
+        if (_cmd(41, 0x40000000) == 0) {
+            _cmd58();
+            debug_if(SD_DBG, "\n\rInit: SDCARD_V2\n\r");
+            cdv = 1;
+            return SDCARD_V2;
+        }
+    }
+    
+    debug("Timeout waiting for v2.x card\r\n");
+    return SDCARD_FAIL;
+}
+
+int SDFileSystem::disk_initialize() {
+    int i = initialise_card();
+    debug_if(SD_DBG, "init card = %d\n", i);
+    _sectors = _sd_sectors();
+    
+    // Set block length to 512 (CMD16)
+    if (_cmd(16, 512) != 0) {
+        debug("Set 512-byte block timed out\r\n");
+        return 1;
+    }
+    
+    _spi.frequency(1000000); // Set to 1MHz for data transfer
+    return 0;
+}
+
+int SDFileSystem::disk_write(const uint8_t *buffer, uint64_t block_number) {
+    // set write address for single block (CMD24)
+    if (_cmd(24, block_number * cdv) != 0) {
+        return 1;
+    }
+    
+    // send the data block
+    _write(buffer, 512);
+    return 0;
+}
+
+int SDFileSystem::disk_read(uint8_t *buffer, uint64_t block_number) {
+    // set read address for single block (CMD17)
+    if (_cmd(17, block_number * cdv) != 0) {
+        return 1;
+    }
+    
+    // receive the data
+    _read(buffer, 512);
+    return 0;
+}
+
+int SDFileSystem::disk_status() { return 0; }
+int SDFileSystem::disk_sync() { return 0; }
+uint64_t SDFileSystem::disk_sectors() { return _sectors; }
+
+
+// PRIVATE FUNCTIONS
+int SDFileSystem::_cmd(int cmd, int arg) {
+    _cs = 0;
+    
+    // send a command
+    _spi.write(0x40 | cmd);
+    _spi.write(arg >> 24);
+    _spi.write(arg >> 16);
+    _spi.write(arg >> 8);
+    _spi.write(arg >> 0);
+    _spi.write(0x95);
+    
+    // wait for the repsonse (response[7] == 0)
+    for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
+        int response = _spi.write(0xFF);
+        if (!(response & 0x80)) {
+            _cs = 1;
+            _spi.write(0xFF);
+            return response;
+        }
+    }
+    _cs = 1;
+    _spi.write(0xFF);
+    return -1; // timeout
+}
+int SDFileSystem::_cmdx(int cmd, int arg) {
+    _cs = 0;
+    
+    // send a command
+    _spi.write(0x40 | cmd);
+    _spi.write(arg >> 24);
+    _spi.write(arg >> 16);
+    _spi.write(arg >> 8);
+    _spi.write(arg >> 0);
+    _spi.write(0x95);
+    
+    // wait for the repsonse (response[7] == 0)
+    for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
+        int response = _spi.write(0xFF);
+        if (!(response & 0x80)) {
+            return response;
+        }
+    }
+    _cs = 1;
+    _spi.write(0xFF);
+    return -1; // timeout
+}
+
+
+int SDFileSystem::_cmd58() {
+    _cs = 0;
+    int arg = 0;
+    
+    // send a command
+    _spi.write(0x40 | 58);
+    _spi.write(arg >> 24);
+    _spi.write(arg >> 16);
+    _spi.write(arg >> 8);
+    _spi.write(arg >> 0);
+    _spi.write(0x95);
+    
+    // wait for the repsonse (response[7] == 0)
+    for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
+        int response = _spi.write(0xFF);
+        if (!(response & 0x80)) {
+            int ocr = _spi.write(0xFF) << 24;
+            ocr |= _spi.write(0xFF) << 16;
+            ocr |= _spi.write(0xFF) << 8;
+            ocr |= _spi.write(0xFF) << 0;
+            _cs = 1;
+            _spi.write(0xFF);
+            return response;
+        }
+    }
+    _cs = 1;
+    _spi.write(0xFF);
+    return -1; // timeout
+}
+
+int SDFileSystem::_cmd8() {
+    _cs = 0;
+    
+    // send a command
+    _spi.write(0x40 | 8); // CMD8
+    _spi.write(0x00);     // reserved
+    _spi.write(0x00);     // reserved
+    _spi.write(0x01);     // 3.3v
+    _spi.write(0xAA);     // check pattern
+    _spi.write(0x87);     // crc
+    
+    // wait for the repsonse (response[7] == 0)
+    for (int i = 0; i < SD_COMMAND_TIMEOUT * 1000; i++) {
+        char response[5];
+        response[0] = _spi.write(0xFF);
+        if (!(response[0] & 0x80)) {
+            for (int j = 1; j < 5; j++) {
+                response[i] = _spi.write(0xFF);
+            }
+            _cs = 1;
+            _spi.write(0xFF);
+            return response[0];
+        }
+    }
+    _cs = 1;
+    _spi.write(0xFF);
+    return -1; // timeout
+}
+
+int SDFileSystem::_read(uint8_t *buffer, uint32_t length) {
+    _cs = 0;
+    
+    // read until start byte (0xFF)
+    while (_spi.write(0xFF) != 0xFE);
+    
+    // read data
+    for (int i = 0; i < length; i++) {
+        buffer[i] = _spi.write(0xFF);
+    }
+    _spi.write(0xFF); // checksum
+    _spi.write(0xFF);
+    
+    _cs = 1;
+    _spi.write(0xFF);
+    return 0;
+}
+
+int SDFileSystem::_write(const uint8_t*buffer, uint32_t length) {
+    _cs = 0;
+    
+    // indicate start of block
+    _spi.write(0xFE);
+    
+    // write the data
+    for (int i = 0; i < length; i++) {
+        _spi.write(buffer[i]);
+    }
+    
+    // write the checksum
+    _spi.write(0xFF);
+    _spi.write(0xFF);
+    
+    // check the response token
+    if ((_spi.write(0xFF) & 0x1F) != 0x05) {
+        _cs = 1;
+        _spi.write(0xFF);
+        return 1;
+    }
+    
+    // wait for write to finish
+    while (_spi.write(0xFF) == 0);
+    
+    _cs = 1;
+    _spi.write(0xFF);
+    return 0;
+}
+
+static uint32_t ext_bits(unsigned char *data, int msb, int lsb) {
+    uint32_t bits = 0;
+    uint32_t size = 1 + msb - lsb;
+    for (int i = 0; i < size; i++) {
+        uint32_t position = lsb + i;
+        uint32_t byte = 15 - (position >> 3);
+        uint32_t bit = position & 0x7;
+        uint32_t value = (data[byte] >> bit) & 1;
+        bits |= value << i;
+    }
+    return bits;
+}
+
+uint64_t SDFileSystem::_sd_sectors() {
+    uint32_t c_size, c_size_mult, read_bl_len;
+    uint32_t block_len, mult, blocknr, capacity;
+    uint32_t hc_c_size;
+    uint64_t blocks;
+    
+    // CMD9, Response R2 (R1 byte + 16-byte block read)
+    if (_cmdx(9, 0) != 0) {
+        debug("Didn't get a response from the disk\n");
+        return 0;
+    }
+    
+    uint8_t csd[16];
+    if (_read(csd, 16) != 0) {
+        debug("Couldn't read csd response from disk\n");
+        return 0;
+    }
+    
+    // csd_structure : csd[127:126]
+    // c_size        : csd[73:62]
+    // c_size_mult   : csd[49:47]
+    // read_bl_len   : csd[83:80] - the *maximum* read block length
+    
+    int csd_structure = ext_bits(csd, 127, 126);
+    
+    switch (csd_structure) {
+        case 0:
+            cdv = 512;
+            c_size = ext_bits(csd, 73, 62);
+            c_size_mult = ext_bits(csd, 49, 47);
+            read_bl_len = ext_bits(csd, 83, 80);
+            
+            block_len = 1 << read_bl_len;
+            mult = 1 << (c_size_mult + 2);
+            blocknr = (c_size + 1) * mult;
+            capacity = blocknr * block_len;
+            blocks = capacity / 512;
+            debug_if(SD_DBG, "\n\rSDCard\n\rc_size: %d \n\rcapacity: %ld \n\rsectors: %lld\n\r", c_size, capacity, blocks);
+            break;
+        
+        case 1:
+            cdv = 1;
+            hc_c_size = ext_bits(csd, 63, 48);
+            blocks = (hc_c_size+1)*1024;
+            debug_if(SD_DBG, "\n\rSDHC Card \n\rhc_c_size: %d\n\rcapacity: %lld \n\rsectors: %lld\n\r", hc_c_size, blocks*512, blocks);
+            break;
+        
+        default:
+            debug("CSD struct unsupported\r\n");
+            return 0;
+    };
+    return blocks;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/SDFileSystem/SDFileSystem.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,85 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_SDFILESYSTEM_H
+#define MBED_SDFILESYSTEM_H
+
+#include "mbed.h"
+#include "FATFileSystem.h"
+#include <stdint.h>
+
+/** Access the filesystem on an SD Card using SPI
+ *
+ * @code
+ * #include "mbed.h"
+ * #include "SDFileSystem.h"
+ *
+ * SDFileSystem sd(p5, p6, p7, p12, "sd"); // MOSI, MISO, SCLK, SSEL
+ *  
+ * int main() {
+ *     FILE *fp = fopen("/sd/mbed.txt", "w");
+ *     fprintf(fp, "Hello World!\n");
+ *     fclose(fp);
+ * }
+ * @endcode
+ */
+class SDFileSystem : public FATFileSystem {
+public:
+
+    /** Create the File System for accessing an SD Card using SPI
+     *
+     * @param mosi SPI mosi pin connected to SD Card
+     * @param miso SPI miso pin conencted to SD Card
+     * @param sclk SPI sclk pin connected to SD Card
+     * @param cs   DigitalOut pin used as SD Card chip select
+     * @param name The name used to access the virtual filesystem
+     */
+    SDFileSystem(PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name);
+    
+    virtual int disk_initialize();
+    virtual int disk_status();
+    virtual int disk_read(uint8_t * buffer, uint64_t block_number);
+    virtual int disk_write(const uint8_t * buffer, uint64_t block_number);
+    virtual int disk_sync();
+    virtual uint64_t disk_sectors();
+
+protected:
+
+    int _cmd(int cmd, int arg);
+    int _cmdx(int cmd, int arg);
+    int _cmd8();
+    int _cmd58();
+    int initialise_card();
+    int initialise_card_v1();
+    int initialise_card_v2();
+    
+    int _read(uint8_t * buffer, uint32_t length);
+    int _write(const uint8_t *buffer, uint32_t length);
+    uint64_t _sd_sectors();
+    uint64_t _sectors;
+    
+    SPI _spi;
+    DigitalOut _cs;
+    int cdv;
+};
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Shell.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,244 @@
+#include "mbed.h"
+#include "cmsis_os.h"
+
+#include <stdlib.h>
+#include <string.h>
+#include <vector>
+#include <string>
+#include "Shell.h"
+#include "Utility.h"
+#include "DHT.h"
+#include "SDFileSystem.h"
+#include "SPI_TFT_ILI9341.h"
+
+
+extern DHT dht;
+extern SDFileSystem sdcard;
+extern I2C i2c;
+extern SPI_TFT_ILI9341 TFT;
+extern std::vector<std::string> images;
+
+void shellUsage(Stream * chp, const char *p) 
+{
+	 chp->printf("Usage: %s\r\n", p);
+}
+
+static void list_commands(Stream *chp, const ShellCommand *scp) {
+
+  while (scp->sc_name != NULL) {
+    chp->printf("%s ", scp->sc_name);
+    scp++;
+  }
+}
+
+static void cmd_info(Stream * chp, int argc, char *argv[]) 
+{
+
+  (void)argv;
+  if (argc > 0) {
+    shellUsage(chp, "info");
+    return;
+  }
+	
+	long sp = __current_sp();
+	long pc = __current_pc();
+	
+
+	heapinfo(chp);
+
+}
+
+
+static ShellCommand local_commands[] = {
+  {"info", cmd_info},
+  {NULL, NULL}
+};
+
+static bool cmdexec(const ShellCommand *scp, Stream * chp,
+                      char *name, int argc, char *argv[]) 
+{
+  while (scp->sc_name != NULL) {
+    if (strcasecmp(scp->sc_name, name) == 0) {
+      scp->sc_func(chp, argc, argv);
+      return false;
+    }
+    scp++;
+  }
+  return true;
+}
+
+void shellStart(const ShellConfig *p) 
+{
+  int n;
+  Stream *chp = p->sc_channel;
+  const ShellCommand *scp = p->sc_commands;
+  char *lp, *cmd, *tokp, line[SHELL_MAX_LINE_LENGTH];
+  char *args[SHELL_MAX_ARGUMENTS + 1];
+
+  chp->printf("\r\nEmbed/RX Shell\r\n");
+  while (true) {
+    chp->printf(">> ");
+    if (shellGetLine(chp, line, sizeof(line))) {
+      chp->printf("\r\nlogout");
+      break;
+    }
+    lp = _strtok(line, " \t", &tokp);
+    cmd = lp;
+    n = 0;
+    while ((lp = _strtok(NULL, " \t", &tokp)) != NULL) {
+      if (n >= SHELL_MAX_ARGUMENTS) {
+        chp->printf("too many arguments\r\n");
+        cmd = NULL;
+        break;
+      }
+      args[n++] = lp;
+    }
+    args[n] = NULL;
+    if (cmd != NULL) {
+      if (strcasecmp(cmd, "exit") == 0) {
+        if (n > 0) {
+          shellUsage(chp, "exit");
+          continue;
+        }
+				// Break here breaks the outer loop
+				// hence, we exit the shell.
+        break;
+      }
+      else if (strcasecmp(cmd, "help") == 0) {
+        if (n > 0) {
+          shellUsage(chp, "help");
+          continue;
+        }
+        chp->printf("Commands: help exit ");
+        list_commands(chp, local_commands);
+        if (scp != NULL)
+          list_commands(chp, scp);
+        chp->printf("\r\n");
+      }
+      else if (cmdexec(local_commands, chp, cmd, n, args) &&
+          ((scp == NULL) || cmdexec(scp, chp, cmd, n, args))) {
+        chp->printf("%s", cmd);
+        chp->printf(" ?\r\n");
+      }
+    }
+  }
+}
+
+bool shellGetLine(Stream *chp, char *line, unsigned size) {
+  char *p = line;
+
+  while (true) {
+    char c;
+
+    if ((c = chp->getc()) == 0)
+      return true;
+    if (c == 4) {
+      chp->printf("^D");
+      return true;
+    }
+    if (c == 8) {
+      if (p != line) {
+        chp->putc(c);
+        chp->putc(0x20);
+        chp->putc(c);
+        p--;
+      }
+      continue;
+    }
+    if (c == '\r') {
+      chp->printf("\r\n");
+      *p = 0;
+      return false;
+    }
+    if (c < 0x20)
+      continue;
+    if (p < line + size - 1) {
+      chp->putc(c);
+      *p++ = (char)c;
+    }
+  }
+}
+
+/**
+ *  \brief List Directories and files 
+ *	\param none
+ *	\return int
+ **/
+
+void cmd_ls(Stream * chp, int argc, char * argv[])
+{
+	DIR * dp;
+	struct dirent * dirp;
+	FILINFO fileInfo;
+	char dirroot[256];
+	
+	if (argc >= 1)
+		sprintf(dirroot, "/sd/%s", argv[0]);
+	else
+		sprintf(dirroot, "/sd");
+	
+	chp->printf("Listing directory [%s]\r\n", dirroot);
+	
+	dp = opendir(dirroot);			
+	while((dirp = readdir(dp)) != NULL)
+	{
+		if (sdcard.stat(dirp->d_name, &fileInfo) == 0)
+		{
+			if (fileInfo.fattrib & AM_DIR )
+					chp->printf("<DIR>\t\t");
+			else
+					chp->printf("%ld\t\t", fileInfo.fsize);
+		}
+		chp->printf("%s\r\n", dirp->d_name);
+	}
+	closedir(dp);
+}
+
+void cmd_sensor(Stream * chp, int argc, char * argv[])
+{
+	float temperature, humidity;
+
+	
+	if (dht.readData() == ERROR_NONE)
+  {
+		temperature = dht.ReadTemperature(CELCIUS);
+		humidity = dht.ReadHumidity();
+		
+		chp->printf("Temperature %.2fC \r\n", temperature);
+    chp->printf("Humidity %.2f%% \r\n", humidity);
+		chp->printf("Dew point %.2f\r\n", dht.CalcdewPoint(temperature, humidity));
+  }
+}
+
+void cmd_load(Stream * chp, int argc, char * argv[])
+{
+	char filename[256];
+	
+	if (argc != 1)
+	{
+		shellUsage(chp, "load <bitmapfile>");
+		return;
+	}
+	
+	sprintf(filename, "/sd/%s", argv[0]);
+		// Load a bitmap startup file
+	int err = TFT.BMP_16(0,0, filename);
+	if (err != 1) TFT.printf(" - Err: %d", err);	
+	
+}
+
+void cmd_rollimages(Stream * chp, int argc, char * argv[])
+{
+			for(std::vector<std::string>::iterator i = images.begin();
+				i != images.end(); i++)
+			{
+				chp->printf("Loading image %s...\r\n", (*i).c_str());
+				TFT.cls();
+				int err = TFT.BMP_16(0,0, (*i).c_str());
+				if (err != 1) chp->printf(" - Err: %d", err);
+			
+				wait(1.0);
+				heapinfo(chp);
+			}	
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Shell.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,41 @@
+#ifndef _TINY_SHELL_H_
+#define _TINY_SHELL_H_
+
+#include "mbed.h"
+#include "cmsis_os.h"
+
+#define SHELL_MAX_LINE_LENGTH       64
+#define SHELL_MAX_ARGUMENTS         4
+
+typedef void (*shellcmd_t) (Stream *, int , char **);
+
+typedef struct {
+    const char * sc_name;
+    shellcmd_t sc_func;
+} ShellCommand;
+
+typedef struct {
+    Stream * sc_channel;
+    ShellCommand * sc_commands;
+} ShellConfig;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* User commands */
+void cmd_ls(Stream * chp, int argc, char * argv[]);	
+void cmd_sensor(Stream * chp, int argc, char * argv[]);
+void cmd_load(Stream * chp, int argc, char * argv[]);
+void cmd_rollimages(Stream * chp, int argc, char * argv[]);
+
+void shellStart(const ShellConfig *);
+bool shellGetLine(Stream * chp, char *line, unsigned size);
+void shellUsage(Stream * chp, const char *p);	
+	
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Utility.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,144 @@
+#include "Utility.h"
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdarg.h>
+#include <string>
+#include <cctype>
+#include <algorithm>
+
+extern I2C i2c;
+
+static void DisplayBuffer(Stream * chp, char * buff)
+{
+	int i = 0;
+	while(buff[i] != 0)
+	{
+		char c = buff[i];
+		if (c == '\n') {
+			chp->printf("\r%c", c);
+			break;
+		}
+		else
+			chp->printf("%c", c);
+		
+		i++;
+	}
+}
+
+
+static int DisplayHeap(void* pBuffer, char const* pFormatString, ...)
+{
+    char*   pStringEnd = (char*)pBuffer + strlen((char*)pBuffer);
+    va_list valist;
+    
+    va_start(valist, pFormatString);
+    
+    return vsprintf(pStringEnd, pFormatString, valist);
+}
+
+
+void heapinfo(Stream * chp)  {
+		char OutputBuffer[256];
+		chp->printf("Build Date/Time: %s %s\r\n", __DATE__, __TIME__);
+		chp->printf("Current Stack : 0x%08X\r\n", __current_sp());
+		chp->printf("Current Heap : 0x%08X\r\n", __current_pc());
+
+	  OutputBuffer[0] = '\0';
+    typedef int (*__heapprt)(void *, char const *, ...);
+    __heapstats( (__heapprt)DisplayHeap, OutputBuffer ) ;
+		chp->printf("Available Memory: ");
+		DisplayBuffer(chp, OutputBuffer);
+}
+
+char *_strtok(char *str, const char *delim, char **saveptr) 
+{
+  char *token;
+  if (str)
+    *saveptr = str;
+  token = *saveptr;
+
+  if (!token)
+    return NULL;
+
+  token += strspn(token, delim);
+  *saveptr = strpbrk(token, delim);
+  if (*saveptr)
+    *(*saveptr)++ = '\0';
+
+  return *token ? token : NULL;
+}
+
+void split( vector<string> & theStringVector,  /* Altered/returned value */
+       const  string  & theString,
+       const  string  & theDelimiter)
+{
+    size_t  start = 0, end = 0;
+    while ( end != string::npos)
+    {
+        end = theString.find( theDelimiter, start);
+
+        // If at end, use length=maxLength.  Else use length=end-start.
+        theStringVector.push_back( theString.substr( start,
+                       (end == string::npos) ? string::npos : end - start));
+
+        // If at end, use start=maxSize.  Else use start=end+delimiter.
+        start = (   ( end > (string::npos - theDelimiter.size()) )
+                  ?  string::npos  :  end + theDelimiter.size());
+    }
+}
+
+std::string trim(const std::string& str,
+                 const std::string& whitespace)
+{
+    size_t strBegin = str.find_first_not_of(whitespace);
+    if (strBegin == std::string::npos)
+        return ""; // no content
+
+    size_t strEnd = str.find_last_not_of(whitespace);
+    size_t strRange = strEnd - strBegin + 1;
+
+    return str.substr(strBegin, strRange);
+}
+
+static void transform_if_first_of_word( char& c )
+{
+    // if the previous character was a space, transform it toupper
+    if( (*(&c - sizeof(char))) == ' ')
+        c = toupper( c );
+}
+
+void capitalize_word_start(std::string & str)
+{
+	str[ 0 ] = toupper( str[ 0 ]);
+        
+  std::for_each( str.begin()+1, str.end(), transform_if_first_of_word );	
+}
+
+void set_ctrl_panel(int paneladdr, uint8_t value)
+{
+		char cmd[2];
+		uint8_t addr;
+	
+		switch(paneladdr)
+		{
+			case 0: 
+				addr = I2C_CTR_PANEL_ADDR;
+				cmd[0] = 0x12;
+				break;
+			case 1:
+				addr = I2C_CTR_PANEL_ADDR;
+				cmd[0] = 0x13;
+				break;
+			default:
+				// don't set anything for non-existing address
+				return;
+		}
+	
+		cmd[1] = value;
+		
+		i2c.write(addr, cmd, 2);
+}
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Utility.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,27 @@
+#ifndef __M_UTILITY_H__
+#define __M_UTILITY_H__
+
+#include "mbed.h"
+#include <string>
+#include <vector>
+
+#define SHELL_SWITCH 0x80
+#define CONN_LED 0x10
+
+#define I2C_CTR_PANEL_ADDR ((0x21) << 1)
+
+void heapinfo(Stream * chp);
+char *_strtok(char *str, const char *delim, char **saveptr);
+void split( vector<string> & theStringVector,  /* Altered/returned value */
+       const  string  & theString,
+       const  string  & theDelimiter);
+
+void set_ctrl_panel(int paneladdr, uint8_t value);
+
+			 
+std::string trim(const std::string& str, const std::string& whitespace = " \t");
+void capitalize_word_start(std::string & str);	
+
+#endif
+ 
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ini.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,182 @@
+/* inih -- simple .INI file parser
+
+inih is released under the New BSD license (see LICENSE.txt). Go to the project
+home page for more info:
+
+http://code.google.com/p/inih/
+
+*/
+
+#include <stdio.h>
+#include <ctype.h>
+#include <string.h>
+
+#include "ini.h"
+
+#if !INI_USE_STACK
+#include <stdlib.h>
+#endif
+
+#define MAX_SECTION 50
+#define MAX_NAME 50
+
+/* Strip whitespace chars off end of given string, in place. Return s. */
+static char* rstrip(char* s)
+{
+    char* p = s + strlen(s);
+    while (p > s && isspace((unsigned char)(*--p)))
+        *p = '\0';
+    return s;
+}
+
+/* Return pointer to first non-whitespace char in given string. */
+static char* lskip(const char* s)
+{
+    while (*s && isspace((unsigned char)(*s)))
+        s++;
+    return (char*)s;
+}
+
+/* Return pointer to first char c or ';' comment in given string, or pointer to
+   null at end of string if neither found. ';' must be prefixed by a whitespace
+   character to register as a comment. */
+static char* find_char_or_comment(const char* s, char c)
+{
+    int was_whitespace = 0;
+    while (*s && *s != c && !(was_whitespace && *s == ';')) {
+        was_whitespace = isspace((unsigned char)(*s));
+        s++;
+    }
+    return (char*)s;
+}
+
+/* Version of strncpy that ensures dest (size bytes) is null-terminated. */
+static char* strncpy0(char* dest, const char* src, size_t size)
+{
+    strncpy(dest, src, size);
+    dest[size - 1] = '\0';
+    return dest;
+}
+
+/* See documentation in header file. */
+int ini_parse_file(FILE* file,
+                   int (*handler)(void*, const char*, const char*,
+                                  const char*),
+                   void* user)
+{
+    /* Uses a fair bit of stack (use heap instead if you need to) */
+#if INI_USE_STACK
+    char line[INI_MAX_LINE];
+#else
+    char* line;
+#endif
+    char section[MAX_SECTION] = "";
+    char prev_name[MAX_NAME] = "";
+
+    char* start;
+    char* end;
+    char* name;
+    char* value;
+    int lineno = 0;
+    int error = 0;
+
+#if !INI_USE_STACK
+    line = (char*)malloc(INI_MAX_LINE);
+    if (!line) {
+        return -2;
+    }
+#endif
+
+    /* Scan through file line by line */
+    while (fgets(line, INI_MAX_LINE, file) != NULL) {
+        lineno++;
+
+        start = line;
+#if INI_ALLOW_BOM
+        if (lineno == 1 && (unsigned char)start[0] == 0xEF &&
+                           (unsigned char)start[1] == 0xBB &&
+                           (unsigned char)start[2] == 0xBF) {
+            start += 3;
+        }
+#endif
+        start = lskip(rstrip(start));
+
+        if (*start == ';' || *start == '#') {
+            /* Per Python ConfigParser, allow '#' comments at start of line */
+        }
+#if INI_ALLOW_MULTILINE
+        else if (*prev_name && *start && start > line) {
+            /* Non-black line with leading whitespace, treat as continuation
+               of previous name's value (as per Python ConfigParser). */
+            if (!handler(user, section, prev_name, start) && !error)
+                error = lineno;
+        }
+#endif
+        else if (*start == '[') {
+            /* A "[section]" line */
+            end = find_char_or_comment(start + 1, ']');
+            if (*end == ']') {
+                *end = '\0';
+                strncpy0(section, start + 1, sizeof(section));
+                *prev_name = '\0';
+            }
+            else if (!error) {
+                /* No ']' found on section line */
+                error = lineno;
+            }
+        }
+        else if (*start && *start != ';') {
+            /* Not a comment, must be a name[=:]value pair */
+            end = find_char_or_comment(start, '=');
+            if (*end != '=') {
+                end = find_char_or_comment(start, ':');
+            }
+            if (*end == '=' || *end == ':') {
+                *end = '\0';
+                name = rstrip(start);
+                value = lskip(end + 1);
+                end = find_char_or_comment(value, '\0');
+                if (*end == ';')
+                    *end = '\0';
+                rstrip(value);
+
+                /* Valid name[=:]value pair found, call handler */
+                strncpy0(prev_name, name, sizeof(prev_name));
+                if (!handler(user, section, name, value) && !error)
+                    error = lineno;
+            }
+            else if (!error) {
+                /* No '=' or ':' found on name[=:]value line */
+                error = lineno;
+            }
+        }
+
+#if INI_STOP_ON_FIRST_ERROR
+        if (error)
+            break;
+#endif
+    }
+
+#if !INI_USE_STACK
+    free(line);
+#endif
+
+    return error;
+}
+
+/* See documentation in header file. */
+int ini_parse(const char* filename,
+              int (*handler)(void*, const char*, const char*, const char*),
+              void* user)
+{
+    FILE* file;
+    int error;
+
+    file = fopen(filename, "r");
+    if (!file)
+        return -1;
+    error = ini_parse_file(file, handler, user);
+    fclose(file);
+    return error;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ini.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,78 @@
+/* inih -- simple .INI file parser
+
+inih is released under the New BSD license (see LICENSE.txt). Go to the project
+home page for more info:
+
+http://code.google.com/p/inih/
+
+*/
+
+#ifndef __INI_H__
+#define __INI_H__
+
+/* Make this header file easier to include in C++ code */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdio.h>
+
+/* Parse given INI-style file. May have [section]s, name=value pairs
+   (whitespace stripped), and comments starting with ';' (semicolon). Section
+   is "" if name=value pair parsed before any section heading. name:value
+   pairs are also supported as a concession to Python's ConfigParser.
+
+   For each name=value pair parsed, call handler function with given user
+   pointer as well as section, name, and value (data only valid for duration
+   of handler call). Handler should return nonzero on success, zero on error.
+
+   Returns 0 on success, line number of first error on parse error (doesn't
+   stop on first error), -1 on file open error, or -2 on memory allocation
+   error (only when INI_USE_STACK is zero).
+*/
+int ini_parse(const char* filename,
+              int (*handler)(void* user, const char* section,
+                             const char* name, const char* value),
+              void* user);
+
+/* Same as ini_parse(), but takes a FILE* instead of filename. This doesn't
+   close the file when it's finished -- the caller must do that. */
+int ini_parse_file(FILE* file,
+                   int (*handler)(void* user, const char* section,
+                                  const char* name, const char* value),
+                   void* user);
+
+/* Nonzero to allow multi-line value parsing, in the style of Python's
+   ConfigParser. If allowed, ini_parse() will call the handler with the same
+   name for each subsequent line parsed. */
+#ifndef INI_ALLOW_MULTILINE
+#define INI_ALLOW_MULTILINE 1
+#endif
+
+/* Nonzero to allow a UTF-8 BOM sequence (0xEF 0xBB 0xBF) at the start of
+   the file. See http://code.google.com/p/inih/issues/detail?id=21 */
+#ifndef INI_ALLOW_BOM
+#define INI_ALLOW_BOM 1
+#endif
+
+/* Nonzero to use stack, zero to use heap (malloc/free). */
+#ifndef INI_USE_STACK
+#define INI_USE_STACK 1
+#endif
+
+/* Stop parsing on first error (default is to keep parsing). */
+#ifndef INI_STOP_ON_FIRST_ERROR
+#define INI_STOP_ON_FIRST_ERROR 0
+#endif
+
+/* Maximum line length for any line in INI file. */
+#ifndef INI_MAX_LINE
+#define INI_MAX_LINE 200
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __INI_H__ */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/main.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,462 @@
+#include "mbed.h"
+#include "cmsis_os.h"
+#include "DHT.h"
+#include "SDFileSystem.h"
+#include "cc3000.h"
+#include "SPI_TFT_ILI9341.h"
+#include "Arial12x12.h"
+#include "Arial24x23.h"
+#include "Arial28x28.h"
+//#include "Arial34x40.h"
+//#include "Arial48x51.h"
+//#include "Arial35x38.h"
+#include "font_big.h"
+#include "Shell.h"
+#include "ini.h"
+#include "Utility.h"
+#include "HttpClient.h"
+#include "JsonParser.h"
+
+
+#include <vector>
+#include <string>
+#include <cstring>
+
+#include "TCPSocketConnection.h"
+#include "TCPSocketServer.h"
+
+using namespace mbed_cc3000;
+
+typedef struct
+{
+		char startupimage[30];
+    char webaddress[256];
+    float imagedelay;
+} configuration;
+
+typedef struct
+{
+	// Values read from DHT11
+	double current_temperature;
+	double current_humidity;
+	double current_dewpoint;
+	// Values read from openweathermap.com
+	int weatherid;
+	int sunrise;
+	int sunset;
+	double temperature;
+	double humidity;
+	double pressure;
+	double windspeed;
+	double clouds;
+	std::string icon;
+	std::string location;
+	std::string description;
+	
+	void debug(Stream & strm)
+	{
+		strm.printf("Weather id : [%d]\r\n", weatherid);
+		strm.printf("Current temperature: [%0.2f C]\r\n", current_temperature);
+		strm.printf("Current humidity: [%0.2f%%]\r\n", current_humidity);
+		strm.printf("Dew Point  : [%0.2f C]\r\n", current_dewpoint);
+		strm.printf("Temperature: [%0.2f C]\r\n", temperature);
+		strm.printf("Humidity   : [%0.2f%%]\r\n", humidity);
+		strm.printf("Pressure   : [%0.2fhpa]\r\n", pressure);
+		strm.printf("Wind Speed : [%%0.2f]\r\n", windspeed);
+		strm.printf("Cloud Coverage: [%0.2f]\r\n", clouds);
+		strm.printf("Location   : [%s]\r\n", location.c_str());
+		strm.printf("Description: [%s]\r\n", description.c_str());
+		strm.printf("Icon id    : [%s]\r\n", icon.c_str());
+	}
+} weather_info;
+
+/* Define ALL Hardware used here and their pin configuration */
+Serial pc(USBTX, USBRX); // tx, rx
+DHT dht(D9, DHT11);
+//DigitalOut conLed(D6);		// PB_10
+DigitalIn shellSwitch(D6); // PB_0 (normally pulled high)
+I2C i2c(I2C_SDA, I2C_SCL); // SDA, SCL
+SDFileSystem sdcard(PB_15, PB_14, PB_13, PB_1, "sd"); // mosi, miso, sclk, cs, name
+// the TFT is connected to SPI pin 5-7
+SPI_TFT_ILI9341 TFT(PC_12, PC_11, PC_10, PC_0, PC_2, PC_3,"TFT"); 	// mosi, miso, sclk, cs, reset, dc
+DigitalOut lcdOn(PC_1);
+cc3000 wifi(PA_10, PA_8, PB_6, SPI(PA_7, PA_6, PA_5), "dlink-B15C", "fricu35860", WPA, false); //irq, en, cs, spi, irq-port
+
+
+/** Globals **/
+std::vector<std::string> images;
+char webdata[1024];
+configuration cfg;
+weather_info winfo;
+HeaderInfo info;
+
+
+static int confighandler(void* user, const char* section, const char* name,
+                   const char* value)
+{
+    configuration* pconfig = (configuration*)user;
+
+    #define MATCH(s, n) strcmp(section, s) == 0 && strcmp(name, n) == 0
+    if (MATCH("rotator", "imagedelay")) {
+        pconfig->imagedelay = atof(value);
+    } else if (MATCH("weather", "webaddress")) {
+				strncpy(pconfig->webaddress, value, sizeof(pconfig->webaddress));
+		} else if (MATCH("boot", "startupimage")) {
+			  strncpy(pconfig->startupimage, value, sizeof(pconfig->startupimage));
+    } else {
+        return 0;  /* unknown section/name, error */
+    }
+    return 1;
+}
+
+/**
+ *  \brief Setup interrupt priorities for Nucleo board
+ *  \param none
+ *  \return none
+ */
+void init() 
+{
+	// First and last IRQ defined in stm32f401xe.h
+  int irqnum;
+  for(irqnum = SysTick_IRQn ; irqnum < SPI4_IRQn + 1 ; irqnum++)
+      NVIC_SetPriority((IRQn_Type)irqnum, 0x04);
+	
+  NVIC_SetPriority(SPI1_IRQn, 0x0);
+  NVIC_SetPriority(FPU_IRQn, 0x1);
+	NVIC_SetPriority(SPI2_IRQn, 0x2);
+	NVIC_SetPriority(SPI3_IRQn, 0x02);
+  NVIC_SetPriority(SysTick_IRQn, 0x3);	
+}
+
+/**
+ * \brief Initialize CC3000
+ * \param none
+ * \return void
+ **/
+void init_cc3000()
+{
+	printf("Loading wifi startup settings ...\r\n");
+	
+  printf("Initializing cc3000 wifi ...\r\n");
+  wifi.init();
+	printf("Connecting to AP ...\r\n");
+  if (wifi.connect() == -1) {
+     printf("Failed to connect. Please verify connection details and try again. \r\n");
+  } else {
+     printf("IP address: %s \r\n", wifi.getIPAddress());
+		 printf("Gateway address: %s \r\n", wifi.getGateway());
+		 set_ctrl_panel(1, 1);
+  }
+}
+
+/**
+ * \brief Initialize LCD
+ * \param none
+ * \return void
+ **/
+void init_LCD()
+{
+		printf("Initializing LCD Screen ...\r\n");
+	
+		lcdOn = 1;
+	
+		TFT.claim(stdout);  
+    TFT.set_orientation(1);
+    TFT.background(Black);    // set background to black
+    TFT.foreground(White);    // set chars to white
+    TFT.cls();                // clear the screen
+ 
+
+    TFT.set_font((unsigned char*) Arial12x12);
+    TFT.locate(0,0);
+
+}
+/**
+ * \brief Initialize switch/led panel on I2C bus
+ * \param none
+ * \return void
+ **/
+void init_i2cpanel()
+{
+		char cmd[2];
+		// Setup direction reg for panel address 1
+	  cmd[0] = 0x00; // Last bit is input
+		cmd[1] = 0x00;
+		// Write to the command register
+		i2c.write(I2C_CTR_PANEL_ADDR, cmd, 2);
+	
+		// Setup direction reg for panel address 2
+		cmd[0] = 0x01;
+		cmd[1] = 0x00;
+		
+		i2c.write(I2C_CTR_PANEL_ADDR, cmd, 2);
+
+}
+
+/**
+ * \brief Counter thread to test rtos
+ * \param arg arguments to the thread
+ * \return none
+ **/
+void counter_thread(void const *args) 
+{
+		uint8_t count;
+
+    while (true) 
+		{
+			set_ctrl_panel(0, count);
+			
+			count++;
+		
+      osDelay(1000);
+    }
+}
+osThreadDef(counter_thread, osPriorityNormal, DEFAULT_STACK_SIZE);
+
+
+int find_images(const char * root, const char * ext)
+{
+	DIR * dp;
+	struct dirent * dirp;
+	FILINFO fileInfo;
+
+	dp = opendir(root);			
+	while((dirp = readdir(dp)) != NULL)
+	{
+		if (sdcard.stat(dirp->d_name, &fileInfo) == 0)
+		{
+			if (!(fileInfo.fattrib & AM_DIR ))
+			{
+				std::string filename = dirp->d_name;
+				std::size_t found = filename.find(ext);
+				if (found!=std::string::npos)
+				{
+					std::string fullpathname = root;
+					fullpathname += "/";
+					fullpathname += filename;
+					images.push_back(fullpathname);
+				}
+			}
+		}
+	}
+	closedir(dp);
+	
+	return images.size();
+}
+
+bool get_current_weather()
+{
+	  // First fetch current weather conditions from sensor
+		pc.printf("Getting current conditions...\r\n");
+	  if(dht.readData() == ERROR_NONE)
+		{
+			float temperature = dht.ReadTemperature(CELCIUS);
+			float humidity = dht.ReadHumidity();
+			float dewpoint = dht.CalcdewPoint(temperature, humidity);
+			
+			winfo.current_temperature = temperature;
+			winfo.current_humidity = humidity;
+			winfo.current_dewpoint = dewpoint;
+			
+			pc.printf("Temperature : %.2f\r\n", temperature);
+			pc.printf("Humidity : %.2f\r\n", humidity);
+			pc.printf("Dew Point : %.2f\r\n", dewpoint);
+			
+			return true;
+		}	else
+			return false;
+}
+
+bool get_weather_info()
+{
+		bool retval = false;
+		HttpClient client("test.com");
+			
+		memset(webdata, 0, sizeof(webdata));
+		
+		// Fetch page from openweather
+		pc.printf("\r\nTrying to fetch page [%s]... \r\n", cfg.webaddress);
+		int ret = client.get(cfg.webaddress, webdata, sizeof(webdata), info);
+		if (ret > 0)  
+		{
+			using namespace JSON;
+			pc.printf("Page fetched successfully - read %d characters \r\n", strlen(webdata));
+			pc.printf("Web Data [%s]\r\n", webdata);
+			
+			MVJSONReader reader(webdata);
+			// pc.printf("Result: %s \r\n", webdata);
+			if (reader.root->hasField("sys"))
+			{
+					winfo.sunrise = reader.root->getField("sys")->getFieldInt("sunrise");
+					winfo.sunset = reader.root->getField("sys")->getFieldInt("sunset");
+          winfo.location = reader.root->getFieldString("name");
+					winfo.temperature = reader.root->getField("main")->getFieldDouble("temp") - 273.15;
+					winfo.pressure = reader.root->getField("main")->getFieldDouble("pressure");
+					winfo.humidity = reader.root->getField("main")->getFieldDouble("humidity");
+					winfo.windspeed = reader.root->getField("wind")->getFieldDouble("speed");
+					winfo.clouds = reader.root->getField("clouds")->getFieldDouble("all");
+					if (reader.root->getField("weather") != NULL)
+            if (reader.root->getField("weather")->size() > 0)
+            {
+                // we take only first element from list
+                winfo.weatherid = reader.root->getField("weather")->at(0)->getFieldInt("id");
+                winfo.icon = reader.root->getField("weather")->at(0)->getFieldString("icon");
+                winfo.description = reader.root->getField("weather")->at(0)->getFieldString("description");
+            }
+					retval = true;
+			}	
+		}else
+			retval = false;
+		
+		return retval;
+}
+
+// Update LCD display based on weather info		
+void update_lcd(bool update_locale)
+{
+	
+		// TFT.cls();
+		if (get_current_weather())
+		{
+			// Use large fonts to display temperature
+			TFT.background(Black);
+			TFT.foreground(White);
+			TFT.locate(170, 120);
+			TFT.set_font((unsigned char *) Neu42x35);
+			TFT.printf("%.0f C",winfo.temperature);
+
+			// At the bottom
+			TFT.fillrect(0,185,320,216,Blue);
+			TFT.background(Blue);
+			TFT.foreground(White);
+			TFT.set_font((unsigned char*) Arial28x28);
+			TFT.locate(0,187);
+			TFT.printf("%.0f%% Humidity", 
+				winfo.current_humidity);
+			
+			TFT.locate(0, 218);
+			TFT.set_font((unsigned char *) Arial12x12);
+			TFT.background(Black);
+			TFT.foreground(White);
+			TFT.printf("Dew Point : %0.2fC", winfo.current_dewpoint);
+		}
+		
+		if (update_locale)
+		{
+			// Fill banner with white
+			TFT.background(White);
+			TFT.foreground(Black);
+			TFT.fillrect(0,0,320,100, White);
+			
+			// Load the graphic icon 
+			std::string filename = "/sd/icons/" + winfo.icon + ".bmp";
+			TFT.BMP_16(0,10, filename.c_str());
+			
+			// Fill the header - top most of LCD with info
+			TFT.locate(100,20);
+			TFT.set_font((unsigned char *) Arial28x28);
+			TFT.background(White);    // set background to black
+			TFT.foreground(Black);    // set chars to white			
+
+			TFT.printf("%s", winfo.location.c_str());
+			TFT.locate(100,60);
+			TFT.set_font((unsigned char *) Arial12x12);
+			capitalize_word_start(winfo.description);
+			TFT.printf("%s", winfo.description.c_str());
+		}
+			
+	
+}
+
+static const ShellCommand cmds[] = {
+	{"ls", cmd_ls},
+	{"load", cmd_load},
+	{"sensor", cmd_sensor},
+	{"roll", cmd_rollimages},
+	{NULL, NULL}
+};
+
+static const ShellConfig shell_cfg1 = {
+  (Serial *) &pc,
+  (ShellCommand *) cmds
+};
+
+int main() 
+{
+   
+	// Set NVIC interrupt priorities
+	init();
+	pc.baud(115200);
+	i2c.frequency(100000);
+	init_i2cpanel();
+	
+	bool startShell = (shellSwitch.read() == 0);
+	pc.printf("Starting shell: [%s]\r\n", startShell ? "Yes":"No");
+
+	int numbmps = find_images("/sd", ".bmp");
+	pc.printf("Found %d bmps in directory /sd\r\n", numbmps);
+	// Read the configuration file
+	pc.printf("Reading /sd/config.ini ...\r\n");
+  if (ini_parse("/sd/config.ini", confighandler, &cfg) < 0) {
+		// Initialize the cfg 
+		strcpy(cfg.webaddress, "http://192.168.1.75/hmap/booksearch.html");
+		strcpy(cfg.startupimage, "boot.bmp");
+		cfg.imagedelay = 1000;
+  }
+	
+	pc.printf("Initializing hardware ...\r\n");
+	init_cc3000();
+	
+	pc.printf("Starting counter leds ....\r\n");
+	osThreadCreate(osThread(counter_thread), NULL);
+	
+	init_LCD();	
+
+	
+	if (startShell)
+	{
+		pc.printf("Starting debug shell ...\r\n");
+		shellStart(&shell_cfg1);
+	}
+	else
+	{
+//		pc.printf("Starting image rotator ...\r\n");
+	  unsigned int count = 0;
+		bool update_weather = true;
+		while(true)
+		{
+				// If we have an RTC, we can detect new day
+				if (update_weather && get_weather_info())
+				{ 
+					winfo.debug(pc);
+					update_lcd(true);
+        }
+				else
+					update_lcd(false);
+	
+        wait(5.0);
+				count++;
+				if ((count % 10) == 0)
+					update_weather = true;
+				else
+					update_weather = false;
+				
+		
+			  //heapinfo(&pc);
+/*		
+			for(std::vector<std::string>::iterator i = images.begin();
+				i != images.end(); i++)
+			{
+				pc.printf("Loading image %s...\r\n", (*i).c_str());
+				TFT.cls();
+				int err = TFT.BMP_16(0,0, (*i).c_str());
+				if (err != 1) TFT.printf(" - Err: %d", err);
+			
+				wait(1.0);
+				heapinfo(&pc);
+			}
+*/						
+		}
+	}
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtos/Mail.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,110 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MAIL_H
+#define MAIL_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/** The Mail class allow to control, send, receive, or wait for mail.
+ A mail is a memory block that is send to a thread or interrupt service routine.
+  @tparam  T         data type of a single message element.
+  @tparam  queue_sz  maximum number of messages in queue.
+*/
+template<typename T, uint32_t queue_sz>
+class Mail {
+public:
+    /** Create and Initialise Mail queue. */
+    Mail() {
+    #ifdef CMSIS_OS_RTX
+        memset(_mail_q, 0, sizeof(_mail_q));
+        _mail_p[0] = _mail_q;
+
+        memset(_mail_m, 0, sizeof(_mail_m));
+        _mail_p[1] = _mail_m;
+
+        _mail_def.pool = _mail_p;
+        _mail_def.queue_sz = queue_sz;
+        _mail_def.item_sz = sizeof(T);
+    #endif
+        _mail_id = osMailCreate(&_mail_def, NULL);
+    }
+
+    /** Allocate a memory block of type T
+      @param   millisec  timeout value or 0 in case of no time-out. (default: 0).
+      @return  pointer to memory block that can be filled with mail or NULL in case error.
+    */
+    T* alloc(uint32_t millisec=0) {
+        return (T*)osMailAlloc(_mail_id, millisec);
+    }
+
+    /** Allocate a memory block of type T and set memory block to zero.
+      @param   millisec  timeout value or 0 in case of no time-out.  (default: 0).
+      @return  pointer to memory block that can be filled with mail or NULL in case error.
+    */
+    T* calloc(uint32_t millisec=0) {
+        return (T*)osMailCAlloc(_mail_id, millisec);
+    }
+
+    /** Put a mail in the queue.
+      @param   mptr  memory block previously allocated with Mail::alloc or Mail::calloc.
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus put(T *mptr) {
+        return osMailPut(_mail_id, (void*)mptr);
+    }
+
+    /** Get a mail from a queue.
+      @param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever).
+      @return  event that contains mail information or error code.
+    */
+    osEvent get(uint32_t millisec=osWaitForever) {
+        return osMailGet(_mail_id, millisec);
+    }
+
+    /** Free a memory block from a mail.
+      @param   mptr  pointer to the memory block that was obtained with Mail::get.
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus free(T *mptr) {
+        return osMailFree(_mail_id, (void*)mptr);
+    }
+
+private:
+    osMailQId    _mail_id;
+    osMailQDef_t _mail_def;
+#ifdef CMSIS_OS_RTX
+    uint32_t     _mail_q[4+(queue_sz)];
+    uint32_t     _mail_m[3+((sizeof(T)+3)/4)*(queue_sz)];
+    void        *_mail_p[2];
+#endif
+};
+
+}
+
+#endif
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtos/MemoryPool.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,83 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MEMORYPOOL_H
+#define MEMORYPOOL_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/** Define and manage fixed-size memory pools of objects of a given type.
+  @tparam  T         data type of a single object (element).
+  @tparam  queue_sz  maximum number of objects (elements) in the memory pool.
+*/
+template<typename T, uint32_t pool_sz>
+class MemoryPool {
+public:
+    /** Create and Initialize a memory pool. */
+    MemoryPool() {
+    #ifdef CMSIS_OS_RTX
+        memset(_pool_m, 0, sizeof(_pool_m));
+        _pool_def.pool = _pool_m;
+
+        _pool_def.pool_sz = pool_sz;
+        _pool_def.item_sz =  sizeof(T);
+    #endif
+        _pool_id = osPoolCreate(&_pool_def);
+    }
+
+    /** Allocate a memory block of type T from a memory pool.
+      @return  address of the allocated memory block or NULL in case of no memory available.
+    */
+    T* alloc(void) {
+        return (T*)osPoolAlloc(_pool_id);
+    }
+
+    /** Allocate a memory block of type T from a memory pool and set memory block to zero.
+      @return  address of the allocated memory block or NULL in case of no memory available.
+    */
+    T* calloc(void) {
+        return (T*)osPoolCAlloc(_pool_id);
+    }
+
+    /** Return an allocated memory block back to a specific memory pool.
+      @param   address of the allocated memory block that is returned to the memory pool.
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus free(T *block) {
+        return osPoolFree(_pool_id, (void*)block);
+    }
+
+private:
+    osPoolId    _pool_id;
+    osPoolDef_t _pool_def;
+#ifdef CMSIS_OS_RTX
+    uint32_t    _pool_m[3+((sizeof(T)+3)/4)*(pool_sz)];
+#endif
+};
+
+}
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtos/Mutex.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "Mutex.h"
+
+#include <string.h>
+#include "mbed_error.h"
+
+namespace rtos {
+
+Mutex::Mutex() {
+#ifdef CMSIS_OS_RTX
+    memset(_mutex_data, 0, sizeof(_mutex_data));
+    _osMutexDef.mutex = _mutex_data;
+#endif
+    _osMutexId = osMutexCreate(&_osMutexDef);
+    if (_osMutexId == NULL) {
+        error("Error initializing the mutex object\n");
+    }
+}
+
+osStatus Mutex::lock(uint32_t millisec) {
+    return osMutexWait(_osMutexId, millisec);
+}
+
+bool Mutex::trylock() {
+    return (osMutexWait(_osMutexId, 0) == osOK);
+}
+
+osStatus Mutex::unlock() {
+    return osMutexRelease(_osMutexId);
+}
+
+Mutex::~Mutex() {
+    osMutexDelete(_osMutexId);
+}
+
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtos/Mutex.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MUTEX_H
+#define MUTEX_H
+
+#include <stdint.h>
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/** The Mutex class is used to synchronise the execution of threads.
+ This is for example used to protect access to a shared resource.
+*/
+class Mutex {
+public:
+    /** Create and Initialize a Mutex object */
+    Mutex();
+
+    /** Wait until a Mutex becomes available.
+      @param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever)
+      @return  status code that indicates the execution status of the function.
+     */
+    osStatus lock(uint32_t millisec=osWaitForever);
+
+    /** Try to lock the mutex, and return immediately
+      @return  true if the mutex was acquired, false otherwise.
+     */
+    bool trylock();
+
+    /** Unlock the mutex that has previously been locked by the same thread
+      @return  status code that indicates the execution status of the function.
+     */
+    osStatus unlock();
+
+    ~Mutex();
+
+private:
+    osMutexId _osMutexId;
+    osMutexDef_t _osMutexDef;
+#ifdef CMSIS_OS_RTX
+    int32_t _mutex_data[3];
+#endif
+};
+
+}
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtos/Queue.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "cmsis_os.h"
+#include "mbed_error.h"
+
+namespace rtos {
+
+/** The Queue class allow to control, send, receive, or wait for messages.
+ A message can be a integer or pointer value  to a certain type T that is send
+ to a thread or interrupt service routine.
+  @tparam  T         data type of a single message element.
+  @tparam  queue_sz  maximum number of messages in queue.
+*/
+template<typename T, uint32_t queue_sz>
+class Queue {
+public:
+    /** Create and initialise a message Queue. */
+    Queue() {
+    #ifdef CMSIS_OS_RTX
+        memset(_queue_q, 0, sizeof(_queue_q));
+        _queue_def.pool = _queue_q;
+        _queue_def.queue_sz = queue_sz;
+    #endif
+        _queue_id = osMessageCreate(&_queue_def, NULL);
+        if (_queue_id == NULL) {
+            error("Error initialising the queue object\n");
+        }
+    }
+
+    /** Put a message in a Queue.
+      @param   data      message pointer.
+      @param   millisec  timeout value or 0 in case of no time-out. (default: 0)
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus put(T* data, uint32_t millisec=0) {
+        return osMessagePut(_queue_id, (uint32_t)data, millisec);
+    }
+
+    /** Get a message or Wait for a message from a Queue.
+      @param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever).
+      @return  event information that includes the message and the status code.
+    */
+    osEvent get(uint32_t millisec=osWaitForever) {
+        return osMessageGet(_queue_id, millisec);
+    }
+
+private:
+    osMessageQId    _queue_id;
+    osMessageQDef_t _queue_def;
+#ifdef CMSIS_OS_RTX
+    uint32_t        _queue_q[4+(queue_sz)];
+#endif
+};
+
+}
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtos/RtosTimer.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "RtosTimer.h"
+
+#include <string.h>
+
+#include "cmsis_os.h"
+#include "mbed_error.h"
+
+namespace rtos {
+
+RtosTimer::RtosTimer(void (*periodic_task)(void const *argument), os_timer_type type, void *argument) {
+#ifdef CMSIS_OS_RTX
+    _timer.ptimer = periodic_task;
+
+    memset(_timer_data, 0, sizeof(_timer_data));
+    _timer.timer = _timer_data;
+#endif
+    _timer_id = osTimerCreate(&_timer, type, argument);
+}
+
+osStatus RtosTimer::start(uint32_t millisec) {
+    return osTimerStart(_timer_id, millisec);
+}
+
+osStatus RtosTimer::stop(void) {
+    return osTimerStop(_timer_id);
+}
+
+RtosTimer::~RtosTimer() {
+    osTimerDelete(_timer_id);
+}
+
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtos/RtosTimer.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,72 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef RTOS_TIMER_H
+#define RTOS_TIMER_H
+
+#include <stdint.h>
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/** The RtosTimer class allow creating and and controlling of timer functions in the system.
+ A timer function is called when a time period expires whereby both on-shot and
+ periodic timers are possible. A timer can be started, restarted, or stopped.
+
+ Timers are handled in the thread osTimerThread.
+ Callback functions run under control of this thread and may use CMSIS-RTOS API calls.
+*/
+class RtosTimer {
+public:
+    /** Create and Start timer.
+      @param   task      name of the timer call back function.
+      @param   type      osTimerOnce for one-shot or osTimerPeriodic for periodic behaviour. (default: osTimerPeriodic)
+      @param   argument  argument to the timer call back function. (default: NULL)
+    */
+    RtosTimer(void (*task)(void const *argument),
+          os_timer_type type=osTimerPeriodic,
+          void *argument=NULL);
+
+    /** Stop the timer.
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus stop(void);
+
+    /** start a timer.
+      @param   millisec  time delay value of the timer.
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus start(uint32_t millisec);
+
+    ~RtosTimer();
+
+private:
+    osTimerId _timer_id;
+    osTimerDef_t _timer;
+#ifdef CMSIS_OS_RTX
+    uint32_t _timer_data[5];
+#endif
+};
+
+}
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtos/Semaphore.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "Semaphore.h"
+
+#include <string.h>
+
+namespace rtos {
+
+Semaphore::Semaphore(int32_t count) {
+#ifdef CMSIS_OS_RTX
+    memset(_semaphore_data, 0, sizeof(_semaphore_data));
+    _osSemaphoreDef.semaphore = _semaphore_data;
+#endif
+    _osSemaphoreId = osSemaphoreCreate(&_osSemaphoreDef, count);
+}
+
+int32_t Semaphore::wait(uint32_t millisec) {
+    return osSemaphoreWait(_osSemaphoreId, millisec);
+}
+
+osStatus Semaphore::release(void) {
+    return osSemaphoreRelease(_osSemaphoreId);
+}
+
+Semaphore::~Semaphore() {
+    osSemaphoreDelete(_osSemaphoreId);
+}
+
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtos/Semaphore.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#include <stdint.h>
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/** The Semaphore class is used to manage and protect access to a set of shared resources. */
+class Semaphore {
+public:
+    /** Create and Initialize a Semaphore object used for managing resources.
+      @param number of available resources; maximum index value is (count-1).
+    */
+    Semaphore(int32_t count);
+
+    /** Wait until a Semaphore resource becomes available.
+      @param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever).
+      @return  number of available tokens, or -1 in case of incorrect parameters
+    */
+    int32_t wait(uint32_t millisec=osWaitForever);
+
+    /** Release a Semaphore resource that was obtain with Semaphore::wait.
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus release(void);
+
+    ~Semaphore();
+
+private:
+    osSemaphoreId _osSemaphoreId;
+    osSemaphoreDef_t _osSemaphoreDef;
+#ifdef CMSIS_OS_RTX
+    uint32_t _semaphore_data[2];
+#endif
+};
+
+}
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtos/Thread.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,91 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "Thread.h"
+
+#include "mbed_error.h"
+
+namespace rtos {
+
+Thread::Thread(void (*task)(void const *argument), void *argument,
+        osPriority priority, uint32_t stack_size, unsigned char *stack_pointer) {
+#ifdef CMSIS_OS_RTX
+    _thread_def.pthread = task;
+    _thread_def.tpriority = priority;
+    _thread_def.stacksize = stack_size;
+    if (stack_pointer != NULL) {
+        _thread_def.stack_pointer = stack_pointer;
+        _dynamic_stack = false;
+    } else {
+        _thread_def.stack_pointer = new unsigned char[stack_size];
+        if (_thread_def.stack_pointer == NULL)
+            error("Error allocating the stack memory\n");
+        _dynamic_stack = true;
+    }
+#endif
+    _tid = osThreadCreate(&_thread_def, argument);
+}
+
+osStatus Thread::terminate() {
+    return osThreadTerminate(_tid);
+}
+
+osStatus Thread::set_priority(osPriority priority) {
+    return osThreadSetPriority(_tid, priority);
+}
+
+osPriority Thread::get_priority() {
+    return osThreadGetPriority(_tid);
+}
+
+int32_t Thread::signal_set(int32_t signals) {
+    return osSignalSet(_tid, signals);
+}
+
+Thread::State Thread::get_state() {
+    return ((State)_thread_def.tcb.state);
+}
+
+osEvent Thread::signal_wait(int32_t signals, uint32_t millisec) {
+    return osSignalWait(signals, millisec);
+}
+
+osStatus Thread::wait(uint32_t millisec) {
+    return osDelay(millisec);
+}
+
+osStatus Thread::yield() {
+    return osThreadYield();
+}
+
+osThreadId Thread::gettid() {
+    return osThreadGetId();
+}
+
+Thread::~Thread() {
+    terminate();
+    if (_dynamic_stack) {
+        delete[] (_thread_def.stack_pointer);
+    }
+}
+
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtos/Thread.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,119 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef THREAD_H
+#define THREAD_H
+
+#include <stdint.h>
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/** The Thread class allow defining, creating, and controlling thread functions in the system. */
+class Thread {
+public:
+    /** Create a new thread, and start it executing the specified function.
+      @param   task           function to be executed by this thread.
+      @param   argument       pointer that is passed to the thread function as start argument. (default: NULL).
+      @param   priority       initial priority of the thread function. (default: osPriorityNormal).
+      @param   stack_size      stack size (in bytes) requirements for the thread function. (default: DEFAULT_STACK_SIZE).
+      @param   stack_pointer  pointer to the stack area to be used by this thread (default: NULL).
+    */
+    Thread(void (*task)(void const *argument), void *argument=NULL,
+           osPriority priority=osPriorityNormal,
+           uint32_t stack_size=DEFAULT_STACK_SIZE,
+           unsigned char *stack_pointer=NULL);
+
+    /** Terminate execution of a thread and remove it from Active Threads
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus terminate();
+
+    /** Set priority of an active thread
+      @param   priority  new priority value for the thread function.
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus set_priority(osPriority priority);
+
+    /** Get priority of an active thread
+      @return  current priority value of the thread function.
+    */
+    osPriority get_priority();
+
+    /** Set the specified Signal Flags of an active thread.
+      @param   signals  specifies the signal flags of the thread that should be set.
+      @return  previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+    */
+    int32_t signal_set(int32_t signals);
+
+    /** State of the Thread */
+    enum State {
+        Inactive,           /**< Not created or terminated */
+        Ready,              /**< Ready to run */
+        Running,            /**< Running */
+        WaitingDelay,       /**< Waiting for a delay to occur */
+        WaitingInterval,    /**< Waiting for an interval to occur */
+        WaitingOr,          /**< Waiting for one event in a set to occur */
+        WaitingAnd,         /**< Waiting for multiple events in a set to occur */
+        WaitingSemaphore,   /**< Waiting for a semaphore event to occur */
+        WaitingMailbox,     /**< Waiting for a mailbox event to occur */
+        WaitingMutex,       /**< Waiting for a mutex event to occur */
+    };
+
+    /** State of this Thread
+      @return  the State of this Thread
+    */
+    State get_state();
+
+    /** Wait for one or more Signal Flags to become signaled for the current RUNNING thread.
+      @param   signals   wait until all specified signal flags set or 0 for any single signal flag.
+      @param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever).
+      @return  event flag information or error code.
+    */
+    static osEvent signal_wait(int32_t signals, uint32_t millisec=osWaitForever);
+
+    /** Wait for a specified time period in millisec:
+      @param   millisec  time delay value
+      @return  status code that indicates the execution status of the function.
+    */
+    static osStatus wait(uint32_t millisec);
+
+    /** Pass control to next thread that is in state READY.
+      @return  status code that indicates the execution status of the function.
+    */
+    static osStatus yield();
+
+    /** Get the thread id of the current running thread.
+      @return  thread ID for reference by other functions or NULL in case of error.
+    */
+    static osThreadId gettid();
+
+    virtual ~Thread();
+
+private:
+    osThreadId _tid;
+    osThreadDef_t _thread_def;
+    bool _dynamic_stack;
+};
+
+}
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtos/rtos.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,36 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef RTOS_H
+#define RTOS_H
+
+#include "Thread.h"
+#include "Mutex.h"
+#include "RtosTimer.h"
+#include "Semaphore.h"
+#include "Mail.h"
+#include "MemoryPool.h"
+#include "Queue.h"
+
+using namespace rtos;
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/HAL_CM.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,171 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    HAL_CM.C
+ *      Purpose: Hardware Abstraction Layer for Cortex-M
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Conf.h"
+#include "rt_HAL_CM.h"
+
+
+/*----------------------------------------------------------------------------
+ *      Global Variables
+ *---------------------------------------------------------------------------*/
+
+#ifdef DBG_MSG
+BIT dbg_msg;
+#endif
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_init_stack ---------------------------------*/
+
+void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
+  /* Prepare TCB and saved context for a first time start of a task. */
+  U32 *stk,i,size;
+
+  /* Prepare a complete interrupt frame for first task start */
+  size = p_TCB->priv_stack >> 2;
+
+  /* Write to the top of stack. */
+  stk = &p_TCB->stack[size];
+
+  /* Auto correct to 8-byte ARM stack alignment. */
+  if ((U32)stk & 0x04) {
+    stk--;
+  }
+
+  stk -= 16;
+
+  /* Default xPSR and initial PC */
+  stk[15] = INITIAL_xPSR;
+  stk[14] = (U32)task_body;
+
+  /* Clear R4-R11,R0-R3,R12,LR registers. */
+  for (i = 0; i < 14; i++) {
+    stk[i] = 0;
+  }
+
+  /* Assign a void pointer to R0. */
+  stk[8] = (U32)p_TCB->msg;
+
+  /* Initial Task stack pointer. */
+  p_TCB->tsk_stack = (U32)stk;
+
+  /* Task entry point. */
+  p_TCB->ptask = task_body;
+
+  /* Set a magic word for checking of stack overflow.
+   For the main thread (ID: 0x01) the stack is in a memory area shared with the
+   heap, therefore the last word of the stack is a moving target.
+   We want to do stack/heap collision detection instead.
+  */
+  if (p_TCB->task_id != 0x01)
+      p_TCB->stack[0] = MAGIC_WORD;
+}
+
+
+/*--------------------------- rt_ret_val ----------------------------------*/
+
+static __inline U32 *rt_ret_regs (P_TCB p_TCB) {
+  /* Get pointer to task return value registers (R0..R3) in Stack */
+#if (__TARGET_FPU_VFP)
+  if (p_TCB->stack_frame) {
+    /* Extended Stack Frame: R4-R11,S16-S31,R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR */
+    return (U32 *)(p_TCB->tsk_stack + 8*4 + 16*4);
+  } else {
+    /* Basic Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */
+    return (U32 *)(p_TCB->tsk_stack + 8*4);
+  }
+#else
+  /* Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */
+  return (U32 *)(p_TCB->tsk_stack + 8*4);
+#endif
+}
+
+void rt_ret_val (P_TCB p_TCB, U32 v0) {
+  U32 *ret;
+
+  ret = rt_ret_regs(p_TCB);
+  ret[0] = v0;
+}
+
+void rt_ret_val2(P_TCB p_TCB, U32 v0, U32 v1) {
+  U32 *ret;
+
+  ret = rt_ret_regs(p_TCB);
+  ret[0] = v0;
+  ret[1] = v1;
+}
+
+
+/*--------------------------- dbg_init --------------------------------------*/
+
+#ifdef DBG_MSG
+void dbg_init (void) {
+  if ((DEMCR & DEMCR_TRCENA)     &&
+      (ITM_CONTROL & ITM_ITMENA) &&
+      (ITM_ENABLE & (1UL << 31))) {
+    dbg_msg = __TRUE;
+  }
+}
+#endif
+
+/*--------------------------- dbg_task_notify -------------------------------*/
+
+#ifdef DBG_MSG
+void dbg_task_notify (P_TCB p_tcb, BOOL create) {
+  while (ITM_PORT31_U32 == 0);
+  ITM_PORT31_U32 = (U32)p_tcb->ptask;
+  while (ITM_PORT31_U32 == 0);
+  ITM_PORT31_U16 = (create << 8) | p_tcb->task_id;
+}
+#endif
+
+/*--------------------------- dbg_task_switch -------------------------------*/
+
+#ifdef DBG_MSG
+void dbg_task_switch (U32 task_id) {
+  while (ITM_PORT31_U32 == 0);
+  ITM_PORT31_U8 = task_id;
+}
+#endif
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/RTX_CM_lib.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,433 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RTX_CM_LIB.H
+ *      Purpose: RTX Kernel System Configuration
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+#include "mbed_error.h"
+
+#if   defined (__CC_ARM)
+#pragma O3
+#define __USED __attribute__((used))
+#elif defined (__GNUC__)
+#pragma GCC optimize ("O3")
+#define __USED __attribute__((used))
+#elif defined (__ICCARM__)
+#define __USED __root
+#endif
+
+
+/*----------------------------------------------------------------------------
+ *      Definitions
+ *---------------------------------------------------------------------------*/
+
+#define _declare_box(pool,size,cnt)  uint32_t pool[(((size)+3)/4)*(cnt) + 3]
+#define _declare_box8(pool,size,cnt) uint64_t pool[(((size)+7)/8)*(cnt) + 2]
+
+#define OS_TCB_SIZE     48
+#define OS_TMR_SIZE     8
+
+#if defined (__CC_ARM) && !defined (__MICROLIB)
+
+typedef void    *OS_ID;
+typedef uint32_t OS_TID;
+typedef uint32_t OS_MUT[3];
+typedef uint32_t OS_RESULT;
+
+#define runtask_id()    rt_tsk_self()
+#define mutex_init(m)   rt_mut_init(m)
+#define mutex_wait(m)   os_mut_wait(m,0xFFFF)
+#define mutex_rel(m)    os_mut_release(m)
+
+extern OS_TID    rt_tsk_self    (void);
+extern void      rt_mut_init    (OS_ID mutex);
+extern OS_RESULT rt_mut_release (OS_ID mutex);
+extern OS_RESULT rt_mut_wait    (OS_ID mutex, uint16_t timeout);
+
+#define os_mut_wait(mutex,timeout) _os_mut_wait((uint32_t)rt_mut_wait,mutex,timeout)
+#define os_mut_release(mutex)      _os_mut_release((uint32_t)rt_mut_release,mutex)
+
+OS_RESULT _os_mut_release (uint32_t p, OS_ID mutex)                   __svc_indirect(0);
+OS_RESULT _os_mut_wait    (uint32_t p, OS_ID mutex, uint16_t timeout) __svc_indirect(0);
+
+#endif
+
+
+/*----------------------------------------------------------------------------
+ *      Global Variables
+ *---------------------------------------------------------------------------*/
+
+#if (OS_TIMERS != 0)
+#define OS_TASK_CNT (OS_TASKCNT + 1)
+#else
+#define OS_TASK_CNT  OS_TASKCNT
+#endif
+
+uint16_t const os_maxtaskrun = OS_TASK_CNT;
+uint32_t const os_rrobin     = (OS_ROBIN << 16) | OS_ROBINTOUT;
+uint32_t const os_trv        = OS_TRV;
+uint8_t  const os_flags      = OS_RUNPRIV;
+
+/* Export following defines to uVision debugger. */
+__USED uint32_t const os_clockrate = OS_TICK;
+__USED uint32_t const os_timernum  = 0;
+
+/* Stack for the os_idle_demon */
+unsigned int idle_task_stack[OS_IDLESTKSIZE];
+unsigned short const idle_task_stack_size = OS_IDLESTKSIZE;
+
+#ifndef OS_FIFOSZ
+ #define OS_FIFOSZ      16
+#endif
+
+/* Fifo Queue buffer for ISR requests.*/
+uint32_t       os_fifo[OS_FIFOSZ*2+1];
+uint8_t  const os_fifo_size = OS_FIFOSZ;
+
+/* An array of Active task pointers. */
+void *os_active_TCB[OS_TASK_CNT];
+
+/* User Timers Resources */
+#if (OS_TIMERS != 0)
+extern void osTimerThread (void const *argument);
+osThreadDef(osTimerThread, (osPriority)(OS_TIMERPRIO-3), 4*OS_TIMERSTKSZ);
+osThreadId osThreadId_osTimerThread;
+osMessageQDef(osTimerMessageQ, OS_TIMERCBQS, void *);
+osMessageQId osMessageQId_osTimerMessageQ;
+#else
+osThreadDef_t os_thread_def_osTimerThread = { NULL };
+osThreadId osThreadId_osTimerThread;
+osMessageQDef(osTimerMessageQ, 0, void *);
+osMessageQId osMessageQId_osTimerMessageQ;
+#endif
+
+
+/*----------------------------------------------------------------------------
+ *      RTX Optimizations (empty functions)
+ *---------------------------------------------------------------------------*/
+
+#if OS_ROBIN == 0
+ void rt_init_robin (void) {;}
+ void rt_chk_robin  (void) {;}
+#endif
+
+#if OS_STKCHECK == 0
+ void rt_stk_check  (void) {;}
+#endif
+
+
+/*----------------------------------------------------------------------------
+ *      Standard Library multithreading interface
+ *---------------------------------------------------------------------------*/
+
+#if defined (__CC_ARM) && !defined (__MICROLIB)
+ static OS_MUT   std_libmutex[OS_MUTEXCNT];
+ static uint32_t nr_mutex;
+
+ /*--------------------------- _mutex_initialize -----------------------------*/
+
+int _mutex_initialize (OS_ID *mutex) {
+  /* Allocate and initialize a system mutex. */
+
+  if (nr_mutex >= OS_MUTEXCNT) {
+    /* If you are here, you need to increase the number OS_MUTEXCNT. */
+    error("Not enough stdlib mutexes\n");
+  }
+  *mutex = &std_libmutex[nr_mutex++];
+  mutex_init (*mutex);
+  return (1);
+}
+
+
+/*--------------------------- _mutex_acquire --------------------------------*/
+
+__attribute__((used)) void _mutex_acquire (OS_ID *mutex) {
+  /* Acquire a system mutex, lock stdlib resources. */
+  if (runtask_id ()) {
+    /* RTX running, acquire a mutex. */
+    mutex_wait (*mutex);
+  }
+}
+
+
+/*--------------------------- _mutex_release --------------------------------*/
+
+__attribute__((used)) void _mutex_release (OS_ID *mutex) {
+  /* Release a system mutex, unlock stdlib resources. */
+  if (runtask_id ()) {
+    /* RTX running, release a mutex. */
+    mutex_rel (*mutex);
+  }
+}
+
+#endif
+
+
+/*----------------------------------------------------------------------------
+ *      RTX Startup
+ *---------------------------------------------------------------------------*/
+
+/* Main Thread definition */
+extern int main (void);
+osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL};
+
+// This define should be probably moved to the CMSIS layer
+#if   defined(TARGET_LPC1768)
+#define INITIAL_SP            (0x10008000UL)
+
+#elif defined(TARGET_LPC11U24)
+#define INITIAL_SP            (0x10002000UL)
+
+#elif defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO)
+#define INITIAL_SP            (0x10002000UL)
+
+#elif defined(TARGET_LPC1114)
+#define INITIAL_SP            (0x10001000UL)
+
+#elif defined(TARGET_LPC812)
+#define INITIAL_SP            (0x10001000UL)
+
+#elif defined(TARGET_KL25Z)
+#define INITIAL_SP            (0x20003000UL)
+
+#elif defined(TARGET_K64F)
+#define INITIAL_SP            (0x20030000UL)
+
+#elif defined(TARGET_KL46Z)
+#define INITIAL_SP            (0x20006000UL)
+
+#elif defined(TARGET_KL05Z)
+#define INITIAL_SP            (0x20000C00UL)
+
+#elif defined(TARGET_LPC4088)
+#define INITIAL_SP            (0x10010000UL)
+
+#elif defined(TARGET_LPC1347)
+#define INITIAL_SP            (0x10002000UL)
+
+#elif defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8)
+#define INITIAL_SP            (0x20002000UL)
+
+#elif defined(TARGET_DISCO_F303VC)
+#define INITIAL_SP            (0x2000A000UL)
+
+#elif defined(TARGET_STM32F407) || defined(TARGET_F407VG)
+#define INITIAL_SP            (0x20020000UL)
+
+#elif defined(TARGET_STM32F401RE)
+#define INITIAL_SP            (0x20018000UL)
+
+#elif defined(TARGET_LPC1549)
+#define INITIAL_SP            (0x02009000UL)
+
+#elif defined(TARGET_LPC11U68)
+#define INITIAL_SP            (0x10004000UL)
+
+#elif defined(TARGET_NRF51822)
+#define INITIAL_SP            (0x20004000UL)
+
+#elif defined(TARGET_STM32F411RE)
+#define INITIAL_SP            (0x20020000UL)
+
+#else
+#error "no target defined"
+
+#endif
+
+#ifdef __CC_ARM
+extern unsigned char     Image$$RW_IRAM1$$ZI$$Limit[];
+#define HEAP_START      (Image$$RW_IRAM1$$ZI$$Limit)
+#elif defined(__GNUC__)
+extern unsigned char     __end__[];
+#define HEAP_START      (__end__)
+#endif
+
+void set_main_stack(void) {
+    // That is the bottom of the main stack block: no collision detection
+    os_thread_def_main.stack_pointer = HEAP_START;
+
+    // Leave OS_SCHEDULERSTKSIZE words for the scheduler and interrupts
+    os_thread_def_main.stacksize = (INITIAL_SP - (unsigned int)HEAP_START) - (OS_SCHEDULERSTKSIZE * 4);
+}
+
+#if defined (__CC_ARM)
+#ifdef __MICROLIB
+void _main_init (void) __attribute__((section(".ARM.Collect$$$$000000FF")));
+void _main_init (void) {
+  osKernelInitialize();
+  set_main_stack();
+  osThreadCreate(&os_thread_def_main, NULL);
+  osKernelStart();
+  for (;;);
+}
+#else
+
+/* The single memory model is checking for stack collision at run time, verifing
+   that the heap pointer is underneath the stack pointer.
+
+   With the RTOS there is not only one stack above the heap, there are multiple
+   stacks and some of them are underneath the heap pointer.
+*/
+#pragma import(__use_two_region_memory)
+
+__asm void __rt_entry (void) {
+
+  IMPORT  __user_setup_stackheap
+  IMPORT  __rt_lib_init
+  IMPORT  os_thread_def_main
+  IMPORT  osKernelInitialize
+  IMPORT  set_main_stack
+  IMPORT  osKernelStart
+  IMPORT  osThreadCreate
+  IMPORT  exit
+
+  BL      __user_setup_stackheap
+  MOV     R1,R2
+  BL      __rt_lib_init
+  BL      osKernelInitialize
+  BL      set_main_stack
+  LDR     R0,=os_thread_def_main
+  MOVS    R1,#0
+  BL      osThreadCreate
+  BL      osKernelStart
+  BL      exit
+
+  ALIGN
+}
+#endif
+
+#elif defined (__GNUC__)
+
+#ifdef __CS3__
+
+/* CS3 start_c routine.
+ *
+ * Copyright (c) 2006, 2007 CodeSourcery Inc
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+#include "cs3.h"
+
+extern void __libc_init_array (void);
+
+__attribute ((noreturn)) void __cs3_start_c (void){
+  unsigned regions = __cs3_region_num;
+  const struct __cs3_region *rptr = __cs3_regions;
+
+  /* Initialize memory */
+  for (regions = __cs3_region_num, rptr = __cs3_regions; regions--; rptr++) {
+    long long *src = (long long *)rptr->init;
+    long long *dst = (long long *)rptr->data;
+    unsigned limit = rptr->init_size;
+    unsigned count;
+
+    if (src != dst)
+      for (count = 0; count != limit; count += sizeof (long long))
+        *dst++ = *src++;
+    else
+      dst = (long long *)((char *)dst + limit);
+    limit = rptr->zero_size;
+    for (count = 0; count != limit; count += sizeof (long long))
+      *dst++ = 0;
+  }
+
+  /* Run initializers.  */
+  __libc_init_array ();
+
+  osKernelInitialize();
+  set_main_stack();
+  osThreadCreate(&os_thread_def_main, NULL);
+  osKernelStart();
+  for (;;);
+}
+
+#else
+
+__attribute__((naked)) void software_init_hook (void) {
+  __asm (
+    ".syntax unified\n"
+    ".thumb\n"
+    "movs r0,#0\n"
+    "movs r1,#0\n"
+    "mov  r4,r0\n"
+    "mov  r5,r1\n"
+    "ldr  r0,= __libc_fini_array\n"
+    "bl   atexit\n"
+    "bl   __libc_init_array\n"
+    "mov  r0,r4\n"
+    "mov  r1,r5\n"
+    "bl   osKernelInitialize\n"
+    "bl   set_main_stack\n"
+    "ldr  r0,=os_thread_def_main\n"
+    "movs r1,#0\n"
+    "bl   osThreadCreate\n"
+    "bl   osKernelStart\n"
+    "bl   exit\n"
+  );
+}
+
+#endif
+
+#elif defined (__ICCARM__)
+
+extern int  __low_level_init(void);
+extern void __iar_data_init3(void);
+extern void exit(int arg);
+
+__noreturn __stackless void __cmain(void) {
+  int a;
+
+  if (__low_level_init() != 0) {
+    __iar_data_init3();
+  }
+  osKernelInitialize();
+  osThreadCreate(&os_thread_def_main, NULL);
+  a = osKernelStart();
+  exit(a);
+}
+
+#endif
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/RTX_Conf.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,73 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RTX_CONFIG.H
+ *      Purpose: Exported functions of RTX_Config.c
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+
+/* Error Codes */
+#define OS_ERR_STK_OVF          1
+#define OS_ERR_FIFO_OVF         2
+#define OS_ERR_MBX_OVF          3
+
+/* Definitions */
+#define BOX_ALIGN_8                   0x80000000
+#define _declare_box(pool,size,cnt)   U32 pool[(((size)+3)/4)*(cnt) + 3]
+#define _declare_box8(pool,size,cnt)  U64 pool[(((size)+7)/8)*(cnt) + 2]
+#define _init_box8(pool,size,bsize)   _init_box (pool,size,(bsize) | BOX_ALIGN_8)
+
+/* Variables */
+extern U32 idle_task_stack[];
+extern U32 os_fifo[];
+extern void *os_active_TCB[];
+
+/* Constants */
+extern U16 const os_maxtaskrun;
+extern U32 const os_trv;
+extern U8  const os_flags;
+extern U32 const os_rrobin;
+extern U32 const os_clockrate;
+extern U32 const os_timernum;
+extern U16 const idle_task_stack_size;
+
+extern U8  const os_fifo_size;
+
+/* Functions */
+extern void os_idle_demon   (void);
+extern int  os_tick_init    (void);
+extern void os_tick_irqack  (void);
+extern void os_tmr_call     (U16  info);
+extern void os_error        (U32 err_code);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/RTX_Conf_CM.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,279 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RTX_Conf_CM.C
+ *      Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "cmsis_os.h"
+
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part BEGIN
+ *---------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+//
+// <h>Thread Configuration
+// =======================
+//
+//   <o>Number of concurrent running threads <0-250>
+//   <i> Defines max. number of threads that will run at the same time.
+//       counting "main", but not counting "osTimerThread"
+//   <i> Default: 6
+#ifndef OS_TASKCNT
+#  if   defined(TARGET_LPC1768) || defined(TARGET_LPC2368)   || defined(TARGET_LPC4088) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\
+	 || defined(TARGET_KL46Z)   || defined(TARGET_STM32F407) || defined(TARGET_F407VG)  || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) || defined(TARGET_NRF51822) || defined(TARGET_STM32F411RE)
+#    define OS_TASKCNT         14
+#  elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401)  || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \
+	 || defined(TARGET_LPC812)   || defined(TARGET_KL25Z)         || defined(TARGET_KL05Z)        || defined(TARGET_STM32F100RB)  || defined(TARGET_STM32F051R8)
+#    define OS_TASKCNT         6
+#  else
+#    error "no target defined"
+#  endif
+#endif
+
+//   <o>Scheduler (+ interrupts) stack size [bytes] <64-4096:8><#/4>
+#ifndef OS_SCHEDULERSTKSIZE
+#  if   defined(TARGET_LPC1768) || defined(TARGET_LPC2368)   || defined(TARGET_LPC4088) || defined(TARGET_LPC1347)  || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\
+	 || defined(TARGET_KL46Z)   || defined(TARGET_STM32F407) || defined(TARGET_F407VG)  || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) || defined(TARGET_NRF51822) || defined(TARGET_STM32F411RE)
+#      define OS_SCHEDULERSTKSIZE    256
+#  elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401)  || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO)  || defined(TARGET_LPC1114) \
+	 || defined(TARGET_LPC812)   || defined(TARGET_KL25Z)         || defined(TARGET_KL05Z)        || defined(TARGET_STM32F100RB)  || defined(TARGET_STM32F051R8)
+#      define OS_SCHEDULERSTKSIZE    128
+#  else
+#    error "no target defined"
+#  endif
+#endif
+
+//   <o>Idle stack size [bytes] <64-4096:8><#/4>
+//   <i> Defines default stack size for the Idle thread.
+#ifndef OS_IDLESTKSIZE
+ #define OS_IDLESTKSIZE         128
+#endif
+
+//   <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
+//   <i> Defines stack size for Timer thread.
+//   <i> Default: 200
+#ifndef OS_TIMERSTKSZ
+ #define OS_TIMERSTKSZ  WORDS_STACK_SIZE
+#endif
+
+// <q>Check for stack overflow
+// <i> Includes the stack checking code for stack overflow.
+// <i> Note that additional code reduces the Kernel performance.
+#ifndef OS_STKCHECK
+ #define OS_STKCHECK    1
+#endif
+
+// <o>Processor mode for thread execution
+//   <0=> Unprivileged mode
+//   <1=> Privileged mode
+// <i> Default: Privileged mode
+#ifndef OS_RUNPRIV
+ #define OS_RUNPRIV     1
+#endif
+
+// </h>
+// <h>SysTick Timer Configuration
+// ==============================
+//
+//   <o>Timer clock value [Hz] <1-1000000000>
+//   <i> Defines the timer clock value.
+//   <i> Default: 6000000  (6MHz)
+#ifndef OS_CLOCK
+#  if defined(TARGET_LPC1768) || defined(TARGET_LPC2368)
+#    define OS_CLOCK       96000000
+
+#  elif defined(TARGET_LPC1347) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549)
+#    define OS_CLOCK       72000000
+
+#  elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401)  || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO)  || defined(TARGET_LPC1114) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_KL46Z) || defined(TARGET_STM32F051R8) || defined(TARGET_LPC11U68)
+#    define OS_CLOCK       48000000
+
+#  elif defined(TARGET_LPC812)
+#    define OS_CLOCK       36000000
+
+#  elif  defined(TARGET_STM32F100RB)
+#    define OS_CLOCK       24000000
+
+#  elif defined(TARGET_LPC4088) || defined(TARGET_K64F)
+#    define OS_CLOCK       120000000
+
+#  elif defined(TARGET_STM32F407) || defined(TARGET_F407VG)
+#    define OS_CLOCK       168000000
+
+#  elif defined(TARGET_NRF51822)
+#    define OS_CLOCK       16000000
+
+#  elif defined(TARGET_STM32F401RE)
+#    define OS_CLOCK       84000000
+
+#  elif defined(TARGET_STM32F411RE)
+#     define OS_CLOCK       100000000
+
+#  else
+#    error "no target defined"
+#  endif
+#endif
+
+//   <o>Timer tick value [us] <1-1000000>
+//   <i> Defines the timer tick value.
+//   <i> Default: 1000  (1ms)
+#ifndef OS_TICK
+ #define OS_TICK        1000
+#endif
+
+// </h>
+
+// <h>System Configuration
+// =======================
+//
+// <e>Round-Robin Thread switching
+// ===============================
+//
+// <i> Enables Round-Robin Thread switching.
+#ifndef OS_ROBIN
+ #define OS_ROBIN       1
+#endif
+
+//   <o>Round-Robin Timeout [ticks] <1-1000>
+//   <i> Defines how long a thread will execute before a thread switch.
+//   <i> Default: 5
+#ifndef OS_ROBINTOUT
+ #define OS_ROBINTOUT   5
+#endif
+
+// </e>
+
+// <e>User Timers
+// ==============
+//   <i> Enables user Timers
+#ifndef OS_TIMERS
+ #define OS_TIMERS      1
+#endif
+
+//   <o>Timer Thread Priority
+//                        <1=> Low
+//                        <2=> Below Normal
+//                        <3=> Normal
+//                        <4=> Above Normal
+//                        <5=> High
+//                        <6=> Realtime (highest)
+//   <i> Defines priority for Timer Thread
+//   <i> Default: High
+#ifndef OS_TIMERPRIO
+ #define OS_TIMERPRIO   5
+#endif
+
+//   <o>Timer Callback Queue size <1-32>
+//   <i> Number of concurrent active timer callback functions.
+//   <i> Default: 4
+#ifndef OS_TIMERCBQSZ
+ #define OS_TIMERCBQS   4
+#endif
+
+// </e>
+
+//   <o>ISR FIFO Queue size<4=>   4 entries  <8=>   8 entries
+//                         <12=> 12 entries  <16=> 16 entries
+//                         <24=> 24 entries  <32=> 32 entries
+//                         <48=> 48 entries  <64=> 64 entries
+//                         <96=> 96 entries
+//   <i> ISR functions store requests to this buffer,
+//   <i> when they are called from the interrupt handler.
+//   <i> Default: 16 entries
+#ifndef OS_FIFOSZ
+ #define OS_FIFOSZ      16
+#endif
+
+// </h>
+
+//------------- <<< end of configuration section >>> -----------------------
+
+// Standard library system mutexes
+// ===============================
+//  Define max. number system mutexes that are used to protect
+//  the arm standard runtime library. For microlib they are not used.
+#ifndef OS_MUTEXCNT
+ #define OS_MUTEXCNT    12
+#endif
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part END
+ *---------------------------------------------------------------------------*/
+
+#define OS_TRV          ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
+
+
+/*----------------------------------------------------------------------------
+ *      OS Idle daemon
+ *---------------------------------------------------------------------------*/
+void os_idle_demon (void) {
+  /* The idle demon is a system thread, running when no other thread is      */
+  /* ready to run.                                                           */
+
+  /* Sleep: ideally, we should put the chip to sleep.
+     Unfortunately, this usually requires disconnecting the interface chip (debugger).
+     This can be done, but it would break the local file system.
+  */
+  for (;;) {
+      // sleep();
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *      RTX Errors
+ *---------------------------------------------------------------------------*/
+extern void mbed_die(void);
+
+void os_error (uint32_t err_code) {
+    /* This function is called when a runtime error is detected. Parameter     */
+    /* 'err_code' holds the runtime error code (defined in RTX_Conf.h).      */
+    mbed_die();
+}
+
+void sysThreadError(osStatus status) {
+    if (status != osOK) {
+        mbed_die();
+    }
+}
+
+/*----------------------------------------------------------------------------
+ *      RTX Configuration Functions
+ *---------------------------------------------------------------------------*/
+
+#include "RTX_CM_lib.h"
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/TARGET_M4/TOOLCHAIN_ARM/HAL_CM4.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,310 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    HAL_CM4.C
+ *      Purpose: Hardware Abstraction Layer for Cortex-M4
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Conf.h"
+#include "rt_System.h"
+#include "rt_HAL_CM.h"
+#include "rt_Task.h"
+#include "rt_MemBox.h"
+
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_set_PSP ------------------------------------*/
+
+__asm void rt_set_PSP (U32 stack) {
+        MSR     PSP,R0
+        BX      LR
+}
+
+
+/*--------------------------- rt_get_PSP ------------------------------------*/
+
+__asm U32 rt_get_PSP (void) {
+        MRS     R0,PSP
+        BX      LR
+}
+
+
+/*--------------------------- os_set_env ------------------------------------*/
+
+__asm void os_set_env (void) {
+   /* Switch to Unprivileged/Privileged Thread mode, use PSP. */
+        MOV     R0,SP                   ; PSP = MSP
+        MSR     PSP,R0
+        LDR     R0,=__cpp(&os_flags)
+        LDRB    R0,[R0]
+        LSLS    R0,#31
+        MOVNE   R0,#0x02                ; Privileged Thread mode, use PSP
+        MOVEQ   R0,#0x03                ; Unprivileged Thread mode, use PSP
+        MSR     CONTROL,R0
+        BX      LR
+
+        ALIGN
+}
+
+
+/*--------------------------- _alloc_box ------------------------------------*/
+
+__asm void *_alloc_box (void *box_mem) {
+   /* Function wrapper for Unprivileged/Privileged mode. */
+        LDR     R12,=__cpp(rt_alloc_box)
+        MRS     R3,IPSR
+        LSLS    R3,#24
+        BXNE    R12
+        MRS     R3,CONTROL
+        LSLS    R3,#31
+        BXEQ    R12
+        SVC     0
+        BX      LR
+
+        ALIGN
+}
+
+
+/*--------------------------- _free_box -------------------------------------*/
+
+__asm int _free_box (void *box_mem, void *box) {
+   /* Function wrapper for Unprivileged/Privileged mode. */
+        LDR     R12,=__cpp(rt_free_box)
+        MRS     R3,IPSR
+        LSLS    R3,#24
+        BXNE    R12
+        MRS     R3,CONTROL
+        LSLS    R3,#31
+        BXEQ    R12
+        SVC     0
+        BX      LR
+
+        ALIGN
+}
+
+
+/*-------------------------- SVC_Handler ------------------------------------*/
+
+__asm void SVC_Handler (void) {
+        PRESERVE8
+
+        IMPORT  SVC_Count
+        IMPORT  SVC_Table
+        IMPORT  rt_stk_check
+
+#ifdef  IFX_XMC4XXX
+        EXPORT  SVC_Handler_Veneer
+SVC_Handler_Veneer
+#endif
+
+        MRS     R0,PSP                  ; Read PSP
+        LDR     R1,[R0,#24]             ; Read Saved PC from Stack
+        LDRB    R1,[R1,#-2]             ; Load SVC Number
+        CBNZ    R1,SVC_User
+
+        LDM     R0,{R0-R3,R12}          ; Read R0-R3,R12 from stack
+        PUSH    {R4,LR}                 ; Save EXC_RETURN
+        BLX     R12                     ; Call SVC Function
+        POP     {R4,LR}                 ; Restore EXC_RETURN
+
+        MRS     R12,PSP                 ; Read PSP
+        STM     R12,{R0-R2}             ; Store return values
+
+        LDR     R3,=__cpp(&os_tsk)
+        LDM     R3,{R1,R2}              ; os_tsk.run, os_tsk.new
+        CMP     R1,R2
+#ifdef  IFX_XMC4XXX
+        PUSHEQ  {LR}
+        POPEQ   {PC}
+#else
+        BXEQ    LR                      ; RETI, no task switch
+#endif
+
+        CBZ     R1,SVC_Next             ; Runtask deleted?
+        TST     LR,#0x10                ; is it extended frame?
+        VSTMDBEQ R12!,{S16-S31}         ; yes, stack also VFP hi-regs
+        MOVEQ   R0,#0x01                ; os_tsk->stack_frame val
+        MOVNE   R0,#0x00
+        STRB    R0,[R1,#TCB_STACKF]     ; os_tsk.run->stack_frame = val
+        STMDB   R12!,{R4-R11}           ; Save Old context
+        STR     R12,[R1,#TCB_TSTACK]    ; Update os_tsk.run->tsk_stack
+
+        PUSH    {R2,R3}
+        BL      rt_stk_check            ; Check for Stack overflow
+        POP     {R2,R3}
+
+SVC_Next
+        STR     R2,[R3]                 ; os_tsk.run = os_tsk.new
+
+        LDR     R12,[R2,#TCB_TSTACK]    ; os_tsk.new->tsk_stack
+        LDMIA   R12!,{R4-R11}           ; Restore New Context
+        LDRB    R0,[R2,#TCB_STACKF]     ; Stack Frame
+        CMP     R0,#0                   ; Basic/Extended Stack Frame
+        VLDMIANE R12!,{S16-S31}         ; restore VFP hi-registers
+        MVNNE   LR,#:NOT:0xFFFFFFED     ; set EXC_RETURN value
+        MVNEQ   LR,#:NOT:0xFFFFFFFD
+        MSR     PSP,R12                 ; Write PSP
+
+SVC_Exit
+#ifdef  IFX_XMC4XXX
+        PUSH    {LR}
+        POP     {PC}
+#else
+        BX      LR
+#endif
+
+        /*------------------- User SVC ------------------------------*/
+
+SVC_User
+        PUSH    {R4,LR}                 ; Save Registers
+        LDR     R2,=SVC_Count
+        LDR     R2,[R2]
+        CMP     R1,R2
+        BHI     SVC_Done                ; Overflow
+
+        LDR     R4,=SVC_Table-4
+        LDR     R4,[R4,R1,LSL #2]       ; Load SVC Function Address
+
+        LDM     R0,{R0-R3,R12}          ; Read R0-R3,R12 from stack
+        BLX     R4                      ; Call SVC Function
+
+        MRS     R12,PSP
+        STM     R12,{R0-R3}             ; Function return values
+SVC_Done
+        POP     {R4,PC}                 ; RETI
+
+        ALIGN
+}
+
+
+/*-------------------------- PendSV_Handler ---------------------------------*/
+
+__asm void PendSV_Handler (void) {
+        PRESERVE8
+
+#ifdef  IFX_XMC4XXX
+        EXPORT  PendSV_Handler_Veneer
+PendSV_Handler_Veneer
+#endif
+
+        PUSH    {R4,LR}                 ; Save EXC_RETURN
+        BL      __cpp(rt_pop_req)
+
+Sys_Switch
+        POP     {R4,LR}                 ; Restore EXC_RETURN
+
+        LDR     R3,=__cpp(&os_tsk)
+        LDM     R3,{R1,R2}              ; os_tsk.run, os_tsk.new
+        CMP     R1,R2
+#ifdef  IFX_XMC4XXX
+        PUSHEQ  {LR}
+        POPEQ   {PC}
+#else
+        BXEQ    LR                      ; RETI, no task switch
+#endif
+
+        MRS     R12,PSP                 ; Read PSP
+        TST     LR,#0x10                ; is it extended frame?
+        VSTMDBEQ R12!,{S16-S31}         ; yes, stack also VFP hi-regs
+        MOVEQ   R0,#0x01                ; os_tsk->stack_frame val
+        MOVNE   R0,#0x00
+        STRB    R0,[R1,#TCB_STACKF]     ; os_tsk.run->stack_frame = val
+        STMDB   R12!,{R4-R11}           ; Save Old context
+        STR     R12,[R1,#TCB_TSTACK]    ; Update os_tsk.run->tsk_stack
+
+        PUSH    {R2,R3}
+        BL      rt_stk_check            ; Check for Stack overflow
+        POP     {R2,R3}
+
+        STR     R2,[R3]                 ; os_tsk.run = os_tsk.new
+
+        LDR     R12,[R2,#TCB_TSTACK]    ; os_tsk.new->tsk_stack
+        LDMIA   R12!,{R4-R11}           ; Restore New Context
+        LDRB    R0,[R2,#TCB_STACKF]     ; Stack Frame
+        CMP     R0,#0                   ; Basic/Extended Stack Frame
+        VLDMIANE R12!,{S16-S31}         ; restore VFP hi-regs
+        MVNNE   LR,#:NOT:0xFFFFFFED     ; set EXC_RETURN value
+        MVNEQ   LR,#:NOT:0xFFFFFFFD
+        MSR     PSP,R12                 ; Write PSP
+
+Sys_Exit
+#ifdef  IFX_XMC4XXX
+        PUSH    {LR}
+        POP     {PC}
+#else
+        BX      LR                      ; Return to Thread Mode
+#endif
+
+        ALIGN
+}
+
+
+/*-------------------------- SysTick_Handler --------------------------------*/
+
+__asm void SysTick_Handler (void) {
+        PRESERVE8
+
+#ifdef  IFX_XMC4XXX
+        EXPORT  SysTick_Handler_Veneer
+SysTick_Handler_Veneer
+#endif
+
+        PUSH    {R4,LR}                 ; Save EXC_RETURN
+        BL      __cpp(rt_systick)
+        B       Sys_Switch
+
+        ALIGN
+}
+
+
+/*-------------------------- OS_Tick_Handler --------------------------------*/
+
+__asm void OS_Tick_Handler (void) {
+        PRESERVE8
+
+        PUSH    {R4,LR}                 ; Save EXC_RETURN
+        BL      __cpp(os_tick_irqack)
+        BL      __cpp(rt_systick)
+        B       Sys_Switch
+
+        ALIGN
+}
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/TARGET_M4/TOOLCHAIN_ARM/SVC_Table.s	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,58 @@
+;/*----------------------------------------------------------------------------
+; *      RL-ARM - RTX
+; *----------------------------------------------------------------------------
+; *      Name:    SVC_TABLE.S
+; *      Purpose: Pre-defined SVC Table for Cortex-M
+; *      Rev.:    V4.70
+; *----------------------------------------------------------------------------
+; *
+; * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+; * All rights reserved.
+; * Redistribution and use in source and binary forms, with or without
+; * modification, are permitted provided that the following conditions are met:
+; *  - Redistributions of source code must retain the above copyright
+; *    notice, this list of conditions and the following disclaimer.
+; *  - Redistributions in binary form must reproduce the above copyright
+; *    notice, this list of conditions and the following disclaimer in the
+; *    documentation and/or other materials provided with the distribution.
+; *  - Neither the name of ARM  nor the names of its contributors may be used 
+; *    to endorse or promote products derived from this software without 
+; *    specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; * POSSIBILITY OF SUCH DAMAGE.
+; *---------------------------------------------------------------------------*/
+
+
+                AREA    SVC_TABLE, CODE, READONLY
+
+                EXPORT  SVC_Count
+
+SVC_Cnt         EQU    (SVC_End-SVC_Table)/4
+SVC_Count       DCD     SVC_Cnt
+
+; Import user SVC functions here.
+;               IMPORT  __SVC_1
+
+                EXPORT  SVC_Table
+SVC_Table
+; Insert user SVC functions here. SVC 0 used by RTL Kernel.
+;               DCD     __SVC_1                 ; user SVC function
+
+SVC_End
+
+                END
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/cmsis_os.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,773 @@
+/* ----------------------------------------------------------------------
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * $Date:        5. June 2012
+ * $Revision:    V1.01
+ *
+ * Project:      CMSIS-RTOS API
+ * Title:        cmsis_os.h RTX header file
+ *
+ * Version 0.02
+ *    Initial Proposal Phase
+ * Version 0.03
+ *    osKernelStart added, optional feature: main started as thread
+ *    osSemaphores have standard behavior
+ *    osTimerCreate does not start the timer, added osTimerStart
+ *    osThreadPass is renamed to osThreadYield
+ * Version 1.01
+ *    Support for C++ interface
+ *     - const attribute removed from the osXxxxDef_t typedef's
+ *     - const attribute added to the osXxxxDef macros
+ *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
+ *    Added: osKernelInitialize
+ * -------------------------------------------------------------------- */
+
+/**
+\page cmsis_os_h Header File Template: cmsis_os.h
+
+The file \b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS).
+Each RTOS that is compliant with CMSIS-RTOS shall provide a specific \b cmsis_os.h header file that represents
+its implementation.
+
+The file cmsis_os.h contains:
+ - CMSIS-RTOS API function definitions
+ - struct definitions for parameters and return types
+ - status and priority values used by CMSIS-RTOS API functions
+ - macros for defining threads and other kernel objects
+
+
+<b>Name conventions and header file modifications</b>
+
+All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions.
+Definitions that are prefixed \b os_ are not used in the application code but local to this header file.
+All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread.
+
+Definitions that are marked with <b>CAN BE CHANGED</b> can be adapted towards the needs of the actual CMSIS-RTOS implementation.
+These definitions can be specific to the underlying RTOS kernel.
+
+Definitions that are marked with <b>MUST REMAIN UNCHANGED</b> cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer
+compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation.
+
+
+<b>Function calls from interrupt service routines</b>
+
+The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR):
+  - \ref osSignalSet
+  - \ref osSemaphoreRelease
+  - \ref osPoolAlloc, \ref osPoolCAlloc, \ref osPoolFree
+  - \ref osMessagePut, \ref osMessageGet
+  - \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree
+
+Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called
+from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector.
+
+Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time.
+If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \b osErrorISRRecursive.
+
+
+<b>Define and reference object definitions</b>
+
+With <b>\#define osObjectsExternal</b> objects are defined as external symbols. This allows to create a consistent header file
+that is used throughout a project as shown below:
+
+<i>Header File</i>
+\code
+#include <cmsis_os.h>                                         // CMSIS RTOS header file
+
+// Thread definition
+extern void thread_sample (void const *argument);             // function prototype
+osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);
+
+// Pool definition
+osPoolDef(MyPool, 10, long);
+\endcode
+
+
+This header file defines all objects when included in a C/C++ source file. When <b>\#define osObjectsExternal</b> is
+present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be
+used throughout the whole project.
+
+<i>Example</i>
+\code
+#include "osObjects.h"     // Definition of the CMSIS-RTOS objects
+\endcode
+
+\code
+#define osObjectExternal   // Objects will be defined as external symbols
+#include "osObjects.h"     // Reference to the CMSIS-RTOS objects
+\endcode
+
+*/
+
+#ifndef _CMSIS_OS_H
+#define _CMSIS_OS_H
+
+/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version.
+#define osCMSIS           0x10001      ///< API version (main [31:16] .sub [15:0])
+
+/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
+#define osCMSIS_RTX     ((4<<16)|61)   ///< RTOS identification and version (main [31:16] .sub [15:0])
+
+/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
+#define osKernelSystemId "RTX V4.61"   ///< RTOS identification string
+
+
+#define CMSIS_OS_RTX
+
+// The stack space occupied is mainly dependent on the underling C standard library
+#if defined(TOOLCHAIN_GCC) || defined(TOOLCHAIN_ARM_STD)
+#    define WORDS_STACK_SIZE   512
+#elif defined(TOOLCHAIN_ARM_MICRO)
+#    define WORDS_STACK_SIZE   128
+#endif
+
+#define DEFAULT_STACK_SIZE         (WORDS_STACK_SIZE*4)
+
+
+/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS.
+#define osFeature_MainThread   1       ///< main thread      1=main can be thread, 0=not available
+#define osFeature_Pool         1       ///< Memory Pools:    1=available, 0=not available
+#define osFeature_MailQ        1       ///< Mail Queues:     1=available, 0=not available
+#define osFeature_MessageQ     1       ///< Message Queues:  1=available, 0=not available
+#define osFeature_Signals      16      ///< maximum number of Signal Flags available per thread
+#define osFeature_Semaphore    65535   ///< maximum count for \ref osSemaphoreCreate function
+#define osFeature_Wait         0       ///< osWait function: 1=available, 0=not available
+
+#if defined (__CC_ARM)
+#define os_InRegs __value_in_regs      // Compiler specific: force struct in registers
+#else
+#define os_InRegs
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "os_tcb.h"
+
+// ==== Enumeration, structures, defines ====
+
+/// Priority used for thread control.
+/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS.
+typedef enum  {
+  osPriorityIdle          = -3,          ///< priority: idle (lowest)
+  osPriorityLow           = -2,          ///< priority: low
+  osPriorityBelowNormal   = -1,          ///< priority: below normal
+  osPriorityNormal        =  0,          ///< priority: normal (default)
+  osPriorityAboveNormal   = +1,          ///< priority: above normal
+  osPriorityHigh          = +2,          ///< priority: high
+  osPriorityRealtime      = +3,          ///< priority: realtime (highest)
+  osPriorityError         =  0x84        ///< system cannot determine priority or thread has illegal priority
+} osPriority;
+
+/// Timeout value.
+/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS.
+#define osWaitForever     0xFFFFFFFF     ///< wait forever timeout value
+
+/// Status code values returned by CMSIS-RTOS functions.
+/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS.
+typedef enum  {
+  osOK                    =     0,       ///< function completed; no error or event occurred.
+  osEventSignal           =  0x08,       ///< function completed; signal event occurred.
+  osEventMessage          =  0x10,       ///< function completed; message event occurred.
+  osEventMail             =  0x20,       ///< function completed; mail event occurred.
+  osEventTimeout          =  0x40,       ///< function completed; timeout occurred.
+  osErrorParameter        =  0x80,       ///< parameter error: a mandatory parameter was missing or specified an incorrect object.
+  osErrorResource         =  0x81,       ///< resource not available: a specified resource was not available.
+  osErrorTimeoutResource  =  0xC1,       ///< resource not available within given time: a specified resource was not available within the timeout period.
+  osErrorISR              =  0x82,       ///< not allowed in ISR context: the function cannot be called from interrupt service routines.
+  osErrorISRRecursive     =  0x83,       ///< function called multiple times from ISR with same object.
+  osErrorPriority         =  0x84,       ///< system cannot determine priority or thread has illegal priority.
+  osErrorNoMemory         =  0x85,       ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.
+  osErrorValue            =  0x86,       ///< value of a parameter is out of range.
+  osErrorOS               =  0xFF,       ///< unspecified RTOS error: run-time error but no other error message fits.
+  os_status_reserved      =  0x7FFFFFFF  ///< prevent from enum down-size compiler optimization.
+} osStatus;
+
+
+/// Timer type value for the timer definition.
+/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
+typedef enum  {
+  osTimerOnce             =     0,       ///< one-shot timer
+  osTimerPeriodic         =     1        ///< repeating timer
+} os_timer_type;
+
+/// Entry point of a thread.
+/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
+typedef void (*os_pthread) (void const *argument);
+
+/// Entry point of a timer call back function.
+/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
+typedef void (*os_ptimer) (void const *argument);
+
+// >>> the following data type definitions may shall adapted towards a specific RTOS
+
+/// Thread ID identifies the thread (pointer to a thread control block).
+/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_thread_cb *osThreadId;
+
+/// Timer ID identifies the timer (pointer to a timer control block).
+/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_timer_cb *osTimerId;
+
+/// Mutex ID identifies the mutex (pointer to a mutex control block).
+/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_mutex_cb *osMutexId;
+
+/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).
+/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_semaphore_cb *osSemaphoreId;
+
+/// Pool ID identifies the memory pool (pointer to a memory pool control block).
+/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_pool_cb *osPoolId;
+
+/// Message ID identifies the message queue (pointer to a message queue control block).
+/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_messageQ_cb *osMessageQId;
+
+/// Mail ID identifies the mail queue (pointer to a mail queue control block).
+/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_mailQ_cb *osMailQId;
+
+
+/// Thread Definition structure contains startup information of a thread.
+/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_thread_def  {
+  os_pthread               pthread;      ///< start address of thread function
+  osPriority             tpriority;      ///< initial thread priority
+  uint32_t               stacksize;      ///< stack size requirements in bytes
+  unsigned char         *stack_pointer;  ///< pointer to the stack memory block
+  struct OS_TCB          tcb;
+} osThreadDef_t;
+
+/// Timer Definition structure contains timer parameters.
+/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_timer_def  {
+  os_ptimer                 ptimer;    ///< start address of a timer function
+  void                      *timer;    ///< pointer to internal data
+} osTimerDef_t;
+
+/// Mutex Definition structure contains setup information for a mutex.
+/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_mutex_def  {
+  void                      *mutex;    ///< pointer to internal data
+} osMutexDef_t;
+
+/// Semaphore Definition structure contains setup information for a semaphore.
+/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_semaphore_def  {
+  void                  *semaphore;    ///< pointer to internal data
+} osSemaphoreDef_t;
+
+/// Definition structure for memory block allocation.
+/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_pool_def  {
+  uint32_t                 pool_sz;    ///< number of items (elements) in the pool
+  uint32_t                 item_sz;    ///< size of an item
+  void                       *pool;    ///< pointer to memory for pool
+} osPoolDef_t;
+
+/// Definition structure for message queue.
+/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_messageQ_def  {
+  uint32_t                queue_sz;    ///< number of elements in the queue
+  void                       *pool;    ///< memory array for messages
+} osMessageQDef_t;
+
+/// Definition structure for mail queue.
+/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_mailQ_def  {
+  uint32_t                queue_sz;    ///< number of elements in the queue
+  uint32_t                 item_sz;    ///< size of an item
+  void                       *pool;    ///< memory array for mail
+} osMailQDef_t;
+
+/// Event structure contains detailed information about an event.
+/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
+///       However the struct may be extended at the end.
+typedef struct  {
+  osStatus                 status;     ///< status code: event or error information
+  union  {
+    uint32_t                    v;     ///< message as 32-bit value
+    void                       *p;     ///< message or mail as void pointer
+    int32_t               signals;     ///< signal flags
+  } value;                             ///< event value
+  union  {
+    osMailQId             mail_id;     ///< mail id obtained by \ref osMailCreate
+    osMessageQId       message_id;     ///< message id obtained by \ref osMessageCreate
+  } def;                               ///< event definition
+} osEvent;
+
+
+//  ==== Kernel Control Functions ====
+
+/// Initialize the RTOS Kernel for creating objects.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS.
+osStatus osKernelInitialize (void);
+
+/// Start the RTOS Kernel.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
+osStatus osKernelStart (void);
+
+/// Check if the RTOS kernel is already started.
+/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
+/// \return 0 RTOS is not started, 1 RTOS is started.
+int32_t osKernelRunning(void);
+
+
+//  ==== Thread Management ====
+
+/// Create a Thread Definition with function, priority, and stack requirements.
+/// \param         name         name of the thread function.
+/// \param         priority     initial priority of the thread function.
+/// \param         stacksz      stack size (in bytes) requirements for the thread function.
+/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osThreadDef(name, priority, stacksz)  \
+extern osThreadDef_t os_thread_def_##name
+#else                            // define the object
+#define osThreadDef(name, priority, stacksz)  \
+unsigned char os_thread_def_stack_##name [stacksz]; \
+osThreadDef_t os_thread_def_##name = \
+{ (name), (priority), (stacksz), (os_thread_def_stack_##name)}
+#endif
+
+/// Access a Thread definition.
+/// \param         name          name of the thread definition object.
+/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osThread(name)  \
+&os_thread_def_##name
+
+/// Create a thread and add it to Active Threads and set it to state READY.
+/// \param[in]     thread_def    thread definition referenced with \ref osThread.
+/// \param[in]     argument      pointer that is passed to the thread function as start argument.
+/// \return thread ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
+osThreadId osThreadCreate (osThreadDef_t *thread_def, void *argument);
+
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS.
+osThreadId osThreadGetId (void);
+
+/// Terminate execution of a thread and remove it from Active Threads.
+/// \param[in]     thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS.
+osStatus osThreadTerminate (osThreadId thread_id);
+
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
+osStatus osThreadYield (void);
+
+/// Change priority of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     priority      new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS.
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
+
+/// Get current priority of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return current priority value of the thread function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS.
+osPriority osThreadGetPriority (osThreadId thread_id);
+
+
+//  ==== Generic Wait Functions ====
+
+/// Wait for Timeout (Time Delay).
+/// \param[in]     millisec      time delay value
+/// \return status code that indicates the execution status of the function.
+osStatus osDelay (uint32_t millisec);
+
+#if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0))     // Generic Wait available
+
+/// Wait for Signal, Message, Mail, or Timeout.
+/// \param[in] millisec          timeout value or 0 in case of no time-out
+/// \return event that contains signal, message, or mail information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
+os_InRegs osEvent osWait (uint32_t millisec);
+
+#endif  // Generic Wait available
+
+
+//  ==== Timer Management Functions ====
+/// Define a Timer object.
+/// \param         name          name of the timer object.
+/// \param         function      name of the timer call back function.
+/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osTimerDef(name, function)  \
+extern osTimerDef_t os_timer_def_##name
+#else                            // define the object
+#define osTimerDef(name, function)  \
+uint32_t os_timer_cb_##name[5]; \
+osTimerDef_t os_timer_def_##name = \
+{ (function), (os_timer_cb_##name) }
+#endif
+
+/// Access a Timer definition.
+/// \param         name          name of the timer object.
+/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osTimer(name) \
+&os_timer_def_##name
+
+/// Create a timer.
+/// \param[in]     timer_def     timer object referenced with \ref osTimer.
+/// \param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
+/// \param[in]     argument      argument to the timer call back function.
+/// \return timer ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS.
+osTimerId osTimerCreate (osTimerDef_t *timer_def, os_timer_type type, void *argument);
+
+/// Start or restart a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \param[in]     millisec      time delay value of the timer.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
+osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
+
+/// Stop the timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS.
+osStatus osTimerStop (osTimerId timer_id);
+
+/// Delete a timer that was created by \ref osTimerCreate.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS.
+osStatus osTimerDelete (osTimerId timer_id);
+
+
+//  ==== Signal Management ====
+
+/// Set the specified Signal Flags of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     signals       specifies the signal flags of the thread that should be set.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS.
+int32_t osSignalSet (osThreadId thread_id, int32_t signals);
+
+/// Clear the specified Signal Flags of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     signals       specifies the signal flags of the thread that shall be cleared.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS.
+int32_t osSignalClear (osThreadId thread_id, int32_t signals);
+
+/// Get Signal Flags status of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSignalGet shall be consistent in every CMSIS-RTOS.
+int32_t osSignalGet (osThreadId thread_id);
+
+/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
+/// \param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return event flag information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
+os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec);
+
+
+//  ==== Mutex Management ====
+
+/// Define a Mutex.
+/// \param         name          name of the mutex object.
+/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMutexDef(name)  \
+extern osMutexDef_t os_mutex_def_##name
+#else                            // define the object
+#define osMutexDef(name)  \
+uint32_t os_mutex_cb_##name[3]; \
+osMutexDef_t os_mutex_def_##name = { (os_mutex_cb_##name) }
+#endif
+
+/// Access a Mutex definition.
+/// \param         name          name of the mutex object.
+/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMutex(name)  \
+&os_mutex_def_##name
+
+/// Create and Initialize a Mutex object.
+/// \param[in]     mutex_def     mutex definition referenced with \ref osMutex.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
+osMutexId osMutexCreate (osMutexDef_t *mutex_def);
+
+/// Wait until a Mutex becomes available.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
+osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
+
+/// Release a Mutex that was obtained by \ref osMutexWait.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
+osStatus osMutexRelease (osMutexId mutex_id);
+
+/// Delete a Mutex that was created by \ref osMutexCreate.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS.
+osStatus osMutexDelete (osMutexId mutex_id);
+
+
+//  ==== Semaphore Management Functions ====
+
+#if (defined (osFeature_Semaphore)  &&  (osFeature_Semaphore != 0))     // Semaphore available
+
+/// Define a Semaphore object.
+/// \param         name          name of the semaphore object.
+/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osSemaphoreDef(name)  \
+extern osSemaphoreDef_t os_semaphore_def_##name
+#else                            // define the object
+#define osSemaphoreDef(name)  \
+uint32_t os_semaphore_cb_##name[2]; \
+osSemaphoreDef_t os_semaphore_def_##name = { (os_semaphore_cb_##name) }
+#endif
+
+/// Access a Semaphore definition.
+/// \param         name          name of the semaphore object.
+/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osSemaphore(name)  \
+&os_semaphore_def_##name
+
+/// Create and Initialize a Semaphore object used for managing resources.
+/// \param[in]     semaphore_def semaphore definition referenced with \ref osSemaphore.
+/// \param[in]     count         number of available resources.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
+osSemaphoreId osSemaphoreCreate (osSemaphoreDef_t *semaphore_def, int32_t count);
+
+/// Wait until a Semaphore token becomes available.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return number of available tokens, or -1 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
+
+/// Release a Semaphore token.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
+osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
+
+/// Delete a Semaphore that was created by \ref osSemaphoreCreate.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
+osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
+
+#endif     // Semaphore available
+
+
+//  ==== Memory Pool Management Functions ====
+
+#if (defined (osFeature_Pool)  &&  (osFeature_Pool != 0))  // Memory Pool Management available
+
+/// \brief Define a Memory Pool.
+/// \param         name          name of the memory pool.
+/// \param         no            maximum number of blocks (objects) in the memory pool.
+/// \param         type          data type of a single block (object).
+/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osPoolDef(name, no, type)   \
+extern osPoolDef_t os_pool_def_##name
+#else                            // define the object
+#define osPoolDef(name, no, type)   \
+uint32_t os_pool_m_##name[3+((sizeof(type)+3)/4)*(no)]; \
+osPoolDef_t os_pool_def_##name = \
+{ (no), sizeof(type), (os_pool_m_##name) }
+#endif
+
+/// \brief Access a Memory Pool definition.
+/// \param         name          name of the memory pool
+/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osPool(name) \
+&os_pool_def_##name
+
+/// Create and Initialize a memory pool.
+/// \param[in]     pool_def      memory pool definition referenced with \ref osPool.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS.
+osPoolId osPoolCreate (osPoolDef_t *pool_def);
+
+/// Allocate a memory block from a memory pool.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
+void *osPoolAlloc (osPoolId pool_id);
+
+/// Allocate a memory block from a memory pool and set memory block to zero.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
+void *osPoolCAlloc (osPoolId pool_id);
+
+/// Return an allocated memory block back to a specific memory pool.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \param[in]     block         address of the allocated memory block that is returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
+osStatus osPoolFree (osPoolId pool_id, void *block);
+
+#endif   // Memory Pool Management available
+
+
+//  ==== Message Queue Management Functions ====
+
+#if (defined (osFeature_MessageQ)  &&  (osFeature_MessageQ != 0))     // Message Queues available
+
+/// \brief Create a Message Queue Definition.
+/// \param         name          name of the queue.
+/// \param         queue_sz      maximum number of messages in the queue.
+/// \param         type          data type of a single message element (for debugger).
+/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMessageQDef(name, queue_sz, type)   \
+extern osMessageQDef_t os_messageQ_def_##name
+#else                            // define the object
+#define osMessageQDef(name, queue_sz, type)   \
+uint32_t os_messageQ_q_##name[4+(queue_sz)]; \
+osMessageQDef_t os_messageQ_def_##name = \
+{ (queue_sz), (os_messageQ_q_##name) }
+#endif
+
+/// \brief Access a Message Queue Definition.
+/// \param         name          name of the queue
+/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMessageQ(name) \
+&os_messageQ_def_##name
+
+/// Create and Initialize a Message Queue.
+/// \param[in]     queue_def     queue definition referenced with \ref osMessageQ.
+/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
+osMessageQId osMessageCreate (osMessageQDef_t *queue_def, osThreadId thread_id);
+
+/// Put a Message to a Queue.
+/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
+/// \param[in]     info          message information.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
+
+/// Get a Message or Wait for a Message from a Queue.
+/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return event information that includes status code.
+/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
+os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
+
+#endif     // Message Queues available
+
+
+//  ==== Mail Queue Management Functions ====
+
+#if (defined (osFeature_MailQ)  &&  (osFeature_MailQ != 0))     // Mail Queues available
+
+/// \brief Create a Mail Queue Definition.
+/// \param         name          name of the queue
+/// \param         queue_sz      maximum number of messages in queue
+/// \param         type          data type of a single message element
+/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMailQDef(name, queue_sz, type) \
+extern osMailQDef_t os_mailQ_def_##name
+#else                            // define the object
+#define osMailQDef(name, queue_sz, type) \
+uint32_t os_mailQ_q_##name[4+(queue_sz)]; \
+uint32_t os_mailQ_m_##name[3+((sizeof(type)+3)/4)*(queue_sz)]; \
+void *   os_mailQ_p_##name[2] = { (os_mailQ_q_##name), os_mailQ_m_##name }; \
+osMailQDef_t os_mailQ_def_##name =  \
+{ (queue_sz), sizeof(type), (os_mailQ_p_##name) }
+#endif
+
+/// \brief Access a Mail Queue Definition.
+/// \param         name          name of the queue
+/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMailQ(name)  \
+&os_mailQ_def_##name
+
+/// Create and Initialize mail queue.
+/// \param[in]     queue_def     reference to the mail queue definition obtain with \ref osMailQ
+/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return mail queue ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS.
+osMailQId osMailCreate (osMailQDef_t *queue_def, osThreadId thread_id);
+
+/// Allocate a memory block from a mail.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
+
+/// Allocate a memory block from a mail and set memory block to zero.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
+
+/// Put a mail to a queue.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     mail          memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS.
+osStatus osMailPut (osMailQId queue_id, void *mail);
+
+/// Get a mail from a queue.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out
+/// \return event that contains mail information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
+os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
+
+/// Free a memory block from a mail.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     mail          pointer to the memory block that was obtained with \ref osMailGet.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
+osStatus osMailFree (osMailQId queue_id, void *mail);
+
+#endif  // Mail Queues available
+
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif  // _CMSIS_OS_H
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/os_tcb.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,51 @@
+#ifndef OS_TCB_H
+#define OS_TCB_H
+
+/* Types */
+typedef char               S8;
+typedef unsigned char      U8;
+typedef short              S16;
+typedef unsigned short     U16;
+typedef int                S32;
+typedef unsigned int       U32;
+typedef long long          S64;
+typedef unsigned long long U64;
+typedef unsigned char      BIT;
+typedef unsigned int       BOOL;
+typedef void               (*FUNCP)(void);
+
+typedef struct OS_TCB {
+  /* General part: identical for all implementations.                        */
+  U8     cb_type;                 /* Control Block Type                      */
+  U8     state;                   /* Task state                              */
+  U8     prio;                    /* Execution priority                      */
+  U8     task_id;                 /* Task ID value for optimized TCB access  */
+  struct OS_TCB *p_lnk;           /* Link pointer for ready/sem. wait list   */
+  struct OS_TCB *p_rlnk;          /* Link pointer for sem./mbx lst backwards */
+  struct OS_TCB *p_dlnk;          /* Link pointer for delay list             */
+  struct OS_TCB *p_blnk;          /* Link pointer for delay list backwards   */
+  U16    delta_time;              /* Time until time out                     */
+  U16    interval_time;           /* Time interval for periodic waits        */
+  U16    events;                  /* Event flags                             */
+  U16    waits;                   /* Wait flags                              */
+  void   **msg;                   /* Direct message passing when task waits  */
+
+  /* Hardware dependant part: specific for CM processor                      */
+  U8     stack_frame;             /* Stack frame: 0=Basic, 1=Extended        */
+  U8     reserved;
+  U16    priv_stack;              /* Private stack size in bytes             */
+  U32    tsk_stack;               /* Current task Stack pointer (R13)        */
+  U32    *stack;                  /* Pointer to Task Stack memory block      */
+
+  /* Library dependant part                                                   */
+#if defined (__CC_ARM) && !defined (__MICROLIB)
+ /* A memory space for arm standard library. */
+  U32 std_libspace[96/4];
+#endif
+
+  /* Task entry point used for uVision debugger                              */
+  FUNCP  ptask;                   /* Task entry address                      */
+} *P_TCB;
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_CMSIS.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1921 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    rt_CMSIS.c
+ *      Purpose: CMSIS RTOS API
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#define __CMSIS_GENERIC
+
+#if defined (__CORTEX_M4) || defined (__CORTEX_M4F)
+  #include "core_cm4.h"
+#elif defined (__CORTEX_M3)
+  #include "core_cm3.h"
+#elif defined (__CORTEX_M0)
+  #include "core_cm0.h"
+#elif defined (__CORTEX_M0PLUS)
+  #include "core_cm0plus.h"
+#else
+  #error "Missing __CORTEX_Mx definition"
+#endif
+
+#include "rt_TypeDef.h"
+#include "RTX_Conf.h"
+#include "rt_System.h"
+#include "rt_Task.h"
+#include "rt_Event.h"
+#include "rt_List.h"
+#include "rt_Time.h"
+#include "rt_Mutex.h"
+#include "rt_Semaphore.h"
+#include "rt_Mailbox.h"
+#include "rt_MemBox.h"
+#include "rt_HAL_CM.h"
+
+#define os_thread_cb OS_TCB
+
+#include "cmsis_os.h"
+
+#if (osFeature_Signals != 16)
+#error Invalid "osFeature_Signals" value!
+#endif
+#if (osFeature_Semaphore > 65535)
+#error Invalid "osFeature_Semaphore" value!
+#endif
+#if (osFeature_Wait != 0)
+#error osWait not supported!
+#endif
+
+
+// ==== Enumeration, structures, defines ====
+
+// Service Calls defines
+
+#if defined (__CC_ARM)          /* ARM Compiler */
+
+#define __NO_RETURN __declspec(noreturn)
+
+#define osEvent_type       osEvent
+#define osEvent_ret_status ret
+#define osEvent_ret_value  ret
+#define osEvent_ret_msg    ret
+#define osEvent_ret_mail   ret
+
+#define osCallback_type    osCallback
+#define osCallback_ret     ret
+
+#define SVC_0_1(f,t,...)                                                       \
+__svc_indirect(0) t  _##f (t(*)());                                            \
+                  t     f (void);                                              \
+__attribute__((always_inline))                                                 \
+static __inline   t __##f (void) {                                             \
+  return _##f(f);                                                              \
+}
+
+#define SVC_1_1(f,t,t1,...)                                                    \
+__svc_indirect(0) t  _##f (t(*)(t1),t1);                                       \
+                  t     f (t1 a1);                                             \
+__attribute__((always_inline))                                                 \
+static __inline   t __##f (t1 a1) {                                            \
+  return _##f(f,a1);                                                           \
+}
+
+#define SVC_2_1(f,t,t1,t2,...)                                                 \
+__svc_indirect(0) t  _##f (t(*)(t1,t2),t1,t2);                                 \
+                  t     f (t1 a1, t2 a2);                                      \
+__attribute__((always_inline))                                                 \
+static __inline   t __##f (t1 a1, t2 a2) {                                     \
+  return _##f(f,a1,a2);                                                        \
+}
+
+#define SVC_3_1(f,t,t1,t2,t3,...)                                              \
+__svc_indirect(0) t  _##f (t(*)(t1,t2,t3),t1,t2,t3);                           \
+                  t     f (t1 a1, t2 a2, t3 a3);                               \
+__attribute__((always_inline))                                                 \
+static __inline   t __##f (t1 a1, t2 a2, t3 a3) {                              \
+  return _##f(f,a1,a2,a3);                                                     \
+}
+
+#define SVC_4_1(f,t,t1,t2,t3,t4,...)                                           \
+__svc_indirect(0) t  _##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4);                     \
+                  t     f (t1 a1, t2 a2, t3 a3, t4 a4);                        \
+__attribute__((always_inline))                                                 \
+static __inline   t __##f (t1 a1, t2 a2, t3 a3, t4 a4) {                       \
+  return _##f(f,a1,a2,a3,a4);                                                  \
+}
+
+#define SVC_1_2 SVC_1_1
+#define SVC_1_3 SVC_1_1
+#define SVC_2_3 SVC_2_1
+
+#elif defined (__GNUC__)        /* GNU Compiler */
+
+#define __NO_RETURN __attribute__((noreturn))
+
+typedef uint32_t __attribute__((vector_size(8)))  ret64;
+typedef uint32_t __attribute__((vector_size(16))) ret128;
+
+#define RET_pointer    __r0
+#define RET_int32_t    __r0
+#define RET_osStatus   __r0
+#define RET_osPriority __r0
+#define RET_osEvent    {(osStatus)__r0, {(uint32_t)__r1}, {(void *)__r2}}
+#define RET_osCallback {(void *)__r0, (void *)__r1}
+
+#define osEvent_type        ret128
+#define osEvent_ret_status (ret128){ret.status}
+#define osEvent_ret_value  (ret128){ret.status, ret.value.v}
+#define osEvent_ret_msg    (ret128){ret.status, ret.value.v, (uint32_t)ret.def.message_id}
+#define osEvent_ret_mail   (ret128){ret.status, ret.value.v, (uint32_t)ret.def.mail_id}
+
+#define osCallback_type     ret64
+#define osCallback_ret     (ret64) {(uint32_t)ret.fp, (uint32_t)ret.arg}
+
+#define SVC_ArgN(n) \
+  register int __r##n __asm("r"#n);
+
+#define SVC_ArgR(n,t,a) \
+  register t   __r##n __asm("r"#n) = a;
+
+#define SVC_Arg0()                                                             \
+  SVC_ArgN(0)                                                                  \
+  SVC_ArgN(1)                                                                  \
+  SVC_ArgN(2)                                                                  \
+  SVC_ArgN(3)
+
+#define SVC_Arg1(t1)                                                           \
+  SVC_ArgR(0,t1,a1)                                                            \
+  SVC_ArgN(1)                                                                  \
+  SVC_ArgN(2)                                                                  \
+  SVC_ArgN(3)
+
+#define SVC_Arg2(t1,t2)                                                        \
+  SVC_ArgR(0,t1,a1)                                                            \
+  SVC_ArgR(1,t2,a2)                                                            \
+  SVC_ArgN(2)                                                                  \
+  SVC_ArgN(3)
+
+#define SVC_Arg3(t1,t2,t3)                                                     \
+  SVC_ArgR(0,t1,a1)                                                            \
+  SVC_ArgR(1,t2,a2)                                                            \
+  SVC_ArgR(2,t3,a3)                                                            \
+  SVC_ArgN(3)
+
+#define SVC_Arg4(t1,t2,t3,t4)                                                  \
+  SVC_ArgR(0,t1,a1)                                                            \
+  SVC_ArgR(1,t2,a2)                                                            \
+  SVC_ArgR(2,t3,a3)                                                            \
+  SVC_ArgR(3,t4,a4)
+
+#if (defined (__CORTEX_M0)) || defined (__CORTEX_M0PLUS)
+#define SVC_Call(f)                                                            \
+  __asm volatile                                                                 \
+  (                                                                            \
+    "ldr r7,="#f"\n\t"                                                         \
+    "mov r12,r7\n\t"                                                           \
+    "svc 0"                                                                    \
+    :               "=r" (__r0), "=r" (__r1), "=r" (__r2), "=r" (__r3)         \
+    :                "r" (__r0),  "r" (__r1),  "r" (__r2),  "r" (__r3)         \
+    : "r7", "r12", "lr", "cc"                                                  \
+  );
+#else
+#define SVC_Call(f)                                                            \
+  __asm volatile                                                                 \
+  (                                                                            \
+    "ldr r12,="#f"\n\t"                                                        \
+    "svc 0"                                                                    \
+    :               "=r" (__r0), "=r" (__r1), "=r" (__r2), "=r" (__r3)         \
+    :                "r" (__r0),  "r" (__r1),  "r" (__r2),  "r" (__r3)         \
+    : "r12", "lr", "cc"                                                        \
+  );
+#endif
+
+#define SVC_0_1(f,t,rv)                                                        \
+__attribute__((always_inline))                                                 \
+static inline  t __##f (void) {                                                \
+  SVC_Arg0();                                                                  \
+  SVC_Call(f);                                                                 \
+  return (t) rv;                                                               \
+}
+
+#define SVC_1_1(f,t,t1,rv)                                                     \
+__attribute__((always_inline))                                                 \
+static inline  t __##f (t1 a1) {                                               \
+  SVC_Arg1(t1);                                                                \
+  SVC_Call(f);                                                                 \
+  return (t) rv;                                                               \
+}
+
+#define SVC_2_1(f,t,t1,t2,rv)                                                  \
+__attribute__((always_inline))                                                 \
+static inline  t __##f (t1 a1, t2 a2) {                                        \
+  SVC_Arg2(t1,t2);                                                             \
+  SVC_Call(f);                                                                 \
+  return (t) rv;                                                               \
+}
+
+#define SVC_3_1(f,t,t1,t2,t3,rv)                                               \
+__attribute__((always_inline))                                                 \
+static inline  t __##f (t1 a1, t2 a2, t3 a3) {                                 \
+  SVC_Arg3(t1,t2,t3);                                                          \
+  SVC_Call(f);                                                                 \
+  return (t) rv;                                                               \
+}
+
+#define SVC_4_1(f,t,t1,t2,t3,t4,rv)                                            \
+__attribute__((always_inline))                                                 \
+static inline  t __##f (t1 a1, t2 a2, t3 a3, t4 a4) {                          \
+  SVC_Arg4(t1,t2,t3,t4);                                                       \
+  SVC_Call(f);                                                                 \
+  return (t) rv;                                                               \
+}
+
+#define SVC_1_2 SVC_1_1
+#define SVC_1_3 SVC_1_1
+#define SVC_2_3 SVC_2_1
+
+#elif defined (__ICCARM__)      /* IAR Compiler */
+
+#define __NO_RETURN __noreturn
+
+#define RET_osEvent        "=r"(ret.status), "=r"(ret.value), "=r"(ret.def)
+#define RET_osCallback     "=r"(ret.fp), "=r"(ret.arg)
+
+#define osEvent_type       osEvent
+#define osEvent_ret_status ret
+#define osEvent_ret_value  ret
+#define osEvent_ret_msg    ret
+#define osEvent_ret_mail   ret
+
+#define osCallback_type    uint64_t
+#define osCallback_ret     ((uint64_t)ret.fp | ((uint64_t)ret.arg)<<32)
+
+#define SVC_Setup(f)                                                           \
+  __asm(                                                                         \
+    "mov r12,%0\n"                                                             \
+    :: "r"(&f): "r12"                                                          \
+  );
+
+#define SVC_Ret3()                                                             \
+  __asm(                                                                         \
+    "ldr r0,[sp,#0]\n"                                                         \
+    "ldr r1,[sp,#4]\n"                                                         \
+    "ldr r2,[sp,#8]\n"                                                         \
+  );
+
+#define SVC_0_1(f,t,...)                                                       \
+t f (void);                                                                    \
+_Pragma("swi_number=0") __swi t _##f (void);                                   \
+static inline t __##f (void) {                                                 \
+  SVC_Setup(f);                                                                \
+  return _##f();                                                               \
+}
+
+#define SVC_1_1(f,t,t1,...)                                                    \
+t f (t1 a1);                                                                   \
+_Pragma("swi_number=0") __swi t _##f (t1 a1);                                  \
+static inline t __##f (t1 a1) {                                                \
+  SVC_Setup(f);                                                                \
+  return _##f(a1);                                                             \
+}
+
+#define SVC_2_1(f,t,t1,t2,...)                                                 \
+t f (t1 a1, t2 a2);                                                            \
+_Pragma("swi_number=0") __swi t _##f (t1 a1, t2 a2);                           \
+static inline t __##f (t1 a1, t2 a2) {                                         \
+  SVC_Setup(f);                                                                \
+  return _##f(a1,a2);                                                          \
+}
+
+#define SVC_3_1(f,t,t1,t2,t3,...)                                              \
+t f (t1 a1, t2 a2, t3 a3);                                                     \
+_Pragma("swi_number=0") __swi t _##f (t1 a1, t2 a2, t3 a3);                    \
+static inline t __##f (t1 a1, t2 a2, t3 a3) {                                  \
+  SVC_Setup(f);                                                                \
+  return _##f(a1,a2,a3);                                                       \
+}
+
+#define SVC_4_1(f,t,t1,t2,t3,t4,...)                                           \
+t f (t1 a1, t2 a2, t3 a3, t4 a4);                                              \
+_Pragma("swi_number=0") __swi t _##f (t1 a1, t2 a2, t3 a3, t4 a4);             \
+static inline t __##f (t1 a1, t2 a2, t3 a3, t4 a4) {                           \
+  SVC_Setup(f);                                                                \
+  return _##f(a1,a2,a3,a4);                                                    \
+}
+
+#define SVC_1_2(f,t,t1,rr)                                                     \
+uint64_t f (t1 a1);                                                            \
+_Pragma("swi_number=0") __swi uint64_t _##f (t1 a1);                           \
+static inline t __##f (t1 a1) {                                                \
+  t ret;                                                                       \
+  SVC_Setup(f);                                                                \
+  _##f(a1);                                                                    \
+  __asm("" : rr : :);                                                            \
+  return ret;                                                                  \
+}
+
+#define SVC_1_3(f,t,t1,rr)                                                     \
+t f (t1 a1);                                                                   \
+void f##_ (t1 a1) {                                                            \
+  f(a1);                                                                       \
+  SVC_Ret3();                                                                  \
+}                                                                              \
+_Pragma("swi_number=0") __swi void _##f (t1 a1);                               \
+static inline t __##f (t1 a1) {                                                \
+  t ret;                                                                       \
+  SVC_Setup(f##_);                                                             \
+  _##f(a1);                                                                    \
+  __asm("" : rr : :);                                                            \
+  return ret;                                                                  \
+}
+
+#define SVC_2_3(f,t,t1,t2,rr)                                                  \
+t f (t1 a1, t2 a2);                                                            \
+void f##_ (t1 a1, t2 a2) {                                                     \
+  f(a1,a2);                                                                    \
+  SVC_Ret3();                                                                  \
+}                                                                              \
+_Pragma("swi_number=0") __swi void _##f (t1 a1, t2 a2);                        \
+static inline t __##f (t1 a1, t2 a2) {                                         \
+  t ret;                                                                       \
+  SVC_Setup(f##_);                                                             \
+  _##f(a1,a2);                                                                 \
+  __asm("" : rr : :);                                                            \
+  return ret;                                                                  \
+}
+
+#endif
+
+
+// Callback structure
+typedef struct {
+  void *fp;             // Function pointer
+  void *arg;            // Function argument
+} osCallback;
+
+
+// OS Section definitions
+#ifdef OS_SECTIONS_LINK_INFO
+extern const uint32_t  os_section_id$$Base;
+extern const uint32_t  os_section_id$$Limit;
+#endif
+
+// OS Timers external resources
+extern osThreadDef_t   os_thread_def_osTimerThread;
+extern osThreadId      osThreadId_osTimerThread;
+extern osMessageQDef_t os_messageQ_def_osTimerMessageQ;
+extern osMessageQId    osMessageQId_osTimerMessageQ;
+
+
+// ==== Helper Functions ====
+
+/// Convert timeout in millisec to system ticks
+static uint32_t rt_ms2tick (uint32_t millisec) {
+  uint32_t tick;
+
+  if (millisec == osWaitForever) return 0xFFFF; // Indefinite timeout
+  if (millisec > 4000000) return 0xFFFE;        // Max ticks supported
+
+  tick = ((1000 * millisec) + os_clockrate - 1)  / os_clockrate;
+  if (tick > 0xFFFE) return 0xFFFE;
+
+  return tick;
+}
+
+/// Convert Thread ID to TCB pointer
+static P_TCB rt_tid2ptcb (osThreadId thread_id) {
+  P_TCB ptcb;
+
+  if (thread_id == NULL) return NULL;
+
+  if ((uint32_t)thread_id & 3) return NULL;
+
+#ifdef OS_SECTIONS_LINK_INFO
+  if ((os_section_id$$Base != 0) && (os_section_id$$Limit != 0)) {
+    if (thread_id  < (osThreadId)os_section_id$$Base)  return NULL;
+    if (thread_id >= (osThreadId)os_section_id$$Limit) return NULL;
+  }
+#endif
+
+  ptcb = thread_id;
+
+  if (ptcb->cb_type != TCB) return NULL;
+
+  return ptcb;
+}
+
+/// Convert ID pointer to Object pointer
+static void *rt_id2obj (void *id) {
+
+  if ((uint32_t)id & 3) return NULL;
+
+#ifdef OS_SECTIONS_LINK_INFO
+  if ((os_section_id$$Base != 0) && (os_section_id$$Limit != 0)) {
+    if (id  < (void *)os_section_id$$Base)  return NULL;
+    if (id >= (void *)os_section_id$$Limit) return NULL;
+  }
+#endif
+
+  return id;
+}
+
+
+// ==== Kernel Control ====
+
+uint8_t os_initialized;                         // Kernel Initialized flag
+uint8_t os_running;                             // Kernel Running flag
+
+// Kernel Control Service Calls declarations
+SVC_0_1(svcKernelInitialize, osStatus, RET_osStatus)
+SVC_0_1(svcKernelStart,      osStatus, RET_osStatus)
+SVC_0_1(svcKernelRunning,    int32_t,  RET_int32_t)
+
+extern void  sysThreadError   (osStatus status);
+osThreadId   svcThreadCreate  (osThreadDef_t *thread_def, void *argument);
+osMessageQId svcMessageCreate (osMessageQDef_t *queue_def, osThreadId thread_id);
+
+// Kernel Control Service Calls
+
+/// Initialize the RTOS Kernel for creating objects
+osStatus svcKernelInitialize (void) {
+  if (os_initialized) return osOK;
+
+  rt_sys_init();                                // RTX System Initialization
+  os_tsk.run->prio = 255;                       // Highest priority
+
+  sysThreadError(osOK);
+
+  os_initialized = 1;
+
+  return osOK;
+}
+
+/// Start the RTOS Kernel
+osStatus svcKernelStart (void) {
+
+  if (os_running) return osOK;
+
+  // Create OS Timers resources (Message Queue & Thread)
+  osMessageQId_osTimerMessageQ = svcMessageCreate (&os_messageQ_def_osTimerMessageQ, NULL);
+  osThreadId_osTimerThread = svcThreadCreate(&os_thread_def_osTimerThread, NULL);
+
+  rt_tsk_prio(0, 0);                            // Lowest priority
+  __set_PSP(os_tsk.run->tsk_stack + 8*4);       // New context
+  os_tsk.run = NULL;                            // Force context switch
+
+  rt_sys_start();
+
+  os_running = 1;
+
+  return osOK;
+}
+
+/// Check if the RTOS kernel is already started
+int32_t svcKernelRunning(void) {
+  return os_running;
+}
+
+// Kernel Control Public API
+
+/// Initialize the RTOS Kernel for creating objects
+osStatus osKernelInitialize (void) {
+  if (__get_IPSR() != 0) return osErrorISR;     // Not allowed in ISR
+  if ((__get_CONTROL() & 1) == 0) {             // Privileged mode
+    return   svcKernelInitialize();
+  } else {
+    return __svcKernelInitialize();
+  }
+}
+
+/// Start the RTOS Kernel
+osStatus osKernelStart (void) {
+  uint32_t stack[8];
+
+  if (__get_IPSR() != 0) return osErrorISR;     // Not allowed in ISR
+  switch (__get_CONTROL() & 0x03) {
+    case 0x00:                                  // Privileged Thread mode & MSP
+      __set_PSP((uint32_t)(stack + 8));         // Initial PSP
+      if (os_flags & 1) {
+        __set_CONTROL(0x02);                    // Set Privileged Thread mode & PSP
+      } else {
+        __set_CONTROL(0x03);                    // Set Unprivileged Thread mode & PSP
+      }
+      __DSB();
+      __ISB();
+      break;
+    case 0x01:                                  // Unprivileged Thread mode & MSP
+      return osErrorOS;
+    case 0x02:                                  // Privileged Thread mode & PSP
+      if ((os_flags & 1) == 0) {                // Unprivileged Thread mode requested
+        __set_CONTROL(0x03);                    // Set Unprivileged Thread mode & PSP
+        __DSB();
+        __ISB();
+      }
+      break;
+    case 0x03:                                  // Unprivileged Thread mode & PSP
+      if  (os_flags & 1) return osErrorOS;      // Privileged Thread mode requested
+      break;
+  }
+  return __svcKernelStart();
+}
+
+/// Check if the RTOS kernel is already started
+int32_t osKernelRunning(void) {
+  if ((__get_IPSR() != 0) || ((__get_CONTROL() & 1) == 0)) {
+    // in ISR or Privileged
+    return os_running;
+  } else {
+    return __svcKernelRunning();
+  }
+}
+
+
+// ==== Thread Management ====
+
+__NO_RETURN void osThreadExit (void);
+
+// Thread Service Calls declarations
+SVC_2_1(svcThreadCreate,      osThreadId, osThreadDef_t *, void *,     RET_pointer)
+SVC_0_1(svcThreadGetId,       osThreadId,                              RET_pointer)
+SVC_1_1(svcThreadTerminate,   osStatus,   osThreadId,                  RET_osStatus)
+SVC_0_1(svcThreadYield,       osStatus,                                RET_osStatus)
+SVC_2_1(svcThreadSetPriority, osStatus,   osThreadId,      osPriority, RET_osStatus)
+SVC_1_1(svcThreadGetPriority, osPriority, osThreadId,                  RET_osPriority)
+
+// Thread Service Calls
+extern OS_TID rt_get_TID (void);
+extern void   rt_init_context (P_TCB p_TCB, U8 priority, FUNCP task_body);
+
+/// Create a thread and add it to Active Threads and set it to state READY
+osThreadId svcThreadCreate (osThreadDef_t *thread_def, void *argument) {
+  P_TCB  ptcb;
+
+  if ((thread_def == NULL) ||
+      (thread_def->pthread == NULL) ||
+      (thread_def->tpriority < osPriorityIdle) ||
+      (thread_def->tpriority > osPriorityRealtime) ||
+      (thread_def->stacksize == 0) ||
+      (thread_def->stack_pointer == NULL) ) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  U8 priority = thread_def->tpriority - osPriorityIdle + 1;
+  P_TCB task_context = &thread_def->tcb;
+
+  /* If "size != 0" use a private user provided stack. */
+  task_context->stack      = (U32*)thread_def->stack_pointer;
+  task_context->priv_stack = thread_def->stacksize;
+  /* Pass parameter 'argv' to 'rt_init_context' */
+  task_context->msg = argument;
+  /* For 'size == 0' system allocates the user stack from the memory pool. */
+  rt_init_context (task_context, priority, (FUNCP)thread_def->pthread);
+
+  /* Find a free entry in 'os_active_TCB' table. */
+  OS_TID tsk = rt_get_TID ();
+  os_active_TCB[tsk-1] = task_context;
+  task_context->task_id = tsk;
+  DBG_TASK_NOTIFY(task_context, __TRUE);
+  rt_dispatch (task_context);
+
+  ptcb = (P_TCB)os_active_TCB[tsk - 1];         // TCB pointer
+
+  *((uint32_t *)ptcb->tsk_stack + 13) = (uint32_t)osThreadExit;
+
+  return ptcb;
+}
+
+/// Return the thread ID of the current running thread
+osThreadId svcThreadGetId (void) {
+  OS_TID tsk;
+
+  tsk = rt_tsk_self();
+  if (tsk == 0) return NULL;
+  return (P_TCB)os_active_TCB[tsk - 1];
+}
+
+/// Terminate execution of a thread and remove it from ActiveThreads
+osStatus svcThreadTerminate (osThreadId thread_id) {
+  OS_RESULT res;
+  P_TCB     ptcb;
+
+  ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer
+  if (ptcb == NULL) return osErrorParameter;
+
+  res = rt_tsk_delete(ptcb->task_id);           // Delete task
+
+  if (res == OS_R_NOK) return osErrorResource;  // Delete task failed
+
+  return osOK;
+}
+
+/// Pass control to next thread that is in state READY
+osStatus svcThreadYield (void) {
+  rt_tsk_pass();                                // Pass control to next task
+  return osOK;
+}
+
+/// Change priority of an active thread
+osStatus svcThreadSetPriority (osThreadId thread_id, osPriority priority) {
+  OS_RESULT res;
+  P_TCB     ptcb;
+
+  ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer
+  if (ptcb == NULL) return osErrorParameter;
+
+  if ((priority < osPriorityIdle) || (priority > osPriorityRealtime)) {
+    return osErrorValue;
+  }
+
+  res = rt_tsk_prio(                            // Change task priority
+    ptcb->task_id,                              // Task ID
+    priority - osPriorityIdle + 1               // New task priority
+  );
+
+  if (res == OS_R_NOK) return osErrorResource;  // Change task priority failed
+
+  return osOK;
+}
+
+/// Get current priority of an active thread
+osPriority svcThreadGetPriority (osThreadId thread_id) {
+  P_TCB ptcb;
+
+  ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer
+  if (ptcb == NULL) return osPriorityError;
+
+  return (osPriority)(ptcb->prio - 1 + osPriorityIdle);
+}
+
+
+// Thread Public API
+
+/// Create a thread and add it to Active Threads and set it to state READY
+osThreadId osThreadCreate (osThreadDef_t *thread_def, void *argument) {
+  if (__get_IPSR() != 0) return NULL;           // Not allowed in ISR
+  if (((__get_CONTROL() & 1) == 0) && (os_running == 0)) {
+    // Privileged and not running
+    return   svcThreadCreate(thread_def, argument);
+  } else {
+    return __svcThreadCreate(thread_def, argument);
+  }
+}
+
+/// Return the thread ID of the current running thread
+osThreadId osThreadGetId (void) {
+  if (__get_IPSR() != 0) return NULL;           // Not allowed in ISR
+  return __svcThreadGetId();
+}
+
+/// Terminate execution of a thread and remove it from ActiveThreads
+osStatus osThreadTerminate (osThreadId thread_id) {
+  if (__get_IPSR() != 0) return osErrorISR;     // Not allowed in ISR
+  return __svcThreadTerminate(thread_id);
+}
+
+/// Pass control to next thread that is in state READY
+osStatus osThreadYield (void) {
+  if (__get_IPSR() != 0) return osErrorISR;     // Not allowed in ISR
+  return __svcThreadYield();
+}
+
+/// Change priority of an active thread
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority) {
+  if (__get_IPSR() != 0) return osErrorISR;     // Not allowed in ISR
+  return __svcThreadSetPriority(thread_id, priority);
+}
+
+/// Get current priority of an active thread
+osPriority osThreadGetPriority (osThreadId thread_id) {
+  if (__get_IPSR() != 0) return osPriorityError;// Not allowed in ISR
+  return __svcThreadGetPriority(thread_id);
+}
+
+/// INTERNAL - Not Public
+/// Auto Terminate Thread on exit (used implicitly when thread exists)
+__NO_RETURN void osThreadExit (void) {
+  __svcThreadTerminate(__svcThreadGetId());
+  for (;;);                                     // Should never come here
+}
+
+
+// ==== Generic Wait Functions ====
+
+// Generic Wait Service Calls declarations
+SVC_1_1(svcDelay,           osStatus, uint32_t, RET_osStatus)
+#if osFeature_Wait != 0
+SVC_1_3(svcWait,  os_InRegs osEvent,  uint32_t, RET_osEvent)
+#endif
+
+// Generic Wait Service Calls
+
+/// Wait for Timeout (Time Delay)
+osStatus svcDelay (uint32_t millisec) {
+  if (millisec == 0) return osOK;
+  rt_dly_wait(rt_ms2tick(millisec));
+  return osEventTimeout;
+}
+
+/// Wait for Signal, Message, Mail, or Timeout
+#if osFeature_Wait != 0
+os_InRegs osEvent_type svcWait (uint32_t millisec) {
+  osEvent ret;
+
+  if (millisec == 0) {
+    ret.status = osOK;
+    return osEvent_ret_status;
+  }
+
+  /* To Do: osEventSignal, osEventMessage, osEventMail */
+  rt_dly_wait(rt_ms2tick(millisec));
+  ret.status = osEventTimeout;
+
+  return osEvent_ret_status;
+}
+#endif
+
+
+// Generic Wait API
+
+/// Wait for Timeout (Time Delay)
+osStatus osDelay (uint32_t millisec) {
+  if (__get_IPSR() != 0) return osErrorISR;     // Not allowed in ISR
+  return __svcDelay(millisec);
+}
+
+/// Wait for Signal, Message, Mail, or Timeout
+os_InRegs osEvent osWait (uint32_t millisec) {
+  osEvent ret;
+
+#if osFeature_Wait == 0
+  ret.status = osErrorOS;
+  return ret;
+#else
+  if (__get_IPSR() != 0) {                      // Not allowed in ISR
+    ret.status = osErrorISR;
+    return ret;
+  }
+  return __svcWait(millisec);
+#endif
+}
+
+
+// ==== Timer Management ====
+
+// Timer definitions
+#define osTimerInvalid  0
+#define osTimerStopped  1
+#define osTimerRunning  2
+
+// Timer structures
+
+typedef struct os_timer_cb_ {                   // Timer Control Block
+  struct os_timer_cb_ *next;                    // Pointer to next active Timer
+  uint8_t             state;                    // Timer State
+  uint8_t              type;                    // Timer Type (Periodic/One-shot)
+  uint16_t         reserved;                    // Reserved
+  uint16_t             tcnt;                    // Timer Delay Count
+  uint16_t             icnt;                    // Timer Initial Count
+  void                 *arg;                    // Timer Function Argument
+  osTimerDef_t       *timer;                    // Pointer to Timer definition
+} os_timer_cb;
+
+// Timer variables
+os_timer_cb *os_timer_head;                     // Pointer to first active Timer
+
+
+// Timer Helper Functions
+
+// Insert Timer into the list sorted by time
+static void rt_timer_insert (os_timer_cb *pt, uint32_t tcnt) {
+  os_timer_cb *p, *prev;
+
+  prev = NULL;
+  p = os_timer_head;
+  while (p != NULL) {
+    if (tcnt < p->tcnt) break;
+    tcnt -= p->tcnt;
+    prev = p;
+    p = p->next;
+  }
+  pt->next = p;
+  pt->tcnt = (uint16_t)tcnt;
+  if (p != NULL) {
+    p->tcnt -= pt->tcnt;
+  }
+  if (prev != NULL) {
+    prev->next = pt;
+  } else {
+    os_timer_head = pt;
+  }
+}
+
+// Remove Timer from the list
+static int rt_timer_remove (os_timer_cb *pt) {
+  os_timer_cb *p, *prev;
+
+  prev = NULL;
+  p = os_timer_head;
+  while (p != NULL) {
+    if (p == pt) break;
+    prev = p;
+    p = p->next;
+  }
+  if (p == NULL) return -1;
+  if (prev != NULL) {
+    prev->next = pt->next;
+  } else {
+    os_timer_head = pt->next;
+  }
+  if (pt->next != NULL) {
+    pt->next->tcnt += pt->tcnt;
+  }
+
+  return 0;
+}
+
+
+// Timer Service Calls declarations
+SVC_3_1(svcTimerCreate,           osTimerId,  osTimerDef_t *, os_timer_type, void *, RET_pointer)
+SVC_2_1(svcTimerStart,            osStatus,   osTimerId,      uint32_t,              RET_osStatus)
+SVC_1_1(svcTimerStop,             osStatus,   osTimerId,                             RET_osStatus)
+SVC_1_1(svcTimerDelete,           osStatus,   osTimerId,                             RET_osStatus)
+SVC_1_2(svcTimerCall,   os_InRegs osCallback, osTimerId,                             RET_osCallback)
+
+// Timer Management Service Calls
+
+/// Create timer
+osTimerId svcTimerCreate (osTimerDef_t *timer_def, os_timer_type type, void *argument) {
+  os_timer_cb *pt;
+
+  if ((timer_def == NULL) || (timer_def->ptimer == NULL)) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  pt = timer_def->timer;
+  if (pt == NULL) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  if ((type != osTimerOnce) && (type != osTimerPeriodic)) {
+    sysThreadError(osErrorValue);
+    return NULL;
+  }
+
+  if (osThreadId_osTimerThread == NULL) {
+    sysThreadError(osErrorResource);
+    return NULL;
+  }
+
+  if (pt->state != osTimerInvalid){
+    sysThreadError(osErrorResource);
+    return NULL;
+  }
+
+  pt->state = osTimerStopped;
+  pt->type  =  (uint8_t)type;
+  pt->arg   = argument;
+  pt->timer = timer_def;
+
+  return (osTimerId)pt;
+}
+
+/// Start or restart timer
+osStatus svcTimerStart (osTimerId timer_id, uint32_t millisec) {
+  os_timer_cb *pt;
+  uint32_t     tcnt;
+
+  pt = rt_id2obj(timer_id);
+  if (pt == NULL) return osErrorParameter;
+
+  tcnt = rt_ms2tick(millisec);
+  if (tcnt == 0) return osErrorValue;
+
+  switch (pt->state) {
+    case osTimerRunning:
+      if (rt_timer_remove(pt) != 0) {
+        return osErrorResource;
+      }
+      break;
+    case osTimerStopped:
+      pt->state = osTimerRunning;
+      pt->icnt  = (uint16_t)tcnt;
+      break;
+    default:
+      return osErrorResource;
+  }
+
+  rt_timer_insert(pt, tcnt);
+
+  return osOK;
+}
+
+/// Stop timer
+osStatus svcTimerStop (osTimerId timer_id) {
+  os_timer_cb *pt;
+
+  pt = rt_id2obj(timer_id);
+  if (pt == NULL) return osErrorParameter;
+
+  if (pt->state != osTimerRunning) return osErrorResource;
+
+  pt->state = osTimerStopped;
+
+  if (rt_timer_remove(pt) != 0) {
+    return osErrorResource;
+  }
+
+  return osOK;
+}
+
+/// Delete timer
+osStatus svcTimerDelete (osTimerId timer_id) {
+  os_timer_cb *pt;
+
+  pt = rt_id2obj(timer_id);
+  if (pt == NULL) return osErrorParameter;
+
+  switch (pt->state) {
+    case osTimerRunning:
+      rt_timer_remove(pt);
+      break;
+    case osTimerStopped:
+      break;
+    default:
+      return osErrorResource;
+  }
+
+  pt->state = osTimerInvalid;
+
+  return osOK;
+}
+
+/// Get timer callback parameters
+os_InRegs osCallback_type svcTimerCall (osTimerId timer_id) {
+  os_timer_cb *pt;
+  osCallback   ret;
+
+  pt = rt_id2obj(timer_id);
+  if (pt == NULL) {
+    ret.fp  = NULL;
+    ret.arg = NULL;
+    return osCallback_ret;
+  }
+
+  ret.fp  = (void *)pt->timer->ptimer;
+  ret.arg = pt->arg;
+
+  return osCallback_ret;
+}
+
+static __INLINE osStatus isrMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
+
+/// Timer Tick (called each SysTick)
+void sysTimerTick (void) {
+  os_timer_cb *pt, *p;
+
+  p = os_timer_head;
+  if (p == NULL) return;
+
+  p->tcnt--;
+  while ((p != NULL) && (p->tcnt == 0)) {
+    pt = p;
+    p = p->next;
+    os_timer_head = p;
+    isrMessagePut(osMessageQId_osTimerMessageQ, (uint32_t)pt, 0);
+    if (pt->type == osTimerPeriodic) {
+      rt_timer_insert(pt, pt->icnt);
+    } else {
+      pt->state = osTimerStopped;
+    }
+  }
+}
+
+
+// Timer Management Public API
+
+/// Create timer
+osTimerId osTimerCreate (osTimerDef_t *timer_def, os_timer_type type, void *argument) {
+  if (__get_IPSR() != 0) return NULL;           // Not allowed in ISR
+  if (((__get_CONTROL() & 1) == 0) && (os_running == 0)) {
+    // Privileged and not running
+    return   svcTimerCreate(timer_def, type, argument);
+  } else {
+    return __svcTimerCreate(timer_def, type, argument);
+  }
+}
+
+/// Start or restart timer
+osStatus osTimerStart (osTimerId timer_id, uint32_t millisec) {
+  if (__get_IPSR() != 0) return osErrorISR;     // Not allowed in ISR
+  return __svcTimerStart(timer_id, millisec);
+}
+
+/// Stop timer
+osStatus osTimerStop (osTimerId timer_id) {
+  if (__get_IPSR() != 0) return osErrorISR;     // Not allowed in ISR
+  return __svcTimerStop(timer_id);
+}
+
+/// Delete timer
+osStatus osTimerDelete (osTimerId timer_id) {
+  if (__get_IPSR() != 0) return osErrorISR;     // Not allowed in ISR
+  return __svcTimerDelete(timer_id);
+}
+
+/// INTERNAL - Not Public
+/// Get timer callback parameters (used by OS Timer Thread)
+os_InRegs osCallback osTimerCall (osTimerId timer_id) {
+  return __svcTimerCall(timer_id);
+}
+
+
+// Timer Thread
+__NO_RETURN void osTimerThread (void const *argument) {
+  osCallback cb;
+  osEvent    evt;
+
+  for (;;) {
+    evt = osMessageGet(osMessageQId_osTimerMessageQ, osWaitForever);
+    if (evt.status == osEventMessage) {
+      cb = osTimerCall(evt.value.p);
+      if (cb.fp != NULL) {
+        (*(os_ptimer)cb.fp)(cb.arg);
+      }
+    }
+  }
+}
+
+
+// ==== Signal Management ====
+
+// Signal Service Calls declarations
+SVC_2_1(svcSignalSet,             int32_t, osThreadId, int32_t,  RET_int32_t)
+SVC_2_1(svcSignalClear,           int32_t, osThreadId, int32_t,  RET_int32_t)
+SVC_1_1(svcSignalGet,             int32_t, osThreadId,           RET_int32_t)
+SVC_2_3(svcSignalWait,  os_InRegs osEvent, int32_t,    uint32_t, RET_osEvent)
+
+// Signal Service Calls
+
+/// Set the specified Signal Flags of an active thread
+int32_t svcSignalSet (osThreadId thread_id, int32_t signals) {
+  P_TCB   ptcb;
+  int32_t sig;
+
+  ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer
+  if (ptcb == NULL) return 0x80000000;
+
+  if (signals & (0xFFFFFFFF << osFeature_Signals)) return 0x80000000;
+
+  sig = ptcb->events;                           // Previous signal flags
+
+  rt_evt_set(signals, ptcb->task_id);           // Set event flags
+
+  return sig;
+}
+
+/// Clear the specified Signal Flags of an active thread
+int32_t svcSignalClear (osThreadId thread_id, int32_t signals) {
+  P_TCB   ptcb;
+  int32_t sig;
+
+  ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer
+  if (ptcb == NULL) return 0x80000000;
+
+  if (signals & (0xFFFFFFFF << osFeature_Signals)) return 0x80000000;
+
+  sig = ptcb->events;                           // Previous signal flags
+
+  rt_evt_clr(signals, ptcb->task_id);           // Clear event flags
+
+  return sig;
+}
+
+/// Get Signal Flags status of an active thread
+int32_t svcSignalGet (osThreadId thread_id) {
+  P_TCB ptcb;
+
+  ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer
+  if (ptcb == NULL) return 0x80000000;
+
+  return ptcb->events;                          // Return event flags
+}
+
+/// Wait for one or more Signal Flags to become signaled for the current RUNNING thread
+os_InRegs osEvent_type svcSignalWait (int32_t signals, uint32_t millisec) {
+  OS_RESULT res;
+  osEvent   ret;
+
+  if (signals & (0xFFFFFFFF << osFeature_Signals)) {
+    ret.status = osErrorValue;
+    return osEvent_ret_status;
+  }
+
+  if (signals != 0) {                           // Wait for all specified signals
+    res = rt_evt_wait(signals, rt_ms2tick(millisec), __TRUE);
+  } else {                                      // Wait for any signal
+    res = rt_evt_wait(0xFFFF,  rt_ms2tick(millisec), __FALSE);
+  }
+
+  if (res == OS_R_EVT) {
+    ret.status = osEventSignal;
+    ret.value.signals = signals ? signals : os_tsk.run->waits;
+  } else {
+    ret.status = millisec ? osEventTimeout : osOK;
+    ret.value.signals = 0;
+  }
+
+  return osEvent_ret_value;
+}
+
+
+// Signal ISR Calls
+
+/// Set the specified Signal Flags of an active thread
+static __INLINE int32_t isrSignalSet (osThreadId thread_id, int32_t signals) {
+  P_TCB   ptcb;
+  int32_t sig;
+
+  ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer
+  if (ptcb == NULL) return 0x80000000;
+
+  if (signals & (0xFFFFFFFF << osFeature_Signals)) return 0x80000000;
+
+  sig = ptcb->events;                           // Previous signal flags
+
+  isr_evt_set(signals, ptcb->task_id);          // Set event flags
+
+  return sig;
+}
+
+
+// Signal Public API
+
+/// Set the specified Signal Flags of an active thread
+int32_t osSignalSet (osThreadId thread_id, int32_t signals) {
+  if (__get_IPSR() != 0) {                      // in ISR
+    return   isrSignalSet(thread_id, signals);
+  } else {                                      // in Thread
+    return __svcSignalSet(thread_id, signals);
+  }
+}
+
+/// Clear the specified Signal Flags of an active thread
+int32_t osSignalClear (osThreadId thread_id, int32_t signals) {
+  if (__get_IPSR() != 0) return osErrorISR;     // Not allowed in ISR
+  return __svcSignalClear(thread_id, signals);
+}
+
+/// Get Signal Flags status of an active thread
+int32_t osSignalGet (osThreadId thread_id) {
+  if (__get_IPSR() != 0) return osErrorISR;     // Not allowed in ISR
+  return __svcSignalGet(thread_id);
+}
+
+/// Wait for one or more Signal Flags to become signaled for the current RUNNING thread
+os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec) {
+  osEvent ret;
+
+  if (__get_IPSR() != 0) {                      // Not allowed in ISR
+    ret.status = osErrorISR;
+    return ret;
+  }
+  return __svcSignalWait(signals, millisec);
+}
+
+
+// ==== Mutex Management ====
+
+// Mutex Service Calls declarations
+SVC_1_1(svcMutexCreate,  osMutexId, osMutexDef_t *,           RET_pointer)
+SVC_2_1(svcMutexWait,    osStatus,  osMutexId,      uint32_t, RET_osStatus)
+SVC_1_1(svcMutexRelease, osStatus,  osMutexId,                RET_osStatus)
+SVC_1_1(svcMutexDelete,  osStatus,  osMutexId,                RET_osStatus)
+
+// Mutex Service Calls
+
+/// Create and Initialize a Mutex object
+osMutexId svcMutexCreate (osMutexDef_t *mutex_def) {
+  OS_ID mut;
+
+  if (mutex_def == NULL) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  mut = mutex_def->mutex;
+  if (mut == NULL) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  if (((P_MUCB)mut)->cb_type != 0) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  rt_mut_init(mut);                             // Initialize Mutex
+
+  return mut;
+}
+
+/// Wait until a Mutex becomes available
+osStatus svcMutexWait (osMutexId mutex_id, uint32_t millisec) {
+  OS_ID     mut;
+  OS_RESULT res;
+
+  mut = rt_id2obj(mutex_id);
+  if (mut == NULL) return osErrorParameter;
+
+  if (((P_MUCB)mut)->cb_type != MUCB) return osErrorParameter;
+
+  res = rt_mut_wait(mut, rt_ms2tick(millisec)); // Wait for Mutex
+
+  if (res == OS_R_TMO) {
+    return (millisec ? osErrorTimeoutResource : osErrorResource);
+  }
+
+  return osOK;
+}
+
+/// Release a Mutex that was obtained with osMutexWait
+osStatus svcMutexRelease (osMutexId mutex_id) {
+  OS_ID     mut;
+  OS_RESULT res;
+
+  mut = rt_id2obj(mutex_id);
+  if (mut == NULL) return osErrorParameter;
+
+  if (((P_MUCB)mut)->cb_type != MUCB) return osErrorParameter;
+
+  res = rt_mut_release(mut);                    // Release Mutex
+
+  if (res == OS_R_NOK) return osErrorResource;  // Thread not owner or Zero Counter
+
+  return osOK;
+}
+
+/// Delete a Mutex that was created by osMutexCreate
+osStatus svcMutexDelete (osMutexId mutex_id) {
+  OS_ID mut;
+
+  mut = rt_id2obj(mutex_id);
+  if (mut == NULL) return osErrorParameter;
+
+  if (((P_MUCB)mut)->cb_type != MUCB) return osErrorParameter;
+
+  rt_mut_delete(mut);                           // Release Mutex
+
+  return osOK;
+}
+
+
+// Mutex Public API
+
+/// Create and Initialize a Mutex object
+osMutexId osMutexCreate (osMutexDef_t *mutex_def) {
+  if (__get_IPSR() != 0) return NULL;           // Not allowed in ISR
+  if (((__get_CONTROL() & 1) == 0) && (os_running == 0)) {
+    // Privileged and not running
+    return    svcMutexCreate(mutex_def);
+  } else {
+    return __svcMutexCreate(mutex_def);
+  }
+}
+
+/// Wait until a Mutex becomes available
+osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec) {
+  if (__get_IPSR() != 0) return osErrorISR;     // Not allowed in ISR
+  return __svcMutexWait(mutex_id, millisec);
+}
+
+/// Release a Mutex that was obtained with osMutexWait
+osStatus osMutexRelease (osMutexId mutex_id) {
+  if (__get_IPSR() != 0) return osErrorISR;     // Not allowed in ISR
+  return __svcMutexRelease(mutex_id);
+}
+
+/// Delete a Mutex that was created by osMutexCreate
+osStatus osMutexDelete (osMutexId mutex_id) {
+  if (__get_IPSR() != 0) return osErrorISR;     // Not allowed in ISR
+  return __svcMutexDelete(mutex_id);
+}
+
+
+// ==== Semaphore Management ====
+
+// Semaphore Service Calls declarations
+SVC_2_1(svcSemaphoreCreate,  osSemaphoreId, const osSemaphoreDef_t *,  int32_t, RET_pointer)
+SVC_2_1(svcSemaphoreWait,    int32_t,       osSemaphoreId,      uint32_t, RET_int32_t)
+SVC_1_1(svcSemaphoreRelease, osStatus,      osSemaphoreId,                RET_osStatus)
+SVC_1_1(svcSemaphoreDelete,  osStatus,            osSemaphoreId,                RET_osStatus)
+
+// Semaphore Service Calls
+
+/// Create and Initialize a Semaphore object
+osSemaphoreId svcSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) {
+  OS_ID sem;
+
+  if (semaphore_def == NULL) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  sem = semaphore_def->semaphore;
+  if (sem == NULL) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  if (((P_SCB)sem)->cb_type != 0) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  if (count > osFeature_Semaphore) {
+    sysThreadError(osErrorValue);
+    return NULL;
+  }
+
+  rt_sem_init(sem, count);                      // Initialize Semaphore
+
+  return sem;
+}
+
+/// Wait until a Semaphore becomes available
+int32_t svcSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) {
+  OS_ID     sem;
+  OS_RESULT res;
+
+  sem = rt_id2obj(semaphore_id);
+  if (sem == NULL) return -1;
+
+  if (((P_SCB)sem)->cb_type != SCB) return -1;
+
+  res = rt_sem_wait(sem, rt_ms2tick(millisec)); // Wait for Semaphore
+
+  if (res == OS_R_TMO) return 0;                // Timeout
+
+  return (((P_SCB)sem)->tokens + 1);
+}
+
+/// Release a Semaphore
+osStatus svcSemaphoreRelease (osSemaphoreId semaphore_id) {
+  OS_ID sem;
+
+  sem = rt_id2obj(semaphore_id);
+  if (sem == NULL) return osErrorParameter;
+
+  if (((P_SCB)sem)->cb_type != SCB) return osErrorParameter;
+
+  if (((P_SCB)sem)->tokens == osFeature_Semaphore) return osErrorResource;
+
+  rt_sem_send(sem);                             // Release Semaphore
+
+  return osOK;
+}
+
+/// Delete a Semaphore that was created by osSemaphoreCreate
+osStatus svcSemaphoreDelete (osSemaphoreId semaphore_id) {
+  OS_ID sem;
+
+  sem = rt_id2obj(semaphore_id);
+  if (sem == NULL) return osErrorParameter;
+
+  if (((P_SCB)sem)->cb_type != SCB) return osErrorParameter;
+
+  rt_sem_delete(sem);                           // Delete Semaphore
+
+  return osOK;
+}
+
+
+// Semaphore ISR Calls
+
+/// Release a Semaphore
+static __INLINE osStatus isrSemaphoreRelease (osSemaphoreId semaphore_id) {
+  OS_ID sem;
+
+  sem = rt_id2obj(semaphore_id);
+  if (sem == NULL) return osErrorParameter;
+
+  if (((P_SCB)sem)->cb_type != SCB) return osErrorParameter;
+
+  if (((P_SCB)sem)->tokens == osFeature_Semaphore) return osErrorResource;
+
+  isr_sem_send(sem);                            // Release Semaphore
+
+  return osOK;
+}
+
+
+// Semaphore Public API
+
+/// Create and Initialize a Semaphore object
+osSemaphoreId osSemaphoreCreate (osSemaphoreDef_t *semaphore_def, int32_t count) {
+  if (__get_IPSR() != 0) return NULL;           // Not allowed in ISR
+  if (((__get_CONTROL() & 1) == 0) && (os_running == 0)) {
+    // Privileged and not running
+    return   svcSemaphoreCreate(semaphore_def, count);
+  } else {
+    return __svcSemaphoreCreate(semaphore_def, count);
+  }
+}
+
+/// Wait until a Semaphore becomes available
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) {
+  if (__get_IPSR() != 0) return -1;             // Not allowed in ISR
+  return __svcSemaphoreWait(semaphore_id, millisec);
+}
+
+/// Release a Semaphore
+osStatus osSemaphoreRelease (osSemaphoreId semaphore_id) {
+  if (__get_IPSR() != 0) {                      // in ISR
+    return   isrSemaphoreRelease(semaphore_id);
+  } else {                                      // in Thread
+    return __svcSemaphoreRelease(semaphore_id);
+  }
+}
+
+/// Delete a Semaphore that was created by osSemaphoreCreate
+osStatus osSemaphoreDelete (osSemaphoreId semaphore_id) {
+  if (__get_IPSR() != 0) return osErrorISR;     // Not allowed in ISR
+  return __svcSemaphoreDelete(semaphore_id);
+}
+
+
+// ==== Memory Management Functions ====
+
+// Memory Management Helper Functions
+
+// Clear Memory Box (Zero init)
+static void rt_clr_box (void *box_mem, void *box) {
+  uint32_t *p, n;
+
+  if (box) {
+    p = box;
+    for (n = ((P_BM)box_mem)->blk_size; n; n -= 4) {
+      *p++ = 0;
+    }
+  }
+}
+
+// Memory Management Service Calls declarations
+SVC_1_1(svcPoolCreate, osPoolId, const osPoolDef_t *,           RET_pointer)
+SVC_2_1(sysPoolAlloc,  void *,   osPoolId,      uint32_t, RET_pointer)
+SVC_2_1(sysPoolFree,   osStatus, osPoolId,      void *,   RET_osStatus)
+
+// Memory Management Service & ISR Calls
+
+/// Create and Initialize memory pool
+osPoolId svcPoolCreate (const osPoolDef_t *pool_def) {
+  uint32_t blk_sz;
+
+  if ((pool_def == NULL) ||
+      (pool_def->pool_sz == 0) ||
+      (pool_def->item_sz == 0) ||
+      (pool_def->pool == NULL)) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  blk_sz = (pool_def->item_sz + 3) & ~3;
+
+  _init_box(pool_def->pool, sizeof(struct OS_BM) + pool_def->pool_sz * blk_sz, blk_sz);
+
+  return pool_def->pool;
+}
+
+/// Allocate a memory block from a memory pool
+void *sysPoolAlloc (osPoolId pool_id, uint32_t clr) {
+  void *ptr;
+
+  if (pool_id == NULL) return NULL;
+
+  ptr = rt_alloc_box(pool_id);
+  if (clr) {
+    rt_clr_box(pool_id, ptr);
+  }
+
+  return ptr;
+}
+
+/// Return an allocated memory block back to a specific memory pool
+osStatus sysPoolFree (osPoolId pool_id, void *block) {
+  int32_t res;
+
+  if (pool_id == NULL) return osErrorParameter;
+
+  res = rt_free_box(pool_id, block);
+  if (res != 0) return osErrorValue;
+
+  return osOK;
+}
+
+
+// Memory Management Public API
+
+/// Create and Initialize memory pool
+osPoolId osPoolCreate (osPoolDef_t *pool_def) {
+  if (__get_IPSR() != 0) return NULL;           // Not allowed in ISR
+  if (((__get_CONTROL() & 1) == 0) && (os_running == 0)) {
+    // Privileged and not running
+    return   svcPoolCreate(pool_def);
+  } else {
+    return __svcPoolCreate(pool_def);
+  }
+}
+
+/// Allocate a memory block from a memory pool
+void *osPoolAlloc (osPoolId pool_id) {
+  if ((__get_IPSR() != 0) || ((__get_CONTROL() & 1) == 0)) {    // in ISR or Privileged
+    return   sysPoolAlloc(pool_id, 0);
+  } else {                                      // in Thread
+    return __sysPoolAlloc(pool_id, 0);
+  }
+}
+
+/// Allocate a memory block from a memory pool and set memory block to zero
+void *osPoolCAlloc (osPoolId pool_id) {
+  if ((__get_IPSR() != 0) || ((__get_CONTROL() & 1) == 0)) {    // in ISR or Privileged
+    return   sysPoolAlloc(pool_id, 1);
+  } else {                                      // in Thread
+    return __sysPoolAlloc(pool_id, 1);
+  }
+}
+
+/// Return an allocated memory block back to a specific memory pool
+osStatus osPoolFree (osPoolId pool_id, void *block) {
+  if ((__get_IPSR() != 0) || ((__get_CONTROL() & 1) == 0)) {    // in ISR or Privileged
+    return   sysPoolFree(pool_id, block);
+  } else {                                      // in Thread
+    return __sysPoolFree(pool_id, block);
+  }
+}
+
+
+// ==== Message Queue Management Functions ====
+
+// Message Queue Management Service Calls declarations
+SVC_2_1(svcMessageCreate,        osMessageQId,    osMessageQDef_t *, osThreadId,           RET_pointer)
+SVC_3_1(svcMessagePut,              osStatus,     osMessageQId,      uint32_t,   uint32_t, RET_osStatus)
+SVC_2_3(svcMessageGet,    os_InRegs osEvent,      osMessageQId,      uint32_t,             RET_osEvent)
+
+// Message Queue Service Calls
+
+/// Create and Initialize Message Queue
+osMessageQId svcMessageCreate (osMessageQDef_t *queue_def, osThreadId thread_id) {
+
+  if ((queue_def == NULL) ||
+      (queue_def->queue_sz == 0) ||
+      (queue_def->pool == NULL)) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  if (((P_MCB)queue_def->pool)->cb_type != 0) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  rt_mbx_init(queue_def->pool, 4*(queue_def->queue_sz + 4));
+
+  return queue_def->pool;
+}
+
+/// Put a Message to a Queue
+osStatus svcMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {
+  OS_RESULT res;
+
+  if (queue_id == NULL) return osErrorParameter;
+
+  if (((P_MCB)queue_id)->cb_type != MCB) return osErrorParameter;
+
+  res = rt_mbx_send(queue_id, (void *)info, rt_ms2tick(millisec));
+
+  if (res == OS_R_TMO) {
+    return (millisec ? osErrorTimeoutResource : osErrorResource);
+  }
+
+  return osOK;
+}
+
+/// Get a Message or Wait for a Message from a Queue
+os_InRegs osEvent_type svcMessageGet (osMessageQId queue_id, uint32_t millisec) {
+  OS_RESULT res;
+  osEvent   ret;
+
+  if (queue_id == NULL) {
+    ret.status = osErrorParameter;
+    return osEvent_ret_status;
+  }
+
+  if (((P_MCB)queue_id)->cb_type != MCB) {
+    ret.status = osErrorParameter;
+    return osEvent_ret_status;
+  }
+
+  res = rt_mbx_wait(queue_id, &ret.value.p, rt_ms2tick(millisec));
+
+  if (res == OS_R_TMO) {
+    ret.status = millisec ? osEventTimeout : osOK;
+    return osEvent_ret_value;
+  }
+
+  ret.status = osEventMessage;
+
+  return osEvent_ret_value;
+}
+
+
+// Message Queue ISR Calls
+
+/// Put a Message to a Queue
+static __INLINE osStatus isrMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {
+
+  if ((queue_id == NULL) || (millisec != 0)) {
+    return osErrorParameter;
+  }
+
+  if (((P_MCB)queue_id)->cb_type != MCB) return osErrorParameter;
+
+  if (rt_mbx_check(queue_id) == 0) {            // Check if Queue is full
+    return osErrorResource;
+  }
+
+  isr_mbx_send(queue_id, (void *)info);
+
+  return osOK;
+}
+
+/// Get a Message or Wait for a Message from a Queue
+static __INLINE os_InRegs osEvent isrMessageGet (osMessageQId queue_id, uint32_t millisec) {
+  OS_RESULT res;
+  osEvent   ret;
+
+  if ((queue_id == NULL) || (millisec != 0)) {
+    ret.status = osErrorParameter;
+    return ret;
+  }
+
+  if (((P_MCB)queue_id)->cb_type != MCB) {
+    ret.status = osErrorParameter;
+    return ret;
+  }
+
+  res = isr_mbx_receive(queue_id, &ret.value.p);
+
+  if (res != OS_R_MBX) {
+    ret.status = osOK;
+    return ret;
+  }
+
+  ret.status = osEventMessage;
+
+  return ret;
+}
+
+
+// Message Queue Management Public API
+
+/// Create and Initialize Message Queue
+osMessageQId osMessageCreate (osMessageQDef_t *queue_def, osThreadId thread_id) {
+  if (__get_IPSR() != 0) return NULL;           // Not allowed in ISR
+  if (((__get_CONTROL() & 1) == 0) && (os_running == 0)) {
+    // Privileged and not running
+    return   svcMessageCreate(queue_def, thread_id);
+  } else {
+    return __svcMessageCreate(queue_def, thread_id);
+  }
+}
+
+/// Put a Message to a Queue
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {
+  if (__get_IPSR() != 0) {                      // in ISR
+    return   isrMessagePut(queue_id, info, millisec);
+  } else {                                      // in Thread
+    return __svcMessagePut(queue_id, info, millisec);
+  }
+}
+
+/// Get a Message or Wait for a Message from a Queue
+os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) {
+  if (__get_IPSR() != 0) {                      // in ISR
+    return   isrMessageGet(queue_id, millisec);
+  } else {                                      // in Thread
+    return __svcMessageGet(queue_id, millisec);
+  }
+}
+
+
+// ==== Mail Queue Management Functions ====
+
+// Mail Queue Management Service Calls declarations
+SVC_2_1(svcMailCreate, osMailQId, osMailQDef_t *, osThreadId,                   RET_pointer)
+SVC_4_1(sysMailAlloc,  void *,    osMailQId,      uint32_t, uint32_t, uint32_t, RET_pointer)
+SVC_3_1(sysMailFree,   osStatus,  osMailQId,      void *,   uint32_t,           RET_osStatus)
+
+// Mail Queue Management Service & ISR Calls
+
+/// Create and Initialize mail queue
+osMailQId svcMailCreate (osMailQDef_t *queue_def, osThreadId thread_id) {
+  uint32_t blk_sz;
+  P_MCB    pmcb;
+  void    *pool;
+
+  if ((queue_def == NULL) ||
+      (queue_def->queue_sz == 0) ||
+      (queue_def->item_sz  == 0) ||
+      (queue_def->pool == NULL)) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  pmcb = *(((void **)queue_def->pool) + 0);
+  pool = *(((void **)queue_def->pool) + 1);
+
+  if ((pool == NULL) || (pmcb == NULL) || (pmcb->cb_type != 0)) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  blk_sz = (queue_def->item_sz + 3) & ~3;
+
+  _init_box(pool, sizeof(struct OS_BM) + queue_def->queue_sz * blk_sz, blk_sz);
+
+  rt_mbx_init(pmcb, 4*(queue_def->queue_sz + 4));
+
+
+  return queue_def->pool;
+}
+
+/// Allocate a memory block from a mail
+void *sysMailAlloc (osMailQId queue_id, uint32_t millisec, uint32_t isr, uint32_t clr) {
+  P_MCB pmcb;
+  void *pool;
+  void *mem;
+
+  if (queue_id == NULL) return NULL;
+
+  pmcb = *(((void **)queue_id) + 0);
+  pool = *(((void **)queue_id) + 1);
+
+  if ((pool == NULL) || (pmcb == NULL)) return NULL;
+
+  if (isr && (millisec != 0)) return NULL;
+
+  mem = rt_alloc_box(pool);
+  if (clr) {
+    rt_clr_box(pool, mem);
+  }
+
+  if ((mem == NULL) && (millisec != 0)) {
+    // Put Task to sleep when Memory not available
+    if (pmcb->p_lnk != NULL) {
+      rt_put_prio((P_XCB)pmcb, os_tsk.run);
+    } else {
+      pmcb->p_lnk = os_tsk.run;
+      os_tsk.run->p_lnk = NULL;
+      os_tsk.run->p_rlnk = (P_TCB)pmcb;
+      // Task is waiting to allocate a message
+      pmcb->state = 3;
+    }
+    rt_block(rt_ms2tick(millisec), WAIT_MBX);
+  }
+
+  return mem;
+}
+
+/// Free a memory block from a mail
+osStatus sysMailFree (osMailQId queue_id, void *mail, uint32_t isr) {
+  P_MCB   pmcb;
+  P_TCB   ptcb;
+  void   *pool;
+  void   *mem;
+  int32_t res;
+
+  if (queue_id == NULL) return osErrorParameter;
+
+  pmcb = *(((void **)queue_id) + 0);
+  pool = *(((void **)queue_id) + 1);
+
+  if ((pmcb == NULL) || (pool == NULL)) return osErrorParameter;
+
+  res = rt_free_box(pool, mail);
+
+  if (res != 0) return osErrorValue;
+
+  if (pmcb->state == 3) {
+    // Task is waiting to allocate a message
+    if (isr) {
+      rt_psq_enq (pmcb, (U32)pool);
+      rt_psh_req ();
+    } else {
+      mem = rt_alloc_box(pool);
+      if (mem != NULL) {
+        ptcb = rt_get_first((P_XCB)pmcb);
+        if (pmcb->p_lnk == NULL) {
+          pmcb->state = 0;
+        }
+        rt_ret_val(ptcb, (U32)mem);
+        rt_rmv_dly(ptcb);
+        rt_dispatch(ptcb);
+      }
+    }
+  }
+
+  return osOK;
+}
+
+
+// Mail Queue Management Public API
+
+/// Create and Initialize mail queue
+osMailQId osMailCreate (osMailQDef_t *queue_def, osThreadId thread_id) {
+  if (__get_IPSR() != 0) return NULL;           // Not allowed in ISR
+  if (((__get_CONTROL() & 1) == 0) && (os_running == 0)) {
+    // Privileged and not running
+    return   svcMailCreate(queue_def, thread_id);
+  } else {
+    return __svcMailCreate(queue_def, thread_id);
+  }
+}
+
+/// Allocate a memory block from a mail
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec) {
+  if (__get_IPSR() != 0) {                      // in ISR
+    return   sysMailAlloc(queue_id, millisec, 1, 0);
+  } else {                                      // in Thread
+    return __sysMailAlloc(queue_id, millisec, 0, 0);
+  }
+}
+
+/// Allocate a memory block from a mail and set memory block to zero
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) {
+  if (__get_IPSR() != 0) {                      // in ISR
+    return   sysMailAlloc(queue_id, millisec, 1, 1);
+  } else {                                      // in Thread
+    return __sysMailAlloc(queue_id, millisec, 0, 1);
+  }
+}
+
+/// Free a memory block from a mail
+osStatus osMailFree (osMailQId queue_id, void *mail) {
+  if (__get_IPSR() != 0) {                      // in ISR
+    return   sysMailFree(queue_id, mail, 1);
+  } else {                                      // in Thread
+    return __sysMailFree(queue_id, mail, 0);
+  }
+}
+
+/// Put a mail to a queue
+osStatus osMailPut (osMailQId queue_id, void *mail) {
+  if (queue_id == NULL) return osErrorParameter;
+  if (mail == NULL)     return osErrorValue;
+  return osMessagePut(*((void **)queue_id), (uint32_t)mail, 0);
+}
+
+/// Get a mail from a queue
+os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) {
+  osEvent ret;
+
+  if (queue_id == NULL) {
+    ret.status = osErrorParameter;
+    return ret;
+  }
+
+  ret = osMessageGet(*((void **)queue_id), millisec);
+  if (ret.status == osEventMessage) ret.status = osEventMail;
+
+  return ret;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_Event.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,191 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_EVENT.C
+ *      Purpose: Implements waits and wake-ups for event flags
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Conf.h"
+#include "rt_System.h"
+#include "rt_Event.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#include "rt_HAL_CM.h"
+
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_evt_wait -----------------------------------*/
+
+OS_RESULT rt_evt_wait (U16 wait_flags, U16 timeout, BOOL and_wait) {
+  /* Wait for one or more event flags with optional time-out.                */
+  /* "wait_flags" identifies the flags to wait for.                          */
+  /* "timeout" is the time-out limit in system ticks (0xffff if no time-out) */
+  /* "and_wait" specifies the AND-ing of "wait_flags" as condition to be met */
+  /* to complete the wait. (OR-ing if set to 0).                             */
+  U32 block_state;
+
+  if (and_wait) {
+    /* Check for AND-connected events */
+    if ((os_tsk.run->events & wait_flags) == wait_flags) {
+      os_tsk.run->events &= ~wait_flags;
+      return (OS_R_EVT);
+    }
+    block_state = WAIT_AND;
+  }
+  else {
+    /* Check for OR-connected events */
+    if (os_tsk.run->events & wait_flags) {
+      os_tsk.run->waits = os_tsk.run->events & wait_flags;
+      os_tsk.run->events &= ~wait_flags;
+      return (OS_R_EVT);
+    }
+    block_state = WAIT_OR;
+  }
+  /* Task has to wait */
+  os_tsk.run->waits = wait_flags;
+  rt_block (timeout, (U8)block_state);
+  return (OS_R_TMO);
+}
+
+
+/*--------------------------- rt_evt_set ------------------------------------*/
+
+void rt_evt_set (U16 event_flags, OS_TID task_id) {
+  /* Set one or more event flags of a selectable task. */
+  P_TCB p_tcb;
+
+  p_tcb = os_active_TCB[task_id-1];
+  if (p_tcb == NULL) {
+    return;
+  }
+  p_tcb->events |= event_flags;
+  event_flags    = p_tcb->waits;
+  /* If the task is not waiting for an event, it should not be put */
+  /* to ready state. */
+  if (p_tcb->state == WAIT_AND) {
+    /* Check for AND-connected events */
+    if ((p_tcb->events & event_flags) == event_flags) {
+      goto wkup;
+    }
+  }
+  if (p_tcb->state == WAIT_OR) {
+    /* Check for OR-connected events */
+    if (p_tcb->events & event_flags) {
+      p_tcb->waits  &= p_tcb->events;
+wkup: p_tcb->events &= ~event_flags;
+      rt_rmv_dly (p_tcb);
+      p_tcb->state   = READY;
+#ifdef __CMSIS_RTOS
+      rt_ret_val2(p_tcb, 0x08/*osEventSignal*/, p_tcb->waits);
+#else
+      rt_ret_val (p_tcb, OS_R_EVT);
+#endif
+      rt_dispatch (p_tcb);
+    }
+  }
+}
+
+
+/*--------------------------- rt_evt_clr ------------------------------------*/
+
+void rt_evt_clr (U16 clear_flags, OS_TID task_id) {
+  /* Clear one or more event flags (identified by "clear_flags") of a */
+  /* selectable task (identified by "task"). */
+  P_TCB task = os_active_TCB[task_id-1];
+
+  if (task == NULL) {
+    return;
+  }
+  task->events &= ~clear_flags;
+}
+
+
+/*--------------------------- isr_evt_set -----------------------------------*/
+
+void isr_evt_set (U16 event_flags, OS_TID task_id) {
+  /* Same function as "os_evt_set", but to be called by ISRs. */
+  P_TCB p_tcb = os_active_TCB[task_id-1];
+
+  if (p_tcb == NULL) {
+    return;
+  }
+  rt_psq_enq (p_tcb, event_flags);
+  rt_psh_req ();
+}
+
+
+/*--------------------------- rt_evt_get ------------------------------------*/
+
+U16 rt_evt_get (void) {
+  /* Get events of a running task after waiting for OR connected events. */
+  return (os_tsk.run->waits);
+}
+
+
+/*--------------------------- rt_evt_psh ------------------------------------*/
+
+void rt_evt_psh (P_TCB p_CB, U16 set_flags) {
+  /* Check if task has to be waken up */
+  U16 event_flags;
+
+  p_CB->events |= set_flags;
+  event_flags = p_CB->waits;
+  if (p_CB->state == WAIT_AND) {
+    /* Check for AND-connected events */
+    if ((p_CB->events & event_flags) == event_flags) {
+      goto rdy;
+    }
+  }
+  if (p_CB->state == WAIT_OR) {
+    /* Check for OR-connected events */
+    if (p_CB->events & event_flags) {
+      p_CB->waits  &= p_CB->events;
+rdy:  p_CB->events &= ~event_flags;
+      rt_rmv_dly (p_CB);
+      p_CB->state   = READY;
+#ifdef __CMSIS_RTOS
+      rt_ret_val2(p_CB, 0x08/*osEventSignal*/, p_CB->waits);
+#else
+      rt_ret_val (p_CB, OS_R_EVT);
+#endif
+      rt_put_prio (&os_rdy, p_CB);
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_Event.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,47 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_EVENT.H
+ *      Purpose: Implements waits and wake-ups for event flags
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Functions */
+extern OS_RESULT rt_evt_wait (U16 wait_flags,  U16 timeout, BOOL and_wait);
+extern void      rt_evt_set  (U16 event_flags, OS_TID task_id);
+extern void      rt_evt_clr  (U16 clear_flags, OS_TID task_id);
+extern void      isr_evt_set (U16 event_flags, OS_TID task_id);
+extern U16       rt_evt_get  (void);
+extern void      rt_evt_psh  (P_TCB p_CB, U16 set_flags);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_HAL_CM.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,277 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_HAL_CM.H
+ *      Purpose: Hardware Abstraction Layer for Cortex-M definitions
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Definitions */
+#define INITIAL_xPSR    0x01000000
+#define DEMCR_TRCENA    0x01000000
+#define ITM_ITMENA      0x00000001
+#define MAGIC_WORD      0xE25A2EA5
+
+#if defined (__CC_ARM)          /* ARM Compiler */
+
+#if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS)
+ #define __USE_EXCLUSIVE_ACCESS
+#else
+ #undef  __USE_EXCLUSIVE_ACCESS
+#endif
+
+#elif defined (__GNUC__)        /* GNU Compiler */
+
+#undef  __USE_EXCLUSIVE_ACCESS
+
+#if defined (__CORTEX_M0) || defined (__CORTEX_M0PLUS)
+#define __TARGET_ARCH_6S_M 1
+#else
+#define __TARGET_ARCH_6S_M 0
+#endif
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#define __TARGET_FPU_VFP 1
+#else
+#define __TARGET_FPU_VFP 0
+#endif
+
+#define __inline inline
+#define __weak   __attribute__((weak))
+
+#ifndef __CMSIS_GENERIC
+
+__attribute__((always_inline)) static inline void __enable_irq(void)
+{
+  __asm volatile ("cpsie i");
+}
+
+__attribute__((always_inline)) static inline U32 __disable_irq(void)
+{
+  U32 result;
+
+  __asm volatile ("mrs %0, primask" : "=r" (result));
+  __asm volatile ("cpsid i");
+  return(result & 1);
+}
+
+#endif
+
+__attribute__(( always_inline)) static inline U8 __clz(U32 value)
+{
+  U8 result;
+
+  __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
+  return(result);
+}
+
+#elif defined (__ICCARM__)      /* IAR Compiler */
+
+#undef  __USE_EXCLUSIVE_ACCESS
+
+#if (__CORE__ == __ARM6M__)
+#define __TARGET_ARCH_6S_M 1
+#else
+#define __TARGET_ARCH_6S_M 0
+#endif
+
+#if defined __ARMVFP__
+#define __TARGET_FPU_VFP 1
+#else
+#define __TARGET_FPU_VFP 0
+#endif
+
+#define __inline inline
+
+#ifndef __CMSIS_GENERIC
+
+static inline void __enable_irq(void)
+{
+  __asm volatile ("cpsie i");
+}
+
+static inline U32 __disable_irq(void)
+{
+  U32 result;
+
+  __asm volatile ("mrs %0, primask" : "=r" (result));
+  __asm volatile ("cpsid i");
+  return(result & 1);
+}
+
+#endif
+
+static inline U8 __clz(U32 value)
+{
+  U8 result;
+
+  __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
+  return(result);
+}
+
+#endif
+
+/* NVIC registers */
+#define NVIC_ST_CTRL    (*((volatile U32 *)0xE000E010))
+#define NVIC_ST_RELOAD  (*((volatile U32 *)0xE000E014))
+#define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
+#define NVIC_ISER         ((volatile U32 *)0xE000E100)
+#define NVIC_ICER         ((volatile U32 *)0xE000E180)
+#if (__TARGET_ARCH_6S_M)
+#define NVIC_IP           ((volatile U32 *)0xE000E400)
+#else
+#define NVIC_IP           ((volatile U8  *)0xE000E400)
+#endif
+#define NVIC_INT_CTRL   (*((volatile U32 *)0xE000ED04))
+#define NVIC_AIR_CTRL   (*((volatile U32 *)0xE000ED0C))
+#define NVIC_SYS_PRI2   (*((volatile U32 *)0xE000ED1C))
+#define NVIC_SYS_PRI3   (*((volatile U32 *)0xE000ED20))
+
+#define OS_PEND_IRQ()   NVIC_INT_CTRL  = (1<<28)
+#define OS_PENDING      ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
+#define OS_UNPEND(fl)   NVIC_INT_CTRL  = (*fl = OS_PENDING) << 25
+#define OS_PEND(fl,p)   NVIC_INT_CTRL  = (fl | p<<2) << 26
+#define OS_LOCK()       NVIC_ST_CTRL   =  0x0005
+#define OS_UNLOCK()     NVIC_ST_CTRL   =  0x0007
+
+#define OS_X_PENDING    ((NVIC_INT_CTRL >> 28) & 1)
+#define OS_X_UNPEND(fl) NVIC_INT_CTRL  = (*fl = OS_X_PENDING) << 27
+#define OS_X_PEND(fl,p) NVIC_INT_CTRL  = (fl | p) << 28
+#if (__TARGET_ARCH_6S_M)
+#define OS_X_INIT(n)    NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \
+                        NVIC_ISER[n>>5] = 1 << (n & 0x1F)
+#else
+#define OS_X_INIT(n)    NVIC_IP[n] = 0xFF; \
+                        NVIC_ISER[n>>5] = 1 << (n & 0x1F)
+#endif
+#define OS_X_LOCK(n)    NVIC_ICER[n>>5] = 1 << (n & 0x1F)
+#define OS_X_UNLOCK(n)  NVIC_ISER[n>>5] = 1 << (n & 0x1F)
+
+/* Core Debug registers */
+#define DEMCR           (*((volatile U32 *)0xE000EDFC))
+
+/* ITM registers */
+#define ITM_CONTROL     (*((volatile U32 *)0xE0000E80))
+#define ITM_ENABLE      (*((volatile U32 *)0xE0000E00))
+#define ITM_PORT30_U32  (*((volatile U32 *)0xE0000078))
+#define ITM_PORT31_U32  (*((volatile U32 *)0xE000007C))
+#define ITM_PORT31_U16  (*((volatile U16 *)0xE000007C))
+#define ITM_PORT31_U8   (*((volatile U8  *)0xE000007C))
+
+/* Variables */
+extern BIT dbg_msg;
+
+/* Functions */
+#ifdef __USE_EXCLUSIVE_ACCESS
+ #define rt_inc(p)     while(__strex((__ldrex(p)+1),p))
+ #define rt_dec(p)     while(__strex((__ldrex(p)-1),p))
+#else
+ #define rt_inc(p)     __disable_irq();(*p)++;__enable_irq();
+ #define rt_dec(p)     __disable_irq();(*p)--;__enable_irq();
+#endif
+
+__inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
+  U32 cnt,c2;
+#ifdef __USE_EXCLUSIVE_ACCESS
+  do {
+    if ((cnt = __ldrex(count)) == size) {
+      __clrex();
+      return (cnt); }
+  } while (__strex(cnt+1, count));
+  do {
+    c2 = (cnt = __ldrex(first)) + 1;
+    if (c2 == size) c2 = 0;
+  } while (__strex(c2, first));
+#else
+  __disable_irq();
+  if ((cnt = *count) < size) {
+    *count = cnt+1;
+    c2 = (cnt = *first) + 1;
+    if (c2 == size) c2 = 0;
+    *first = c2;
+  }
+  __enable_irq ();
+#endif
+  return (cnt);
+}
+
+__inline static void rt_systick_init (void) {
+  NVIC_ST_RELOAD  = os_trv;
+  NVIC_ST_CURRENT = 0;
+  NVIC_ST_CTRL    = 0x0007;
+  NVIC_SYS_PRI3  |= 0xFF000000;
+}
+
+__inline static void rt_svc_init (void) {
+#if !(__TARGET_ARCH_6S_M)
+  int sh,prigroup;
+#endif
+  NVIC_SYS_PRI3 |= 0x00FF0000;
+#if (__TARGET_ARCH_6S_M)
+  NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
+#else
+  sh       = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
+  prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
+  if (prigroup >= sh) {
+    sh = prigroup + 1;
+  }
+  NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
+#endif
+}
+
+extern void rt_set_PSP (U32 stack);
+extern U32  rt_get_PSP (void);
+extern void os_set_env (void);
+extern void *_alloc_box (void *box_mem);
+extern int  _free_box (void *box_mem, void *box);
+
+extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
+extern void rt_ret_val  (P_TCB p_TCB, U32 v0);
+extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
+
+extern void dbg_init (void);
+extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
+extern void dbg_task_switch (U32 task_id);
+
+#ifdef DBG_MSG
+#define DBG_INIT() dbg_init()
+#define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
+#define DBG_TASK_SWITCH(task_id)      if (dbg_msg && (os_tsk.new_tsk != os_tsk.run)) \
+                                                   dbg_task_switch(task_id)
+#else
+#define DBG_INIT()
+#define DBG_TASK_NOTIFY(p_tcb,create)
+#define DBG_TASK_SWITCH(task_id)
+#endif
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_List.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,321 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_LIST.C
+ *      Purpose: Functions for the management of different lists
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Conf.h"
+#include "rt_System.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#include "rt_Time.h"
+#include "rt_HAL_CM.h"
+
+/*----------------------------------------------------------------------------
+ *      Global Variables
+ *---------------------------------------------------------------------------*/
+
+/* List head of chained ready tasks */
+struct OS_XCB  os_rdy;
+/* List head of chained delay tasks */
+struct OS_XCB  os_dly;
+
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_put_prio -----------------------------------*/
+
+void rt_put_prio (P_XCB p_CB, P_TCB p_task) {
+  /* Put task identified with "p_task" into list ordered by priority.       */
+  /* "p_CB" points to head of list; list has always an element at end with  */
+  /* a priority less than "p_task->prio".                                   */
+  P_TCB p_CB2;
+  U32 prio;
+  BOOL sem_mbx = __FALSE;
+
+  if (p_CB->cb_type == SCB || p_CB->cb_type == MCB || p_CB->cb_type == MUCB) {
+    sem_mbx = __TRUE;
+  }
+  prio = p_task->prio;
+  p_CB2 = p_CB->p_lnk;
+  /* Search for an entry in the list */
+  while (p_CB2 != NULL && prio <= p_CB2->prio) {
+    p_CB = (P_XCB)p_CB2;
+    p_CB2 = p_CB2->p_lnk;
+  }
+  /* Entry found, insert the task into the list */
+  p_task->p_lnk = p_CB2;
+  p_CB->p_lnk = p_task;
+  if (sem_mbx) {
+    if (p_CB2 != NULL) {
+      p_CB2->p_rlnk = p_task;
+    }
+    p_task->p_rlnk = (P_TCB)p_CB;
+  }
+  else {
+    p_task->p_rlnk = NULL;
+  }
+}
+
+
+/*--------------------------- rt_get_first ----------------------------------*/
+
+P_TCB rt_get_first (P_XCB p_CB) {
+  /* Get task at head of list: it is the task with highest priority. */
+  /* "p_CB" points to head of list. */
+  P_TCB p_first;
+
+  p_first = p_CB->p_lnk;
+  p_CB->p_lnk = p_first->p_lnk;
+  if (p_CB->cb_type == SCB || p_CB->cb_type == MCB || p_CB->cb_type == MUCB) {
+    if (p_first->p_lnk != NULL) {
+      p_first->p_lnk->p_rlnk = (P_TCB)p_CB;
+      p_first->p_lnk = NULL;
+    }
+    p_first->p_rlnk = NULL;
+  }
+  else {
+    p_first->p_lnk = NULL;
+  }
+  return (p_first);
+}
+
+
+/*--------------------------- rt_put_rdy_first ------------------------------*/
+
+void rt_put_rdy_first (P_TCB p_task) {
+  /* Put task identified with "p_task" at the head of the ready list. The   */
+  /* task must have at least a priority equal to highest priority in list.  */
+  p_task->p_lnk = os_rdy.p_lnk;
+  p_task->p_rlnk = NULL;
+  os_rdy.p_lnk = p_task;
+}
+
+
+/*--------------------------- rt_get_same_rdy_prio --------------------------*/
+
+P_TCB rt_get_same_rdy_prio (void) {
+  /* Remove a task of same priority from ready list if any exists. Other-   */
+  /* wise return NULL.                                                      */
+  P_TCB p_first;
+
+  p_first = os_rdy.p_lnk;
+  if (p_first->prio == os_tsk.run->prio) {
+    os_rdy.p_lnk = os_rdy.p_lnk->p_lnk;
+    return (p_first);
+  }
+  return (NULL);
+}
+
+
+/*--------------------------- rt_resort_prio --------------------------------*/
+
+void rt_resort_prio (P_TCB p_task) {
+  /* Re-sort ordered lists after the priority of 'p_task' has changed.      */
+  P_TCB p_CB;
+
+  if (p_task->p_rlnk == NULL) {
+    if (p_task->state == READY) {
+      /* Task is chained into READY list. */
+      p_CB = (P_TCB)&os_rdy;
+      goto res;
+    }
+  }
+  else {
+    p_CB = p_task->p_rlnk;
+    while (p_CB->cb_type == TCB) {
+      /* Find a header of this task chain list. */
+      p_CB = p_CB->p_rlnk;
+    }
+res:rt_rmv_list (p_task);
+    rt_put_prio ((P_XCB)p_CB, p_task);
+  }
+}
+
+
+/*--------------------------- rt_put_dly ------------------------------------*/
+
+void rt_put_dly (P_TCB p_task, U16 delay) {
+  /* Put a task identified with "p_task" into chained delay wait list using */
+  /* a delay value of "delay".                                              */
+  P_TCB p;
+  U32 delta,idelay = delay;
+
+  p = (P_TCB)&os_dly;
+  if (p->p_dlnk == NULL) {
+    /* Delay list empty */
+    delta = 0;
+    goto last;
+  }
+  delta = os_dly.delta_time;
+  while (delta < idelay) {
+    if (p->p_dlnk == NULL) {
+      /* End of list found */
+last: p_task->p_dlnk = NULL;
+      p->p_dlnk = p_task;
+      p_task->p_blnk = p;
+      p->delta_time = (U16)(idelay - delta);
+      p_task->delta_time = 0;
+      return;
+    }
+    p = p->p_dlnk;
+    delta += p->delta_time;
+  }
+  /* Right place found */
+  p_task->p_dlnk = p->p_dlnk;
+  p->p_dlnk = p_task;
+  p_task->p_blnk = p;
+  if (p_task->p_dlnk != NULL) {
+    p_task->p_dlnk->p_blnk = p_task;
+  }
+  p_task->delta_time = (U16)(delta - idelay);
+  p->delta_time -= p_task->delta_time;
+}
+
+
+/*--------------------------- rt_dec_dly ------------------------------------*/
+
+void rt_dec_dly (void) {
+  /* Decrement delta time of list head: remove tasks having a value of zero.*/
+  P_TCB p_rdy;
+
+  if (os_dly.p_dlnk == NULL) {
+    return;
+  }
+  os_dly.delta_time--;
+  while ((os_dly.delta_time == 0) && (os_dly.p_dlnk != NULL)) {
+    p_rdy = os_dly.p_dlnk;
+    if (p_rdy->p_rlnk != NULL) {
+      /* Task is really enqueued, remove task from semaphore/mailbox */
+      /* timeout waiting list. */
+      p_rdy->p_rlnk->p_lnk = p_rdy->p_lnk;
+      if (p_rdy->p_lnk != NULL) {
+        p_rdy->p_lnk->p_rlnk = p_rdy->p_rlnk;
+        p_rdy->p_lnk = NULL;
+      }
+      p_rdy->p_rlnk = NULL;
+    }
+    rt_put_prio (&os_rdy, p_rdy);
+    os_dly.delta_time = p_rdy->delta_time;
+    if (p_rdy->state == WAIT_ITV) {
+      /* Calculate the next time for interval wait. */
+      p_rdy->delta_time = p_rdy->interval_time + (U16)os_time;
+    }
+    p_rdy->state   = READY;
+    os_dly.p_dlnk = p_rdy->p_dlnk;
+    if (p_rdy->p_dlnk != NULL) {
+      p_rdy->p_dlnk->p_blnk =  (P_TCB)&os_dly;
+      p_rdy->p_dlnk = NULL;
+    }
+    p_rdy->p_blnk = NULL;
+  }
+}
+
+
+/*--------------------------- rt_rmv_list -----------------------------------*/
+
+void rt_rmv_list (P_TCB p_task) {
+  /* Remove task identified with "p_task" from ready, semaphore or mailbox  */
+  /* waiting list if enqueued.                                              */
+  P_TCB p_b;
+
+  if (p_task->p_rlnk != NULL) {
+    /* A task is enqueued in semaphore / mailbox waiting list. */
+    p_task->p_rlnk->p_lnk = p_task->p_lnk;
+    if (p_task->p_lnk != NULL) {
+      p_task->p_lnk->p_rlnk = p_task->p_rlnk;
+    }
+    return;
+  }
+
+  p_b = (P_TCB)&os_rdy;
+  while (p_b != NULL) {
+    /* Search the ready list for task "p_task" */
+    if (p_b->p_lnk == p_task) {
+      p_b->p_lnk = p_task->p_lnk;
+      return;
+    }
+    p_b = p_b->p_lnk;
+  }
+}
+
+
+/*--------------------------- rt_rmv_dly ------------------------------------*/
+
+void rt_rmv_dly (P_TCB p_task) {
+  /* Remove task identified with "p_task" from delay list if enqueued.      */
+  P_TCB p_b;
+
+  p_b = p_task->p_blnk;
+  if (p_b != NULL) {
+    /* Task is really enqueued */
+    p_b->p_dlnk = p_task->p_dlnk;
+    if (p_task->p_dlnk != NULL) {
+      /* 'p_task' is in the middle of list */
+      p_b->delta_time += p_task->delta_time;
+      p_task->p_dlnk->p_blnk = p_b;
+      p_task->p_dlnk = NULL;
+    }
+    else {
+      /* 'p_task' is at the end of list */
+      p_b->delta_time = 0;
+    }
+    p_task->p_blnk = NULL;
+  }
+}
+
+
+/*--------------------------- rt_psq_enq ------------------------------------*/
+
+void rt_psq_enq (OS_ID entry, U32 arg) {
+  /* Insert post service request "entry" into ps-queue. */
+  U32 idx;
+
+  idx = rt_inc_qi (os_psq->size, &os_psq->count, &os_psq->first);
+  if (idx < os_psq->size) {
+    os_psq->q[idx].id  = entry;
+    os_psq->q[idx].arg = arg;
+  }
+  else {
+    os_error (OS_ERR_FIFO_OVF);
+  }
+}
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_List.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,68 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_LIST.H
+ *      Purpose: Functions for the management of different lists
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Definitions */
+
+/* Values for 'cb_type' */
+#define TCB             0
+#define MCB             1
+#define SCB             2
+#define MUCB            3
+#define HCB             4
+
+/* Variables */
+extern struct OS_XCB os_rdy;
+extern struct OS_XCB os_dly;
+
+/* Functions */
+extern void  rt_put_prio      (P_XCB p_CB, P_TCB p_task);
+extern P_TCB rt_get_first     (P_XCB p_CB);
+extern void  rt_put_rdy_first (P_TCB p_task);
+extern P_TCB rt_get_same_rdy_prio (void);
+extern void  rt_resort_prio   (P_TCB p_task);
+extern void  rt_put_dly       (P_TCB p_task, U16 delay);
+extern void  rt_dec_dly       (void);
+extern void  rt_rmv_list      (P_TCB p_task);
+extern void  rt_rmv_dly       (P_TCB p_task);
+extern void  rt_psq_enq       (OS_ID entry, U32 arg);
+
+/* This is a fast macro generating in-line code */
+#define rt_rdy_prio(void) (os_rdy.p_lnk->prio)
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_Mailbox.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,293 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_MAILBOX.C
+ *      Purpose: Implements waits and wake-ups for mailbox messages
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Conf.h"
+#include "rt_System.h"
+#include "rt_List.h"
+#include "rt_Mailbox.h"
+#include "rt_MemBox.h"
+#include "rt_Task.h"
+#include "rt_HAL_CM.h"
+
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_mbx_init -----------------------------------*/
+
+void rt_mbx_init (OS_ID mailbox, U16 mbx_size) {
+  /* Initialize a mailbox */
+  P_MCB p_MCB = mailbox;
+
+  p_MCB->cb_type = MCB;
+  p_MCB->state   = 0;
+  p_MCB->isr_st  = 0;
+  p_MCB->p_lnk   = NULL;
+  p_MCB->first   = 0;
+  p_MCB->last    = 0;
+  p_MCB->count   = 0;
+  p_MCB->size    = (mbx_size + sizeof(void *) - sizeof(struct OS_MCB)) /
+                                                     (U32)sizeof (void *);
+}
+
+
+/*--------------------------- rt_mbx_send -----------------------------------*/
+
+OS_RESULT rt_mbx_send (OS_ID mailbox, void *p_msg, U16 timeout) {
+  /* Send message to a mailbox */
+  P_MCB p_MCB = mailbox;
+  P_TCB p_TCB;
+
+  if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 1)) {
+    /* A task is waiting for message */
+    p_TCB = rt_get_first ((P_XCB)p_MCB);
+#ifdef __CMSIS_RTOS
+    rt_ret_val2(p_TCB, 0x10/*osEventMessage*/, (U32)p_msg);
+#else
+    *p_TCB->msg = p_msg;
+    rt_ret_val (p_TCB, OS_R_MBX);
+#endif
+    rt_rmv_dly (p_TCB);
+    rt_dispatch (p_TCB);
+  }
+  else {
+    /* Store message in mailbox queue */
+    if (p_MCB->count == p_MCB->size) {
+      /* No free message entry, wait for one. If message queue is full, */
+      /* then no task is waiting for message. The 'p_MCB->p_lnk' list   */
+      /* pointer can now be reused for send message waits task list.    */
+      if (timeout == 0) {
+        return (OS_R_TMO);
+      }
+      if (p_MCB->p_lnk != NULL) {
+        rt_put_prio ((P_XCB)p_MCB, os_tsk.run);
+      }
+      else {
+        p_MCB->p_lnk = os_tsk.run;
+        os_tsk.run->p_lnk  = NULL;
+        os_tsk.run->p_rlnk = (P_TCB)p_MCB;
+        /* Task is waiting to send a message */
+        p_MCB->state = 2;
+      }
+      os_tsk.run->msg = p_msg;
+      rt_block (timeout, WAIT_MBX);
+      return (OS_R_TMO);
+    }
+    /* Yes, there is a free entry in a mailbox. */
+    p_MCB->msg[p_MCB->first] = p_msg;
+    rt_inc (&p_MCB->count);
+    if (++p_MCB->first == p_MCB->size) {
+      p_MCB->first = 0;
+    }
+  }
+  return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_mbx_wait -----------------------------------*/
+
+OS_RESULT rt_mbx_wait (OS_ID mailbox, void **message, U16 timeout) {
+  /* Receive a message; possibly wait for it */
+  P_MCB p_MCB = mailbox;
+  P_TCB p_TCB;
+
+  /* If a message is available in the fifo buffer */
+  /* remove it from the fifo buffer and return. */
+  if (p_MCB->count) {
+    *message = p_MCB->msg[p_MCB->last];
+    if (++p_MCB->last == p_MCB->size) {
+      p_MCB->last = 0;
+    }
+    if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 2)) {
+      /* A task is waiting to send message */
+      p_TCB = rt_get_first ((P_XCB)p_MCB);
+#ifdef __CMSIS_RTOS
+      rt_ret_val(p_TCB, 0/*osOK*/);
+#else
+      rt_ret_val(p_TCB, OS_R_OK);
+#endif
+      p_MCB->msg[p_MCB->first] = p_TCB->msg;
+      if (++p_MCB->first == p_MCB->size) {
+        p_MCB->first = 0;
+      }
+      rt_rmv_dly (p_TCB);
+      rt_dispatch (p_TCB);
+    }
+    else {
+      rt_dec (&p_MCB->count);
+    }
+    return (OS_R_OK);
+  }
+  /* No message available: wait for one */
+  if (timeout == 0) {
+    return (OS_R_TMO);
+  }
+  if (p_MCB->p_lnk != NULL) {
+    rt_put_prio ((P_XCB)p_MCB, os_tsk.run);
+  }
+  else {
+    p_MCB->p_lnk = os_tsk.run;
+    os_tsk.run->p_lnk = NULL;
+    os_tsk.run->p_rlnk = (P_TCB)p_MCB;
+    /* Task is waiting to receive a message */
+    p_MCB->state = 1;
+  }
+  rt_block(timeout, WAIT_MBX);
+#ifndef __CMSIS_RTOS
+  os_tsk.run->msg = message;
+#endif
+  return (OS_R_TMO);
+}
+
+
+/*--------------------------- rt_mbx_check ----------------------------------*/
+
+OS_RESULT rt_mbx_check (OS_ID mailbox) {
+  /* Check for free space in a mailbox. Returns the number of messages     */
+  /* that can be stored to a mailbox. It returns 0 when mailbox is full.   */
+  P_MCB p_MCB = mailbox;
+
+  return (p_MCB->size - p_MCB->count);
+}
+
+
+/*--------------------------- isr_mbx_send ----------------------------------*/
+
+void isr_mbx_send (OS_ID mailbox, void *p_msg) {
+  /* Same function as "os_mbx_send", but to be called by ISRs. */
+  P_MCB p_MCB = mailbox;
+
+  rt_psq_enq (p_MCB, (U32)p_msg);
+  rt_psh_req ();
+}
+
+
+/*--------------------------- isr_mbx_receive -------------------------------*/
+
+OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message) {
+  /* Receive a message in the interrupt function. The interrupt function   */
+  /* should not wait for a message since this would block the rtx os.      */
+  P_MCB p_MCB = mailbox;
+
+  if (p_MCB->count) {
+    /* A message is available in the fifo buffer. */
+    *message = p_MCB->msg[p_MCB->last];
+    if (p_MCB->state == 2) {
+      /* A task is locked waiting to send message */
+      rt_psq_enq (p_MCB, 0);
+      rt_psh_req ();
+    }
+    rt_dec (&p_MCB->count);
+    if (++p_MCB->last == p_MCB->size) {
+      p_MCB->last = 0;
+    }
+    return (OS_R_MBX);
+  }
+  return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_mbx_psh ------------------------------------*/
+
+void rt_mbx_psh (P_MCB p_CB, void *p_msg) {
+  /* Store the message to the mailbox queue or pass it to task directly. */
+  P_TCB p_TCB;
+  void *mem;
+
+  if (p_CB->p_lnk != NULL) switch (p_CB->state) {
+#ifdef __CMSIS_RTOS
+    case 3:
+      /* Task is waiting to allocate memory, remove it from the waiting list */
+      mem = rt_alloc_box(p_msg);
+      if (mem == NULL) break;
+      p_TCB = rt_get_first ((P_XCB)p_CB);
+      rt_ret_val(p_TCB, (U32)mem);
+      p_TCB->state = READY;
+      rt_rmv_dly (p_TCB);
+      rt_put_prio (&os_rdy, p_TCB);
+      break;
+#endif
+    case 2:
+      /* Task is waiting to send a message, remove it from the waiting list */
+      p_TCB = rt_get_first ((P_XCB)p_CB);
+#ifdef __CMSIS_RTOS
+      rt_ret_val(p_TCB, 0/*osOK*/);
+#else
+      rt_ret_val(p_TCB, OS_R_OK);
+#endif
+      p_CB->msg[p_CB->first] = p_TCB->msg;
+      rt_inc (&p_CB->count);
+      if (++p_CB->first == p_CB->size) {
+        p_CB->first = 0;
+      }
+      p_TCB->state = READY;
+      rt_rmv_dly (p_TCB);
+      rt_put_prio (&os_rdy, p_TCB);
+      break;
+    case 1:
+      /* Task is waiting for a message, pass the message to the task directly */
+      p_TCB = rt_get_first ((P_XCB)p_CB);
+#ifdef __CMSIS_RTOS
+      rt_ret_val2(p_TCB, 0x10/*osEventMessage*/, (U32)p_msg);
+#else
+      *p_TCB->msg = p_msg;
+      rt_ret_val (p_TCB, OS_R_MBX);
+#endif
+      p_TCB->state = READY;
+      rt_rmv_dly (p_TCB);
+      rt_put_prio (&os_rdy, p_TCB);
+      break;
+  } else {
+      /* No task is waiting for a message, store it to the mailbox queue */
+      if (p_CB->count < p_CB->size) {
+        p_CB->msg[p_CB->first] = p_msg;
+        rt_inc (&p_CB->count);
+        if (++p_CB->first == p_CB->size) {
+          p_CB->first = 0;
+        }
+      }
+      else {
+        os_error (OS_ERR_MBX_OVF);
+      }
+  }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_Mailbox.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,49 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_MAILBOX.H
+ *      Purpose: Implements waits and wake-ups for mailbox messages
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Functions */
+extern void      rt_mbx_init  (OS_ID mailbox, U16 mbx_size);
+extern OS_RESULT rt_mbx_send  (OS_ID mailbox, void *p_msg,    U16 timeout);
+extern OS_RESULT rt_mbx_wait  (OS_ID mailbox, void **message, U16 timeout);
+extern OS_RESULT rt_mbx_check (OS_ID mailbox);
+extern void      isr_mbx_send (OS_ID mailbox, void *p_msg);
+extern OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message);
+extern void      rt_mbx_psh   (P_MCB p_CB,    void *p_msg);
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_MemBox.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,167 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_MEMBOX.C
+ *      Purpose: Interface functions for fixed memory block management system
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Conf.h"
+#include "rt_System.h"
+#include "rt_MemBox.h"
+#include "rt_HAL_CM.h"
+
+/*----------------------------------------------------------------------------
+ *      Global Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- _init_box -------------------------------------*/
+
+int _init_box  (void *box_mem, U32 box_size, U32 blk_size) {
+  /* Initialize memory block system, returns 0 if OK, 1 if fails. */
+  void *end;
+  void *blk;
+  void *next;
+  U32  sizeof_bm;
+
+  /* Create memory structure. */
+  if (blk_size & BOX_ALIGN_8) {
+    /* Memory blocks 8-byte aligned. */
+    blk_size = ((blk_size & ~BOX_ALIGN_8) + 7) & ~7;
+    sizeof_bm = (sizeof (struct OS_BM) + 7) & ~7;
+  }
+  else {
+    /* Memory blocks 4-byte aligned. */
+    blk_size = (blk_size + 3) & ~3;
+    sizeof_bm = sizeof (struct OS_BM);
+  }
+  if (blk_size == 0) {
+    return (1);
+  }
+  if ((blk_size + sizeof_bm) > box_size) {
+    return (1);
+  }
+  /* Create a Memory structure. */
+  blk = ((U8 *) box_mem) + sizeof_bm;
+  ((P_BM) box_mem)->free = blk;
+  end = ((U8 *) box_mem) + box_size;
+  ((P_BM) box_mem)->end      = end;
+  ((P_BM) box_mem)->blk_size = blk_size;
+
+  /* Link all free blocks using offsets. */
+  end = ((U8 *) end) - blk_size;
+  while (1)  {
+    next = ((U8 *) blk) + blk_size;
+    if (next > end)  break;
+    *((void **)blk) = next;
+    blk = next;
+  }
+  /* end marker */
+  *((void **)blk) = 0;
+  return (0);
+}
+
+/*--------------------------- rt_alloc_box ----------------------------------*/
+
+void *rt_alloc_box (void *box_mem) {
+  /* Allocate a memory block and return start address. */
+  void **free;
+#ifndef __USE_EXCLUSIVE_ACCESS
+  int  irq_dis;
+
+  irq_dis = __disable_irq ();
+  free = ((P_BM) box_mem)->free;
+  if (free) {
+    ((P_BM) box_mem)->free = *free;
+  }
+  if (!irq_dis) __enable_irq ();
+#else
+  do {
+    if ((free = (void **)__ldrex(&((P_BM) box_mem)->free)) == 0) {
+      __clrex();
+      break;
+    }
+  } while (__strex((U32)*free, &((P_BM) box_mem)->free));
+#endif
+  return (free);
+}
+
+
+/*--------------------------- _calloc_box -----------------------------------*/
+
+void *_calloc_box (void *box_mem)  {
+  /* Allocate a 0-initialized memory block and return start address. */
+  void *free;
+  U32 *p;
+  U32 i;
+
+  free = _alloc_box (box_mem);
+  if (free)  {
+    p = free;
+    for (i = ((P_BM) box_mem)->blk_size; i; i -= 4)  {
+      *p = 0;
+      p++;
+    }
+  }
+  return (free);
+}
+
+
+/*--------------------------- rt_free_box -----------------------------------*/
+
+int rt_free_box (void *box_mem, void *box) {
+  /* Free a memory block, returns 0 if OK, 1 if box does not belong to box_mem */
+#ifndef __USE_EXCLUSIVE_ACCESS
+  int irq_dis;
+#endif
+
+  if (box < box_mem || box >= ((P_BM) box_mem)->end) {
+    return (1);
+  }
+
+#ifndef __USE_EXCLUSIVE_ACCESS
+  irq_dis = __disable_irq ();
+  *((void **)box) = ((P_BM) box_mem)->free;
+  ((P_BM) box_mem)->free = box;
+  if (!irq_dis) __enable_irq ();
+#else
+  do {
+    *((void **)box) = (void *)__ldrex(&((P_BM) box_mem)->free);
+  } while (__strex ((U32)box, &((P_BM) box_mem)->free));
+#endif
+  return (0);
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_MemBox.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,47 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_MEMBOX.H
+ *      Purpose: Interface functions for fixed memory block management system
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Functions */
+#define rt_init_box     _init_box
+#define rt_calloc_box   _calloc_box
+extern int     _init_box   (void *box_mem, U32 box_size, U32 blk_size);
+extern void *rt_alloc_box  (void *box_mem);
+extern void *  _calloc_box (void *box_mem);
+extern int   rt_free_box   (void *box_mem, void *box);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_Mutex.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,198 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_MUTEX.C
+ *      Purpose: Implements mutex synchronization objects
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Conf.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#include "rt_Mutex.h"
+#include "rt_HAL_CM.h"
+
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_mut_init -----------------------------------*/
+
+void rt_mut_init (OS_ID mutex) {
+  /* Initialize a mutex object */
+  P_MUCB p_MCB = mutex;
+
+  p_MCB->cb_type = MUCB;
+  p_MCB->prio    = 0;
+  p_MCB->level   = 0;
+  p_MCB->p_lnk   = NULL;
+  p_MCB->owner   = NULL;
+}
+
+
+/*--------------------------- rt_mut_delete ---------------------------------*/
+
+#ifdef __CMSIS_RTOS
+OS_RESULT rt_mut_delete (OS_ID mutex) {
+  /* Delete a mutex object */
+  P_MUCB p_MCB = mutex;
+  P_TCB  p_TCB;
+
+  /* Restore owner task's priority. */
+  if (p_MCB->level != 0) {
+    p_MCB->owner->prio = p_MCB->prio;
+    if (p_MCB->owner != os_tsk.run) {
+      rt_resort_prio (p_MCB->owner);
+    }
+  }
+
+  while (p_MCB->p_lnk != NULL) {
+    /* A task is waiting for mutex. */
+    p_TCB = rt_get_first ((P_XCB)p_MCB);
+    rt_ret_val(p_TCB, 0/*osOK*/);
+    rt_rmv_dly(p_TCB);
+    p_TCB->state = READY;
+    rt_put_prio (&os_rdy, p_TCB);
+  }
+
+  if (os_rdy.p_lnk && (os_rdy.p_lnk->prio > os_tsk.run->prio)) {
+    /* preempt running task */
+    rt_put_prio (&os_rdy, os_tsk.run);
+    os_tsk.run->state = READY;
+    rt_dispatch (NULL);
+  }
+
+  p_MCB->cb_type = 0;
+
+  return (OS_R_OK);
+}
+#endif
+
+
+/*--------------------------- rt_mut_release --------------------------------*/
+
+OS_RESULT rt_mut_release (OS_ID mutex) {
+  /* Release a mutex object */
+  P_MUCB p_MCB = mutex;
+  P_TCB  p_TCB;
+
+  if (p_MCB->level == 0 || p_MCB->owner != os_tsk.run) {
+    /* Unbalanced mutex release or task is not the owner */
+    return (OS_R_NOK);
+  }
+  if (--p_MCB->level != 0) {
+    return (OS_R_OK);
+  }
+  /* Restore owner task's priority. */
+  os_tsk.run->prio = p_MCB->prio;
+  if (p_MCB->p_lnk != NULL) {
+    /* A task is waiting for mutex. */
+    p_TCB = rt_get_first ((P_XCB)p_MCB);
+#ifdef __CMSIS_RTOS
+    rt_ret_val(p_TCB, 0/*osOK*/);
+#else
+    rt_ret_val(p_TCB, OS_R_MUT);
+#endif
+    rt_rmv_dly (p_TCB);
+    /* A waiting task becomes the owner of this mutex. */
+    p_MCB->level     = 1;
+    p_MCB->owner     = p_TCB;
+    p_MCB->prio      = p_TCB->prio;
+    /* Priority inversion, check which task continues. */
+    if (os_tsk.run->prio >= rt_rdy_prio()) {
+      rt_dispatch (p_TCB);
+    }
+    else {
+      /* Ready task has higher priority than running task. */
+      rt_put_prio (&os_rdy, os_tsk.run);
+      rt_put_prio (&os_rdy, p_TCB);
+      os_tsk.run->state = READY;
+      p_TCB->state      = READY;
+      rt_dispatch (NULL);
+    }
+  }
+  else {
+    /* Check if own priority raised by priority inversion. */
+    if (rt_rdy_prio() > os_tsk.run->prio) {
+      rt_put_prio (&os_rdy, os_tsk.run);
+      os_tsk.run->state = READY;
+      rt_dispatch (NULL);
+    }
+  }
+  return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_mut_wait -----------------------------------*/
+
+OS_RESULT rt_mut_wait (OS_ID mutex, U16 timeout) {
+  /* Wait for a mutex, continue when mutex is free. */
+  P_MUCB p_MCB = mutex;
+
+  if (p_MCB->level == 0) {
+    p_MCB->owner = os_tsk.run;
+    p_MCB->prio  = os_tsk.run->prio;
+    goto inc;
+  }
+  if (p_MCB->owner == os_tsk.run) {
+    /* OK, running task is the owner of this mutex. */
+inc:p_MCB->level++;
+    return (OS_R_OK);
+  }
+  /* Mutex owned by another task, wait until released. */
+  if (timeout == 0) {
+    return (OS_R_TMO);
+  }
+  /* Raise the owner task priority if lower than current priority. */
+  /* This priority inversion is called priority inheritance.       */
+  if (p_MCB->prio < os_tsk.run->prio) {
+    p_MCB->owner->prio = os_tsk.run->prio;
+    rt_resort_prio (p_MCB->owner);
+  }
+  if (p_MCB->p_lnk != NULL) {
+    rt_put_prio ((P_XCB)p_MCB, os_tsk.run);
+  }
+  else {
+    p_MCB->p_lnk = os_tsk.run;
+    os_tsk.run->p_lnk  = NULL;
+    os_tsk.run->p_rlnk = (P_TCB)p_MCB;
+  }
+  rt_block(timeout, WAIT_MUT);
+  return (OS_R_TMO);
+}
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_Mutex.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,45 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_MUTEX.H
+ *      Purpose: Implements mutex synchronization objects
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Functions */
+extern void      rt_mut_init    (OS_ID mutex);
+extern OS_RESULT rt_mut_delete  (OS_ID mutex);
+extern OS_RESULT rt_mut_release (OS_ID mutex);
+extern OS_RESULT rt_mut_wait    (OS_ID mutex, U16 timeout);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_Robin.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,85 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_ROBIN.C
+ *      Purpose: Round Robin Task switching
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Conf.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#include "rt_Time.h"
+#include "rt_Robin.h"
+#include "rt_HAL_CM.h"
+
+/*----------------------------------------------------------------------------
+ *      Global Variables
+ *---------------------------------------------------------------------------*/
+
+struct OS_ROBIN os_robin;
+
+
+/*----------------------------------------------------------------------------
+ *      Global Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- rt_init_robin ---------------------------------*/
+
+__weak void rt_init_robin (void) {
+  /* Initialize Round Robin variables. */
+  os_robin.task = NULL;
+  os_robin.tout = (U16)os_rrobin;
+}
+
+/*--------------------------- rt_chk_robin ----------------------------------*/
+
+__weak void rt_chk_robin (void) {
+  /* Check if Round Robin timeout expired and switch to the next ready task.*/
+  P_TCB p_new;
+
+  if (os_robin.task != os_rdy.p_lnk) {
+    /* New task was suspended, reset Round Robin timeout. */
+    os_robin.task = os_rdy.p_lnk;
+    os_robin.time = (U16)os_time + os_robin.tout - 1;
+  }
+  if (os_robin.time == (U16)os_time) {
+    /* Round Robin timeout has expired, swap Robin tasks. */
+    os_robin.task = NULL;
+    p_new = rt_get_first (&os_rdy);
+    rt_put_prio ((P_XCB)&os_rdy, p_new);
+  }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_Robin.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,46 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_ROBIN.H
+ *      Purpose: Round Robin Task switching definitions
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Variables */
+extern struct OS_ROBIN os_robin;
+
+/* Functions */
+extern void rt_init_robin (void);
+extern void rt_chk_robin  (void);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_Semaphore.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,184 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_SEMAPHORE.C
+ *      Purpose: Implements binary and counting semaphores
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Conf.h"
+#include "rt_System.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#include "rt_Semaphore.h"
+#include "rt_HAL_CM.h"
+
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_sem_init -----------------------------------*/
+
+void rt_sem_init (OS_ID semaphore, U16 token_count) {
+  /* Initialize a semaphore */
+  P_SCB p_SCB = semaphore;
+
+  p_SCB->cb_type = SCB;
+  p_SCB->p_lnk  = NULL;
+  p_SCB->tokens = token_count;
+}
+
+
+/*--------------------------- rt_sem_delete ---------------------------------*/
+
+#ifdef __CMSIS_RTOS
+OS_RESULT rt_sem_delete (OS_ID semaphore) {
+  /* Delete semaphore */
+  P_SCB p_SCB = semaphore;
+  P_TCB p_TCB;
+
+  while (p_SCB->p_lnk != NULL) {
+    /* A task is waiting for token */
+    p_TCB = rt_get_first ((P_XCB)p_SCB);
+    rt_ret_val(p_TCB, 0);
+    rt_rmv_dly(p_TCB);
+    p_TCB->state = READY;
+    rt_put_prio (&os_rdy, p_TCB);
+  }
+
+  if (os_rdy.p_lnk && (os_rdy.p_lnk->prio > os_tsk.run->prio)) {
+    /* preempt running task */
+    rt_put_prio (&os_rdy, os_tsk.run);
+    os_tsk.run->state = READY;
+    rt_dispatch (NULL);
+  }
+
+  p_SCB->cb_type = 0;
+
+  return (OS_R_OK);
+}
+#endif
+
+
+/*--------------------------- rt_sem_send -----------------------------------*/
+
+OS_RESULT rt_sem_send (OS_ID semaphore) {
+  /* Return a token to semaphore */
+  P_SCB p_SCB = semaphore;
+  P_TCB p_TCB;
+
+  if (p_SCB->p_lnk != NULL) {
+    /* A task is waiting for token */
+    p_TCB = rt_get_first ((P_XCB)p_SCB);
+#ifdef __CMSIS_RTOS
+    rt_ret_val(p_TCB, 1);
+#else
+    rt_ret_val(p_TCB, OS_R_SEM);
+#endif
+    rt_rmv_dly (p_TCB);
+    rt_dispatch (p_TCB);
+  }
+  else {
+    /* Store token. */
+    p_SCB->tokens++;
+  }
+  return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_sem_wait -----------------------------------*/
+
+OS_RESULT rt_sem_wait (OS_ID semaphore, U16 timeout) {
+  /* Obtain a token; possibly wait for it */
+  P_SCB p_SCB = semaphore;
+
+  if (p_SCB->tokens) {
+    p_SCB->tokens--;
+    return (OS_R_OK);
+  }
+  /* No token available: wait for one */
+  if (timeout == 0) {
+    return (OS_R_TMO);
+  }
+  if (p_SCB->p_lnk != NULL) {
+    rt_put_prio ((P_XCB)p_SCB, os_tsk.run);
+  }
+  else {
+    p_SCB->p_lnk = os_tsk.run;
+    os_tsk.run->p_lnk = NULL;
+    os_tsk.run->p_rlnk = (P_TCB)p_SCB;
+  }
+  rt_block(timeout, WAIT_SEM);
+  return (OS_R_TMO);
+}
+
+
+/*--------------------------- isr_sem_send ----------------------------------*/
+
+void isr_sem_send (OS_ID semaphore) {
+  /* Same function as "os_sem"send", but to be called by ISRs */
+  P_SCB p_SCB = semaphore;
+
+  rt_psq_enq (p_SCB, 0);
+  rt_psh_req ();
+}
+
+
+/*--------------------------- rt_sem_psh ------------------------------------*/
+
+void rt_sem_psh (P_SCB p_CB) {
+  /* Check if task has to be waken up */
+  P_TCB p_TCB;
+
+  if (p_CB->p_lnk != NULL) {
+    /* A task is waiting for token */
+    p_TCB = rt_get_first ((P_XCB)p_CB);
+    rt_rmv_dly (p_TCB);
+    p_TCB->state   = READY;
+#ifdef __CMSIS_RTOS
+    rt_ret_val(p_TCB, 1);
+#else
+    rt_ret_val(p_TCB, OS_R_SEM);
+#endif
+    rt_put_prio (&os_rdy, p_TCB);
+  }
+  else {
+    /* Store token */
+    p_CB->tokens++;
+  }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_Semaphore.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,47 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_SEMAPHORE.H
+ *      Purpose: Implements binary and counting semaphores
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Functions */
+extern void      rt_sem_init  (OS_ID semaphore, U16 token_count);
+extern OS_RESULT rt_sem_delete(OS_ID semaphore);
+extern OS_RESULT rt_sem_send  (OS_ID semaphore);
+extern OS_RESULT rt_sem_wait  (OS_ID semaphore, U16 timeout);
+extern void      isr_sem_send (OS_ID semaphore);
+extern void      rt_sem_psh (P_SCB p_CB);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_System.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,300 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_SYSTEM.C
+ *      Purpose: System Task Manager
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Conf.h"
+#include "rt_Task.h"
+#include "rt_System.h"
+#include "rt_Event.h"
+#include "rt_List.h"
+#include "rt_Mailbox.h"
+#include "rt_Semaphore.h"
+#include "rt_Time.h"
+#include "rt_Robin.h"
+#include "rt_HAL_CM.h"
+
+/*----------------------------------------------------------------------------
+ *      Global Variables
+ *---------------------------------------------------------------------------*/
+
+int os_tick_irqn;
+
+/*----------------------------------------------------------------------------
+ *      Local Variables
+ *---------------------------------------------------------------------------*/
+
+static volatile BIT os_lock;
+static volatile BIT os_psh_flag;
+static          U8  pend_flags;
+
+/*----------------------------------------------------------------------------
+ *      Global Functions
+ *---------------------------------------------------------------------------*/
+
+#if defined (__CC_ARM)
+__asm void $$RTX$$version (void) {
+   /* Export a version number symbol for a version control. */
+
+                EXPORT  __RL_RTX_VER
+
+__RL_RTX_VER    EQU     0x450
+}
+#endif
+
+
+/*--------------------------- rt_suspend ------------------------------------*/
+U32 rt_suspend (void) {
+  /* Suspend OS scheduler */
+  U32 delta = 0xFFFF;
+
+  rt_tsk_lock();
+
+  if (os_dly.p_dlnk) {
+    delta = os_dly.delta_time;
+  }
+#ifndef __CMSIS_RTOS
+  if (os_tmr.next) {
+    if (os_tmr.tcnt < delta) delta = os_tmr.tcnt;
+  }
+#endif
+
+  return (delta);
+}
+
+
+/*--------------------------- rt_resume -------------------------------------*/
+void rt_resume (U32 sleep_time) {
+  /* Resume OS scheduler after suspend */
+  P_TCB next;
+  U32   delta;
+
+  os_tsk.run->state = READY;
+  rt_put_rdy_first (os_tsk.run);
+
+  os_robin.task = NULL;
+
+  /* Update delays. */
+  if (os_dly.p_dlnk) {
+    delta = sleep_time;
+    if (delta >= os_dly.delta_time) {
+      delta   -= os_dly.delta_time;
+      os_time += os_dly.delta_time;
+      os_dly.delta_time = 1;
+      while (os_dly.p_dlnk) {
+        rt_dec_dly();
+        if (delta == 0) break;
+        delta--;
+        os_time++;
+      }
+    } else {
+      os_time           += delta;
+      os_dly.delta_time -= delta;
+    }
+  } else {
+    os_time += sleep_time;
+  }
+
+#ifndef __CMSIS_RTOS
+  /* Check the user timers. */
+  if (os_tmr.next) {
+    delta = sleep_time;
+    if (delta >= os_tmr.tcnt) {
+      delta   -= os_tmr.tcnt;
+      os_tmr.tcnt = 1;
+      while (os_tmr.next) {
+        rt_tmr_tick();
+        if (delta == 0) break;
+        delta--;
+      }
+    } else {
+      os_tmr.tcnt -= delta;
+    }
+  }
+#endif
+
+  /* Switch back to highest ready task */
+  next = rt_get_first (&os_rdy);
+  rt_switch_req (next);
+
+  rt_tsk_unlock();
+}
+
+
+/*--------------------------- rt_tsk_lock -----------------------------------*/
+
+void rt_tsk_lock (void) {
+  /* Prevent task switching by locking out scheduler */
+  if (os_tick_irqn < 0) {
+    OS_LOCK();
+    os_lock = __TRUE;
+    OS_UNPEND (&pend_flags);
+  } else {
+    OS_X_LOCK(os_tick_irqn);
+    os_lock = __TRUE;
+    OS_X_UNPEND (&pend_flags);
+  }
+}
+
+
+/*--------------------------- rt_tsk_unlock ---------------------------------*/
+
+void rt_tsk_unlock (void) {
+  /* Unlock scheduler and re-enable task switching */
+  if (os_tick_irqn < 0) {
+    OS_UNLOCK();
+    os_lock = __FALSE;
+    OS_PEND (pend_flags, os_psh_flag);
+    os_psh_flag = __FALSE;
+  } else {
+    OS_X_UNLOCK(os_tick_irqn);
+    os_lock = __FALSE;
+    OS_X_PEND (pend_flags, os_psh_flag);
+    os_psh_flag = __FALSE;
+  }
+}
+
+
+/*--------------------------- rt_psh_req ------------------------------------*/
+
+void rt_psh_req (void) {
+  /* Initiate a post service handling request if required. */
+  if (os_lock == __FALSE) {
+    OS_PEND_IRQ ();
+  }
+  else {
+    os_psh_flag = __TRUE;
+  }
+}
+
+
+/*--------------------------- rt_pop_req ------------------------------------*/
+
+void rt_pop_req (void) {
+  /* Process an ISR post service requests. */
+  struct OS_XCB *p_CB;
+  P_TCB next;
+  U32  idx;
+
+  os_tsk.run->state = READY;
+  rt_put_rdy_first (os_tsk.run);
+
+  idx = os_psq->last;
+  while (os_psq->count) {
+    p_CB = os_psq->q[idx].id;
+    if (p_CB->cb_type == TCB) {
+      /* Is of TCB type */
+      rt_evt_psh ((P_TCB)p_CB, (U16)os_psq->q[idx].arg);
+    }
+    else if (p_CB->cb_type == MCB) {
+      /* Is of MCB type */
+      rt_mbx_psh ((P_MCB)p_CB, (void *)os_psq->q[idx].arg);
+    }
+    else {
+      /* Must be of SCB type */
+      rt_sem_psh ((P_SCB)p_CB);
+    }
+    if (++idx == os_psq->size) idx = 0;
+    rt_dec (&os_psq->count);
+  }
+  os_psq->last = idx;
+
+  next = rt_get_first (&os_rdy);
+  rt_switch_req (next);
+}
+
+
+/*--------------------------- os_tick_init ----------------------------------*/
+
+__weak int os_tick_init (void) {
+  /* Initialize SysTick timer as system tick timer. */
+  rt_systick_init ();
+  return (-1);  /* Return IRQ number of SysTick timer */
+}
+
+
+/*--------------------------- os_tick_irqack --------------------------------*/
+
+__weak void os_tick_irqack (void) {
+  /* Acknowledge timer interrupt. */
+}
+
+
+/*--------------------------- rt_systick ------------------------------------*/
+
+extern void sysTimerTick(void);
+
+void rt_systick (void) {
+  /* Check for system clock update, suspend running task. */
+  P_TCB next;
+
+  os_tsk.run->state = READY;
+  rt_put_rdy_first (os_tsk.run);
+
+  /* Check Round Robin timeout. */
+  rt_chk_robin ();
+
+  /* Update delays. */
+  os_time++;
+  rt_dec_dly ();
+
+  /* Check the user timers. */
+#ifdef __CMSIS_RTOS
+  sysTimerTick();
+#else
+  rt_tmr_tick ();
+#endif
+
+  /* Switch back to highest ready task */
+  next = rt_get_first (&os_rdy);
+  rt_switch_req (next);
+}
+
+/*--------------------------- rt_stk_check ----------------------------------*/
+__weak void rt_stk_check (void) {
+    /* Check for stack overflow. */
+    if (os_tsk.run->task_id == 0x01) {
+        // TODO: For the main thread the check should be done against the main heap pointer
+    } else {
+        if ((os_tsk.run->tsk_stack < (U32)os_tsk.run->stack) ||
+            (os_tsk.run->stack[0] != MAGIC_WORD)) {
+            os_error (OS_ERR_STK_OVF);
+        }
+    }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_System.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,53 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_SYSTEM.H
+ *      Purpose: System Task Manager definitions
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Variables */
+#define os_psq  ((P_PSQ)&os_fifo)
+extern int os_tick_irqn;
+
+/* Functions */
+extern U32  rt_suspend    (void);
+extern void rt_resume     (U32 sleep_time);
+extern void rt_tsk_lock   (void);
+extern void rt_tsk_unlock (void);
+extern void rt_psh_req    (void);
+extern void rt_pop_req    (void);
+extern void rt_systick    (void);
+extern void rt_stk_check  (void);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_Task.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,340 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_TASK.C
+ *      Purpose: Task functions and system start up.
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Conf.h"
+#include "rt_System.h"
+#include "rt_Task.h"
+#include "rt_List.h"
+#include "rt_MemBox.h"
+#include "rt_Robin.h"
+#include "rt_HAL_CM.h"
+
+/*----------------------------------------------------------------------------
+ *      Global Variables
+ *---------------------------------------------------------------------------*/
+
+/* Running and next task info. */
+struct OS_TSK os_tsk;
+
+/* Task Control Blocks of idle demon */
+struct OS_TCB os_idle_TCB;
+
+
+/*----------------------------------------------------------------------------
+ *      Local Functions
+ *---------------------------------------------------------------------------*/
+
+OS_TID rt_get_TID (void) {
+  U32 tid;
+
+  for (tid = 1; tid <= os_maxtaskrun; tid++) {
+    if (os_active_TCB[tid-1] == NULL) {
+      return ((OS_TID)tid);
+    }
+  }
+  return (0);
+}
+
+#if defined (__CC_ARM) && !defined (__MICROLIB)
+/*--------------------------- __user_perthread_libspace ---------------------*/
+extern void  *__libspace_start;
+
+void *__user_perthread_libspace (void) {
+  /* Provide a separate libspace for each task. */
+  if (os_tsk.run == NULL) {
+    /* RTX not running yet. */
+    return (&__libspace_start);
+  }
+  return (void *)(os_tsk.run->std_libspace);
+}
+#endif
+
+/*--------------------------- rt_init_context -------------------------------*/
+
+void rt_init_context (P_TCB p_TCB, U8 priority, FUNCP task_body) {
+  /* Initialize general part of the Task Control Block. */
+  p_TCB->cb_type = TCB;
+  p_TCB->state   = READY;
+  p_TCB->prio    = priority;
+  p_TCB->p_lnk   = NULL;
+  p_TCB->p_rlnk  = NULL;
+  p_TCB->p_dlnk  = NULL;
+  p_TCB->p_blnk  = NULL;
+  p_TCB->delta_time    = 0;
+  p_TCB->interval_time = 0;
+  p_TCB->events  = 0;
+  p_TCB->waits   = 0;
+  p_TCB->stack_frame = 0;
+
+  rt_init_stack (p_TCB, task_body);
+}
+
+
+/*--------------------------- rt_switch_req ---------------------------------*/
+
+void rt_switch_req (P_TCB p_new) {
+  /* Switch to next task (identified by "p_new"). */
+  os_tsk.new_tsk   = p_new;
+  p_new->state = RUNNING;
+  DBG_TASK_SWITCH(p_new->task_id);
+}
+
+
+/*--------------------------- rt_dispatch -----------------------------------*/
+
+void rt_dispatch (P_TCB next_TCB) {
+  /* Dispatch next task if any identified or dispatch highest ready task    */
+  /* "next_TCB" identifies a task to run or has value NULL (=no next task)  */
+  if (next_TCB == NULL) {
+    /* Running task was blocked: continue with highest ready task */
+    next_TCB = rt_get_first (&os_rdy);
+    rt_switch_req (next_TCB);
+  }
+  else {
+    /* Check which task continues */
+    if (next_TCB->prio > os_tsk.run->prio) {
+      /* preempt running task */
+      rt_put_rdy_first (os_tsk.run);
+      os_tsk.run->state = READY;
+      rt_switch_req (next_TCB);
+    }
+    else {
+      /* put next task into ready list, no task switch takes place */
+      next_TCB->state = READY;
+      rt_put_prio (&os_rdy, next_TCB);
+    }
+  }
+}
+
+
+/*--------------------------- rt_block --------------------------------------*/
+
+void rt_block (U16 timeout, U8 block_state) {
+  /* Block running task and choose next ready task.                         */
+  /* "timeout" sets a time-out value or is 0xffff (=no time-out).           */
+  /* "block_state" defines the appropriate task state */
+  P_TCB next_TCB;
+
+  if (timeout) {
+    if (timeout < 0xffff) {
+      rt_put_dly (os_tsk.run, timeout);
+    }
+    os_tsk.run->state = block_state;
+    next_TCB = rt_get_first (&os_rdy);
+    rt_switch_req (next_TCB);
+  }
+}
+
+
+/*--------------------------- rt_tsk_pass -----------------------------------*/
+
+void rt_tsk_pass (void) {
+  /* Allow tasks of same priority level to run cooperatively.*/
+  P_TCB p_new;
+
+  p_new = rt_get_same_rdy_prio();
+  if (p_new != NULL) {
+    rt_put_prio ((P_XCB)&os_rdy, os_tsk.run);
+    os_tsk.run->state = READY;
+    rt_switch_req (p_new);
+  }
+}
+
+
+/*--------------------------- rt_tsk_self -----------------------------------*/
+
+OS_TID rt_tsk_self (void) {
+  /* Return own task identifier value. */
+  if (os_tsk.run == NULL) {
+    return (0);
+  }
+  return (os_tsk.run->task_id);
+}
+
+
+/*--------------------------- rt_tsk_prio -----------------------------------*/
+
+OS_RESULT rt_tsk_prio (OS_TID task_id, U8 new_prio) {
+  /* Change execution priority of a task to "new_prio". */
+  P_TCB p_task;
+
+  if (task_id == 0) {
+    /* Change execution priority of calling task. */
+    os_tsk.run->prio = new_prio;
+run:if (rt_rdy_prio() > new_prio) {
+      rt_put_prio (&os_rdy, os_tsk.run);
+      os_tsk.run->state   = READY;
+      rt_dispatch (NULL);
+    }
+    return (OS_R_OK);
+  }
+
+  /* Find the task in the "os_active_TCB" array. */
+  if (task_id > os_maxtaskrun || os_active_TCB[task_id-1] == NULL) {
+    /* Task with "task_id" not found or not started. */
+    return (OS_R_NOK);
+  }
+  p_task = os_active_TCB[task_id-1];
+  p_task->prio = new_prio;
+  if (p_task == os_tsk.run) {
+    goto run;
+  }
+  rt_resort_prio (p_task);
+  if (p_task->state == READY) {
+    /* Task enqueued in a ready list. */
+    p_task = rt_get_first (&os_rdy);
+    rt_dispatch (p_task);
+  }
+  return (OS_R_OK);
+}
+
+/*--------------------------- rt_tsk_delete ---------------------------------*/
+
+OS_RESULT rt_tsk_delete (OS_TID task_id) {
+  /* Terminate the task identified with "task_id". */
+  P_TCB task_context;
+
+  if (task_id == 0 || task_id == os_tsk.run->task_id) {
+    /* Terminate itself. */
+    os_tsk.run->state     = INACTIVE;
+    os_tsk.run->tsk_stack = rt_get_PSP ();
+    rt_stk_check ();
+    os_active_TCB[os_tsk.run->task_id-1] = NULL;
+
+    os_tsk.run->stack = NULL;
+    DBG_TASK_NOTIFY(os_tsk.run, __FALSE);
+    os_tsk.run = NULL;
+    rt_dispatch (NULL);
+    /* The program should never come to this point. */
+  }
+  else {
+    /* Find the task in the "os_active_TCB" array. */
+    if (task_id > os_maxtaskrun || os_active_TCB[task_id-1] == NULL) {
+      /* Task with "task_id" not found or not started. */
+      return (OS_R_NOK);
+    }
+    task_context = os_active_TCB[task_id-1];
+    rt_rmv_list (task_context);
+    rt_rmv_dly (task_context);
+    os_active_TCB[task_id-1] = NULL;
+
+    task_context->stack = NULL;
+    DBG_TASK_NOTIFY(task_context, __FALSE);
+  }
+  return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_sys_init -----------------------------------*/
+
+#ifdef __CMSIS_RTOS
+void rt_sys_init (void) {
+#else
+void rt_sys_init (FUNCP first_task, U32 prio_stksz, void *stk) {
+#endif
+  /* Initialize system and start up task declared with "first_task". */
+  U32 i;
+
+  DBG_INIT();
+
+  /* Initialize dynamic memory and task TCB pointers to NULL. */
+  for (i = 0; i < os_maxtaskrun; i++) {
+    os_active_TCB[i] = NULL;
+  }
+
+  /* Set up TCB of idle demon */
+  os_idle_TCB.task_id = 255;
+  os_idle_TCB.priv_stack = idle_task_stack_size;
+  os_idle_TCB.stack = idle_task_stack;
+  rt_init_context (&os_idle_TCB, 0, os_idle_demon);
+
+  /* Set up ready list: initially empty */
+  os_rdy.cb_type = HCB;
+  os_rdy.p_lnk   = NULL;
+  /* Set up delay list: initially empty */
+  os_dly.cb_type = HCB;
+  os_dly.p_dlnk  = NULL;
+  os_dly.p_blnk  = NULL;
+  os_dly.delta_time = 0;
+
+  /* Fix SP and systemvariables to assume idle task is running  */
+  /* Transform main program into idle task by assuming idle TCB */
+#ifndef __CMSIS_RTOS
+  rt_set_PSP (os_idle_TCB.tsk_stack+32);
+#endif
+  os_tsk.run = &os_idle_TCB;
+  os_tsk.run->state = RUNNING;
+
+  /* Initialize ps queue */
+  os_psq->first = 0;
+  os_psq->last  = 0;
+  os_psq->size  = os_fifo_size;
+
+  rt_init_robin ();
+
+  /* Intitialize SVC and PendSV */
+  rt_svc_init ();
+
+#ifndef __CMSIS_RTOS
+  /* Intitialize and start system clock timer */
+  os_tick_irqn = os_tick_init ();
+  if (os_tick_irqn >= 0) {
+    OS_X_INIT(os_tick_irqn);
+  }
+
+  /* Start up first user task before entering the endless loop */
+  rt_tsk_create (first_task, prio_stksz, stk, NULL);
+#endif
+}
+
+
+/*--------------------------- rt_sys_start ----------------------------------*/
+
+#ifdef __CMSIS_RTOS
+void rt_sys_start (void) {
+  /* Start system */
+
+  /* Intitialize and start system clock timer */
+  os_tick_irqn = os_tick_init ();
+  if (os_tick_irqn >= 0) {
+    OS_X_INIT(os_tick_irqn);
+  }
+}
+#endif
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_Task.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,74 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_TASK.H
+ *      Purpose: Task functions and system start up.
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Definitions */
+#define __CMSIS_RTOS    1
+
+/* Values for 'state'   */
+#define INACTIVE        0
+#define READY           1
+#define RUNNING         2
+#define WAIT_DLY        3
+#define WAIT_ITV        4
+#define WAIT_OR         5
+#define WAIT_AND        6
+#define WAIT_SEM        7
+#define WAIT_MBX        8
+#define WAIT_MUT        9
+
+/* Return codes */
+#define OS_R_TMO        0x01
+#define OS_R_EVT        0x02
+#define OS_R_SEM        0x03
+#define OS_R_MBX        0x04
+#define OS_R_MUT        0x05
+
+#define OS_R_OK         0x00
+#define OS_R_NOK        0xff
+
+/* Variables */
+extern struct OS_TSK os_tsk;
+extern struct OS_TCB os_idle_TCB;
+
+/* Functions */
+extern void      rt_switch_req (P_TCB p_new);
+extern void      rt_dispatch   (P_TCB next_TCB);
+extern void      rt_block      (U16 timeout, U8 block_state);
+extern void      rt_tsk_pass   (void);
+extern OS_TID    rt_tsk_self   (void);
+extern OS_RESULT rt_tsk_prio   (OS_TID task_id, U8 new_prio);
+extern OS_RESULT rt_tsk_delete (OS_TID task_id);
+extern void      rt_sys_init   (void);
+extern void      rt_sys_start  (void);
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_Time.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,95 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_TIME.C
+ *      Purpose: Delay and interval wait functions
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Conf.h"
+#include "rt_Task.h"
+#include "rt_Time.h"
+
+/*----------------------------------------------------------------------------
+ *      Global Variables
+ *---------------------------------------------------------------------------*/
+
+/* Free running system tick counter */
+U32 os_time;
+
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_time_get -----------------------------------*/
+
+U32 rt_time_get (void) {
+  /* Get system time tick */
+  return (os_time);
+}
+
+
+/*--------------------------- rt_dly_wait -----------------------------------*/
+
+void rt_dly_wait (U16 delay_time) {
+  /* Delay task by "delay_time" */
+  rt_block (delay_time, WAIT_DLY);
+}
+
+
+/*--------------------------- rt_itv_set ------------------------------------*/
+
+void rt_itv_set (U16 interval_time) {
+  /* Set interval length and define start of first interval */
+  os_tsk.run->interval_time = interval_time;
+  os_tsk.run->delta_time = interval_time + (U16)os_time;
+}
+
+
+/*--------------------------- rt_itv_wait -----------------------------------*/
+
+void rt_itv_wait (void) {
+  /* Wait for interval end and define start of next one */
+  U16 delta;
+
+  delta = os_tsk.run->delta_time - (U16)os_time;
+  os_tsk.run->delta_time += os_tsk.run->interval_time;
+  if ((delta & 0x8000) == 0) {
+    rt_block (delta, WAIT_ITV);
+  }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_Time.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,48 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_TIME.H
+ *      Purpose: Delay and interval wait functions definitions
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Variables */
+extern U32 os_time;
+
+/* Functions */
+extern U32  rt_time_get (void);
+extern void rt_dly_wait (U16 delay_time);
+extern void rt_itv_set  (U16 interval_time);
+extern void rt_itv_wait (void);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos/rtx/rt_TypeDef.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,129 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_TYPEDEF.H
+ *      Purpose: Type Definitions
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+#ifndef RT_TYPE_DEF_H
+#define RT_TYPE_DEF_H
+
+#include "os_tcb.h"
+
+typedef U32     OS_TID;
+typedef void    *OS_ID;
+typedef U32     OS_RESULT;
+
+#define TCB_STACKF      32        /* 'stack_frame' offset                    */
+#define TCB_TSTACK      36        /* 'tsk_stack' offset                      */
+
+typedef struct OS_PSFE {          /* Post Service Fifo Entry                 */
+  void  *id;                      /* Object Identification                   */
+  U32    arg;                     /* Object Argument                         */
+} *P_PSFE;
+
+typedef struct OS_PSQ {           /* Post Service Queue                      */
+  U8     first;                   /* FIFO Head Index                         */
+  U8     last;                    /* FIFO Tail Index                         */
+  U8     count;                   /* Number of stored items in FIFO          */
+  U8     size;                    /* FIFO Size                               */
+  struct OS_PSFE q[1];            /* FIFO Content                            */
+} *P_PSQ;
+
+typedef struct OS_TSK {
+  P_TCB  run;                     /* Current running task                    */
+  P_TCB  new_tsk;                 /* Scheduled task to run                   */
+} *P_TSK;
+
+typedef struct OS_ROBIN {         /* Round Robin Control                     */
+  P_TCB  task;                    /* Round Robin task                        */
+  U16    time;                    /* Round Robin switch time                 */
+  U16    tout;                    /* Round Robin timeout                     */
+} *P_ROBIN;
+
+typedef struct OS_XCB {
+  U8     cb_type;                 /* Control Block Type                      */
+  struct OS_TCB *p_lnk;           /* Link pointer for ready/sem. wait list   */
+  struct OS_TCB *p_rlnk;          /* Link pointer for sem./mbx lst backwards */
+  struct OS_TCB *p_dlnk;          /* Link pointer for delay list             */
+  struct OS_TCB *p_blnk;          /* Link pointer for delay list backwards   */
+  U16    delta_time;              /* Time until time out                     */
+} *P_XCB;
+
+typedef struct OS_MCB {
+  U8     cb_type;                 /* Control Block Type                      */
+  U8     state;                   /* State flag variable                     */
+  U8     isr_st;                  /* State flag variable for isr functions   */
+  struct OS_TCB *p_lnk;           /* Chain of tasks waiting for message      */
+  U16    first;                   /* Index of the message list begin         */
+  U16    last;                    /* Index of the message list end           */
+  U16    count;                   /* Actual number of stored messages        */
+  U16    size;                    /* Maximum number of stored messages       */
+  void   *msg[1];                 /* FIFO for Message pointers 1st element   */
+} *P_MCB;
+
+typedef struct OS_SCB {
+  U8     cb_type;                 /* Control Block Type                      */
+  U8     mask;                    /* Semaphore token mask                    */
+  U16    tokens;                  /* Semaphore tokens                        */
+  struct OS_TCB *p_lnk;           /* Chain of tasks waiting for tokens       */
+} *P_SCB;
+
+typedef struct OS_MUCB {
+  U8     cb_type;                 /* Control Block Type                      */
+  U8     prio;                    /* Owner task default priority             */
+  U16    level;                   /* Call nesting level                      */
+  struct OS_TCB *p_lnk;           /* Chain of tasks waiting for mutex        */
+  struct OS_TCB *owner;           /* Mutex owner task                        */
+} *P_MUCB;
+
+typedef struct OS_XTMR {
+  struct OS_TMR  *next;
+  U16    tcnt;
+} *P_XTMR;
+
+typedef struct OS_TMR {
+  struct OS_TMR  *next;           /* Link pointer to Next timer              */
+  U16    tcnt;                    /* Timer delay count                       */
+  U16    info;                    /* User defined call info                  */
+} *P_TMR;
+
+typedef struct OS_BM {
+  void *free;                     /* Pointer to first free memory block      */
+  void *end;                      /* Pointer to memory block end             */
+  U32  blk_size;                  /* Memory block size                       */
+} *P_BM;
+
+/* Definitions */
+#define __TRUE          1
+#define __FALSE         0
+#define NULL            ((void *) 0)
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/AnalogIn.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGIN_H
+#define MBED_ANALOGIN_H
+
+#include "platform.h"
+
+#if DEVICE_ANALOGIN
+
+#include "analogin_api.h"
+
+namespace mbed {
+
+/** An analog input, used for reading the voltage on a pin
+ *
+ * Example:
+ * @code
+ * // Print messages when the AnalogIn is greater than 50%
+ *
+ * #include "mbed.h"
+ *
+ * AnalogIn temperature(p20);
+ *
+ * int main() {
+ *     while(1) {
+ *         if(temperature > 0.5) {
+ *             printf("Too hot! (%f)", temperature.read());
+ *         }
+ *     }
+ * }
+ * @endcode
+ */
+class AnalogIn {
+
+public:
+
+    /** Create an AnalogIn, connected to the specified pin
+     *
+     * @param pin AnalogIn pin to connect to
+     * @param name (optional) A string to identify the object
+     */
+    AnalogIn(PinName pin) {
+        analogin_init(&_adc, pin);
+    }
+
+    /** Read the input voltage, represented as a float in the range [0.0, 1.0]
+     *
+     * @returns A floating-point value representing the current input voltage, measured as a percentage
+     */
+    float read() {
+        return analogin_read(&_adc);
+    }
+
+    /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
+     *
+     * @returns
+     *   16-bit unsigned short representing the current input voltage, normalised to a 16-bit value
+     */
+    unsigned short read_u16() {
+        return analogin_read_u16(&_adc);
+    }
+
+#ifdef MBED_OPERATORS
+    /** An operator shorthand for read()
+     *
+     * The float() operator can be used as a shorthand for read() to simplify common code sequences
+     *
+     * Example:
+     * @code
+     * float x = volume.read();
+     * float x = volume;
+     *
+     * if(volume.read() > 0.25) { ... }
+     * if(volume > 0.25) { ... }
+     * @endcode
+     */
+    operator float() {
+        return read();
+    }
+#endif
+
+protected:
+    analogin_t _adc;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/AnalogOut.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,122 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGOUT_H
+#define MBED_ANALOGOUT_H
+
+#include "platform.h"
+
+#if DEVICE_ANALOGOUT
+
+#include "analogout_api.h"
+
+namespace mbed {
+
+/** An analog output, used for setting the voltage on a pin
+ *
+ * Example:
+ * @code
+ * // Make a sawtooth output
+ *
+ * #include "mbed.h"
+ *
+ * AnalogOut tri(p18);
+ * int main() {
+ *     while(1) {
+ *         tri = tri + 0.01;
+ *         wait_us(1);
+ *         if(tri == 1) {
+ *             tri = 0;
+ *         }
+ *     }
+ * }
+ * @endcode
+ */
+class AnalogOut {
+
+public:
+
+    /** Create an AnalogOut connected to the specified pin
+     *
+     *  @param AnalogOut pin to connect to (18)
+     */
+    AnalogOut(PinName pin) {
+        analogout_init(&_dac, pin);
+    }
+
+    /** Set the output voltage, specified as a percentage (float)
+     *
+     *  @param value A floating-point value representing the output voltage,
+     *    specified as a percentage. The value should lie between
+     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
+     *    Values outside this range will be saturated to 0.0f or 1.0f.
+     */
+    void write(float value) {
+        analogout_write(&_dac, value);
+    }
+
+    /** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
+     *
+     *  @param value 16-bit unsigned short representing the output voltage,
+     *            normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
+     */
+    void write_u16(unsigned short value) {
+        analogout_write_u16(&_dac, value);
+    }
+
+    /** Return the current output voltage setting, measured as a percentage (float)
+     *
+     *  @returns
+     *    A floating-point value representing the current voltage being output on the pin,
+     *    measured as a percentage. The returned value will lie between
+     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
+     *
+     *  @note
+     *    This value may not match exactly the value set by a previous write().
+     */
+    float read() {
+        return analogout_read(&_dac);
+    }
+
+#ifdef MBED_OPERATORS
+    /** An operator shorthand for write()
+     */
+    AnalogOut& operator= (float percent) {
+        write(percent);
+        return *this;
+    }
+
+    AnalogOut& operator= (AnalogOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** An operator shorthand for read()
+     */
+    operator float() {
+        return read();
+    }
+#endif
+
+protected:
+    dac_t _dac;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/BusIn.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,79 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSIN_H
+#define MBED_BUSIN_H
+
+#include "platform.h"
+#include "DigitalIn.h"
+
+namespace mbed {
+
+/** A digital input bus, used for reading the state of a collection of pins
+ */
+class BusIn {
+
+public:
+    /* Group: Configuration Methods */
+
+    /** Create an BusIn, connected to the specified pins
+     *
+     * @param <n> DigitalIn pin to connect to bus bit <n> (p5-p30, NC)
+     *
+     * @note
+     *  It is only required to specify as many pin variables as is required
+     *  for the bus; the rest will default to NC (not connected)
+     */
+    BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+          PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+          PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+          PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+    BusIn(PinName pins[16]);
+
+    virtual ~BusIn();
+
+    /** Read the value of the input bus
+     *
+     *  @returns
+     *   An integer with each bit corresponding to the value read from the associated DigitalIn pin
+     */
+    int read();
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone
+     */
+    void mode(PinMode pull);
+
+#ifdef MBED_OPERATORS
+    /** A shorthand for read()
+     */
+    operator int();
+#endif
+
+protected:
+    DigitalIn* _pin[16];
+
+    /* disallow copy constructor and assignment operators */
+private:
+    BusIn(const BusIn&);
+    BusIn & operator = (const BusIn&);
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/BusInOut.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,99 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSINOUT_H
+#define MBED_BUSINOUT_H
+
+#include "DigitalInOut.h"
+
+namespace mbed {
+
+/** A digital input output bus, used for setting the state of a collection of pins
+ */
+class BusInOut {
+
+public:
+
+    /** Create an BusInOut, connected to the specified pins
+     *
+     *  @param p<n> DigitalInOut pin to connect to bus bit p<n> (p5-p30, NC)
+     *
+     *  @note
+     *  It is only required to specify as many pin variables as is required
+     *  for the bus; the rest will default to NC (not connected)
+     */
+    BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+             PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+             PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+             PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+    BusInOut(PinName pins[16]);
+
+    virtual ~BusInOut();
+
+    /* Group: Access Methods */
+
+    /** Write the value to the output bus
+     *
+     *  @param value An integer specifying a bit to write for every corresponding DigitalInOut pin
+     */
+    void write(int value);
+
+
+    /** Read the value currently output on the bus
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated DigitalInOut pin setting
+     */
+    int read();
+
+    /** Set as an output
+     */
+    void output();
+
+    /** Set as an input
+     */
+    void input();
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone
+     */
+    void mode(PinMode pull);
+
+#ifdef MBED_OPERATORS
+     /** A shorthand for write()
+     */
+    BusInOut& operator= (int v);
+    BusInOut& operator= (BusInOut& rhs);
+
+    /** A shorthand for read()
+     */
+    operator int();
+#endif
+
+protected:
+    DigitalInOut* _pin[16];
+
+    /* disallow copy constructor and assignment operators */
+private:
+    BusInOut(const BusInOut&);
+    BusInOut & operator = (const BusInOut&);
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/BusOut.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSOUT_H
+#define MBED_BUSOUT_H
+
+#include "DigitalOut.h"
+
+namespace mbed {
+
+/** A digital output bus, used for setting the state of a collection of pins
+ */
+class BusOut {
+
+public:
+
+    /** Create an BusOut, connected to the specified pins
+     *
+     *  @param p<n> DigitalOut pin to connect to bus bit <n> (p5-p30, NC)
+     *
+     *  @note
+     *  It is only required to specify as many pin variables as is required
+     *  for the bus; the rest will default to NC (not connected)
+     */
+    BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+           PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+           PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+           PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+    BusOut(PinName pins[16]);
+
+    virtual ~BusOut();
+
+    /** Write the value to the output bus
+     *
+     *  @param value An integer specifying a bit to write for every corresponding DigitalOut pin
+     */
+    void write(int value);
+
+    /** Read the value currently output on the bus
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated DigitalOut pin setting
+     */
+    int read();
+
+#ifdef MBED_OPERATORS
+    /** A shorthand for write()
+     */
+    BusOut& operator= (int v);
+    BusOut& operator= (BusOut& rhs);
+
+    /** A shorthand for read()
+     */
+    operator int();
+#endif
+
+protected:
+    DigitalOut* _pin[16];
+
+   /* disallow copy constructor and assignment operators */
+private:
+    BusOut(const BusOut&);
+    BusOut & operator = (const BusOut&);
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/CAN.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,244 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_H
+#define MBED_CAN_H
+
+#include "platform.h"
+
+#if DEVICE_CAN
+
+#include "can_api.h"
+#include "can_helper.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** CANMessage class
+ */
+class CANMessage : public CAN_Message {
+
+public:
+    /** Creates empty CAN message.
+     */
+    CANMessage() : CAN_Message() {
+        len    = 8;
+        type   = CANData;
+        format = CANStandard;
+        id     = 0;
+        memset(data, 0, 8);
+    }
+
+    /** Creates CAN message with specific content.
+     */
+    CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
+      len    = _len & 0xF;
+      type   = _type;
+      format = _format;
+      id     = _id;
+      memcpy(data, _data, _len);
+    }
+
+    /** Creates CAN remote message.
+     */
+    CANMessage(int _id, CANFormat _format = CANStandard) {
+      len    = 0;
+      type   = CANRemote;
+      format = _format;
+      id     = _id;
+      memset(data, 0, 8);
+    }
+};
+
+/** A can bus client, used for communicating with can devices
+ */
+class CAN {
+
+public:
+    /** Creates an CAN interface connected to specific pins.
+     *
+     *  @param rd read from transmitter
+     *  @param td transmit to transmitter
+     *
+     * Example:
+     * @code
+     * #include "mbed.h"
+     *
+     * Ticker ticker;
+     * DigitalOut led1(LED1);
+     * DigitalOut led2(LED2);
+     * CAN can1(p9, p10);
+     * CAN can2(p30, p29);
+     *
+     * char counter = 0;
+     *
+     * void send() {
+     *     if(can1.write(CANMessage(1337, &counter, 1))) {
+     *         printf("Message sent: %d\n", counter);
+     *         counter++;
+     *     }
+     *     led1 = !led1;
+     * }
+     *
+     * int main() {
+     *     ticker.attach(&send, 1);
+     *    CANMessage msg;
+     *     while(1) {
+     *         if(can2.read(msg)) {
+     *             printf("Message received: %d\n\n", msg.data[0]);
+     *             led2 = !led2;
+     *         }
+     *         wait(0.2);
+     *     }
+     * }
+     * @endcode
+     */
+    CAN(PinName rd, PinName td);
+    virtual ~CAN();
+
+    /** Set the frequency of the CAN interface
+     *
+     *  @param hz The bus frequency in hertz
+     *
+     *  @returns
+     *    1 if successful,
+     *    0 otherwise
+     */
+    int frequency(int hz);
+
+    /** Write a CANMessage to the bus.
+     *
+     *  @param msg The CANMessage to write.
+     *
+     *  @returns
+     *    0 if write failed,
+     *    1 if write was successful
+     */
+    int write(CANMessage msg);
+
+    /** Read a CANMessage from the bus.
+     *
+     *  @param msg A CANMessage to read to.
+     *  @param handle message filter handle (0 for any message)
+     *
+     *  @returns
+     *    0 if no message arrived,
+     *    1 if message arrived
+     */
+    int read(CANMessage &msg, int handle = 0);
+
+    /** Reset CAN interface.
+     *
+     * To use after error overflow.
+     */
+    void reset();
+
+    /** Puts or removes the CAN interface into silent monitoring mode
+     *
+     *  @param silent boolean indicating whether to go into silent mode or not
+     */
+    void monitor(bool silent);
+
+    enum Mode {
+        Reset = 0,
+        Normal,
+        Silent,
+        LocalTest,
+        GlobalTest,
+        SilentTest
+    };
+
+    /** Change CAN operation to the specified mode
+     *
+     *  @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest)
+     *
+     *  @returns
+     *    0 if mode change failed or unsupported,
+     *    1 if mode change was successful
+     */
+    int mode(Mode mode);
+
+    /** Filter out incomming messages
+     *
+     *  @param id the id to filter on
+     *  @param mask the mask applied to the id
+     *  @param format format to filter on (Default CANAny)
+     *  @param handle message filter handle (Optional)
+     *
+     *  @returns
+     *    0 if filter change failed or unsupported,
+     *    new filter handle if successful
+     */
+    int filter(unsigned int id, unsigned int mask, CANFormat format = CANAny, int handle = 0);
+
+    /** Returns number of read errors to detect read overflow errors.
+     */
+    unsigned char rderror();
+
+    /** Returns number of write errors to detect write overflow errors.
+     */
+    unsigned char tderror();
+
+    enum IrqType {
+        RxIrq = 0,
+        TxIrq,
+        EwIrq,
+        DoIrq,
+        WuIrq,
+        EpIrq,
+        AlIrq,
+        BeIrq,
+        IdIrq
+    };
+
+    /** Attach a function to call whenever a CAN frame received interrupt is
+     *  generated.
+     *
+     *  @param fptr A pointer to a void function, or 0 to set as none
+     *  @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)
+     */
+    void attach(void (*fptr)(void), IrqType type=RxIrq);
+
+   /** Attach a member function to call whenever a CAN frame received interrupt
+    *  is generated.
+    *
+    *  @param tptr pointer to the object to call the member function on
+    *  @param mptr pointer to the member function to be called
+    *  @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
+    */
+   template<typename T>
+   void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
+        if((mptr != NULL) && (tptr != NULL)) {
+            _irq[type].attach(tptr, mptr);
+            can_irq_set(&_can, (CanIrqType)type, 1);
+        }
+        else {
+            can_irq_set(&_can, (CanIrqType)type, 0);
+        }
+    }
+
+    static void _irq_handler(uint32_t id, CanIrqType type);
+
+protected:
+    can_t           _can;
+    FunctionPointer _irq[9];
+};
+
+} // namespace mbed
+
+#endif
+
+#endif    // MBED_CAN_H
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/CallChain.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,182 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CALLCHAIN_H
+#define MBED_CALLCHAIN_H
+
+#include "FunctionPointer.h"
+#include <string.h>
+
+namespace mbed {
+
+/** Group one or more functions in an instance of a CallChain, then call them in
+ * sequence using CallChain::call(). Used mostly by the interrupt chaining code,
+ * but can be used for other purposes.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * CallChain chain;
+ *
+ * void first(void) {
+ *     printf("'first' function.\n");
+ * }
+ *
+ * void second(void) {
+ *     printf("'second' function.\n");
+ * }
+ *
+ * class Test {
+ * public:
+ *     void f(void) {
+ *         printf("A::f (class member).\n");
+ *     }
+ * };
+ *
+ * int main() {
+ *     Test test;
+ *
+ *     chain.add(second);
+ *     chain.add_front(first);
+ *     chain.add(&test, &Test::f);
+ *     chain.call();
+ * }
+ * @endcode
+ */
+
+typedef FunctionPointer* pFunctionPointer_t;
+
+class CallChain {
+public:
+    /** Create an empty chain
+     *
+     *  @param size (optional) Initial size of the chain
+     */
+    CallChain(int size = 4);
+    virtual ~CallChain();
+
+    /** Add a function at the end of the chain
+     *
+     *  @param function A pointer to a void function
+     *
+     *  @returns
+     *  The function object created for 'function'
+     */
+    pFunctionPointer_t add(void (*function)(void));
+
+    /** Add a function at the end of the chain
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     *
+     *  @returns
+     *  The function object created for 'tptr' and 'mptr'
+     */
+    template<typename T>
+    pFunctionPointer_t add(T *tptr, void (T::*mptr)(void)) {
+        return common_add(new FunctionPointer(tptr, mptr));
+    }
+
+    /** Add a function at the beginning of the chain
+     *
+     *  @param function A pointer to a void function
+     *
+     *  @returns
+     *  The function object created for 'function'
+     */
+    pFunctionPointer_t add_front(void (*function)(void));
+
+    /** Add a function at the beginning of the chain
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     *
+     *  @returns
+     *  The function object created for 'tptr' and 'mptr'
+     */
+    template<typename T>
+    pFunctionPointer_t add_front(T *tptr, void (T::*mptr)(void)) {
+        return common_add_front(new FunctionPointer(tptr, mptr));
+    }
+
+    /** Get the number of functions in the chain
+     */
+    int size() const;
+
+    /** Get a function object from the chain
+     *
+     *  @param i function object index
+     *
+     *  @returns
+     *  The function object at position 'i' in the chain
+     */
+    pFunctionPointer_t get(int i) const;
+
+    /** Look for a function object in the call chain
+     *
+     *  @param f the function object to search
+     *
+     *  @returns
+     *  The index of the function object if found, -1 otherwise.
+     */
+    int find(pFunctionPointer_t f) const;
+
+    /** Clear the call chain (remove all functions in the chain).
+     */
+    void clear();
+
+    /** Remove a function object from the chain
+     *
+     *  @arg f the function object to remove
+     *
+     *  @returns
+     *  true if the function object was found and removed, false otherwise.
+     */
+    bool remove(pFunctionPointer_t f);
+
+    /** Call all the functions in the chain in sequence
+     */
+    void call();
+
+#ifdef MBED_OPERATORS
+    void operator ()(void) {
+        call();
+    }
+    pFunctionPointer_t operator [](int i) const {
+        return get(i);
+    }
+#endif
+
+private:
+    void _check_size();
+    pFunctionPointer_t common_add(pFunctionPointer_t pf);
+    pFunctionPointer_t common_add_front(pFunctionPointer_t pf);
+
+    pFunctionPointer_t* _chain;
+    int _size;
+    int _elements;
+
+    /* disallow copy constructor and assignment operators */
+private:
+    CallChain(const CallChain&);
+    CallChain & operator = (const CallChain&);
+};
+
+} // namespace mbed
+
+#endif
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/DigitalIn.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,98 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALIN_H
+#define MBED_DIGITALIN_H
+
+#include "platform.h"
+
+#include "gpio_api.h"
+
+namespace mbed {
+
+/** A digital input, used for reading the state of a pin
+ *
+ * Example:
+ * @code
+ * // Flash an LED while a DigitalIn is true
+ *
+ * #include "mbed.h"
+ *
+ * DigitalIn enable(p5);
+ * DigitalOut led(LED1);
+ *
+ * int main() {
+ *     while(1) {
+ *         if(enable) {
+ *             led = !led;
+ *         }
+ *         wait(0.25);
+ *     }
+ * }
+ * @endcode
+ */
+class DigitalIn {
+
+public:
+    /** Create a DigitalIn connected to the specified pin
+     *
+     *  @param pin DigitalIn pin to connect to
+     */
+    DigitalIn(PinName pin) : gpio() {
+        gpio_init_in(&gpio, pin);
+    }
+
+    /** Create a DigitalIn connected to the specified pin
+     *
+     *  @param pin DigitalIn pin to connect to
+     *  @param mode the initial mode of the pin
+     */
+    DigitalIn(PinName pin, PinMode mode) : gpio() {
+        gpio_init_in_ex(&gpio, pin, mode);
+    }
+    /** Read the input, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    An integer representing the state of the input pin,
+     *    0 for logical 0, 1 for logical 1
+     */
+    int read() {
+        return gpio_read(&gpio);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode pull) {
+        gpio_mode(&gpio, pull);
+    }
+
+#ifdef MBED_OPERATORS
+    /** An operator shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+#endif
+
+protected:
+    gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/DigitalInOut.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,115 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALINOUT_H
+#define MBED_DIGITALINOUT_H
+
+#include "platform.h"
+
+#include "gpio_api.h"
+
+namespace mbed {
+
+/** A digital input/output, used for setting or reading a bi-directional pin
+ */
+class DigitalInOut {
+
+public:
+    /** Create a DigitalInOut connected to the specified pin
+     *
+     *  @param pin DigitalInOut pin to connect to
+     */
+    DigitalInOut(PinName pin) : gpio() {
+        gpio_init_in(&gpio, pin);
+    }
+
+    /** Create a DigitalInOut connected to the specified pin
+     *
+     *  @param pin DigitalInOut pin to connect to
+     *  @param direction the initial direction of the pin
+     *  @param mode the initial mode of the pin
+     *  @param value the initial value of the pin if is an output
+     */
+    DigitalInOut(PinName pin, PinDirection direction, PinMode mode, int value) : gpio() {
+        gpio_init_inout(&gpio, pin, direction, mode, value);
+    }
+
+    /** Set the output, specified as 0 or 1 (int)
+     *
+     *  @param value An integer specifying the pin output value,
+     *      0 for logical 0, 1 (or any other non-zero value) for logical 1
+     */
+    void write(int value) {
+        gpio_write(&gpio, value);
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    an integer representing the output setting of the pin if it is an output,
+     *    or read the input if set as an input
+     */
+    int read() {
+        return gpio_read(&gpio);
+    }
+
+    /** Set as an output
+     */
+    void output() {
+        gpio_dir(&gpio, PIN_OUTPUT);
+    }
+
+    /** Set as an input
+     */
+    void input() {
+        gpio_dir(&gpio, PIN_INPUT);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode pull) {
+        gpio_mode(&gpio, pull);
+    }
+
+#ifdef MBED_OPERATORS
+    /** A shorthand for write()
+     */
+    DigitalInOut& operator= (int value) {
+        write(value);
+        return *this;
+    }
+
+    DigitalInOut& operator= (DigitalInOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+#endif
+
+protected:
+    gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/DigitalOut.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,107 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALOUT_H
+#define MBED_DIGITALOUT_H
+
+#include "platform.h"
+#include "gpio_api.h"
+
+namespace mbed {
+
+/** A digital output, used for setting the state of a pin
+ *
+ * Example:
+ * @code
+ * // Toggle a LED
+ * #include "mbed.h"
+ *
+ * DigitalOut led(LED1);
+ *
+ * int main() {
+ *     while(1) {
+ *         led = !led;
+ *         wait(0.2);
+ *     }
+ * }
+ * @endcode
+ */
+class DigitalOut {
+
+public:
+    /** Create a DigitalOut connected to the specified pin
+     *
+     *  @param pin DigitalOut pin to connect to
+     */
+    DigitalOut(PinName pin) : gpio() {
+        gpio_init_out(&gpio, pin);
+    }
+
+    /** Create a DigitalOut connected to the specified pin
+     *
+     *  @param pin DigitalOut pin to connect to
+     *  @param value the initial pin value
+     */
+    DigitalOut(PinName pin, int value) : gpio() {
+        gpio_init_out_ex(&gpio, pin, value);
+    }
+
+    /** Set the output, specified as 0 or 1 (int)
+     *
+     *  @param value An integer specifying the pin output value,
+     *      0 for logical 0, 1 (or any other non-zero value) for logical 1
+     */
+    void write(int value) {
+        gpio_write(&gpio, value);
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    an integer representing the output setting of the pin,
+     *    0 for logical 0, 1 for logical 1
+     */
+    int read() {
+        return gpio_read(&gpio);
+    }
+
+#ifdef MBED_OPERATORS
+    /** A shorthand for write()
+     */
+    DigitalOut& operator= (int value) {
+        write(value);
+        return *this;
+    }
+
+    DigitalOut& operator= (DigitalOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+#endif
+
+protected:
+    gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/DirHandle.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,105 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIRHANDLE_H
+#define MBED_DIRHANDLE_H
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+#   define NAME_MAX 255
+typedef int mode_t;
+
+#else
+#   include <sys/syslimits.h>
+#endif
+
+#include "FileHandle.h"
+
+struct dirent {
+    char d_name[NAME_MAX+1];
+};
+
+namespace mbed {
+
+/** Represents a directory stream. Objects of this type are returned
+ *  by a FileSystemLike's opendir method. Implementations must define
+ *  at least closedir, readdir and rewinddir.
+ *
+ *  If a FileSystemLike class defines the opendir method, then the
+ *  directories of an object of that type can be accessed by
+ *  DIR *d = opendir("/example/directory") (or opendir("/example")
+ *  to open the root of the filesystem), and then using readdir(d) etc.
+ *
+ *  The root directory is considered to contain all FileLike and
+ *  FileSystemLike objects, so the DIR* returned by opendir("/") will
+ *  reflect this.
+ */
+class DirHandle {
+
+public:
+    /** Closes the directory.
+     *
+     *  @returns
+     *    0 on success,
+     *   -1 on error.
+     */
+    virtual int closedir()=0;
+
+    /** Return the directory entry at the current position, and
+     *  advances the position to the next entry.
+     *
+     * @returns
+     *  A pointer to a dirent structure representing the
+     *  directory entry at the current position, or NULL on reaching
+     *  end of directory or error.
+     */
+    virtual struct dirent *readdir()=0;
+
+    /** Resets the position to the beginning of the directory.
+     */
+    virtual void rewinddir()=0;
+
+    /** Returns the current position of the DirHandle.
+     *
+     * @returns
+     *   the current position,
+     *  -1 on error.
+     */
+    virtual off_t telldir() { return -1; }
+
+    /** Sets the position of the DirHandle.
+     *
+     *  @param location The location to seek to. Must be a value returned by telldir.
+     */
+    virtual void seekdir(off_t location) { }
+
+    virtual ~DirHandle() {}
+};
+
+} // namespace mbed
+
+typedef mbed::DirHandle DIR;
+
+extern "C" {
+    DIR *opendir(const char*);
+    struct dirent *readdir(DIR *);
+    int closedir(DIR*);
+    void rewinddir(DIR*);
+    long telldir(DIR*);
+    void seekdir(DIR*, long);
+    int mkdir(const char *name, mode_t n);
+};
+
+#endif /* MBED_DIRHANDLE_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/Ethernet.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,171 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ETHERNET_H
+#define MBED_ETHERNET_H
+
+#include "platform.h"
+
+#if DEVICE_ETHERNET
+
+namespace mbed {
+
+/** An ethernet interface, to use with the ethernet pins.
+ *
+ * Example:
+ * @code
+ * // Read destination and source from every ethernet packet
+ *
+ * #include "mbed.h"
+ *
+ * Ethernet eth;
+ *
+ * int main() {
+ *     char buf[0x600];
+ *
+ *     while(1) {
+ *         int size = eth.receive();
+ *         if(size > 0) {
+ *             eth.read(buf, size);
+ *             printf("Destination:  %02X:%02X:%02X:%02X:%02X:%02X\n",
+ *                     buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+ *             printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n",
+ *                     buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]);
+ *         }
+ *
+ *         wait(1);
+ *     }
+ * }
+ * @endcode
+ */
+class Ethernet {
+
+public:
+
+    /** Initialise the ethernet interface.
+     */
+    Ethernet();
+
+    /** Powers the hardware down.
+     */
+    virtual ~Ethernet();
+
+    enum Mode {
+        AutoNegotiate,
+        HalfDuplex10,
+        FullDuplex10,
+        HalfDuplex100,
+        FullDuplex100
+    };
+
+    /** Writes into an outgoing ethernet packet.
+     *
+     *  It will append size bytes of data to the previously written bytes.
+     *
+     *  @param data An array to write.
+     *  @param size The size of data.
+     *
+     *  @returns
+     *   The number of written bytes.
+     */
+    int write(const char *data, int size);
+
+    /** Send an outgoing ethernet packet.
+     *
+     *  After filling in the data in an ethernet packet it must be send.
+     *  Send will provide a new packet to write to.
+     *
+     *  @returns
+     *    0 if the sending was failed,
+     *    or the size of the packet successfully sent.
+     */
+    int send();
+
+    /** Recevies an arrived ethernet packet.
+     *
+     *  Receiving an ethernet packet will drop the last received ethernet packet
+     *  and make a new ethernet packet ready to read.
+     *  If no ethernet packet is arrived it will return 0.
+     *
+     *  @returns
+     *    0 if no ethernet packet is arrived,
+     *    or the size of the arrived packet.
+     */
+    int receive();
+
+    /** Read from an recevied ethernet packet.
+     *
+     *  After receive returnd a number bigger than 0it is
+     *  possible to read bytes from this packet.
+     *  Read will write up to size bytes into data.
+     *
+     *  It is possible to use read multible times.
+     *  Each time read will start reading after the last read byte before.
+     *
+     *  @returns
+     *  The number of byte read.
+     */
+    int read(char *data, int size);
+
+    /** Gives the ethernet address of the mbed.
+     *
+     *  @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in.
+     */
+    void address(char *mac);
+
+    /** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up.
+     *
+     *  @returns
+     *   0 if no ethernet link is pressent,
+     *   1 if an ethernet link is pressent.
+     *
+     * Example:
+     * @code
+     * // Using the Ethernet link function
+     * #include "mbed.h"
+     *
+     * Ethernet eth;
+     *
+     * int main() {
+     *     wait(1); // Needed after startup.
+     *     if (eth.link()) {
+     *          printf("online\n");
+     *     } else {
+     *          printf("offline\n");
+     *     }
+     * }
+     * @endcode
+     */
+    int link();
+
+    /** Sets the speed and duplex parameters of an ethernet link
+     *
+     * - AutoNegotiate      Auto negotiate speed and duplex
+     * - HalfDuplex10       10 Mbit, half duplex
+     * - FullDuplex10       10 Mbit, full duplex
+     * - HalfDuplex100      100 Mbit, half duplex
+     * - FullDuplex100      100 Mbit, full duplex
+     *
+     *  @param mode the speed and duplex mode to set the link to:
+     */
+    void set_link(Mode mode);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/FileBase.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,81 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEBASE_H
+#define MBED_FILEBASE_H
+
+typedef int FILEHANDLE;
+
+#include <stdio.h>
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+#    define O_RDONLY 0
+#    define O_WRONLY 1
+#    define O_RDWR   2
+#    define O_CREAT  0x0200
+#    define O_TRUNC  0x0400
+#    define O_APPEND 0x0008
+
+#    define NAME_MAX 255
+
+typedef int mode_t;
+typedef int ssize_t;
+typedef long off_t;
+
+#else
+#    include <sys/fcntl.h>
+#    include <sys/types.h>
+#    include <sys/syslimits.h>
+#endif
+
+#include "platform.h"
+
+namespace mbed {
+
+typedef enum {
+    FilePathType,
+    FileSystemPathType
+} PathType;
+
+class FileBase {
+public:
+    FileBase(const char *name, PathType t);
+
+    virtual ~FileBase();
+
+    const char* getName(void);
+    PathType    getPathType(void);
+
+    static FileBase *lookup(const char *name, unsigned int len);
+
+    static FileBase *get(int n);
+
+protected:
+    static FileBase *_head;
+
+    FileBase   *_next;
+    const char *_name;
+    PathType    _path_type;
+
+    /* disallow copy constructor and assignment operators */
+private:
+    FileBase(const FileBase&);
+    FileBase & operator = (const FileBase&);
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/FileHandle.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,120 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEHANDLE_H
+#define MBED_FILEHANDLE_H
+
+typedef int FILEHANDLE;
+
+#include <stdio.h>
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+typedef int ssize_t;
+typedef long off_t;
+
+#else
+#   include <sys/types.h>
+#endif
+
+namespace mbed {
+
+/** An OO equivalent of the internal FILEHANDLE variable
+ *  and associated _sys_* functions.
+ *
+ * FileHandle is an abstract class, needing at least sys_write and
+ *  sys_read to be implmented for a simple interactive device.
+ *
+ * No one ever directly tals to/instanciates a FileHandle - it gets
+ *  created by FileSystem, and wrapped up by stdio.
+ */
+class FileHandle {
+
+public:
+    /** Write the contents of a buffer to the file
+     *
+     *  @param buffer the buffer to write from
+     *  @param length the number of characters to write
+     *
+     *  @returns
+     *  The number of characters written (possibly 0) on success, -1 on error.
+     */
+    virtual ssize_t write(const void* buffer, size_t length) = 0;
+
+    /** Close the file
+     *
+     *  @returns
+     *  Zero on success, -1 on error.
+     */
+    virtual int close() = 0;
+
+    /** Function read
+     *  Reads the contents of the file into a buffer
+     *
+     *  @param buffer the buffer to read in to
+     *  @param length the number of characters to read
+     *
+     *  @returns
+     *  The number of characters read (zero at end of file) on success, -1 on error.
+     */
+    virtual ssize_t read(void* buffer, size_t length) = 0;
+
+    /** Check if the handle is for a interactive terminal device.
+     * If so, line buffered behaviour is used by default
+     *
+     *  @returns
+     *    1 if it is a terminal,
+     *    0 otherwise
+     */
+    virtual int isatty() = 0;
+
+    /** Move the file position to a given offset from a given location.
+     *
+     *  @param offset The offset from whence to move to
+     *  @param whence SEEK_SET for the start of the file, SEEK_CUR for the
+     *   current file position, or SEEK_END for the end of the file.
+     *
+     *  @returns
+     *    new file position on success,
+     *    -1 on failure or unsupported
+     */
+    virtual off_t lseek(off_t offset, int whence) = 0;
+
+    /** Flush any buffers associated with the FileHandle, ensuring it
+     *  is up to date on disk
+     *
+     *  @returns
+     *    0 on success or un-needed,
+     *   -1 on error
+     */
+    virtual int fsync() = 0;
+
+    virtual off_t flen() {
+        /* remember our current position */
+        off_t pos = lseek(0, SEEK_CUR);
+        if(pos == -1) return -1;
+        /* seek to the end to get the file length */
+        off_t res = lseek(0, SEEK_END);
+        /* return to our old position */
+        lseek(pos, SEEK_SET);
+        return res;
+    }
+
+    virtual ~FileHandle();
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/FileLike.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILELIKE_H
+#define MBED_FILELIKE_H
+
+#include "FileBase.h"
+#include "FileHandle.h"
+
+namespace mbed {
+
+/* Class FileLike
+ *  A file-like object is one that can be opened with fopen by
+ *  fopen("/name", mode). It is intersection of the classes Base and
+ *  FileHandle.
+ */
+class FileLike : public FileHandle, public FileBase {
+
+public:
+    /* Constructor FileLike
+     *
+     * Variables
+     *  name - The name to use to open the file.
+     */
+    FileLike(const char *name);
+
+    virtual ~FileLike();
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/FilePath.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEPATH_H
+#define MBED_FILEPATH_H
+
+#include "platform.h"
+
+#include "FileSystemLike.h"
+#include "FileLike.h"
+
+namespace mbed {
+
+class FilePath {
+public:
+    FilePath(const char* file_path);
+
+    const char* fileName(void);
+
+    bool          isFileSystem(void);
+    FileSystemLike* fileSystem(void);
+
+    bool    isFile(void);
+    FileLike* file(void);
+    bool    exists(void);
+
+private:
+    const char* file_name;
+    FileBase* fb;
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/FileSystemLike.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,105 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILESYSTEMLIKE_H
+#define MBED_FILESYSTEMLIKE_H
+
+#include "platform.h"
+
+#include "FileBase.h"
+#include "FileHandle.h"
+#include "DirHandle.h"
+
+namespace mbed {
+
+/** A filesystem-like object is one that can be used to open files
+ *  though it by fopen("/name/filename", mode)
+ *
+ *  Implementations must define at least open (the default definitions
+ *  of the rest of the functions just return error values).
+ */
+class FileSystemLike : public FileBase {
+
+public:
+    /** FileSystemLike constructor
+     *
+     *  @param name The name to use for the filesystem.
+     */
+    FileSystemLike(const char *name);
+
+    virtual ~FileSystemLike();
+
+    static DirHandle *opendir();
+    friend class BaseDirHandle;
+
+    /** Opens a file from the filesystem
+     *
+     *  @param filename The name of the file to open.
+     *  @param flags One of O_RDONLY, O_WRONLY, or O_RDWR, OR'd with
+     *    zero or more of O_CREAT, O_TRUNC, or O_APPEND.
+     *
+     *  @returns
+     *    A pointer to a FileHandle object representing the
+     *   file on success, or NULL on failure.
+     */
+    virtual FileHandle *open(const char *filename, int flags) = 0;
+
+    /** Remove a file from the filesystem.
+     *
+     *  @param filename the name of the file to remove.
+     *  @param returns 0 on success, -1 on failure.
+     */
+    virtual int remove(const char *filename) { return -1; };
+
+    /** Rename a file in the filesystem.
+     *
+     *  @param oldname the name of the file to rename.
+     *  @param newname the name to rename it to.
+     *
+     *  @returns
+     *    0 on success,
+     *   -1 on failure.
+     */
+    virtual int rename(const char *oldname, const char *newname) { return -1; };
+
+    /** Opens a directory in the filesystem and returns a DirHandle
+     *   representing the directory stream.
+     *
+     *  @param name The name of the directory to open.
+     *
+     *  @returns
+     *    A DirHandle representing the directory stream, or
+     *   NULL on failure.
+     */
+    virtual DirHandle *opendir(const char *name) { return NULL; };
+
+    /** Creates a directory in the filesystem.
+     *
+     *  @param name The name of the directory to create.
+     *  @param mode The permissions to create the directory with.
+     *
+     *  @returns
+     *    0 on success,
+     *   -1 on failure.
+     */
+    virtual int mkdir(const char *name, mode_t mode) { return -1; }
+
+    // TODO other filesystem functions (mkdir, rm, rn, ls etc)
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/FunctionPointer.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,95 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FUNCTIONPOINTER_H
+#define MBED_FUNCTIONPOINTER_H
+
+#include <string.h>
+
+namespace mbed {
+
+typedef void (*pvoidf_t)(void);
+
+/** A class for storing and calling a pointer to a static or member void function
+ */
+class FunctionPointer {
+public:
+
+    /** Create a FunctionPointer, attaching a static function
+     *
+     *  @param function The void static function to attach (default is none)
+     */
+    FunctionPointer(void (*function)(void) = 0);
+
+    /** Create a FunctionPointer, attaching a member function
+     *
+     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)
+     *  @param function The address of the void member function to attach
+     */
+    template<typename T>
+    FunctionPointer(T *object, void (T::*member)(void)) {
+        attach(object, member);
+    }
+
+    /** Attach a static function
+     *
+     *  @param function The void static function to attach (default is none)
+     */
+    void attach(void (*function)(void) = 0);
+
+    /** Attach a member function
+     *
+     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)
+     *  @param function The address of the void member function to attach
+     */
+    template<typename T>
+    void attach(T *object, void (T::*member)(void)) {
+        _object = static_cast<void*>(object);
+        memcpy(_member, (char*)&member, sizeof(member));
+        _membercaller = &FunctionPointer::membercaller<T>;
+        _function = 0;
+    }
+
+    /** Call the attached static or member function
+     */
+    void call();
+
+    pvoidf_t get_function() const {
+        return (pvoidf_t)_function;
+    }
+
+#ifdef MBED_OPERATORS
+    void operator ()(void);
+#endif
+
+private:
+    template<typename T>
+    static void membercaller(void *object, char *member) {
+        T* o = static_cast<T*>(object);
+        void (T::*m)(void);
+        memcpy((char*)&m, member, sizeof(m));
+        (o->*m)();
+    }
+
+    void (*_function)(void);             // static function pointer - 0 if none attached
+    void *_object;                       // object this pointer - 0 if none attached
+    char _member[16];                    // raw member function pointer storage - converted back by registered _membercaller
+    void (*_membercaller)(void*, char*); // registered membercaller function to convert back and call _member on _object
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/I2C.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,145 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_H
+#define MBED_I2C_H
+
+#include "platform.h"
+
+#if DEVICE_I2C
+
+#include "i2c_api.h"
+
+namespace mbed {
+
+/** An I2C Master, used for communicating with I2C slave devices
+ *
+ * Example:
+ * @code
+ * // Read from I2C slave at address 0x62
+ *
+ * #include "mbed.h"
+ *
+ * I2C i2c(p28, p27);
+ *
+ * int main() {
+ *     int address = 0x62;
+ *     char data[2];
+ *     i2c.read(address, data, 2);
+ * }
+ * @endcode
+ */
+class I2C {
+
+public:
+    enum RxStatus {
+        NoData,
+        MasterGeneralCall,
+        MasterWrite,
+        MasterRead
+    };
+
+    enum Acknowledge {
+        NoACK = 0,
+        ACK   = 1
+    };
+
+    /** Create an I2C Master interface, connected to the specified pins
+     *
+     *  @param sda I2C data line pin
+     *  @param scl I2C clock line pin
+     */
+    I2C(PinName sda, PinName scl);
+
+    /** Set the frequency of the I2C interface
+     *
+     *  @param hz The bus frequency in hertz
+     */
+    void frequency(int hz);
+
+    /** Read from an I2C slave
+     *
+     * Performs a complete read transaction. The bottom bit of
+     * the address is forced to 1 to indicate a read.
+     *
+     *  @param address 8-bit I2C slave address [ addr | 1 ]
+     *  @param data Pointer to the byte-array to read data in to
+     *  @param length Number of bytes to read
+     *  @param repeated Repeated start, true - don't send stop at end
+     *
+     *  @returns
+     *       0 on success (ack),
+     *   non-0 on failure (nack)
+     */
+    int read(int address, char *data, int length, bool repeated = false);
+
+    /** Read a single byte from the I2C bus
+     *
+     *  @param ack indicates if the byte is to be acknowledged (1 = acknowledge)
+     *
+     *  @returns
+     *    the byte read
+     */
+    int read(int ack);
+
+    /** Write to an I2C slave
+     *
+     * Performs a complete write transaction. The bottom bit of
+     * the address is forced to 0 to indicate a write.
+     *
+     *  @param address 8-bit I2C slave address [ addr | 0 ]
+     *  @param data Pointer to the byte-array data to send
+     *  @param length Number of bytes to send
+     *  @param repeated Repeated start, true - do not send stop at end
+     *
+     *  @returns
+     *       0 on success (ack),
+     *   non-0 on failure (nack)
+     */
+    int write(int address, const char *data, int length, bool repeated = false);
+
+    /** Write single byte out on the I2C bus
+     *
+     *  @param data data to write out on bus
+     *
+     *  @returns
+     *    '1' if an ACK was received,
+     *    '0' otherwise
+     */
+    int write(int data);
+
+    /** Creates a start condition on the I2C bus
+     */
+
+    void start(void);
+
+    /** Creates a stop condition on the I2C bus
+     */
+    void stop(void);
+
+protected:
+    void aquire();
+
+    i2c_t _i2c;
+    static I2C  *_owner;
+    int         _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/I2CSlave.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,155 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_SLAVE_H
+#define MBED_I2C_SLAVE_H
+
+#include "platform.h"
+
+#if DEVICE_I2CSLAVE
+
+#include "i2c_api.h"
+
+namespace mbed {
+
+/** An I2C Slave, used for communicating with an I2C Master device
+ *
+ * Example:
+ * @code
+ * // Simple I2C responder
+ * #include <mbed.h>
+ *
+ * I2CSlave slave(p9, p10);
+ *
+ * int main() {
+ *     char buf[10];
+ *     char msg[] = "Slave!";
+ *
+ *     slave.address(0xA0);
+ *     while (1) {
+ *         int i = slave.receive();
+ *         switch (i) {
+ *             case I2CSlave::ReadAddressed:
+ *                 slave.write(msg, strlen(msg) + 1); // Includes null char
+ *                 break;
+ *             case I2CSlave::WriteGeneral:
+ *                 slave.read(buf, 10);
+ *                 printf("Read G: %s\n", buf);
+ *                 break;
+ *             case I2CSlave::WriteAddressed:
+ *                 slave.read(buf, 10);
+ *                 printf("Read A: %s\n", buf);
+ *                 break;
+ *         }
+ *         for(int i = 0; i < 10; i++) buf[i] = 0;    // Clear buffer
+ *     }
+ * }
+ * @endcode
+ */
+class I2CSlave {
+
+public:
+    enum RxStatus {
+        NoData         = 0,
+        ReadAddressed  = 1,
+        WriteGeneral   = 2,
+        WriteAddressed = 3
+    };
+
+    /** Create an I2C Slave interface, connected to the specified pins.
+     *
+     *  @param sda I2C data line pin
+     *  @param scl I2C clock line pin
+     */
+    I2CSlave(PinName sda, PinName scl);
+
+    /** Set the frequency of the I2C interface
+     *
+     *  @param hz The bus frequency in hertz
+     */
+    void frequency(int hz);
+
+    /** Checks to see if this I2C Slave has been addressed.
+     *
+     *  @returns
+     *  A status indicating if the device has been addressed, and how
+     *  - NoData            - the slave has not been addressed
+     *  - ReadAddressed     - the master has requested a read from this slave
+     *  - WriteAddressed    - the master is writing to this slave
+     *  - WriteGeneral      - the master is writing to all slave
+     */
+    int receive(void);
+
+    /** Read from an I2C master.
+     *
+     *  @param data pointer to the byte array to read data in to
+     *  @param length maximum number of bytes to read
+     *
+     *  @returns
+     *       0 on success,
+     *   non-0 otherwise
+     */
+    int read(char *data, int length);
+
+    /** Read a single byte from an I2C master.
+     *
+     *  @returns
+     *    the byte read
+     */
+    int read(void);
+
+    /** Write to an I2C master.
+     *
+     *  @param data pointer to the byte array to be transmitted
+     *  @param length the number of bytes to transmite
+     *
+     *  @returns
+     *       0 on success,
+     *   non-0 otherwise
+     */
+    int write(const char *data, int length);
+
+    /** Write a single byte to an I2C master.
+     *
+     *  @data the byte to write
+     *
+     *  @returns
+     *    '1' if an ACK was received,
+     *    '0' otherwise
+     */
+    int write(int data);
+
+    /** Sets the I2C slave address.
+     *
+     *  @param address The address to set for the slave (ignoring the least
+     *  signifcant bit). If set to 0, the slave will only respond to the
+     *  general call address.
+     */
+    void address(int address);
+
+    /** Reset the I2C slave back into the known ready receiving state.
+     */
+    void stop(void);
+
+protected:
+    i2c_t _i2c;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/InterruptIn.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,136 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERRUPTIN_H
+#define MBED_INTERRUPTIN_H
+
+#include "platform.h"
+
+#if DEVICE_INTERRUPTIN
+
+#include "gpio_api.h"
+#include "gpio_irq_api.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** A digital interrupt input, used to call a function on a rising or falling edge
+ *
+ * Example:
+ * @code
+ * // Flash an LED while waiting for events
+ *
+ * #include "mbed.h"
+ *
+ * InterruptIn event(p16);
+ * DigitalOut led(LED1);
+ *
+ * void trigger() {
+ *     printf("triggered!\n");
+ * }
+ *
+ * int main() {
+ *     event.rise(&trigger);
+ *     while(1) {
+ *         led = !led;
+ *         wait(0.25);
+ *     }
+ * }
+ * @endcode
+ */
+class InterruptIn {
+
+public:
+
+    /** Create an InterruptIn connected to the specified pin
+     *
+     *  @param pin InterruptIn pin to connect to
+     *  @param name (optional) A string to identify the object
+     */
+    InterruptIn(PinName pin);
+    virtual ~InterruptIn();
+
+     int read();
+#ifdef MBED_OPERATORS
+    operator int();
+
+#endif
+
+    /** Attach a function to call when a rising edge occurs on the input
+     *
+     *  @param fptr A pointer to a void function, or 0 to set as none
+     */
+    void rise(void (*fptr)(void));
+
+    /** Attach a member function to call when a rising edge occurs on the input
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     */
+    template<typename T>
+    void rise(T* tptr, void (T::*mptr)(void)) {
+        _rise.attach(tptr, mptr);
+        gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
+    }
+
+    /** Attach a function to call when a falling edge occurs on the input
+     *
+     *  @param fptr A pointer to a void function, or 0 to set as none
+     */
+    void fall(void (*fptr)(void));
+
+    /** Attach a member function to call when a falling edge occurs on the input
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     */
+    template<typename T>
+    void fall(T* tptr, void (T::*mptr)(void)) {
+        _fall.attach(tptr, mptr);
+        gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone
+     */
+    void mode(PinMode pull);
+
+    /** Enable IRQ. This method depends on hw implementation, might enable one
+     *  port interrupts. For further information, check gpio_irq_enable().
+     */
+    void enable_irq();
+
+    /** Disable IRQ. This method depends on hw implementation, might disable one
+     *  port interrupts. For further information, check gpio_irq_disable().
+     */
+    void disable_irq();
+
+    static void _irq_handler(uint32_t id, gpio_irq_event event);
+
+protected:
+    gpio_t gpio;
+    gpio_irq_t gpio_irq;
+
+    FunctionPointer _rise;
+    FunctionPointer _fall;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/InterruptManager.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,144 @@
+#ifndef MBED_INTERRUPTMANAGER_H
+#define MBED_INTERRUPTMANAGER_H
+
+#include "cmsis.h"
+#include "CallChain.h"
+#include <string.h>
+
+namespace mbed {
+
+/** Use this singleton if you need to chain interrupt handlers.
+ *
+ * Example (for LPC1768):
+ * @code
+ * #include "InterruptManager.h"
+ * #include "mbed.h"
+ *
+ * Ticker flipper;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * void flip(void) {
+ *     led1 = !led1;
+ * }
+ *
+ * void handler(void) {
+ *     led2 = !led1;
+ * }
+ *
+ * int main() {
+ *     led1 = led2 = 0;
+ *     flipper.attach(&flip, 1.0);
+ *     InterruptManager::get()->add_handler(handler, TIMER3_IRQn);
+ * }
+ * @endcode
+ */
+class InterruptManager {
+public:
+    /** Return the only instance of this class
+     */
+    static InterruptManager* get();
+
+    /** Destroy the current instance of the interrupt manager
+     */
+    static void destroy();
+
+    /** Add a handler for an interrupt at the end of the handler list
+     *
+     *  @param function the handler to add
+     *  @param irq interrupt number
+     *
+     *  @returns
+     *  The function object created for 'function'
+     */
+    pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq) {
+        return add_common(function, irq);
+    }
+
+    /** Add a handler for an interrupt at the beginning of the handler list
+     *
+     *  @param function the handler to add
+     *  @param irq interrupt number
+     *
+     *  @returns
+     *  The function object created for 'function'
+     */
+    pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq) {
+        return add_common(function, irq, true);
+    }
+
+    /** Add a handler for an interrupt at the end of the handler list
+     *
+     *  @param tptr pointer to the object that has the handler function
+     *  @param mptr pointer to the actual handler function
+     *  @param irq interrupt number
+     *
+     *  @returns
+     *  The function object created for 'tptr' and 'mptr'
+     */
+    template<typename T>
+    pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
+        return add_common(tptr, mptr, irq);
+    }
+
+    /** Add a handler for an interrupt at the beginning of the handler list
+     *
+     *  @param tptr pointer to the object that has the handler function
+     *  @param mptr pointer to the actual handler function
+     *  @param irq interrupt number
+     *
+     *  @returns
+     *  The function object created for 'tptr' and 'mptr'
+     */
+    template<typename T>
+    pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
+        return add_common(tptr, mptr, irq, true);
+    }
+
+    /** Remove a handler from an interrupt
+     *
+     *  @param handler the function object for the handler to remove
+     *  @param irq the interrupt number
+     *
+     *  @returns
+     *  true if the handler was found and removed, false otherwise
+     */
+    bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq);
+
+private:
+    InterruptManager();
+    ~InterruptManager();
+
+    // We declare the copy contructor and the assignment operator, but we don't
+    // implement them. This way, if someone tries to copy/assign our instance,
+    // he will get an error at compile time.
+    InterruptManager(const InterruptManager&);
+    InterruptManager& operator =(const InterruptManager&);
+
+    template<typename T>
+    pFunctionPointer_t add_common(T *tptr, void (T::*mptr)(void), IRQn_Type irq, bool front=false) {
+        int irq_pos = get_irq_index(irq);
+        bool change = must_replace_vector(irq);
+
+        pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(tptr, mptr) : _chains[irq_pos]->add(tptr, mptr);
+        if (change)
+            NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+        return pf;
+    }
+
+    pFunctionPointer_t add_common(void (*function)(void), IRQn_Type irq, bool front=false);
+    bool must_replace_vector(IRQn_Type irq);
+    int get_irq_index(IRQn_Type irq);
+    void irq_helper();
+    void add_helper(void (*function)(void), IRQn_Type irq, bool front=false);
+    static void static_irq_helper();
+
+    CallChain* _chains[NVIC_NUM_VECTORS];
+    static InterruptManager* _instance;
+};
+
+} // namespace mbed
+
+#endif
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/LocalFileSystem.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOCALFILESYSTEM_H
+#define MBED_LOCALFILESYSTEM_H
+
+#include "platform.h"
+
+#if DEVICE_LOCALFILESYSTEM
+
+#include "FileSystemLike.h"
+
+namespace mbed {
+
+FILEHANDLE local_file_open(const char* name, int flags);
+
+class LocalFileHandle : public FileHandle {
+
+public:
+    LocalFileHandle(FILEHANDLE fh);
+
+    virtual int close();
+
+    virtual ssize_t write(const void *buffer, size_t length);
+
+    virtual ssize_t read(void *buffer, size_t length);
+
+    virtual int isatty();
+
+    virtual off_t lseek(off_t position, int whence);
+
+    virtual int fsync();
+
+    virtual off_t flen();
+
+protected:
+    FILEHANDLE _fh;
+    int pos;
+};
+
+/** A filesystem for accessing the local mbed Microcontroller USB disk drive
+ *
+ *  This allows programs to read and write files on the same disk drive that is used to program the
+ *  mbed Microcontroller. Once created, the standard C file access functions are used to open,
+ *  read and write files.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * LocalFileSystem local("local");               // Create the local filesystem under the name "local"
+ *
+ * int main() {
+ *     FILE *fp = fopen("/local/out.txt", "w");  // Open "out.txt" on the local file system for writing
+ *     fprintf(fp, "Hello World!");
+ *     fclose(fp);
+ *     remove("/local/out.txt");                 // Removes the file "out.txt" from the local file system
+ *
+ *     DIR *d = opendir("/local");               // Opens the root directory of the local file system
+ *     struct dirent *p;
+ *     while((p = readdir(d)) != NULL) {         // Print the names of the files in the local file system
+ *       printf("%s\n", p->d_name);              // to stdout.
+ *     }
+ *     closedir(d);
+ * }
+ * @endcode
+ *
+ * @note
+ *  If the microcontroller program makes an access to the local drive, it will be marked as "removed"
+ *  on the Host computer. This means it is no longer accessible from the Host Computer.
+ *
+ *  The drive will only re-appear when the microcontroller program exists. Note that if the program does
+ *  not exit, you will need to hold down reset on the mbed Microcontroller to be able to see the drive again!
+ */
+class LocalFileSystem : public FileSystemLike {
+
+public:
+    LocalFileSystem(const char* n) : FileSystemLike(n) {
+
+    }
+
+    virtual FileHandle *open(const char* name, int flags);
+    virtual int remove(const char *filename);
+    virtual DirHandle *opendir(const char *name);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/PortIn.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTIN_H
+#define MBED_PORTIN_H
+
+#include "platform.h"
+
+#if DEVICE_PORTIN
+
+#include "port_api.h"
+
+namespace mbed {
+
+/** A multiple pin digital input
+ *
+ *  Example:
+ * @code
+ * // Switch on an LED if any of mbed pins 21-26 is high
+ *
+ * #include "mbed.h"
+ *
+ * PortIn     p(Port2, 0x0000003F);   // p21-p26
+ * DigitalOut ind(LED4);
+ *
+ * int main() {
+ *     while(1) {
+ *         int pins = p.read();
+ *         if(pins) {
+ *             ind = 1;
+ *         } else {
+ *             ind = 0;
+ *         }
+ *     }
+ * }
+ * @endcode
+ */
+class PortIn {
+public:
+
+    /** Create an PortIn, connected to the specified port
+     *
+     *  @param port Port to connect to (Port0-Port5)
+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+        */
+    PortIn(PortName port, int mask = 0xFFFFFFFF) {
+        port_init(&_port, port, mask, PIN_INPUT);
+    }
+
+    /** Read the value currently output on the port
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated port pin setting
+     */
+    int read() {
+        return port_read(&_port);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode mode) {
+        port_mode(&_port, mode);
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+
+private:
+    port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/PortInOut.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,105 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTINOUT_H
+#define MBED_PORTINOUT_H
+
+#include "platform.h"
+
+#if DEVICE_PORTINOUT
+
+#include "port_api.h"
+
+namespace mbed {
+
+/** A multiple pin digital in/out used to set/read multiple bi-directional pins
+ */
+class PortInOut {
+public:
+
+    /** Create an PortInOut, connected to the specified port
+     *
+     *  @param port Port to connect to (Port0-Port5)
+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+     */
+    PortInOut(PortName port, int mask = 0xFFFFFFFF) {
+        port_init(&_port, port, mask, PIN_INPUT);
+    }
+
+    /** Write the value to the output port
+     *
+     *  @param value An integer specifying a bit to write for every corresponding port pin
+     */
+    void write(int value) {
+        port_write(&_port, value);
+    }
+
+    /** Read the value currently output on the port
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated port pin setting
+     */
+    int read() {
+        return port_read(&_port);
+    }
+
+    /** Set as an output
+     */
+    void output() {
+        port_dir(&_port, PIN_OUTPUT);
+    }
+
+    /** Set as an input
+     */
+    void input() {
+        port_dir(&_port, PIN_INPUT);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode mode) {
+        port_mode(&_port, mode);
+    }
+
+    /** A shorthand for write()
+     */
+    PortInOut& operator= (int value) {
+        write(value);
+        return *this;
+    }
+
+    PortInOut& operator= (PortInOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+
+private:
+    port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/PortOut.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,105 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTOUT_H
+#define MBED_PORTOUT_H
+
+#include "platform.h"
+
+#if DEVICE_PORTOUT
+
+#include "port_api.h"
+
+namespace mbed {
+/** A multiple pin digital out
+ *
+ * Example:
+ * @code
+ * // Toggle all four LEDs
+ *
+ * #include "mbed.h"
+ *
+ * // LED1 = P1.18  LED2 = P1.20  LED3 = P1.21  LED4 = P1.23
+ * #define LED_MASK 0x00B40000
+ *
+ * PortOut ledport(Port1, LED_MASK);
+ *
+ * int main() {
+ *     while(1) {
+ *         ledport = LED_MASK;
+ *         wait(1);
+ *         ledport = 0;
+ *         wait(1);
+ *     }
+ * }
+ * @endcode
+ */
+class PortOut {
+public:
+
+    /** Create an PortOut, connected to the specified port
+     *
+     *  @param port Port to connect to (Port0-Port5)
+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+     */
+    PortOut(PortName port, int mask = 0xFFFFFFFF) {
+        port_init(&_port, port, mask, PIN_OUTPUT);
+    }
+
+    /** Write the value to the output port
+     *
+     *  @param value An integer specifying a bit to write for every corresponding PortOut pin
+     */
+    void write(int value) {
+        port_write(&_port, value);
+    }
+
+    /** Read the value currently output on the port
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated PortOut pin setting
+     */
+    int read() {
+        return port_read(&_port);
+    }
+
+    /** A shorthand for write()
+     */
+    PortOut& operator= (int value) {
+        write(value);
+        return *this;
+    }
+
+    PortOut& operator= (PortOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+
+private:
+    port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/PwmOut.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,159 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PWMOUT_H
+#define MBED_PWMOUT_H
+
+#include "platform.h"
+
+#if DEVICE_PWMOUT
+#include "pwmout_api.h"
+
+namespace mbed {
+
+/** A pulse-width modulation digital output
+ *
+ * Example
+ * @code
+ * // Fade a led on.
+ * #include "mbed.h"
+ *
+ * PwmOut led(LED1);
+ *
+ * int main() {
+ *     while(1) {
+ *         led = led + 0.01;
+ *         wait(0.2);
+ *         if(led == 1.0) {
+ *             led = 0;
+ *         }
+ *     }
+ * }
+ * @endcode
+ *
+ * @note
+ *  On the LPC1768 and LPC2368, the PWMs all share the same
+ *  period - if you change the period for one, you change it for all.
+ *  Although routines that change the period maintain the duty cycle
+ *  for its PWM, all other PWMs will require their duty cycle to be
+ *  refreshed.
+ */
+class PwmOut {
+
+public:
+
+    /** Create a PwmOut connected to the specified pin
+     *
+     *  @param pin PwmOut pin to connect to
+     */
+    PwmOut(PinName pin) {
+        pwmout_init(&_pwm, pin);
+    }
+
+    /** Set the ouput duty-cycle, specified as a percentage (float)
+     *
+     *  @param value A floating-point value representing the output duty-cycle,
+     *    specified as a percentage. The value should lie between
+     *    0.0f (representing on 0%) and 1.0f (representing on 100%).
+     *    Values outside this range will be saturated to 0.0f or 1.0f.
+     */
+    void write(float value) {
+        pwmout_write(&_pwm, value);
+    }
+
+    /** Return the current output duty-cycle setting, measured as a percentage (float)
+     *
+     *  @returns
+     *    A floating-point value representing the current duty-cycle being output on the pin,
+     *    measured as a percentage. The returned value will lie between
+     *    0.0f (representing on 0%) and 1.0f (representing on 100%).
+     *
+     *  @note
+     *  This value may not match exactly the value set by a previous <write>.
+     */
+    float read() {
+        return pwmout_read(&_pwm);
+    }
+
+    /** Set the PWM period, specified in seconds (float), keeping the duty cycle the same.
+     *
+     *  @note
+     *   The resolution is currently in microseconds; periods smaller than this
+     *   will be set to zero.
+     */
+    void period(float seconds) {
+        pwmout_period(&_pwm, seconds);
+    }
+
+    /** Set the PWM period, specified in milli-seconds (int), keeping the duty cycle the same.
+     */
+    void period_ms(int ms) {
+        pwmout_period_ms(&_pwm, ms);
+    }
+
+    /** Set the PWM period, specified in micro-seconds (int), keeping the duty cycle the same.
+     */
+    void period_us(int us) {
+        pwmout_period_us(&_pwm, us);
+    }
+
+    /** Set the PWM pulsewidth, specified in seconds (float), keeping the period the same.
+     */
+    void pulsewidth(float seconds) {
+        pwmout_pulsewidth(&_pwm, seconds);
+    }
+
+    /** Set the PWM pulsewidth, specified in milli-seconds (int), keeping the period the same.
+     */
+    void pulsewidth_ms(int ms) {
+        pwmout_pulsewidth_ms(&_pwm, ms);
+    }
+
+    /** Set the PWM pulsewidth, specified in micro-seconds (int), keeping the period the same.
+     */
+    void pulsewidth_us(int us) {
+        pwmout_pulsewidth_us(&_pwm, us);
+    }
+
+#ifdef MBED_OPERATORS
+    /** A operator shorthand for write()
+     */
+    PwmOut& operator= (float value) {
+        write(value);
+        return *this;
+    }
+
+    PwmOut& operator= (PwmOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** An operator shorthand for read()
+     */
+    operator float() {
+        return read();
+    }
+#endif
+
+protected:
+    pwmout_t _pwm;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/RawSerial.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,91 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_RAW_SERIAL_H
+#define MBED_RAW_SERIAL_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "SerialBase.h"
+#include "serial_api.h"
+
+namespace mbed {
+
+/** A serial port (UART) for communication with other serial devices
+ * This is a variation of the Serial class that doesn't use streams,
+ * thus making it safe to use in interrupt handlers with the RTOS.
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * Example:
+ * @code
+ * // Send a char to the PC
+ *
+ * #include "mbed.h"
+ *
+ * RawSerial pc(USBTX, USBRX);
+ *
+ * int main() {
+ *     pc.putc('A');
+ * }
+ * @endcode
+ */
+class RawSerial: public SerialBase {
+
+public:
+    /** Create a RawSerial port, connected to the specified transmit and receive pins
+     *
+     *  @param tx Transmit pin
+     *  @param rx Receive pin
+     *
+     *  @note
+     *    Either tx or rx may be specified as NC if unused
+     */
+    RawSerial(PinName tx, PinName rx);
+
+    /** Write a char to the serial port
+     *
+     * @param c The char to write
+     *
+     * @returns The written char or -1 if an error occured
+     */
+    int putc(int c);
+
+    /** Read a char from the serial port
+     *
+     * @returns The char read from the serial port
+     */
+    int getc();
+
+    /** Write a string to the serial port
+     *
+     * @param str The string to write
+     *
+     * @returns 0 if the write succeeds, EOF for error
+     */
+    int puts(const char *str);
+
+    int printf(const char *format, ...);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/SPI.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,114 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPI_H
+#define MBED_SPI_H
+
+#include "platform.h"
+
+#if DEVICE_SPI
+
+#include "spi_api.h"
+
+namespace mbed {
+
+/** A SPI Master, used for communicating with SPI slave devices
+ *
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ *
+ * Most SPI devices will also require Chip Select and Reset signals. These
+ * can be controlled using <DigitalOut> pins
+ *
+ * Example:
+ * @code
+ * // Send a byte to a SPI slave, and record the response
+ *
+ * #include "mbed.h"
+ *
+ * SPI device(p5, p6, p7); // mosi, miso, sclk
+ *
+ * int main() {
+ *     int response = device.write(0xFF);
+ * }
+ * @endcode
+ */
+class SPI {
+
+public:
+
+    /** Create a SPI master connected to the specified pins
+     *
+     * Pin Options:
+     *  (5, 6, 7) or (11, 12, 13)
+     *
+     *  mosi or miso can be specfied as NC if not used
+     *
+     *  @param mosi SPI Master Out, Slave In pin
+     *  @param miso SPI Master In, Slave Out pin
+     *  @param sclk SPI Clock pin
+     */
+    SPI(PinName mosi, PinName miso, PinName sclk, PinName _unused=NC);
+
+    /** Configure the data transmission format
+     *
+     *  @param bits Number of bits per SPI frame (4 - 16)
+     *  @param mode Clock polarity and phase mode (0 - 3)
+     *
+     * @code
+     * mode | POL PHA
+     * -----+--------
+     *   0  |  0   0
+     *   1  |  0   1
+     *   2  |  1   0
+     *   3  |  1   1
+     * @endcode
+     */
+    void format(int bits, int mode = 0);
+
+    /** Set the spi bus clock frequency
+     *
+     *  @param hz SCLK frequency in hz (default = 1MHz)
+     */
+    void frequency(int hz = 1000000);
+
+    /** Write to the SPI Slave and return the response
+     *
+     *  @param value Data to be sent to the SPI slave
+     *
+     *  @returns
+     *    Response from the SPI slave
+    */
+    virtual int write(int value);
+
+public:
+    virtual ~SPI() {
+    }
+
+protected:
+    spi_t _spi;
+
+    void aquire(void);
+    static SPI *_owner;
+    int _bits;
+    int _mode;
+    int _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/SPISlave.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,127 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPISLAVE_H
+#define MBED_SPISLAVE_H
+
+#include "platform.h"
+
+#if DEVICE_SPISLAVE
+
+#include "spi_api.h"
+
+namespace mbed {
+
+/** A SPI slave, used for communicating with a SPI Master device
+ *
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ *
+ * Example:
+ * @code
+ * // Reply to a SPI master as slave
+ *
+ * #include "mbed.h"
+ *
+ * SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
+ *
+ * int main() {
+ *     device.reply(0x00);              // Prime SPI with first reply
+ *     while(1) {
+ *         if(device.receive()) {
+ *             int v = device.read();   // Read byte from master
+ *             v = (v + 1) % 0x100;     // Add one to it, modulo 256
+ *             device.reply(v);         // Make this the next reply
+ *         }
+ *     }
+ * }
+ * @endcode
+ */
+class SPISlave {
+
+public:
+
+    /** Create a SPI slave connected to the specified pins
+     *
+     * Pin Options:
+     *  (5, 6, 7i, 8) or (11, 12, 13, 14)
+     *
+     *  mosi or miso can be specfied as NC if not used
+     *
+     *  @param mosi SPI Master Out, Slave In pin
+     *  @param miso SPI Master In, Slave Out pin
+     *  @param sclk SPI Clock pin
+     *  @param ssel SPI chip select pin
+     *  @param name (optional) A string to identify the object
+     */
+    SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel);
+
+    /** Configure the data transmission format
+     *
+     *  @param bits Number of bits per SPI frame (4 - 16)
+     *  @param mode Clock polarity and phase mode (0 - 3)
+     *
+     * @code
+     * mode | POL PHA
+     * -----+--------
+     *   0  |  0   0
+     *   1  |  0   1
+     *   2  |  1   0
+     *   3  |  1   1
+     * @endcode
+     */
+    void format(int bits, int mode = 0);
+
+    /** Set the spi bus clock frequency
+     *
+     *  @param hz SCLK frequency in hz (default = 1MHz)
+     */
+    void frequency(int hz = 1000000);
+
+    /** Polls the SPI to see if data has been received
+     *
+     *  @returns
+     *    0 if no data,
+     *    1 otherwise
+     */
+    int receive(void);
+
+    /** Retrieve  data from receive buffer as slave
+     *
+     *  @returns
+     *    the data in the receive buffer
+     */
+    int read(void);
+
+    /** Fill the transmission buffer with the value to be written out
+     *  as slave on the next received message from the master.
+     *
+     *  @param value the data to be transmitted next
+     */
+    void reply(int value);
+
+protected:
+    spi_t _spi;
+
+    int _bits;
+    int _mode;
+    int _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/Serial.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,70 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_H
+#define MBED_SERIAL_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "Stream.h"
+#include "SerialBase.h"
+#include "serial_api.h"
+
+namespace mbed {
+
+/** A serial port (UART) for communication with other serial devices
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * Example:
+ * @code
+ * // Print "Hello World" to the PC
+ *
+ * #include "mbed.h"
+ *
+ * Serial pc(USBTX, USBRX);
+ *
+ * int main() {
+ *     pc.printf("Hello World\n");
+ * }
+ * @endcode
+ */
+class Serial : public SerialBase, public Stream {
+
+public:
+    /** Create a Serial port, connected to the specified transmit and receive pins
+     *
+     *  @param tx Transmit pin
+     *  @param rx Receive pin
+     *
+     *  @note
+     *    Either tx or rx may be specified as NC if unused
+     */
+    Serial(PinName tx, PinName rx, const char *name=NULL);
+
+protected:
+    virtual int _getc();
+    virtual int _putc(int c);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/SerialBase.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,140 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIALBASE_H
+#define MBED_SERIALBASE_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "Stream.h"
+#include "FunctionPointer.h"
+#include "serial_api.h"
+
+namespace mbed {
+
+/** A base class for serial port implementations
+ * Can't be instantiated directly (use Serial or RawSerial)
+ */
+class SerialBase {
+
+public:
+    /** Set the baud rate of the serial port
+     *
+     *  @param baudrate The baudrate of the serial port (default = 9600).
+     */
+    void baud(int baudrate);
+
+    enum Parity {
+        None = 0,
+        Odd,
+        Even,
+        Forced1,
+        Forced0
+    };
+
+    enum IrqType {
+        RxIrq = 0,
+        TxIrq
+    };
+
+    enum Flow {
+        Disabled = 0,
+        RTS,
+        CTS,
+        RTSCTS
+    };
+
+    /** Set the transmission format used by the serial port
+     *
+     *  @param bits The number of bits in a word (5-8; default = 8)
+     *  @param parity The parity used (SerialBase::None, SerialBase::Odd, SerialBase::Even, SerialBase::Forced1, SerialBase::Forced0; default = SerialBase::None)
+     *  @param stop The number of stop bits (1 or 2; default = 1)
+     */
+    void format(int bits=8, Parity parity=SerialBase::None, int stop_bits=1);
+
+    /** Determine if there is a character available to read
+     *
+     *  @returns
+     *    1 if there is a character available to read,
+     *    0 otherwise
+     */
+    int readable();
+
+    /** Determine if there is space available to write a character
+     *
+     *  @returns
+     *    1 if there is space to write a character,
+     *    0 otherwise
+     */
+    int writeable();
+
+    /** Attach a function to call whenever a serial interrupt is generated
+     *
+     *  @param fptr A pointer to a void function, or 0 to set as none
+     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+     */
+    void attach(void (*fptr)(void), IrqType type=RxIrq);
+
+    /** Attach a member function to call whenever a serial interrupt is generated
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+     */
+    template<typename T>
+    void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
+        if((mptr != NULL) && (tptr != NULL)) {
+            _irq[type].attach(tptr, mptr);
+            serial_irq_set(&_serial, (SerialIrq)type, 1);
+        }
+    }
+
+    /** Generate a break condition on the serial line
+     */
+    void send_break();
+
+#if DEVICE_SERIAL_FC
+    /** Set the flow control type on the serial port
+     *
+     *  @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
+     *  @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
+     *  @param flow2 the second flow control pin (CTS for RTSCTS)
+     */
+    void set_flow_control(Flow type, PinName flow1=NC, PinName flow2=NC);
+#endif
+
+    static void _irq_handler(uint32_t id, SerialIrq irq_type);
+
+protected:
+    SerialBase(PinName tx, PinName rx);
+    virtual ~SerialBase() {
+    }
+
+    int _base_getc();
+    int _base_putc(int c);
+
+    serial_t        _serial;
+    FunctionPointer _irq[2];
+    int             _baud;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/Stream.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,62 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_STREAM_H
+#define MBED_STREAM_H
+
+#include "platform.h"
+#include "FileLike.h"
+
+namespace mbed {
+
+class Stream : public FileLike {
+
+public:
+    Stream(const char *name=NULL);
+    virtual ~Stream();
+
+    int putc(int c);
+    int puts(const char *s);
+    int getc();
+    char *gets(char *s, int size);
+    int printf(const char* format, ...);
+    int scanf(const char* format, ...);
+
+    operator std::FILE*() {return _file;}
+
+protected:
+    virtual int close();
+    virtual ssize_t write(const void* buffer, size_t length);
+    virtual ssize_t read(void* buffer, size_t length);
+    virtual off_t lseek(off_t offset, int whence);
+    virtual int isatty();
+    virtual int fsync();
+    virtual off_t flen();
+
+    virtual int _putc(int c) = 0;
+    virtual int _getc() = 0;
+
+    std::FILE *_file;
+
+    /* disallow copy constructor and assignment operators */
+private:
+    Stream(const Stream&);
+    Stream & operator = (const Stream&);
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/Ticker.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,118 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TICKER_H
+#define MBED_TICKER_H
+
+#include "TimerEvent.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** A Ticker is used to call a function at a recurring interval
+ *
+ *  You can use as many seperate Ticker objects as you require.
+ *
+ * Example:
+ * @code
+ * // Toggle the blinking led after 5 seconds
+ *
+ * #include "mbed.h"
+ *
+ * Ticker timer;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * int flip = 0;
+ *
+ * void attime() {
+ *     flip = !flip;
+ * }
+ *
+ * int main() {
+ *     timer.attach(&attime, 5);
+ *     while(1) {
+ *         if(flip == 0) {
+ *             led1 = !led1;
+ *         } else {
+ *             led2 = !led2;
+ *         }
+ *         wait(0.2);
+ *     }
+ * }
+ * @endcode
+ */
+class Ticker : public TimerEvent {
+
+public:
+
+    /** Attach a function to be called by the Ticker, specifiying the interval in seconds
+     *
+     *  @param fptr pointer to the function to be called
+     *  @param t the time between calls in seconds
+     */
+    void attach(void (*fptr)(void), float t) {
+        attach_us(fptr, t * 1000000.0f);
+    }
+
+    /** Attach a member function to be called by the Ticker, specifiying the interval in seconds
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     *  @param t the time between calls in seconds
+     */
+    template<typename T>
+    void attach(T* tptr, void (T::*mptr)(void), float t) {
+        attach_us(tptr, mptr, t * 1000000.0f);
+    }
+
+    /** Attach a function to be called by the Ticker, specifiying the interval in micro-seconds
+     *
+     *  @param fptr pointer to the function to be called
+     *  @param t the time between calls in micro-seconds
+     */
+    void attach_us(void (*fptr)(void), unsigned int t) {
+        _function.attach(fptr);
+        setup(t);
+    }
+
+    /** Attach a member function to be called by the Ticker, specifiying the interval in micro-seconds
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     *  @param t the time between calls in micro-seconds
+     */
+    template<typename T>
+    void attach_us(T* tptr, void (T::*mptr)(void), unsigned int t) {
+        _function.attach(tptr, mptr);
+        setup(t);
+    }
+
+    /** Detach the function
+     */
+    void detach();
+
+protected:
+    void setup(unsigned int t);
+    virtual void handler();
+
+    unsigned int _delay;
+    FunctionPointer _function;
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/Timeout.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,60 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMEOUT_H
+#define MBED_TIMEOUT_H
+
+#include "Ticker.h"
+
+namespace mbed {
+
+/** A Timeout is used to call a function at a point in the future
+ *
+ * You can use as many seperate Timeout objects as you require.
+ *
+ * Example:
+ * @code
+ * // Blink until timeout.
+ *
+ * #include "mbed.h"
+ *
+ * Timeout timeout;
+ * DigitalOut led(LED1);
+ *
+ * int on = 1;
+ *
+ * void attimeout() {
+ *     on = 0;
+ * }
+ *
+ * int main() {
+ *     timeout.attach(&attimeout, 5);
+ *     while(on) {
+ *         led = !led;
+ *         wait(0.2);
+ *     }
+ * }
+ * @endcode
+ */
+class Timeout : public Ticker {
+
+protected:
+    virtual void handler();
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/Timer.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,89 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMER_H
+#define MBED_TIMER_H
+
+#include "platform.h"
+
+namespace mbed {
+
+/** A general purpose timer
+ *
+ * Example:
+ * @code
+ * // Count the time to toggle a LED
+ *
+ * #include "mbed.h"
+ *
+ * Timer timer;
+ * DigitalOut led(LED1);
+ * int begin, end;
+ *
+ * int main() {
+ *     timer.start();
+ *     begin = timer.read_us();
+ *     led = !led;
+ *     end = timer.read_us();
+ *     printf("Toggle the led takes %d us", end - begin);
+ * }
+ * @endcode
+ */
+class Timer {
+
+public:
+    Timer();
+
+    /** Start the timer
+     */
+    void start();
+
+    /** Stop the timer
+     */
+    void stop();
+
+    /** Reset the timer to 0.
+     *
+     * If it was already counting, it will continue
+     */
+    void reset();
+
+    /** Get the time passed in seconds
+     */
+    float read();
+
+    /** Get the time passed in mili-seconds
+     */
+    int read_ms();
+
+    /** Get the time passed in micro-seconds
+     */
+    int read_us();
+
+#ifdef MBED_OPERATORS
+    operator float();
+#endif
+
+protected:
+    int slicetime();
+    int _running;          // whether the timer is running
+    unsigned int _start;   // the start time of the latest slice
+    int _time;             // any accumulated time from previous slices
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/TimerEvent.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,53 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMEREVENT_H
+#define MBED_TIMEREVENT_H
+
+#include "us_ticker_api.h"
+
+namespace mbed {
+
+/** Base abstraction for timer interrupts
+*/
+class TimerEvent {
+public:
+    TimerEvent();
+
+    /** The handler registered with the underlying timer interrupt
+     */
+    static void irq(uint32_t id);
+
+    /** Destruction removes it...
+     */
+    virtual ~TimerEvent();
+
+protected:
+    // The handler called to service the timer event of the derived class
+    virtual void handler() = 0;
+
+    // insert in to linked list
+    void insert(unsigned int timestamp);
+
+    // remove from linked list, if in it
+    void remove();
+
+    ticker_event_t event;
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/can_helper.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_HELPER_H
+#define MBED_CAN_HELPER_H
+
+#if DEVICE_CAN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum CANFormat {
+    CANStandard = 0,
+    CANExtended = 1,
+    CANAny = 2
+};
+typedef enum CANFormat CANFormat;
+
+enum CANType {
+    CANData   = 0,
+    CANRemote = 1
+};
+typedef enum CANType CANType;
+
+struct CAN_Message {
+    unsigned int   id;                 // 29 bit identifier
+    unsigned char  data[8];            // Data field
+    unsigned char  len;                // Length of data field in bytes
+    CANFormat      format;             // 0 - STANDARD, 1- EXTENDED IDENTIFIER
+    CANType        type;               // 0 - DATA FRAME, 1 - REMOTE FRAME
+};
+typedef struct CAN_Message CAN_Message;
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif
+
+#endif // MBED_CAN_HELPER_H
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/mbed.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_H
+#define MBED_H
+
+#define MBED_LIBRARY_VERSION 88
+
+#include "platform.h"
+
+// Useful C libraries
+#include <math.h>
+#include <time.h>
+
+// mbed Debug libraries
+#include "mbed_error.h"
+#include "mbed_interface.h"
+
+// mbed Peripheral components
+#include "DigitalIn.h"
+#include "DigitalOut.h"
+#include "DigitalInOut.h"
+#include "BusIn.h"
+#include "BusOut.h"
+#include "BusInOut.h"
+#include "PortIn.h"
+#include "PortInOut.h"
+#include "PortOut.h"
+#include "AnalogIn.h"
+#include "AnalogOut.h"
+#include "PwmOut.h"
+#include "Serial.h"
+#include "SPI.h"
+#include "SPISlave.h"
+#include "I2C.h"
+#include "I2CSlave.h"
+#include "Ethernet.h"
+#include "CAN.h"
+#include "RawSerial.h"
+
+// mbed Internal components
+#include "Timer.h"
+#include "Ticker.h"
+#include "Timeout.h"
+#include "LocalFileSystem.h"
+#include "InterruptIn.h"
+#include "wait_api.h"
+#include "sleep_api.h"
+#include "rtc_time.h"
+
+using namespace mbed;
+using namespace std;
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/mbed_assert.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ASSERT_H
+#define MBED_ASSERT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Internal mbed assert function which is invoked when MBED_ASSERT macro failes.
+ *  This function is active only if NDEBUG is not defined prior to including this
+ *  assert header file.
+ *  In case of MBED_ASSERT failing condition, the assertation message is printed
+ *  to stderr and mbed_die() is called.
+ *  @param expr Expresion to be checked.
+ *  @param file File where assertation failed.
+ *  @param line Failing assertation line number.
+ */
+void mbed_assert_internal(const char *expr, const char *file, int line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#ifdef NDEBUG
+#define MBED_ASSERT(expr) ((void)0)
+
+#else
+#define MBED_ASSERT(expr)                                \
+do {                                                     \
+    if (!(expr)) {                                       \
+        mbed_assert_internal(#expr, __FILE__, __LINE__); \
+    }                                                    \
+} while (0)
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/mbed_debug.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEBUG_H
+#define MBED_DEBUG_H
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#include <stdarg.h>
+
+/** Output a debug message
+ *
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug(const char *format, ...) {
+    va_list args;
+    va_start(args, format);
+    vfprintf(stderr, format, args);
+    va_end(args);
+}
+
+/** Conditionally output a debug message
+ *
+ * NOTE: If the condition is constant false (!= 1) and the compiler optimization
+ * level is greater than 0, then the whole function will be compiled away.
+ *
+ * @param condition output only if condition is true (== 1)
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug_if(int condition, const char *format, ...) {
+    if (condition == 1) {
+        va_list args;
+        va_start(args, format);
+        vfprintf(stderr, format, args);
+        va_end(args);
+    }
+}
+
+#else
+static inline void debug(const char *format, ...) {}
+static inline void debug_if(int condition, const char *format, ...) {}
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/mbed_error.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ERROR_H
+#define MBED_ERROR_H
+
+/** To generate a fatal compile-time error, you can use the pre-processor #error directive.
+ *
+ * @code
+ * #error "That shouldn't have happened!"
+ * @endcode
+ *
+ * If the compiler evaluates this line, it will report the error and stop the compile.
+ *
+ * For example, you could use this to check some user-defined compile-time variables:
+ *
+ * @code
+ * #define NUM_PORTS 7
+ * #if (NUM_PORTS > 4)
+ *     #error "NUM_PORTS must be less than 4"
+ * #endif
+ * @endcode
+ *
+ * Reporting Run-Time Errors:
+ * To generate a fatal run-time error, you can use the mbed error() function.
+ *
+ * @code
+ * error("That shouldn't have happened!");
+ * @endcode
+ *
+ * If the mbed running the program executes this function, it will print the
+ * message via the USB serial port, and then die with the blue lights of death!
+ *
+ * The message can use printf-style formatting, so you can report variables in the
+ * message too. For example, you could use this to check a run-time condition:
+ *
+ * @code
+ * if(x >= 5) {
+ *     error("expected x to be less than 5, but got %d", x);
+ * }
+ * #endcode
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void error(const char* format, ...);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/mbed_interface.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,115 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERFACE_H
+#define MBED_INTERFACE_H
+
+#include "device.h"
+
+/* Mbed interface mac address
+ * if MBED_MAC_ADD_x are zero, interface uid sets mac address,
+ * otherwise MAC_ADD_x are used.
+ */
+#define MBED_MAC_ADDR_INTERFACE 0x00
+#define MBED_MAC_ADDR_0  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_1  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_2  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_3  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_4  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_5  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDRESS_SUM (MBED_MAC_ADDR_0 | MBED_MAC_ADDR_1 | MBED_MAC_ADDR_2 | MBED_MAC_ADDR_3 | MBED_MAC_ADDR_4 | MBED_MAC_ADDR_5)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_SEMIHOST
+
+/** Functions to control the mbed interface
+ *
+ * mbed Microcontrollers have a built-in interface to provide functionality such as
+ * drag-n-drop download, reset, serial-over-usb, and access to the mbed local file
+ * system. These functions provide means to control the interface suing semihost
+ * calls it supports.
+ */
+
+/** Determine whether the mbed interface is connected, based on whether debug is enabled
+ *
+ *  @returns
+ *    1 if interface is connected,
+ *    0 otherwise
+ */
+int mbed_interface_connected(void);
+
+/** Instruct the mbed interface to reset, as if the reset button had been pressed
+ *
+ *  @returns
+ *    1 if successful,
+ *    0 otherwise (e.g. interface not present)
+ */
+int mbed_interface_reset(void);
+
+/** This will disconnect the debug aspect of the interface, so semihosting will be disabled.
+ * The interface will still support the USB serial aspect
+ *
+ *  @returns
+ *    0 if successful,
+ *   -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_disconnect(void);
+
+/** This will disconnect the debug aspect of the interface, and if the USB cable is not
+ * connected, also power down the interface. If the USB cable is connected, the interface
+ * will remain powered up and visible to the host
+ *
+ *  @returns
+ *    0 if successful,
+ *   -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_powerdown(void);
+
+/** This returns a string containing the 32-character UID of the mbed interface
+ *  This is a weak function that can be overwritten if required
+ *
+ *  @param uid A 33-byte array to write the null terminated 32-byte string
+ *
+ *  @returns
+ *    0 if successful,
+ *   -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_uid(char *uid);
+
+#endif
+
+/** This returns a unique 6-byte MAC address, based on the interface UID
+ * If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00)
+ *
+ * This is a weak function that can be overwritten if you want to provide your own mechanism to
+ * provide a MAC address.
+ *
+ *  @param mac A 6-byte array to write the MAC address
+ */
+void mbed_mac_address(char *mac);
+
+/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence
+ */
+void mbed_die(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/platform.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PLATFORM_H
+#define MBED_PLATFORM_H
+
+#define MBED_OPERATORS    1
+
+#include "device.h"
+#include "PinNames.h"
+#include "PeripheralNames.h"
+
+#include <cstddef>
+#include <cstdlib>
+#include <cstdio>
+#include <cstring>
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/rtc_time.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,75 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Implementation of the C time.h functions
+ *
+ * Provides mechanisms to set and read the current time, based
+ * on the microcontroller Real-Time Clock (RTC), plus some
+ * standard C manipulation and formating functions.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * int main() {
+ *     set_time(1256729737);  // Set RTC time to Wed, 28 Oct 2009 11:35:37
+ *
+ *     while(1) {
+ *         time_t seconds = time(NULL);
+ *
+ *         printf("Time as seconds since January 1, 1970 = %d\n", seconds);
+ *
+ *         printf("Time as a basic string = %s", ctime(&seconds));
+ *
+ *         char buffer[32];
+ *         strftime(buffer, 32, "%I:%M %p\n", localtime(&seconds));
+ *         printf("Time as a custom formatted string = %s", buffer);
+ *
+ *         wait(1);
+ *     }
+ * }
+ * @endcode
+ */
+
+/** Set the current time
+ *
+ * Initialises and sets the time of the microcontroller Real-Time Clock (RTC)
+ * to the time represented by the number of seconds since January 1, 1970
+ * (the UNIX timestamp).
+ *
+ * @param t Number of seconds since January 1, 1970 (the UNIX timestamp)
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * int main() {
+ *     set_time(1256729737); // Set time to Wed, 28 Oct 2009 11:35:37
+ * }
+ * @endcode
+ */
+void set_time(time_t t);
+
+#ifdef __cplusplus
+}
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/semihost_api.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SEMIHOST_H
+#define MBED_SEMIHOST_H
+
+#include "device.h"
+#include "toolchain.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_SEMIHOST
+
+#ifndef __CC_ARM
+
+#if defined(__ICCARM__)
+inline int __semihost(int reason, const void *arg) {
+    return __semihosting(reason, (void*)arg);
+}
+#else
+
+#ifdef __thumb__
+#   define AngelSWI            0xAB
+#   define AngelSWIInsn        "bkpt"
+#   define AngelSWIAsm          bkpt
+#else
+#   define AngelSWI            0x123456
+#   define AngelSWIInsn        "swi"
+#   define AngelSWIAsm          swi
+#endif
+
+static inline int __semihost(int reason, const void *arg) {
+    int value;
+
+    asm volatile (
+       "mov r0, %1"          "\n\t"
+       "mov r1, %2"          "\n\t"
+       AngelSWIInsn " %a3"   "\n\t"
+       "mov %0, r0"
+       : "=r" (value)                                         /* output operands             */
+       : "r" (reason), "r" (arg), "i" (AngelSWI)              /* input operands              */
+       : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"   /* list of clobbered registers */
+    );
+
+    return value;
+}
+#endif
+#endif
+
+#if DEVICE_LOCALFILESYSTEM
+FILEHANDLE semihost_open(const char* name, int openmode);
+int semihost_close (FILEHANDLE fh);
+int semihost_read  (FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode);
+int semihost_write (FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode);
+int semihost_ensure(FILEHANDLE fh);
+long semihost_flen (FILEHANDLE fh);
+int semihost_seek  (FILEHANDLE fh, long position);
+int semihost_istty (FILEHANDLE fh);
+
+int semihost_remove(const char *name);
+int semihost_rename(const char *old_name, const char *new_name);
+#endif
+
+int semihost_uid(char *uid);
+int semihost_reset(void);
+int semihost_vbus(void);
+int semihost_powerdown(void);
+int semihost_exit(void);
+
+int semihost_connected(void);
+int semihost_disabledebug(void);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/toolchain.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,36 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TOOLCHAIN_H
+#define MBED_TOOLCHAIN_H
+
+#if defined(TOOLCHAIN_ARM)
+#include <rt_sys.h>
+#endif
+
+#ifndef FILEHANDLE
+typedef int FILEHANDLE;
+#endif
+
+#if defined (__ICCARM__)
+#   define WEAK     __weak
+#   define PACKED   __packed
+#else
+#   define WEAK     __attribute__((weak))
+#   define PACKED   __attribute__((packed))
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/api/wait_api.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_WAIT_API_H
+#define MBED_WAIT_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Generic wait functions.
+ *
+ * These provide simple NOP type wait capabilities.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * DigitalOut heartbeat(LED1);
+ *
+ * int main() {
+ *     while (1) {
+ *         heartbeat = 1;
+ *         wait(0.5);
+ *         heartbeat = 0;
+ *         wait(0.5);
+ *     }
+ * }
+ */
+
+/** Waits for a number of seconds, with microsecond resolution (within
+ *  the accuracy of single precision floating point).
+ *
+ *  @param s number of seconds to wait
+ */
+void wait(float s);
+
+/** Waits a number of milliseconds.
+ *
+ *  @param ms the whole number of milliseconds to wait
+ */
+void wait_ms(int ms);
+
+/** Waits a number of microseconds.
+ *
+ *  @param us the whole number of microseconds to wait
+ */
+void wait_us(int us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/BusIn.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BusIn.h"
+
+namespace mbed {
+
+BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+    }
+}
+
+BusIn::BusIn(PinName pins[16]) {
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+    }
+}
+
+BusIn::~BusIn() {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            delete _pin[i];
+        }
+    }
+}
+
+int BusIn::read() {
+    int v = 0;
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            v |= _pin[i]->read() << i;
+        }
+    }
+    return v;
+}
+
+void BusIn::mode(PinMode pull) {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->mode(pull);
+        }
+    }
+}
+
+#ifdef MBED_OPERATORS
+BusIn::operator int() {
+    return read();
+}
+#endif
+
+} // namespace mbed
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/BusInOut.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,101 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BusInOut.h"
+
+namespace mbed {
+
+BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+    }
+}
+
+BusInOut::BusInOut(PinName pins[16]) {
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+    }
+}
+
+BusInOut::~BusInOut() {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            delete _pin[i];
+        }
+    }
+}
+
+void BusInOut::write(int value) {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->write((value >> i) & 1);
+        }
+    }
+}
+
+int BusInOut::read() {
+    int v = 0;
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            v |= _pin[i]->read() << i;
+        }
+    }
+    return v;
+}
+
+void BusInOut::output() {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->output();
+        }
+    }
+}
+
+void BusInOut::input() {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->input();
+        }
+    }
+}
+
+void BusInOut::mode(PinMode pull) {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->mode(pull);
+        }
+    }
+}
+
+#ifdef MBED_OPERATORS
+BusInOut& BusInOut::operator= (int v) {
+    write(v);
+    return *this;
+}
+
+BusInOut& BusInOut::operator= (BusInOut& rhs) {
+    write(rhs.read());
+    return *this;
+}
+
+BusInOut::operator int() {
+    return read();
+}
+#endif
+
+} // namespace mbed
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/BusOut.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BusOut.h"
+
+namespace mbed {
+
+BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+    }
+}
+
+BusOut::BusOut(PinName pins[16]) {
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+    }
+}
+
+BusOut::~BusOut() {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            delete _pin[i];
+        }
+    }
+}
+
+void BusOut::write(int value) {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->write((value >> i) & 1);
+        }
+    }
+}
+
+int BusOut::read() {
+    int v = 0;
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            v |= _pin[i]->read() << i;
+        }
+    }
+    return v;
+}
+
+#ifdef MBED_OPERATORS
+BusOut& BusOut::operator= (int v) {
+    write(v);
+    return *this;
+}
+
+BusOut& BusOut::operator= (BusOut& rhs) {
+    write(rhs.read());
+    return *this;
+}
+
+BusOut::operator int() {
+    return read();
+}
+#endif
+
+} // namespace mbed
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/CAN.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,87 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "CAN.h"
+
+#if DEVICE_CAN
+
+#include "cmsis.h"
+
+namespace mbed {
+
+CAN::CAN(PinName rd, PinName td) : _can(), _irq() {
+    can_init(&_can, rd, td);
+    can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this);
+}
+
+CAN::~CAN() {
+    can_irq_free(&_can);
+    can_free(&_can);
+}
+
+int CAN::frequency(int f) {
+    return can_frequency(&_can, f);
+}
+
+int CAN::write(CANMessage msg) {
+    return can_write(&_can, msg, 0);
+}
+
+int CAN::read(CANMessage &msg, int handle) {
+    return can_read(&_can, &msg, handle);
+}
+
+void CAN::reset() {
+    can_reset(&_can);
+}
+
+unsigned char CAN::rderror() {
+    return can_rderror(&_can);
+}
+
+unsigned char CAN::tderror() {
+    return can_tderror(&_can);
+}
+
+void CAN::monitor(bool silent) {
+    can_monitor(&_can, (silent) ? 1 : 0);
+}
+
+int CAN::mode(Mode mode) {
+    return can_mode(&_can, (CanMode)mode);
+}
+
+int CAN::filter(unsigned int id, unsigned int mask, CANFormat format, int handle) {
+    return can_filter(&_can, id, mask, format, handle);
+}
+
+void CAN::attach(void (*fptr)(void), IrqType type) {
+    if (fptr) {
+        _irq[(CanIrqType)type].attach(fptr);
+        can_irq_set(&_can, (CanIrqType)type, 1);
+    } else {
+        can_irq_set(&_can, (CanIrqType)type, 0);
+    }
+}
+
+void CAN::_irq_handler(uint32_t id, CanIrqType type) {
+    CAN *handler = (CAN*)id;
+    handler->_irq[type].call();
+}
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/CallChain.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,91 @@
+#include "CallChain.h"
+#include "cmsis.h"
+
+namespace mbed {
+
+CallChain::CallChain(int size) : _chain(), _size(size), _elements(0) {
+    _chain = new pFunctionPointer_t[size]();
+}
+
+CallChain::~CallChain() {
+    clear();
+    delete _chain;
+}
+
+pFunctionPointer_t CallChain::add(void (*function)(void)) {
+    return common_add(new FunctionPointer(function));
+}
+
+pFunctionPointer_t CallChain::add_front(void (*function)(void)) {
+    return common_add_front(new FunctionPointer(function));
+}
+
+int CallChain::size() const {
+    return _elements;
+}
+
+pFunctionPointer_t CallChain::get(int i) const {
+    if (i < 0 || i >= _elements)
+        return NULL;
+    return _chain[i];
+}
+
+int CallChain::find(pFunctionPointer_t f) const {
+    for (int i = 0; i < _elements; i++)
+        if (f == _chain[i])
+            return i;
+    return -1;
+}
+
+void CallChain::clear() {
+    for(int i = 0; i < _elements; i ++) {
+        delete _chain[i];
+        _chain[i] = NULL;
+    }
+    _elements = 0;
+}
+
+bool CallChain::remove(pFunctionPointer_t f) {
+    int i;
+
+    if ((i = find(f)) == -1)
+        return false;
+    if (i != _elements - 1)
+        memmove(_chain + i, _chain + i + 1, (_elements - i - 1) * sizeof(pFunctionPointer_t));
+    delete f;
+    _elements --;
+    return true;
+}
+
+void CallChain::call() {
+    for(int i = 0; i < _elements; i++)
+        _chain[i]->call();
+}
+
+void CallChain::_check_size() {
+    if (_elements < _size)
+        return;
+    _size = (_size < 4) ? 4 : _size + 4;
+    pFunctionPointer_t* new_chain = new pFunctionPointer_t[_size]();
+    memcpy(new_chain, _chain, _elements * sizeof(pFunctionPointer_t));
+    delete _chain;
+    _chain = new_chain;
+}
+
+pFunctionPointer_t CallChain::common_add(pFunctionPointer_t pf) {
+    _check_size();
+    _chain[_elements] = pf;
+    _elements ++;
+    return pf;
+}
+
+pFunctionPointer_t CallChain::common_add_front(pFunctionPointer_t pf) {
+    _check_size();
+    memmove(_chain + 1, _chain, _elements * sizeof(pFunctionPointer_t));
+    _chain[0] = pf;
+    _elements ++;
+    return pf;
+}
+
+} // namespace mbed
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/Ethernet.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,74 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Ethernet.h"
+
+#if DEVICE_ETHERNET
+
+#include "ethernet_api.h"
+
+namespace mbed {
+
+Ethernet::Ethernet() {
+    ethernet_init();
+}
+
+Ethernet::~Ethernet() {
+    ethernet_free();
+}
+
+int Ethernet::write(const char *data, int size) {
+    return ethernet_write(data, size);
+}
+
+int Ethernet::send() {
+    return ethernet_send();
+}
+
+int Ethernet::receive() {
+    return ethernet_receive();
+}
+
+int Ethernet::read(char *data, int size) {
+    return ethernet_read(data, size);
+}
+
+void Ethernet::address(char *mac) {
+    return ethernet_address(mac);
+}
+
+int Ethernet::link() {
+    return ethernet_link();
+}
+
+void Ethernet::set_link(Mode mode) {
+    int speed = -1;
+    int duplex = 0;
+
+    switch(mode) {
+        case AutoNegotiate : speed = -1; duplex = 0; break;
+        case HalfDuplex10  : speed = 0;  duplex = 0; break;
+        case FullDuplex10  : speed = 0;  duplex = 1; break;
+        case HalfDuplex100 : speed = 1;  duplex = 0; break;
+        case FullDuplex100 : speed = 1;  duplex = 1; break;
+    }
+
+    ethernet_set_link(speed, duplex);
+}
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/FileBase.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,83 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileBase.h"
+
+namespace mbed {
+
+FileBase *FileBase::_head = NULL;
+
+FileBase::FileBase(const char *name, PathType t) : _next(NULL),
+                                                   _name(name),
+                                                   _path_type(t) {
+    if (name != NULL) {
+        // put this object at head of the list
+        _next = _head;
+        _head = this;
+    } else {
+        _next = NULL;
+    }
+}
+
+FileBase::~FileBase() {
+    if (_name != NULL) {
+        // remove this object from the list
+        if (_head == this) { // first in the list, so just drop me
+            _head = _next;
+        } else {             // find the object before me, then drop me
+            FileBase *p = _head;
+            while (p->_next != this) {
+                p = p->_next;
+            }
+            p->_next = _next;
+        }
+    }
+}
+
+FileBase *FileBase::lookup(const char *name, unsigned int len) {
+    FileBase *p = _head;
+    while (p != NULL) {
+        /* Check that p->_name matches name and is the correct length */
+        if (p->_name != NULL && std::strncmp(p->_name, name, len) == 0 && std::strlen(p->_name) == len) {
+            return p;
+        }
+        p = p->_next;
+    }
+    return NULL;
+}
+
+FileBase *FileBase::get(int n) {
+    FileBase *p = _head;
+    int m = 0;
+    while (p != NULL) {
+        if (m == n) return p;
+
+        m++;
+        p = p->_next;
+    }
+    return NULL;
+}
+
+const char* FileBase::getName(void) {
+    return _name;
+}
+
+PathType FileBase::getPathType(void) {
+    return _path_type;
+}
+
+} // namespace mbed
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/FileLike.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,29 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileLike.h"
+
+namespace mbed {
+
+FileLike::FileLike(const char *name) : FileHandle(), FileBase(name, FilePathType) {
+
+}
+
+FileLike::~FileLike() {
+
+}
+
+} // namespace mbed
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/FilePath.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FilePath.h"
+
+namespace mbed {
+
+FilePath::FilePath(const char* file_path) : file_name(NULL), fb(NULL) {
+    if ((file_path[0] != '/') || (file_path[1] == 0)) return;
+
+    const char* file_system = &file_path[1];
+    file_name = file_system;
+    int len = 0;
+    while (true) {
+        char c = *file_name;
+        if (c == '/') { // end of object name
+            file_name++; // point to one char after the '/'
+            break;
+        }
+        if (c == 0) { // end of object name, with no filename
+            break;
+        }
+        len++;
+        file_name++;
+    }
+
+    fb = FileBase::lookup(file_system, len);
+}
+
+const char* FilePath::fileName(void) {
+    return file_name;
+}
+
+bool FilePath::isFileSystem(void) {
+    if (NULL == fb)
+        return false;
+    return (fb->getPathType() == FileSystemPathType);
+}
+
+FileSystemLike* FilePath::fileSystem(void) {
+    if (isFileSystem()) {
+        return (FileSystemLike*)fb;
+    }
+    return NULL;
+}
+
+bool FilePath::isFile(void) {
+    if (NULL == fb)
+        return false;
+    return (fb->getPathType() == FilePathType);
+}
+
+FileLike* FilePath::file(void) {
+    if (isFile()) {
+        return (FileLike*)fb;
+    }
+    return NULL;
+}
+
+bool FilePath::exists(void) {
+    return fb != NULL;
+}
+
+} // namespace mbed
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/FileSystemLike.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,78 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileSystemLike.h"
+
+namespace mbed {
+
+class BaseDirHandle : public DirHandle {
+public:
+    /*
+      We keep track of our current location as the n'th object in the
+      FileSystemLike list. Using a Base* instead would cause problems if that
+      object were to be destroyed between readdirs.
+      Using this method does mean though that destroying/creating objects can
+      give unusual results from readdir.
+    */
+    off_t n;
+    struct dirent cur_entry;
+
+    BaseDirHandle() : n(0), cur_entry() {
+    }
+
+    virtual int closedir() {
+        delete this;
+        return 0;
+    }
+
+    virtual struct dirent *readdir() {
+        FileBase *ptr = FileBase::get(n);
+        if (ptr == NULL) return NULL;
+
+        /* Increment n, so next readdir gets the next item */
+        n++;
+
+        /* Setup cur entry and return a pointer to it */
+        std::strncpy(cur_entry.d_name, ptr->getName(), NAME_MAX);
+        return &cur_entry;
+    }
+
+    virtual off_t telldir() {
+        return n;
+    }
+
+    virtual void seekdir(off_t offset) {
+        n = offset;
+    }
+
+    virtual void rewinddir() {
+        n = 0;
+    }
+};
+
+FileSystemLike::FileSystemLike(const char *name) : FileBase(name, FileSystemPathType) {
+
+}
+
+FileSystemLike::~FileSystemLike() {
+
+}
+
+DirHandle *FileSystemLike::opendir() {
+    return new BaseDirHandle();
+}
+
+} // namespace mbed
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/FunctionPointer.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+FunctionPointer::FunctionPointer(void (*function)(void)): _function(),
+                                                          _object(),
+                                                          _membercaller() {
+    attach(function);
+}
+
+void FunctionPointer::attach(void (*function)(void)) {
+    _function = function;
+    _object = 0;
+}
+
+void FunctionPointer::call(void) {
+    if (_function) {
+        _function();
+    } else if (_object) {
+        _membercaller(_object, _member);
+    }
+}
+
+#ifdef MBED_OPERATORS
+void FunctionPointer::operator ()(void) {
+    call();
+}
+#endif
+
+} // namespace mbed
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/I2C.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,92 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "I2C.h"
+
+#if DEVICE_I2C
+
+namespace mbed {
+
+I2C *I2C::_owner = NULL;
+
+I2C::I2C(PinName sda, PinName scl) : _i2c(), _hz(100000) {
+    // The init function also set the frequency to 100000
+    i2c_init(&_i2c, sda, scl);
+
+    // Used to avoid unnecessary frequency updates
+    _owner = this;
+}
+
+void I2C::frequency(int hz) {
+    _hz = hz;
+
+    // We want to update the frequency even if we are already the bus owners
+    i2c_frequency(&_i2c, _hz);
+
+    // Updating the frequency of the bus we become the owners of it
+    _owner = this;
+}
+
+void I2C::aquire() {
+    if (_owner != this) {
+        i2c_frequency(&_i2c, _hz);
+        _owner = this;
+    }
+}
+
+// write - Master Transmitter Mode
+int I2C::write(int address, const char* data, int length, bool repeated) {
+    aquire();
+
+    int stop = (repeated) ? 0 : 1;
+    int written = i2c_write(&_i2c, address, data, length, stop);
+
+    return length != written;
+}
+
+int I2C::write(int data) {
+    return i2c_byte_write(&_i2c, data);
+}
+
+// read - Master Reciever Mode
+int I2C::read(int address, char* data, int length, bool repeated) {
+    aquire();
+
+    int stop = (repeated) ? 0 : 1;
+    int read = i2c_read(&_i2c, address, data, length, stop);
+
+    return length != read;
+}
+
+int I2C::read(int ack) {
+    if (ack) {
+        return i2c_byte_read(&_i2c, 0);
+    } else {
+        return i2c_byte_read(&_i2c, 1);
+    }
+}
+
+void I2C::start(void) {
+    i2c_start(&_i2c);
+}
+
+void I2C::stop(void) {
+    i2c_stop(&_i2c);
+}
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/I2CSlave.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "I2CSlave.h"
+
+#if DEVICE_I2CSLAVE
+
+namespace mbed {
+
+I2CSlave::I2CSlave(PinName sda, PinName scl) : _i2c() {
+    i2c_init(&_i2c, sda, scl);
+    i2c_frequency(&_i2c, 100000);
+    i2c_slave_mode(&_i2c, 1);
+}
+
+void I2CSlave::frequency(int hz) {
+    i2c_frequency(&_i2c, hz);
+}
+
+void I2CSlave::address(int address) {
+    int addr = (address & 0xFF) | 1;
+    i2c_slave_address(&_i2c, 0, addr, 0);
+}
+
+int I2CSlave::receive(void) {
+    return i2c_slave_receive(&_i2c);
+}
+
+int I2CSlave::read(char *data, int length) {
+    return i2c_slave_read(&_i2c, data, length) != length;
+}
+
+int I2CSlave::read(void) {
+    return i2c_byte_read(&_i2c, 0);
+}
+
+int I2CSlave::write(const char *data, int length) {
+    return i2c_slave_write(&_i2c, data, length) != length;
+}
+
+int I2CSlave::write(int data) {
+    return i2c_byte_write(&_i2c, data);
+}
+
+void I2CSlave::stop(void) {
+    i2c_stop(&_i2c);
+}
+
+}
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/InterruptIn.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,86 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "InterruptIn.h"
+
+#if DEVICE_INTERRUPTIN
+
+namespace mbed {
+
+InterruptIn::InterruptIn(PinName pin) : gpio(),
+                                        gpio_irq(),
+                                        _rise(),
+                                        _fall() {
+    gpio_irq_init(&gpio_irq, pin, (&InterruptIn::_irq_handler), (uint32_t)this);
+    gpio_init_in(&gpio, pin);
+}
+
+InterruptIn::~InterruptIn() {
+    gpio_irq_free(&gpio_irq);
+}
+
+int InterruptIn::read() {
+    return gpio_read(&gpio);
+}
+
+void InterruptIn::mode(PinMode pull) {
+    gpio_mode(&gpio, pull);
+}
+
+void InterruptIn::rise(void (*fptr)(void)) {
+    if (fptr) {
+        _rise.attach(fptr);
+        gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
+    } else {
+        gpio_irq_set(&gpio_irq, IRQ_RISE, 0);
+    }
+}
+
+void InterruptIn::fall(void (*fptr)(void)) {
+    if (fptr) {
+        _fall.attach(fptr);
+        gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
+    } else {
+        gpio_irq_set(&gpio_irq, IRQ_FALL, 0);
+    }
+}
+
+void InterruptIn::_irq_handler(uint32_t id, gpio_irq_event event) {
+    InterruptIn *handler = (InterruptIn*)id;
+    switch (event) {
+        case IRQ_RISE: handler->_rise.call(); break;
+        case IRQ_FALL: handler->_fall.call(); break;
+        case IRQ_NONE: break;
+    }
+}
+
+void InterruptIn::enable_irq() {
+    gpio_irq_enable(&gpio_irq);
+}
+
+void InterruptIn::disable_irq() {
+    gpio_irq_disable(&gpio_irq);
+}
+
+#ifdef MBED_OPERATORS
+InterruptIn::operator int() {
+    return read();
+}
+#endif
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/InterruptManager.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,90 @@
+#include "InterruptManager.h"
+#include <string.h>
+
+#define CHAIN_INITIAL_SIZE    4
+
+namespace mbed {
+
+typedef void (*pvoidf)(void);
+
+InterruptManager* InterruptManager::_instance = (InterruptManager*)NULL;
+
+InterruptManager* InterruptManager::get() {
+    if (NULL == _instance)
+        _instance = new InterruptManager();
+    return _instance;
+}
+
+InterruptManager::InterruptManager() {
+    memset(_chains, 0, NVIC_NUM_VECTORS * sizeof(CallChain*));
+}
+
+void InterruptManager::destroy() {
+    // Not a good idea to call this unless NO interrupt at all
+    // is under the control of the handler; otherwise, a system crash
+    // is very likely to occur
+    if (NULL != _instance) {
+        delete _instance;
+        _instance = (InterruptManager*)NULL;
+    }
+}
+
+InterruptManager::~InterruptManager() {
+    for(int i = 0; i < NVIC_NUM_VECTORS; i++)
+        if (NULL != _chains[i])
+            delete _chains[i];
+}
+
+bool InterruptManager::must_replace_vector(IRQn_Type irq) {
+    int irq_pos = get_irq_index(irq);
+
+    if (NULL == _chains[irq_pos]) {
+        _chains[irq_pos] = new CallChain(CHAIN_INITIAL_SIZE);
+        _chains[irq_pos]->add((pvoidf)NVIC_GetVector(irq));
+        return true;
+    }
+    return false;
+}
+
+pFunctionPointer_t InterruptManager::add_common(void (*function)(void), IRQn_Type irq, bool front) {
+    int irq_pos = get_irq_index(irq);
+    bool change = must_replace_vector(irq);
+
+    pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(function) : _chains[irq_pos]->add(function);
+    if (change)
+        NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+    return pf;
+}
+
+bool InterruptManager::remove_handler(pFunctionPointer_t handler, IRQn_Type irq) {
+    int irq_pos = get_irq_index(irq);
+
+    if (NULL == _chains[irq_pos])
+        return false;
+    if (!_chains[irq_pos]->remove(handler))
+        return false;
+    // If there's a single function left in the chain, swith the interrupt vector
+    // to call that function directly. This way we save both time and space.
+    if (_chains[irq_pos]->size() == 1 && NULL != _chains[irq_pos]->get(0)->get_function()) {
+        NVIC_SetVector(irq, (uint32_t)_chains[irq_pos]->get(0)->get_function());
+        delete _chains[irq_pos];
+        _chains[irq_pos] = (CallChain*) NULL;
+    }
+    return true;
+}
+
+void InterruptManager::irq_helper() {
+    _chains[__get_IPSR()]->call();
+}
+
+int InterruptManager::get_irq_index(IRQn_Type irq) {
+    return (int)irq + NVIC_USER_IRQ_OFFSET;
+}
+
+void InterruptManager::static_irq_helper() {
+    InterruptManager::get()->irq_helper();
+}
+
+} // namespace mbed
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/LocalFileSystem.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,224 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "LocalFileSystem.h"
+
+#if DEVICE_LOCALFILESYSTEM
+
+#include "semihost_api.h"
+#include <string.h>
+#include <stdio.h>
+
+namespace mbed {
+
+/* Extension to FINFO type defined in RTL.h (in Keil RL) - adds 'create time'. */
+typedef struct {
+    unsigned char  hr;   /* Hours    [0..23]                  */
+    unsigned char  min;  /* Minutes  [0..59]                  */
+    unsigned char  sec;  /* Seconds  [0..59]                  */
+    unsigned char  day;  /* Day      [1..31]                  */
+    unsigned char  mon;  /* Month    [1..12]                  */
+    unsigned short year; /* Year     [1980..2107]             */
+} FTIME;
+
+typedef struct {         /* File Search info record           */
+    char  name[32];      /* File name                         */
+    long  size;          /* File size in bytes                */
+    int   fileID;        /* System File Identification        */
+    FTIME create_time;   /* Date & time file was created      */
+    FTIME write_time;    /* Date & time of last write         */
+} XFINFO;
+
+#define RESERVED_FOR_USER_APPLICATIONS (0x100) /* 0x100 - 0x1ff */
+#define USR_XFFIND (RESERVED_FOR_USER_APPLICATIONS + 0)
+
+static int xffind (const char *pattern, XFINFO *info) {
+    unsigned param[4];
+
+    param[0] = (unsigned long)pattern;
+    param[1] = (unsigned long)strlen(pattern);
+    param[2] = (unsigned long)info;
+    param[3] = (unsigned long)sizeof(XFINFO);
+
+    return __semihost(USR_XFFIND, param);
+}
+
+#define OPEN_R          0
+#define OPEN_B          1
+#define OPEN_PLUS       2
+#define OPEN_W          4
+#define OPEN_A          8
+#define OPEN_INVALID   -1
+
+int posix_to_semihost_open_flags(int flags) {
+    /* POSIX flags -> semihosting open mode */
+    int openmode;
+    if (flags & O_RDWR) {
+        /* a plus mode */
+        openmode = OPEN_PLUS;
+        if (flags & O_APPEND) {
+            openmode |= OPEN_A;
+        } else if (flags & O_TRUNC) {
+            openmode |= OPEN_W;
+        } else {
+            openmode |= OPEN_R;
+        }
+    } else if (flags & O_WRONLY) {
+        /* write or append */
+        if (flags & O_APPEND) {
+            openmode = OPEN_A;
+        } else {
+            openmode = OPEN_W;
+        }
+    } else if (flags == O_RDONLY) {
+        /* read mode */
+        openmode = OPEN_R;
+    } else {
+        /* invalid flags */
+        openmode = OPEN_INVALID;
+    }
+
+    return openmode;
+}
+
+FILEHANDLE local_file_open(const char* name, int flags) {
+    int openmode = posix_to_semihost_open_flags(flags);
+    if (openmode == OPEN_INVALID) {
+        return (FILEHANDLE)NULL;
+    }
+
+    FILEHANDLE fh = semihost_open(name, openmode);
+    if (fh == -1) {
+        return (FILEHANDLE)NULL;
+    }
+
+    return fh;
+}
+
+LocalFileHandle::LocalFileHandle(FILEHANDLE fh) : _fh(fh), pos(0) {
+}
+
+int LocalFileHandle::close() {
+    int retval = semihost_close(_fh);
+    delete this;
+    return retval;
+}
+
+ssize_t LocalFileHandle::write(const void *buffer, size_t length) {
+    ssize_t n = semihost_write(_fh, (const unsigned char*)buffer, length, 0); // number of characters not written
+    n = length - n; // number of characters written
+    pos += n;
+    return n;
+}
+
+ssize_t LocalFileHandle::read(void *buffer, size_t length) {
+    ssize_t n = semihost_read(_fh, (unsigned char*)buffer, length, 0); // number of characters not read
+    n = length - n; // number of characters read
+    pos += n;
+    return n;
+}
+
+int LocalFileHandle::isatty() {
+    return semihost_istty(_fh);
+}
+
+off_t LocalFileHandle::lseek(off_t position, int whence) {
+    if (whence == SEEK_CUR) {
+        position += pos;
+    } else if (whence == SEEK_END) {
+        position += semihost_flen(_fh);
+    } /* otherwise SEEK_SET, so position is fine */
+
+    /* Always seems to return -1, so just ignore for now. */
+    semihost_seek(_fh, position);
+    pos = position;
+    return position;
+}
+
+int LocalFileHandle::fsync() {
+    return semihost_ensure(_fh);
+}
+
+off_t LocalFileHandle::flen() {
+    return semihost_flen(_fh);
+}
+
+class LocalDirHandle : public DirHandle {
+
+public:
+    struct dirent cur_entry;
+    XFINFO info;
+
+    LocalDirHandle() : cur_entry(), info() {
+    }
+
+    virtual int closedir() {
+        delete this;
+        return 0;
+    }
+
+    virtual struct dirent *readdir() {
+        if (xffind("*", &info)!=0) {
+            return NULL;
+        }
+        memcpy(cur_entry.d_name, info.name, sizeof(info.name));
+        return &cur_entry;
+    }
+
+    virtual void rewinddir() {
+        info.fileID = 0;
+    }
+
+    virtual off_t telldir() {
+        return info.fileID;
+    }
+
+    virtual void seekdir(off_t offset) {
+        info.fileID = offset;
+    }
+};
+
+FileHandle *LocalFileSystem::open(const char* name, int flags) {
+    /* reject filenames with / in them */
+    for (const char *tmp = name; *tmp; tmp++) {
+        if (*tmp == '/') {
+            return NULL;
+        }
+    }
+
+    int openmode = posix_to_semihost_open_flags(flags);
+    if (openmode == OPEN_INVALID) {
+        return NULL;
+    }
+
+    FILEHANDLE fh = semihost_open(name, openmode);
+    if (fh == -1) {
+        return NULL;
+    }
+    return new LocalFileHandle(fh);
+}
+
+int LocalFileSystem::remove(const char *filename) {
+    return semihost_remove(filename);
+}
+
+DirHandle *LocalFileSystem::opendir(const char *name) {
+    return new LocalDirHandle();
+}
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/RawSerial.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,68 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "RawSerial.h"
+#include "wait_api.h"
+#include <cstdarg>
+
+#if DEVICE_SERIAL
+
+#define STRING_STACK_LIMIT    120
+
+namespace mbed {
+
+RawSerial::RawSerial(PinName tx, PinName rx) : SerialBase(tx, rx) {
+}
+
+int RawSerial::getc() {
+    return _base_getc();
+}
+
+int RawSerial::putc(int c) {
+    return _base_putc(c);
+}
+
+int RawSerial::puts(const char *str) {
+    while (*str)
+        putc(*str ++);
+    return 0;
+}
+
+// Experimental support for printf in RawSerial. No Stream inheritance
+// means we can't call printf() directly, so we use sprintf() instead.
+// We only call malloc() for the sprintf() buffer if the buffer
+// length is above a certain threshold, otherwise we use just the stack.
+int RawSerial::printf(const char *format, ...) {
+    std::va_list arg;
+    va_start(arg, format);
+    int len = vsnprintf(NULL, 0, format, arg);
+    if (len < STRING_STACK_LIMIT) {
+        char temp[STRING_STACK_LIMIT];
+        vsprintf(temp, format, arg);
+        puts(temp);
+    } else {
+        char *temp = new char[len + 1];
+        vsprintf(temp, format, arg);
+        puts(temp);
+        delete[] temp;
+    }
+    va_end(arg);
+    return len;
+}
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/SPI.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "SPI.h"
+
+#if DEVICE_SPI
+
+namespace mbed {
+
+SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName _unused) :
+        _spi(),
+        _bits(8),
+        _mode(0),
+        _hz(1000000) {
+    spi_init(&_spi, mosi, miso, sclk, NC);
+    spi_format(&_spi, _bits, _mode, 0);
+    spi_frequency(&_spi, _hz);
+}
+
+void SPI::format(int bits, int mode) {
+    _bits = bits;
+    _mode = mode;
+    SPI::_owner = NULL; // Not that elegant, but works. rmeyer
+    aquire();
+}
+
+void SPI::frequency(int hz) {
+    _hz = hz;
+    SPI::_owner = NULL; // Not that elegant, but works. rmeyer
+    aquire();
+}
+
+SPI* SPI::_owner = NULL;
+
+// ignore the fact there are multiple physical spis, and always update if it wasnt us last
+void SPI::aquire() {
+     if (_owner != this) {
+        spi_format(&_spi, _bits, _mode, 0);
+        spi_frequency(&_spi, _hz);
+        _owner = this;
+    }
+}
+
+int SPI::write(int value) {
+    aquire();
+    return spi_master_write(&_spi, value);
+}
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/SPISlave.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "SPISlave.h"
+
+#if DEVICE_SPISLAVE
+
+namespace mbed {
+
+SPISlave::SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
+    _spi(),
+    _bits(8),
+    _mode(0),
+    _hz(1000000)
+ {
+    spi_init(&_spi, mosi, miso, sclk, ssel);
+    spi_format(&_spi, _bits, _mode, 1);
+    spi_frequency(&_spi, _hz);
+}
+
+void SPISlave::format(int bits, int mode) {
+    _bits = bits;
+    _mode = mode;
+    spi_format(&_spi, _bits, _mode, 1);
+}
+
+void SPISlave::frequency(int hz) {
+    _hz = hz;
+    spi_frequency(&_spi, _hz);
+}
+
+int SPISlave::receive(void) {
+    return(spi_slave_receive(&_spi));
+}
+
+int SPISlave::read(void) {
+    return(spi_slave_read(&_spi));
+}
+
+void SPISlave::reply(int value) {
+    spi_slave_write(&_spi, value);
+}
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/Serial.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,37 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Serial.h"
+#include "wait_api.h"
+
+#if DEVICE_SERIAL
+
+namespace mbed {
+
+Serial::Serial(PinName tx, PinName rx, const char *name) : SerialBase(tx, rx), Stream(name) {
+}
+
+int Serial::_getc() {
+    return _base_getc();
+}
+
+int Serial::_putc(int c) {
+    return _base_putc(c);
+}
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/SerialBase.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,109 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "SerialBase.h"
+#include "wait_api.h"
+
+#if DEVICE_SERIAL
+
+namespace mbed {
+
+SerialBase::SerialBase(PinName tx, PinName rx) : _serial(), _baud(9600) {
+    serial_init(&_serial, tx, rx);
+    serial_irq_handler(&_serial, SerialBase::_irq_handler, (uint32_t)this);
+}
+
+void SerialBase::baud(int baudrate) {
+    serial_baud(&_serial, baudrate);
+    _baud = baudrate;
+}
+
+void SerialBase::format(int bits, Parity parity, int stop_bits) {
+    serial_format(&_serial, bits, (SerialParity)parity, stop_bits);
+}
+
+int SerialBase::readable() {
+    return serial_readable(&_serial);
+}
+
+
+int SerialBase::writeable() {
+    return serial_writable(&_serial);
+}
+
+void SerialBase::attach(void (*fptr)(void), IrqType type) {
+    if (fptr) {
+        _irq[type].attach(fptr);
+        serial_irq_set(&_serial, (SerialIrq)type, 1);
+    } else {
+        serial_irq_set(&_serial, (SerialIrq)type, 0);
+    }
+}
+
+void SerialBase::_irq_handler(uint32_t id, SerialIrq irq_type) {
+    SerialBase *handler = (SerialBase*)id;
+    handler->_irq[irq_type].call();
+}
+
+int SerialBase::_base_getc() {
+    return serial_getc(&_serial);
+}
+
+int SerialBase::_base_putc(int c) {
+    serial_putc(&_serial, c);
+    return c;
+}
+
+void SerialBase::send_break() {
+  // Wait for 1.5 frames before clearing the break condition
+  // This will have different effects on our platforms, but should
+  // ensure that we keep the break active for at least one frame.
+  // We consider a full frame (1 start bit + 8 data bits bits +
+  // 1 parity bit + 2 stop bits = 12 bits) for computation.
+  // One bit time (in us) = 1000000/_baud
+  // Twelve bits: 12000000/baud delay
+  // 1.5 frames: 18000000/baud delay
+  serial_break_set(&_serial);
+  wait_us(18000000/_baud);
+  serial_break_clear(&_serial);
+}
+
+#if DEVICE_SERIAL_FC
+void SerialBase::set_flow_control(Flow type, PinName flow1, PinName flow2) {
+    FlowControl flow_type = (FlowControl)type;
+    switch(type) {
+        case RTS:
+            serial_set_flow_control(&_serial, flow_type, flow1, NC);
+            break;
+
+        case CTS:
+            serial_set_flow_control(&_serial, flow_type, NC, flow1);
+            break;
+
+        case RTSCTS:
+        case Disabled:
+            serial_set_flow_control(&_serial, flow_type, flow1, flow2);
+            break;
+
+        default:
+            break;
+    }
+}
+#endif
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/Stream.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,112 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Stream.h"
+
+#include <cstdarg>
+
+namespace mbed {
+
+Stream::Stream(const char *name) : FileLike(name), _file(NULL) {
+    /* open ourselves */
+    char buf[12]; /* :0x12345678 + null byte */
+    std::sprintf(buf, ":%p", this);
+    _file = std::fopen(buf, "w+");
+    setbuf(_file, NULL);
+}
+
+Stream::~Stream() {
+    fclose(_file);
+}
+
+int Stream::putc(int c) {
+    fflush(_file);
+    return std::fputc(c, _file);
+}
+int Stream::puts(const char *s) {
+    fflush(_file);
+    return std::fputs(s, _file);
+}
+int Stream::getc() {
+    fflush(_file);
+    return std::fgetc(_file);
+}
+char* Stream::gets(char *s, int size) {
+    fflush(_file);
+    return std::fgets(s,size,_file);
+}
+
+int Stream::close() {
+    return 0;
+}
+
+ssize_t Stream::write(const void* buffer, size_t length) {
+    const char* ptr = (const char*)buffer;
+    const char* end = ptr + length;
+    while (ptr != end) {
+        if (_putc(*ptr++) == EOF) {
+            break;
+        }
+    }
+    return ptr - (const char*)buffer;
+}
+
+ssize_t Stream::read(void* buffer, size_t length) {
+    char* ptr = (char*)buffer;
+    char* end = ptr + length;
+    while (ptr != end) {
+        int c = _getc();
+        if (c==EOF) break;
+        *ptr++ = c;
+    }
+    return ptr - (const char*)buffer;
+}
+
+off_t Stream::lseek(off_t offset, int whence) {
+    return 0;
+}
+
+int Stream::isatty() {
+    return 0;
+}
+
+int Stream::fsync() {
+    return 0;
+}
+
+off_t Stream::flen() {
+    return 0;
+}
+
+int Stream::printf(const char* format, ...) {
+    std::va_list arg;
+    va_start(arg, format);
+    fflush(_file);
+    int r = vfprintf(_file, format, arg);
+    va_end(arg);
+    return r;
+}
+
+int Stream::scanf(const char* format, ...) {
+    std::va_list arg;
+    va_start(arg, format);
+    fflush(_file);
+    int r = vfscanf(_file, format, arg);
+    va_end(arg);
+    return r;
+}
+
+} // namespace mbed
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/Ticker.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Ticker.h"
+
+#include "TimerEvent.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+void Ticker::detach() {
+    remove();
+    _function.attach(0);
+}
+
+void Ticker::setup(unsigned int t) {
+    remove();
+    _delay = t;
+    insert(_delay + us_ticker_read());
+}
+
+void Ticker::handler() {
+    insert(event.timestamp + _delay);
+    _function.call();
+}
+
+} // namespace mbed
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/Timeout.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,25 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Timeout.h"
+
+namespace mbed {
+
+void Timeout::handler() {
+    _function.call();
+}
+
+} // namespace mbed
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/Timer.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Timer.h"
+#include "us_ticker_api.h"
+
+namespace mbed {
+
+Timer::Timer() : _running(), _start(), _time() {
+    reset();
+}
+
+void Timer::start() {
+    _start = us_ticker_read();
+    _running = 1;
+}
+
+void Timer::stop() {
+    _time += slicetime();
+    _running = 0;
+}
+
+int Timer::read_us() {
+    return _time + slicetime();
+}
+
+float Timer::read() {
+    return (float)read_us() / 1000000.0f;
+}
+
+int Timer::read_ms() {
+    return read_us() / 1000;
+}
+
+int Timer::slicetime() {
+    if (_running) {
+        return us_ticker_read() - _start;
+    } else {
+        return 0;
+    }
+}
+
+void Timer::reset() {
+    _start = us_ticker_read();
+    _time = 0;
+}
+
+#ifdef MBED_OPERATORS
+Timer::operator float() {
+    return read();
+}
+#endif
+
+} // namespace mbed
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/TimerEvent.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "TimerEvent.h"
+#include "cmsis.h"
+
+#include <stddef.h>
+
+namespace mbed {
+
+TimerEvent::TimerEvent() : event() {
+    us_ticker_set_handler((&TimerEvent::irq));
+}
+
+void TimerEvent::irq(uint32_t id) {
+    TimerEvent *timer_event = (TimerEvent*)id;
+    timer_event->handler();
+}
+
+TimerEvent::~TimerEvent() {
+    remove();
+}
+
+// insert in to linked list
+void TimerEvent::insert(unsigned int timestamp) {
+    us_ticker_insert_event(&event, timestamp, (uint32_t)this);
+}
+
+void TimerEvent::remove() {
+    us_ticker_remove_event(&event);
+}
+
+} // namespace mbed
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/assert.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,33 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "device.h"
+
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
+
+#include <stdlib.h>
+#include "mbed_interface.h"
+
+void mbed_assert_internal(const char *expr, const char *file, int line)
+{
+#if DEVICE_STDIO_MESSAGES
+    fprintf(stderr, "mbed assertation failed: %s, file: %s, line %d \n", expr, file, line);
+#endif
+    mbed_die();
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/board.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,60 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "wait_api.h"
+#include "toolchain.h"
+#include "mbed_interface.h"
+
+WEAK void mbed_die(void) {
+#ifndef NRF51_H
+	__disable_irq();	// dont allow interrupts to disturb the flash pattern
+#endif
+#if   (DEVICE_ERROR_RED == 1)
+    gpio_t led_red; gpio_init_out(&led_red, LED_RED);
+#elif (DEVICE_ERROR_PATTERN == 1)
+    gpio_t led_1; gpio_init_out(&led_1, LED1);
+    gpio_t led_2; gpio_init_out(&led_2, LED2);
+    gpio_t led_3; gpio_init_out(&led_3, LED3);
+    gpio_t led_4; gpio_init_out(&led_4, LED4);
+#endif
+
+    while (1) {
+#if   (DEVICE_ERROR_RED == 1)
+        gpio_write(&led_red, 1);
+
+#elif (DEVICE_ERROR_PATTERN == 1)
+        gpio_write(&led_1, 1);
+        gpio_write(&led_2, 0);
+        gpio_write(&led_3, 0);
+        gpio_write(&led_4, 1);
+#endif
+
+        wait_ms(150);
+
+#if   (DEVICE_ERROR_RED == 1)
+        gpio_write(&led_red, 0);
+
+#elif (DEVICE_ERROR_PATTERN == 1)
+        gpio_write(&led_1, 0);
+        gpio_write(&led_2, 1);
+        gpio_write(&led_3, 1);
+        gpio_write(&led_4, 0);
+#endif
+
+        wait_ms(150);
+    }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/error.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,34 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdlib.h>
+#include <stdarg.h>
+#include "device.h"
+#include "toolchain.h"
+#include "mbed_error.h"
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
+
+WEAK void error(const char* format, ...) {
+#if DEVICE_STDIO_MESSAGES
+    va_list arg;
+    va_start(arg, format);
+    vfprintf(stderr, format, arg);
+    va_end(arg);
+#endif
+    exit(1);
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/exit.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "semihost_api.h"
+#include "mbed_interface.h"
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
+
+#ifdef TOOLCHAIN_GCC_CW
+// TODO: Ideally, we would like to define directly "_ExitProcess"
+void mbed_exit(int return_code) {
+#else
+void exit(int return_code) {
+#endif
+
+#if DEVICE_STDIO_MESSAGES
+    fflush(stdout);
+    fflush(stderr);
+#endif
+
+#if DEVICE_SEMIHOST
+    if (mbed_interface_connected()) {
+        semihost_exit();
+    }
+#endif
+    if (return_code) {
+        mbed_die();
+    }
+
+    while (1);
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/gpio.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,62 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+
+static inline void _gpio_init_in(gpio_t* gpio, PinName pin, PinMode mode)
+{
+    gpio_init(gpio, pin);
+    if (pin != NC) {
+        gpio_dir(gpio, PIN_INPUT);
+        gpio_mode(gpio, mode);
+    }
+}
+
+static inline void _gpio_init_out(gpio_t* gpio, PinName pin, PinMode mode, int value)
+{
+    gpio_init(gpio, pin);
+    if (pin != NC) {
+        gpio_write(gpio, value);
+        gpio_dir(gpio, PIN_OUTPUT);
+        gpio_mode(gpio, mode);
+    }
+}
+
+void gpio_init_in(gpio_t* gpio, PinName pin) {
+    gpio_init_in_ex(gpio, pin, PullDefault);
+}
+
+void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode) {
+    _gpio_init_in(gpio, pin, mode);
+}
+
+void gpio_init_out(gpio_t* gpio, PinName pin) {
+    gpio_init_out_ex(gpio, pin, 0);
+}
+
+void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value) {
+    _gpio_init_out(gpio, pin, PullNone, value);
+}
+
+void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value) {
+    if (direction == PIN_INPUT) {
+        _gpio_init_in(gpio, pin, mode);
+        if (pin != NC)
+            gpio_write(gpio, value); // we prepare the value in case it is switched later
+    } else {
+        _gpio_init_out(gpio, pin, mode, value);
+    }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/mbed_interface.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,113 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+#include "mbed_interface.h"
+
+#include "gpio_api.h"
+#include "wait_api.h"
+#include "semihost_api.h"
+#include "mbed_error.h"
+#include "toolchain.h"
+
+#if DEVICE_SEMIHOST
+
+// return true if a debugger is attached, indicating mbed interface is connected
+int mbed_interface_connected(void) {
+    return semihost_connected();
+}
+
+int mbed_interface_reset(void) {
+    if (mbed_interface_connected()) {
+        semihost_reset();
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+WEAK int mbed_interface_uid(char *uid) {
+    if (mbed_interface_connected()) {
+        return semihost_uid(uid); // Returns 0 if successful, -1 on failure
+    } else {
+        uid[0] = 0;
+        return -1;
+    }
+}
+
+int mbed_interface_disconnect(void) {
+    int res;
+    if (mbed_interface_connected()) {
+        if ((res = semihost_disabledebug()) != 0)
+            return res;
+        while (mbed_interface_connected());
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+int mbed_interface_powerdown(void) {
+    int res;
+    if (mbed_interface_connected()) {
+        if ((res = semihost_powerdown()) != 0)
+            return res;
+        while (mbed_interface_connected());
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+// for backward compatibility
+void mbed_reset(void) {
+    mbed_interface_reset();
+}
+
+WEAK int mbed_uid(char *uid) {
+    return mbed_interface_uid(uid);
+}
+#endif
+
+WEAK void mbed_mac_address(char *mac) {
+#if DEVICE_SEMIHOST
+    char uid[DEVICE_ID_LENGTH + 1];
+    int i;
+
+    // if we have a UID, extract the MAC
+    if (mbed_interface_uid(uid) == 0) {
+        char *p = uid;
+#if defined(DEVICE_MAC_OFFSET)
+        p += DEVICE_MAC_OFFSET;
+#endif
+        for (i=0; i<6; i++) {
+            int byte;
+            sscanf(p, "%2x", &byte);
+            mac[i] = byte;
+            p += 2;
+        }
+    } else {  // else return a default MAC
+#endif
+        mac[0] = 0x00;
+        mac[1] = 0x02;
+        mac[2] = 0xF7;
+        mac[3] = 0xF0;
+        mac[4] = 0x00;
+        mac[5] = 0x00;
+#if DEVICE_SEMIHOST
+    }
+#endif
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/pinmap_common.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,70 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pinmap.h"
+#include "mbed_error.h"
+
+void pinmap_pinout(PinName pin, const PinMap *map) {
+    if (pin == NC)
+        return;
+
+    while (map->pin != NC) {
+        if (map->pin == pin) {
+            pin_function(pin, map->function);
+
+            pin_mode(pin, PullNone);
+            return;
+        }
+        map++;
+    }
+    error("could not pinout");
+}
+
+uint32_t pinmap_merge(uint32_t a, uint32_t b) {
+    // both are the same (inc both NC)
+    if (a == b)
+        return a;
+
+    // one (or both) is not connected
+    if (a == (uint32_t)NC)
+        return b;
+    if (b == (uint32_t)NC)
+        return a;
+
+    // mis-match error case
+    error("pinmap mis-match");
+    return (uint32_t)NC;
+}
+
+uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map) {
+    while (map->pin != NC) {
+        if (map->pin == pin)
+            return map->peripheral;
+        map++;
+    }
+    return (uint32_t)NC;
+}
+
+uint32_t pinmap_peripheral(PinName pin, const PinMap* map) {
+    uint32_t peripheral = (uint32_t)NC;
+
+    if (pin == (PinName)NC)
+        return (uint32_t)NC;
+    peripheral = pinmap_find_peripheral(pin, map);
+    if ((uint32_t)NC == peripheral) // no mapping available
+        error("pinmap not found for peripheral");
+    return peripheral;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/retarget.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,483 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "platform.h"
+#include "FileHandle.h"
+#include "FileSystemLike.h"
+#include "FilePath.h"
+#include "serial_api.h"
+#include "toolchain.h"
+#include <errno.h>
+
+#if defined(__ARMCC_VERSION)
+#   include <rt_sys.h>
+#   define PREFIX(x)    _sys##x
+#   define OPEN_MAX     _SYS_OPEN
+#   ifdef __MICROLIB
+#       pragma import(__use_full_stdio)
+#   endif
+
+#elif defined(__ICCARM__)
+#   include <yfuns.h>
+#   define PREFIX(x)        _##x
+#   define OPEN_MAX         16
+
+#   define STDIN_FILENO     0
+#   define STDOUT_FILENO    1
+#   define STDERR_FILENO    2
+
+#else
+#   include <sys/stat.h>
+#   include <sys/unistd.h>
+#   include <sys/syslimits.h>
+#   define PREFIX(x)    x
+#endif
+
+using namespace mbed;
+
+#if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+// Before version 5.03, we were using a patched version of microlib with proper names
+extern const char __stdin_name[]  = ":tt";
+extern const char __stdout_name[] = ":tt";
+extern const char __stderr_name[] = ":tt";
+
+#else
+extern const char __stdin_name[]  = "/stdin";
+extern const char __stdout_name[] = "/stdout";
+extern const char __stderr_name[] = "/stderr";
+#endif
+
+/* newlib has the filehandle field in the FILE struct as a short, so
+ * we can't just return a Filehandle* from _open and instead have to
+ * put it in a filehandles array and return the index into that array
+ * (or rather index+3, as filehandles 0-2 are stdin/out/err).
+ */
+static FileHandle *filehandles[OPEN_MAX];
+
+FileHandle::~FileHandle() {
+    /* Remove all open filehandles for this */
+    for (unsigned int fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
+        if (filehandles[fh_i] == this) {
+            filehandles[fh_i] = NULL;
+        }
+    }
+}
+
+#if DEVICE_SERIAL
+extern int stdio_uart_inited;
+extern serial_t stdio_uart;
+#endif
+
+static void init_serial() {
+#if DEVICE_SERIAL
+    if (stdio_uart_inited) return;
+    serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
+#endif
+}
+
+static inline int openmode_to_posix(int openmode) {
+    int posix = openmode;
+#ifdef __ARMCC_VERSION
+    if (openmode & OPEN_PLUS) {
+        posix = O_RDWR;
+    } else if(openmode & OPEN_W) {
+        posix = O_WRONLY;
+    } else if(openmode & OPEN_A) {
+        posix = O_WRONLY|O_APPEND;
+    } else {
+        posix = O_RDONLY;
+    }
+    /* a, w, a+, w+ all create if file does not already exist */
+    if (openmode & (OPEN_A|OPEN_W)) {
+        posix |= O_CREAT;
+    }
+    /* w and w+ truncate */
+    if (openmode & OPEN_W) {
+        posix |= O_TRUNC;
+    }
+#elif defined(__ICCARM__)
+    switch (openmode & _LLIO_RDWRMASK) {
+        case _LLIO_RDONLY: posix = O_RDONLY; break;
+        case _LLIO_WRONLY: posix = O_WRONLY; break;
+        case _LLIO_RDWR  : posix = O_RDWR  ; break;
+    }
+    if (openmode & _LLIO_CREAT ) posix |= O_CREAT;
+    if (openmode & _LLIO_APPEND) posix |= O_APPEND;
+    if (openmode & _LLIO_TRUNC ) posix |= O_TRUNC;
+#endif
+    return posix;
+}
+
+extern "C" FILEHANDLE PREFIX(_open)(const char* name, int openmode) {
+    #if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+    // Before version 5.03, we were using a patched version of microlib with proper names
+    // This is the workaround that the microlib author suggested us
+    static int n = 0;
+    if (!std::strcmp(name, ":tt")) return n++;
+
+    #else
+    /* Use the posix convention that stdin,out,err are filehandles 0,1,2.
+     */
+    if (std::strcmp(name, __stdin_name) == 0) {
+        init_serial();
+        return 0;
+    } else if (std::strcmp(name, __stdout_name) == 0) {
+        init_serial();
+        return 1;
+    } else if (std::strcmp(name, __stderr_name) == 0) {
+        init_serial();
+        return 2;
+    }
+    #endif
+
+    // find the first empty slot in filehandles
+    unsigned int fh_i;
+    for (fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
+        if (filehandles[fh_i] == NULL) break;
+    }
+    if (fh_i >= sizeof(filehandles)/sizeof(*filehandles)) {
+        return -1;
+    }
+
+    FileHandle *res;
+
+    /* FILENAME: ":0x12345678" describes a FileLike* */
+    if (name[0] == ':') {
+        void *p;
+        sscanf(name, ":%p", &p);
+        res = (FileHandle*)p;
+
+    /* FILENAME: "/file_system/file_name" */
+    } else {
+        FilePath path(name);
+
+        if (!path.exists())
+            return -1;
+        else if (path.isFile()) {
+            res = path.file();
+        } else {
+            FileSystemLike *fs = path.fileSystem();
+            if (fs == NULL) return -1;
+            int posix_mode = openmode_to_posix(openmode);
+            res = fs->open(path.fileName(), posix_mode); /* NULL if fails */
+        }
+    }
+
+    if (res == NULL) return -1;
+    filehandles[fh_i] = res;
+
+    return fh_i + 3; // +3 as filehandles 0-2 are stdin/out/err
+}
+
+extern "C" int PREFIX(_close)(FILEHANDLE fh) {
+    if (fh < 3) return 0;
+
+    FileHandle* fhc = filehandles[fh-3];
+    filehandles[fh-3] = NULL;
+    if (fhc == NULL) return -1;
+
+    return fhc->close();
+}
+
+#if defined(__ICCARM__)
+extern "C" size_t    __write (int        fh, const unsigned char *buffer, size_t length) {
+#else
+extern "C" int PREFIX(_write)(FILEHANDLE fh, const unsigned char *buffer, unsigned int length, int mode) {
+#endif
+    int n; // n is the number of bytes written
+    if (fh < 3) {
+#if DEVICE_SERIAL
+        if (!stdio_uart_inited) init_serial();
+        for (unsigned int i = 0; i < length; i++) {
+            serial_putc(&stdio_uart, buffer[i]);
+        }
+#endif
+        n = length;
+    } else {
+        FileHandle* fhc = filehandles[fh-3];
+        if (fhc == NULL) return -1;
+
+        n = fhc->write(buffer, length);
+    }
+#ifdef __ARMCC_VERSION
+    return length-n;
+#else
+    return n;
+#endif
+}
+
+#if defined(__ICCARM__)
+extern "C" size_t    __read (int        fh, unsigned char *buffer, size_t       length) {
+#else
+extern "C" int PREFIX(_read)(FILEHANDLE fh, unsigned char *buffer, unsigned int length, int mode) {
+#endif
+    int n; // n is the number of bytes read
+    if (fh < 3) {
+        // only read a character at a time from stdin
+#if DEVICE_SERIAL
+        if (!stdio_uart_inited) init_serial();
+        *buffer = serial_getc(&stdio_uart);
+#endif
+        n = 1;
+    } else {
+        FileHandle* fhc = filehandles[fh-3];
+        if (fhc == NULL) return -1;
+
+        n = fhc->read(buffer, length);
+    }
+#ifdef __ARMCC_VERSION
+    return length-n;
+#else
+    return n;
+#endif
+}
+
+#ifdef __ARMCC_VERSION
+extern "C" int PREFIX(_istty)(FILEHANDLE fh)
+#else
+extern "C" int _isatty(FILEHANDLE fh)
+#endif
+{
+    /* stdin, stdout and stderr should be tty */
+    if (fh < 3) return 1;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) return -1;
+
+    return fhc->isatty();
+}
+
+extern "C"
+#if defined(__ARMCC_VERSION)
+int _sys_seek(FILEHANDLE fh, long position)
+#elif defined(__ICCARM__)
+long __lseek(int fh, long offset, int whence)
+#else
+int _lseek(FILEHANDLE fh, int offset, int whence)
+#endif
+{
+    if (fh < 3) return 0;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) return -1;
+
+#if defined(__ARMCC_VERSION)
+    return fhc->lseek(position, SEEK_SET);
+#else
+    return fhc->lseek(offset, whence);
+#endif
+}
+
+#ifdef __ARMCC_VERSION
+extern "C" int PREFIX(_ensure)(FILEHANDLE fh) {
+    if (fh < 3) return 0;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) return -1;
+
+    return fhc->fsync();
+}
+
+extern "C" long PREFIX(_flen)(FILEHANDLE fh) {
+    if (fh < 3) return 0;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) return -1;
+
+    return fhc->flen();
+}
+#endif
+
+
+#if !defined(__ARMCC_VERSION) && !defined(__ICCARM__)
+extern "C" int _fstat(int fd, struct stat *st) {
+    if ((STDOUT_FILENO == fd) || (STDERR_FILENO == fd) || (STDIN_FILENO == fd)) {
+        st->st_mode = S_IFCHR;
+        return  0;
+    }
+
+    errno = EBADF;
+    return -1;
+}
+#endif
+
+namespace std {
+extern "C" int remove(const char *path) {
+    FilePath fp(path);
+    FileSystemLike *fs = fp.fileSystem();
+    if (fs == NULL) return -1;
+
+    return fs->remove(fp.fileName());
+}
+
+extern "C" int rename(const char *oldname, const char *newname) {
+    FilePath fpOld(oldname);
+    FilePath fpNew(newname);
+    FileSystemLike *fsOld = fpOld.fileSystem();
+    FileSystemLike *fsNew = fpNew.fileSystem();
+
+    /* rename only if both files are on the same FS */
+    if (fsOld != fsNew || fsOld == NULL) return -1;
+
+    return fsOld->rename(fpOld.fileName(), fpNew.fileName());
+}
+
+extern "C" char *tmpnam(char *s) {
+    return NULL;
+}
+
+extern "C" FILE *tmpfile() {
+    return NULL;
+}
+} // namespace std
+
+#ifdef __ARMCC_VERSION
+extern "C" char *_sys_command_string(char *cmd, int len) {
+    return NULL;
+}
+#endif
+
+extern "C" DIR *opendir(const char *path) {
+    /* root dir is FileSystemLike */
+    if (path[0] == '/' && path[1] == 0) {
+        return FileSystemLike::opendir();
+    }
+
+    FilePath fp(path);
+    FileSystemLike* fs = fp.fileSystem();
+    if (fs == NULL) return NULL;
+
+    return fs->opendir(fp.fileName());
+}
+
+extern "C" struct dirent *readdir(DIR *dir) {
+    return dir->readdir();
+}
+
+extern "C" int closedir(DIR *dir) {
+    return dir->closedir();
+}
+
+extern "C" void rewinddir(DIR *dir) {
+    dir->rewinddir();
+}
+
+extern "C" off_t telldir(DIR *dir) {
+    return dir->telldir();
+}
+
+extern "C" void seekdir(DIR *dir, off_t off) {
+    dir->seekdir(off);
+}
+
+extern "C" int mkdir(const char *path, mode_t mode) {
+    FilePath fp(path);
+    FileSystemLike *fs = fp.fileSystem();
+    if (fs == NULL) return -1;
+
+    return fs->mkdir(fp.fileName(), mode);
+}
+
+#if defined(TOOLCHAIN_GCC)
+/* prevents the exception handling name demangling code getting pulled in */
+#include "mbed_error.h"
+namespace __gnu_cxx {
+    void __verbose_terminate_handler() {
+        error("Exception");
+    }
+}
+extern "C" WEAK void __cxa_pure_virtual(void);
+extern "C" WEAK void __cxa_pure_virtual(void) {
+    exit(1);
+}
+
+#endif
+
+// ****************************************************************************
+// mbed_main is a function that is called before main()
+// mbed_sdk_init() is also a function that is called before main(), but unlike
+// mbed_main(), it is not meant for user code, but for the SDK itself to perform
+// initializations before main() is called.
+
+extern "C" WEAK void mbed_main(void);
+extern "C" WEAK void mbed_main(void) {
+}
+
+extern "C" WEAK void mbed_sdk_init(void);
+extern "C" WEAK void mbed_sdk_init(void) {
+}
+
+#if defined(TOOLCHAIN_ARM)
+extern "C" int $Super$$main(void);
+
+extern "C" int $Sub$$main(void) {
+    mbed_sdk_init();
+    mbed_main();
+    return $Super$$main();
+}
+#elif defined(TOOLCHAIN_GCC)
+extern "C" int __real_main(void);
+
+extern "C" int __wrap_main(void) {
+    mbed_sdk_init();
+    mbed_main();
+    return __real_main();
+}
+#elif defined(TOOLCHAIN_IAR)
+// IAR doesn't have the $Super/$Sub mechanism of armcc, nor something equivalent
+// to ld's --wrap. It does have a --redirect, but that doesn't help, since redirecting
+// 'main' to another symbol looses the original 'main' symbol. However, its startup
+// code will call a function to setup argc and argv (__iar_argc_argv) if it is defined.
+// Since mbed doesn't use argc/argv, we use this function to call our mbed_main.
+extern "C" void __iar_argc_argv() {
+    mbed_sdk_init();
+    mbed_main();
+}
+#endif
+
+// Provide implementation of _sbrk (low-level dynamic memory allocation
+// routine) for GCC_ARM which compares new heap pointer with MSP instead of
+// SP.  This make it compatible with RTX RTOS thread stacks.
+#if defined(TOOLCHAIN_GCC_ARM)
+// Linker defined symbol used by _sbrk to indicate where heap should start.
+extern "C" int __end__;
+
+// Turn off the errno macro and use actual global variable instead.
+#undef errno
+extern "C" int errno;
+
+// For ARM7 only
+register unsigned char * stack_ptr __asm ("sp");
+
+// Dynamic memory allocation related syscall.
+extern "C" caddr_t _sbrk(int incr) {
+    static unsigned char* heap = (unsigned char*)&__end__;
+    unsigned char*        prev_heap = heap;
+    unsigned char*        new_heap = heap + incr;
+
+#if defined(TARGET_ARM7)
+    if (new_heap >= stack_ptr) {
+#else
+    if (new_heap >= (unsigned char*)__get_MSP()) {
+#endif
+        errno = ENOMEM;
+        return (caddr_t)-1;
+    }
+
+    heap = new_heap;
+    return (caddr_t) prev_heap;
+}
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/rtc_time.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "rtc_api.h"
+
+#include <time.h>
+#include "rtc_time.h"
+#include "us_ticker_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#if defined (__ICCARM__)
+time_t __time32(time_t *timer)
+#else
+time_t time(time_t *timer)
+#endif
+
+{
+#if DEVICE_RTC
+    if (!(rtc_isenabled())) {
+        set_time(0);
+    }
+    time_t t = rtc_read();
+
+#else
+    time_t t = 0;
+#endif
+
+    if (timer != NULL) {
+        *timer = t;
+    }
+    return t;
+}
+
+void set_time(time_t t) {
+#if DEVICE_RTC
+    rtc_init();
+    rtc_write(t);
+#endif
+}
+
+clock_t clock() {
+    clock_t t = us_ticker_read();
+    t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time
+    return t;
+}
+
+#ifdef __cplusplus
+}
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/semihost_api.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,163 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cmsis.h"
+#include "semihost_api.h"
+
+#include <stdint.h>
+#include <string.h>
+
+#if DEVICE_SEMIHOST
+
+// ARM Semihosting Commands
+#define SYS_OPEN   (0x1)
+#define SYS_CLOSE  (0x2)
+#define SYS_WRITE  (0x5)
+#define SYS_READ   (0x6)
+#define SYS_ISTTY  (0x9)
+#define SYS_SEEK   (0xa)
+#define SYS_ENSURE (0xb)
+#define SYS_FLEN   (0xc)
+#define SYS_REMOVE (0xe)
+#define SYS_RENAME (0xf)
+#define SYS_EXIT   (0x18)
+
+// mbed Semihosting Commands
+#define RESERVED_FOR_USER_APPLICATIONS (0x100) // 0x100 - 0x1ff
+#define USR_XFFIND      (RESERVED_FOR_USER_APPLICATIONS + 0)
+#define USR_UID      (RESERVED_FOR_USER_APPLICATIONS + 1)
+#define USR_RESET     (RESERVED_FOR_USER_APPLICATIONS + 2)
+#define USR_VBUS     (RESERVED_FOR_USER_APPLICATIONS + 3)
+#define USR_POWERDOWN     (RESERVED_FOR_USER_APPLICATIONS + 4)
+#define USR_DISABLEDEBUG (RESERVED_FOR_USER_APPLICATIONS + 5)
+
+#if DEVICE_LOCALFILESYSTEM
+FILEHANDLE semihost_open(const char* name, int openmode) {
+    uint32_t args[3];
+    args[0] = (uint32_t)name;
+    args[1] = (uint32_t)openmode;
+    args[2] = (uint32_t)strlen(name);
+    return __semihost(SYS_OPEN, args);
+}
+
+int semihost_close(FILEHANDLE fh) {
+    return __semihost(SYS_CLOSE, &fh);
+}
+
+int semihost_write(FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode) {
+    if (length == 0) return 0;
+
+    uint32_t args[3];
+    args[0] = (uint32_t)fh;
+    args[1] = (uint32_t)buffer;
+    args[2] = (uint32_t)length;
+    return __semihost(SYS_WRITE, args);
+}
+
+int semihost_read(FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode) {
+    uint32_t args[3];
+    args[0] = (uint32_t)fh;
+    args[1] = (uint32_t)buffer;
+    args[2] = (uint32_t)length;
+    return __semihost(SYS_READ, args);
+}
+
+int semihost_istty(FILEHANDLE fh) {
+    return __semihost(SYS_ISTTY, &fh);
+}
+
+int semihost_seek(FILEHANDLE fh, long position) {
+    uint32_t args[2];
+    args[0] = (uint32_t)fh;
+    args[1] = (uint32_t)position;
+    return __semihost(SYS_SEEK, args);
+}
+
+int semihost_ensure(FILEHANDLE fh) {
+    return __semihost(SYS_ENSURE, &fh);
+}
+
+long semihost_flen(FILEHANDLE fh) {
+    return __semihost(SYS_FLEN, &fh);
+}
+
+int semihost_remove(const char *name) {
+    uint32_t args[2];
+    args[0] = (uint32_t)name;
+    args[1] = (uint32_t)strlen(name);
+    return __semihost(SYS_REMOVE, args);
+}
+
+int semihost_rename(const char *old_name, const char *new_name) {
+    uint32_t args[4];
+    args[0] = (uint32_t)old_name;
+    args[1] = (uint32_t)strlen(old_name);
+    args[0] = (uint32_t)new_name;
+    args[1] = (uint32_t)strlen(new_name);
+    return __semihost(SYS_RENAME, args);
+}
+#endif
+
+int semihost_exit(void) {
+    uint32_t args[4];
+    return __semihost(SYS_EXIT, args);
+}
+
+int semihost_uid(char *uid) {
+    uint32_t args[2];
+    args[0] = (uint32_t)uid;
+    args[1] = DEVICE_ID_LENGTH + 1;
+    return __semihost(USR_UID, &args);
+}
+
+int semihost_reset(void) {
+    // Does not normally return, however if used with older firmware versions
+    // that do not support this call it will return -1.
+    return __semihost(USR_RESET, NULL);
+}
+
+int semihost_vbus(void) {
+    return __semihost(USR_VBUS, NULL);
+}
+
+int semihost_powerdown(void) {
+    return __semihost(USR_POWERDOWN, NULL);
+}
+
+#if DEVICE_DEBUG_AWARENESS
+
+int semihost_connected(void) {
+    return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? 1 : 0;
+}
+
+#else
+// These processors cannot know if the interface is connect, assume so:
+static int is_debugger_attached = 1;
+
+int semihost_connected(void) {
+    return is_debugger_attached;
+}
+#endif
+
+int semihost_disabledebug(void) {
+#if !(DEVICE_DEBUG_AWARENESS)
+    is_debugger_attached = 0;
+#endif
+    return __semihost(USR_DISABLEDEBUG, NULL);
+}
+
+#endif
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/us_ticker_api.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,115 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "cmsis.h"
+
+static ticker_event_handler event_handler;
+static ticker_event_t *head = NULL;
+
+void us_ticker_set_handler(ticker_event_handler handler) {
+    us_ticker_init();
+
+    event_handler = handler;
+}
+
+void us_ticker_irq_handler(void) {
+    us_ticker_clear_interrupt();
+
+    /* Go through all the pending TimerEvents */
+    while (1) {
+        if (head == NULL) {
+            // There are no more TimerEvents left, so disable matches.
+            us_ticker_disable_interrupt();
+            return;
+        }
+
+        if ((int)(head->timestamp - us_ticker_read()) <= 0) {
+            // This event was in the past:
+            //      point to the following one and execute its handler
+            ticker_event_t *p = head;
+            head = head->next;
+            if (event_handler != NULL) {
+                event_handler(p->id); // NOTE: the handler can set new events
+            }
+        } else {
+            // This event and the following ones in the list are in the future:
+            //      set it as next interrupt and return
+            us_ticker_set_interrupt(head->timestamp);
+            return;
+        }
+    }
+}
+
+void us_ticker_insert_event(ticker_event_t *obj, unsigned int timestamp, uint32_t id) {
+    /* disable interrupts for the duration of the function */
+    __disable_irq();
+
+    // initialise our data
+    obj->timestamp = timestamp;
+    obj->id = id;
+
+    /* Go through the list until we either reach the end, or find
+       an element this should come before (which is possibly the
+       head). */
+    ticker_event_t *prev = NULL, *p = head;
+    while (p != NULL) {
+        /* check if we come before p */
+        if ((int)(timestamp - p->timestamp) <= 0) {
+            break;
+        }
+        /* go to the next element */
+        prev = p;
+        p = p->next;
+    }
+    /* if prev is NULL we're at the head */
+    if (prev == NULL) {
+        head = obj;
+        us_ticker_set_interrupt(timestamp);
+    } else {
+        prev->next = obj;
+    }
+    /* if we're at the end p will be NULL, which is correct */
+    obj->next = p;
+
+    __enable_irq();
+}
+
+void us_ticker_remove_event(ticker_event_t *obj) {
+    __disable_irq();
+
+    // remove this object from the list
+    if (head == obj) {
+        // first in the list, so just drop me
+        head = obj->next;
+        if (obj->next != NULL) {
+            us_ticker_set_interrupt(head->timestamp);
+        }
+    } else {
+        // find the object before me, then drop me
+        ticker_event_t* p = head;
+        while (p != NULL) {
+            if (p->next == obj) {
+                p->next = obj->next;
+                break;
+            }
+            p = p->next;
+        }
+    }
+
+    __enable_irq();
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/common/wait_api.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "wait_api.h"
+#include "us_ticker_api.h"
+
+void wait(float s) {
+    wait_us(s * 1000000.0f);
+}
+
+void wait_ms(int ms) {
+    wait_us(ms * 1000);
+}
+
+void wait_us(int us) {
+    uint32_t start = us_ticker_read();
+    while ((us_ticker_read() - start) < (uint32_t)us);
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/hal/analogin_api.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGIN_API_H
+#define MBED_ANALOGIN_API_H
+
+#include "device.h"
+
+#if DEVICE_ANALOGIN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct analogin_s analogin_t;
+
+void     analogin_init    (analogin_t *obj, PinName pin);
+float    analogin_read    (analogin_t *obj);
+uint16_t analogin_read_u16(analogin_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/hal/analogout_api.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,43 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGOUT_API_H
+#define MBED_ANALOGOUT_API_H
+
+#include "device.h"
+
+#if DEVICE_ANALOGOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct dac_s dac_t;
+
+void     analogout_init     (dac_t *obj, PinName pin);
+void     analogout_free     (dac_t *obj);
+void     analogout_write    (dac_t *obj, float value);
+void     analogout_write_u16(dac_t *obj, uint16_t value);
+float    analogout_read     (dac_t *obj);
+uint16_t analogout_read_u16 (dac_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/hal/can_api.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,81 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_API_H
+#define MBED_CAN_API_H
+
+#include "device.h"
+
+#if DEVICE_CAN
+
+#include "PinNames.h"
+#include "PeripheralNames.h"
+#include "can_helper.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    IRQ_RX,
+    IRQ_TX,
+    IRQ_ERROR,
+    IRQ_OVERRUN,
+    IRQ_WAKEUP,
+    IRQ_PASSIVE,
+    IRQ_ARB,
+    IRQ_BUS,
+    IRQ_READY
+} CanIrqType;
+
+
+typedef enum {
+    MODE_RESET,
+    MODE_NORMAL,
+    MODE_SILENT,
+    MODE_TEST_GLOBAL,
+    MODE_TEST_LOCAL,
+    MODE_TEST_SILENT
+} CanMode;
+
+typedef void (*can_irq_handler)(uint32_t id, CanIrqType type);
+
+typedef struct can_s can_t;
+
+void          can_init     (can_t *obj, PinName rd, PinName td);
+void          can_free     (can_t *obj);
+int           can_frequency(can_t *obj, int hz);
+
+void          can_irq_init (can_t *obj, can_irq_handler handler, uint32_t id);
+void          can_irq_free (can_t *obj);
+void          can_irq_set  (can_t *obj, CanIrqType irq, uint32_t enable);
+
+int           can_write    (can_t *obj, CAN_Message, int cc);
+int           can_read     (can_t *obj, CAN_Message *msg, int handle);
+int           can_mode     (can_t *obj, CanMode mode);
+int           can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle);
+void          can_reset    (can_t *obj);
+unsigned char can_rderror  (can_t *obj);
+unsigned char can_tderror  (can_t *obj);
+void          can_monitor  (can_t *obj, int silent);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif    // MBED_CAN_API_H
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/hal/ethernet_api.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ETHERNET_API_H
+#define MBED_ETHERNET_API_H
+
+#include "device.h"
+
+#if DEVICE_ETHERNET
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Connection constants
+
+int ethernet_init(void);
+void ethernet_free(void);
+
+// write size bytes from data to ethernet buffer
+// return num bytes written
+// or -1 if size is too big
+int ethernet_write(const char *data, int size);
+
+// send ethernet write buffer, returning the packet size sent
+int ethernet_send(void);
+
+// recieve from ethernet buffer, returning packet size, or 0 if no packet
+int ethernet_receive(void);
+
+// read size bytes in to data, return actual num bytes read (0..size)
+// if data == NULL, throw the bytes away
+int ethernet_read(char *data, int size);
+
+// get the ethernet address
+void ethernet_address(char *mac);
+
+// see if the link is up
+int ethernet_link(void);
+
+// force link settings
+void ethernet_set_link(int speed, int duplex);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/hal/gpio_api.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_API_H
+#define MBED_GPIO_API_H
+
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Set the given pin as GPIO
+ * @param pin The pin to be set as GPIO
+ * @return The GPIO port mask for this pin
+ **/
+uint32_t gpio_set(PinName pin);
+
+/* GPIO object */
+void gpio_init(gpio_t *obj, PinName pin);
+
+void gpio_mode (gpio_t *obj, PinMode mode);
+void gpio_dir  (gpio_t *obj, PinDirection direction);
+
+void gpio_write(gpio_t *obj, int value);
+int  gpio_read (gpio_t *obj);
+
+// the following set of functions are generic and are implemented in the common gpio.c file
+void gpio_init_in(gpio_t* gpio, PinName pin);
+void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode);
+void gpio_init_out(gpio_t* gpio, PinName pin);
+void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value);
+void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/hal/gpio_irq_api.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,50 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_IRQ_API_H
+#define MBED_GPIO_IRQ_API_H
+
+#include "device.h"
+
+#if DEVICE_INTERRUPTIN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    IRQ_NONE,
+    IRQ_RISE,
+    IRQ_FALL
+} gpio_irq_event;
+
+typedef struct gpio_irq_s gpio_irq_t;
+
+typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
+
+int  gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id);
+void gpio_irq_free(gpio_irq_t *obj);
+void gpio_irq_set (gpio_irq_t *obj, gpio_irq_event event, uint32_t enable);
+void gpio_irq_enable(gpio_irq_t *obj);
+void gpio_irq_disable(gpio_irq_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/hal/i2c_api.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_API_H
+#define MBED_I2C_API_H
+
+#include "device.h"
+
+#if DEVICE_I2C
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct i2c_s i2c_t;
+
+enum {
+  I2C_ERROR_NO_SLAVE = -1,
+  I2C_ERROR_BUS_BUSY = -2
+};
+
+void i2c_init         (i2c_t *obj, PinName sda, PinName scl);
+void i2c_frequency    (i2c_t *obj, int hz);
+int  i2c_start        (i2c_t *obj);
+int  i2c_stop         (i2c_t *obj);
+int  i2c_read         (i2c_t *obj, int address, char *data, int length, int stop);
+int  i2c_write        (i2c_t *obj, int address, const char *data, int length, int stop);
+void i2c_reset        (i2c_t *obj);
+int  i2c_byte_read    (i2c_t *obj, int last);
+int  i2c_byte_write   (i2c_t *obj, int data);
+
+#if DEVICE_I2CSLAVE
+void i2c_slave_mode   (i2c_t *obj, int enable_slave);
+int  i2c_slave_receive(i2c_t *obj);
+int  i2c_slave_read   (i2c_t *obj, char *data, int length);
+int  i2c_slave_write  (i2c_t *obj, const char *data, int length);
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/hal/pinmap.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,44 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINMAP_H
+#define MBED_PINMAP_H
+
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName pin;
+    int peripheral;
+    int function;
+} PinMap;
+
+void pin_function(PinName pin, int function);
+void pin_mode    (PinName pin, PinMode mode);
+
+uint32_t pinmap_peripheral(PinName pin, const PinMap* map);
+uint32_t pinmap_merge     (uint32_t a, uint32_t b);
+void     pinmap_pinout    (PinName pin, const PinMap *map);
+uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/hal/port_api.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,43 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTMAP_H
+#define MBED_PORTMAP_H
+
+#include "device.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct port_s port_t;
+
+PinName port_pin(PortName port, int pin_n);
+
+void port_init (port_t *obj, PortName port, int mask, PinDirection dir);
+void port_mode (port_t *obj, PinMode mode);
+void port_dir  (port_t *obj, PinDirection dir);
+void port_write(port_t *obj, int value);
+int  port_read (port_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/hal/pwmout_api.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,50 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PWMOUT_API_H
+#define MBED_PWMOUT_API_H
+
+#include "device.h"
+
+#if DEVICE_PWMOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct pwmout_s pwmout_t;
+
+void pwmout_init         (pwmout_t* obj, PinName pin);
+void pwmout_free         (pwmout_t* obj);
+
+void  pwmout_write       (pwmout_t* obj, float percent);
+float pwmout_read        (pwmout_t* obj);
+
+void pwmout_period       (pwmout_t* obj, float seconds);
+void pwmout_period_ms    (pwmout_t* obj, int ms);
+void pwmout_period_us    (pwmout_t* obj, int us);
+
+void pwmout_pulsewidth   (pwmout_t* obj, float seconds);
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms);
+void pwmout_pulsewidth_us(pwmout_t* obj, int us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/hal/rtc_api.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,43 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_RTC_API_H
+#define MBED_RTC_API_H
+
+#include "device.h"
+
+#if DEVICE_RTC
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void rtc_init(void);
+void rtc_free(void);
+int rtc_isenabled(void);
+
+time_t rtc_read(void);
+void rtc_write(time_t t);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/hal/serial_api.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,79 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_API_H
+#define MBED_SERIAL_API_H
+
+#include "device.h"
+
+#if DEVICE_SERIAL
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ParityNone = 0,
+    ParityOdd = 1,
+    ParityEven = 2,
+    ParityForced1 = 3,
+    ParityForced0 = 4
+} SerialParity;
+
+typedef enum {
+    RxIrq,
+    TxIrq
+} SerialIrq;
+
+typedef enum {
+    FlowControlNone,
+    FlowControlRTS,
+    FlowControlCTS,
+    FlowControlRTSCTS
+} FlowControl;
+
+typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
+
+typedef struct serial_s serial_t;
+
+void serial_init       (serial_t *obj, PinName tx, PinName rx);
+void serial_free       (serial_t *obj);
+void serial_baud       (serial_t *obj, int baudrate);
+void serial_format     (serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id);
+void serial_irq_set    (serial_t *obj, SerialIrq irq, uint32_t enable);
+
+int  serial_getc       (serial_t *obj);
+void serial_putc       (serial_t *obj, int c);
+int  serial_readable   (serial_t *obj);
+int  serial_writable   (serial_t *obj);
+void serial_clear      (serial_t *obj);
+
+void serial_break_set  (serial_t *obj);
+void serial_break_clear(serial_t *obj);
+
+void serial_pinout_tx(PinName tx);
+
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/hal/sleep_api.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,65 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SLEEP_API_H
+#define MBED_SLEEP_API_H
+
+#include "device.h"
+
+#if DEVICE_SLEEP
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Send the microcontroller to sleep
+ *
+ * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
+ * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
+ * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
+ * memory state are maintained, and the peripherals continue to work and can generate interrupts.
+ *
+ * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
+ *
+ * @note
+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+void sleep(void);
+
+/** Send the microcontroller to deep sleep
+ *
+ * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
+ * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
+ * is still maintained.
+ *
+ * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
+ *
+ * @note
+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+void deepsleep(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/hal/spi_api.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPI_API_H
+#define MBED_SPI_API_H
+
+#include "device.h"
+
+#if DEVICE_SPI
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct spi_s spi_t;
+
+void spi_init         (spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
+void spi_free         (spi_t *obj);
+void spi_format       (spi_t *obj, int bits, int mode, int slave);
+void spi_frequency    (spi_t *obj, int hz);
+int  spi_master_write (spi_t *obj, int value);
+int  spi_slave_receive(spi_t *obj);
+int  spi_slave_read   (spi_t *obj);
+void spi_slave_write  (spi_t *obj, int value);
+int  spi_busy         (spi_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/hal/us_ticker_api.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,50 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_US_TICKER_API_H
+#define MBED_US_TICKER_API_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+uint32_t us_ticker_read(void);
+
+typedef void (*ticker_event_handler)(uint32_t id);
+void us_ticker_set_handler(ticker_event_handler handler);
+
+typedef struct ticker_event_s {
+    uint32_t timestamp;
+    uint32_t id;
+    struct ticker_event_s *next;
+} ticker_event_t;
+
+void us_ticker_init(void);
+void us_ticker_set_interrupt(unsigned int timestamp);
+void us_ticker_disable_interrupt(void);
+void us_ticker_clear_interrupt(void);
+void us_ticker_irq_handler(void);
+
+void us_ticker_insert_event(ticker_event_t *obj, unsigned int timestamp, uint32_t id);
+void us_ticker_remove_event(ticker_event_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/startup_stm32f401xe.s	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,369 @@
+;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name          : startup_stm32f401xe.s
+;* Author             : MCD Application Team
+;* Version            : V2.1.0RC2
+;* Date               : 14-May-2014
+;* Description        : STM32F401xe devices vector table for MDK-ARM_MICRO toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+                
+Stack_Mem       SPACE   Stack_Size
+__initial_sp    EQU     0x20018000 ; Top of RAM
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000400
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+                DCD     0                                 ; Reserved                                                
+                DCD     0                                 ; Reserved                                               
+                DCD     0                                 ; Reserved                                             
+                DCD     0                                 ; Reserved                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+                DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     0                                 ; Reserved                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+                DCD     0                                 ; Reserved                  
+                DCD     0                                 ; Reserved                 
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved                                   
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     0                                 ; Reserved                                             
+                DCD     SDIO_IRQHandler                   ; SDIO                                            
+                DCD     TIM5_IRQHandler                   ; TIM5                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     0                                 ; Reserved                                           
+                DCD     0                                 ; Reserved                                           
+                DCD     0                                 ; Reserved                   
+                DCD     0                                 ; Reserved                   
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
+                DCD     0                                 ; Reserved  
+                DCD     0                                 ; Reserved  
+                DCD     0                                 ; Reserved                                              
+                DCD     0                                 ; Reserved                                               
+                DCD     0                                 ; Reserved                                               
+                DCD     0                                 ; Reserved                                               
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+                DCD     USART6_IRQHandler                 ; USART6                                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+                DCD     0                                 ; Reserved                     
+                DCD     0                                 ; Reserved                       
+                DCD     0                                 ; Reserved                         
+                DCD     0                                 ; Reserved                                    
+                DCD     0                                 ; Reserved  
+                DCD     0                                 ; Reserved				                              
+                DCD     0                                 ; Reserved
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     0                                 ; Reserved
+		DCD     0                                 ; Reserved
+		DCD     SPI4_IRQHandler                   ; SPI4
+                                         
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]                                
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  ADC_IRQHandler                    [WEAK]                                                                        
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_TIM9_IRQHandler          [WEAK]                  
+                EXPORT  TIM1_UP_TIM10_IRQHandler          [WEAK]                
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler     [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                                                                  
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                                                                     
+                EXPORT  SDIO_IRQHandler                   [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                                               
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                                                                                     
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                                       
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  FPU_IRQHandler                    [WEAK]
+				EXPORT  SPI4_IRQHandler                   [WEAK]
+                
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMP_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Stream0_IRQHandler                                       
+DMA1_Stream1_IRQHandler                                          
+DMA1_Stream2_IRQHandler                                          
+DMA1_Stream3_IRQHandler                                          
+DMA1_Stream4_IRQHandler                                          
+DMA1_Stream5_IRQHandler                                          
+DMA1_Stream6_IRQHandler                                          
+ADC_IRQHandler                                                                                                    
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_TIM9_IRQHandler                        
+TIM1_UP_TIM10_IRQHandler                      
+TIM1_TRG_COM_TIM11_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                                                                           
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+OTG_FS_WKUP_IRQHandler                                                                           
+DMA1_Stream7_IRQHandler                                                                                                             
+SDIO_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                                                     
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                                                                                                                  
+OTG_FS_IRQHandler                                                    
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+FPU_IRQHandler
+SPI4_IRQHandler
+           
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f401xe.sct	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,46 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F401RE: 512KB FLASH + 96KB SRAM
+LR_IROM1 0x08000000 0x80000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x80000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x194) (0x18000-0x194)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/sys.cpp	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model, 
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32f4xx.h"
+#include "cmsis_nvic.h"
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */ 
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS   (0x20000000)  // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000)  // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    uint32_t *vectors = (uint32_t *)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+        for (i=0; i<NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/cmsis_nvic.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */ 
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32F401RE
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 85 vectors = 340 bytes from 0x40 to ...
+// Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM
+#define NVIC_NUM_VECTORS      101
+#define NVIC_USER_IRQ_OFFSET  16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/hal_tick.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,121 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.c
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#include "hal_tick.h"
+
+TIM_HandleTypeDef TimMasterHandle;
+uint32_t PreviousVal = 0;
+
+void us_ticker_irq_handler(void);
+
+void timer_irq_handler(void) {
+    // Channel 1 for mbed timeout
+    if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
+        __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
+        us_ticker_irq_handler();
+    }
+
+    // Channel 2 for HAL tick
+    if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
+        __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
+        uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
+        if ((val - PreviousVal) >= HAL_TICK_DELAY) {
+            // Increment HAL variable
+            HAL_IncTick();
+            // Prepare next interrupt
+            __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
+            PreviousVal = val;
+#if 0 // For DEBUG only
+            HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
+#endif
+        }
+    }
+}
+
+// Reconfigure the HAL tick using a standard timer instead of systick.
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+    // Enable timer clock
+    TIM_MST_RCC;
+
+    // Reset timer
+    TIM_MST_RESET_ON;
+    TIM_MST_RESET_OFF;
+  
+    // Configure time base
+    TimMasterHandle.Instance = TIM_MST;
+    TimMasterHandle.Init.Period            = 0xFFFFFFFF;
+    TimMasterHandle.Init.Prescaler         = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
+    TimMasterHandle.Init.ClockDivision     = 0;
+    TimMasterHandle.Init.CounterMode       = TIM_COUNTERMODE_UP;
+    TimMasterHandle.Init.RepetitionCounter = 0;
+    HAL_TIM_OC_Init(&TimMasterHandle);
+
+    NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+    NVIC_EnableIRQ(TIM_MST_IRQ);
+
+    // Channel 1 for mbed timeout
+    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+    // Channel 2 for HAL tick
+    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
+    PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
+    __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
+    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+
+#if 0 // For DEBUG only
+    __GPIOB_CLK_ENABLE();
+    GPIO_InitTypeDef GPIO_InitStruct;
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#endif
+
+    return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/hal_tick.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,61 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.h
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "cmsis_nvic.h"
+   
+#define TIM_MST      TIM5
+#define TIM_MST_IRQ  TIM5_IRQn
+#define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f401xe.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,4752 @@
+/**
+  ******************************************************************************
+  * @file    stm32f401xe.h
+  * @author  MCD Application Team
+  * @version V2.1.0RC2
+  * @date    14-May-2014
+  * @brief   CMSIS STM32F401xExx Device Peripheral Access Layer Header File. 
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f401xe
+  * @{
+  */
+    
+#ifndef __STM32F401xE_H
+#define __STM32F401xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
+  */
+#define __CM4_REV                 0x0001  /*!< Core revision r0p1                            */
+#define __MPU_PRESENT             1       /*!< STM32F4XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1       /*!< FPU present                                   */
+
+/**
+  * @}
+  */
+   
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+typedef enum
+{
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
+  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */  
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
+  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
+  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
+  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
+  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  FPU_IRQn                    = 81,      /*!< FPU global interrupt                                             */
+  SPI4_IRQn                   = 84       /*!< SPI4 global Interrupt                                            */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
+  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
+  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
+  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
+  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
+  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
+  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
+  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
+  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
+  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
+  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
+  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
+  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
+  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
+  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
+  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
+  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
+                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
+  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
+  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
+  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
+} CRC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
+  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
+  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
+  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
+  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
+  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
+  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
+  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
+  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
+  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
+  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
+  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/** 
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint16_t BSRRL;    /*!< GPIO port bit set/reset low register,  Address offset: 0x18      */
+  __IO uint16_t BSRRH;    /*!< GPIO port bit set/reset high register, Address offset: 0x1A      */
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/** 
+  * @brief System configuration controller
+  */
+  
+typedef struct
+{
+  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
+  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
+} SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
+  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
+  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
+  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
+  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
+  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
+  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
+  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
+  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
+} I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/** 
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
+  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
+  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
+  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
+  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
+  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
+  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
+  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
+  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
+  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
+  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
+  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
+  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
+  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
+  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
+  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
+  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
+  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
+  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
+  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
+  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
+
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
+  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
+  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
+  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
+  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
+  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
+  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
+  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
+  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
+  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
+  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
+  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
+  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
+  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
+  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
+  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
+  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
+  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
+  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
+  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
+  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
+  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
+  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
+  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
+  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
+  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
+  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
+  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
+  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
+  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
+  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
+  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
+  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
+  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
+  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
+  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
+  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
+  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
+} RTC_TypeDef;
+
+
+/** 
+  * @brief SD host Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
+  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
+  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
+  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
+  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
+  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
+  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
+} SPI_TypeDef;
+
+/** 
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
+} TIM_TypeDef;
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+ 
+typedef struct
+{
+  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
+  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
+  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
+  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
+  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
+  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/** 
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/** 
+  * @brief __USB_OTG_Core_register
+  */
+typedef struct
+{
+  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register    Address offset : 0x00      */
+  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register             Address offset : 0x04      */
+  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register        Address offset : 0x08      */
+  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register        Address offset : 0x0C      */
+  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                    Address offset : 0x10      */
+  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                Address offset : 0x14      */
+  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register           Address offset : 0x18      */
+  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register            Address offset : 0x1C      */
+  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register      Address offset : 0x20      */
+  __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                Address offset : 0x24      */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28    */
+  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg     Address offset : 0x2C      */
+  uint32_t Reserved30[2];             /* Reserved                                  Address offset : 0x30      */
+  __IO uint32_t GCCFG;                /*!<  General Purpose IO Register            Address offset : 0x38      */
+  __IO uint32_t CID;                  /*!< User ID Register                          Address offset : 0x3C      */
+  uint32_t  Reserved40[48];           /*!< Reserved                                  Address offset : 0x40-0xFF */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg            Address offset : 0x100 */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
+}
+USB_OTG_GlobalTypeDef;
+
+
+
+/** 
+  * @brief __device_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DCFG;         /*!< dev Configuration Register   Address offset : 0x800 */
+  __IO uint32_t DCTL;         /*!< dev Control Register         Address offset : 0x804 */
+  __IO uint32_t DSTS;         /*!< dev Status Register (RO)     Address offset : 0x808 */
+  uint32_t Reserved0C;        /*!< Reserved                     Address offset : 0x80C */
+  __IO uint32_t DIEPMSK;      /* !< dev IN Endpoint Mask        Address offset : 0x810 */
+  __IO uint32_t DOEPMSK;      /*!< dev OUT Endpoint Mask        Address offset : 0x814 */
+  __IO uint32_t DAINT;        /*!< dev All Endpoints Itr Reg    Address offset : 0x818 */
+  __IO uint32_t DAINTMSK;     /*!< dev All Endpoints Itr Mask   Address offset : 0x81C */
+  uint32_t  Reserved20;       /*!< Reserved                     Address offset : 0x820 */
+  uint32_t Reserved9;         /*!< Reserved                     Address offset : 0x824 */
+  __IO uint32_t DVBUSDIS;     /*!< dev VBUS discharge Register  Address offset : 0x828 */
+  __IO uint32_t DVBUSPULSE;   /*!< dev VBUS Pulse Register      Address offset : 0x82C */
+  __IO uint32_t DTHRCTL;      /*!< dev thr                      Address offset : 0x830 */
+  __IO uint32_t DIEPEMPMSK;   /*!< dev empty msk                Address offset : 0x834 */
+  __IO uint32_t DEACHINT;     /*!< dedicated EP interrupt       Address offset : 0x838 */
+  __IO uint32_t DEACHMSK;     /*!< dedicated EP msk             Address offset : 0x83C */  
+  uint32_t Reserved40;        /*!< dedicated EP mask            Address offset : 0x840 */
+  __IO uint32_t DINEP1MSK;    /*!< dedicated EP mask            Address offset : 0x844 */
+  uint32_t  Reserved44[15];   /*!< Reserved                     Address offset : 0x844-0x87C */
+  __IO uint32_t DOUTEP1MSK;   /*!< dedicated EP msk             Address offset : 0x884 */   
+}
+USB_OTG_DeviceTypeDef;
+
+
+/** 
+  * @brief __IN_Endpoint-Specific_Register
+  */
+typedef struct 
+{
+  __IO uint32_t DIEPCTL;        /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h     */
+  uint32_t Reserved04;          /* Reserved                       900h + (ep_num * 20h) + 04h  */
+  __IO uint32_t DIEPINT;        /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h     */
+  uint32_t Reserved0C;          /* Reserved                       900h + (ep_num * 20h) + 0Ch  */
+  __IO uint32_t DIEPTSIZ;       /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h        */
+  __IO uint32_t DIEPDMA;        /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h  */
+  __IO uint32_t DTXFSTS;        /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h   */
+  uint32_t Reserved18;           /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+}
+USB_OTG_INEndpointTypeDef;
+
+
+/** 
+  * @brief __OUT_Endpoint-Specific_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DOEPCTL;       /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
+  uint32_t Reserved04;         /* Reserved                      B00h + (ep_num * 20h) + 04h*/
+  __IO uint32_t DOEPINT;       /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
+  uint32_t Reserved0C;         /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
+  __IO uint32_t DOEPTSIZ;      /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
+  __IO uint32_t DOEPDMA;       /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
+  uint32_t Reserved18[2];      /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_OUTEndpointTypeDef;
+
+
+/** 
+  * @brief __Host_Mode_Register_Structures
+  */
+typedef struct 
+{
+  __IO uint32_t HCFG;             /* Host Configuration Register    400h*/
+  __IO uint32_t HFIR;             /* Host Frame Interval Register   404h*/
+  __IO uint32_t HFNUM;            /* Host Frame Nbr/Frame Remaining 408h*/
+  uint32_t Reserved40C;           /* Reserved                       40Ch*/
+  __IO uint32_t HPTXSTS;          /* Host Periodic Tx FIFO/ Queue Status 410h*/
+  __IO uint32_t HAINT;            /* Host All Channels Interrupt Register 414h*/
+  __IO uint32_t HAINTMSK;         /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HostTypeDef;
+
+
+/** 
+  * @brief __Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;
+  __IO uint32_t HCSPLT;
+  __IO uint32_t HCINT;
+  __IO uint32_t HCINTMSK;
+  __IO uint32_t HCTSIZ;
+  __IO uint32_t HCDMA;
+  uint32_t Reserved[2];
+}
+USB_OTG_HostChannelTypeDef;
+
+    
+/** 
+  * @brief Peripheral_memory_map
+  */
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define CCMDATARAM_BASE       ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
+#define SRAM1_BASE            ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region                             */
+#define SRAM2_BASE            ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region                              */
+#define SRAM3_BASE            ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region                              */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define CCMDATARAM_BB_BASE    ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region  */
+#define SRAM1_BB_BASE         ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region                             */
+#define SRAM2_BB_BASE         ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region                              */
+#define SRAM3_BB_BASE         ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region                              */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region                                */
+#define BKPSRAM_BB_BASE       ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */
+
+/* Legacy defines */
+#define SRAM_BASE             SRAM1_BASE
+#define SRAM_BB_BASE          SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
+#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
+#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
+#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
+#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00)
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           ((uint32_t )0xE0042000)
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000)
+
+#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000)
+#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800)
+#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900)
+#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00)
+#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20)
+#define USB_OTG_HOST_BASE                    ((uint32_t )0x400)
+#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440)
+#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500)
+#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20)
+#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00)
+#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000)
+#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000)
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4                ((SPI_TypeDef *) SPI4_BASE) 
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+  
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for ADC_SR register  ********************/
+#define  ADC_SR_AWD                          ((uint32_t)0x00000001)       /*!<Analog watchdog flag */
+#define  ADC_SR_EOC                          ((uint32_t)0x00000002)       /*!<End of conversion */
+#define  ADC_SR_JEOC                         ((uint32_t)0x00000004)       /*!<Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008)       /*!<Injected channel Start flag */
+#define  ADC_SR_STRT                         ((uint32_t)0x00000010)       /*!<Regular channel Start flag */
+#define  ADC_SR_OVR                          ((uint32_t)0x00000020)       /*!<Overrun flag */
+
+/*******************  Bit definition for ADC_CR1 register  ********************/
+#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!<Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!<AAnalog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!<Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!<Scan mode */
+#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!<Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!<Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!<Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!<Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!<Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!<Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!<Bit 2 */
+#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!<Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!<Analog watchdog enable on regular channels */
+#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!<RES[2:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)         /*!<overrun interrupt enable */
+  
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!<A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!<Continuous Conversion */
+#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!<Direct Memory access mode */
+#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!<DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!<End of conversion selection */
+#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!<Data Alignment */
+#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!<Bit 3 */
+#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!<Start Conversion of injected channels */
+#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!<Bit 3 */
+#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!<Bit 0 */
+#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!<Bit 1 */
+#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!<Start Conversion of regular channels */
+
+/******************  Bit definition for ADC_SMPR1 register  *******************/
+#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!<Bit 2 */
+#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */
+
+/******************  Bit definition for ADC_SMPR2 register  *******************/
+#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!<Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!<Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!<Bit 2 */
+
+/******************  Bit definition for ADC_JOFR1 register  *******************/
+#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFR2 register  *******************/
+#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFR3 register  *******************/
+#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFR4 register  *******************/
+#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x0FFF)            /*!<Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define  ADC_HTR_HT                          ((uint32_t)0x0FFF)            /*!<Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define  ADC_LTR_LT                          ((uint32_t)0x0FFF)            /*!<Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_SQR1 register  *******************/
+#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
+#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
+#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
+#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
+#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!<L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!<Bit 3 */
+
+/*******************  Bit definition for ADC_SQR2 register  *******************/
+#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!<Bit 4 */
+#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!<Bit 0 */
+#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!<Bit 1 */
+#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!<Bit 2 */
+#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!<Bit 3 */
+#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!<Bit 4 */
+
+/*******************  Bit definition for ADC_SQR3 register  *******************/
+#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!<Bit 4 */
+#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!<Bit 0 */
+#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!<Bit 1 */
+#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!<Bit 2 */
+#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!<Bit 3 */
+#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!<Bit 4 */
+
+/*******************  Bit definition for ADC_JSQR register  *******************/
+#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */
+#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */
+#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!<JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!<Bit 0 */
+#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!<Bit 1 */
+
+/*******************  Bit definition for ADC_JDR1 register  *******************/
+#define  ADC_JDR1_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR2 register  *******************/
+#define  ADC_JDR2_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR3 register  *******************/
+#define  ADC_JDR3_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR4 register  *******************/
+#define  ADC_JDR4_JDATA                      ((uint32_t)0xFFFF)            /*!<Injected data */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!<Regular data */
+#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!<ADC2 data */
+
+/*******************  Bit definition for ADC_CSR register  ********************/
+#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!<ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!<ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!<ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!<ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!<ADC1 Regular channel Start flag */
+#define  ADC_CSR_DOVR1                       ((uint32_t)0x00000020)        /*!<ADC1 DMA overrun  flag */
+#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100)        /*!<ADC2 Analog watchdog flag */
+#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200)        /*!<ADC2 End of conversion */
+#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400)        /*!<ADC2 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800)        /*!<ADC2 Injected channel Start flag */
+#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000)        /*!<ADC2 Regular channel Start flag */
+#define  ADC_CSR_DOVR2                       ((uint32_t)0x00002000)        /*!<ADC2 DMA overrun  flag */
+#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000)        /*!<ADC3 Analog watchdog flag */
+#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000)        /*!<ADC3 End of conversion */
+#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000)        /*!<ADC3 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000)        /*!<ADC3 Injected channel Start flag */
+#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000)        /*!<ADC3 Regular channel Start flag */
+#define  ADC_CSR_DOVR3                       ((uint32_t)0x00200000)        /*!<ADC3 DMA overrun  flag */
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001F)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */
+#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */
+#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */
+#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */
+#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */
+#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800)        /*!<Bit 3 */
+#define  ADC_CCR_DDS                         ((uint32_t)0x00002000)        /*!<DMA disable selection (Multi-ADC mode) */
+#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000)        /*!<Bit 0 */
+#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000)        /*!<Bit 1 */
+#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */
+#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000)        /*!<VBAT Enable */
+#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!<Temperature Sensor and VREFINT Enable */
+
+/*******************  Bit definition for ADC_CDR register  ********************/
+#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFF)         /*!<1st data of a pair of regular conversions */
+#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000)         /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint32_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint32_t)0x01)        /*!< RESET bit */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMA_SxCR register  *****************/ 
+#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000)
+#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000)
+#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000)
+#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000) 
+#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000)
+#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000)
+#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000)
+#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000)
+#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000)
+#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000)
+#define DMA_SxCR_ACK                         ((uint32_t)0x00100000)
+#define DMA_SxCR_CT                          ((uint32_t)0x00080000)  
+#define DMA_SxCR_DBM                         ((uint32_t)0x00040000)
+#define DMA_SxCR_PL                          ((uint32_t)0x00030000)
+#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000)
+#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000)
+#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000)
+#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000)
+#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000)
+#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000)
+#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800)
+#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800)
+#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000)
+#define DMA_SxCR_MINC                        ((uint32_t)0x00000400)
+#define DMA_SxCR_PINC                        ((uint32_t)0x00000200)
+#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100)
+#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0)
+#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040)
+#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080)
+#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020)
+#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010)
+#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008)
+#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004)
+#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002)
+#define DMA_SxCR_EN                          ((uint32_t)0x00000001)
+
+/********************  Bits definition for DMA_SxCNDTR register  **************/
+#define DMA_SxNDT                            ((uint32_t)0x0000FFFF)
+#define DMA_SxNDT_0                          ((uint32_t)0x00000001)
+#define DMA_SxNDT_1                          ((uint32_t)0x00000002)
+#define DMA_SxNDT_2                          ((uint32_t)0x00000004)
+#define DMA_SxNDT_3                          ((uint32_t)0x00000008)
+#define DMA_SxNDT_4                          ((uint32_t)0x00000010)
+#define DMA_SxNDT_5                          ((uint32_t)0x00000020)
+#define DMA_SxNDT_6                          ((uint32_t)0x00000040)
+#define DMA_SxNDT_7                          ((uint32_t)0x00000080)
+#define DMA_SxNDT_8                          ((uint32_t)0x00000100)
+#define DMA_SxNDT_9                          ((uint32_t)0x00000200)
+#define DMA_SxNDT_10                         ((uint32_t)0x00000400)
+#define DMA_SxNDT_11                         ((uint32_t)0x00000800)
+#define DMA_SxNDT_12                         ((uint32_t)0x00001000)
+#define DMA_SxNDT_13                         ((uint32_t)0x00002000)
+#define DMA_SxNDT_14                         ((uint32_t)0x00004000)
+#define DMA_SxNDT_15                         ((uint32_t)0x00008000)
+
+/********************  Bits definition for DMA_SxFCR register  ****************/ 
+#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080)
+#define DMA_SxFCR_FS                         ((uint32_t)0x00000038)
+#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008)
+#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010)
+#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020)
+#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004)
+#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003)
+#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001)
+#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002)
+
+/********************  Bits definition for DMA_LISR register  *****************/ 
+#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000)
+#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000)
+#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000)
+#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000)
+#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000)
+#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000)
+#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000)
+#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000)
+#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000)
+#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000)
+#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800)
+#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400)
+#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200)
+#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100)
+#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040)
+#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020)
+#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010)
+#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008)
+#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004)
+#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for DMA_HISR register  *****************/ 
+#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000)
+#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000)
+#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000)
+#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000)
+#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000)
+#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000)
+#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000)
+#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000)
+#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000)
+#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000)
+#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800)
+#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400)
+#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200)
+#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100)
+#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040)
+#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020)
+#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010)
+#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008)
+#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004)
+#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for DMA_LIFCR register  ****************/ 
+#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000)
+#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000)
+#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000)
+#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000)
+#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000)
+#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000)
+#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000)
+#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000)
+#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000)
+#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000)
+#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800)
+#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400)
+#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200)
+#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100)
+#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040)
+#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020)
+#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010)
+#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008)
+#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004)
+#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001)
+
+/********************  Bits definition for DMA_HIFCR  register  ****************/ 
+#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000)
+#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000)
+#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000)
+#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000)
+#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000)
+#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000)
+#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000)
+#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000)
+#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000)
+#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000)
+#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800)
+#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400)
+#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200)
+#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100)
+#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040)
+#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020)
+#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010)
+#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008)
+#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004)
+#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001)
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for FLASH_ACR register  *****************/
+#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000F)
+#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000)
+#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001)
+#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002)
+#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003)
+#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004)
+#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005)
+#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006)
+#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007)
+
+#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100)
+#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200)
+#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400)
+#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800)
+#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000)
+#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00)
+#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03)
+
+/*******************  Bits definition for FLASH_SR register  ******************/
+#define FLASH_SR_EOP                         ((uint32_t)0x00000001)
+#define FLASH_SR_SOP                         ((uint32_t)0x00000002)
+#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010)
+#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020)
+#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040)
+#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080)
+#define FLASH_SR_BSY                         ((uint32_t)0x00010000)
+
+/*******************  Bits definition for FLASH_CR register  ******************/
+#define FLASH_CR_PG                          ((uint32_t)0x00000001)
+#define FLASH_CR_SER                         ((uint32_t)0x00000002)
+#define FLASH_CR_MER                         ((uint32_t)0x00000004)
+#define FLASH_CR_SNB                         ((uint32_t)0x000000F8)
+#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008)
+#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010)
+#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020)
+#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040)
+#define FLASH_CR_SNB_4                       ((uint32_t)0x00000080)
+#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300)
+#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100)
+#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200)
+#define FLASH_CR_STRT                        ((uint32_t)0x00010000)
+#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000)
+#define FLASH_CR_LOCK                        ((uint32_t)0x80000000)
+
+/*******************  Bits definition for FLASH_OPTCR register  ***************/
+#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001)
+#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002)
+#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004)
+#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008)
+#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000C)
+
+#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020)
+#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040)
+#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080)
+#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00)
+#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100)
+#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200)
+#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400)
+#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800)
+#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000)
+#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000)
+#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000)
+#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000)
+#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000)
+#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000)
+#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000)
+#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000)
+#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000)
+#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000)
+#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000)
+#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000)
+#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000)
+#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000)
+#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000)
+#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000)
+                                             
+/******************  Bits definition for FLASH_OPTCR1 register  ***************/
+#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000)
+#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000)
+#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000)
+#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000)
+#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000)
+#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000)
+#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000)
+#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000)
+#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000)
+#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000)
+#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000)
+#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002)
+
+#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008)
+
+#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020)
+
+#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080)
+
+#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200)
+
+#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800)
+
+#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000)
+
+#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000)
+
+#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000)
+
+#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000)
+
+#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000)
+
+#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000)
+
+#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000)
+
+#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000)
+
+#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000)
+
+#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000)
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000)
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002)
+
+#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008)
+
+#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020)
+
+#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080)
+
+#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200)
+
+#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800)
+
+#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000)
+
+#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000)
+
+#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000)
+
+#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000)
+
+#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000)
+
+#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000)
+
+#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000)
+
+#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000)
+
+#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000)
+
+#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000)
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002)
+
+#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008)
+
+#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020)
+
+#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080)
+
+#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200)
+
+#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800)
+
+#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000)
+
+#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000)
+
+#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000)
+
+#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000)
+
+#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000)
+
+#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000)
+
+#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000)
+
+#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000)
+
+#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000)
+
+#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000)
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)
+#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)
+#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)
+#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)
+#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)
+#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)
+#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)
+#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)
+#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)
+#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)
+#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)
+#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)
+#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)
+#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)
+#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)
+#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)
+#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)
+#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)
+#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)
+#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)
+#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)
+#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)
+#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)
+#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)
+#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)
+#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)
+#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)
+#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)
+#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)
+#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)
+#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  ********************/
+#define  I2C_CR1_PE                          ((uint32_t)0x00000001)     /*!<Peripheral Enable                             */
+#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002)     /*!<SMBus Mode                                    */
+#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008)     /*!<SMBus Type                                    */
+#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010)     /*!<ARP Enable                                    */
+#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020)     /*!<PEC Enable                                    */
+#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040)     /*!<General Call Enable                           */
+#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080)     /*!<Clock Stretching Disable (Slave mode)  */
+#define  I2C_CR1_START                       ((uint32_t)0x00000100)     /*!<Start Generation                              */
+#define  I2C_CR1_STOP                        ((uint32_t)0x00000200)     /*!<Stop Generation                               */
+#define  I2C_CR1_ACK                         ((uint32_t)0x00000400)     /*!<Acknowledge Enable                            */
+#define  I2C_CR1_POS                         ((uint32_t)0x00000800)     /*!<Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         ((uint32_t)0x00001000)     /*!<Packet Error Checking                         */
+#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000)     /*!<SMBus Alert                                   */
+#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000)     /*!<Software Reset                                */
+
+/*******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003F)     /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001)     /*!<Bit 0 */
+#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002)     /*!<Bit 1 */
+#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004)     /*!<Bit 2 */
+#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008)     /*!<Bit 3 */
+#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010)     /*!<Bit 4 */
+#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020)     /*!<Bit 5 */
+
+#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100)     /*!<Error Interrupt Enable  */
+#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200)     /*!<Event Interrupt Enable  */
+#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400)     /*!<Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800)     /*!<DMA Requests Enable     */
+#define  I2C_CR2_LAST                        ((uint32_t)0x00001000)     /*!<DMA Last Transfer       */
+
+/*******************  Bit definition for I2C_OAR1 register  *******************/
+#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)     /*!<Interface Address */
+#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)     /*!<Interface Address */
+
+#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001)     /*!<Bit 0 */
+#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002)     /*!<Bit 1 */
+#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004)     /*!<Bit 2 */
+#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008)     /*!<Bit 3 */
+#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010)     /*!<Bit 4 */
+#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020)     /*!<Bit 5 */
+#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040)     /*!<Bit 6 */
+#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080)     /*!<Bit 7 */
+#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100)     /*!<Bit 8 */
+#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200)     /*!<Bit 9 */
+
+#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000)     /*!<Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OAR2 register  *******************/
+#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001)        /*!<Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FE)        /*!<Interface address           */
+
+/********************  Bit definition for I2C_DR register  ********************/
+#define  I2C_DR_DR                           ((uint32_t)0x000000FF)        /*!<8-bit Data Register         */
+
+/*******************  Bit definition for I2C_SR1 register  ********************/
+#define  I2C_SR1_SB                          ((uint32_t)0x00000001)     /*!<Start Bit (Master mode)                  */
+#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002)     /*!<Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         ((uint32_t)0x00000004)     /*!<Byte Transfer Finished                          */
+#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008)     /*!<10-bit header sent (Master mode)         */
+#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010)     /*!<Stop detection (Slave mode)              */
+#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040)     /*!<Data Register not Empty (receivers)      */
+#define  I2C_SR1_TXE                         ((uint32_t)0x00000080)     /*!<Data Register Empty (transmitters)       */
+#define  I2C_SR1_BERR                        ((uint32_t)0x00000100)     /*!<Bus Error                                       */
+#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200)     /*!<Arbitration Lost (master mode)           */
+#define  I2C_SR1_AF                          ((uint32_t)0x00000400)     /*!<Acknowledge Failure                             */
+#define  I2C_SR1_OVR                         ((uint32_t)0x00000800)     /*!<Overrun/Underrun                                */
+#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000)     /*!<PEC Error in reception                          */
+#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000)     /*!<Timeout or Tlow Error                           */
+#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000)     /*!<SMBus Alert                                     */
+
+/*******************  Bit definition for I2C_SR2 register  ********************/
+#define  I2C_SR2_MSL                         ((uint32_t)0x00000001)     /*!<Master/Slave                              */
+#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002)     /*!<Bus Busy                                  */
+#define  I2C_SR2_TRA                         ((uint32_t)0x00000004)     /*!<Transmitter/Receiver                      */
+#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010)     /*!<General Call Address (Slave mode)  */
+#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020)     /*!<SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040)     /*!<SMBus Host Header (Slave mode)     */
+#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080)     /*!<Dual Flag (Slave mode)             */
+#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00)     /*!<Packet Error Checking Register            */
+
+/*******************  Bit definition for I2C_CCR register  ********************/
+#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFF)     /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000)     /*!<Fast Mode Duty Cycle                                       */
+#define  I2C_CCR_FS                          ((uint32_t)0x00008000)     /*!<I2C Master Mode Selection                                  */
+
+/******************  Bit definition for I2C_TRISE register  *******************/
+#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003F)     /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************  Bit definition for I2C_FLTR register  *******************/
+#define  I2C_FLTR_DNF                        ((uint32_t)0x0000000F)     /*!<Digital Noise Filter */
+#define  I2C_FLTR_ANOFF                      ((uint32_t)0x00000010)     /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint32_t)0xFFFF)            /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint32_t)0x07)               /*!<PR[2:0] (Prescaler divider)         */
+#define  IWDG_PR_PR_0                        ((uint32_t)0x01)               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint32_t)0x02)               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint32_t)0x04)               /*!<Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint32_t)0x0FFF)            /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint32_t)0x01)               /*!<Watchdog prescaler value update      */
+#define  IWDG_SR_RVU                         ((uint32_t)0x02)               /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPDS                         ((uint32_t)0x00000001)     /*!< Low-Power Deepsleep                 */
+#define  PWR_CR_PDDS                         ((uint32_t)0x00000002)     /*!< Power Down Deepsleep                */
+#define  PWR_CR_CWUF                         ((uint32_t)0x00000004)     /*!< Clear Wakeup Flag                   */
+#define  PWR_CR_CSBF                         ((uint32_t)0x00000008)     /*!< Clear Standby Flag                  */
+#define  PWR_CR_PVDE                         ((uint32_t)0x00000010)     /*!< Power Voltage Detector Enable       */
+
+#define  PWR_CR_PLS                          ((uint32_t)0x000000E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080)     /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000)     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020)     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040)     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060)     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080)     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0)     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0)     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0)     /*!< PVD level 7 */
+
+#define  PWR_CR_DBP                          ((uint32_t)0x00000100)     /*!< Disable Backup Domain write protection                     */
+#define  PWR_CR_FPDS                         ((uint32_t)0x00000200)     /*!< Flash power down in Stop mode                              */
+#define  PWR_CR_LPLVDS                       ((uint32_t)0x00000400)     /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
+#define  PWR_CR_MRLVDS                       ((uint32_t)0x00000800)     /*!< Main Regulator Low Voltage in Deep Sleep mode              */
+#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000)     /*!< Refer to AN4073 on how to use this bit                     */
+#define  PWR_CR_VOS                          ((uint32_t)0x0000C000)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ 
+#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000)     /*!< Bit 0 */
+#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000)     /*!< Bit 1 */
+
+/* Legacy define */
+#define  PWR_CR_PMODE                        PWR_CR_VOS
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint32_t)0x00000001)     /*!< Wakeup Flag                                      */
+#define  PWR_CSR_SBF                         ((uint32_t)0x00000002)     /*!< Standby Flag                                     */
+#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004)     /*!< PVD Output                                       */
+#define  PWR_CSR_BRR                         ((uint32_t)0x00000008)     /*!< Backup regulator ready                           */
+#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100)     /*!< Enable WKUP pin                                  */
+#define  PWR_CSR_BRE                         ((uint32_t)0x00000200)     /*!< Backup regulator enable                          */
+#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000)     /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)
+
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)
+#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)
+#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)
+#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000)
+#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000)
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003F)
+#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001)
+#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002)
+#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004)
+#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008)
+#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010)
+#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020)
+
+#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0)
+#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040)
+#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080)
+#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100)
+#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200)
+#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400)
+#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800)
+#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000)
+#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000)
+#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000)
+
+#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000)
+#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000)
+#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000)
+
+#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000)
+#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000)
+#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000)
+
+#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000)
+#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000)
+#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000)
+#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000)
+#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000)
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00)        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00)        /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000)        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000)        /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000)
+#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000)
+#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000)
+#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000)
+#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000)
+#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000)
+
+/*!< MCO1 configuration */
+#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000)
+#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000)
+#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000)
+
+#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000)
+
+#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000)
+#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000)
+#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000)
+#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000)
+
+#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000)
+#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000)
+#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000)
+#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000)
+
+#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000)
+#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000)
+#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000)
+
+/********************  Bit definition for RCC_CIR register  *******************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)
+#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020)
+
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)
+#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000)
+
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)
+#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000)
+
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)
+
+/********************  Bit definition for RCC_AHB1RSTR register  **************/
+#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001)
+#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002)
+#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004)
+#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008)
+#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010)
+#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080)
+#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000)
+#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000)
+#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000)
+
+/********************  Bit definition for RCC_AHB2RSTR register  **************/
+#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080)
+
+/********************  Bit definition for RCC_AHB3RSTR register  **************/
+
+/********************  Bit definition for RCC_APB1RSTR register  **************/
+#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)
+#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)
+#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)
+#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)
+#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000)
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)
+
+/********************  Bit definition for RCC_APB2RSTR register  **************/
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001)
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010)
+#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)
+#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100)
+#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800)
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)
+#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000)
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000)
+#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000)
+#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000)
+#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000)
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001)
+#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002)
+#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004)
+#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008)
+#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010)
+#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080)
+#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000)
+#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000)
+#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000)
+#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000)
+#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000)
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080)
+
+/********************  Bit definition for RCC_AHB3ENR register  ***************/
+
+/********************  Bit definition for RCC_APB1ENR register  ***************/
+#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)
+#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)
+#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)
+#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)
+#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000)
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)
+
+/********************  Bit definition for RCC_APB2ENR register  ***************/
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001)
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010)
+#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)
+#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100)
+#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800)
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)
+#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000)
+#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000)
+#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000)
+#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000)
+#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000)
+
+/********************  Bit definition for RCC_AHB1LPENR register  *************/
+#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001)
+#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002)
+#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004)
+#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008)
+#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010)
+#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080)
+#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000)
+#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000)
+#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000)
+#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000)
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000)
+#define  RCC_AHB1LPENR_SRAM3LPEN             ((uint32_t)0x00080000)
+#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000)
+#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000)
+
+/********************  Bit definition for RCC_AHB2LPENR register  *************/
+#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080)
+
+/********************  Bit definition for RCC_AHB3LPENR register  *************/
+
+/********************  Bit definition for RCC_APB1LPENR register  *************/
+#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)
+#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)
+#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)
+#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)
+#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)
+#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)
+#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)
+#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)
+#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)
+#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)
+#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000)
+#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)
+#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)
+
+/********************  Bit definition for RCC_APB2LPENR register  *************/
+#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001)
+#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010)
+#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020)
+#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100)
+#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800)
+#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)
+#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000)
+#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000)
+#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000)
+#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000)
+#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000)
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)
+
+#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300)
+#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100)
+#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200)
+
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)
+#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000)
+#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000)
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)
+#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000)
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)
+
+/********************  Bit definition for RCC_SSCGR register  *****************/
+#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFF)
+#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000)
+#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000)
+#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000)
+
+/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
+#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0)
+#define  RCC_PLLI2SCFGR_PLLI2SN_0            ((uint32_t)0x00000040)
+#define  RCC_PLLI2SCFGR_PLLI2SN_1            ((uint32_t)0x00000080)
+#define  RCC_PLLI2SCFGR_PLLI2SN_2            ((uint32_t)0x00000100)
+#define  RCC_PLLI2SCFGR_PLLI2SN_3            ((uint32_t)0x00000200)
+#define  RCC_PLLI2SCFGR_PLLI2SN_4            ((uint32_t)0x00000400)
+#define  RCC_PLLI2SCFGR_PLLI2SN_5            ((uint32_t)0x00000800)
+#define  RCC_PLLI2SCFGR_PLLI2SN_6            ((uint32_t)0x00001000)
+#define  RCC_PLLI2SCFGR_PLLI2SN_7            ((uint32_t)0x00002000)
+#define  RCC_PLLI2SCFGR_PLLI2SN_8            ((uint32_t)0x00004000)
+
+#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000)
+#define  RCC_PLLI2SCFGR_PLLI2SR_0            ((uint32_t)0x10000000)
+#define  RCC_PLLI2SCFGR_PLLI2SR_1            ((uint32_t)0x20000000)
+#define  RCC_PLLI2SCFGR_PLLI2SR_2            ((uint32_t)0x40000000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM                            ((uint32_t)0x00400000)
+#define RTC_TR_HT                            ((uint32_t)0x00300000)
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
+#define RTC_TR_ST                            ((uint32_t)0x00000070)
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
+#define RTC_DR_MT                            ((uint32_t)0x00001000)
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
+#define RTC_DR_DT                            ((uint32_t)0x00000030)
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_COE                           ((uint32_t)0x00800000)
+#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
+#define RTC_CR_POL                           ((uint32_t)0x00100000)
+#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
+#define RTC_CR_BCK                           ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)
+#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
+#define RTC_CR_DCE                           ((uint32_t)0x00000080)
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
+#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00001FFF)
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CALIBR register  ***************/
+#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
+#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
+#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
+#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000)
+#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000)
+#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          SD host Interface                                 */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDIO_POWER register  ******************/
+#define  SDIO_POWER_PWRCTRL                  ((uint32_t)0x03)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                ((uint32_t)0x01)               /*!<Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                ((uint32_t)0x02)               /*!<Bit 1 */
+
+/******************  Bit definition for SDIO_CLKCR register  ******************/
+#define  SDIO_CLKCR_CLKDIV                   ((uint32_t)0x00FF)            /*!<Clock divide factor             */
+#define  SDIO_CLKCR_CLKEN                    ((uint32_t)0x0100)            /*!<Clock enable bit                */
+#define  SDIO_CLKCR_PWRSAV                   ((uint32_t)0x0200)            /*!<Power saving configuration bit  */
+#define  SDIO_CLKCR_BYPASS                   ((uint32_t)0x0400)            /*!<Clock divider bypass enable bit */
+
+#define  SDIO_CLKCR_WIDBUS                   ((uint32_t)0x1800)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 ((uint32_t)0x0800)            /*!<Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 ((uint32_t)0x1000)            /*!<Bit 1 */
+
+#define  SDIO_CLKCR_NEGEDGE                  ((uint32_t)0x2000)            /*!<SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  ((uint32_t)0x4000)            /*!<HW Flow Control enable          */
+
+/*******************  Bit definition for SDIO_ARG register  *******************/
+#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!<Command argument */
+
+/*******************  Bit definition for SDIO_CMD register  *******************/
+#define  SDIO_CMD_CMDINDEX                   ((uint32_t)0x003F)            /*!<Command Index                               */
+
+#define  SDIO_CMD_WAITRESP                   ((uint32_t)0x00C0)            /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 ((uint32_t)0x0040)            /*!< Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 ((uint32_t)0x0080)            /*!< Bit 1 */
+
+#define  SDIO_CMD_WAITINT                    ((uint32_t)0x0100)            /*!<CPSM Waits for Interrupt Request                               */
+#define  SDIO_CMD_WAITPEND                   ((uint32_t)0x0200)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     ((uint32_t)0x0400)            /*!<Command path state machine (CPSM) Enable bit                   */
+#define  SDIO_CMD_SDIOSUSPEND                ((uint32_t)0x0800)            /*!<SD I/O suspend command                                         */
+#define  SDIO_CMD_ENCMDCOMPL                 ((uint32_t)0x1000)            /*!<Enable CMD completion                                          */
+#define  SDIO_CMD_NIEN                       ((uint32_t)0x2000)            /*!<Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   ((uint32_t)0x4000)            /*!<CE-ATA command       */
+
+/*****************  Bit definition for SDIO_RESPCMD register  *****************/
+#define  SDIO_RESPCMD_RESPCMD                ((uint32_t)0x3F)               /*!<Response command index */
+
+/******************  Bit definition for SDIO_RESP0 register  ******************/
+#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP1 register  ******************/
+#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP2 register  ******************/
+#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP3 register  ******************/
+#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP4 register  ******************/
+#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */
+
+/******************  Bit definition for SDIO_DTIMER register  *****************/
+#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!<Data timeout period. */
+
+/******************  Bit definition for SDIO_DLEN register  *******************/
+#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!<Data length value    */
+
+/******************  Bit definition for SDIO_DCTRL register  ******************/
+#define  SDIO_DCTRL_DTEN                     ((uint32_t)0x0001)            /*!<Data transfer enabled bit         */
+#define  SDIO_DCTRL_DTDIR                    ((uint32_t)0x0002)            /*!<Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   ((uint32_t)0x0004)            /*!<Data transfer mode selection      */
+#define  SDIO_DCTRL_DMAEN                    ((uint32_t)0x0008)            /*!<DMA enabled bit                   */
+
+#define  SDIO_DCTRL_DBLOCKSIZE               ((uint32_t)0x00F0)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint32_t)0x0010)            /*!<Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint32_t)0x0020)            /*!<Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint32_t)0x0080)            /*!<Bit 3 */
+
+#define  SDIO_DCTRL_RWSTART                  ((uint32_t)0x0100)            /*!<Read wait start         */
+#define  SDIO_DCTRL_RWSTOP                   ((uint32_t)0x0200)            /*!<Read wait stop          */
+#define  SDIO_DCTRL_RWMOD                    ((uint32_t)0x0400)            /*!<Read wait mode          */
+#define  SDIO_DCTRL_SDIOEN                   ((uint32_t)0x0800)            /*!<SD I/O enable functions */
+
+/******************  Bit definition for SDIO_DCOUNT register  *****************/
+#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!<Data count value */
+
+/******************  Bit definition for SDIO_STA register  ********************/
+#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!<Command response received (CRC check failed)  */
+#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!<Data block sent/received (CRC check failed)   */
+#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!<Command response timeout                      */
+#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!<Data timeout                                  */
+#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!<Transmit FIFO underrun error                  */
+#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!<Received FIFO overrun error                   */
+#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!<Command response received (CRC check passed)  */
+#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!<Command sent (no response required)           */
+#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!<Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!<Data block sent/received (CRC check passed)   */
+#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!<Command transfer in progress                  */
+#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!<Data transmit in progress                     */
+#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!<Data receive in progress                      */
+#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!<Transmit FIFO full                            */
+#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!<Receive FIFO full                             */
+#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!<Transmit FIFO empty                           */
+#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!<Receive FIFO empty                            */
+#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!<Data available in transmit FIFO               */
+#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!<Data available in receive FIFO                */
+#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!<SDIO interrupt received                       */
+#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received for CMD61 */
+
+/*******************  Bit definition for SDIO_ICR register  *******************/
+#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!<CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!<DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!<CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!<DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!<TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!<RXOVERR flag clear bit  */
+#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!<CMDREND flag clear bit  */
+#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!<CMDSENT flag clear bit  */
+#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!<DATAEND flag clear bit  */
+#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!<STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!<DBCKEND flag clear bit  */
+#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!<SDIOIT flag clear bit   */
+#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!<CEATAEND flag clear bit */
+
+/******************  Bit definition for SDIO_MASK register  *******************/
+#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!<Command CRC Fail Interrupt Enable          */
+#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!<Data CRC Fail Interrupt Enable             */
+#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!<Command TimeOut Interrupt Enable           */
+#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!<Data TimeOut Interrupt Enable              */
+#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!<Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!<Command Sent Interrupt Enable              */
+#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!<Data End Interrupt Enable                  */
+#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!<Start Bit Error Interrupt Enable           */
+#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!<Data Block End Interrupt Enable            */
+#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!<CCommand Acting Interrupt Enable           */
+#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!<Data Transmit Acting Interrupt Enable      */
+#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!<Data receive acting interrupt enabled      */
+#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!<Tx FIFO Half Empty interrupt Enable        */
+#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!<Rx FIFO Half Full interrupt Enable         */
+#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!<Tx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!<Rx FIFO Full interrupt Enable              */
+#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!<Tx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!<Rx FIFO Empty interrupt Enable             */
+#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!<Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!<Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
+#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!<Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDIO_FIFO register  *******************/
+#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001)            /*!<Clock Phase      */
+#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002)            /*!<Clock Polarity   */
+#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004)            /*!<Master Selection */
+
+#define  SPI_CR1_BR                          ((uint32_t)0x00000038)            /*!<BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008)            /*!<Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010)            /*!<Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020)            /*!<Bit 2 */
+
+#define  SPI_CR1_SPE                         ((uint32_t)0x00000040)            /*!<SPI Enable                          */
+#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080)            /*!<Frame Format                        */
+#define  SPI_CR1_SSI                         ((uint32_t)0x00000100)            /*!<Internal slave select               */
+#define  SPI_CR1_SSM                         ((uint32_t)0x00000200)            /*!<Software slave management           */
+#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400)            /*!<Receive only                        */
+#define  SPI_CR1_DFF                         ((uint32_t)0x00000800)            /*!<Data Frame Format                   */
+#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000)            /*!<Transmit CRC next                   */
+#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000)            /*!<Hardware CRC calculation enable     */
+#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000)            /*!<Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000)            /*!<Bidirectional data mode enable      */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001)               /*!<Rx Buffer DMA Enable                 */
+#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002)               /*!<Tx Buffer DMA Enable                 */
+#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004)               /*!<SS Output Enable                     */
+#define  SPI_CR2_FRF                         ((uint32_t)0x00000010)               /*!<Frame Format                         */
+#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020)               /*!<Error Interrupt Enable               */
+#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040)               /*!<RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080)               /*!<Tx buffer Empty Interrupt Enable     */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint32_t)0x00000001)               /*!<Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint32_t)0x00000002)               /*!<Transmit buffer Empty    */
+#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004)               /*!<Channel side             */
+#define  SPI_SR_UDR                          ((uint32_t)0x00000008)               /*!<Underrun flag            */
+#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010)               /*!<CRC Error flag           */
+#define  SPI_SR_MODF                         ((uint32_t)0x00000020)               /*!<Mode fault               */
+#define  SPI_SR_OVR                          ((uint32_t)0x00000040)               /*!<Overrun flag             */
+#define  SPI_SR_BSY                          ((uint32_t)0x00000080)               /*!<Busy flag                */
+#define  SPI_SR_FRE                          ((uint32_t)0x00000100)               /*!<Frame format error flag  */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint32_t)0x0000FFFF)            /*!<Data Register           */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFF)            /*!<CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFF)            /*!<Rx CRC Register         */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFF)            /*!<Tx CRC Register         */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001)            /*!<Channel length (number of bits per audio channel) */
+
+#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004)            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008)            /*!<steady state clock polarity               */
+
+#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020)            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080)            /*!<PCM frame synchronization                 */
+
+#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200)            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400)            /*!<I2S Enable         */
+#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800)            /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FF)            /*!<I2S Linear prescaler         */
+#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100)            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200)            /*!<Master Clock Output Enable   */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  
+#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001)
+#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002)
+#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004)
+
+/******************  Bit definition for SYSCFG_PMC register  ******************/
+#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit  */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x000F) /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0xF000) /*!<EXTI 3 configuration */
+/** 
+  * @brief   EXTI0 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x0000) /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x0001) /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x0002) /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x0003) /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x0004) /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x0007) /*!<PH[0] pin */
+
+/** 
+  * @brief   EXTI1 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x0000) /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x0010) /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x0020) /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x0030) /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x0040) /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x0070) /*!<PH[1] pin */
+
+/** 
+  * @brief   EXTI2 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x0000) /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x0100) /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x0200) /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x0300) /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x0400) /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x0700) /*!<PH[2] pin */
+
+/** 
+  * @brief   EXTI3 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x0000) /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x1000) /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x2000) /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x3000) /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x4000) /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x7000) /*!<PH[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x000F) /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0xF000) /*!<EXTI 7 configuration */
+/** 
+  * @brief   EXTI4 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x0000) /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x0001) /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x0002) /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x0003) /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x0004) /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x0007) /*!<PH[4] pin */
+
+/** 
+  * @brief   EXTI5 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x0000) /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x0010) /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x0020) /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x0030) /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x0040) /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x0070) /*!<PH[5] pin */
+
+/** 
+  * @brief   EXTI6 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x0000) /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x0100) /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x0200) /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x0300) /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x0400) /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x0700) /*!<PH[6] pin */
+
+/** 
+  * @brief   EXTI7 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x0000) /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x1000) /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x2000) /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x3000) /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x4000) /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x7000) /*!<PH[7] pin */
+
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x000F) /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0xF000) /*!<EXTI 11 configuration */
+           
+/** 
+  * @brief   EXTI8 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x0000) /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x0001) /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x0002) /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x0003) /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x0004) /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x0007) /*!<PH[8] pin */
+
+/** 
+  * @brief   EXTI9 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x0000) /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x0010) /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x0020) /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x0030) /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x0040) /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x0070) /*!<PH[9] pin */
+
+/** 
+  * @brief   EXTI10 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x0000) /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x0100) /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x0200) /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x0300) /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x0400) /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x0700) /*!<PH[10] pin */
+
+/** 
+  * @brief   EXTI11 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x0000) /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x1000) /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x2000) /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x3000) /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x4000) /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x7000) /*!<PH[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x000F) /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0xF000) /*!<EXTI 15 configuration */
+/** 
+  * @brief   EXTI12 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x0000) /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x0001) /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x0002) /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x0003) /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x0004) /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x0007) /*!<PH[12] pin */
+
+/** 
+  * @brief   EXTI13 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x0000) /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x0010) /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x0020) /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x0030) /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x0040) /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x0070) /*!<PH[13] pin */
+
+/** 
+  * @brief   EXTI14 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x0000) /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x0100) /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x0200) /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x0300) /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x0400) /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x0700) /*!<PH[14] pin */
+
+/** 
+  * @brief   EXTI15 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x0000) /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x1000) /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x2000) /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x3000) /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x4000) /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x7000) /*!<PH[15] pin */
+
+/******************  Bit definition for SYSCFG_CMPCR register  ****************/  
+#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100) /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint32_t)0x0001)            /*!<Counter enable        */
+#define  TIM_CR1_UDIS                        ((uint32_t)0x0002)            /*!<Update disable        */
+#define  TIM_CR1_URS                         ((uint32_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint32_t)0x0008)            /*!<One pulse mode        */
+#define  TIM_CR1_DIR                         ((uint32_t)0x0010)            /*!<Direction             */
+
+#define  TIM_CR1_CMS                         ((uint32_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint32_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint32_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint32_t)0x0080)            /*!<Auto-reload preload enable     */
+
+#define  TIM_CR1_CKD                         ((uint32_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint32_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint32_t)0x0200)            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint32_t)0x0001)            /*!<Capture/Compare Preloaded Control        */
+#define  TIM_CR2_CCUS                        ((uint32_t)0x0004)            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint32_t)0x0008)            /*!<Capture/Compare DMA Selection            */
+
+#define  TIM_CR2_MMS                         ((uint32_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint32_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint32_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint32_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint32_t)0x0080)            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint32_t)0x0100)            /*!<Output Idle state 1 (OC1 output)  */
+#define  TIM_CR2_OIS1N                       ((uint32_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint32_t)0x0400)            /*!<Output Idle state 2 (OC2 output)  */
+#define  TIM_CR2_OIS2N                       ((uint32_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint32_t)0x1000)            /*!<Output Idle state 3 (OC3 output)  */
+#define  TIM_CR2_OIS3N                       ((uint32_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint32_t)0x4000)            /*!<Output Idle state 4 (OC4 output)  */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint32_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection)    */
+#define  TIM_SMCR_SMS_0                      ((uint32_t)0x0001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint32_t)0x0002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint32_t)0x0004)            /*!<Bit 2 */
+
+#define  TIM_SMCR_TS                         ((uint32_t)0x0070)            /*!<TS[2:0] bits (Trigger selection)        */
+#define  TIM_SMCR_TS_0                       ((uint32_t)0x0010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint32_t)0x0020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint32_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint32_t)0x0080)            /*!<Master/slave mode                       */
+
+#define  TIM_SMCR_ETF                        ((uint32_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint32_t)0x0100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint32_t)0x0400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint32_t)0x0800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint32_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x1000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x2000)            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint32_t)0x4000)            /*!<External clock enable     */
+#define  TIM_SMCR_ETP                        ((uint32_t)0x8000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint32_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint32_t)0x0002)            /*!<Capture/Compare 1 interrupt enable   */
+#define  TIM_DIER_CC2IE                      ((uint32_t)0x0004)            /*!<Capture/Compare 2 interrupt enable   */
+#define  TIM_DIER_CC3IE                      ((uint32_t)0x0008)            /*!<Capture/Compare 3 interrupt enable   */
+#define  TIM_DIER_CC4IE                      ((uint32_t)0x0010)            /*!<Capture/Compare 4 interrupt enable   */
+#define  TIM_DIER_COMIE                      ((uint32_t)0x0020)            /*!<COM interrupt enable                 */
+#define  TIM_DIER_TIE                        ((uint32_t)0x0040)            /*!<Trigger interrupt enable             */
+#define  TIM_DIER_BIE                        ((uint32_t)0x0080)            /*!<Break interrupt enable               */
+#define  TIM_DIER_UDE                        ((uint32_t)0x0100)            /*!<Update DMA request enable            */
+#define  TIM_DIER_CC1DE                      ((uint32_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint32_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint32_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint32_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint32_t)0x2000)            /*!<COM DMA request enable               */
+#define  TIM_DIER_TDE                        ((uint32_t)0x4000)            /*!<Trigger DMA request enable           */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint32_t)0x0001)            /*!<Update interrupt Flag              */
+#define  TIM_SR_CC1IF                        ((uint32_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag   */
+#define  TIM_SR_CC2IF                        ((uint32_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag   */
+#define  TIM_SR_CC3IF                        ((uint32_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag   */
+#define  TIM_SR_CC4IF                        ((uint32_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag   */
+#define  TIM_SR_COMIF                        ((uint32_t)0x0020)            /*!<COM interrupt Flag                 */
+#define  TIM_SR_TIF                          ((uint32_t)0x0040)            /*!<Trigger interrupt Flag             */
+#define  TIM_SR_BIF                          ((uint32_t)0x0080)            /*!<Break interrupt Flag               */
+#define  TIM_SR_CC1OF                        ((uint32_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint32_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint32_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint32_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint32_t)0x01)               /*!<Update Generation                         */
+#define  TIM_EGR_CC1G                        ((uint32_t)0x02)               /*!<Capture/Compare 1 Generation              */
+#define  TIM_EGR_CC2G                        ((uint32_t)0x04)               /*!<Capture/Compare 2 Generation              */
+#define  TIM_EGR_CC3G                        ((uint32_t)0x08)               /*!<Capture/Compare 3 Generation              */
+#define  TIM_EGR_CC4G                        ((uint32_t)0x10)               /*!<Capture/Compare 4 Generation              */
+#define  TIM_EGR_COMG                        ((uint32_t)0x20)               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint32_t)0x40)               /*!<Trigger Generation                        */
+#define  TIM_EGR_BG                          ((uint32_t)0x80)               /*!<Break Generation                          */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint32_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x0004)            /*!<Output Compare 1 Fast enable                 */
+#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x0008)            /*!<Output Compare 1 Preload enable              */
+
+#define  TIM_CCMR1_OC1M                      ((uint32_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x0080)            /*!<Output Compare 1Clear Enable                 */
+
+#define  TIM_CCMR1_CC2S                      ((uint32_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x0400)            /*!<Output Compare 2 Fast enable                 */
+#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x0800)            /*!<Output Compare 2 Preload enable              */
+
+#define  TIM_CCMR1_OC2M                      ((uint32_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint32_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint32_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x8000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint32_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x0004)            /*!<Output Compare 3 Fast enable           */
+#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x0008)            /*!<Output Compare 3 Preload enable        */
+
+#define  TIM_CCMR2_OC3M                      ((uint32_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint32_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x0400)            /*!<Output Compare 4 Fast enable    */
+#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x0800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint32_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint32_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint32_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x8000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint32_t)0x0001)            /*!<Capture/Compare 1 output enable                 */
+#define  TIM_CCER_CC1P                       ((uint32_t)0x0002)            /*!<Capture/Compare 1 output Polarity               */
+#define  TIM_CCER_CC1NE                      ((uint32_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable   */
+#define  TIM_CCER_CC1NP                      ((uint32_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint32_t)0x0010)            /*!<Capture/Compare 2 output enable                 */
+#define  TIM_CCER_CC2P                       ((uint32_t)0x0020)            /*!<Capture/Compare 2 output Polarity               */
+#define  TIM_CCER_CC2NE                      ((uint32_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable   */
+#define  TIM_CCER_CC2NP                      ((uint32_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint32_t)0x0100)            /*!<Capture/Compare 3 output enable                 */
+#define  TIM_CCER_CC3P                       ((uint32_t)0x0200)            /*!<Capture/Compare 3 output Polarity               */
+#define  TIM_CCER_CC3NE                      ((uint32_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable   */
+#define  TIM_CCER_CC3NP                      ((uint32_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint32_t)0x1000)            /*!<Capture/Compare 4 output enable                 */
+#define  TIM_CCER_CC4P                       ((uint32_t)0x2000)            /*!<Capture/Compare 4 output Polarity               */
+#define  TIM_CCER_CC4NP                      ((uint32_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint32_t)0xFFFF)            /*!<Counter Value            */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint32_t)0xFFFF)            /*!<Prescaler Value          */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint32_t)0xFFFF)            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint32_t)0xFF)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 1 Value  */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 2 Value  */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 3 Value  */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint32_t)0xFFFF)            /*!<Capture/Compare 4 Value  */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint32_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint32_t)0x0001)            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint32_t)0x0002)            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint32_t)0x0004)            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint32_t)0x0008)            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint32_t)0x0010)            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint32_t)0x0020)            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint32_t)0x0040)            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint32_t)0x0080)            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint32_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x0100)            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint32_t)0x0400)            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint32_t)0x0800)            /*!<Off-State Selection for Run mode  */
+#define  TIM_BDTR_BKE                        ((uint32_t)0x1000)            /*!<Break enable                      */
+#define  TIM_BDTR_BKP                        ((uint32_t)0x2000)            /*!<Break Polarity                    */
+#define  TIM_BDTR_AOE                        ((uint32_t)0x4000)            /*!<Automatic Output enable           */
+#define  TIM_BDTR_MOE                        ((uint32_t)0x8000)            /*!<Main Output enable                */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint32_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint32_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint32_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint32_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint32_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint32_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint32_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint32_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint32_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint32_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint32_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint32_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint32_t)0xFFFF)            /*!<DMA register for burst accesses                    */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM_OR_TI4_RMP                       ((uint32_t)0x00C0)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0                     ((uint32_t)0x0040)            /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1                     ((uint32_t)0x0080)            /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP                      ((uint32_t)0x0C00)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0                    ((uint32_t)0x0400)            /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1                    ((uint32_t)0x0800)            /*!<Bit 1 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for USART_SR register  *******************/
+#define  USART_SR_PE                         ((uint32_t)0x0001)            /*!<Parity Error                 */
+#define  USART_SR_FE                         ((uint32_t)0x0002)            /*!<Framing Error                */
+#define  USART_SR_NE                         ((uint32_t)0x0004)            /*!<Noise Error Flag             */
+#define  USART_SR_ORE                        ((uint32_t)0x0008)            /*!<OverRun Error                */
+#define  USART_SR_IDLE                       ((uint32_t)0x0010)            /*!<IDLE line detected           */
+#define  USART_SR_RXNE                       ((uint32_t)0x0020)            /*!<Read Data Register Not Empty */
+#define  USART_SR_TC                         ((uint32_t)0x0040)            /*!<Transmission Complete        */
+#define  USART_SR_TXE                        ((uint32_t)0x0080)            /*!<Transmit Data Register Empty */
+#define  USART_SR_LBD                        ((uint32_t)0x0100)            /*!<LIN Break Detection Flag     */
+#define  USART_SR_CTS                        ((uint32_t)0x0200)            /*!<CTS Flag                     */
+
+/*******************  Bit definition for USART_DR register  *******************/
+#define  USART_DR_DR                         ((uint32_t)0x01FF)            /*!<Data value */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_Fraction              ((uint32_t)0x000F)            /*!<Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              ((uint32_t)0xFFF0)            /*!<Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_SBK                       ((uint32_t)0x0001)            /*!<Send Break                             */
+#define  USART_CR1_RWU                       ((uint32_t)0x0002)            /*!<Receiver wakeup                        */
+#define  USART_CR1_RE                        ((uint32_t)0x0004)            /*!<Receiver Enable                        */
+#define  USART_CR1_TE                        ((uint32_t)0x0008)            /*!<Transmitter Enable                     */
+#define  USART_CR1_IDLEIE                    ((uint32_t)0x0010)            /*!<IDLE Interrupt Enable                  */
+#define  USART_CR1_RXNEIE                    ((uint32_t)0x0020)            /*!<RXNE Interrupt Enable                  */
+#define  USART_CR1_TCIE                      ((uint32_t)0x0040)            /*!<Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint32_t)0x0080)            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PEIE                      ((uint32_t)0x0100)            /*!<PE Interrupt Enable                    */
+#define  USART_CR1_PS                        ((uint32_t)0x0200)            /*!<Parity Selection                       */
+#define  USART_CR1_PCE                       ((uint32_t)0x0400)            /*!<Parity Control Enable                  */
+#define  USART_CR1_WAKE                      ((uint32_t)0x0800)            /*!<Wakeup method                          */
+#define  USART_CR1_M                         ((uint32_t)0x1000)            /*!<Word length                            */
+#define  USART_CR1_UE                        ((uint32_t)0x2000)            /*!<USART Enable                           */
+#define  USART_CR1_OVER8                     ((uint32_t)0x8000)            /*!<USART Oversampling by 8 enable         */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADD                       ((uint32_t)0x000F)            /*!<Address of the USART node            */
+#define  USART_CR2_LBDL                      ((uint32_t)0x0020)            /*!<LIN Break Detection Length           */
+#define  USART_CR2_LBDIE                     ((uint32_t)0x0040)            /*!<LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint32_t)0x0100)            /*!<Last Bit Clock pulse                 */
+#define  USART_CR2_CPHA                      ((uint32_t)0x0200)            /*!<Clock Phase                          */
+#define  USART_CR2_CPOL                      ((uint32_t)0x0400)            /*!<Clock Polarity                       */
+#define  USART_CR2_CLKEN                     ((uint32_t)0x0800)            /*!<Clock Enable                         */
+
+#define  USART_CR2_STOP                      ((uint32_t)0x3000)            /*!<STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint32_t)0x1000)            /*!<Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint32_t)0x2000)            /*!<Bit 1 */
+
+#define  USART_CR2_LINEN                     ((uint32_t)0x4000)            /*!<LIN mode enable */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint32_t)0x0001)            /*!<Error Interrupt Enable      */
+#define  USART_CR3_IREN                      ((uint32_t)0x0002)            /*!<IrDA mode Enable            */
+#define  USART_CR3_IRLP                      ((uint32_t)0x0004)            /*!<IrDA Low-Power              */
+#define  USART_CR3_HDSEL                     ((uint32_t)0x0008)            /*!<Half-Duplex Selection       */
+#define  USART_CR3_NACK                      ((uint32_t)0x0010)            /*!<Smartcard NACK enable       */
+#define  USART_CR3_SCEN                      ((uint32_t)0x0020)            /*!<Smartcard mode enable       */
+#define  USART_CR3_DMAR                      ((uint32_t)0x0040)            /*!<DMA Enable Receiver         */
+#define  USART_CR3_DMAT                      ((uint32_t)0x0080)            /*!<DMA Enable Transmitter      */
+#define  USART_CR3_RTSE                      ((uint32_t)0x0100)            /*!<RTS Enable                  */
+#define  USART_CR3_CTSE                      ((uint32_t)0x0200)            /*!<CTS Enable                  */
+#define  USART_CR3_CTSIE                     ((uint32_t)0x0400)            /*!<CTS Interrupt Enable        */
+#define  USART_CR3_ONEBIT                    ((uint32_t)0x0800)            /*!<USART One bit method enable */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint32_t)0x00FF)            /*!<PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    ((uint32_t)0x0001)            /*!<Bit 0 */
+#define  USART_GTPR_PSC_1                    ((uint32_t)0x0002)            /*!<Bit 1 */
+#define  USART_GTPR_PSC_2                    ((uint32_t)0x0004)            /*!<Bit 2 */
+#define  USART_GTPR_PSC_3                    ((uint32_t)0x0008)            /*!<Bit 3 */
+#define  USART_GTPR_PSC_4                    ((uint32_t)0x0010)            /*!<Bit 4 */
+#define  USART_GTPR_PSC_5                    ((uint32_t)0x0020)            /*!<Bit 5 */
+#define  USART_GTPR_PSC_6                    ((uint32_t)0x0040)            /*!<Bit 6 */
+#define  USART_GTPR_PSC_7                    ((uint32_t)0x0080)            /*!<Bit 7 */
+
+#define  USART_GTPR_GT                       ((uint32_t)0xFF00)            /*!<Guard time value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint32_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint32_t)0x01)               /*!<Bit 0 */
+#define  WWDG_CR_T1                          ((uint32_t)0x02)               /*!<Bit 1 */
+#define  WWDG_CR_T2                          ((uint32_t)0x04)               /*!<Bit 2 */
+#define  WWDG_CR_T3                          ((uint32_t)0x08)               /*!<Bit 3 */
+#define  WWDG_CR_T4                          ((uint32_t)0x10)               /*!<Bit 4 */
+#define  WWDG_CR_T5                          ((uint32_t)0x20)               /*!<Bit 5 */
+#define  WWDG_CR_T6                          ((uint32_t)0x40)               /*!<Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint32_t)0x80)               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint32_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint32_t)0x0001)            /*!<Bit 0 */
+#define  WWDG_CFR_W1                         ((uint32_t)0x0002)            /*!<Bit 1 */
+#define  WWDG_CFR_W2                         ((uint32_t)0x0004)            /*!<Bit 2 */
+#define  WWDG_CFR_W3                         ((uint32_t)0x0008)            /*!<Bit 3 */
+#define  WWDG_CFR_W4                         ((uint32_t)0x0010)            /*!<Bit 4 */
+#define  WWDG_CFR_W5                         ((uint32_t)0x0020)            /*!<Bit 5 */
+#define  WWDG_CFR_W6                         ((uint32_t)0x0040)            /*!<Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint32_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x0080)            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x0100)            /*!<Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint32_t)0x0200)            /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint32_t)0x01)               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                DBG                                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)
+#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)
+#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)
+
+#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)
+#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)/*!<Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001)
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002)
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004)
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008)
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010)
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020)
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040)
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080)
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100)
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400)
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800)
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000)
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000)
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001)
+#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002)
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000)
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000)
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG			                        */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_SRQSCS                  ((uint32_t)0x00000001)            /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ                     ((uint32_t)0x00000002)            /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS                  ((uint32_t)0x00000100)            /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ                   ((uint32_t)0x00000200)            /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN                 ((uint32_t)0x00000400)            /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN                  ((uint32_t)0x00000800)            /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS                  ((uint32_t)0x00010000)            /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT                    ((uint32_t)0x00020000)            /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD                   ((uint32_t)0x00040000)            /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD                   ((uint32_t)0x00080000)            /*!< B-session valid */
+
+/********************  Bit definition forUSB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS                 ((uint32_t)0x00000003)            /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0               ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1               ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS                   ((uint32_t)0x00000004)            /*!< FS- and LS-only support */
+
+/********************  Bit definition forUSB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD                    ((uint32_t)0x00000003)            /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                  ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1                  ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK                ((uint32_t)0x00000004)            /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD                     ((uint32_t)0x000007F0)            /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                   ((uint32_t)0x00000010)            /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1                   ((uint32_t)0x00000020)            /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2                   ((uint32_t)0x00000040)            /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3                   ((uint32_t)0x00000080)            /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4                   ((uint32_t)0x00000100)            /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5                   ((uint32_t)0x00000200)            /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6                   ((uint32_t)0x00000400)            /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL                   ((uint32_t)0x00001800)            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                 ((uint32_t)0x00000800)            /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1                 ((uint32_t)0x00001000)            /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL               ((uint32_t)0x03000000)            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0             ((uint32_t)0x01000000)            /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1             ((uint32_t)0x02000000)            /*!<Bit 1 */
+
+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK                 ((uint32_t)0x00000001)            /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK                ((uint32_t)0x00000002)            /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP                 ((uint32_t)0x00000010)            /*!< PHY suspended */
+
+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET                   ((uint32_t)0x00000004)            /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG                 ((uint32_t)0x00000100)            /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG                 ((uint32_t)0x00000200)            /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET                  ((uint32_t)0x00020000)            /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG                 ((uint32_t)0x00040000)            /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE                  ((uint32_t)0x00080000)            /*!< Debounce done */
+
+/********************  Bit definition forUSB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG                  ((uint32_t)0x00000001)            /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS                    ((uint32_t)0x00000002)            /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS                  ((uint32_t)0x00000004)            /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS                  ((uint32_t)0x00000008)            /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL                    ((uint32_t)0x00000070)            /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2                  ((uint32_t)0x00000040)            /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK                  ((uint32_t)0x00000080)            /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK                  ((uint32_t)0x00000100)            /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK                  ((uint32_t)0x00000200)            /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK                  ((uint32_t)0x00000400)            /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE                ((uint32_t)0x00000800)            /*!< Power-on programming done */
+
+/********************  Bit definition forUSB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL                   ((uint32_t)0x0000FFFF)            /*!< Frame interval */
+
+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM                   ((uint32_t)0x0000FFFF)            /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM                   ((uint32_t)0xFFFF0000)            /*!< Frame time remaining */
+
+/********************  Bit definition forUSB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS                 ((uint32_t)0x00000001)            /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD                 ((uint32_t)0x00000006)            /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0               ((uint32_t)0x00000002)            /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1               ((uint32_t)0x00000004)            /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR                    ((uint32_t)0x00000008)            /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF                   ((uint32_t)0x003FFF00)            /*!< Frame number of the received SOF */
+
+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT                    ((uint32_t)0x00000001)            /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN                 ((uint32_t)0x0000001E)            /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0               ((uint32_t)0x00000002)            /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1               ((uint32_t)0x00000004)            /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2               ((uint32_t)0x00000008)            /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3               ((uint32_t)0x00000010)            /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN                   ((uint32_t)0x00000020)            /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL                 ((uint32_t)0x00000080)            /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL                ((uint32_t)0x00000100)            /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL                   ((uint32_t)0x00000007)            /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL                  ((uint32_t)0x00000040)            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP                  ((uint32_t)0x00000100)            /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP                  ((uint32_t)0x00000200)            /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT                    ((uint32_t)0x00003C00)            /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2                  ((uint32_t)0x00001000)            /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3                  ((uint32_t)0x00002000)            /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 ((uint32_t)0x00008000)            /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS                ((uint32_t)0x00020000)            /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR                  ((uint32_t)0x00040000)            /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM                 ((uint32_t)0x00080000)            /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              ((uint32_t)0x00100000)            /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              ((uint32_t)0x00200000)            /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS                   ((uint32_t)0x00400000)            /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI                    ((uint32_t)0x00800000)            /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI                    ((uint32_t)0x01000000)            /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD                 ((uint32_t)0x02000000)            /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD                   ((uint32_t)0x20000000)            /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD                   ((uint32_t)0x40000000)            /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT                  ((uint32_t)0x80000000)            /*!< Corrupt Tx packet */
+
+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST                   ((uint32_t)0x00000001)            /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST                   ((uint32_t)0x00000002)            /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST                   ((uint32_t)0x00000004)            /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH                 ((uint32_t)0x00000010)            /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH                 ((uint32_t)0x00000020)            /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM                  ((uint32_t)0x000007C0)            /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                ((uint32_t)0x00000040)            /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                ((uint32_t)0x00000080)            /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                ((uint32_t)0x00000100)            /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                ((uint32_t)0x00000200)            /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                ((uint32_t)0x00000400)            /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ                  ((uint32_t)0x40000000)            /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL                  ((uint32_t)0x80000000)            /*!< AHB master idle */
+
+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM                     ((uint32_t)0x00000008)            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM                 ((uint32_t)0x00000020)            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM                 ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM                  ((uint32_t)0x00000100)            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM                     ((uint32_t)0x00000200)            /*!< BNA interrupt mask */
+
+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL                ((uint32_t)0x0000FFFF)            /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV                 ((uint32_t)0x00FF0000)            /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               ((uint32_t)0x00010000)            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               ((uint32_t)0x00020000)            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               ((uint32_t)0x00040000)            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               ((uint32_t)0x00080000)            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               ((uint32_t)0x00100000)            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               ((uint32_t)0x00200000)            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               ((uint32_t)0x00400000)            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               ((uint32_t)0x00800000)            /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP                 ((uint32_t)0xFF000000)            /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               ((uint32_t)0x01000000)            /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               ((uint32_t)0x02000000)            /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               ((uint32_t)0x04000000)            /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               ((uint32_t)0x08000000)            /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               ((uint32_t)0x10000000)            /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               ((uint32_t)0x20000000)            /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               ((uint32_t)0x40000000)            /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               ((uint32_t)0x80000000)            /*!<Bit 7 */
+
+/********************  Bit definition forUSB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT                   ((uint32_t)0x0000FFFF)            /*!< Channel interrupts */
+
+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM                   ((uint32_t)0x00000008)            /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM                  ((uint32_t)0x00000010)            /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP                 ((uint32_t)0x00000040)            /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM                    ((uint32_t)0x00000100)            /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM                    ((uint32_t)0x00000200)            /*!< BNA interrupt mask */
+
+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD                    ((uint32_t)0x00000001)            /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS                    ((uint32_t)0x00000002)            /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT                  ((uint32_t)0x00000004)            /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF                     ((uint32_t)0x00000008)            /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL                  ((uint32_t)0x00000010)            /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE                  ((uint32_t)0x00000020)            /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF                ((uint32_t)0x00000040)            /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              ((uint32_t)0x00000080)            /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP                   ((uint32_t)0x00000400)            /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP                 ((uint32_t)0x00000800)            /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST                  ((uint32_t)0x00001000)            /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE                 ((uint32_t)0x00002000)            /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP                 ((uint32_t)0x00004000)            /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF                    ((uint32_t)0x00008000)            /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT                  ((uint32_t)0x00040000)            /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT                  ((uint32_t)0x00080000)            /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR                ((uint32_t)0x00100000)            /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       ((uint32_t)0x00200000)            /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP               ((uint32_t)0x00400000)            /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT                 ((uint32_t)0x01000000)            /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT                   ((uint32_t)0x02000000)            /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE                   ((uint32_t)0x04000000)            /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG                 ((uint32_t)0x10000000)            /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT                 ((uint32_t)0x20000000)            /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT                  ((uint32_t)0x40000000)            /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT                  ((uint32_t)0x80000000)            /*!< Resume/remote wakeup detected interrupt */
+
+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM                   ((uint32_t)0x00000002)            /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT                  ((uint32_t)0x00000004)            /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM                    ((uint32_t)0x00000008)            /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM                 ((uint32_t)0x00000010)            /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM                 ((uint32_t)0x00000020)            /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM               ((uint32_t)0x00000040)            /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM               ((uint32_t)0x00000080)            /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM                  ((uint32_t)0x00000400)            /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM                ((uint32_t)0x00000800)            /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST                  ((uint32_t)0x00001000)            /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM                ((uint32_t)0x00002000)            /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM                ((uint32_t)0x00004000)            /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM                   ((uint32_t)0x00008000)            /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM                  ((uint32_t)0x00020000)            /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT                  ((uint32_t)0x00040000)            /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT                  ((uint32_t)0x00080000)            /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM               ((uint32_t)0x00100000)            /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         ((uint32_t)0x00200000)            /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM                  ((uint32_t)0x00400000)            /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM                   ((uint32_t)0x01000000)            /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM                    ((uint32_t)0x02000000)            /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM                  ((uint32_t)0x04000000)            /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM                ((uint32_t)0x10000000)            /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT                 ((uint32_t)0x20000000)            /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM                   ((uint32_t)0x40000000)            /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM                    ((uint32_t)0x80000000)            /*!< Resume/remote wakeup detected interrupt mask */
+
+/********************  Bit definition forUSB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT                  ((uint32_t)0x0000FFFF)            /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT                  ((uint32_t)0xFFFF0000)            /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM                  ((uint32_t)0x0000FFFF)            /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM                    ((uint32_t)0x0000000F)            /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT                     ((uint32_t)0x00007FF0)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID                     ((uint32_t)0x00018000)            /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS                   ((uint32_t)0x001E0000)            /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM                    ((uint32_t)0x0000FFFF)            /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM                    ((uint32_t)0xFFFF0000)            /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM                   ((uint32_t)0x0000000F)            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
+#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0)            /*!< Byte count */
+
+#define USB_OTG_DPID                    ((uint32_t)0x00018000)            /*!< Data PID */
+#define USB_OTG_DPID_0                  ((uint32_t)0x00008000)            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  ((uint32_t)0x00010000)            /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000)            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000)            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000)            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000)            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000)            /*!<Bit 3 */
+
+#define USB_OTG_EPNUM                   ((uint32_t)0x0000000F)            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000)            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000)            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000)            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000)            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000)            /*!<Bit 3 */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM                   ((uint32_t)0x0000000F)            /*!< Channel number */
+#define USB_OTG_CHNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define USB_OTG_CHNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define USB_OTG_CHNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
+#define USB_OTG_CHNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
+#define USB_OTG_BCNT                    ((uint32_t)0x00007FF0)            /*!< Byte count */
+
+#define USB_OTG_DPID                    ((uint32_t)0x00018000)            /*!< Data PID */
+#define USB_OTG_DPID_0                  ((uint32_t)0x00008000)            /*!<Bit 0 */
+#define USB_OTG_DPID_1                  ((uint32_t)0x00010000)            /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS                  ((uint32_t)0x001E0000)            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                ((uint32_t)0x00020000)            /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1                ((uint32_t)0x00040000)            /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2                ((uint32_t)0x00080000)            /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3                ((uint32_t)0x00100000)            /*!<Bit 3 */
+
+#define USB_OTG_EPNUM                   ((uint32_t)0x0000000F)            /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                 ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define USB_OTG_EPNUM_1                 ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define USB_OTG_EPNUM_2                 ((uint32_t)0x00000004)            /*!<Bit 2 */
+#define USB_OTG_EPNUM_3                 ((uint32_t)0x00000008)            /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM                  ((uint32_t)0x01E00000)            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                ((uint32_t)0x00200000)            /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1                ((uint32_t)0x00400000)            /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2                ((uint32_t)0x00800000)            /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3                ((uint32_t)0x01000000)            /*!<Bit 3 */
+
+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD                    ((uint32_t)0x0000FFFF)            /*!< RxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT                  ((uint32_t)0x0000FFFF)            /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA                 ((uint32_t)0x0000FFFF)            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD                  ((uint32_t)0xFFFF0000)            /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA                  ((uint32_t)0x0000FFFF)            /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD                   ((uint32_t)0xFFFF0000)            /*!< Endpoint 0 TxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP                  ((uint32_t)0x00000FFF)            /*!< Device VBUS pulsing time */
+
+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV                ((uint32_t)0x0000FFFF)            /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV                ((uint32_t)0x00FF0000)            /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              ((uint32_t)0x00010000)            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              ((uint32_t)0x00020000)            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              ((uint32_t)0x00040000)            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              ((uint32_t)0x00080000)            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              ((uint32_t)0x00100000)            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              ((uint32_t)0x00200000)            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              ((uint32_t)0x00400000)            /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              ((uint32_t)0x00800000)            /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP                ((uint32_t)0x7F000000)            /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              ((uint32_t)0x01000000)            /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              ((uint32_t)0x02000000)            /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              ((uint32_t)0x04000000)            /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              ((uint32_t)0x08000000)            /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              ((uint32_t)0x10000000)            /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              ((uint32_t)0x20000000)            /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              ((uint32_t)0x40000000)            /*!<Bit 6 */
+
+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN             ((uint32_t)0x00000001)            /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN                ((uint32_t)0x00000002)            /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN                ((uint32_t)0x000007FC)            /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              ((uint32_t)0x00000004)            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              ((uint32_t)0x00000008)            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              ((uint32_t)0x00000010)            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              ((uint32_t)0x00000020)            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              ((uint32_t)0x00000040)            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              ((uint32_t)0x00000080)            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              ((uint32_t)0x00000100)            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              ((uint32_t)0x00000200)            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              ((uint32_t)0x00000400)            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN                 ((uint32_t)0x00010000)            /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN                ((uint32_t)0x03FE0000)            /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              ((uint32_t)0x00020000)            /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              ((uint32_t)0x00040000)            /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              ((uint32_t)0x00080000)            /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              ((uint32_t)0x00100000)            /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              ((uint32_t)0x00200000)            /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              ((uint32_t)0x00400000)            /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              ((uint32_t)0x00800000)            /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              ((uint32_t)0x01000000)            /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              ((uint32_t)0x02000000)            /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN                   ((uint32_t)0x08000000)            /*!< Arbiter parking enable */
+
+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM               ((uint32_t)0x0000FFFF)            /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT                 ((uint32_t)0x00000002)            /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT                 ((uint32_t)0x00020000)            /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_PWRDWN                  ((uint32_t)0x00010000)            /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN                ((uint32_t)0x00020000)            /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN                ((uint32_t)0x00040000)            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN                ((uint32_t)0x00080000)            /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN                ((uint32_t)0x00100000)            /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS              ((uint32_t)0x00200000)            /*!< VBUS sensing disable option */
+
+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM                ((uint32_t)0x00000002)            /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM                ((uint32_t)0x00020000)            /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition forUSB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID              ((uint32_t)0xFFFFFFFF)            /*!< Product ID field */
+
+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM                     ((uint32_t)0x00000008)            /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020)            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100)            /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM                     ((uint32_t)0x00000200)            /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM                    ((uint32_t)0x00002000)            /*!< NAK interrupt mask */
+
+/********************  Bit definition forUSB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS                   ((uint32_t)0x00000001)            /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET                   ((uint32_t)0x00000002)            /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA                    ((uint32_t)0x00000004)            /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG                 ((uint32_t)0x00000008)            /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA                    ((uint32_t)0x00000010)            /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG                 ((uint32_t)0x00000020)            /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES                    ((uint32_t)0x00000040)            /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP                   ((uint32_t)0x00000080)            /*!< Port suspend */
+#define USB_OTG_HPRT_PRST                    ((uint32_t)0x00000100)            /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS                   ((uint32_t)0x00000C00)            /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                 ((uint32_t)0x00000400)            /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1                 ((uint32_t)0x00000800)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR                    ((uint32_t)0x00001000)            /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL                   ((uint32_t)0x0001E000)            /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                 ((uint32_t)0x00002000)            /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1                 ((uint32_t)0x00004000)            /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2                 ((uint32_t)0x00008000)            /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3                 ((uint32_t)0x00010000)            /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD                    ((uint32_t)0x00060000)            /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                  ((uint32_t)0x00020000)            /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1                  ((uint32_t)0x00040000)            /*!<Bit 1 */
+
+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM                    ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM                     ((uint32_t)0x00000008)            /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK               ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM                 ((uint32_t)0x00000020)            /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM                 ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM                  ((uint32_t)0x00000100)            /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM                     ((uint32_t)0x00000200)            /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM                   ((uint32_t)0x00001000)            /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM                    ((uint32_t)0x00002000)            /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM                   ((uint32_t)0x00004000)            /*!< NYET interrupt mask */
+
+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA                   ((uint32_t)0x0000FFFF)            /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD                   ((uint32_t)0xFFFF0000)            /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ                   ((uint32_t)0x000007FF)            /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP                  ((uint32_t)0x00008000)            /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID              ((uint32_t)0x00010000)            /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS                  ((uint32_t)0x00020000)            /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP                   ((uint32_t)0x000C0000)            /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                 ((uint32_t)0x00040000)            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 ((uint32_t)0x00080000)            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL                   ((uint32_t)0x00200000)            /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM                  ((uint32_t)0x03C00000)            /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                ((uint32_t)0x00400000)            /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                ((uint32_t)0x00800000)            /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                ((uint32_t)0x01000000)            /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                ((uint32_t)0x02000000)            /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK                    ((uint32_t)0x04000000)            /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK                    ((uint32_t)0x08000000)            /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          ((uint32_t)0x10000000)            /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM                 ((uint32_t)0x20000000)            /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS                   ((uint32_t)0x40000000)            /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA                   ((uint32_t)0x80000000)            /*!< Endpoint enable */
+
+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ                   ((uint32_t)0x000007FF)            /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM                   ((uint32_t)0x00007800)            /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                 ((uint32_t)0x00000800)            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1                 ((uint32_t)0x00001000)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2                 ((uint32_t)0x00002000)            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3                 ((uint32_t)0x00004000)            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR                   ((uint32_t)0x00008000)            /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV                   ((uint32_t)0x00020000)            /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP                   ((uint32_t)0x000C0000)            /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                 ((uint32_t)0x00040000)            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1                 ((uint32_t)0x00080000)            /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC                      ((uint32_t)0x00300000)            /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                    ((uint32_t)0x00100000)            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1                    ((uint32_t)0x00200000)            /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD                     ((uint32_t)0x1FC00000)            /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                   ((uint32_t)0x00400000)            /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1                   ((uint32_t)0x00800000)            /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2                   ((uint32_t)0x01000000)            /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3                   ((uint32_t)0x02000000)            /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4                   ((uint32_t)0x04000000)            /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5                   ((uint32_t)0x08000000)            /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6                   ((uint32_t)0x10000000)            /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM                  ((uint32_t)0x20000000)            /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS                   ((uint32_t)0x40000000)            /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA                   ((uint32_t)0x80000000)            /*!< Channel enable */
+
+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR                 ((uint32_t)0x0000007F)            /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0               ((uint32_t)0x00000001)            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1               ((uint32_t)0x00000002)            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2               ((uint32_t)0x00000004)            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3               ((uint32_t)0x00000008)            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4               ((uint32_t)0x00000010)            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5               ((uint32_t)0x00000020)            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6               ((uint32_t)0x00000040)            /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR                 ((uint32_t)0x00003F80)            /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0               ((uint32_t)0x00000080)            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1               ((uint32_t)0x00000100)            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2               ((uint32_t)0x00000200)            /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3               ((uint32_t)0x00000400)            /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4               ((uint32_t)0x00000800)            /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5               ((uint32_t)0x00001000)            /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6               ((uint32_t)0x00002000)            /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS                 ((uint32_t)0x0000C000)            /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0               ((uint32_t)0x00004000)            /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1               ((uint32_t)0x00008000)            /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT               ((uint32_t)0x00010000)            /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN                 ((uint32_t)0x80000000)            /*!< Split enable */
+
+/********************  Bit definition forUSB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC                    ((uint32_t)0x00000001)            /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH                     ((uint32_t)0x00000002)            /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR                  ((uint32_t)0x00000004)            /*!< AHB error */
+#define USB_OTG_HCINT_STALL                   ((uint32_t)0x00000008)            /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK                     ((uint32_t)0x00000010)            /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK                     ((uint32_t)0x00000020)            /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET                    ((uint32_t)0x00000040)            /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR                   ((uint32_t)0x00000080)            /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR                   ((uint32_t)0x00000100)            /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR                   ((uint32_t)0x00000200)            /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR                   ((uint32_t)0x00000400)            /*!< Data toggle error */
+
+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC                    ((uint32_t)0x00000001)            /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD                  ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC                     ((uint32_t)0x00000008)            /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE                  ((uint32_t)0x00000010)            /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE                  ((uint32_t)0x00000040)            /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE                    ((uint32_t)0x00000080)            /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              ((uint32_t)0x00000100)            /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA                     ((uint32_t)0x00000200)            /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS               ((uint32_t)0x00000800)            /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR                    ((uint32_t)0x00001000)            /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK                     ((uint32_t)0x00002000)            /*!< NAK interrupt */
+
+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM                   ((uint32_t)0x00000001)            /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM                    ((uint32_t)0x00000002)            /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR                  ((uint32_t)0x00000004)            /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM                  ((uint32_t)0x00000008)            /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM                    ((uint32_t)0x00000010)            /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM                    ((uint32_t)0x00000020)            /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET                    ((uint32_t)0x00000040)            /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM                  ((uint32_t)0x00000080)            /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM                  ((uint32_t)0x00000100)            /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM                  ((uint32_t)0x00000200)            /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM                  ((uint32_t)0x00000400)            /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFF)            /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000)            /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT                  ((uint32_t)0x60000000)            /*!< Packet count */
+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ                    ((uint32_t)0x0007FFFF)            /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT                    ((uint32_t)0x1FF80000)            /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING                    ((uint32_t)0x80000000)            /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID                      ((uint32_t)0x60000000)            /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    ((uint32_t)0x20000000)            /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1                    ((uint32_t)0x40000000)            /*!<Bit 1 */
+
+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR                  ((uint32_t)0xFFFFFFFF)            /*!< DMA address */
+
+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR                    ((uint32_t)0xFFFFFFFF)            /*!< DMA address */
+
+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV                ((uint32_t)0x0000FFFF)            /*!< IN endpoint TxFIFO space avail */
+
+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA                 ((uint32_t)0x0000FFFF)            /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD                 ((uint32_t)0xFFFF0000)            /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ                     ((uint32_t)0x000007FF)            /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP                    ((uint32_t)0x00008000)            /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS                    ((uint32_t)0x00020000)            /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            ((uint32_t)0x10000000)            /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM                   ((uint32_t)0x20000000)            /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP                     ((uint32_t)0x000C0000)            /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                   ((uint32_t)0x00040000)            /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1                   ((uint32_t)0x00080000)            /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM                      ((uint32_t)0x00100000)            /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL                     ((uint32_t)0x00200000)            /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK                      ((uint32_t)0x04000000)            /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK                      ((uint32_t)0x08000000)            /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS                     ((uint32_t)0x40000000)            /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA                     ((uint32_t)0x80000000)            /*!< Endpoint enable */
+
+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC                    ((uint32_t)0x00000001)            /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD                  ((uint32_t)0x00000002)            /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP                    ((uint32_t)0x00000008)            /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS                 ((uint32_t)0x00000010)            /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP                 ((uint32_t)0x00000040)            /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET                    ((uint32_t)0x00004000)            /*!< NYET interrupt */
+
+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  ((uint32_t)0x0007FFFF)            /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  ((uint32_t)0x1FF80000)            /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT                 ((uint32_t)0x60000000)            /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               ((uint32_t)0x20000000)            /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               ((uint32_t)0x40000000)            /*!<Bit 1 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK                 ((uint32_t)0x00000001)            /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK                 ((uint32_t)0x00000002)            /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 ((uint32_t)0x00000010)            /*!<Bit 1 */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+ 
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+ 
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+                                              ((INSTANCE) == DMA1_Stream1) || \
+                                              ((INSTANCE) == DMA1_Stream2) || \
+                                              ((INSTANCE) == DMA1_Stream3) || \
+                                              ((INSTANCE) == DMA1_Stream4) || \
+                                              ((INSTANCE) == DMA1_Stream5) || \
+                                              ((INSTANCE) == DMA1_Stream6) || \
+                                              ((INSTANCE) == DMA1_Stream7) || \
+                                              ((INSTANCE) == DMA2_Stream0) || \
+                                              ((INSTANCE) == DMA2_Stream1) || \
+                                              ((INSTANCE) == DMA2_Stream2) || \
+                                              ((INSTANCE) == DMA2_Stream3) || \
+                                              ((INSTANCE) == DMA2_Stream4) || \
+                                              ((INSTANCE) == DMA2_Stream5) || \
+                                              ((INSTANCE) == DMA2_Stream6) || \
+                                              ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
+                                    ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \
+                                      ((INSTANCE) == SPI3)    || \
+                                      ((INSTANCE) == I2S2ext) || \
+                                      ((INSTANCE) == I2S3ext))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3) || \
+                                       ((INSTANCE) == SPI4))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
+                                           ((INSTANCE) == SPI2)    || \
+                                           ((INSTANCE) == SPI3)    || \
+                                           ((INSTANCE) == I2S2ext) || \
+                                           ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                   ((INSTANCE) == TIM2)   || \
+                                   ((INSTANCE) == TIM3)   || \
+                                   ((INSTANCE) == TIM4)   || \
+                                   ((INSTANCE) == TIM5)   || \
+                                   ((INSTANCE) == TIM9)   || \
+                                   ((INSTANCE) == TIM10)  || \
+                                   ((INSTANCE) == TIM11))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
+                                         ((INSTANCE) == TIM2)  || \
+                                         ((INSTANCE) == TIM3)  || \
+                                         ((INSTANCE) == TIM4)  || \
+                                         ((INSTANCE) == TIM5)  || \
+                                         ((INSTANCE) == TIM9)  || \
+                                         ((INSTANCE) == TIM10) || \
+                                         ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                       ((INSTANCE) == TIM2) || \
+                                       ((INSTANCE) == TIM3) || \
+                                       ((INSTANCE) == TIM4) || \
+                                       ((INSTANCE) == TIM5) || \
+                                       ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
+                                         ((INSTANCE) == TIM2) || \
+                                         ((INSTANCE) == TIM3) || \
+                                         ((INSTANCE) == TIM4) || \
+                                         ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                       ((INSTANCE) == TIM2) || \
+                                       ((INSTANCE) == TIM3) || \
+                                       ((INSTANCE) == TIM4) || \
+                                       ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
+                                         ((INSTANCE) == TIM2) || \
+                                         ((INSTANCE) == TIM3) || \
+                                         ((INSTANCE) == TIM4) || \
+                                         ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                       ((INSTANCE) == TIM2) || \
+                                       ((INSTANCE) == TIM3) || \
+                                       ((INSTANCE) == TIM4) || \
+                                       ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                          ((INSTANCE) == TIM2) || \
+                                          ((INSTANCE) == TIM3) || \
+                                          ((INSTANCE) == TIM4) || \
+                                          ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                          ((INSTANCE) == TIM2) || \
+                                          ((INSTANCE) == TIM3) || \
+                                          ((INSTANCE) == TIM4) || \
+                                          ((INSTANCE) == TIM5)) 
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                             ((INSTANCE) == TIM2) || \
+                                             ((INSTANCE) == TIM3) || \
+                                             ((INSTANCE) == TIM4) || \
+                                             ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                          ((INSTANCE) == TIM2) || \
+                                          ((INSTANCE) == TIM3) || \
+                                          ((INSTANCE) == TIM4) || \
+                                          ((INSTANCE) == TIM5) || \
+                                          ((INSTANCE) == TIM9))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                         ((INSTANCE) == TIM2) || \
+                                         ((INSTANCE) == TIM3) || \
+                                         ((INSTANCE) == TIM4) || \
+                                         ((INSTANCE) == TIM5) || \
+                                         ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+                                              ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                        ((INSTANCE) == TIM2) || \
+                                        ((INSTANCE) == TIM3) || \
+                                        ((INSTANCE) == TIM4) || \
+                                        ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                         ((INSTANCE) == TIM5)  || \
+                                         ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM2) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM3) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM4) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM5) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM9) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+    ||                                         \
+    (((INSTANCE) == TIM10) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((INSTANCE) == TIM11) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART6))     
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F401xE_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,223 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx.h
+  * @author  MCD Application Team
+  * @version V2.1.0RC2
+  * @date    14-May-2014
+  * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.           
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32F4xx device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral’s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_HAL_DRIVER"
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx
+  * @{
+  */
+    
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+   
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+    !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+    !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE)
+  /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+  /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+  /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
+  /* #define STM32F417xx */   /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+  /* #define STM32F427xx */   /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+  /* #define STM32F437xx */   /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+  /* #define STM32F429xx */   /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, 
+                                   STM32F439NI, STM32F429IG  and STM32F429II Devices */
+  /* #define STM32F439xx */   /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, 
+                                   STM32F439NI, STM32F439IG and STM32F439II Devices */
+  /* #define STM32F401xC */   /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+#define STM32F401xE           /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+  /* #define STM32F411xE */   /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */     
+#endif
+   
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V2.1.0RC2
+  */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC     (0x02) /*!< [7:0]  release candidate */ 
+#define __STM32F4xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_RC))
+                                             
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32F405xx)
+  #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+  #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+  #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+  #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+  #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+  #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+  #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+  #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+  #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+  #include "stm32f401xe.h"
+#elif defined(STM32F411xE)
+  #include "stm32f411xe.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */ 
+typedef enum 
+{
+  RESET = 0, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum 
+{
+  DISABLE = 0, 
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum 
+{
+  ERROR = 0, 
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,537 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   HAL module driver.
+  *          This is the common part of the HAL initialization
+  *
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The common HAL driver contains a set of generic and common APIs that can be
+    used by the PPP peripheral drivers and the user to start using the HAL. 
+    [..]
+    The HAL contains two APIs' categories: 
+         (+) Common HAL APIs
+         (+) Services HAL APIs
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL 
+  * @brief HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/**
+ * @brief STM32F4xx HAL Driver version number V1.1.0RC2
+   */
+#define __STM32F4xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32F4xx_HAL_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
+#define __STM32F4xx_HAL_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_HAL_VERSION_RC     (0x02) /*!< [7:0]  release candidate */ 
+#define __STM32F4xx_HAL_VERSION         ((__STM32F4xx_HAL_VERSION_MAIN << 24)\
+                                        |(__STM32F4xx_HAL_VERSION_SUB1 << 16)\
+                                        |(__STM32F4xx_HAL_VERSION_SUB2 << 8 )\
+                                        |(__STM32F4xx_HAL_VERSION_RC))
+                                        
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
+/* ---  MEMRMP Register ---*/ 
+/* Alias word address of UFB_MODE bit */ 
+#define MEMRMP_OFFSET             SYSCFG_OFFSET 
+#define UFB_MODE_BitNumber        ((uint8_t)0x8) 
+#define UFB_MODE_BB               (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BitNumber * 4)) 
+
+/* ---  CMPCR Register ---*/ 
+/* Alias word address of CMP_PD bit */ 
+#define CMPCR_OFFSET              (SYSCFG_OFFSET + 0x20) 
+#define CMP_PD_BitNumber          ((uint8_t)0x00) 
+#define CMPCR_CMP_PD_BB           (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4))
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static __IO uint32_t uwTick;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_Private_Functions
+  * @{
+  */
+
+/** @defgroup HAL_Group1 Initialization and de-initialization Functions 
+ *  @brief    Initialization and de-initialization functions
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initializes the Flash interface the NVIC allocation and initial clock 
+          configuration. It initializes the systick also when timeout is needed 
+          and the backup domain when enabled.
+      (+) de-Initializes common part of the HAL
+      (+) Configure The time base source to have 1ms time base with a dedicated 
+          Tick interrupt priority. 
+        (++) Systick timer is used by default as source of time base, but user 
+             can eventually implement his proper time base source (a general purpose 
+             timer for example or other time source), keeping in mind that Time base 
+             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+             handled in milliseconds basis.
+        (++) Time base configuration function (HAL_InitTick ()) is called automatically 
+             at the beginning of the program after reset by HAL_Init() or at any time 
+             when clock is configured, by HAL_RCC_ClockConfig(). 
+        (++) Source of time base is configured  to generate interrupts at regular 
+             time intervals. Care must be taken if HAL_Delay() is called from a 
+             peripheral ISR process, the Tick interrupt line must have higher priority 
+            (numerically lower) than the peripheral interrupt. Otherwise the caller 
+            ISR process will be blocked. 
+       (++) functions affecting time base configurations are declared as __weak  
+             to make  override possible  in case of other  implementations in user file.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function is used to initialize the HAL Library; it must be the first 
+  *         instruction to be executed in the main program (before to call any other
+  *         HAL function), it performs the following:
+  *           Configure the Flash prefetch, instruction and Data caches.
+  *           Configures the SysTick to generate an interrupt each 1 millisecond,
+  *           which is clocked by the HSI (at this stage, the clock is not yet
+  *           configured and thus the system is running from the internal HSI at 16 MHz).
+  *           Set NVIC Group Priority to 4.
+  *           Calls the HAL_MspInit() callback function defined in user file 
+  *           "stm32f4xx_hal_msp.c" to do the global low level hardware initialization 
+  *            
+  * @note   SysTick is used as time base for the HAL_Delay() function, the application
+  *         need to ensure that the SysTick time base is always set to 1 millisecond
+  *         to have correct HAL operation.
+  * @param  None
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_Init(void)
+{
+  /* Configure Flash prefetch, Instruction cache, Data cache */ 
+#if (INSTRUCTION_CACHE_ENABLE != 0)
+   __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+#endif /* INSTRUCTION_CACHE_ENABLE */
+
+#if (DATA_CACHE_ENABLE != 0)
+   __HAL_FLASH_DATA_CACHE_ENABLE();
+#endif /* DATA_CACHE_ENABLE */
+
+#if (PREFETCH_ENABLE != 0)
+  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+  /* Set Interrupt Group Priority */
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+  HAL_InitTick(TICK_INT_PRIORITY);
+  
+  /* Init the low level hardware */
+  HAL_MspInit();
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function de-Initializes common part of the HAL and stops the systick.
+  *         This function is optional.   
+  * @param  None
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+  /* Reset of all peripherals */
+  __APB1_FORCE_RESET();
+  __APB1_RELEASE_RESET();
+
+  __APB2_FORCE_RESET();
+  __APB2_RELEASE_RESET();
+
+  __AHB1_FORCE_RESET();
+  __AHB1_RELEASE_RESET();
+
+  __AHB2_FORCE_RESET();
+  __AHB2_RELEASE_RESET();
+
+  __AHB3_FORCE_RESET();
+  __AHB3_RELEASE_RESET();
+
+  /* De-Init the low level hardware */
+  HAL_MspDeInit();
+    
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the MSP.
+  * @param  None
+  * @retval None
+  */
+__weak void HAL_MspInit(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the MSP.
+  * @param  None  
+  * @retval None
+  */
+__weak void HAL_MspDeInit(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief This function configures the source of the time base.
+  *        The time source is configured  to have 1ms time base with a dedicated 
+  *        Tick interrupt priority.
+  * @note This function is called  automatically at the beginning of program after
+  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
+  * @note In the default implementation, SysTick timer is the source of time base. 
+  *       It is used to generate interrupts at regular time intervals. 
+  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process, 
+  *       The the SysTick interrupt must have higher priority (numerically lower) 
+  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+  *       The function is declared as __weak  to be overwritten  in case of other
+  *       implementation  in user file.
+  * @param TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  /*Configure the SysTick to have interrupt in 1ms time basis*/
+  HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
+
+  /*Configure the SysTick IRQ priority */
+  HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Group2 HAL Control functions 
+ *  @brief    HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### HAL Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Provide a tick value in millisecond
+      (+) Provide a blocking delay in millisecond
+      (+) Suspend the time base source interrupt
+      (+) Resume the time base source interrupt
+      (+) Get the HAL API driver version
+      (+) Get the device identifier
+      (+) Get the device revision identifier
+      (+) Enable/Disable Debug module during SLEEP mode
+      (+) Enable/Disable Debug module during STOP mode
+      (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief This function is called to increment  a global variable "uwTick"
+  *        used as application time base.
+  * @note In the default implementation, this variable is incremented each 1ms
+  *       in Systick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other 
+  *      implementations in user file.
+  * @param None
+  * @retval None
+  */
+__weak void HAL_IncTick(void)
+{
+  uwTick++;
+}
+
+/**
+  * @brief Provides a tick value in millisecond.
+  * @note This function is declared as __weak to be overwritten in case of other 
+  *       implementations in user file.
+  * @param None
+  * @retval tick value
+  */
+__weak uint32_t HAL_GetTick(void)
+{
+  return uwTick;
+}
+
+/**
+  * @brief This function provides accurate delay (in milliseconds) based 
+  *        on variable incremented.
+  * @note In the default implementation , SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals where uwTick
+  *       is incremented.
+  * @note ThiS function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @param Delay: specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+__weak void HAL_Delay(__IO uint32_t Delay)
+{
+  uint32_t tickstart = 0;
+  tickstart = HAL_GetTick();
+  while((HAL_GetTick() - tickstart) < Delay)
+  {
+  }
+}
+
+/**
+  * @brief Suspend Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+  *       is called, the the SysTick interrupt will be disabled and so Tick increment 
+  *       is suspended.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @param None
+  * @retval None
+  */
+__weak void HAL_SuspendTick(void)
+{
+  /* Disable SysTick Interrupt */
+  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief Resume Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+  *       is called, the the SysTick interrupt will be enabled and so Tick increment 
+  *       is resumed.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @param None
+  * @retval None
+  */
+__weak void HAL_ResumeTick(void)
+{
+  /* Enable SysTick Interrupt */
+  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief  Returns the HAL revision
+  * @param  None
+  * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+  */
+uint32_t HAL_GetHalVersion(void)
+{
+ return __STM32F4xx_HAL_VERSION;
+}
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @param  None
+  * @retval Device revision identifier
+  */
+uint32_t HAL_GetREVID(void)
+{
+   return((DBGMCU->IDCODE) >> 16);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @param  None
+  * @retval Device identifier
+  */
+uint32_t HAL_GetDEVID(void)
+{
+   return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
+}
+
+/**
+  * @brief  Enable the Debug Module during SLEEP mode
+  * @param  None
+  * @retval None
+  */
+void HAL_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Disable the Debug Module during SLEEP mode
+  * @param  None
+  * @retval None
+  */
+void HAL_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STOP mode
+  * @param  None
+  * @retval None
+  */
+void HAL_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Disable the Debug Module during STOP mode
+  * @param  None
+  * @retval None
+  */
+void HAL_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STANDBY mode
+  * @param  None
+  * @retval None
+  */
+void HAL_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Disable the Debug Module during STANDBY mode
+  * @param  None
+  * @retval None
+  */
+void HAL_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Enables the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.  
+  * @retval None
+  */
+void HAL_EnableCompensationCell(void)
+{
+  *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief  Power-down the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.  
+  * @retval None
+  */
+void HAL_DisableCompensationCell(void)
+{
+  *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE;
+}
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/**
+  * @brief  Enables the Internal FLASH Bank Swapping.
+  *   
+  * @note   This function can be used only for STM32F42xxx/43xxx devices. 
+  *
+  * @note   Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) 
+  *         and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)   
+  *
+  * @retval None
+  */
+void HAL_EnableMemorySwappingBank(void)
+{
+  *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief  Disables the Internal FLASH Bank Swapping.
+  *   
+  * @note   This function can be used only for STM32F42xxx/43xxx devices. 
+  *
+  * @note   The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000) 
+  *         and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) 
+  *           
+  * @retval None
+  */
+void HAL_DisableMemorySwappingBank(void)
+{
+
+  *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE;
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,195 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   This file contains all the functions prototypes for the HAL 
+  *          module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_H
+#define __STM32F4xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_conf.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HAL
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief  Freeze/Unfreeze Peripherals in Debug mode 
+  */
+#define __HAL_FREEZE_TIM2_DBGMCU()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_FREEZE_TIM3_DBGMCU()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_FREEZE_TIM4_DBGMCU()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_FREEZE_TIM5_DBGMCU()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_FREEZE_TIM6_DBGMCU()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_FREEZE_TIM7_DBGMCU()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_FREEZE_TIM12_DBGMCU()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_FREEZE_TIM13_DBGMCU()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_FREEZE_TIM14_DBGMCU()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_FREEZE_RTC_DBGMCU()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_FREEZE_WWDG_DBGMCU()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_FREEZE_IWDG_DBGMCU()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_FREEZE_CAN1_DBGMCU()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
+#define __HAL_FREEZE_CAN2_DBGMCU()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
+#define __HAL_FREEZE_TIM1_DBGMCU()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_FREEZE_TIM8_DBGMCU()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_FREEZE_TIM9_DBGMCU()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
+#define __HAL_FREEZE_TIM10_DBGMCU()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
+#define __HAL_FREEZE_TIM11_DBGMCU()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
+
+#define __HAL_UNFREEZE_TIM2_DBGMCU()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_UNFREEZE_TIM3_DBGMCU()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_UNFREEZE_TIM4_DBGMCU()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_UNFREEZE_TIM5_DBGMCU()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_UNFREEZE_TIM6_DBGMCU()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_UNFREEZE_TIM7_DBGMCU()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_UNFREEZE_TIM12_DBGMCU()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_UNFREEZE_TIM13_DBGMCU()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_UNFREEZE_TIM14_DBGMCU()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_UNFREEZE_RTC_DBGMCU()            (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_UNFREEZE_WWDG_DBGMCU()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_UNFREEZE_IWDG_DBGMCU()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_UNFREEZE_CAN1_DBGMCU()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
+#define __HAL_UNFREEZE_CAN2_DBGMCU()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
+#define __HAL_UNFREEZE_TIM1_DBGMCU()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_UNFREEZE_TIM8_DBGMCU()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_UNFREEZE_TIM9_DBGMCU()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
+#define __HAL_UNFREEZE_TIM10_DBGMCU()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
+#define __HAL_UNFREEZE_TIM11_DBGMCU()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
+
+/** @brief  Main Flash memory mapped at 0x00000000
+  */
+#define __HAL_REMAPMEMORY_FLASH()             (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
+
+/** @brief  System Flash memory mapped at 0x00000000
+  */
+#define __HAL_REMAPMEMORY_SYSTEMFLASH()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+                                                  SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
+                                                 }while(0);
+
+/** @brief  Embedded SRAM mapped at 0x00000000
+  */
+#define __HAL_REMAPMEMORY_SRAM()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+                                           SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
+                                          }while(0);
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+/** @brief  FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
+  */
+#define __HAL_REMAPMEMORY_FSMC()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+                                           SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
+                                          }while(0);
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 
+/** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
+  */
+#define __HAL_REMAPMEMORY_FMC()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+                                          SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
+                                         }while(0);
+
+/** @brief  FMC/SDRAM Bank 1 and 2 mapped at 0x00000000
+  */
+#define __HAL_REMAPMEMORY_FMC_SDRAM()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+                                                SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
+                                               }while(0);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+
+/* Peripheral Control functions  ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(__IO uint32_t Delay);
+uint32_t HAL_GetTick(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+void HAL_EnableDBGSleepMode(void);
+void HAL_DisableDBGSleepMode(void);
+void HAL_EnableDBGStopMode(void);
+void HAL_DisableDBGStopMode(void);
+void HAL_EnableDBGStandbyMode(void);
+void HAL_DisableDBGStandbyMode(void);
+void HAL_EnableCompensationCell(void);
+void HAL_DisableCompensationCell(void);
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+void HAL_EnableMemorySwappingBank(void);
+void HAL_DisableMemorySwappingBank(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1290 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_adc.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Analog to Digital Convertor (ADC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + State and errors functions
+  *         
+  @verbatim
+  ==============================================================================
+                    ##### ADC Peripheral features #####
+  ==============================================================================
+  [..] 
+  (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
+  (#) Interrupt generation at the end of conversion, end of injected conversion,  
+      and in case of analog watchdog or overrun events
+  (#) Single and continuous conversion modes.
+  (#) Scan mode for automatic conversion of channel 0 to channel x.
+  (#) Data alignment with in-built data coherency.
+  (#) Channel-wise programmable sampling time.
+  (#) External trigger option with configurable polarity for both regular and 
+      injected conversion.
+  (#) Dual/Triple mode (on devices with 2 ADCs or more).
+  (#) Configurable DMA data storage in Dual/Triple ADC mode. 
+  (#) Configurable delay between conversions in Dual/Triple interleaved mode.
+  (#) ADC conversion type (refer to the datasheets).
+  (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at 
+      slower speed.
+  (#) ADC input range: VREF(minus) = VIN = VREF(plus).
+  (#) DMA request generation during regular channel conversion.
+
+
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
+       (##) Enable the ADC interface clock using __ADC_CLK_ENABLE()
+       (##) ADC pins configuration
+             (+++) Enable the clock for the ADC GPIOs using the following function:
+                   __GPIOx_CLK_ENABLE()  
+             (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() 
+       (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
+             (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
+             (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
+             (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
+      (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
+             (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+             (+++) Configure and enable two DMA streams stream for managing data
+                 transfer from peripheral to memory (output stream)
+             (+++) Associate the initilalized DMA handle to the CRYP DMA handle
+                 using  __HAL_LINKDMA()
+             (+++) Configure the priority and enable the NVIC for the transfer complete
+                 interrupt on the two DMA Streams. The output stream should have higher
+                 priority than the input stream.
+                       
+     (#) Configure the ADC Prescaler, conversion resolution and data alignment 
+         using the HAL_ADC_Init() function.
+         
+     (#) Configure the ADC regular channels group features, use HAL_ADC_Init()
+         and HAL_ADC_ConfigChannel() functions.
+         
+     (#) Three operation modes are available within this driver :     
+  
+     *** Polling mode IO operation ***
+     =================================
+     [..]    
+       (+) Start the ADC peripheral using HAL_ADC_Start() 
+       (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
+           user can specify the value of timeout according to his end application      
+       (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
+       (+) Stop the ADC peripheral using HAL_ADC_Stop()
+       
+     *** Interrupt mode IO operation ***    
+     ===================================
+     [..]    
+       (+) Start the ADC peripheral using HAL_ADC_Start_IT() 
+       (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
+       (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can 
+            add his own code by customization of function pointer HAL_ADC_ConvCpltCallback 
+       (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can 
+            add his own code by customization of function pointer HAL_ADC_ErrorCallback
+        (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()     
+
+     *** DMA mode IO operation ***    
+     ==============================
+     [..]    
+       (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length 
+           of data to be transferred at each end of conversion 
+       (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can 
+            add his own code by customization of function pointer HAL_ADC_ConvCpltCallback 
+       (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can 
+            add his own code by customization of function pointer HAL_ADC_ErrorCallback
+       (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
+                    
+     *** ADC HAL driver macros list ***
+     ============================================= 
+     [..]
+       Below the list of most used macros in ADC HAL driver.
+       
+      (+) __HAL_ADC_ENABLE : Enable the ADC peripheral
+      (+) __HAL_ADC_DISABLE : Disable the ADC peripheral
+      (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
+      (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
+      (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
+      (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
+      (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
+      (+) __HAL_ADC_GET_RESOLUTION: Return resolution bits in CR1 register 
+      
+     [..] 
+       (@) You can refer to the ADC HAL driver header file for more useful macros          
+  
+    @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADC 
+  * @brief ADC driver modules
+  * @{
+  */ 
+
+#ifdef HAL_ADC_MODULE_ENABLED
+    
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/ 
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void ADC_Init(ADC_HandleTypeDef* hadc);
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_DMAError(DMA_HandleTypeDef *hdma);
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup ADC_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the ADC. 
+      (+) De-initialize the ADC. 
+         
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the ADCx peripheral according to the specified parameters 
+  *         in the ADC_InitStruct and initializes the ADC MSP.
+  *           
+  * @note   This function is used to configure the global features of the ADC ( 
+  *         ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
+  *         the rest of the configuration parameters are specific to the regular
+  *         channels group (scan mode activation, continuous mode activation,
+  *         External trigger source and edge, DMA continuous request after the  
+  *         last transfer and End of conversion selection).
+  *             
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
+{
+  /* Check ADC handle */
+  if(hadc == NULL)
+  {
+     return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+  assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 
+  assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
+  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+  assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+  assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+  
+  if(hadc->State == HAL_ADC_STATE_RESET)
+  {
+    /* Init the low level hardware */
+    HAL_ADC_MspInit(hadc);
+  }
+  
+  /* Initialize the ADC state */
+  hadc->State = HAL_ADC_STATE_BUSY;
+  
+  /* Set ADC parameters */
+  ADC_Init(hadc);
+  
+  /* Set ADC error code to none */
+  hadc->ErrorCode = HAL_ADC_ERROR_NONE;
+  
+  /* Initialize the ADC state */
+  hadc->State = HAL_ADC_STATE_READY;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deinitializes the ADCx peripheral registers to their default reset values. 
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
+{
+  /* Check ADC handle */
+  if(hadc == NULL)
+  {
+     return HAL_ERROR;
+  } 
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Change ADC state */
+  hadc->State = HAL_ADC_STATE_BUSY;
+  
+  /* DeInit the low level hardware */
+  HAL_ADC_MspDeInit(hadc);
+  
+  /* Set ADC error code to none */
+  hadc->ErrorCode = HAL_ADC_ERROR_NONE;
+  
+  /* Change ADC state */
+  hadc->State = HAL_ADC_STATE_RESET;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the ADC MSP.
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.  
+  * @retval None
+  */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_ADC_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  DeInitializes the ADC MSP.
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.  
+  * @retval None
+  */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_ADC_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group2 IO operation functions
+ *  @brief    IO operation functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### IO operation functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Start conversion of regular channel.
+      (+) Stop conversion of regular channel.
+      (+) Start conversion of regular channel and enable interrupt.
+      (+) Stop conversion of regular channel and disable interrupt.
+      (+) Start conversion of regular channel and enable DMA transfer.
+      (+) Stop conversion of regular channel and disable DMA transfer.
+      (+) Handle ADC interrupt request. 
+               
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables ADC and starts conversion of the regular channels.
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
+{
+  uint16_t i = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Check if an injected conversion is ongoing */
+  if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
+  {
+    /* Change ADC state */
+    hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;  
+  }
+  else
+  {
+    /* Change ADC state */
+    hadc->State = HAL_ADC_STATE_BUSY_REG;
+  } 
+    
+  /* Check if ADC peripheral is disabled in order to enable it and wait during 
+     Tstab time the ADC's stabilization */
+  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+  {  
+    /* Enable the Peripheral */
+    __HAL_ADC_ENABLE(hadc);
+    
+    /* Delay inserted to wait during Tstab time the ADC's stabilazation */
+    for(; i <= 540; i++)
+    {
+      __NOP();
+    }
+  }
+
+  /* Check if Multimode enabled */
+  if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+  {
+    /* if no external trigger present enable software conversion of regular channels */
+    if(hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
+    {
+      /* Enable the selected ADC software conversion for regular group */
+      hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+    }
+  }
+  else
+  {
+    /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
+    if((hadc->Instance == ADC1) && (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
+    {
+      /* Enable the selected ADC software conversion for regular group */
+        hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+    }
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables ADC and stop conversion of regular channels.
+  * 
+  * @note   Caution: This function will stop also injected channels.  
+  *
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  *
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
+{
+  /* Disable the Peripheral */
+  __HAL_ADC_DISABLE(hadc);
+  
+  /* Change ADC state */
+  hadc->State = HAL_ADC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Poll for regular conversion complete
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @param  Timeout: Timeout value in millisecond.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+  uint32_t timeout;
+ 
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;  
+
+  /* Check End of conversion flag */
+  while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        hadc->State= HAL_ADC_STATE_TIMEOUT;
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Check if an injected conversion is ready */
+  if(hadc->State == HAL_ADC_STATE_EOC_INJ)
+  {
+    /* Change ADC state */
+    hadc->State = HAL_ADC_STATE_EOC_INJ_REG;  
+  }
+  else
+  {
+    /* Change ADC state */
+    hadc->State = HAL_ADC_STATE_EOC_REG;
+  }
+  
+  /* Return ADC state */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Poll for conversion event
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @param  EventType: the ADC event type.
+  *          This parameter can be one of the following values:
+  *            @arg AWD_EVENT: ADC Analog watch Dog event.
+  *            @arg OVR_EVENT: ADC Overrun event.
+  * @param  Timeout: Timeout value in millisecond.   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_EVENT_TYPE(EventType));
+  
+  uint32_t timeout; 
+
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;   
+
+  /* Check selected event flag */
+  while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        hadc->State= HAL_ADC_STATE_TIMEOUT;
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Check analog watchdog flag */
+  if(EventType == AWD_EVENT)
+  {
+     /* Change ADC state */
+     hadc->State = HAL_ADC_STATE_AWD;
+      
+     /* Clear the ADCx's analog watchdog flag */
+     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+  }
+  else
+  {
+     /* Change ADC state */
+     hadc->State = HAL_ADC_STATE_ERROR;
+     
+     /* Clear the ADCx's Overrun flag */
+     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+  }
+  
+  /* Return ADC state */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Enables the interrupt and starts ADC conversion of regular channels.
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
+{
+  uint16_t i = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Check if an injected conversion is ongoing */
+  if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
+  {
+    /* Change ADC state */
+    hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;  
+  }
+  else
+  {
+    /* Change ADC state */
+    hadc->State = HAL_ADC_STATE_BUSY_REG;
+  } 
+  
+  /* Set ADC error code to none */
+  hadc->ErrorCode = HAL_ADC_ERROR_NONE;
+  
+  /* Check if ADC peripheral is disabled in order to enable it and wait during 
+     Tstab time the ADC's stabilization */
+  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+  {  
+    /* Enable the Peripheral */
+    __HAL_ADC_ENABLE(hadc);
+    
+    /* Delay inserted to wait during Tstab time the ADC's stabilazation */
+    for(; i <= 540; i++)
+    {
+      __NOP();
+    }
+  }
+  
+  /* Enable the ADC overrun interrupt */
+  __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+  
+  /* Enable the ADC end of conversion interrupt for regular group */
+  __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+  
+  /* Check if Multimode enabled */
+  if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+  {
+    /* if no externel trigger present enable software conversion of regular channels */
+    if (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
+    {
+      /* Enable the selected ADC software conversion for regular group */
+      hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+    }
+  }
+  else
+  {
+    /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
+    if ((hadc->Instance == (ADC_TypeDef*)0x40012000) && (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
+    {
+      /* Enable the selected ADC software conversion for regular group */
+        hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+    }
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables the interrupt and stop ADC conversion of regular channels.
+  * 
+  * @note   Caution: This function will stop also injected channels.  
+  *
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
+{
+  /* Disable the ADC end of conversion interrupt for regular group */
+  __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+  
+  /* Disable the ADC end of conversion interrupt for injected group */
+  __HAL_ADC_DISABLE_IT(hadc, ADC_CR1_JEOCIE);
+  
+  /* Enable the Periphral */
+  __HAL_ADC_DISABLE(hadc);
+  
+  /* Change ADC state */
+  hadc->State = HAL_ADC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handles ADC interrupt request  
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval None
+  */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
+{
+  uint32_t tmp1 = 0, tmp2 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
+  assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
+  
+  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);
+  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);
+  /* Check End of conversion flag for regular channels */
+  if(tmp1 && tmp2)
+  {
+    /* Check if an injected conversion is ready */
+    if(hadc->State == HAL_ADC_STATE_EOC_INJ)
+    {
+      /* Change ADC state */
+      hadc->State = HAL_ADC_STATE_EOC_INJ_REG;  
+    }
+    else
+    {
+      /* Change ADC state */
+      hadc->State = HAL_ADC_STATE_EOC_REG;
+    }
+  
+    if((hadc->Init.ContinuousConvMode == DISABLE) && (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
+    {
+      if(hadc->Init.EOCSelection == EOC_SEQ_CONV)
+      {   
+        /* DISABLE the ADC end of conversion interrupt for regular group */
+        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+        
+        /* DISABLE the ADC overrun interrupt */
+        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+      }
+      else
+      {
+        if (hadc->NbrOfCurrentConversionRank == 0)
+        {
+          hadc->NbrOfCurrentConversionRank = hadc->Init.NbrOfConversion;
+        }
+        
+        /* Decrement the number of conversion when an interrupt occurs */
+        hadc->NbrOfCurrentConversionRank--;
+        
+        /* Check if all conversions are finished */
+        if(hadc->NbrOfCurrentConversionRank == 0)
+        {
+          /* DISABLE the ADC end of conversion interrupt for regular group */
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+          
+          /* DISABLE the ADC overrun interrupt */
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+        }
+      }
+    }
+    
+    /* Conversion complete callback */ 
+    HAL_ADC_ConvCpltCallback(hadc);
+    
+   /* Clear the ADCx flag for regular end of conversion */
+    __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_EOC);
+  }
+  
+  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);
+  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC);                               
+  /* Check End of conversion flag for injected channels */
+  if(tmp1 && tmp2)
+  {
+    /* Check if a regular conversion is ready */
+    if(hadc->State == HAL_ADC_STATE_EOC_REG)
+    {
+      /* Change ADC state */
+      hadc->State = HAL_ADC_STATE_EOC_INJ_REG;  
+    }
+    else
+    {
+      /* Change ADC state */
+      hadc->State = HAL_ADC_STATE_EOC_INJ;
+    }
+    
+    tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+    tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+    if(((hadc->Init.ContinuousConvMode == DISABLE) || tmp1) && tmp2)
+    {
+      /* DISABLE the ADC end of conversion interrupt for injected group */
+      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+    }
+    
+    /* Conversion complete callback */ 
+    HAL_ADCEx_InjectedConvCpltCallback(hadc);
+    
+   /* Clear the ADCx flag for injected end of conversion */
+    __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_JEOC);
+  }
+  
+  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);
+  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD);                          
+  /* Check Analog watchdog flag */
+  if(tmp1 && tmp2)
+  {
+    /* Change ADC state */
+    hadc->State = HAL_ADC_STATE_AWD;
+      
+    /* Clear the ADCx's Analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD);
+    
+    /* Level out of window callback */ 
+    HAL_ADC_LevelOutOfWindowCallback(hadc);
+  }
+  
+  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);
+  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);
+  /* Check Overrun flag */
+  if(tmp1 && tmp2)
+  {
+    /* Change ADC state to overrun state */
+    hadc->State = HAL_ADC_STATE_ERROR;
+    
+    /* Set ADC error code to overrun */
+    hadc->ErrorCode |= HAL_ADC_ERROR_OVR;
+    
+    /* Clear the Overrun flag */
+    __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_OVR);
+    
+    /* Error callback */ 
+    HAL_ADC_ErrorCallback(hadc);
+  }
+}
+
+/**
+  * @brief  Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral  
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @param  pData: The destination Buffer address.
+  * @param  Length: The length of data to be transferred from ADC peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+  uint16_t i = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Enable ADC overrun interrupt */
+  __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+  
+  /* Enable ADC DMA mode */
+  hadc->Instance->CR2 |= ADC_CR2_DMA;
+  
+  /* Set the DMA transfer complete callback */
+  hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+  
+  /* Set the DMA half transfer complete callback */
+  hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+     
+  /* Set the DMA error callback */
+  hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
+  
+  /* Enable the DMA Stream */
+  HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+  
+  /* Change ADC state */
+  hadc->State = HAL_ADC_STATE_BUSY_REG;
+   
+  /* Check if ADC peripheral is disabled in order to enable it and wait during 
+     Tstab time the ADC's stabilization */
+  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+  {  
+    /* Enable the Peripheral */
+    __HAL_ADC_ENABLE(hadc);
+    
+    /* Delay inserted to wait during Tstab time the ADC's stabilazation */
+    for(; i <= 540; i++)
+    {
+      __NOP();
+    }
+  }
+  
+  /* if no external trigger present enable software conversion of regular channels */
+  if (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
+  {
+    /* Enable the selected ADC software conversion for regular group */
+    hadc->Instance->CR2 |= ADC_CR2_SWSTART;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables ADC DMA (Single-ADC mode) and disables ADC peripheral    
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
+{
+  /* Disable the Periphral */
+  __HAL_ADC_DISABLE(hadc);
+  
+  /* Disable ADC overrun interrupt */
+  __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+  
+  /* Disable the selected ADC DMA mode */
+  hadc->Instance->CR2 &= ~ADC_CR2_DMA;
+  
+  /* Disable the ADC DMA Stream */
+  HAL_DMA_Abort(hadc->DMA_Handle);
+  
+  /* Change ADC state */
+  hadc->State = HAL_ADC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Gets the converted value from data register of regular channel.
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval Converted value
+  */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
+{       
+  /* Return the selected ADC converted value */ 
+  return hadc->Instance->DR;
+}
+
+/**
+  * @brief  Regular conversion complete callback in non blocking mode 
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval None
+  */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_ADC_ConvCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Regular conversion half DMA transfer callback in non blocking mode 
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval None
+  */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Analog watchdog callback in non blocking mode 
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval None
+  */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error ADC callback.
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval None
+  */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_ADC_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup ADC_Group3 Peripheral Control functions
+ *  @brief   	Peripheral Control functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure regular channels. 
+      (+) Configure injected channels.
+      (+) Configure multimode.
+      (+) Configure the analog watch dog.
+      
+@endverbatim
+  * @{
+  */
+
+  /**
+  * @brief  Configures for the selected ADC regular channel its corresponding
+  *         rank in the sequencer and its sample time.
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @param  sConfig: ADC configuration structure. 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+    
+  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
+  if (sConfig->Channel > ADC_CHANNEL_9)
+  {
+    /* Clear the old sample time */
+    hadc->Instance->SMPR1 &= ~__HAL_ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
+    
+    /* Set the new sample time */
+    hadc->Instance->SMPR1 |= __HAL_ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Clear the old sample time */
+    hadc->Instance->SMPR2 &= ~__HAL_ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
+    
+    /* Set the new sample time */
+    hadc->Instance->SMPR2 |= __HAL_ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
+  }
+  
+  /* For Rank 1 to 6 */
+  if (sConfig->Rank < 7)
+  {
+    /* Clear the old SQx bits for the selected rank */
+    hadc->Instance->SQR3 &= ~__HAL_ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
+    
+    /* Set the SQx bits for the selected rank */
+    hadc->Instance->SQR3 |= __HAL_ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
+  }
+  /* For Rank 7 to 12 */
+  else if (sConfig->Rank < 13)
+  {
+    /* Clear the old SQx bits for the selected rank */
+    hadc->Instance->SQR2 &= ~__HAL_ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
+    
+    /* Set the SQx bits for the selected rank */
+    hadc->Instance->SQR2 |= __HAL_ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
+  }
+  /* For Rank 13 to 16 */
+  else
+  {
+    /* Clear the old SQx bits for the selected rank */
+    hadc->Instance->SQR1 &= ~__HAL_ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
+    
+    /* Set the SQx bits for the selected rank */
+    hadc->Instance->SQR1 |= __HAL_ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
+  }
+  
+  /* if ADC1 Channel_18 is selected enable VBAT Channel */
+  if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
+  {
+    /* Enable the VBAT channel*/
+    ADC->CCR |= ADC_CCR_VBATE;
+  }
+  
+  /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
+  if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
+  {
+    /* Enable the TSVREFE channel*/
+    ADC->CCR |= ADC_CCR_TSVREFE;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the analog watchdog.
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @param  AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure 
+  *         that contains the configuration information of ADC analog watchdog.
+  * @retval HAL status	  
+  */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
+{
+#ifdef USE_FULL_ASSERT  
+  uint32_t tmp = 0;
+#endif /* USE_FULL_ASSERT  */  
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));
+  assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
+  assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+
+#ifdef USE_FULL_ASSERT  
+  tmp = __HAL_ADC_GET_RESOLUTION(hadc);
+  assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
+  assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
+#endif /* USE_FULL_ASSERT  */
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  if(AnalogWDGConfig->ITMode == ENABLE)
+  {
+    /* Enable the ADC Analog watchdog interrupt */
+    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
+  }
+  else
+  {
+    /* Disable the ADC Analog watchdog interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
+  }
+  
+  /* Clear AWDEN, JAWDEN and AWDSGL bits */
+  hadc->Instance->CR1 &=  ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);
+  
+  /* Set the analog watchdog enable mode */
+  hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;
+  
+  /* Set the high threshold */
+  hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
+  
+  /* Set the low threshold */
+  hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
+  
+  /* Clear the Analog watchdog channel select bits */
+  hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
+  
+  /* Set the Analog watchdog channel */
+  hadc->Instance->CR1 |= AnalogWDGConfig->Channel;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group4 ADC Peripheral State functions
+ *  @brief   ADC Peripheral State functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### Peripheral State and errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the ADC state
+      (+) Check the ADC Error
+         
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  return the ADC state
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval HAL state
+  */
+HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
+{
+  /* Return ADC state */
+  return hadc->State;
+}
+
+/**
+  * @brief  Return the ADC error code
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval ADC Error Code
+  */
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
+{
+  return hadc->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Initializes the ADCx peripheral according to the specified parameters 
+  *         in the ADC_InitStruct without initializing the ADC MSP.       
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.  
+  * @retval None
+  */
+static void ADC_Init(ADC_HandleTypeDef* hadc)
+{
+  
+  /* Set ADC parameters */
+  /* Set the ADC clock prescaler */
+  ADC->CCR &= ~(ADC_CCR_ADCPRE);
+  ADC->CCR |=  hadc->Init.ClockPrescaler;
+  
+  /* Set ADC scan mode */
+  hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
+  hadc->Instance->CR1 |=  __HAL_ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
+  
+  /* Set ADC resolution */
+  hadc->Instance->CR1 &= ~(ADC_CR1_RES);
+  hadc->Instance->CR1 |=  hadc->Init.Resolution;
+  
+  /* Set ADC data alignment */
+  hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
+  hadc->Instance->CR2 |= hadc->Init.DataAlign;
+  
+  /* Select external trigger to start conversion */
+  hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
+  hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
+
+  /* Select external trigger polarity */
+  hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
+  hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
+  
+  /* Enable or disable ADC continuous conversion mode */
+  hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
+  hadc->Instance->CR2 |= __HAL_ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);
+  
+  if (hadc->Init.DiscontinuousConvMode != DISABLE)
+  {
+    assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
+  
+    /* Enable the selected ADC regular discontinuous mode */
+    hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
+    
+    /* Set the number of channels to be converted in discontinuous mode */
+    hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
+    hadc->Instance->CR1 |=  __HAL_ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
+  }
+  else
+  {
+    /* Disable the selected ADC regular discontinuous mode */
+    hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
+  }
+  
+  /* Set ADC number of conversion */
+  hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
+  hadc->Instance->SQR1 |=  __HAL_ADC_SQR1(hadc->Init.NbrOfConversion);
+  
+  /* Enable or disable ADC DMA continuous request */
+  hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
+  hadc->Instance->CR2 |= __HAL_ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);
+  
+  /* Enable or disable ADC end of conversion selection */
+  hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
+  hadc->Instance->CR2 |= __HAL_ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
+}
+
+/**
+  * @brief  DMA transfer complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)   
+{
+  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    
+  /* Check if an injected conversion is ready */
+  if(hadc->State == HAL_ADC_STATE_EOC_INJ)
+  {
+    /* Change ADC state */
+    hadc->State = HAL_ADC_STATE_EOC_INJ_REG;  
+  }
+  else
+  {
+    /* Change ADC state */
+    hadc->State = HAL_ADC_STATE_EOC_REG;
+  }
+    
+    HAL_ADC_ConvCpltCallback(hadc); 
+}
+
+/**
+  * @brief  DMA half transfer complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
+{
+    ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    /* Conversion complete callback */
+    HAL_ADC_ConvHalfCpltCallback(hadc); 
+}
+
+/**
+  * @brief  DMA error callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void ADC_DMAError(DMA_HandleTypeDef *hdma)   
+{
+    ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    hadc->State= HAL_ADC_STATE_ERROR;
+    /* Set ADC error code to DMA error */
+    hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
+    HAL_ADC_ErrorCallback(hadc); 
+}
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,706 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_adc.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of ADC HAL extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_ADC_H
+#define __STM32F4xx_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+   
+/** 
+  * @brief  HAL State structures definition  
+  */ 
+typedef enum
+{
+  HAL_ADC_STATE_RESET                   = 0x00,    /*!< ADC not yet initialized or disabled */
+  HAL_ADC_STATE_READY                   = 0x01,    /*!< ADC peripheral ready for use */
+  HAL_ADC_STATE_BUSY                    = 0x02,    /*!< An internal process is ongoing */ 
+  HAL_ADC_STATE_BUSY_REG                = 0x12,    /*!< Regular conversion is ongoing */
+  HAL_ADC_STATE_BUSY_INJ                = 0x22,    /*!< Injected conversion is ongoing */
+  HAL_ADC_STATE_BUSY_INJ_REG            = 0x32,    /*!< Injected and regular conversion are ongoing */
+  HAL_ADC_STATE_TIMEOUT                 = 0x03,    /*!< Timeout state */
+  HAL_ADC_STATE_ERROR                   = 0x04,    /*!< ADC state error */
+  HAL_ADC_STATE_EOC                     = 0x05,    /*!< Conversion is completed */
+  HAL_ADC_STATE_EOC_REG                 = 0x15,    /*!< Regular conversion is completed */
+  HAL_ADC_STATE_EOC_INJ                 = 0x25,    /*!< Injected conversion is completed */
+  HAL_ADC_STATE_EOC_INJ_REG             = 0x35,    /*!< Injected and regular conversion are completed */
+  HAL_ADC_STATE_AWD                     = 0x06    /*!< ADC state analog watchdog */
+
+}HAL_ADC_StateTypeDef;
+
+/** 
+  * @brief   ADC Init structure definition  
+  */ 
+typedef struct
+{
+  uint32_t ClockPrescaler;        /*!< Select the frequency of the clock to the ADC. The clock is common for 
+                                       all the ADCs.
+                                       This parameter can be a value of @ref ADC_ClockPrescaler */
+  uint32_t Resolution;            /*!< Configures the ADC resolution dual mode. 
+                                       This parameter can be a value of @ref ADC_Resolution */
+  uint32_t DataAlign;             /*!< Specifies whether the ADC data  alignment is left or right.  
+                                       This parameter can be a value of @ref ADC_data_align */
+  uint32_t ScanConvMode;          /*!< Specifies whether the conversion is performed in Scan (multi channels) or 
+                                       Single (one channel) mode.
+                                       This parameter can be set to ENABLE or DISABLE */ 
+  uint32_t EOCSelection;          /*!< Specifies whether the EOC flag is set 
+                                       at the end of single channel conversion or at the end of all conversions.
+                                       This parameter can be a value of @ref ADC_EOCSelection */
+  uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in Continuous or Single mode.
+                                       This parameter can be set to ENABLE or DISABLE. */
+  uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode.
+                                       This parameter can be set to ENABLE or DISABLE. */ 
+  uint32_t NbrOfConversion;       /*!< Specifies the number of ADC conversions that will be done using the sequencer for
+                                       regular channel group.
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
+  uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous or not 
+                                       for regular channels.
+                                       This parameter can be set to ENABLE or DISABLE. */
+  uint32_t NbrOfDiscConversion;   /*!< Specifies the number of ADC discontinuous conversions that will be done 
+                                       using the sequencer for regular channel group.
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+  uint32_t ExternalTrigConvEdge;  /*!< Select the external trigger edge and enable the trigger of a regular group. 
+                                       This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
+  uint32_t ExternalTrigConv;      /*!< Select the external event used to trigger the start of conversion of a regular group.
+                                       This parameter can be a value of @ref ADC_External_trigger_Source_Regular */ 
+}ADC_InitTypeDef;
+
+/** 
+  * @brief  ADC handle Structure definition
+  */ 
+typedef struct
+{
+  ADC_TypeDef                   *Instance;                   /*!< Register base address */
+
+  ADC_InitTypeDef               Init;                        /*!< ADC required parameters */
+
+  __IO uint32_t                 NbrOfCurrentConversionRank;  /*!< ADC number of current conversion rank */
+
+  DMA_HandleTypeDef             *DMA_Handle;                 /*!< Pointer DMA Handler */
+
+  HAL_LockTypeDef               Lock;                        /*!< ADC locking object */
+
+  __IO HAL_ADC_StateTypeDef     State;                       /*!< ADC communication state */
+
+  __IO uint32_t                 ErrorCode;                   /*!< ADC Error code */
+}ADC_HandleTypeDef;
+
+/** 
+  * @brief   ADC Configuration regular Channel structure definition
+  */ 
+typedef struct 
+{
+  uint32_t Channel;        /*!< The ADC channel to configure. 
+                                This parameter can be a value of @ref ADC_channels */
+  uint32_t Rank;           /*!< The rank in the regular group sequencer. 
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+  uint32_t SamplingTime;   /*!< The sample time value to be set for the selected channel.
+                                This parameter can be a value of @ref ADC_sampling_times */
+  uint32_t Offset;         /*!< Reserved for future use, can be set to 0 */
+}ADC_ChannelConfTypeDef;
+
+/** 
+  * @brief   ADC Configuration multi-mode structure definition  
+  */ 
+typedef struct
+{
+  uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode.
+                                   This parameter can be a value of @ref ADC_analog_watchdog_selection */
+  uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
+                                   This parameter must be a 12-bit value. */     
+  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
+                                   This parameter must be a 12-bit value. */
+  uint32_t Channel;           /*!< Configures ADC channel for the analog watchdog. 
+                                   This parameter has an effect only if watchdog mode is configured on single channel 
+                                   This parameter can be a value of @ref ADC_channels */      
+  uint32_t ITMode;            /*!< Specifies whether the analog watchdog is configured
+                                   is interrupt mode or in polling mode.
+                                   This parameter can be set to ENABLE or DISABLE */
+  uint32_t WatchdogNumber;    /*!< Reserved for future use, can be set to 0 */
+}ADC_AnalogWDGConfTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants
+  * @{
+  */
+
+
+/** @defgroup ADC_Error_Code 
+  * @{
+  */ 
+
+#define HAL_ADC_ERROR_NONE        ((uint32_t)0x00)   /*!< No error             */
+#define HAL_ADC_ERROR_OVR         ((uint32_t)0x01)   /*!< OVR error            */
+#define HAL_ADC_ERROR_DMA         ((uint32_t)0x02)   /*!< DMA transfer error   */
+/**
+  * @}
+  */  
+
+
+/** @defgroup ADC_ClockPrescaler 
+  * @{
+  */ 
+#define ADC_CLOCKPRESCALER_PCLK_DIV2    ((uint32_t)0x00000000)
+#define ADC_CLOCKPRESCALER_PCLK_DIV4    ((uint32_t)ADC_CCR_ADCPRE_0)
+#define ADC_CLOCKPRESCALER_PCLK_DIV6    ((uint32_t)ADC_CCR_ADCPRE_1)
+#define ADC_CLOCKPRESCALER_PCLK_DIV8    ((uint32_t)ADC_CCR_ADCPRE)
+#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK)     (((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \
+                                              ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV4) || \
+                                              ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV6) || \
+                                              ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV8))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_Resolution 
+  * @{
+  */ 
+#define ADC_RESOLUTION12b  ((uint32_t)0x00000000)
+#define ADC_RESOLUTION10b  ((uint32_t)ADC_CR1_RES_0)
+#define ADC_RESOLUTION8b   ((uint32_t)ADC_CR1_RES_1)
+#define ADC_RESOLUTION6b   ((uint32_t)ADC_CR1_RES)
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \
+                                       ((RESOLUTION) == ADC_RESOLUTION10b) || \
+                                       ((RESOLUTION) == ADC_RESOLUTION8b)  || \
+                                       ((RESOLUTION) == ADC_RESOLUTION6b))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_External_trigger_edge_Regular 
+  * @{
+  */ 
+#define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTEN_0)
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CR2_EXTEN_1)
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_EXTEN)
+
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)    || \
+                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)  || \
+                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_External_trigger_Source_Regular 
+  * @{
+  */ 
+#define ADC_EXTERNALTRIGCONV_T1_CC1    ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGCONV_T1_CC2    ((uint32_t)ADC_CR2_EXTSEL_0)
+#define ADC_EXTERNALTRIGCONV_T1_CC3    ((uint32_t)ADC_CR2_EXTSEL_1)
+#define ADC_EXTERNALTRIGCONV_T2_CC2    ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T2_CC3    ((uint32_t)ADC_CR2_EXTSEL_2)
+#define ADC_EXTERNALTRIGCONV_T2_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T2_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
+#define ADC_EXTERNALTRIGCONV_T3_CC1    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T3_TRGO   ((uint32_t)ADC_CR2_EXTSEL_3)
+#define ADC_EXTERNALTRIGCONV_T4_CC4    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T5_CC1    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
+#define ADC_EXTERNALTRIGCONV_T5_CC2    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T5_CC3    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
+#define ADC_EXTERNALTRIGCONV_T8_CC1    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T8_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
+#define ADC_EXTERNALTRIGCONV_Ext_IT11  ((uint32_t)ADC_CR2_EXTSEL)
+
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)  || \
+                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)  || \
+                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)  || \
+                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)  || \
+                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3)  || \
+                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4)  || \
+                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1)  || \
+                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)  || \
+                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1)  || \
+                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2)  || \
+                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3)  || \
+                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1)  || \
+                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
+                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_data_align 
+  * @{
+  */ 
+#define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000)
+#define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+                                  ((ALIGN) == ADC_DATAALIGN_LEFT))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_channels 
+  * @{
+  */ 
+#define ADC_CHANNEL_0           ((uint32_t)0x00000000)
+#define ADC_CHANNEL_1           ((uint32_t)ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_2           ((uint32_t)ADC_CR1_AWDCH_1)
+#define ADC_CHANNEL_3           ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_4           ((uint32_t)ADC_CR1_AWDCH_2)
+#define ADC_CHANNEL_5           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_6           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
+#define ADC_CHANNEL_7           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_8           ((uint32_t)ADC_CR1_AWDCH_3)
+#define ADC_CHANNEL_9           ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_10          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
+#define ADC_CHANNEL_11          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_12          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
+#define ADC_CHANNEL_13          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_14          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
+#define ADC_CHANNEL_15          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_16          ((uint32_t)ADC_CR1_AWDCH_4)
+#define ADC_CHANNEL_17          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_18          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
+
+#define ADC_CHANNEL_TEMPSENSOR  ((uint32_t)ADC_CHANNEL_16)
+#define ADC_CHANNEL_VREFINT     ((uint32_t)ADC_CHANNEL_17)
+#define ADC_CHANNEL_VBAT        ((uint32_t)ADC_CHANNEL_18)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)  || \
+                                 ((CHANNEL) == ADC_CHANNEL_1)  || \
+                                 ((CHANNEL) == ADC_CHANNEL_2)  || \
+                                 ((CHANNEL) == ADC_CHANNEL_3)  || \
+                                 ((CHANNEL) == ADC_CHANNEL_4)  || \
+                                 ((CHANNEL) == ADC_CHANNEL_5)  || \
+                                 ((CHANNEL) == ADC_CHANNEL_6)  || \
+                                 ((CHANNEL) == ADC_CHANNEL_7)  || \
+                                 ((CHANNEL) == ADC_CHANNEL_8)  || \
+                                 ((CHANNEL) == ADC_CHANNEL_9)  || \
+                                 ((CHANNEL) == ADC_CHANNEL_10) || \
+                                 ((CHANNEL) == ADC_CHANNEL_11) || \
+                                 ((CHANNEL) == ADC_CHANNEL_12) || \
+                                 ((CHANNEL) == ADC_CHANNEL_13) || \
+                                 ((CHANNEL) == ADC_CHANNEL_14) || \
+                                 ((CHANNEL) == ADC_CHANNEL_15) || \
+                                 ((CHANNEL) == ADC_CHANNEL_16) || \
+                                 ((CHANNEL) == ADC_CHANNEL_17) || \
+                                 ((CHANNEL) == ADC_CHANNEL_18))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_sampling_times 
+  * @{
+  */ 
+#define ADC_SAMPLETIME_3CYCLES    ((uint32_t)0x00000000)
+#define ADC_SAMPLETIME_15CYCLES   ((uint32_t)ADC_SMPR1_SMP10_0)
+#define ADC_SAMPLETIME_28CYCLES   ((uint32_t)ADC_SMPR1_SMP10_1)
+#define ADC_SAMPLETIME_56CYCLES   ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
+#define ADC_SAMPLETIME_84CYCLES   ((uint32_t)ADC_SMPR1_SMP10_2)
+#define ADC_SAMPLETIME_112CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
+#define ADC_SAMPLETIME_144CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
+#define ADC_SAMPLETIME_480CYCLES  ((uint32_t)ADC_SMPR1_SMP10)
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES)   || \
+                                  ((TIME) == ADC_SAMPLETIME_15CYCLES)  || \
+                                  ((TIME) == ADC_SAMPLETIME_28CYCLES)  || \
+                                  ((TIME) == ADC_SAMPLETIME_56CYCLES)  || \
+                                  ((TIME) == ADC_SAMPLETIME_84CYCLES)  || \
+                                  ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
+                                  ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
+                                  ((TIME) == ADC_SAMPLETIME_480CYCLES))
+/**
+  * @}
+  */ 
+
+  /** @defgroup ADC_EOCSelection 
+  * @{
+  */ 
+#define EOC_SEQ_CONV              ((uint32_t)0x00000000)
+#define EOC_SINGLE_CONV           ((uint32_t)0x00000001)
+#define EOC_SINGLE_SEQ_CONV       ((uint32_t)0x00000002)  /*!< reserved for future use */
+
+#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == EOC_SINGLE_CONV)   || \
+                                           ((EOCSelection) == EOC_SEQ_CONV)  || \
+                                           ((EOCSelection) == EOC_SINGLE_SEQ_CONV))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_Event_type 
+  * @{
+  */ 
+#define AWD_EVENT             ((uint32_t)ADC_FLAG_AWD)
+#define OVR_EVENT             ((uint32_t)ADC_FLAG_OVR)
+
+#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \
+                                  ((EVENT) == OVR_EVENT))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_selection 
+  * @{
+  */ 
+#define ADC_ANALOGWATCHDOG_SINGLE_REG         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC       ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC    ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_ALL_REG            ((uint32_t)ADC_CR1_AWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_INJEC          ((uint32_t)ADC_CR1_JAWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC       ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_NONE               ((uint32_t)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)        || \
+                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)      || \
+                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)   || \
+                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)           || \
+                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)         || \
+                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      || \
+                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
+/**
+  * @}
+  */ 
+    
+/** @defgroup ADC_interrupts_definition 
+  * @{
+  */ 
+#define ADC_IT_EOC      ((uint32_t)ADC_CR1_EOCIE)  
+#define ADC_IT_AWD      ((uint32_t)ADC_CR1_AWDIE) 
+#define ADC_IT_JEOC     ((uint32_t)ADC_CR1_JEOCIE)
+#define ADC_IT_OVR      ((uint32_t)ADC_CR1_OVRIE) 
+
+#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
+                       ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) 
+/**
+  * @}
+  */ 
+    
+/** @defgroup ADC_flags_definition 
+  * @{
+  */ 
+#define ADC_FLAG_AWD    ((uint32_t)ADC_SR_AWD)
+#define ADC_FLAG_EOC    ((uint32_t)ADC_SR_EOC)
+#define ADC_FLAG_JEOC   ((uint32_t)ADC_SR_JEOC)
+#define ADC_FLAG_JSTRT  ((uint32_t)ADC_SR_JSTRT)
+#define ADC_FLAG_STRT   ((uint32_t)ADC_SR_STRT)
+#define ADC_FLAG_OVR    ((uint32_t)ADC_SR_OVR)
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_channels_type 
+  * @{
+  */ 
+#define ALL_CHANNELS      ((uint32_t)0x00000001)
+#define REGULAR_CHANNELS  ((uint32_t)0x00000002) /*!< reserved for future use */
+#define INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */
+
+#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ALL_CHANNELS) || \
+                                            ((CHANNEL_TYPE) == REGULAR_CHANNELS) || \
+                                            ((CHANNEL_TYPE) == INJECTED_CHANNELS))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_thresholds 
+  * @{
+  */ 
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFF))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_regular_length 
+  * @{
+  */ 
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_regular_rank 
+  * @{
+  */ 
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_regular_discontinuous_mode_number 
+  * @{
+  */ 
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_range_verification
+  * @{
+  */ 
+#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE)                                     \
+   ((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
+    (((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
+    (((RESOLUTION) == ADC_RESOLUTION8b)  && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
+    (((RESOLUTION) == ADC_RESOLUTION6b)  && ((ADC_VALUE) <= ((uint32_t)0x003F))))
+/**
+  * @}
+  */   
+  
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset ADC handle state
+  * @param  __HANDLE__: ADC handle
+  * @retval None
+  */
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+
+/**
+  * @brief  Enable the ADC peripheral.
+  * @param  __HANDLE__: ADC handle
+  * @retval None
+  */
+#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |=  ADC_CR2_ADON)
+
+/**
+  * @brief  Disable the ADC peripheral.
+  * @param  __HANDLE__: ADC handle
+  * @retval None
+  */
+#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &=  ~ADC_CR2_ADON)
+
+/**
+  * @brief  Set ADC Regular channel sequence length.
+  * @param  _NbrOfConversion_: Regular channel sequence length. 
+  * @retval None
+  */
+#define __HAL_ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
+
+/**
+  * @brief  Set the ADC's sample time for channel numbers between 10 and 18.
+  * @param  _SAMPLETIME_: Sample time parameter.
+  * @param  _CHANNELNB_: Channel number.  
+  * @retval None
+  */
+#define __HAL_ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
+
+/**
+  * @brief  Set the ADC's sample time for channel numbers between 0 and 9.
+  * @param  _SAMPLETIME_: Sample time parameter.
+  * @param  _CHANNELNB_: Channel number.  
+  * @retval None
+  */
+#define __HAL_ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
+
+/**
+  * @brief  Set the selected regular channel rank for rank between 1 and 6.
+  * @param  _CHANNELNB_: Channel number.
+  * @param  _RANKNB_: Rank number.    
+  * @retval None
+  */
+#define __HAL_ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
+
+/**
+  * @brief  Set the selected regular channel rank for rank between 7 and 12.
+  * @param  _CHANNELNB_: Channel number.
+  * @param  _RANKNB_: Rank number.    
+  * @retval None
+  */
+#define __HAL_ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
+
+/**
+  * @brief  Set the selected regular channel rank for rank between 13 and 16.
+  * @param  _CHANNELNB_: Channel number.
+  * @param  _RANKNB_: Rank number.    
+  * @retval None
+  */
+#define __HAL_ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
+
+/**
+  * @brief  Enable ADC continuous conversion mode.
+  * @param  _CONTINUOUS_MODE_: Continuous mode.
+  * @retval None
+  */
+#define __HAL_ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
+
+/**
+  * @brief  Configures the number of discontinuous conversions for the regular group channels.
+  * @param  _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
+  * @retval None
+  */
+#define __HAL_ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << 13)
+
+/**
+  * @brief  Enable ADC scan mode.
+  * @param  _SCANCONV_MODE_: Scan conversion mode.
+  * @retval None
+  */
+#define __HAL_ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
+
+/**
+  * @brief  Enable the ADC end of conversion selection.
+  * @param  _EOCSelection_MODE_: End of conversion selection mode.
+  * @retval None
+  */
+#define __HAL_ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
+
+/**
+  * @brief  Enable the ADC DMA continuous request.
+  * @param  _DMAContReq_MODE_: DMA continuous request mode.
+  * @retval None
+  */
+#define __HAL_ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
+
+/**
+  * @brief  Enable the ADC end of conversion interrupt.
+  * @param  __HANDLE__: specifies the ADC Handle.
+  * @param  __INTERRUPT__: ADC Interrupt.
+  * @retval None
+  */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the ADC end of conversion interrupt.
+  * @param  __HANDLE__: specifies the ADC Handle.
+  * @param  __INTERRUPT__: ADC interrupt.
+  * @retval None
+  */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
+
+/** @brief  Check if the specified ADC interrupt source is enabled or disabled.
+  * @param  __HANDLE__: specifies the ADC Handle.
+  * @param  __INTERRUPT__: specifies the ADC interrupt source to check.
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+  * @brief  Clear the ADC's pending flags.
+  * @param  __HANDLE__: specifies the ADC Handle.
+  * @param  __FLAG__: ADC flag.
+  * @retval None
+  */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) &= ~(__FLAG__))
+
+/**
+  * @brief  Get the selected ADC's flag status.
+  * @param  __HANDLE__: specifies the ADC Handle.
+  * @param  __FLAG__: ADC flag.
+  * @retval None
+  */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief Return resolution bits in CR1 register.
+  * @param __HANDLE__: ADC handle
+  * @retval None
+  */
+#define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
+
+/* Include ADC HAL Extension module */
+#include "stm32f4xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions ***********************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void       HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
+void       HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
+
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
+
+void              HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
+
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
+
+uint32_t          HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
+
+void       HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
+void       HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
+void       HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
+void       HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
+
+/* Peripheral State functions ***************************************************/
+HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
+uint32_t             HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_ADC_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,841 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_adc_ex.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the ADC extension peripheral:
+  *           + Extended features functions
+  *         
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
+       (##) Enable the ADC interface clock using __ADC_CLK_ENABLE()
+       (##) ADC pins configuration
+             (+++) Enable the clock for the ADC GPIOs using the following function:
+                   __GPIOx_CLK_ENABLE()  
+             (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() 
+       (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
+             (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
+             (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
+             (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
+      (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
+             (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+             (+++) Configure and enable two DMA streams stream for managing data
+                 transfer from peripheral to memory (output stream)
+             (+++) Associate the initilalized DMA handle to the ADC DMA handle
+                 using  __HAL_LINKDMA()
+             (+++) Configure the priority and enable the NVIC for the transfer complete
+                 interrupt on the two DMA Streams. The output stream should have higher
+                 priority than the input stream.                  
+     (#) Configure the ADC Prescaler, conversion resolution and data alignment 
+         using the HAL_ADC_Init() function. 
+  
+     (#) Configure the ADC Injected channels group features, use HAL_ADC_Init()
+         and HAL_ADC_ConfigChannel() functions.
+         
+     (#) Three operation modes are available within this driver :     
+  
+     *** Polling mode IO operation ***
+     =================================
+     [..]    
+       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart() 
+       (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
+           user can specify the value of timeout according to his end application      
+       (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.
+       (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()
+  
+     *** Interrupt mode IO operation ***    
+     ===================================
+     [..]    
+       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT() 
+       (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
+       (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can 
+            add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback 
+       (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can 
+            add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
+       (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()
+       
+            
+     *** DMA mode IO operation ***    
+     ==============================
+     [..]    
+       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length 
+           of data to be transferred at each end of conversion 
+       (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can 
+            add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback 
+       (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can 
+            add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
+        (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA()
+        
+     *** Multi mode ADCs Regular channels configuration ***
+     ======================================================
+     [..]        
+       (+) Select the Multi mode ADC regular channels features (dual or triple mode)  
+          and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions. 
+       (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length 
+           of data to be transferred at each end of conversion           
+       (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.
+  
+  
+    @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADCEx 
+  * @brief ADC Extended driver modules
+  * @{
+  */ 
+
+#ifdef HAL_ADC_MODULE_ENABLED
+    
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/ 
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);
+static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); 
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup ADCEx_Group1 Extended features functions 
+ *  @brief    Extended features functions  
+ *
+@verbatim   
+ ===============================================================================
+                 ##### Extended features functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Start conversion of injected channel.
+      (+) Stop conversion of injected channel.
+      (+) Start multimode and enable DMA transfer.
+      (+) Stop multimode and disable DMA transfer.
+      (+) Get result of injected channel conversion.
+      (+) Get result of multimode conversion.
+      (+) Configure injected channels.
+      (+) Configure multimode.
+               
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables the selected ADC software start conversion of the injected channels.
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
+{
+  uint32_t i = 0, tmp1 = 0, tmp2 = 0;
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Check if a regular conversion is ongoing */
+  if(hadc->State == HAL_ADC_STATE_BUSY_REG)
+  {
+    /* Change ADC state */
+    hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;  
+  }
+  else
+  {
+    /* Change ADC state */
+    hadc->State = HAL_ADC_STATE_BUSY_INJ;
+  } 
+  
+  /* Check if ADC peripheral is disabled in order to enable it and wait during 
+     Tstab time the ADC's stabilization */
+  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+  {  
+    /* Enable the Peripheral */
+    __HAL_ADC_ENABLE(hadc);
+    
+    /* Delay inserted to wait during Tstab time the ADC's stabilazation */
+    for(; i <= 540; i++)
+    {
+      __NOP();
+    }
+  }
+  
+  /* Check if Multimode enabled */
+  if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+  {
+    tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+    tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+    if(tmp1 && tmp2)
+    {
+      /* Enable the selected ADC software conversion for injected group */
+      hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+    }
+  }
+  else
+  {
+    tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+    tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+    if((hadc->Instance == ADC1) && tmp1 && tmp2)  
+    {
+      /* Enable the selected ADC software conversion for injected group */
+      hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+    }
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables the interrupt and starts ADC conversion of injected channels.
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  *
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
+{
+  uint32_t i = 0, tmp1 = 0, tmp2 =0;
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Check if a regular conversion is ongoing */
+  if(hadc->State == HAL_ADC_STATE_BUSY_REG)
+  {
+    /* Change ADC state */
+    hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;  
+  }
+  else
+  {
+    /* Change ADC state */
+    hadc->State = HAL_ADC_STATE_BUSY_INJ;
+  }
+  
+  /* Set ADC error code to none */
+  hadc->ErrorCode = HAL_ADC_ERROR_NONE;
+  
+  /* Check if ADC peripheral is disabled in order to enable it and wait during 
+     Tstab time the ADC's stabilization */
+  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+  {  
+    /* Enable the Peripheral */
+    __HAL_ADC_ENABLE(hadc);
+    
+    /* Delay inserted to wait during Tstab time the ADC's stabilazation */
+    for(; i <= 540; i++)
+    {
+      __NOP();
+    }
+  }
+  
+  /* Enable the ADC end of conversion interrupt for injected group */
+  __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+  
+  /* Enable the ADC overrun interrupt */
+  __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+  
+  /* Check if Multimode enabled */
+  if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+  {
+    tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+    tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+    if(tmp1 && tmp2)
+    {
+      /* Enable the selected ADC software conversion for injected group */
+      hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+    }
+  }
+  else
+  {
+    tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+    tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+    if((hadc->Instance == ADC1) && tmp1 && tmp2)  
+    {
+      /* Enable the selected ADC software conversion for injected group */
+      hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+    }
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables ADC and stop conversion of injected channels.
+  *
+  * @note   Caution: This function will stop also regular channels.  
+  *
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
+{
+  /* Disable the Peripheral */
+  __HAL_ADC_DISABLE(hadc);
+  
+  /* Change ADC state */
+  hadc->State = HAL_ADC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Poll for injected conversion complete
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @param  Timeout: Timeout value in millisecond.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+  uint32_t timeout;
+ 
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;  
+
+  /* Check End of conversion flag */
+  while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        hadc->State= HAL_ADC_STATE_TIMEOUT;
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Check if a regular conversion is ready */
+  if(hadc->State == HAL_ADC_STATE_EOC_REG)
+  {
+    /* Change ADC state */
+    hadc->State = HAL_ADC_STATE_EOC_INJ_REG;  
+  }
+  else
+  {
+    /* Change ADC state */
+    hadc->State = HAL_ADC_STATE_EOC_INJ;
+  }
+  
+  /* Return ADC state */
+  return HAL_OK;
+}      
+  
+/**
+  * @brief  Disables the interrupt and stop ADC conversion of injected channels.
+  * 
+  * @note   Caution: This function will stop also regular channels.  
+  *
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
+{
+  /* Disable the ADC end of conversion interrupt for regular group */
+  __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+  
+  /* Disable the ADC end of conversion interrupt for injected group */
+  __HAL_ADC_DISABLE_IT(hadc, ADC_CR1_JEOCIE);
+  
+  /* Enable the Periphral */
+  __HAL_ADC_DISABLE(hadc);
+  
+  /* Change ADC state */
+  hadc->State = HAL_ADC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Gets the converted value from data register of injected channel.
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @param  InjectedRank: the ADC injected rank.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
+  *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
+  *            @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
+  *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
+  * @retval None
+  */
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+  
+   /* Clear the ADCx's flag for injected end of conversion */
+   __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_JEOC);
+  
+  /* Return the selected ADC converted value */ 
+  switch(InjectedRank)
+  {  
+    case ADC_INJECTED_RANK_4:
+    {
+      tmp =  hadc->Instance->JDR4;
+    }  
+    break;
+    case ADC_INJECTED_RANK_3: 
+    {  
+      tmp =  hadc->Instance->JDR3;
+    }  
+    break;
+    case ADC_INJECTED_RANK_2: 
+    {  
+      tmp =  hadc->Instance->JDR2;
+    }
+    break;
+    case ADC_INJECTED_RANK_1:
+    {
+      tmp =  hadc->Instance->JDR1;
+    }
+    break;
+    default:
+    break;  
+  }
+  return tmp;
+}
+
+/**
+  * @brief  Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral
+  * 
+  * @note   Caution: This function must be used only with the ADC master.  
+  *
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @param  pData:   Pointer to buffer in which transferred from ADC peripheral to memory will be stored. 
+  * @param  Length:  The length of data to be transferred from ADC peripheral to memory.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+  uint16_t counter = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Enable ADC overrun interrupt */
+  __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+  
+  if (hadc->Init.DMAContinuousRequests != DISABLE)
+  {
+    /* Enable the selected ADC DMA request after last transfer */
+    ADC->CCR |= ADC_CCR_DDS;
+  }
+  else
+  {
+    /* Disable the selected ADC EOC rising on each regular channel conversion */
+    ADC->CCR &= ~ADC_CCR_DDS;
+  }
+  
+  /* Set the DMA transfer complete callback */
+  hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
+  
+  /* Set the DMA half transfer complete callback */
+  hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
+     
+  /* Set the DMA error callback */
+  hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
+  
+  /* Enable the DMA Stream */
+  HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
+  
+  /* Change ADC state */
+  hadc->State = HAL_ADC_STATE_BUSY_REG;
+  
+  /* Check if ADC peripheral is disabled in order to enable it and wait during 
+     Tstab time the ADC's stabilization */
+  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
+  {  
+    /* Enable the Peripheral */
+    __HAL_ADC_ENABLE(hadc);
+    
+    /* Delay inserted to wait during Tstab time the ADC's stabilazation */
+    for(; counter <= 540; counter++)
+    {
+      __NOP();
+    }
+  }
+  
+  /* if no external trigger present enable software conversion of regular channels */
+  if (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
+  {
+    /* Enable the selected ADC software conversion for regular group */
+    hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables ADC DMA (multi-ADC mode) and disables ADC peripheral    
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
+{
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Enable the Peripheral */
+  __HAL_ADC_DISABLE(hadc);
+  
+  /* Disable ADC overrun interrupt */
+  __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+  
+  /* Disable the selected ADC DMA request after last transfer */
+  ADC->CCR &= ~ADC_CCR_DDS;
+  
+  /* Disable the ADC DMA Stream */
+  HAL_DMA_Abort(hadc->DMA_Handle);
+  
+  /* Change ADC state */
+  hadc->State = HAL_ADC_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+    
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns the last ADC1, ADC2 and ADC3 regular conversions results 
+  *         data in the selected multi mode.
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval The converted data value.
+  */
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
+{
+  /* Return the multi mode conversion value */
+  return ADC->CDR;
+}
+
+/**
+  * @brief  Injected conversion complete callback in non blocking mode 
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @retval None
+  */
+__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Configures for the selected ADC injected channel its corresponding
+  *         rank in the sequencer and its sample time.
+  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  *         the configuration information for the specified ADC.
+  * @param  sConfigInjected: ADC configuration structure for injected channel. 
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
+{
+  
+#ifdef USE_FULL_ASSERT  
+  uint32_t tmp = 0;
+#endif /* USE_FULL_ASSERT  */
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
+  assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
+  assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
+  assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
+  assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
+  assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
+  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
+  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
+
+#ifdef USE_FULL_ASSERT
+  tmp = __HAL_ADC_GET_RESOLUTION(hadc);
+  assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
+#endif /* USE_FULL_ASSERT  */
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
+  if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)
+  {
+    /* Clear the old sample time */
+    hadc->Instance->SMPR1 &= ~__HAL_ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
+    
+    /* Set the new sample time */
+    hadc->Instance->SMPR1 |= __HAL_ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Clear the old sample time */
+    hadc->Instance->SMPR2 &= ~__HAL_ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
+    
+    /* Set the new sample time */
+    hadc->Instance->SMPR2 |= __HAL_ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
+  }
+  
+  /*---------------------------- ADCx JSQR Configuration -----------------*/
+  hadc->Instance->JSQR &= ~(ADC_JSQR_JL);
+  hadc->Instance->JSQR |=  __HAL_ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
+  
+  /* Rank configuration */
+  
+  /* Clear the old SQx bits for the selected rank */
+  hadc->Instance->JSQR &= ~__HAL_ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
+   
+  /* Set the SQx bits for the selected rank */
+  hadc->Instance->JSQR |= __HAL_ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
+
+  /* Select external trigger to start conversion */
+  hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
+  hadc->Instance->CR2 |=  sConfigInjected->ExternalTrigInjecConv;
+  
+  /* Select external trigger polarity */
+  hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
+  hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
+  
+  if (sConfigInjected->AutoInjectedConv != DISABLE)
+  {
+    /* Enable the selected ADC automatic injected group conversion */
+    hadc->Instance->CR1 |= ADC_CR1_JAUTO;
+  }
+  else
+  {
+    /* Disable the selected ADC automatic injected group conversion */
+    hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);
+  }
+  
+  if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)
+  {
+    /* Enable the selected ADC injected discontinuous mode */
+    hadc->Instance->CR1 |= ADC_CR1_JDISCEN;
+  }
+  else
+  {
+    /* Disable the selected ADC injected discontinuous mode */
+    hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);
+  }
+  
+  switch(sConfigInjected->InjectedRank)
+  {
+    case 1:
+      /* Set injected channel 1 offset */
+      hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);
+      hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;
+      break;
+    case 2:
+      /* Set injected channel 2 offset */
+      hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);
+      hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;
+      break;
+    case 3:
+      /* Set injected channel 3 offset */
+      hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);
+      hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;
+      break;
+    default:
+      /* Set injected channel 4 offset */
+      hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);
+      hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
+      break;
+  }
+  
+  /* if ADC1 Channel_18 is selected enable VBAT Channel */
+  if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))
+  {
+    /* Enable the VBAT channel*/
+    ADC->CCR |= ADC_CCR_VBATE;
+  }
+  
+  /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
+  if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))
+  {
+    /* Enable the TSVREFE channel*/
+    ADC->CCR |= ADC_CCR_TSVREFE;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the ADC multi-mode 
+  * @param  hadc      : pointer to a ADC_HandleTypeDef structure that contains
+  *                     the configuration information for the specified ADC.  
+  * @param  multimode : pointer to an ADC_MultiModeTypeDef structure that contains 
+  *                     the configuration information for  multimode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_MODE(multimode->Mode));
+  assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
+  assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Set ADC mode */
+  ADC->CCR &= ~(ADC_CCR_MULTI);
+  ADC->CCR |= multimode->Mode;
+  
+  /* Set the ADC DMA access mode */
+  ADC->CCR &= ~(ADC_CCR_DMA);
+  ADC->CCR |= multimode->DMAAccessMode;
+  
+  /* Set delay between two sampling phases */
+  ADC->CCR &= ~(ADC_CCR_DELAY);
+  ADC->CCR |= multimode->TwoSamplingDelay;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+  /**
+  * @brief  DMA transfer complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)   
+{
+    ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    
+  /* Check if an injected conversion is ready */
+  if(hadc->State == HAL_ADC_STATE_EOC_INJ)
+  {
+    /* Change ADC state */
+    hadc->State = HAL_ADC_STATE_EOC_INJ_REG;  
+  }
+  else
+  {
+    /* Change ADC state */
+    hadc->State = HAL_ADC_STATE_EOC_REG;
+  }
+    
+    HAL_ADC_ConvCpltCallback(hadc); 
+}
+
+/**
+  * @brief  DMA half transfer complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
+{
+    ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    /* Conversion complete callback */
+    HAL_ADC_ConvHalfCpltCallback(hadc); 
+}
+
+/**
+  * @brief  DMA error callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)   
+{
+    ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    hadc->State= HAL_ADC_STATE_ERROR;
+    /* Set ADC error code to DMA error */
+    hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
+    HAL_ADC_ErrorCallback(hadc); 
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,329 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_adc.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of ADC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_ADC_EX_H
+#define __STM32F4xx_ADC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ADCEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+   
+/** 
+  * @brief   ADC Configuration injected Channel structure definition
+  */ 
+typedef struct 
+{
+  uint32_t InjectedChannel;                /*!< Configure the ADC injected channel.
+                                                This parameter can be a value of @ref ADC_channels */ 
+  uint32_t InjectedRank;                   /*!< The rank in the injected group sequencer
+                                                This parameter must be a number between Min_Data = 1 and Max_Data = 4. */ 
+  uint32_t InjectedSamplingTime;           /*!< The sample time value to be set for the selected channel.
+                                                This parameter can be a value of @ref ADC_sampling_times */
+  uint32_t InjectedOffset;                 /*!< Defines the offset to be subtracted from the raw converted data when convert injected channels.
+                                                This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+  uint32_t InjectedNbrOfConversion;        /*!< Specifies the number of ADC conversions that will be done using the sequencer for
+                                                injected channel group.
+                                                This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
+  uint32_t AutoInjectedConv;               /*!< Enables or disables the selected ADC automatic injected group 
+                                                conversion after regular one */
+  uint32_t InjectedDiscontinuousConvMode;  /*!< Specifies whether the conversion is performed in Discontinuous mode or not for injected channels.
+                                                This parameter can be set to ENABLE or DISABLE. */
+  uint32_t ExternalTrigInjecConvEdge;      /*!< Select the external trigger edge and enable the trigger of an injected channels. 
+                                                This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected */
+  uint32_t ExternalTrigInjecConv;          /*!< Select the external event used to trigger the start of conversion of a injected channels.
+                                                This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected */
+}ADC_InjectionConfTypeDef;
+
+/** 
+  * @brief   ADC Configuration multi-mode structure definition  
+  */ 
+typedef struct
+{
+  uint32_t Mode;              /*!< Configures the ADC to operate in independent or multi mode. 
+                                   This parameter can be a value of @ref ADCEx_Common_mode */
+  uint32_t DMAAccessMode;     /*!< Configures the Direct memory access mode for multi ADC mode.
+                                   This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */
+  uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.
+                                   This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases */
+}ADC_MultiModeTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Constants
+  * @{
+  */
+
+
+/** @defgroup ADCEx_Common_mode 
+  * @{
+  */ 
+#define ADC_MODE_INDEPENDENT                  ((uint32_t)0x00000000)      
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT    ((uint32_t)ADC_CCR_MULTI_0)
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG      ((uint32_t)ADC_CCR_MULTI_1)
+#define ADC_DUALMODE_INJECSIMULT              ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
+#define ADC_DUALMODE_REGSIMULT                ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
+#define ADC_DUALMODE_INTERL                   ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
+#define ADC_DUALMODE_ALTERTRIG                ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT  ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig    ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
+#define ADC_TRIPLEMODE_INJECSIMULT            ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_REGSIMULT              ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
+#define ADC_TRIPLEMODE_INTERL                 ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_ALTERTRIG              ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT)                 || \
+                           ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT)   || \
+                           ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)     || \
+                           ((MODE) == ADC_DUALMODE_INJECSIMULT)             || \
+                           ((MODE) == ADC_DUALMODE_REGSIMULT)               || \
+                           ((MODE) == ADC_DUALMODE_INTERL)                  || \
+                           ((MODE) == ADC_DUALMODE_ALTERTRIG)               || \
+                           ((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
+                           ((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig)   || \
+                           ((MODE) == ADC_TRIPLEMODE_INJECSIMULT)           || \
+                           ((MODE) == ADC_TRIPLEMODE_REGSIMULT)             || \
+                           ((MODE) == ADC_TRIPLEMODE_INTERL)                || \
+                           ((MODE) == ADC_TRIPLEMODE_ALTERTRIG))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode 
+  * @{
+  */ 
+#define ADC_DMAACCESSMODE_DISABLED  ((uint32_t)0x00000000)     /*!< DMA mode disabled */
+#define ADC_DMAACCESSMODE_1         ((uint32_t)ADC_CCR_DMA_0)  /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
+#define ADC_DMAACCESSMODE_2         ((uint32_t)ADC_CCR_DMA_1)  /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
+#define ADC_DMAACCESSMODE_3         ((uint32_t)ADC_CCR_DMA)    /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
+
+#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
+                                      ((MODE) == ADC_DMAACCESSMODE_1)        || \
+                                      ((MODE) == ADC_DMAACCESSMODE_2)        || \
+                                      ((MODE) == ADC_DMAACCESSMODE_3))
+/**
+  * @}
+  */ 
+
+  /** @defgroup ADCEx_delay_between_2_sampling_phases 
+  * @{
+  */ 
+#define ADC_TWOSAMPLINGDELAY_5CYCLES    ((uint32_t)0x00000000)
+#define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)ADC_CCR_DELAY_0)
+#define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)ADC_CCR_DELAY_1)
+#define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_9CYCLES    ((uint32_t)ADC_CCR_DELAY_2)
+#define ADC_TWOSAMPLINGDELAY_10CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_11CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_12CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_13CYCLES   ((uint32_t)ADC_CCR_DELAY_3)
+#define ADC_TWOSAMPLINGDELAY_14CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_15CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_16CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_17CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
+#define ADC_TWOSAMPLINGDELAY_18CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_19CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_20CYCLES   ((uint32_t)ADC_CCR_DELAY)
+
+#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
+                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
+                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
+                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
+                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
+                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
+                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
+                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
+                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
+                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
+                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
+                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
+                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
+                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
+                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
+                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_External_trigger_edge_Injected 
+  * @{
+  */ 
+#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE           ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING         ((uint32_t)ADC_CR2_JEXTEN_0)
+#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING        ((uint32_t)ADC_CR2_JEXTEN_1)
+#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_JEXTEN)
+
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE)    || \
+                                          ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING)  || \
+                                          ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
+                                          ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADCEx_External_trigger_Source_Injected 
+  * @{
+  */ 
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4           ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO          ((uint32_t)ADC_CR2_JEXTSEL_0)
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1           ((uint32_t)ADC_CR2_JEXTSEL_1)
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO          ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC2           ((uint32_t)ADC_CR2_JEXTSEL_2)
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4           ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC1           ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC2           ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC3           ((uint32_t)ADC_CR2_JEXTSEL_3)
+#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T5_CC4           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
+#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC2           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC3           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC4           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15         ((uint32_t)ADC_CR2_JEXTSEL)
+
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)  || \
+                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)  || \
+                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2)  || \
+                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)  || \
+                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1)  || \
+                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2)  || \
+                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3)  || \
+                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4)  || \
+                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
+                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2)  || \
+                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3)  || \
+                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)  || \
+                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADCEx_injected_channel_selection 
+  * @{
+  */ 
+#define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001)
+#define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002)
+#define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003)
+#define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004)
+
+/**
+  * @}
+  */
+    
+/** @defgroup ADCEx_injected_length 
+  * @{
+  */ 
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADCEx_injected_rank 
+  * @{
+  */ 
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)4)))
+/**
+  * @}
+  */ 
+ 
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+  * @brief  Set the selected injected Channel rank.
+  * @param  _CHANNELNB_: Channel number.
+  * @param  _RANKNB_: Rank number. 
+  * @param  _JSQR_JL_: Sequence length.     
+  * @retval None
+  */
+#define   __HAL_ADC_JSQR(_CHANNELNB_, _RANKNB_,_JSQR_JL_) \
+((_CHANNELNB_) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
+uint32_t          HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
+uint32_t          HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
+void       HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_ADC_EX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1414 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_can.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Controller Area Network (CAN) peripheral:
+  *           + Initialization and de-initialization functions 
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Error functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]            
+      (#) Enable the CAN controller interface clock using 
+          __CAN1_CLK_ENABLE() for CAN1 and __CAN1_CLK_ENABLE() for CAN2
+      -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
+       
+      (#) CAN pins configuration
+        (++) Enable the clock for the CAN GPIOs using the following function:
+             __GPIOx_CLK_ENABLE()   
+        (++) Connect and configure the involved CAN pins to AF9 using the 
+              following function HAL_GPIO_Init() 
+              
+      (#) Initialise and configure the CAN using CAN_Init() function.   
+                 
+      (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
+           
+      (#) Receive a CAN frame using HAL_CAN_Recieve() function.
+
+     *** Polling mode IO operation ***
+     =================================
+     [..]    
+       (+) Start the CAN peripheral transmission and wait the end of this operation 
+           using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
+           according to his end application
+       (+) Start the CAN peripheral reception and wait the end of this operation 
+           using HAL_CAN_Receive(), at this stage user can specify the value of timeout
+           according to his end application 
+       
+     *** Interrupt mode IO operation ***    
+     ===================================
+     [..]    
+       (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
+       (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()         
+       (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
+       (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can 
+            add his own code by customization of function pointer HAL_CAN_TxCpltCallback 
+       (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can 
+            add his own code by customization of function pointer HAL_CAN_ErrorCallback
+ 
+     *** CAN HAL driver macros list ***
+     ============================================= 
+     [..]
+       Below the list of most used macros in CAN HAL driver.
+       
+      (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
+      (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
+      (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
+      (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
+      (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
+      
+     [..] 
+      (@) You can refer to the CAN HAL driver header file for more useful macros 
+                
+  @endverbatim
+           
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CAN 
+  * @brief CAN driver modules
+  * @{
+  */ 
+  
+#ifdef HAL_CAN_MODULE_ENABLED  
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+  
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CAN_Private_Functions
+  * @{
+  */
+
+/** @defgroup CAN_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the CAN. 
+      (+) De-initialize the CAN. 
+         
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initializes the CAN peripheral according to the specified
+  *         parameters in the CAN_InitStruct.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
+{
+  uint32_t InitStatus = 3;
+  uint32_t timeout = 0;
+  
+  /* Check CAN handle */
+  if(hcan == NULL)
+  {
+     return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
+  assert_param(IS_CAN_MODE(hcan->Init.Mode));
+  assert_param(IS_CAN_SJW(hcan->Init.SJW));
+  assert_param(IS_CAN_BS1(hcan->Init.BS1));
+  assert_param(IS_CAN_BS2(hcan->Init.BS2));
+  assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
+  
+
+  if(hcan->State == HAL_CAN_STATE_RESET)
+  {    
+    /* Init the low level hardware */
+    HAL_CAN_MspInit(hcan);
+  }
+  
+  /* Initialize the CAN state*/
+  hcan->State = HAL_CAN_STATE_BUSY;
+  
+  /* Exit from sleep mode */
+  hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
+
+  /* Request initialisation */
+  hcan->Instance->MCR |= CAN_MCR_INRQ ;
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + 10;   
+  
+  /* Wait the acknowledge */
+  while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+  {
+    if(HAL_GetTick() >= timeout)
+    {
+      hcan->State= HAL_CAN_STATE_TIMEOUT;
+      /* Process unlocked */
+      __HAL_UNLOCK(hcan);
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Check acknowledge */
+  if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+  {
+    InitStatus = CAN_INITSTATUS_FAILED;
+  }
+  else 
+  {
+    /* Set the time triggered communication mode */
+    if (hcan->Init.TTCM == ENABLE)
+    {
+      hcan->Instance->MCR |= CAN_MCR_TTCM;
+    }
+    else
+    {
+      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
+    }
+
+    /* Set the automatic bus-off management */
+    if (hcan->Init.ABOM == ENABLE)
+    {
+      hcan->Instance->MCR |= CAN_MCR_ABOM;
+    }
+    else
+    {
+      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
+    }
+
+    /* Set the automatic wake-up mode */
+    if (hcan->Init.AWUM == ENABLE)
+    {
+      hcan->Instance->MCR |= CAN_MCR_AWUM;
+    }
+    else
+    {
+      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
+    }
+
+    /* Set the no automatic retransmission */
+    if (hcan->Init.NART == ENABLE)
+    {
+      hcan->Instance->MCR |= CAN_MCR_NART;
+    }
+    else
+    {
+      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
+    }
+
+    /* Set the receive FIFO locked mode */
+    if (hcan->Init.RFLM == ENABLE)
+    {
+      hcan->Instance->MCR |= CAN_MCR_RFLM;
+    }
+    else
+    {
+      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
+    }
+
+    /* Set the transmit FIFO priority */
+    if (hcan->Init.TXFP == ENABLE)
+    {
+      hcan->Instance->MCR |= CAN_MCR_TXFP;
+    }
+    else
+    {
+      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
+    }
+
+    /* Set the bit timing register */
+    hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
+                ((uint32_t)hcan->Init.SJW) | \
+                ((uint32_t)hcan->Init.BS1) | \
+                ((uint32_t)hcan->Init.BS2) | \
+               ((uint32_t)hcan->Init.Prescaler - 1);
+
+    /* Request leave initialisation */
+    hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+
+    /* Get timeout */
+    timeout = HAL_GetTick() + 10;   
+   
+   /* Wait the acknowledge */
+   while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+   {
+     if(HAL_GetTick() >= timeout)
+     {
+       hcan->State= HAL_CAN_STATE_TIMEOUT;
+       /* Process unlocked */
+       __HAL_UNLOCK(hcan);
+       return HAL_TIMEOUT;
+     }
+   }
+
+    /* Check acknowledged */
+    if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+    {
+      InitStatus = CAN_INITSTATUS_FAILED;
+    }
+    else
+    {
+      InitStatus = CAN_INITSTATUS_SUCCESS;
+    }
+  }
+ 
+  if(InitStatus == CAN_INITSTATUS_SUCCESS)
+  {
+    /* Set CAN error code to none */
+    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+    
+    /* Initialize the CAN state */
+    hcan->State = HAL_CAN_STATE_READY;
+  
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Initialize the CAN state */
+    hcan->State = HAL_CAN_STATE_ERROR;
+    
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configures the CAN reception filter according to the specified
+  *         parameters in the CAN_FilterInitStruct.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
+  *         contains the filter configuration information.
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
+{
+  uint32_t filternbrbitpos = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
+  assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
+  assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
+  assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
+  assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
+  assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
+  
+  filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
+
+  /* Initialisation mode for the filter */
+  CAN1->FMR |= (uint32_t)CAN_FMR_FINIT;
+  
+  /* Select the start slave bank */
+  CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
+  CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);
+     
+  /* Filter Deactivation */
+  CAN1->FA1R &= ~(uint32_t)filternbrbitpos;
+
+  /* Filter Scale */
+  if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+  {
+    /* 16-bit scale for the filter */
+    CAN1->FS1R &= ~(uint32_t)filternbrbitpos;
+
+    /* First 16-bit identifier and First 16-bit mask */
+    /* Or First 16-bit identifier and Second 16-bit identifier */
+    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = 
+       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
+        (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+
+    /* Second 16-bit identifier and Second 16-bit mask */
+    /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = 
+       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
+  }
+
+  if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+  {
+    /* 32-bit scale for the filter */
+    CAN1->FS1R |= filternbrbitpos;
+    /* 32-bit identifier or First 32-bit identifier */
+    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = 
+       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+    /* 32-bit mask or Second 32-bit identifier */
+    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = 
+       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
+  }
+
+  /* Filter Mode */
+  if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
+  {
+    /*Id/Mask mode for the filter*/
+    CAN1->FM1R &= ~(uint32_t)filternbrbitpos;
+  }
+  else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+  {
+    /*Identifier list mode for the filter*/
+    CAN1->FM1R |= (uint32_t)filternbrbitpos;
+  }
+
+  /* Filter FIFO assignment */
+  if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
+  {
+    /* FIFO 0 assignation for the filter */
+    CAN1->FFA1R &= ~(uint32_t)filternbrbitpos;
+  }
+
+  if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
+  {
+    /* FIFO 1 assignation for the filter */
+    CAN1->FFA1R |= (uint32_t)filternbrbitpos;
+  }
+  
+  /* Filter activation */
+  if (sFilterConfig->FilterActivation == ENABLE)
+  {
+    CAN1->FA1R |= filternbrbitpos;
+  }
+
+  /* Leave the initialisation mode for the filter */
+  CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deinitializes the CANx peripheral registers to their default reset values. 
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
+{
+  /* Check CAN handle */
+  if(hcan == NULL)
+  {
+     return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+  
+  /* Change CAN state */
+  hcan->State = HAL_CAN_STATE_BUSY;
+  
+  /* DeInit the low level hardware */
+  HAL_CAN_MspDeInit(hcan);
+  
+  /* Change CAN state */
+  hcan->State = HAL_CAN_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hcan);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CAN MSP.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @retval None
+  */
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  DeInitializes the CAN MSP.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @retval None
+  */
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Group2 IO operation functions
+ *  @brief    IO operation functions 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### IO operation functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Transmit a CAN frame message.
+      (+) Receive a CAN frame message.
+      (+) Enter CAN peripheral in sleep mode. 
+      (+) Wake up the CAN peripheral from sleep mode.
+               
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initiates and transmits a CAN frame message.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @param  Timeout: Specify Timeout value   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
+{
+  uint32_t  transmitmailbox = 5;
+  
+  uint32_t timeout;
+   
+  /* Check the parameters */
+  assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+  assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+  assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+  
+  /* Process locked */
+  __HAL_LOCK(hcan);
+  
+  if(hcan->State == HAL_CAN_STATE_BUSY_RX) 
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+  }
+  else
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_BUSY_TX;
+  }
+  
+  /* Select one empty transmit mailbox */
+  if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+  {
+    transmitmailbox = 0;
+  }
+  else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+  {
+    transmitmailbox = 1;
+  }
+  else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+  {
+    transmitmailbox = 2;
+  }
+  else
+  {
+    transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+  }
+
+  if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
+  {
+    /* Set up the Id */
+    hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+    if (hcan->pTxMsg->IDE == CAN_ID_STD)
+    {
+      assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));  
+      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
+                                                  hcan->pTxMsg->RTR);
+    }
+    else
+    {
+      assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
+                                                  hcan->pTxMsg->IDE | \
+                                                  hcan->pTxMsg->RTR);
+    }
+    
+    /* Set up the DLC */
+    hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
+    hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+    hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+    /* Set up the data field */
+    hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | 
+                                             ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
+                                             ((uint32_t)hcan->pTxMsg->Data[1] << 8) | 
+                                             ((uint32_t)hcan->pTxMsg->Data[0]));
+    hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | 
+                                             ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
+                                             ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
+                                             ((uint32_t)hcan->pTxMsg->Data[4]));
+    /* Request transmission */
+    hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+  
+    /* Get timeout */
+    timeout = HAL_GetTick() + Timeout;   
+  
+    /* Check End of transmission flag */
+    while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          hcan->State = HAL_CAN_STATE_TIMEOUT;
+          /* Process unlocked */
+          __HAL_UNLOCK(hcan);
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
+    {
+      /* Change CAN state */
+      hcan->State = HAL_CAN_STATE_BUSY_RX;
+      
+      /* Process unlocked */
+      __HAL_UNLOCK(hcan);
+    }
+    else
+    {
+      /* Change CAN state */
+      hcan->State = HAL_CAN_STATE_READY;
+      
+      /* Process unlocked */
+      __HAL_UNLOCK(hcan);
+    }
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_ERROR; 
+    
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Initiates and transmits a CAN frame message.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+  uint32_t  transmitmailbox = 5;
+  uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+  assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+  assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+  
+  tmp = hcan->State;
+  if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_RX))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcan);
+    
+    /* Select one empty transmit mailbox */
+    if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+    {
+      transmitmailbox = 0;
+    }
+    else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+    {
+      transmitmailbox = 1;
+    }
+    else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+    {
+      transmitmailbox = 2;
+    }
+    else
+    {
+      transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+    }
+
+    if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
+    {
+      /* Set up the Id */
+      hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+      if(hcan->pTxMsg->IDE == CAN_ID_STD)
+      {
+        assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));  
+        hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
+                                                  hcan->pTxMsg->RTR);
+      }
+      else
+      {
+        assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+        hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
+                                                  hcan->pTxMsg->IDE | \
+                                                  hcan->pTxMsg->RTR);
+      }
+    
+      /* Set up the DLC */
+      hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
+      hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+      hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+      /* Set up the data field */
+      hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | 
+                                             ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
+                                             ((uint32_t)hcan->pTxMsg->Data[1] << 8) | 
+                                             ((uint32_t)hcan->pTxMsg->Data[0]));
+      hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | 
+                                             ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
+                                             ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
+                                             ((uint32_t)hcan->pTxMsg->Data[4]));
+    
+      if(hcan->State == HAL_CAN_STATE_BUSY_RX) 
+      {
+        /* Change CAN state */
+        hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+      }
+      else
+      {
+        /* Change CAN state */
+        hcan->State = HAL_CAN_STATE_BUSY_TX;
+      }
+      
+      /* Set CAN error code to none */
+      hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+      
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcan);
+      
+      /* Enable Error warning Interrupt */
+      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
+      
+      /* Enable Error passive Interrupt */
+      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
+      
+      /* Enable Bus-off Interrupt */
+      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
+      
+      /* Enable Last error code Interrupt */
+      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
+      
+      /* Enable Error Interrupt */
+      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
+      
+      /* Enable Transmit mailbox empty Interrupt */
+      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);
+      
+      /* Request transmission */
+      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Receives a correct CAN frame.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @param  FIFONumber: FIFO Number value
+  * @param  Timeout: Specify Timeout value 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
+{
+  uint32_t timeout;
+   
+  /* Check the parameters */
+  assert_param(IS_CAN_FIFO(FIFONumber));
+  
+  /* Process locked */
+  __HAL_LOCK(hcan);
+  
+  if(hcan->State == HAL_CAN_STATE_BUSY_TX) 
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+  }
+  else
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_BUSY_RX;
+  }
+    
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;   
+  
+  /* Check pending message */
+  while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        hcan->State = HAL_CAN_STATE_TIMEOUT;
+        /* Process unlocked */
+        __HAL_UNLOCK(hcan);
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Get the Id */
+  hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+  if (hcan->pRxMsg->IDE == CAN_ID_STD)
+  {
+    hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
+  }
+  else
+  {
+    hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
+  }
+  
+  hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+  /* Get the DLC */
+  hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+  /* Get the FMI */
+  hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
+  /* Get the data field */
+  hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+  hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
+  hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
+  hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
+  hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+  hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
+  hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
+  hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
+  
+  /* Release the FIFO */
+  if(FIFONumber == CAN_FIFO0)
+  {
+    /* Release FIFO0 */
+    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+  }
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    /* Release FIFO1 */
+    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+  }
+  
+  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_BUSY_TX;
+    
+    /* Process unlocked */
+    __HAL_UNLOCK(hcan);
+  }
+  else
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_READY;
+    
+    /* Process unlocked */
+    __HAL_UNLOCK(hcan);
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Receives a correct CAN frame.
+  * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @param  FIFONumber: Specify the FIFO number    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+  uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_FIFO(FIFONumber));
+  
+  tmp = hcan->State;
+  if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX))
+  {
+    /* Process locked */
+    __HAL_LOCK(hcan);
+  
+    if(hcan->State == HAL_CAN_STATE_BUSY_TX) 
+    {
+      /* Change CAN state */
+      hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      /* Change CAN state */
+      hcan->State = HAL_CAN_STATE_BUSY_RX;
+    }
+    
+    /* Set CAN error code to none */
+    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+    
+    /* Enable Error warning Interrupt */
+    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
+      
+    /* Enable Error passive Interrupt */
+    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
+      
+    /* Enable Bus-off Interrupt */
+    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
+      
+    /* Enable Last error code Interrupt */
+    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
+      
+    /* Enable Error Interrupt */
+    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hcan);
+
+    if(FIFONumber == CAN_FIFO0)
+    {
+      /* Enable FIFO 0 message pending Interrupt */
+      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
+    }
+    else
+    {
+      /* Enable FIFO 1 message pending Interrupt */
+      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
+    }
+    
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enters the Sleep (low power) mode.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
+{
+  uint32_t timeout;
+   
+  /* Process locked */
+  __HAL_LOCK(hcan);
+  
+  /* Change CAN state */
+  hcan->State = HAL_CAN_STATE_BUSY; 
+    
+  /* Request Sleep mode */
+   hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+   
+  /* Sleep mode status */
+  if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+  {
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + 10;   
+  
+  /* Wait the acknowledge */
+  while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+  {
+    if(HAL_GetTick() >= timeout)
+    {
+      hcan->State = HAL_CAN_STATE_TIMEOUT;
+      /* Process unlocked */
+      __HAL_UNLOCK(hcan);
+      return HAL_TIMEOUT;
+    }
+  }
+  
+  /* Change CAN state */
+  hcan->State = HAL_CAN_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hcan);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
+  *         is in the normal mode.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
+{
+  uint32_t timeout;
+    
+  /* Process locked */
+  __HAL_LOCK(hcan);
+  
+  /* Change CAN state */
+  hcan->State = HAL_CAN_STATE_BUSY;  
+ 
+  /* Wake up request */
+  hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
+    
+  /* Get timeout */
+  timeout = HAL_GetTick() + 10;   
+  
+  /* Sleep mode status */
+  while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+  {
+    if(HAL_GetTick() >= timeout)
+    {
+      hcan->State= HAL_CAN_STATE_TIMEOUT;
+      /* Process unlocked */
+      __HAL_UNLOCK(hcan);
+      return HAL_TIMEOUT;
+    }
+  }
+  if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+  {
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  /* Change CAN state */
+  hcan->State = HAL_CAN_STATE_READY; 
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hcan);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handles CAN interrupt request  
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
+{
+  uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
+  
+  /* Check End of transmission flag */
+  if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
+  {
+    tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
+    tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
+    tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
+    if(tmp1 || tmp2 || tmp3)  
+    {
+      /* Call transmit function */
+      CAN_Transmit_IT(hcan);
+    }
+  }
+  
+  tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
+  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
+  /* Check End of reception flag for FIFO0 */
+  if((tmp1 != 0) && tmp2)
+  {
+    /* Call receive function */
+    CAN_Receive_IT(hcan, CAN_FIFO0);
+  }
+  
+  tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
+  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
+  /* Check End of reception flag for FIFO1 */
+  if((tmp1 != 0) && tmp2)
+  {
+    /* Call receive function */
+    CAN_Receive_IT(hcan, CAN_FIFO1);
+  }
+  
+  tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
+  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
+  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
+  /* Check Error Warning Flag */
+  if(tmp1 && tmp2 && tmp3)
+  {
+    /* Set CAN error code to EWG error */
+    hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
+    /* Clear Error Warning Flag */ 
+    __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_EWG);
+  }
+  
+  tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
+  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
+  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); 
+  /* Check Error Passive Flag */
+  if(tmp1 && tmp2 && tmp3)
+  {
+    /* Set CAN error code to EPV error */
+    hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
+    /* Clear Error Passive Flag */ 
+    __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_EPV);
+  }
+  
+  tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
+  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
+  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);  
+  /* Check Bus-Off Flag */
+  if(tmp1 && tmp2 && tmp3)
+  {
+    /* Set CAN error code to BOF error */
+    hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
+    /* Clear Bus-Off Flag */ 
+    __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_BOF);
+  }
+  
+  tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
+  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
+  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
+  /* Check Last error code Flag */
+  if((!tmp1) && tmp2 && tmp3)
+  {
+    tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;
+    switch(tmp1)
+    {
+      case(CAN_ESR_LEC_0):
+          /* Set CAN error code to STF error */
+          hcan->ErrorCode |= HAL_CAN_ERROR_STF;
+          break;
+      case(CAN_ESR_LEC_1):
+          /* Set CAN error code to FOR error */
+          hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
+          break;
+      case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
+          /* Set CAN error code to ACK error */
+          hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
+          break;
+      case(CAN_ESR_LEC_2):
+          /* Set CAN error code to BR error */
+          hcan->ErrorCode |= HAL_CAN_ERROR_BR;
+          break;
+      case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
+          /* Set CAN error code to BD error */
+          hcan->ErrorCode |= HAL_CAN_ERROR_BD;
+          break;
+      case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
+          /* Set CAN error code to CRC error */
+          hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
+          break;
+      default:
+          break;
+    }
+
+    /* Clear Last error code Flag */ 
+    hcan->Instance->ESR &= ~(CAN_ESR_LEC);
+  }
+  
+  /* Call the Error call Back in case of Errors */
+  if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
+  {
+    /* Set the CAN state ready to be able to start again the process */
+    hcan->State = HAL_CAN_STATE_READY;
+    /* Call Error callback function */
+    HAL_CAN_ErrorCallback(hcan);
+  }  
+}
+
+/**
+  * @brief  Transmission  complete callback in non blocking mode 
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Transmission  complete callback in non blocking mode 
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_RxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error CAN callback.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Group3 Peripheral State and Error functions
+ *  @brief   CAN Peripheral State functions 
+ *
+@verbatim   
+  ==============================================================================
+            ##### Peripheral State and Error functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) Check the CAN state.
+      (+) Check CAN Errors detected during interrupt process
+         
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  return the CAN state
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval HAL state
+  */
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
+{
+  /* Return CAN state */
+  return hcan->State;
+}
+
+/**
+  * @brief  Return the CAN error code
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval CAN Error Code
+  */
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
+{
+  return hcan->ErrorCode;
+}
+
+/**
+  * @}
+  */
+/**
+  * @brief  Initiates and transmits a CAN frame message.
+  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+  /* Disable Transmit mailbox empty Interrupt */
+  __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
+  
+  if(hcan->State == HAL_CAN_STATE_BUSY_TX)
+  {   
+    /* Disable Error warning Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
+    
+    /* Disable Error passive Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
+    
+    /* Disable Bus-off Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
+    
+    /* Disable Last error code Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
+    
+    /* Disable Error Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
+  }
+  
+  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_BUSY_RX;
+  }
+  else
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_READY;
+  }
+  
+  /* Transmission complete callback */ 
+  HAL_CAN_TxCpltCallback(hcan);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Receives a correct CAN frame.
+  * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.  
+  * @param  FIFONumber: Specify the FIFO number    
+  * @retval HAL status
+  * @retval None
+  */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+  /* Get the Id */
+  hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+  if (hcan->pRxMsg->IDE == CAN_ID_STD)
+  {
+    hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
+  }
+  else
+  {
+    hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
+  }
+  
+  hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+  /* Get the DLC */
+  hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+  /* Get the FMI */
+  hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
+  /* Get the data field */
+  hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+  hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
+  hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
+  hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
+  hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+  hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
+  hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
+  hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
+  /* Release the FIFO */
+  /* Release FIFO0 */
+  if (FIFONumber == CAN_FIFO0)
+  {
+    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+    
+    /* Disable FIFO 0 message pending Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
+  }
+  /* Release FIFO1 */
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+    
+    /* Disable FIFO 1 message pending Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
+  }
+  
+  if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+  {   
+    /* Disable Error warning Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
+    
+    /* Disable Error passive Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
+    
+    /* Disable Bus-off Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
+    
+    /* Disable Last error code Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
+    
+    /* Disable Error Interrupt */
+    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
+  }
+  
+  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
+  {
+    /* Disable CAN state */
+    hcan->State = HAL_CAN_STATE_BUSY_TX;
+  }
+  else
+  {
+    /* Change CAN state */
+    hcan->State = HAL_CAN_STATE_READY;
+  }
+
+  /* Receive complete callback */ 
+  HAL_CAN_RxCpltCallback(hcan);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#endif /* HAL_CAN_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_can.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,782 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_can.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of CAN HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CAN_H
+#define __STM32F4xx_HAL_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CAN
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  HAL State structures definition  
+  */ 
+typedef enum
+{
+  HAL_CAN_STATE_RESET             = 0x00,  /*!< CAN not yet initialized or disabled */
+  HAL_CAN_STATE_READY             = 0x01,  /*!< CAN initialized and ready for use   */  
+  HAL_CAN_STATE_BUSY              = 0x02,  /*!< CAN process is ongoing              */     
+  HAL_CAN_STATE_BUSY_TX           = 0x12,  /*!< CAN process is ongoing              */   
+  HAL_CAN_STATE_BUSY_RX           = 0x22,  /*!< CAN process is ongoing              */ 
+  HAL_CAN_STATE_BUSY_TX_RX        = 0x32,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_TIMEOUT           = 0x03,  /*!< Timeout state                       */
+  HAL_CAN_STATE_ERROR             = 0x04   /*!< CAN error state                     */  
+
+}HAL_CAN_StateTypeDef;
+
+/** 
+  * @brief  CAN init structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;  /*!< Specifies the length of a time quantum. 
+                            This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
+  
+  uint32_t Mode;       /*!< Specifies the CAN operating mode.
+                            This parameter can be a value of @ref CAN_operating_mode */
+
+  uint32_t SJW;        /*!< Specifies the maximum number of time quanta 
+                            the CAN hardware is allowed to lengthen or 
+                            shorten a bit to perform resynchronization.
+                            This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+  uint32_t BS1;        /*!< Specifies the number of time quanta in Bit Segment 1. 
+                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+                             
+  uint32_t BS2;        /*!< Specifies the number of time quanta in Bit Segment 2.
+                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+  
+  uint32_t TTCM;       /*!< Enable or disable the time triggered communication mode.
+                            This parameter can be set to ENABLE or DISABLE. */
+  
+  uint32_t ABOM;       /*!< Enable or disable the automatic bus-off management.
+                            This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t AWUM;       /*!< Enable or disable the automatic wake-up mode. 
+                            This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t NART;       /*!< Enable or disable the non-automatic retransmission mode.
+                            This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t RFLM;       /*!< Enable or disable the receive FIFO Locked mode.
+                            This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t TXFP;       /*!< Enable or disable the transmit FIFO priority.
+                            This parameter can be set to ENABLE or DISABLE */
+}CAN_InitTypeDef;
+
+/** 
+  * @brief  CAN filter configuration structure definition
+  */
+typedef struct
+{
+  uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit
+                                       configuration, first one for a 16-bit configuration).
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 
+                                              
+  uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit
+                                       configuration, second one for a 16-bit configuration).
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 
+
+  uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,
+                                       according to the mode (MSBs for a 32-bit configuration,
+                                       first one for a 16-bit configuration).
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 
+
+  uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,
+                                       according to the mode (LSBs for a 32-bit configuration,
+                                       second one for a 16-bit configuration).
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 
+
+  uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+                                       This parameter can be a value of @ref CAN_filter_FIFO */
+  
+  uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized. 
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
+
+  uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.
+                                       This parameter can be a value of @ref CAN_filter_mode */
+
+  uint32_t FilterScale;           /*!< Specifies the filter scale.
+                                       This parameter can be a value of @ref CAN_filter_scale */
+
+  uint32_t FilterActivation;      /*!< Enable or disable the filter.
+                                       This parameter can be set to ENABLE or DISABLE. */
+                                       
+  uint32_t BankNumber;            /*!< Select the start slave bank filter.
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ 
+  
+}CAN_FilterConfTypeDef;
+
+/** 
+  * @brief  CAN Tx message structure definition  
+  */
+typedef struct
+{
+  uint32_t StdId;    /*!< Specifies the standard identifier.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ 
+                        
+  uint32_t ExtId;    /*!< Specifies the extended identifier.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ 
+                        
+  uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
+                          This parameter can be a value of @ref CAN_identifier_type */
+
+  uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
+                          This parameter can be a value of @ref CAN_remote_transmission_request */                         
+
+  uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+
+  uint32_t Data[8];  /*!< Contains the data to be transmitted. 
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+   
+}CanTxMsgTypeDef;
+
+/** 
+  * @brief  CAN Rx message structure definition  
+  */
+typedef struct
+{
+  uint32_t StdId;       /*!< Specifies the standard identifier.
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ 
+
+  uint32_t ExtId;       /*!< Specifies the extended identifier.
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ 
+
+  uint32_t IDE;         /*!< Specifies the type of identifier for the message that will be received. 
+                             This parameter can be a value of @ref CAN_identifier_type */
+
+  uint32_t RTR;         /*!< Specifies the type of frame for the received message.
+                             This parameter can be a value of @ref CAN_remote_transmission_request */
+
+  uint32_t DLC;         /*!< Specifies the length of the frame that will be received.
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+
+  uint32_t Data[8];     /*!< Contains the data to be received. 
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+  uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+                        
+  uint32_t FIFONumber;  /*!< Specifies the receive FIFO number. 
+                             This parameter can be CAN_FIFO0 or CAN_FIFO1 */
+                       
+}CanRxMsgTypeDef;
+
+/** 
+  * @brief  CAN handle Structure definition  
+  */ 
+typedef struct
+{
+  CAN_TypeDef                 *Instance;  /*!< Register base address          */
+  
+  CAN_InitTypeDef             Init;       /*!< CAN required parameters        */
+  
+  CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */
+
+  CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure */
+  
+  __IO HAL_CAN_StateTypeDef   State;      /*!< CAN communication state        */
+  
+  HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
+  
+  __IO uint32_t               ErrorCode;  /*!< CAN Error code                 */
+  
+}CAN_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Constants
+  * @{
+  */
+
+/** @defgroup HAL CAN Error Code 
+  * @{
+  */
+#define   HAL_CAN_ERROR_NONE      0x00    /*!< No error             */
+#define   HAL_CAN_ERROR_EWG       0x01    /*!< EWG error            */   
+#define   HAL_CAN_ERROR_EPV       0x02    /*!< EPV error            */
+#define   HAL_CAN_ERROR_BOF       0x04    /*!< BOF error            */
+#define   HAL_CAN_ERROR_STF       0x08    /*!< Stuff error          */
+#define   HAL_CAN_ERROR_FOR       0x10    /*!< Form error           */
+#define   HAL_CAN_ERROR_ACK       0x20    /*!< Acknowledgment error */
+#define   HAL_CAN_ERROR_BR        0x40    /*!< Bit recessive        */
+#define   HAL_CAN_ERROR_BD        0x80    /*!< LEC dominant         */
+#define   HAL_CAN_ERROR_CRC       0x100   /*!< LEC transfer error   */
+/**
+  * @}
+  */  
+
+
+/** @defgroup CAN_InitStatus 
+  * @{
+  */
+#define CAN_INITSTATUS_FAILED       ((uint8_t)0x00)  /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS      ((uint8_t)0x01)  /*!< CAN initialization OK */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_operating_mode 
+  * @{
+  */
+#define CAN_MODE_NORMAL             ((uint32_t)0x00000000)                     /*!< Normal mode   */
+#define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */
+#define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */
+#define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+                           ((MODE) == CAN_MODE_LOOPBACK)|| \
+                           ((MODE) == CAN_MODE_SILENT) || \
+                           ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_synchronisation_jump_width 
+  * @{
+  */
+#define CAN_SJW_1TQ                 ((uint32_t)0x00000000)     /*!< 1 time quantum */
+#define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */
+#define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */
+#define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+                         ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 
+  * @{
+  */
+#define CAN_BS1_1TQ                 ((uint32_t)0x00000000)                                       /*!< 1 time quantum  */
+#define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */
+#define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */
+#define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */
+#define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */
+#define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */
+#define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */
+#define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */
+#define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */
+#define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */
+#define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */
+#define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */
+#define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */
+#define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */
+#define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */
+#define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 
+  * @{
+  */
+#define CAN_BS2_1TQ                 ((uint32_t)0x00000000)                       /*!< 1 time quantum */
+#define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */
+#define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */
+#define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */
+#define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */
+#define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */
+#define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */
+#define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_clock_prescaler 
+  * @{
+  */
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_number 
+  * @{
+  */
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_mode 
+  * @{
+  */
+#define CAN_FILTERMODE_IDMASK       ((uint8_t)0x00)  /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST       ((uint8_t)0x01)  /*!< Identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+                                  ((MODE) == CAN_FILTERMODE_IDLIST))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_scale 
+  * @{
+  */
+#define CAN_FILTERSCALE_16BIT       ((uint8_t)0x00)  /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT       ((uint8_t)0x01)  /*!< One 32-bit filter  */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+                                    ((SCALE) == CAN_FILTERSCALE_32BIT))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_FIFO
+  * @{
+  */
+#define CAN_FILTER_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
+
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+                                  ((FIFO) == CAN_FILTER_FIFO1))
+
+/* Legacy defines */
+#define CAN_FilterFIFO0  CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1  CAN_FILTER_FIFO1
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Start_bank_filter_for_slave_CAN 
+  * @{
+  */
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Tx 
+  * @{
+  */
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_identifier_type 
+  * @{
+  */
+#define CAN_ID_STD             ((uint32_t)0x00000000)  /*!< Standard Id */
+#define CAN_ID_EXT             ((uint32_t)0x00000004)  /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \
+                                ((IDTYPE) == CAN_ID_EXT))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_remote_transmission_request 
+  * @{
+  */
+#define CAN_RTR_DATA                ((uint32_t)0x00000000)  /*!< Data frame */
+#define CAN_RTR_REMOTE              ((uint32_t)0x00000002)  /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_transmit_constants 
+  * @{
+  */
+#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00)  /*!< CAN transmission failed */
+#define CAN_TXSTATUS_OK             ((uint8_t)0x01)  /*!< CAN transmission succeeded */
+#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02)  /*!< CAN transmission pending */
+#define CAN_TXSTATUS_NOMAILBOX      ((uint8_t)0x04)  /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_receive_FIFO_number_constants 
+  * @{
+  */
+#define CAN_FIFO0                   ((uint8_t)0x00)  /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1                   ((uint8_t)0x01)  /*!< CAN FIFO 1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_flags 
+  * @{
+  */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+   and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with 
+   CAN_GetFlagStatus() function.  */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0             ((uint32_t)0x00000500)  /*!< Request MailBox0 flag         */
+#define CAN_FLAG_RQCP1             ((uint32_t)0x00000508)  /*!< Request MailBox1 flag         */
+#define CAN_FLAG_RQCP2             ((uint32_t)0x00000510)  /*!< Request MailBox2 flag         */
+#define CAN_FLAG_TXOK0             ((uint32_t)0x00000501)  /*!< Transmission OK MailBox0 flag */
+#define CAN_FLAG_TXOK1             ((uint32_t)0x00000509)  /*!< Transmission OK MailBox1 flag */
+#define CAN_FLAG_TXOK2             ((uint32_t)0x00000511)  /*!< Transmission OK MailBox2 flag */
+#define CAN_FLAG_TME0              ((uint32_t)0x0000051A)  /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME1              ((uint32_t)0x0000051B)  /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME2              ((uint32_t)0x0000051C)  /*!< Transmit mailbox 0 empty flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FF0               ((uint32_t)0x00000203)  /*!< FIFO 0 Full flag    */
+#define CAN_FLAG_FOV0              ((uint32_t)0x00000204)  /*!< FIFO 0 Overrun flag */
+
+#define CAN_FLAG_FF1               ((uint32_t)0x00000403)  /*!< FIFO 1 Full flag    */
+#define CAN_FLAG_FOV1              ((uint32_t)0x00000404)  /*!< FIFO 1 Overrun flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU               ((uint32_t)0x00000103)  /*!< Wake up flag           */
+#define CAN_FLAG_SLAK              ((uint32_t)0x00000101)  /*!< Sleep acknowledge flag */
+#define CAN_FLAG_SLAKI             ((uint32_t)0x00000104)  /*!< Sleep acknowledge flag */
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. 
+         In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG               ((uint32_t)0x00000300)  /*!< Error warning flag   */
+#define CAN_FLAG_EPV               ((uint32_t)0x00000301)  /*!< Error passive flag   */
+#define CAN_FLAG_BOF               ((uint32_t)0x00000302)  /*!< Bus-Off flag         */
+
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_BOF)   || \
+                               ((FLAG) == CAN_FLAG_EPV)   || ((FLAG) == CAN_FLAG_EWG)   || \
+                               ((FLAG) == CAN_FLAG_WKU)   || ((FLAG) == CAN_FLAG_FOV0)  || \
+                               ((FLAG) == CAN_FLAG_FF0)   || ((FLAG) == CAN_FLAG_SLAK)  || \
+                               ((FLAG) == CAN_FLAG_FOV1)  || ((FLAG) == CAN_FLAG_FF1)   || \
+                               ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0))
+                               
+
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_SLAK)  || ((FLAG) == CAN_FLAG_RQCP2) || \
+                                ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
+                                ((FLAG) == CAN_FLAG_FF0)   || ((FLAG) == CAN_FLAG_FOV0)  || \
+                                ((FLAG) == CAN_FLAG_FF1)   || ((FLAG) == CAN_FLAG_FOV1)  || \
+                                ((FLAG) == CAN_FLAG_WKU))
+/**
+  * @}
+  */
+
+  
+/** @defgroup CAN_interrupts 
+  * @{
+  */ 
+#define CAN_IT_TME                  ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0                 ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_FF0                  ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */
+#define CAN_IT_FOV0                 ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */
+#define CAN_IT_FMP1                 ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_FF1                  ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */
+#define CAN_IT_FOV1                 ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU                  ((uint32_t)CAN_IER_WKUIE)  /*!< Wake-up interrupt           */
+#define CAN_IT_SLK                  ((uint32_t)CAN_IER_SLKIE)  /*!< Sleep acknowledge interrupt */
+
+/* Error Interrupts */
+#define CAN_IT_EWG                  ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt   */
+#define CAN_IT_EPV                  ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt   */
+#define CAN_IT_BOF                  ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt         */
+#define CAN_IT_LEC                  ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
+#define CAN_IT_ERR                  ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt           */
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0   CAN_IT_TME
+#define CAN_IT_RQCP1   CAN_IT_TME
+#define CAN_IT_RQCP2   CAN_IT_TME
+
+#define IS_CAN_IT(IT)        (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||\
+                             ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||\
+                             ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||\
+                             ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||\
+                             ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||\
+                             ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||\
+                             ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||\
+                             ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||\
+                             ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||\
+                             ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||\
+                             ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||\
+                             ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+/**
+  * @}
+  */
+
+/* Time out for INAK bit */
+#define INAK_TIMEOUT      ((uint32_t)0x0000FFFF)
+/* Time out for SLAK bit */
+#define SLAK_TIMEOUT      ((uint32_t)0x0000FFFF)
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0   ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1   ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2   ((uint8_t)0x02)
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset CAN handle state
+  * @param  __HANDLE__: specifies the CAN Handle.
+  * @retval None
+  */
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+
+/**
+  * @brief  Enable the specified CAN interrupts.
+  * @param  __HANDLE__: CAN handle
+  * @param  __INTERRUPT__: CAN Interrupt
+  * @retval None
+  */
+#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified CAN interrupts.
+  * @param  __HANDLE__: CAN handle
+  * @param  __INTERRUPT__: CAN Interrupt
+  * @retval None
+  */
+#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Return the number of pending received messages.
+  * @param  __HANDLE__: CAN handle
+  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @retval The number of pending message.
+  */
+#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
+
+/** @brief  Check whether the specified CAN flag is set or not.
+  * @param  __HANDLE__: CAN Handle
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+  *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+  *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+  *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+  *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+  *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+  *            @arg CAN_FLAG_WKU: Wake up Flag
+  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+  *            @arg CAN_FLAG_EWG: Error Warning Flag
+  *            @arg CAN_FLAG_EPV: Error Passive Flag
+  *            @arg CAN_FLAG_BOF: Bus-Off Flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define CAN_FLAG_MASK  ((uint32_t)0x000000FF)
+#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ ((((__HANDLE__)->Instance->ESR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))))
+
+/** @brief  Clear the specified CAN pending flag.
+  * @param  __HANDLE__: CAN Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+  *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+  *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+  *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+  *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+  *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+  *            @arg CAN_FLAG_WKU: Wake up Flag
+  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+  *            @arg CAN_FLAG_EWG: Error Warning Flag
+  *            @arg CAN_FLAG_EPV: Error Passive Flag
+  *            @arg CAN_FLAG_BOF: Bus-Off Flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 1)? (((__HANDLE__)->Instance->MSR) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__HANDLE__)->Instance->ESR) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))))
+
+/** @brief  Check if the specified CAN interrupt source is enabled or disabled.
+  * @param  __HANDLE__: CAN Handle
+  * @param  __INTERRUPT__: specifies the CAN interrupt source to check.
+  *          This parameter can be one of the following values:
+  *             @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
+  *             @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
+  *             @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+  * @brief  Check the transmission status of a CAN Frame.
+  * @param  __HANDLE__: CAN Handle
+  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+  * @retval The new status of transmission  (TRUE or FALSE).
+  */
+#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
+ ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
+
+
+
+/**
+  * @brief  Release the specified receive FIFO.
+  * @param  __HANDLE__: CAN handle
+  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @retval None
+  */
+#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) 
+
+/**
+  * @brief  Cancel a transmit request.
+  * @param  __HANDLE__: CAN Handle
+  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+  * @retval None
+  */
+#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
+ ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
+
+/**
+  * @brief  Enable or disable the DBG Freeze for CAN.
+  * @param  __HANDLE__: CAN Handle
+  * @param  __NEWSTATE__: new state of the CAN peripheral. 
+  *          This parameter can be: ENABLE (CAN reception/transmission is frozen
+  *          during debug. Reception FIFOs can still be accessed/controlled normally) 
+  *          or DISABLE (CAN is working during debug).
+  * @retval None
+  */
+#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
+((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) 
+   
+/* Exported functions --------------------------------------------------------*/  
+
+/* Initialization/de-initialization functions ***********************************/ 
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
+
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+
+/* Peripheral State functions ***************************************************/
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
+
+void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_CAN_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,401 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_conf_template.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   HAL configuration template file. 
+  *          This file should be copied to the application folder and renamed
+  *          to stm32f4xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+#define HAL_MODULE_ENABLED  
+#define HAL_ADC_MODULE_ENABLED  
+#define HAL_CAN_MODULE_ENABLED  
+#define HAL_CRC_MODULE_ENABLED  
+#define HAL_CRYP_MODULE_ENABLED  
+#define HAL_DAC_MODULE_ENABLED  
+#define HAL_DCMI_MODULE_ENABLED 
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED 
+#define HAL_ETH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_SDRAM_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED  
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED   
+#define HAL_IWDG_MODULE_ENABLED 
+#define HAL_LTDC_MODULE_ENABLED 
+#define HAL_PWR_MODULE_ENABLED   
+#define HAL_RCC_MODULE_ENABLED 
+//#define HAL_RNG_MODULE_ENABLED   
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED   
+#define HAL_SD_MODULE_ENABLED  
+#define HAL_SPI_MODULE_ENABLED   
+#define HAL_TIM_MODULE_ENABLED   
+#define HAL_UART_MODULE_ENABLED 
+#define HAL_USART_MODULE_ENABLED 
+#define HAL_IRDA_MODULE_ENABLED 
+#define HAL_SMARTCARD_MODULE_ENABLED 
+#define HAL_WWDG_MODULE_ENABLED  
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source 
+  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the external oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0x0F) /*!< tick interrupt priority */
+#define  USE_RTOS                     0
+#define  PREFETCH_ENABLE              1
+#define  INSTRUCTION_CACHE_ENABLE     1
+#define  DATA_CACHE_ENABLE            1
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2
+#define MAC_ADDR1   0
+#define MAC_ADDR2   0
+#define MAC_ADDR3   0
+#define MAC_ADDR4   0
+#define MAC_ADDR5   0
+
+/* Definition of the Ethernet driver buffers size and count */   
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/ 
+#define DP83848_PHY_ADDRESS             0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
+ 
+#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
+  
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
+ 
+#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
+
+#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
+#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
+
+#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
+#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+   
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f4xx_hal_cryp.h" 
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+ 
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */ 
+  
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */      
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+   
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,423 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_cortex.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   CORTEX HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the CORTEX:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions 
+  *
+  @verbatim  
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+
+    [..]  
+    *** How to configure Interrupts using CORTEX HAL driver ***
+    ===========================================================
+    [..]     
+    This section provides functions allowing to configure the NVIC interrupts (IRQ).
+    The Cortex-M4 exceptions are managed by CMSIS functions.
+   
+    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
+        function according to the following table.
+    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). 
+    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+    (#) please refer to programing manual for details in how to configure priority. 
+      
+     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. 
+         The pending IRQ priority will be managed only by the sub priority.
+   
+     -@- IRQ priority order (sorted by highest to lowest priority):
+        (+@) Lowest pre-emption priority
+        (+@) Lowest sub priority
+        (+@) Lowest hardware priority (IRQ number)
+ 
+    [..]  
+    *** How to configure Systick using CORTEX HAL driver ***
+    ========================================================
+    [..]
+    Setup SysTick Timer for time base.
+           
+   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
+       is a CMSIS function that:
+        (++) Configures the SysTick Reload register with value passed as function parameter.
+        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+        (++) Resets the SysTick Counter register.
+        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+        (++) Enables the SysTick Interrupt.
+        (++) Starts the SysTick Counter.
+    
+   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+       inside the stm32f4xx_hal_cortex.h file.
+
+   (+) You can change the SysTick IRQ priority by calling the
+       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function 
+       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+   (+) To adjust the SysTick time base, use the following formula:
+                            
+       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
+       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+       (++) Reload Value should not exceed 0xFFFFFF
+   
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX 
+  * @brief CORTEX HAL module driver
+  * @{
+  */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CORTEX_Private_Functions
+  * @{
+  */
+
+
+/** @defgroup CORTEX_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]
+      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+      Systick functionalities 
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Sets the priority grouping field (pre-emption priority and subpriority)
+  *         using the required unlock sequence.
+  * @param  PriorityGroup: The priority grouping bits length. 
+  *         This parameter can be one of the following values:
+  *         @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
+  *                                    4 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
+  *                                    3 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
+  *                                    2 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
+  *                                    1 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
+  *                                    0 bits for subpriority
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
+  *         The pending IRQ priority will be managed only by the subpriority. 
+  * @retval None
+  */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+  
+  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+  NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+  * @brief  Sets the priority of an interrupt.
+  * @param  IRQn: External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
+  * @param  PreemptPriority: The pre-emption priority for the IRQn channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority 
+  * @param  SubPriority: the subpriority level for the IRQ channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority.          
+  * @retval None
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{ 
+  uint32_t prioritygroup = 0x00;
+  
+  /* Check the parameters */
+  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+  
+  prioritygroup = NVIC_GetPriorityGrouping();
+  
+  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+  *         function should be called before. 
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)  
+  * @retval None
+  */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
+}
+
+/**
+  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)  
+  * @retval None
+  */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  /* Disable interrupt */
+  NVIC_DisableIRQ(IRQn);
+}
+
+/**
+  * @brief  Initiates a system reset request to reset the MCU.
+  * @param None
+  * @retval None
+  */
+void HAL_NVIC_SystemReset(void)
+{
+  /* System Reset */
+  NVIC_SystemReset();
+}
+
+/**
+  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+  *         Counter is in free running mode to generate periodic interrupts.
+  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+  * @retval status:  - 0  Function succeeded.
+  *                  - 1  Function failed.
+  */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+   return SysTick_Config(TicksNumb);
+}
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_Group2 Peripheral Control functions 
+ *  @brief   Cortex control functions 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================  
+    [..]
+      This subsection provides a set of functions allowing to control the CORTEX
+      (NVIC, SYSTICK) functionalities. 
+ 
+      
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
+  * @param  None
+  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+  */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+  /* Get the PRIGROUP[10:8] field value */
+  return NVIC_GetPriorityGrouping();
+}
+
+/**
+  * @brief  Gets the priority of an interrupt.
+  * @param  IRQn: External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
+  * @param   PriorityGroup: the priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *           @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
+  *                                      4 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
+  *                                      3 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
+  *                                      2 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
+  *                                      1 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
+  *                                      0 bits for subpriority
+  * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
+  * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
+  * @retval None
+  */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+  * @brief  Sets Pending bit of an external interrupt.
+  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of @ref IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)  
+  * @retval None
+  */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{ 
+  /* Set interrupt pending */
+  NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Gets Pending Interrupt (reads the pending register in the NVIC 
+  *         and returns the pending bit for the specified interrupt).
+  * @param  IRQn External interrupt number.
+  *          This parameter can be an enumerator of IRQn_Type enumeration
+  *          (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)  
+  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{ 
+  /* Return 1 if pending else 0 */
+  return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Clears the pending bit of an external interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)  
+  * @retval None
+  */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{ 
+  /* Clear pending interrupt */
+  NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+  * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
+  * @param IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)  
+  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{ 
+  /* Return 1 if active else 0 */
+  return NVIC_GetActive(IRQn);
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  CLKSource: specifies the SysTick clock source.
+  *          This parameter can be one of the following values:
+  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+  {
+    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+  }
+}
+
+/**
+  * @brief  This function handles SYSTICK interrupt request.
+  * @param  None
+  * @retval None
+  */
+void HAL_SYSTICK_IRQHandler(void)
+{
+  HAL_SYSTICK_Callback();
+}
+
+/**
+  * @brief  SYSTICK callback.
+  * @param  None
+  * @retval None
+  */
+__weak void HAL_SYSTICK_Callback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SYSTICK_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cortex.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,164 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_cortex.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of CORTEX HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CORTEX_H
+#define __STM32F4xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CORTEX
+  * @{
+  */ 
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants
+  * @{
+  */
+
+
+/** @defgroup CORTEX_Preemption_Priority_Group 
+  * @{
+  */
+
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
+                                                                 1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
+                                                                 0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_SysTick_clock_source 
+  * @{
+  */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
+#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+/**
+  * @}
+  */
+
+/* Exported Macros -----------------------------------------------------------*/
+
+/** @brief Configures the SysTick clock source.
+  * @param __CLKSRC__: specifies the SysTick clock source.
+  *   This parameter can be one of the following values:
+  *     @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+  *     @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__)                             \
+                            do {                                               \
+                                 if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK)   \
+                                  {                                            \
+                                    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;   \
+                                  }                                            \
+                                 else                                          \
+                                    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;  \
+                                } while(0)
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/* Initialization and de-initialization functions *******************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+
+/* Peripheral Control functions *************************************************/
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CORTEX_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,340 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_crc.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   CRC HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The CRC HAL driver can be used as follows:
+
+      (#) Enable CRC AHB clock using __CRC_CLK_ENABLE();
+
+      (#) Use HAL_CRC_Accumulate() function to compute the CRC value of 
+          a 32-bit data buffer using combination of the previous CRC value
+          and the new one.
+
+      (#) Use HAL_CRC_Calculate() function to compute the CRC Value of 
+          a new 32-bit data buffer. This function resets the CRC computation  
+          unit before starting the computation to avoid getting wrong CRC values.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CRC 
+  * @brief CRC HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CRC_Private_Functions
+  * @{
+  */
+
+/** @defgroup CRC_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions. 
+ *
+@verbatim    
+  ==============================================================================
+            ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the CRC according to the specified parameters 
+          in the CRC_InitTypeDef and create the associated handle
+      (+) DeInitialize the CRC peripheral
+      (+) Initialize the CRC MSP
+      (+) DeInitialize CRC MSP 
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the CRC according to the specified
+  *         parameters in the CRC_InitTypeDef and creates the associated handle.
+  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
+  *         the configuration information for CRC
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
+{
+  /* Check the CRC handle allocation */
+  if(hcrc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+  if(hcrc->State == HAL_CRC_STATE_RESET)
+  {
+    /* Init the low level hardware */
+    HAL_CRC_MspInit(hcrc);
+  }
+  
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+   
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the CRC peripheral.
+  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
+  *         the configuration information for CRC
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
+{
+  /* Check the CRC handle allocation */
+  if(hcrc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* DeInit the low level hardware */
+  HAL_CRC_MspDeInit(hcrc);
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hcrc);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRC MSP.
+  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
+  *         the configuration information for CRC
+  * @retval None
+  */
+__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CRC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the CRC MSP.
+  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
+  *         the configuration information for CRC
+  * @retval None
+  */
+__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CRC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Group2 Peripheral Control functions 
+ *  @brief    management functions. 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Compute the 32-bit CRC value of 32-bit data buffer,
+          using combination of the previous CRC value and the new one.
+      (+) Compute the 32-bit CRC value of 32-bit data buffer,
+          independently of the previous CRC value.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Computes the 32-bit CRC of 32-bit data buffer using combination
+  *         of the previous CRC value and the new one.
+  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
+  *         the configuration information for CRC
+  * @param  pBuffer: pointer to the buffer containing the data to be computed
+  * @param  BufferLength: length of the buffer to be computed
+  * @retval 32-bit CRC
+  */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index = 0;
+
+  /* Process Locked */
+  __HAL_LOCK(hcrc);
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* Enter Data to the CRC calculator */
+  for(index = 0; index < BufferLength; index++)
+  {
+    hcrc->Instance->DR = pBuffer[index];
+  }
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcrc);
+
+  /* Return the CRC computed value */
+  return hcrc->Instance->DR;
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of 32-bit data buffer independently
+  *         of the previous CRC value.
+  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
+  *         the configuration information for CRC
+  * @param  pBuffer: Pointer to the buffer containing the data to be computed
+  * @param  BufferLength: Length of the buffer to be computed
+  * @retval 32-bit CRC
+  */
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index = 0;
+
+  /* Process Locked */
+  __HAL_LOCK(hcrc); 
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* Reset CRC Calculation Unit */
+  __HAL_CRC_DR_RESET(hcrc);
+
+  /* Enter Data to the CRC calculator */
+  for(index = 0; index < BufferLength; index++)
+  {
+    hcrc->Instance->DR = pBuffer[index];
+  }
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcrc);
+
+  /* Return the CRC computed value */
+  return hcrc->Instance->DR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Group3 Peripheral State functions 
+ *  @brief    Peripheral State functions. 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### Peripheral State functions #####
+  ==============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the CRC state.
+  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
+  *         the configuration information for CRC
+  * @retval HAL state
+  */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
+{
+  return hcrc->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_crc.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,131 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_crc.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of CRC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CRC_H
+#define __STM32F4xx_HAL_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  CRC HAL State Structure definition  
+  */ 
+typedef enum
+{
+  HAL_CRC_STATE_RESET     = 0x00,  /*!< CRC not yet initialized or disabled */
+  HAL_CRC_STATE_READY     = 0x01,  /*!< CRC initialized and ready for use   */
+  HAL_CRC_STATE_BUSY      = 0x02,  /*!< CRC internal process is ongoing     */
+  HAL_CRC_STATE_TIMEOUT   = 0x03,  /*!< CRC timeout state                   */
+  HAL_CRC_STATE_ERROR     = 0x04   /*!< CRC error state                     */
+
+}HAL_CRC_StateTypeDef;
+
+/** 
+  * @brief  CRC handle Structure definition
+  */ 
+typedef struct
+{
+  CRC_TypeDef                 *Instance;  /*!< Register base address   */
+
+  HAL_LockTypeDef             Lock;       /*!< CRC locking object      */
+
+  __IO HAL_CRC_StateTypeDef   State;      /*!< CRC communication state */
+
+}CRC_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset CRC handle state
+  * @param  __HANDLE__: CRC handle
+  * @retval None
+  */
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
+
+/**
+  * @brief  Resets CRC Data Register.
+  * @param  __HANDLE__: CRC handle
+  * @retval None
+  */
+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+
+/* Peripheral Control functions  ************************************************/
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+
+/* Peripheral State functions  **************************************************/
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,3784 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_cryp.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   CRYP HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Cryptography (CRYP) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + AES processing functions
+  *           + DES processing functions
+  *           + TDES processing functions
+  *           + DMA callback functions
+  *           + CRYP IRQ handler management
+  *           + Peripheral State functions
+  *
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The CRYP HAL driver can be used as follows:
+
+      (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
+         (##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE()
+         (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
+             (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
+             (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
+             (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
+         (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
+             (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+             (+++) Configure and enable two DMA streams one for managing data transfer from
+                 memory to peripheral (input stream) and another stream for managing data
+                 transfer from peripheral to memory (output stream)
+             (+++) Associate the initilalized DMA handle to the CRYP DMA handle
+                 using  __HAL_LINKDMA()
+             (+++) Configure the priority and enable the NVIC for the transfer complete
+                 interrupt on the two DMA Streams. The output stream should have higher
+                 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+    
+      (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
+         (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
+         (##) The key size: 128, 192 and 256. This parameter is relevant only for AES
+         (##) The encryption/decryption key. It's size depends on the algorithm
+              used for encryption/decryption
+         (##) The initialization vector (counter). It is not used ECB mode.
+    
+      (#)Three processing (encryption/decryption) functions are available:
+         (##) Polling mode: encryption and decryption APIs are blocking functions
+              i.e. they process the data and wait till the processing is finished,
+              e.g. HAL_CRYP_AESCBC_Encrypt()
+         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
+              i.e. they process the data under interrupt,
+              e.g. HAL_CRYP_AESCBC_Encrypt_IT()
+         (##) DMA mode: encryption and decryption APIs are not blocking functions
+              i.e. the data transfer is ensured by DMA,
+              e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
+    
+      (#)When the processing function is called at first time after HAL_CRYP_Init()
+         the CRYP peripheral is initialized and processes the buffer in input.
+         At second call, the processing function performs an append of the already
+         processed buffer.
+         When a new data block is to be processed, call HAL_CRYP_Init() then the
+         processing function.
+    
+       (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CRYP 
+  * @brief CRYP HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize);
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);
+static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
+static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
+static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
+static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
+static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CRYP_Private_Functions
+  * @{
+  */
+
+/** @defgroup CRYP_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions. 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the CRYP according to the specified parameters 
+          in the CRYP_InitTypeDef and creates the associated handle
+      (+) DeInitialize the CRYP peripheral
+      (+) Initialize the CRYP MSP
+      (+) DeInitialize CRYP MSP 
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the CRYP according to the specified
+  *         parameters in the CRYP_InitTypeDef and creates the associated handle.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
+{ 
+  /* Check the CRYP handle allocation */
+  if(hcryp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
+  assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
+    
+  if(hcryp->State == HAL_CRYP_STATE_RESET)
+  {
+    /* Init the low level hardware */
+    HAL_CRYP_MspInit(hcryp);
+  }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Set the key size and data type*/
+  CRYP->CR = (uint32_t) (hcryp->Init.KeySize | hcryp->Init.DataType);
+  
+  /* Reset CrypInCount and CrypOutCount */
+  hcryp->CrypInCount = 0;
+  hcryp->CrypOutCount = 0;
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Set the default CRYP phase */
+  hcryp->Phase = HAL_CRYP_PHASE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the CRYP peripheral. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
+{
+  /* Check the CRYP handle allocation */
+  if(hcryp == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Set the default CRYP phase */
+  hcryp->Phase = HAL_CRYP_PHASE_READY;
+  
+  /* Reset CrypInCount and CrypOutCount */
+  hcryp->CrypInCount = 0;
+  hcryp->CrypOutCount = 0;
+  
+  /* Disable the CRYP Peripheral Clock */
+  __HAL_CRYP_DISABLE();
+  
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
+  HAL_CRYP_MspDeInit(hcryp);
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hcryp);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP MSP.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CRYP_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes CRYP MSP.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CRYP_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Group2 AES processing functions 
+ *  @brief   processing functions. 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### AES processing functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Encrypt plaintext using AES-128/192/256 using chaining modes
+      (+) Decrypt cyphertext using AES-128/192/256 using chaining modes
+    [..]  Three processing functions are available:
+      (+) Polling mode
+      (+) Interrupt mode
+      (+) DMA mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode
+  *         then encrypt pPlainData. The cypher data are available in pCypherData
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Timeout: Specify Timeout value 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  {
+    /* Set the key */
+    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+    
+    /* Set the CRYP peripheral in AES ECB mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB);
+    
+    /* Flush FIFO */
+    __HAL_CRYP_FIFO_FLUSH();
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Set the phase */
+    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+  }
+  
+    /* Write Plain Data and Get Cypher Data */
+    if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode
+  *         then encrypt pPlainData. The cypher data are available in pCypherData
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Timeout: Specify Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  {
+    /* Set the key */
+    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+    
+    /* Set the CRYP peripheral in AES ECB mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC);
+    
+    /* Set the Initialization Vector */
+    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+    
+    /* Flush FIFO */
+    __HAL_CRYP_FIFO_FLUSH();
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Set the phase */
+    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+  }
+  
+    /* Write Plain Data and Get Cypher Data */
+    if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode
+  *         then encrypt pPlainData. The cypher data are available in pCypherData
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Timeout: Specify Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{  
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  {
+    /* Set the key */
+    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+    
+    /* Set the CRYP peripheral in AES ECB mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR);
+    
+    /* Set the Initialization Vector */
+    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+    
+    /* Flush FIFO */
+    __HAL_CRYP_FIFO_FLUSH();
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Set the phase */
+    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+  }
+  
+    /* Write Plain Data and Get Cypher Data */
+    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode
+  *         then decrypted pCypherData. The cypher data are available in pPlainData
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Timeout: Specify Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+   uint32_t timeout = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  {
+    /* Set the key */
+    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+    
+    /* Set the CRYP peripheral in AES Key mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Get timeout */
+    timeout = HAL_GetTick() + Timeout;
+
+    while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+        
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    
+    /* Disable CRYP */
+    __HAL_CRYP_DISABLE();
+    
+    /* Reset the ALGOMODE bits*/
+    CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+    
+    /* Set the CRYP peripheral in AES ECB decryption mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+    /* Flush FIFO */
+    __HAL_CRYP_FIFO_FLUSH();
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Set the phase */
+    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+  }
+    
+    /* Write Plain Data and Get Cypher Data */
+    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode
+  *         then decrypted pCypherData. The cypher data are available in pPlainData
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Timeout: Specify Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+   uint32_t timeout = 0;   
+  
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  {
+    /* Set the key */
+    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+    
+    /* Set the CRYP peripheral in AES Key mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Get Timeout */
+    timeout = HAL_GetTick() + Timeout;
+
+    while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    
+    /* Reset the ALGOMODE bits*/
+    CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+    
+    /* Set the CRYP peripheral in AES CBC decryption mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+    
+    /* Set the Initialization Vector */
+    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+    
+    /* Flush FIFO */
+    __HAL_CRYP_FIFO_FLUSH();
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Set the phase */
+    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+  }
+  
+    /* Write Plain Data and Get Cypher Data */
+    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode
+  *         then decrypted pCypherData. The cypher data are available in pPlainData
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Timeout: Specify Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{  
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Check if initialization phase has already been performed */
+  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  {
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set the key */
+    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+    
+    /* Set the CRYP peripheral in AES CTR mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+    
+    /* Set the Initialization Vector */
+    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+    
+    /* Flush FIFO */
+    __HAL_CRYP_FIFO_FLUSH();
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Set the phase */
+    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+  }
+  
+    /* Write Plain Data and Get Cypher Data */
+    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pPlainData;
+    hcryp->pCrypOutBuffPtr = pCypherData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+      
+      /* Set the CRYP peripheral in AES ECB mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB);
+      
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+     /* Set the phase */
+     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  {
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->pCrypInBuffPtr += 16;
+    hcryp->CrypInCount -= 16;
+    if(hcryp->CrypInCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      /* Call the Input data transfer complete callback */
+      HAL_CRYP_InCpltCallback(hcryp);
+    }
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  {
+    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    hcryp->pCrypOutBuffPtr += 16;
+    hcryp->CrypOutCount -= 16;
+    if(hcryp->CrypOutCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      /* Process Locked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Call Input transfer complete callback */
+      HAL_CRYP_OutCpltCallback(hcryp);
+    }
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pPlainData;
+    hcryp->pCrypOutBuffPtr = pCypherData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {      
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+      
+      /* Set the CRYP peripheral in AES CBC mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC);
+      
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+      
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+     /* Set the phase */
+     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  {
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->pCrypInBuffPtr += 16;
+    hcryp->CrypInCount -= 16;
+    if(hcryp->CrypInCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      /* Call the Input data transfer complete callback */
+      HAL_CRYP_InCpltCallback(hcryp);
+    }
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  {
+    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    hcryp->pCrypOutBuffPtr += 16;
+    hcryp->CrypOutCount -= 16;
+    if(hcryp->CrypOutCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      /* Process Locked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Call Input transfer complete callback */
+      HAL_CRYP_OutCpltCallback(hcryp);
+    }
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pPlainData;
+    hcryp->pCrypOutBuffPtr = pCypherData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+      
+      /* Set the CRYP peripheral in AES CTR mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR);
+      
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+      
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+     /* Set the phase */
+     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  {
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->pCrypInBuffPtr += 16;
+    hcryp->CrypInCount -= 16;
+    if(hcryp->CrypInCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      /* Call the Input data transfer complete callback */
+      HAL_CRYP_InCpltCallback(hcryp);
+    }
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  {
+    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    hcryp->pCrypOutBuffPtr += 16;
+    hcryp->CrypOutCount -= 16;
+    if(hcryp->CrypOutCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Call Input transfer complete callback */
+      HAL_CRYP_OutCpltCallback(hcryp);
+    }
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t timeout = 0;   
+
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pCypherData;
+    hcryp->pCrypOutBuffPtr = pPlainData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+  /* Check if initialization phase has already been performed */
+  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  {
+    /* Set the key */
+    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+    
+    /* Set the CRYP peripheral in AES Key mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Get timeout */
+    timeout = HAL_GetTick() + 1;
+
+    while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+    {
+      /* Check for the Timeout */
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hcryp);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+    
+    /* Reset the ALGOMODE bits*/
+    CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+    
+    /* Set the CRYP peripheral in AES ECB decryption mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+    
+    /* Flush FIFO */
+    __HAL_CRYP_FIFO_FLUSH();
+    
+     /* Set the phase */
+     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+  }
+     
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  {
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->pCrypInBuffPtr += 16;
+    hcryp->CrypInCount -= 16;
+    if(hcryp->CrypInCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      /* Call the Input data transfer complete callback */
+      HAL_CRYP_InCpltCallback(hcryp);
+    }
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  {
+    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    hcryp->pCrypOutBuffPtr += 16;
+    hcryp->CrypOutCount -= 16;
+    if(hcryp->CrypOutCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Call Input transfer complete callback */
+      HAL_CRYP_OutCpltCallback(hcryp);
+    }
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CBC decryption mode using IT.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+
+  uint32_t timeout = 0;   
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    /* Get the buffer addresses and sizes */    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pCypherData;
+    hcryp->pCrypOutBuffPtr = pPlainData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+      
+      /* Set the CRYP peripheral in AES Key mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+      
+      /* Enable CRYP */
+      __HAL_CRYP_ENABLE();
+      
+    /* Get timeout */
+    timeout = HAL_GetTick() + 1;
+
+    while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+    {
+      /* Check for the Timeout */
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hcryp);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+    
+      /* Reset the ALGOMODE bits*/
+      CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+    
+      /* Set the CRYP peripheral in AES CBC decryption mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+    
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+    
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+    
+      /* Enable CRYP */
+      __HAL_CRYP_ENABLE();
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  {
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->pCrypInBuffPtr += 16;
+    hcryp->CrypInCount -= 16;
+    if(hcryp->CrypInCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      /* Call the Input data transfer complete callback */
+      HAL_CRYP_InCpltCallback(hcryp);
+    }
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  {
+    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    hcryp->pCrypOutBuffPtr += 16;
+    hcryp->CrypOutCount -= 16;
+    if(hcryp->CrypOutCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Call Input transfer complete callback */
+      HAL_CRYP_OutCpltCallback(hcryp);
+    }
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    /* Get the buffer addresses and sizes */    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pCypherData;
+    hcryp->pCrypOutBuffPtr = pPlainData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+      
+      /* Set the CRYP peripheral in AES CTR mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+      
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+      
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  {
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->pCrypInBuffPtr += 16;
+    hcryp->CrypInCount -= 16;
+    if(hcryp->CrypInCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      /* Call the Input data transfer complete callback */
+      HAL_CRYP_InCpltCallback(hcryp);
+    }
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  {
+    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    hcryp->pCrypOutBuffPtr += 16;
+    hcryp->CrypOutCount -= 16;
+    if(hcryp->CrypOutCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Call Input transfer complete callback */
+      HAL_CRYP_OutCpltCallback(hcryp);
+    }
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pPlainData;
+    outputaddr = (uint32_t)pCypherData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+      
+      /* Set the CRYP peripheral in AES ECB mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB);
+      
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+     /* Set the phase */
+     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+     
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pPlainData;
+    outputaddr = (uint32_t)pCypherData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+      
+      /* Set the CRYP peripheral in AES ECB mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC);
+      
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+      
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+       /* Set the phase */
+       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+     }
+     /* Set the input and output addresses and start DMA transfer */ 
+     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+     
+     /* Process Unlocked */
+     __HAL_UNLOCK(hcryp);
+     
+     /* Return function status */
+     return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pPlainData;
+    outputaddr = (uint32_t)pCypherData;
+    
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+      
+      /* Set the CRYP peripheral in AES ECB mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR);
+      
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+      
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+       /* Set the phase */
+       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t timeout = 0;   
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pCypherData;
+    outputaddr = (uint32_t)pPlainData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+    /* Set the key */
+    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+    
+    /* Set the CRYP peripheral in AES Key mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Get timeout */
+    timeout = HAL_GetTick() + 1;
+    
+    while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+    {
+      /* Check for the Timeout */
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hcryp);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+    
+    /* Reset the ALGOMODE bits*/
+    CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+    
+    /* Set the CRYP peripheral in AES ECB decryption mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+    
+    /* Flush FIFO */
+    __HAL_CRYP_FIFO_FLUSH();
+    
+     /* Set the phase */
+     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+     
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+     /* Process Unlocked */
+     __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t timeout = 0;   
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pCypherData;
+    outputaddr = (uint32_t)pPlainData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+      
+      /* Set the CRYP peripheral in AES Key mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+      
+      /* Enable CRYP */
+      __HAL_CRYP_ENABLE();
+      
+      /* Get timeout */
+      timeout = HAL_GetTick() + 1;
+
+      while(HAL_IS_BIT_SET(CRYP->SR, CRYP_FLAG_BUSY))
+      {
+        /* Check for the Timeout */
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+      
+      /* Reset the ALGOMODE bits*/
+      CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+      
+      /* Set the CRYP peripheral in AES CBC decryption mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+      
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+      
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{  
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pCypherData;
+    outputaddr = (uint32_t)pPlainData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+      
+      /* Set the CRYP peripheral in AES CTR mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+      
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+      
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;   
+  }
+}
+
+
+/**
+  * @}
+  */
+/** @defgroup CRYP_Group3 DES processing functions 
+ *  @brief   processing functions. 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### DES processing functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Encrypt plaintext using DES using ECB or CBC chaining modes
+      (+) Decrypt cyphertext using ECB or CBC chaining modes
+    [..]  Three processing functions are available:
+      (+) Polling mode
+      (+) Interrupt mode
+      (+) DMA mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the CRYP peripheral in DES ECB encryption mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Timeout: Specify Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Set CRYP peripheral in DES ECB encryption mode */
+  CRYP_SetDESECBMode(hcryp, 0);
+  
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE();
+  
+  /* Write Plain Data and Get Cypher Data */
+  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Timeout: Specify Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Set CRYP peripheral in DES ECB decryption mode */
+  CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
+  
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE();
+  
+  /* Write Plain Data and Get Cypher Data */
+  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in DES CBC encryption mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Timeout: Specify Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Set CRYP peripheral in DES CBC encryption mode */
+  CRYP_SetDESCBCMode(hcryp, 0);
+  
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE();
+  
+  /* Write Plain Data and Get Cypher Data */
+  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Timeout: Specify Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Set CRYP peripheral in DES CBC decryption mode */
+  CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+  
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE();
+  
+  /* Write Plain Data and Get Cypher Data */
+  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in DES ECB encryption mode using IT.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pPlainData;
+    hcryp->pCrypOutBuffPtr = pCypherData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set CRYP peripheral in DES ECB encryption mode */
+    CRYP_SetDESECBMode(hcryp, 0);
+    
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  {
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    
+    hcryp->pCrypInBuffPtr += 8;
+    hcryp->CrypInCount -= 8;
+    if(hcryp->CrypInCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      /* Call the Input data transfer complete callback */
+      HAL_CRYP_InCpltCallback(hcryp);
+    }
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  {
+    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    
+    hcryp->pCrypOutBuffPtr += 8;
+    hcryp->CrypOutCount -= 8;
+    if(hcryp->CrypOutCount == 0)
+    {
+      /* Disable IT */
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      /* Disable CRYP */
+      __HAL_CRYP_DISABLE();
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Call Input transfer complete callback */
+      HAL_CRYP_OutCpltCallback(hcryp);
+    }
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in DES CBC encryption mode using interrupt.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pPlainData;
+    hcryp->pCrypOutBuffPtr = pCypherData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set CRYP peripheral in DES CBC encryption mode */
+    CRYP_SetDESCBCMode(hcryp, 0);
+    
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  {
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+
+    hcryp->pCrypInBuffPtr += 8;
+    hcryp->CrypInCount -= 8;
+    if(hcryp->CrypInCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      /* Call the Input data transfer complete callback */
+      HAL_CRYP_InCpltCallback(hcryp);
+    }
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  {
+    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+
+    hcryp->pCrypOutBuffPtr += 8;
+    hcryp->CrypOutCount -= 8;
+    if(hcryp->CrypOutCount == 0)
+    {
+      /* Disable IT */
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      /* Disable CRYP */
+      __HAL_CRYP_DISABLE();
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Call Input transfer complete callback */
+      HAL_CRYP_OutCpltCallback(hcryp);
+    }
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using IT.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pCypherData;
+    hcryp->pCrypOutBuffPtr = pPlainData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set CRYP peripheral in DES ECB decryption mode */
+    CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
+    
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  {
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    
+    hcryp->pCrypInBuffPtr += 8;
+    hcryp->CrypInCount -= 8;
+    if(hcryp->CrypInCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      /* Call the Input data transfer complete callback */
+      HAL_CRYP_InCpltCallback(hcryp);
+    }
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  {
+    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+
+    hcryp->pCrypOutBuffPtr += 8;
+    hcryp->CrypOutCount -= 8;
+    if(hcryp->CrypOutCount == 0)
+    {
+      /* Disable IT */
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      /* Disable CRYP */
+      __HAL_CRYP_DISABLE();
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Call Input transfer complete callback */
+      HAL_CRYP_OutCpltCallback(hcryp);
+    }
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using interrupt.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pCypherData;
+    hcryp->pCrypOutBuffPtr = pPlainData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set CRYP peripheral in DES CBC decryption mode */
+    CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+    
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  {
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+
+    hcryp->pCrypInBuffPtr += 8;
+    hcryp->CrypInCount -= 8;
+    if(hcryp->CrypInCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      /* Call the Input data transfer complete callback */
+      HAL_CRYP_InCpltCallback(hcryp);
+    }
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  {
+    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+
+    hcryp->pCrypOutBuffPtr += 8;
+    hcryp->CrypOutCount -= 8;
+    if(hcryp->CrypOutCount == 0)
+    {
+      /* Disable IT */
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      /* Disable CRYP */
+      __HAL_CRYP_DISABLE();
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Call Input transfer complete callback */
+      HAL_CRYP_OutCpltCallback(hcryp);
+    }
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in DES ECB encryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pPlainData;
+    outputaddr = (uint32_t)pCypherData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set CRYP peripheral in DES ECB encryption mode */
+    CRYP_SetDESECBMode(hcryp, 0);
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in DES CBC encryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pPlainData;
+    outputaddr = (uint32_t)pCypherData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set CRYP peripheral in DES CBC encryption mode */
+    CRYP_SetDESCBCMode(hcryp, 0);
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pCypherData;
+    outputaddr = (uint32_t)pPlainData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set CRYP peripheral in DES ECB decryption mode */
+    CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pCypherData;
+    outputaddr = (uint32_t)pPlainData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set CRYP peripheral in DES CBC decryption mode */
+    CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Group4 TDES processing functions 
+ *  @brief   processing functions. 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### TDES processing functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Encrypt plaintext using TDES based on ECB or CBC chaining modes
+      (+) Decrypt cyphertext using TDES based on ECB or CBC chaining modes
+    [..]  Three processing functions are available:
+      (+) Polling mode
+      (+) Interrupt mode
+      (+) DMA mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the CRYP peripheral in TDES ECB encryption mode
+  *         then encrypt pPlainData. The cypher data are available in pCypherData
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Timeout: Specify Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Set CRYP peripheral in TDES ECB encryption mode */
+  CRYP_SetTDESECBMode(hcryp, 0);
+  
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE();
+  
+  /* Write Plain Data and Get Cypher Data */
+  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in TDES ECB decryption mode
+  *         then decrypted pCypherData. The cypher data are available in pPlainData
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Timeout: Specify Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{  
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Set CRYP peripheral in TDES ECB decryption mode */
+  CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
+  
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE();
+  
+  /* Write Cypher Data and Get Plain Data */
+  if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in TDES CBC encryption mode
+  *         then encrypt pPlainData. The cypher data are available in pCypherData
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Timeout: Specify Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Set CRYP peripheral in TDES CBC encryption mode */
+  CRYP_SetTDESCBCMode(hcryp, 0);
+  
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE();
+  
+  /* Write Plain Data and Get Cypher Data */
+  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in TDES CBC decryption mode
+  *         then decrypted pCypherData. The cypher data are available in pPlainData
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Timeout: Specify Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Set CRYP peripheral in TDES CBC decryption mode */
+  CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+  
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE();
+  
+  /* Write Cypher Data and Get Plain Data */
+  if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pPlainData;
+    hcryp->pCrypOutBuffPtr = pCypherData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set CRYP peripheral in TDES ECB encryption mode */
+    CRYP_SetTDESECBMode(hcryp, 0);
+    
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  {
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+
+    hcryp->pCrypInBuffPtr += 8;
+    hcryp->CrypInCount -= 8;
+    if(hcryp->CrypInCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      /* Call the Input data transfer complete callback */
+      HAL_CRYP_InCpltCallback(hcryp);
+    }
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  {
+    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+
+    hcryp->pCrypOutBuffPtr += 8;
+    hcryp->CrypOutCount -= 8;
+    if(hcryp->CrypOutCount == 0)
+    {
+      /* Disable IT */
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      /* Disable CRYP */
+      __HAL_CRYP_DISABLE();
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Call the Output data transfer complete callback */
+      HAL_CRYP_OutCpltCallback(hcryp);
+    }
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in TDES CBC encryption mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pPlainData;
+    hcryp->pCrypOutBuffPtr = pCypherData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set CRYP peripheral in TDES CBC encryption mode */
+    CRYP_SetTDESCBCMode(hcryp, 0);
+    
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  {
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+
+    hcryp->pCrypInBuffPtr += 8;
+    hcryp->CrypInCount -= 8;
+    if(hcryp->CrypInCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      /* Call the Input data transfer complete callback */
+      HAL_CRYP_InCpltCallback(hcryp);
+    }
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  {
+    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+        
+    hcryp->pCrypOutBuffPtr += 8;
+    hcryp->CrypOutCount -= 8;
+    if(hcryp->CrypOutCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      /* Disable CRYP */
+      __HAL_CRYP_DISABLE();
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Call Input transfer complete callback */
+      HAL_CRYP_OutCpltCallback(hcryp);
+    }
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in TDES ECB decryption mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pCypherData;
+    hcryp->pCrypOutBuffPtr = pPlainData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set CRYP peripheral in TDES ECB decryption mode */
+    CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
+    
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  {
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+
+    hcryp->pCrypInBuffPtr += 8;
+    hcryp->CrypInCount -= 8;
+    if(hcryp->CrypInCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      /* Call the Input data transfer complete callback */
+      HAL_CRYP_InCpltCallback(hcryp);
+    }
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  {
+    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+
+    hcryp->pCrypOutBuffPtr += 8;
+    hcryp->CrypOutCount -= 8;
+    if(hcryp->CrypOutCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      /* Disable CRYP */
+      __HAL_CRYP_DISABLE();
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Call Input transfer complete callback */
+      HAL_CRYP_OutCpltCallback(hcryp);
+    }
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+} 
+
+/**
+  * @brief  Initializes the CRYP peripheral in TDES CBC decryption mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pCypherData;
+    hcryp->pCrypOutBuffPtr = pPlainData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set CRYP peripheral in TDES CBC decryption mode */
+    CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+    
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE();
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  {
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+
+    hcryp->pCrypInBuffPtr += 8;
+    hcryp->CrypInCount -= 8;
+    if(hcryp->CrypInCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      /* Call the Input data transfer complete callback */
+      HAL_CRYP_InCpltCallback(hcryp);
+    }
+  }
+  else if(__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  {
+    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+
+    hcryp->pCrypOutBuffPtr += 8;
+    hcryp->CrypOutCount -= 8;
+    if(hcryp->CrypOutCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      /* Disable CRYP */
+      __HAL_CRYP_DISABLE();
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Call Input transfer complete callback */
+      HAL_CRYP_OutCpltCallback(hcryp);
+    }
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in TDES ECB encryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pPlainData;
+    outputaddr = (uint32_t)pCypherData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set CRYP peripheral in TDES ECB encryption mode */
+    CRYP_SetTDESECBMode(hcryp, 0);
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in TDES CBC encryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pPlainData;
+    outputaddr = (uint32_t)pCypherData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set CRYP peripheral in TDES CBC encryption mode */
+    CRYP_SetTDESCBCMode(hcryp, 0);
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in TDES ECB decryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pCypherData;
+    outputaddr = (uint32_t)pPlainData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set CRYP peripheral in TDES ECB decryption mode */
+    CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in TDES CBC decryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pCypherData;
+    outputaddr = (uint32_t)pPlainData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set CRYP peripheral in TDES CBC decryption mode */
+    CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Group5 DMA callback functions 
+ *  @brief   DMA callback functions. 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### DMA callback functions  #####
+  ==============================================================================  
+    [..]  This section provides DMA callback functions:
+      (+) DMA Input data transfer complete
+      (+) DMA Output data transfer complete
+      (+) DMA error
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Input FIFO transfer completed callbacks.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CRYP_InCpltCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Output FIFO transfer completed callbacks.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CRYP_OutCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  CRYP error callbacks.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CRYP_ErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Group6 CRYP IRQ handler management  
+ *  @brief   CRYP IRQ handler.
+ *
+@verbatim   
+  ==============================================================================
+                ##### CRYP IRQ handler management #####
+  ==============================================================================  
+[..]  This section provides CRYP IRQ handler function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function handles CRYP interrupt request.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
+{
+  switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
+  {
+  case CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT:
+    HAL_CRYP_TDESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
+    break;
+    
+  case CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT:
+    HAL_CRYP_TDESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
+    break;
+    
+  case CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT:
+    HAL_CRYP_TDESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
+    break;
+    
+  case CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT:
+    HAL_CRYP_TDESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
+    break;
+    
+  case CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT:
+    HAL_CRYP_DESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
+    break;
+    
+  case CRYP_CR_ALGOMODE_DES_ECB_DECRYPT:
+    HAL_CRYP_DESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
+    break;
+    
+  case CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT:
+    HAL_CRYP_DESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
+    break;
+    
+  case CRYP_CR_ALGOMODE_DES_CBC_DECRYPT:
+    HAL_CRYP_DESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
+    break;
+    
+  case CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT:
+    HAL_CRYP_AESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
+    break;
+    
+  case CRYP_CR_ALGOMODE_AES_ECB_DECRYPT:
+    HAL_CRYP_AESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
+    break;
+    
+  case CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT:
+    HAL_CRYP_AESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
+    break;
+    
+  case CRYP_CR_ALGOMODE_AES_CBC_DECRYPT:
+    HAL_CRYP_AESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
+    break;
+    
+  case CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT:
+    HAL_CRYP_AESCTR_Encrypt_IT(hcryp, NULL, 0, NULL);       
+    break;
+    
+  case CRYP_CR_ALGOMODE_AES_CTR_DECRYPT:
+    HAL_CRYP_AESCTR_Decrypt_IT(hcryp, NULL, 0, NULL);        
+    break;
+    
+  default:
+    break;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Group7 Peripheral State functions 
+ *  @brief   Peripheral State functions. 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### Peripheral State functions #####
+  ==============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the CRYP state.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL state
+  */
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
+{
+  return hcryp->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  DMA CRYP Input Data process complete callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)  
+{
+  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  
+  /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
+     in the DMACR register */
+  CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
+  
+  /* Call input data transfer complete callback */
+  HAL_CRYP_InCpltCallback(hcryp);
+}
+
+/**
+  * @brief  DMA CRYP Output Data process complete callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
+{
+  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  
+  /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit
+     in the DMACR register */
+  CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
+  
+  /* Disable CRYP */
+  __HAL_CRYP_DISABLE();
+  
+  /* Change the CRYP state to ready */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Call output data transfer complete callback */
+  HAL_CRYP_OutCpltCallback(hcryp);
+}
+
+/**
+  * @brief  DMA CRYP communication error callback. 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
+{
+  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  hcryp->State= HAL_CRYP_STATE_READY;
+  HAL_CRYP_ErrorCallback(hcryp);
+}
+
+/**
+  * @brief  Writes the Key in Key registers. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Key: Pointer to Key buffer
+  * @param  KeySize: Size of Key
+  * @retval None
+  */
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
+{
+  uint32_t keyaddr = (uint32_t)Key;
+  
+  switch(KeySize)
+  {
+  case CRYP_KEYSIZE_256B:
+    /* Key Initialisation */
+    CRYP->K0LR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K0RR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
+    break;
+  case CRYP_KEYSIZE_192B:
+    CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
+    break;
+  case CRYP_KEYSIZE_128B:       
+    CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
+    break;
+  default:
+    break;
+  }
+}
+
+/**
+  * @brief  Writes the InitVector/InitCounter in IV registers. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  InitVector: Pointer to InitVector/InitCounter buffer
+  * @param  IVSize: Size of the InitVector/InitCounter
+  * @retval None
+  */
+static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)
+{
+  uint32_t ivaddr = (uint32_t)InitVector;
+  
+  switch(IVSize)
+  {
+  case CRYP_KEYSIZE_128B:
+    CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
+    ivaddr+=4;
+    CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
+    ivaddr+=4;
+    CRYP->IV1LR = __REV(*(uint32_t*)(ivaddr));
+    ivaddr+=4;
+    CRYP->IV1RR = __REV(*(uint32_t*)(ivaddr));
+    break;
+    /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */
+  case CRYP_KEYSIZE_192B:
+    CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
+    ivaddr+=4;
+    CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
+    break;
+  case CRYP_KEYSIZE_256B:
+    CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
+    ivaddr+=4;
+    CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
+    break;
+  default:
+    break;
+  }
+}
+
+/**
+  * @brief  Process Data: Writes Input data in polling mode and read the output data
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Input: Pointer to the Input buffer
+  * @param  Ilength: Length of the Input buffer, must be a multiple of 16.
+  * @param  Output: Pointer to the returned buffer
+  * @retval None
+  */
+static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
+{
+  uint32_t timeout = 0;
+  
+  uint32_t i = 0;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+  
+  for(i=0; (i < Ilength); i+=16)
+  {
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    
+    /* Get timeout */
+    timeout = HAL_GetTick() + Timeout;
+
+    while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
+    {    
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+        
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Process Data: Write Input data in polling mode. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Input: Pointer to the Input buffer
+  * @param  Ilength: Length of the Input buffer, must be a multiple of 8
+  * @param  Output: Pointer to the returned buffer
+  * @param  Timeout: Specify Timeout value  
+  * @retval None
+  */
+static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  
+  uint32_t i = 0;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+  
+  for(i=0; (i < Ilength); i+=8)
+  {
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    
+    /* Get timeout */
+    timeout = HAL_GetTick() + Timeout;
+    
+    while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the DMA configuration and start the DMA transfer
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  inputaddr: address of the Input buffer
+  * @param  Size: Size of the Input buffer, must be a multiple of 16.
+  * @param  outputaddr: address of the Output buffer
+  * @retval None
+  */
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
+{
+  /* Set the CRYP DMA transfer complete callback */
+  hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
+  /* Set the DMA error callback */
+  hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
+  
+  /* Set the CRYP DMA transfer complete callback */
+  hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
+  /* Set the DMA error callback */
+  hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
+  
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE();
+  
+  /* Enable the DMA In DMA Stream */
+  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&CRYP->DR, Size/4);
+  
+  /* Enable In DMA request */
+  CRYP->DMACR = (CRYP_DMACR_DIEN);
+  
+  /* Enable the DMA Out DMA Stream */
+  HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&CRYP->DOUT, outputaddr, Size/4);
+  
+  /* Enable Out DMA request */
+  CRYP->DMACR |= CRYP_DMACR_DOEN;
+ 
+}
+
+/**
+  * @brief  Sets the CRYP peripheral in DES ECB mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Direction: Encryption or decryption
+  * @retval None
+  */
+static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
+{
+  /* Check if initialization phase has already been performed */
+  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  {
+    /* Set the CRYP peripheral in AES ECB mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_DES_ECB | Direction);
+    
+    /* Set the key */
+    CRYP->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
+    CRYP->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
+    
+    /* Flush FIFO */
+    __HAL_CRYP_FIFO_FLUSH();
+    
+    /* Set the phase */
+    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+  }
+}
+
+/**
+  * @brief  Sets the CRYP peripheral in DES CBC mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Direction: Encryption or decryption
+  * @retval None
+  */
+static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
+{
+  /* Check if initialization phase has already been performed */
+  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  {
+    /* Set the CRYP peripheral in AES ECB mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_DES_CBC | Direction);
+    
+    /* Set the key */
+    CRYP->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
+    CRYP->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
+    
+    /* Set the Initialization Vector */
+    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
+    
+    /* Flush FIFO */
+    __HAL_CRYP_FIFO_FLUSH();
+    
+    /* Set the phase */
+    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+  }
+}
+
+/**
+  * @brief  Sets the CRYP peripheral in TDES ECB mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Direction: Encryption or decryption
+  * @retval None
+  */
+static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
+{
+  /* Check if initialization phase has already been performed */
+  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  {
+    /* Set the CRYP peripheral in AES ECB mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_TDES_ECB | Direction);
+    
+    /* Set the key */
+    CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
+    
+    /* Flush FIFO */
+    __HAL_CRYP_FIFO_FLUSH();
+    
+    /* Set the phase */
+    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+  }
+}
+
+/**
+  * @brief  Sets the CRYP peripheral in TDES CBC mode
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Direction: Encryption or decryption
+  * @retval None
+  */
+static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
+{
+  /* Check if initialization phase has already been performed */
+  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  {
+    /* Set the CRYP peripheral in AES CBC mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_TDES_CBC | Direction);
+    
+    /* Set the key */
+    CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
+    
+    /* Set the Initialization Vector */
+    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
+    
+    /* Flush FIFO */
+    __HAL_CRYP_FIFO_FLUSH();
+    
+    /* Set the phase */
+    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+#endif /* HAL_CRYP_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,404 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_cryp.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of CRYP HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CRYP_H
+#define __STM32F4xx_HAL_CRYP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRYP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  CRYP Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t DataType;    /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+                             This parameter can be a value of @ref CRYP_Data_Type */
+
+  uint32_t KeySize;     /*!< Used only in AES mode only : 128, 192 or 256 bit key length. 
+                             This parameter can be a value of @ref CRYP_Key_Size */
+
+  uint8_t* pKey;        /*!< The key used for encryption/decryption */
+
+  uint8_t* pInitVect;   /*!< The initialization vector used also as initialization
+                             counter in CTR mode */
+
+  uint8_t IVSize;       /*!< The size of initialization vector. 
+                             This parameter (called nonce size in CCM) is used only 
+                             in AES-128/192/256 encryption/decryption CCM mode */
+
+  uint8_t TagSize;      /*!< The size of returned authentication TAG. 
+                             This parameter is used only in AES-128/192/256 
+                             encryption/decryption CCM mode */
+
+  uint8_t* Header;      /*!< The header used in GCM and CCM modes */
+
+  uint16_t HeaderSize;  /*!< The size of header buffer in bytes */
+
+  uint8_t* pScratch;    /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes.
+                             This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */
+}CRYP_InitTypeDef;
+
+/** 
+  * @brief HAL CRYP State structures definition
+  */
+typedef enum
+{
+  HAL_CRYP_STATE_RESET             = 0x00,  /*!< CRYP not yet initialized or disabled  */
+  HAL_CRYP_STATE_READY             = 0x01,  /*!< CRYP initialized and ready for use    */
+  HAL_CRYP_STATE_BUSY              = 0x02,  /*!< CRYP internal processing is ongoing   */
+  HAL_CRYP_STATE_TIMEOUT           = 0x03,  /*!< CRYP timeout state                    */
+  HAL_CRYP_STATE_ERROR             = 0x04   /*!< CRYP error state                      */
+}HAL_CRYP_STATETypeDef;
+
+/** 
+  * @brief HAL CRYP phase structures definition
+  */
+typedef enum
+{
+  HAL_CRYP_PHASE_READY             = 0x01,    /*!< CRYP peripheral is ready for initialization. */
+  HAL_CRYP_PHASE_PROCESS           = 0x02,    /*!< CRYP peripheral is in processing phase */
+  HAL_CRYP_PHASE_FINAL             = 0x03     /*!< CRYP peripheral is in final phase
+                                                   This is relevant only with CCM and GCM modes */
+}HAL_PhaseTypeDef;
+
+/** 
+  * @brief  CRYP handle Structure definition
+  */ 
+typedef struct
+{
+      CRYP_InitTypeDef         Init;             /*!< CRYP required parameters */
+
+      uint8_t                  *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+      uint8_t                  *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+      __IO uint16_t            CrypInCount;      /*!< Counter of inputed data */
+
+      __IO uint16_t            CrypOutCount;     /*!< Counter of outputed data */
+
+      HAL_StatusTypeDef        Status;           /*!< CRYP peripheral status */
+
+      HAL_PhaseTypeDef         Phase;            /*!< CRYP peripheral phase */
+
+      DMA_HandleTypeDef        *hdmain;          /*!< CRYP In DMA handle parameters */
+
+      DMA_HandleTypeDef        *hdmaout;         /*!< CRYP Out DMA handle parameters */
+
+      HAL_LockTypeDef          Lock;             /*!< CRYP locking object */
+
+   __IO  HAL_CRYP_STATETypeDef State;            /*!< CRYP peripheral state */
+}CRYP_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRYP_Exported_Constants
+  * @{
+  */
+
+/** @defgroup CRYP_Key_Size 
+  * @{
+  */
+#define CRYP_KEYSIZE_128B         ((uint32_t)0x00000000)
+#define CRYP_KEYSIZE_192B         CRYP_CR_KEYSIZE_0
+#define CRYP_KEYSIZE_256B         CRYP_CR_KEYSIZE_1
+
+#define IS_CRYP_KEYSIZE(KEYSIZE)  (((KEYSIZE) == CRYP_KEYSIZE_128B)  || \
+                                   ((KEYSIZE) == CRYP_KEYSIZE_192B)  || \
+                                   ((KEYSIZE) == CRYP_KEYSIZE_256B))
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Data_Type 
+  * @{
+  */
+#define CRYP_DATATYPE_32B         ((uint32_t)0x00000000)
+#define CRYP_DATATYPE_16B         CRYP_CR_DATATYPE_0
+#define CRYP_DATATYPE_8B          CRYP_CR_DATATYPE_1
+#define CRYP_DATATYPE_1B          CRYP_CR_DATATYPE
+
+#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DATATYPE_32B) || \
+                                    ((DATATYPE) == CRYP_DATATYPE_16B) || \
+                                    ((DATATYPE) == CRYP_DATATYPE_8B)  || \
+                                    ((DATATYPE) == CRYP_DATATYPE_1B))  
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_AlgoModeDirection
+  * @{
+  */ 
+#define CRYP_CR_ALGOMODE_DIRECTION         ((uint32_t)0x0008003C)
+#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT  ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT  ((uint32_t)0x00000004)
+#define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT  ((uint32_t)0x00000008)
+#define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT  ((uint32_t)0x0000000C)
+#define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT   ((uint32_t)0x00000010)
+#define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT   ((uint32_t)0x00000014)
+#define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT   ((uint32_t)0x00000018)
+#define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT   ((uint32_t)0x0000001C)
+#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT   ((uint32_t)0x00000020)
+#define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT   ((uint32_t)0x00000024)
+#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT   ((uint32_t)0x00000028)
+#define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT   ((uint32_t)0x0000002C)
+#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT   ((uint32_t)0x00000030)
+#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT   ((uint32_t)0x00000034)
+/**
+  * @}
+  */
+  
+/** @defgroup CRYP_Interrupt
+  * @{
+  */
+#define CRYP_IT_INI               ((uint32_t)CRYP_IMSCR_INIM)   /*!< Input FIFO Interrupt */
+#define CRYP_IT_OUTI              ((uint32_t)CRYP_IMSCR_OUTIM)  /*!< Output FIFO Interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Flags 
+  * @{
+  */
+
+#define CRYP_FLAG_BUSY   ((uint32_t)0x00000010)  /*!< The CRYP core is currently 
+                                                     processing a block of data 
+                                                     or a key preparation (for 
+                                                     AES decryption). */
+#define CRYP_FLAG_IFEM   ((uint32_t)0x00000001)  /*!< Input FIFO is empty */
+#define CRYP_FLAG_IFNF   ((uint32_t)0x00000002)  /*!< Input FIFO is not Full */
+#define CRYP_FLAG_OFNE   ((uint32_t)0x00000004)  /*!< Output FIFO is not empty */
+#define CRYP_FLAG_OFFU   ((uint32_t)0x00000008)  /*!< Output FIFO is Full */
+#define CRYP_FLAG_OUTRIS ((uint32_t)0x01000002)  /*!< Output FIFO service raw 
+                                                      interrupt status */
+#define CRYP_FLAG_INRIS  ((uint32_t)0x01000001)  /*!< Input FIFO service raw 
+                                                      interrupt status */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset CRYP handle state
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @retval None
+  */
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
+
+/**
+  * @brief  Enable/Disable the CRYP peripheral.
+  * @param  None
+  * @retval None
+  */
+#define __HAL_CRYP_ENABLE()  (CRYP->CR |=  CRYP_CR_CRYPEN)
+#define __HAL_CRYP_DISABLE() (CRYP->CR &=  ~CRYP_CR_CRYPEN)
+
+/**
+  * @brief  Flush the data FIFO.
+  * @param  None
+  * @retval None
+  */
+#define __HAL_CRYP_FIFO_FLUSH() (CRYP->CR |=  CRYP_CR_FFLUSH)
+
+/**
+  * @brief  Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC,
+  * @param  MODE: The algorithm mode.
+  * @retval None
+  */
+#define __HAL_CRYP_SET_MODE(MODE)  CRYP->CR |= (uint32_t)(MODE)
+
+/** @brief  Check whether the specified CRYP flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data 
+  *                                 or a key preparation (for AES decryption). 
+  *            @arg CRYP_FLAG_IFEM: Input FIFO is empty
+  *            @arg CRYP_FLAG_IFNF: Input FIFO is not full
+  *            @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
+  *            @arg CRYP_FLAG_OFNE: Output FIFO is not empty
+  *            @arg CRYP_FLAG_OFFU: Output FIFO is full
+  *            @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define CRYP_FLAG_MASK  ((uint32_t)0x0000001F)
+#define __HAL_CRYP_GET_FLAG(__FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01)?(((CRYP->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
+                                                 (((CRYP->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
+
+/** @brief  Check whether the specified CRYP interrupt is set or not.
+  * @param  __INTERRUPT__: specifies the interrupt to check.
+  *         This parameter can be one of the following values:
+  *            @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending
+  *            @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_CRYP_GET_IT(__INTERRUPT__) ((CRYP->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief  Enable the CRYP interrupt.
+  * @param  __INTERRUPT__: CRYP Interrupt.
+  * @retval None
+  */
+#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((CRYP->IMSCR) |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the CRYP interrupt.
+  * @param  __INTERRUPT__: CRYP interrupt.
+  * @retval None
+  */
+#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((CRYP->IMSCR) &= ~(__INTERRUPT__))
+
+/* Include CRYP HAL Extension module */
+#include "stm32f4xx_hal_cryp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
+
+/* AES encryption/decryption using polling  ***********************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+
+/* AES encryption/decryption using interrupt  *********************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* AES encryption/decryption using DMA  ***************************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* DES encryption/decryption using polling  ***********************************/
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+
+/* DES encryption/decryption using interrupt  *********************************/
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* DES encryption/decryption using DMA  ***************************************/
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* TDES encryption/decryption using polling  **********************************/
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+
+/* TDES encryption/decryption using interrupt  ********************************/
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* TDES encryption/decryption using DMA  **************************************/
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* Processing functions  ******************************************************/
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+
+/* Peripheral State functions  ************************************************/
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
+
+/* MSP functions  *************************************************************/
+void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+
+/* CallBack functions  ********************************************************/
+void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
+
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CRYP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp_ex.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,3019 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_cryp_ex.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Extended CRYP HAL module driver
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of CRYP extension peripheral:
+  *           + Extended AES processing functions     
+  *  
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The CRYP Extension HAL driver can be used as follows:
+    (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
+        (##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE()
+        (##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT())
+            (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
+            (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
+            (+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
+        (##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA())
+            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+            (+++) Configure and enable two DMA streams one for managing data transfer from
+                memory to peripheral (input stream) and another stream for managing data
+                transfer from peripheral to memory (output stream)
+            (+++) Associate the initilalized DMA handle to the CRYP DMA handle
+                using  __HAL_LINKDMA()
+            (+++) Configure the priority and enable the NVIC for the transfer complete
+                interrupt on the two DMA Streams. The output stream should have higher
+                priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+    (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
+        (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
+        (##) The key size: 128, 192 and 256. This parameter is relevant only for AES
+        (##) The encryption/decryption key. Its size depends on the algorithm
+                used for encryption/decryption
+        (##) The initialization vector (counter). It is not used ECB mode.
+    (#)Three processing (encryption/decryption) functions are available:
+        (##) Polling mode: encryption and decryption APIs are blocking functions
+             i.e. they process the data and wait till the processing is finished
+             e.g. HAL_CRYPEx_AESGCM_Encrypt()
+        (##) Interrupt mode: encryption and decryption APIs are not blocking functions
+                i.e. they process the data under interrupt
+                e.g. HAL_CRYPEx_AESGCM_Encrypt_IT()
+        (##) DMA mode: encryption and decryption APIs are not blocking functions
+                i.e. the data transfer is ensured by DMA
+                e.g. HAL_CRYPEx_AESGCM_Encrypt_DMA()
+    (#)When the processing function is called at first time after HAL_CRYP_Init()
+       the CRYP peripheral is initialized and processes the buffer in input.
+       At second call, the processing function performs an append of the already
+       processed buffer.
+       When a new data block is to be processed, call HAL_CRYP_Init() then the
+       processing function.
+    (#)In AES-GCM and AES-CCM modes are an authenticated encryption algorithms
+       which provide authentication messages.
+       HAL_AES_GCM_Finish() and HAL_AES_CCM_Finish() are used to provide those
+       authentication messages.
+       Call those functions after the processing ones (polling, interrupt or DMA).
+       e.g. in AES-CCM mode call HAL_CRYPEx_AESCCM_Encrypt() to encrypt the plain data
+            then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message
+    (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CRYPEx 
+  * @brief CRYP Extension HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+
+#if defined(STM32F437xx) || defined(STM32F439xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize);
+static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);
+static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout);
+static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout);
+static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma);
+static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma);
+static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma);
+static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CRYPEx_Private_Functions
+  * @{
+  */
+
+/** @defgroup CRYPEx_Group1 Extended AES processing functions 
+ *  @brief   Extended processing functions. 
+ *
+@verbatim   
+  ==============================================================================
+              ##### Extended AES processing functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Encrypt plaintext using AES-128/192/256 using GCM and CCM chaining modes
+      (+) Decrypt cyphertext using AES-128/192/256 using GCM and CCM chaining modes
+      (+) Finish the processing. This function is available only for GCM and CCM
+    [..]  Three processing methods are available:
+      (+) Polling mode
+      (+) Interrupt mode
+      (+) DMA mode
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CCM encryption mode then 
+  *         encrypt pPlainData. The cypher data are available in pCypherData.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  uint32_t headersize = hcryp->Init.HeaderSize;
+  uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
+  uint32_t loopcounter = 0;
+  uint32_t bufferidx = 0;
+  uint8_t blockb0[16] = {0};/* Block B0 */
+  uint8_t ctr[16] = {0}; /* Counter */
+  uint32_t b0addr = (uint32_t)blockb0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP peripheral state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  {
+    /************************ Formatting the header block *********************/
+    if(headersize != 0)
+    {
+      /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
+      if(headersize < 65280)
+      {
+        hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
+        hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
+        headersize += 2;
+      }
+      else
+      {
+        /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
+        hcryp->Init.pScratch[bufferidx++] = 0xFF;
+        hcryp->Init.pScratch[bufferidx++] = 0xFE;
+        hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
+        hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
+        hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
+        hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
+        headersize += 6;
+      }
+      /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
+      for(loopcounter = 0; loopcounter < headersize; loopcounter++)
+      {
+        hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
+      }
+      /* Check if the header size is modulo 16 */
+      if ((headersize % 16) != 0)
+      {
+        /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
+        for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
+        {
+          hcryp->Init.pScratch[loopcounter] = 0;
+        }
+        /* Set the header size to modulo 16 */
+        headersize = ((headersize/16) + 1) * 16;
+      }
+      /* Set the pointer headeraddr to hcryp->Init.pScratch */
+      headeraddr = (uint32_t)hcryp->Init.pScratch;
+    }
+    /*********************** Formatting the block B0 **************************/
+    if(headersize != 0)
+    {
+      blockb0[0] = 0x40;
+    }
+    /* Flags byte */
+    /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
+    blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
+    blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
+ 
+    for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
+    {
+      blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
+    }
+    for ( ; loopcounter < 13; loopcounter++)
+    {
+      blockb0[loopcounter+1] = 0;
+    }
+    
+    blockb0[14] = (Size >> 8);
+    blockb0[15] = (Size & 0xFF);
+    
+    /************************* Formatting the initial counter *****************/
+    /* Byte 0:
+       Bits 7 and 6 are reserved and shall be set to 0
+       Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks
+       are distinct from B0
+       Bits 0, 1, and 2 contain the same encoding of q as in B0
+    */
+    ctr[0] = blockb0[0] & 0x07;
+    /* byte 1 to NonceSize is the IV (Nonce) */
+    for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
+    {
+      ctr[loopcounter] = blockb0[loopcounter];
+    }
+    /* Set the LSB to 1 */
+    ctr[15] |= 0x01;
+    
+    /* Set the key */
+    CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+    
+    /* Set the CRYP peripheral in AES CCM mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
+    
+    /* Set the Initialization Vector */
+    CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, CRYP_KEYSIZE_128B);
+    
+    /* Select init phase */
+    __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+    
+    b0addr = (uint32_t)blockb0;
+    /* Write the blockb0 block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(b0addr);
+    b0addr+=4;
+    CRYP->DR = *(uint32_t*)(b0addr);
+    b0addr+=4;
+    CRYP->DR = *(uint32_t*)(b0addr);
+    b0addr+=4;
+    CRYP->DR = *(uint32_t*)(b0addr);
+    
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE();
+    
+    /* Get timeout */
+    timeout = HAL_GetTick() + Timeout;
+
+    while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+        
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    /***************************** Header phase *******************************/
+    if(headersize != 0)
+    {
+      /* Select header phase */
+      __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+      
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE();
+      
+      for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
+      {
+        /* Get timeout */
+        timeout = HAL_GetTick() + Timeout;
+        while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+        {
+          {
+            /* Check for the Timeout */
+            if(Timeout != HAL_MAX_DELAY)
+            {
+              if(HAL_GetTick() >= timeout)
+              {
+                /* Change state */
+                hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+                
+                /* Process Unlocked */          
+                __HAL_UNLOCK(hcryp);
+                
+                return HAL_TIMEOUT;
+              }
+            }
+          }
+        }
+        /* Write the header block in the IN FIFO */
+        CRYP->DR = *(uint32_t*)(headeraddr);
+        headeraddr+=4;
+        CRYP->DR = *(uint32_t*)(headeraddr);
+        headeraddr+=4;
+        CRYP->DR = *(uint32_t*)(headeraddr);
+        headeraddr+=4;
+        CRYP->DR = *(uint32_t*)(headeraddr);
+        headeraddr+=4;
+      }
+      
+      /* Get timeout */
+      timeout = HAL_GetTick() + Timeout;
+
+      while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+      {
+        /* Check for the Timeout */
+        if(Timeout != HAL_MAX_DELAY)
+        {
+          if(HAL_GetTick() >= timeout)
+          {
+            /* Change state */
+            hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+            
+            /* Process Unlocked */          
+            __HAL_UNLOCK(hcryp);
+            
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    /* Save formatted counter into the scratch buffer pScratch */
+    for(loopcounter = 0; (loopcounter < 16); loopcounter++)
+    {
+      hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
+    }
+    /* Reset bit 0 */
+    hcryp->Init.pScratch[15] &= 0xfe;
+    
+    /* Select payload phase once the header phase is performed */
+    __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+    
+    /* Flush FIFO */
+    __HAL_CRYP_FIFO_FLUSH();
+    
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE();
+    
+    /* Set the phase */
+    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+  }
+  
+  /* Write Plain Data and Get Cypher Data */
+  if(CRYPEx_GCMCCM_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+  
+  /* Change the CRYP peripheral state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES GCM encryption mode then 
+  *         encrypt pPlainData. The cypher data are available in pCypherData.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP peripheral state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  {
+    /* Set the key */
+    CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+    
+    /* Set the CRYP peripheral in AES GCM mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
+    
+    /* Set the Initialization Vector */
+    CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+    
+    /* Flush FIFO */
+    __HAL_CRYP_FIFO_FLUSH();
+    
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE();
+    
+    /* Get timeout */
+    timeout = HAL_GetTick() + Timeout;
+
+    while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    
+    /* Set the header phase */
+    if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+    
+    /* Disable the CRYP peripheral */
+    __HAL_CRYP_DISABLE();
+    
+    /* Select payload phase once the header phase is performed */
+    __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+    
+    /* Flush FIFO */
+    __HAL_CRYP_FIFO_FLUSH();
+    
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE();
+    
+    /* Set the phase */
+    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+  }
+  
+  /* Write Plain Data and Get Cypher Data */
+  if(CRYPEx_GCMCCM_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+  
+  /* Change the CRYP peripheral state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES GCM decryption mode then
+  *         decrypted pCypherData. The cypher data are available in pPlainData.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the cyphertext buffer, must be a multiple of 16
+  * @param  pPlainData: Pointer to the plaintext buffer 
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP peripheral state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  {
+    /* Set the key */
+    CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+    
+    /* Set the CRYP peripheral in AES GCM decryption mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
+    
+    /* Set the Initialization Vector */
+    CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+    
+    /* Flush FIFO */
+    __HAL_CRYP_FIFO_FLUSH();
+    
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE();
+    
+    /* Get the timeout */
+    timeout = HAL_GetTick() + Timeout;
+
+    while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    
+    /* Set the header phase */
+    if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+    /* Disable the CRYP peripheral */
+    __HAL_CRYP_DISABLE();
+    
+    /* Select payload phase once the header phase is performed */
+    __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+    
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE();
+    
+    /* Set the phase */
+    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+  }
+  
+  /* Write Plain Data and Get Cypher Data */
+  if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+  
+  /* Change the CRYP peripheral state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Computes the authentication TAG.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Size: Total length of the plain/cyphertext buffer
+  * @param  AuthTag: Pointer to the authentication buffer
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint16_t Size, uint8_t *AuthTag, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  uint32_t headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */
+  uint32_t inputlength = Size * 8; /* input length in bits */
+  uint32_t tagaddr = (uint32_t)AuthTag;
+  
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP peripheral state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)
+  {
+    /* Change the CRYP phase */
+    hcryp->Phase = HAL_CRYP_PHASE_FINAL;
+    
+    /* Disable CRYP to start the final phase */
+    __HAL_CRYP_DISABLE();
+    
+    /* Select final phase */
+    __HAL_CRYP_SET_PHASE(CRYP_PHASE_FINAL);
+    
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE();
+    
+    /* Write the number of bits in header (64 bits) followed by the number of bits
+       in the payload */
+    if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+    {
+      CRYP->DR = 0;
+      CRYP->DR = __RBIT(headerlength);
+      CRYP->DR = 0;
+      CRYP->DR = __RBIT(inputlength);
+    }
+    else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+    {
+      CRYP->DR = 0;
+      CRYP->DR = __REV(headerlength);
+      CRYP->DR = 0;
+      CRYP->DR = __REV(inputlength);
+    }
+    else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+    {
+      CRYP->DR = 0;
+      CRYP->DR = __REV16(headerlength);
+      CRYP->DR = 0;
+      CRYP->DR = __REV16(inputlength);
+    }
+    else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
+    {
+      CRYP->DR = 0;
+      CRYP->DR = (uint32_t)(headerlength);
+      CRYP->DR = 0;
+      CRYP->DR = (uint32_t)(inputlength);
+    }
+    /* Get timeout */
+    timeout = HAL_GetTick() + Timeout;
+
+    while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+        
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    
+    /* Read the Auth TAG in the IN FIFO */
+    *(uint32_t*)(tagaddr) = CRYP->DOUT;
+    tagaddr+=4;
+    *(uint32_t*)(tagaddr) = CRYP->DOUT;
+    tagaddr+=4;
+    *(uint32_t*)(tagaddr) = CRYP->DOUT;
+    tagaddr+=4;
+    *(uint32_t*)(tagaddr) = CRYP->DOUT;
+  }
+  
+  /* Change the CRYP peripheral state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Computes the authentication TAG for AES CCM mode.
+  * @note   This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt()   
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  AuthTag: Pointer to the authentication buffer
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  uint32_t tagaddr = (uint32_t)AuthTag;
+  uint32_t ctraddr = (uint32_t)hcryp->Init.pScratch;
+  uint32_t temptag[4] = {0}; /* Temporary TAG (MAC) */
+  uint32_t loopcounter;
+  
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP peripheral state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)
+  {
+    /* Change the CRYP phase */
+    hcryp->Phase = HAL_CRYP_PHASE_FINAL;
+    
+    /* Disable CRYP to start the final phase */
+    __HAL_CRYP_DISABLE();
+    
+    /* Select final phase */
+    __HAL_CRYP_SET_PHASE(CRYP_PHASE_FINAL);
+    
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE();
+    
+    /* Write the counter block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)ctraddr;
+    ctraddr+=4;
+    CRYP->DR = *(uint32_t*)ctraddr;
+    ctraddr+=4;
+    CRYP->DR = *(uint32_t*)ctraddr;
+    ctraddr+=4;
+    CRYP->DR = *(uint32_t*)ctraddr;
+    
+    /* Get timeout */
+    timeout = HAL_GetTick() + Timeout;
+
+    while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    
+    /* Read the Auth TAG in the IN FIFO */
+    temptag[0] = CRYP->DOUT;
+    temptag[1] = CRYP->DOUT;
+    temptag[2] = CRYP->DOUT;
+    temptag[3] = CRYP->DOUT;
+  }
+  
+  /* Copy temporary authentication TAG in user TAG buffer */
+  for(loopcounter = 0; loopcounter < hcryp->Init.TagSize ; loopcounter++)
+  {
+    /* Set the authentication TAG buffer */
+    *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter);
+  }
+  
+  /* Change the CRYP peripheral state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CCM decryption mode then
+  *         decrypted pCypherData. The cypher data are available in pPlainData.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  uint32_t headersize = hcryp->Init.HeaderSize;
+  uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
+  uint32_t loopcounter = 0;
+  uint32_t bufferidx = 0;
+  uint8_t blockb0[16] = {0};/* Block B0 */
+  uint8_t ctr[16] = {0}; /* Counter */
+  uint32_t b0addr = (uint32_t)blockb0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Change the CRYP peripheral state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  {
+    /************************ Formatting the header block *********************/
+    if(headersize != 0)
+    {
+      /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
+      if(headersize < 65280)
+      {
+        hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
+        hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
+        headersize += 2;
+      }
+      else
+      {
+        /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
+        hcryp->Init.pScratch[bufferidx++] = 0xFF;
+        hcryp->Init.pScratch[bufferidx++] = 0xFE;
+        hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
+        hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
+        hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
+        hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
+        headersize += 6;
+      }
+      /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
+      for(loopcounter = 0; loopcounter < headersize; loopcounter++)
+      {
+        hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
+      }
+      /* Check if the header size is modulo 16 */
+      if ((headersize % 16) != 0)
+      {
+        /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
+        for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
+        {
+          hcryp->Init.pScratch[loopcounter] = 0;
+        }
+        /* Set the header size to modulo 16 */
+        headersize = ((headersize/16) + 1) * 16;
+      }
+      /* Set the pointer headeraddr to hcryp->Init.pScratch */
+      headeraddr = (uint32_t)hcryp->Init.pScratch;
+    }
+    /*********************** Formatting the block B0 **************************/
+    if(headersize != 0)
+    {
+      blockb0[0] = 0x40;
+    }
+    /* Flags byte */
+    /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
+    blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
+    blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
+    
+    for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
+    {
+      blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
+    }
+    for ( ; loopcounter < 13; loopcounter++)
+    {
+      blockb0[loopcounter+1] = 0;
+    }
+    
+    blockb0[14] = (Size >> 8);
+    blockb0[15] = (Size & 0xFF);
+    
+    /************************* Formatting the initial counter *****************/
+    /* Byte 0:
+       Bits 7 and 6 are reserved and shall be set to 0
+       Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter 
+       blocks are distinct from B0
+       Bits 0, 1, and 2 contain the same encoding of q as in B0
+    */
+    ctr[0] = blockb0[0] & 0x07;
+    /* byte 1 to NonceSize is the IV (Nonce) */
+    for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
+    {
+      ctr[loopcounter] = blockb0[loopcounter];
+    }
+    /* Set the LSB to 1 */
+    ctr[15] |= 0x01;
+    
+    /* Set the key */
+    CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+    
+    /* Set the CRYP peripheral in AES CCM mode */
+    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
+    
+    /* Set the Initialization Vector */
+    CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, CRYP_KEYSIZE_128B);
+    
+    /* Select init phase */
+    __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+    
+    b0addr = (uint32_t)blockb0;
+    /* Write the blockb0 block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(b0addr);
+    b0addr+=4;
+    CRYP->DR = *(uint32_t*)(b0addr);
+    b0addr+=4;
+    CRYP->DR = *(uint32_t*)(b0addr);
+    b0addr+=4;
+    CRYP->DR = *(uint32_t*)(b0addr);
+    
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE();
+    
+    /* Get timeout */
+    timeout = HAL_GetTick() + Timeout;
+ 
+    while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+        
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    /***************************** Header phase *******************************/
+    if(headersize != 0)
+    {
+      /* Select header phase */
+      __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+      
+      /* Enable Crypto processor */
+      __HAL_CRYP_ENABLE();
+      
+      for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
+      {
+        /* Get timeout */
+        timeout = HAL_GetTick() + Timeout;
+
+        while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+        {
+          /* Check for the Timeout */
+          if(Timeout != HAL_MAX_DELAY)
+          {
+            if(HAL_GetTick() >= timeout)
+            {
+              /* Change state */
+              hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+              
+              /* Process Unlocked */          
+              __HAL_UNLOCK(hcryp);
+              
+              return HAL_TIMEOUT;
+            }
+          }
+        }
+        /* Write the header block in the IN FIFO */
+        CRYP->DR = *(uint32_t*)(headeraddr);
+        headeraddr+=4;
+        CRYP->DR = *(uint32_t*)(headeraddr);
+        headeraddr+=4;
+        CRYP->DR = *(uint32_t*)(headeraddr);
+        headeraddr+=4;
+        CRYP->DR = *(uint32_t*)(headeraddr);
+        headeraddr+=4;
+      }
+      
+      /* Get timeout */
+      timeout = HAL_GetTick() + Timeout;
+
+      while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+      {
+      /* Check for the Timeout */
+        if(Timeout != HAL_MAX_DELAY)
+        {
+          if(HAL_GetTick() >= timeout)
+          {
+            /* Change state */
+            hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+            
+            /* Process Unlocked */          
+            __HAL_UNLOCK(hcryp);
+            
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    /* Save formatted counter into the scratch buffer pScratch */
+    for(loopcounter = 0; (loopcounter < 16); loopcounter++)
+    {
+      hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
+    }
+    /* Reset bit 0 */
+    hcryp->Init.pScratch[15] &= 0xfe;
+    /* Select payload phase once the header phase is performed */
+    __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+    
+    /* Flush FIFO */
+    __HAL_CRYP_FIFO_FLUSH();
+    
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE();
+    
+    /* Set the phase */
+    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+  }
+  
+  /* Write Plain Data and Get Cypher Data */
+  if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+  
+  /* Change the CRYP peripheral state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES GCM encryption mode using IT.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t timeout = 0;   
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    /* Get the buffer addresses and sizes */    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pPlainData;
+    hcryp->pCrypOutBuffPtr = pCypherData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP peripheral state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+      
+      /* Set the CRYP peripheral in AES GCM mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+      
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+      /* Enable CRYP to start the init phase */
+      __HAL_CRYP_ENABLE();
+      
+      /* Get timeout */
+      timeout = HAL_GetTick() + 1;
+
+      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+      {
+        /* Check for the Timeout */
+        
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+          
+          return HAL_TIMEOUT;
+          
+        }
+      }
+      
+      /* Set the header phase */
+      if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      /* Disable the CRYP peripheral */
+      __HAL_CRYP_DISABLE();
+      
+      /* Select payload phase once the header phase is performed */
+      __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+      
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    if(Size != 0)
+    {
+      /* Enable Interrupts */
+      __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE();
+    }
+    else
+    {
+      /* Process Locked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP state and phase */
+      hcryp->State = HAL_CRYP_STATE_READY;
+    }
+    /* Return function status */
+    return HAL_OK;
+  }
+  else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  {
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->pCrypInBuffPtr += 16;
+    hcryp->CrypInCount -= 16;
+    if(hcryp->CrypInCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      /* Call the Input data transfer complete callback */
+      HAL_CRYP_InCpltCallback(hcryp);
+    }
+  }
+  else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  {
+    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    hcryp->pCrypOutBuffPtr += 16;
+    hcryp->CrypOutCount -= 16;
+    if(hcryp->CrypOutCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP peripheral state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Call Input transfer complete callback */
+      HAL_CRYP_OutCpltCallback(hcryp);
+    }
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t timeout = 0;   
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  uint32_t headersize = hcryp->Init.HeaderSize;
+  uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
+  uint32_t loopcounter = 0;
+  uint32_t bufferidx = 0;
+  uint8_t blockb0[16] = {0};/* Block B0 */
+  uint8_t ctr[16] = {0}; /* Counter */
+  uint32_t b0addr = (uint32_t)blockb0;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pPlainData;
+    hcryp->pCrypOutBuffPtr = pCypherData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP peripheral state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {    
+      /************************ Formatting the header block *******************/
+      if(headersize != 0)
+      {
+        /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
+        if(headersize < 65280)
+        {
+          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
+          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
+          headersize += 2;
+        }
+        else
+        {
+          /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
+          hcryp->Init.pScratch[bufferidx++] = 0xFF;
+          hcryp->Init.pScratch[bufferidx++] = 0xFE;
+          hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
+          hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
+          hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
+          hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
+          headersize += 6;
+        }
+        /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
+        for(loopcounter = 0; loopcounter < headersize; loopcounter++)
+        {
+          hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
+        }
+        /* Check if the header size is modulo 16 */
+        if ((headersize % 16) != 0)
+        {
+          /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
+          for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
+          {
+            hcryp->Init.pScratch[loopcounter] = 0;
+          }
+          /* Set the header size to modulo 16 */
+          headersize = ((headersize/16) + 1) * 16;
+        }
+        /* Set the pointer headeraddr to hcryp->Init.pScratch */
+        headeraddr = (uint32_t)hcryp->Init.pScratch;
+      }
+      /*********************** Formatting the block B0 ************************/
+      if(headersize != 0)
+      {
+        blockb0[0] = 0x40;
+      }
+      /* Flags byte */
+      /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
+      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
+      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
+      
+      for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
+      {
+        blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
+      }
+      for ( ; loopcounter < 13; loopcounter++)
+      {
+        blockb0[loopcounter+1] = 0;
+      }
+      
+      blockb0[14] = (Size >> 8);
+      blockb0[15] = (Size & 0xFF);
+      
+      /************************* Formatting the initial counter ***************/
+      /* Byte 0:
+         Bits 7 and 6 are reserved and shall be set to 0
+         Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter 
+         blocks are distinct from B0
+         Bits 0, 1, and 2 contain the same encoding of q as in B0
+      */
+      ctr[0] = blockb0[0] & 0x07;
+      /* byte 1 to NonceSize is the IV (Nonce) */
+      for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
+      {
+        ctr[loopcounter] = blockb0[loopcounter];
+      }
+      /* Set the LSB to 1 */
+      ctr[15] |= 0x01;
+      
+      /* Set the key */
+      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+      
+      /* Set the CRYP peripheral in AES CCM mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, hcryp->Init.KeySize);
+      
+      /* Select init phase */
+      __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+      
+      b0addr = (uint32_t)blockb0;
+      /* Write the blockb0 block in the IN FIFO */
+      CRYP->DR = *(uint32_t*)(b0addr);
+      b0addr+=4;
+      CRYP->DR = *(uint32_t*)(b0addr);
+      b0addr+=4;
+      CRYP->DR = *(uint32_t*)(b0addr);
+      b0addr+=4;
+      CRYP->DR = *(uint32_t*)(b0addr);
+      
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE();
+      
+      /* Get timeout */
+      timeout = HAL_GetTick() + 1;
+
+      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+      {
+        /* Check for the Timeout */
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+      /***************************** Header phase *****************************/
+      if(headersize != 0)
+      {
+        /* Select header phase */
+        __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+        
+        /* Enable Crypto processor */
+        __HAL_CRYP_ENABLE();
+        
+        for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
+        {
+          /* Get timeout */
+          timeout = HAL_GetTick() + 1;
+
+          while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+          {
+            /* Check for the Timeout */
+            if(HAL_GetTick() >= timeout)
+            {
+              /* Change state */
+              hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+              
+              /* Process Unlocked */          
+              __HAL_UNLOCK(hcryp);
+              
+              return HAL_TIMEOUT;
+            }
+          }
+          /* Write the header block in the IN FIFO */
+          CRYP->DR = *(uint32_t*)(headeraddr);
+          headeraddr+=4;
+          CRYP->DR = *(uint32_t*)(headeraddr);
+          headeraddr+=4;
+          CRYP->DR = *(uint32_t*)(headeraddr);
+          headeraddr+=4;
+          CRYP->DR = *(uint32_t*)(headeraddr);
+          headeraddr+=4;
+        }
+        
+        /* Get timeout */
+        timeout = HAL_GetTick() + 1;
+
+        while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+        {
+          /* Check for the Timeout */
+          if(HAL_GetTick() >= timeout)
+          {
+            /* Change state */
+            hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+            
+            /* Process Unlocked */          
+            __HAL_UNLOCK(hcryp);
+            
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      /* Save formatted counter into the scratch buffer pScratch */
+      for(loopcounter = 0; (loopcounter < 16); loopcounter++)
+      {
+        hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
+      }
+      /* Reset bit 0 */
+      hcryp->Init.pScratch[15] &= 0xfe;
+      
+      /* Select payload phase once the header phase is performed */
+      __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+      
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    if(Size != 0)
+    {
+      /* Enable Interrupts */
+      __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE();
+    }
+    else
+    {
+      /* Change the CRYP state and phase */
+      hcryp->State = HAL_CRYP_STATE_READY;
+    }
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  {
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->pCrypInBuffPtr += 16;
+    hcryp->CrypInCount -= 16;
+    if(hcryp->CrypInCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      /* Call Input transfer complete callback */
+      HAL_CRYP_InCpltCallback(hcryp);
+    }
+  }
+  else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  {
+    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    hcryp->pCrypOutBuffPtr += 16;
+    hcryp->CrypOutCount -= 16;
+    if(hcryp->CrypOutCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP peripheral state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Call Input transfer complete callback */
+      HAL_CRYP_OutCpltCallback(hcryp);
+    }
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES GCM decryption mode using IT.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Size: Length of the cyphertext buffer, must be a multiple of 16
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t timeout = 0;   
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    /* Get the buffer addresses and sizes */    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pCypherData;
+    hcryp->pCrypOutBuffPtr = pPlainData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP peripheral state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+      
+      /* Set the CRYP peripheral in AES GCM decryption mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+      
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+      /* Enable CRYP to start the init phase */
+      __HAL_CRYP_ENABLE();
+      
+      /* Get timeout */
+      timeout = HAL_GetTick() + 1;
+      
+      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+      {
+        /* Check for the Timeout */
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+      
+      /* Set the header phase */
+      if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      /* Disable the CRYP peripheral */
+      __HAL_CRYP_DISABLE();
+      
+      /* Select payload phase once the header phase is performed */
+      __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    if(Size != 0)
+    {
+      /* Enable Interrupts */
+      __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE();
+    }
+    else
+    {
+      /* Process Locked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP state and phase */
+      hcryp->State = HAL_CRYP_STATE_READY;
+    }
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  {
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->pCrypInBuffPtr += 16;
+    hcryp->CrypInCount -= 16;
+    if(hcryp->CrypInCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      /* Call the Input data transfer complete callback */
+      HAL_CRYP_InCpltCallback(hcryp);
+    }
+  }
+  else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  {
+    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    hcryp->pCrypOutBuffPtr += 16;
+    hcryp->CrypOutCount -= 16;
+    if(hcryp->CrypOutCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP peripheral state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Call Input transfer complete callback */
+      HAL_CRYP_OutCpltCallback(hcryp);
+    }
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CCM decryption mode using interrupt
+  *         then decrypted pCypherData. The cypher data are available in pPlainData.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer 
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
+  * @param  pPlainData: Pointer to the plaintext buffer  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  uint32_t timeout = 0;
+  uint32_t headersize = hcryp->Init.HeaderSize;
+  uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
+  uint32_t loopcounter = 0;
+  uint32_t bufferidx = 0;
+  uint8_t blockb0[16] = {0};/* Block B0 */
+  uint8_t ctr[16] = {0}; /* Counter */
+  uint32_t b0addr = (uint32_t)blockb0;
+  
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pCypherData;
+    hcryp->pCrypOutBuffPtr = pPlainData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP peripheral state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /************************ Formatting the header block *******************/
+      if(headersize != 0)
+      {
+        /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
+        if(headersize < 65280)
+        {
+          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
+          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
+          headersize += 2;
+        }
+        else
+        {
+          /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
+          hcryp->Init.pScratch[bufferidx++] = 0xFF;
+          hcryp->Init.pScratch[bufferidx++] = 0xFE;
+          hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
+          hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
+          hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
+          hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
+          headersize += 6;
+        }
+        /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
+        for(loopcounter = 0; loopcounter < headersize; loopcounter++)
+        {
+          hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
+        }
+        /* Check if the header size is modulo 16 */
+        if ((headersize % 16) != 0)
+        {
+          /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
+          for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
+          {
+            hcryp->Init.pScratch[loopcounter] = 0;
+          }
+          /* Set the header size to modulo 16 */
+          headersize = ((headersize/16) + 1) * 16;
+        }
+        /* Set the pointer headeraddr to hcryp->Init.pScratch */
+        headeraddr = (uint32_t)hcryp->Init.pScratch;
+      }
+      /*********************** Formatting the block B0 ************************/
+      if(headersize != 0)
+      {
+        blockb0[0] = 0x40;
+      }
+      /* Flags byte */
+      /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
+      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
+      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
+      
+      for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
+      {
+        blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
+      }
+      for ( ; loopcounter < 13; loopcounter++)
+      {
+        blockb0[loopcounter+1] = 0;
+      }
+      
+      blockb0[14] = (Size >> 8);
+      blockb0[15] = (Size & 0xFF);
+      
+      /************************* Formatting the initial counter ***************/
+      /* Byte 0:
+         Bits 7 and 6 are reserved and shall be set to 0
+         Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter 
+         blocks are distinct from B0
+         Bits 0, 1, and 2 contain the same encoding of q as in B0
+      */
+      ctr[0] = blockb0[0] & 0x07;
+      /* byte 1 to NonceSize is the IV (Nonce) */
+      for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
+      {
+        ctr[loopcounter] = blockb0[loopcounter];
+      }
+      /* Set the LSB to 1 */
+      ctr[15] |= 0x01;
+      
+      /* Set the key */
+      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+      
+      /* Set the CRYP peripheral in AES CCM mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, hcryp->Init.KeySize);
+      
+      /* Select init phase */
+      __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+      
+      b0addr = (uint32_t)blockb0;
+      /* Write the blockb0 block in the IN FIFO */
+      CRYP->DR = *(uint32_t*)(b0addr);
+      b0addr+=4;
+      CRYP->DR = *(uint32_t*)(b0addr);
+      b0addr+=4;
+      CRYP->DR = *(uint32_t*)(b0addr);
+      b0addr+=4;
+      CRYP->DR = *(uint32_t*)(b0addr);
+      
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE();
+      
+      /* Get timeout */
+      timeout = HAL_GetTick() + 1;
+
+      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+      {
+        /* Check for the Timeout */
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+      /***************************** Header phase *****************************/
+      if(headersize != 0)
+      {
+        /* Select header phase */
+        __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+        
+        /* Enable Crypto processor */
+        __HAL_CRYP_ENABLE();
+        
+        for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
+        {
+          /* Get timeout */
+          timeout = HAL_GetTick() + 1;
+
+          while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+          {
+            /* Check for the Timeout */
+            if(HAL_GetTick() >= timeout)
+            {
+              /* Change state */
+              hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+              
+              /* Process Unlocked */          
+              __HAL_UNLOCK(hcryp);
+              
+              return HAL_TIMEOUT;
+            }
+          }
+          /* Write the header block in the IN FIFO */
+          CRYP->DR = *(uint32_t*)(headeraddr);
+          headeraddr+=4;
+          CRYP->DR = *(uint32_t*)(headeraddr);
+          headeraddr+=4;
+          CRYP->DR = *(uint32_t*)(headeraddr);
+          headeraddr+=4;
+          CRYP->DR = *(uint32_t*)(headeraddr);
+          headeraddr+=4;
+        }
+        
+        /* Get timeout */
+        timeout = HAL_GetTick() + 1;
+
+        while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+        {
+          /* Check for the Timeout */
+          if(HAL_GetTick() >= timeout)
+          {
+            /* Change state */
+            hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+            
+            /* Process Unlocked */          
+            __HAL_UNLOCK(hcryp);
+            
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      /* Save formatted counter into the scratch buffer pScratch */
+      for(loopcounter = 0; (loopcounter < 16); loopcounter++)
+      {
+        hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
+      }
+      /* Reset bit 0 */
+      hcryp->Init.pScratch[15] &= 0xfe;
+      /* Select payload phase once the header phase is performed */
+      __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+      
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(CRYP_IT_INI | CRYP_IT_OUTI);
+    
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE();
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else if (__HAL_CRYP_GET_IT(CRYP_IT_INI))
+  {
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    hcryp->pCrypInBuffPtr += 16;
+    hcryp->CrypInCount -= 16;
+    if(hcryp->CrypInCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_INI);
+      /* Call the Input data transfer complete callback */
+      HAL_CRYP_InCpltCallback(hcryp);
+    }
+  }
+  else if (__HAL_CRYP_GET_IT(CRYP_IT_OUTI))
+  {
+    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    hcryp->pCrypOutBuffPtr += 16;
+    hcryp->CrypOutCount -= 16;
+    if(hcryp->CrypOutCount == 0)
+    {
+      __HAL_CRYP_DISABLE_IT(CRYP_IT_OUTI);
+      /* Process Unlocked */
+      __HAL_UNLOCK(hcryp);
+      /* Change the CRYP peripheral state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      /* Call Input transfer complete callback */
+      HAL_CRYP_OutCpltCallback(hcryp);
+    }
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES GCM encryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t timeout = 0;
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pPlainData;
+    outputaddr = (uint32_t)pCypherData;
+    
+    /* Change the CRYP peripheral state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+      
+      /* Set the CRYP peripheral in AES GCM mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+      
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+      /* Enable CRYP to start the init phase */
+      __HAL_CRYP_ENABLE();
+      
+      /* Get timeout */
+      timeout = HAL_GetTick() + 1;
+
+      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+      {
+        /* Check for the Timeout */
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+      /* Set the header phase */
+      if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      /* Disable the CRYP peripheral */
+      __HAL_CRYP_DISABLE();
+      
+      /* Select payload phase once the header phase is performed */
+      __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+      
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Unlock process */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
+  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t timeout = 0;   
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  uint32_t headersize;
+  uint32_t headeraddr;
+  uint32_t loopcounter = 0;
+  uint32_t bufferidx = 0;
+  uint8_t blockb0[16] = {0};/* Block B0 */
+  uint8_t ctr[16] = {0}; /* Counter */
+  uint32_t b0addr = (uint32_t)blockb0;
+  
+  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pPlainData;
+    outputaddr = (uint32_t)pCypherData;
+    
+    headersize = hcryp->Init.HeaderSize;
+    headeraddr = (uint32_t)hcryp->Init.Header;
+    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pPlainData;
+    hcryp->pCrypOutBuffPtr = pCypherData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP peripheral state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /************************ Formatting the header block *******************/
+      if(headersize != 0)
+      {
+        /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
+        if(headersize < 65280)
+        {
+          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
+          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
+          headersize += 2;
+        }
+        else
+        {
+          /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
+          hcryp->Init.pScratch[bufferidx++] = 0xFF;
+          hcryp->Init.pScratch[bufferidx++] = 0xFE;
+          hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
+          hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
+          hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
+          hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
+          headersize += 6;
+        }
+        /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
+        for(loopcounter = 0; loopcounter < headersize; loopcounter++)
+        {
+          hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
+        }
+        /* Check if the header size is modulo 16 */
+        if ((headersize % 16) != 0)
+        {
+          /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
+          for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
+          {
+            hcryp->Init.pScratch[loopcounter] = 0;
+          }
+          /* Set the header size to modulo 16 */
+          headersize = ((headersize/16) + 1) * 16;
+        }
+        /* Set the pointer headeraddr to hcryp->Init.pScratch */
+        headeraddr = (uint32_t)hcryp->Init.pScratch;
+      }
+      /*********************** Formatting the block B0 ************************/
+      if(headersize != 0)
+      {
+        blockb0[0] = 0x40;
+      }
+      /* Flags byte */
+      /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
+      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
+      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
+      
+      for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
+      {
+        blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
+      }
+      for ( ; loopcounter < 13; loopcounter++)
+      {
+        blockb0[loopcounter+1] = 0;
+      }
+      
+      blockb0[14] = (Size >> 8);
+      blockb0[15] = (Size & 0xFF);
+      
+      /************************* Formatting the initial counter ***************/
+      /* Byte 0:
+         Bits 7 and 6 are reserved and shall be set to 0
+         Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter 
+         blocks are distinct from B0
+         Bits 0, 1, and 2 contain the same encoding of q as in B0
+      */
+      ctr[0] = blockb0[0] & 0x07;
+      /* byte 1 to NonceSize is the IV (Nonce) */
+      for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
+      {
+        ctr[loopcounter] = blockb0[loopcounter];
+      }
+      /* Set the LSB to 1 */
+      ctr[15] |= 0x01;
+      
+      /* Set the key */
+      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+      
+      /* Set the CRYP peripheral in AES CCM mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, CRYP_KEYSIZE_128B);
+      
+      /* Select init phase */
+      __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+      
+      b0addr = (uint32_t)blockb0;
+      /* Write the blockb0 block in the IN FIFO */
+      CRYP->DR = *(uint32_t*)(b0addr);
+      b0addr+=4;
+      CRYP->DR = *(uint32_t*)(b0addr);
+      b0addr+=4;
+      CRYP->DR = *(uint32_t*)(b0addr);
+      b0addr+=4;
+      CRYP->DR = *(uint32_t*)(b0addr);
+      
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE();
+      
+      /* Get timeout */
+      timeout = HAL_GetTick() + 1;
+ 
+      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+      {
+        /* Check for the Timeout */
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+      /***************************** Header phase *****************************/
+      if(headersize != 0)
+      {
+        /* Select header phase */
+        __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+        
+        /* Enable Crypto processor */
+        __HAL_CRYP_ENABLE();
+        
+        for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
+        {
+          /* Get timeout */
+          timeout = HAL_GetTick() + 1;
+          
+          while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+          {
+            /* Check for the Timeout */
+            if(HAL_GetTick() >= timeout)
+            {
+              /* Change state */
+              hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+              
+              /* Process Unlocked */          
+              __HAL_UNLOCK(hcryp);
+              
+              return HAL_TIMEOUT;
+            }
+          }
+          /* Write the header block in the IN FIFO */
+          CRYP->DR = *(uint32_t*)(headeraddr);
+          headeraddr+=4;
+          CRYP->DR = *(uint32_t*)(headeraddr);
+          headeraddr+=4;
+          CRYP->DR = *(uint32_t*)(headeraddr);
+          headeraddr+=4;
+          CRYP->DR = *(uint32_t*)(headeraddr);
+          headeraddr+=4;
+        }
+        
+        /* Get timeout */
+        timeout = HAL_GetTick() + 1;
+
+        while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+        {
+          /* Check for the Timeout */
+          if(HAL_GetTick() >= timeout)
+          {
+            /* Change state */
+            hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+            
+            /* Process Unlocked */          
+            __HAL_UNLOCK(hcryp);
+            
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      /* Save formatted counter into the scratch buffer pScratch */
+      for(loopcounter = 0; (loopcounter < 16); loopcounter++)
+      {
+        hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
+      }
+      /* Reset bit 0 */
+      hcryp->Init.pScratch[15] &= 0xfe;
+      
+      /* Select payload phase once the header phase is performed */
+      __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+      
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Unlock process */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES GCM decryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer.
+  * @param  Size: Length of the cyphertext buffer, must be a multiple of 16
+  * @param  pPlainData: Pointer to the plaintext buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t timeout = 0;   
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  
+  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pCypherData;
+    outputaddr = (uint32_t)pPlainData;
+    
+    /* Change the CRYP peripheral state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+      
+      /* Set the CRYP peripheral in AES GCM decryption mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+      
+      /* Enable CRYP to start the init phase */
+      __HAL_CRYP_ENABLE();
+      
+      /* Get timeout */
+      timeout = HAL_GetTick() + 1;
+
+      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+      {
+        /* Check for the Timeout */
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+      
+      /* Set the header phase */
+      if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      /* Disable the CRYP peripheral */
+      __HAL_CRYP_DISABLE();
+      
+      /* Select payload phase once the header phase is performed */
+      __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Unlock process */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CCM decryption mode using DMA
+  *         then decrypted pCypherData. The cypher data are available in pPlainData.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer  
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
+  * @param  pPlainData: Pointer to the plaintext buffer  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t timeout = 0;   
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  uint32_t headersize;
+  uint32_t headeraddr;
+  uint32_t loopcounter = 0;
+  uint32_t bufferidx = 0;
+  uint8_t blockb0[16] = {0};/* Block B0 */
+  uint8_t ctr[16] = {0}; /* Counter */
+  uint32_t b0addr = (uint32_t)blockb0;
+  
+  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pCypherData;
+    outputaddr = (uint32_t)pPlainData;
+    
+    headersize = hcryp->Init.HeaderSize;
+    headeraddr = (uint32_t)hcryp->Init.Header;
+    
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pCypherData;
+    hcryp->pCrypOutBuffPtr = pPlainData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP peripheral state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /************************ Formatting the header block *******************/
+      if(headersize != 0)
+      {
+        /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
+        if(headersize < 65280)
+        {
+          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
+          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
+          headersize += 2;
+        }
+        else
+        {
+          /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
+          hcryp->Init.pScratch[bufferidx++] = 0xFF;
+          hcryp->Init.pScratch[bufferidx++] = 0xFE;
+          hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
+          hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
+          hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
+          hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
+          headersize += 6;
+        }
+        /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
+        for(loopcounter = 0; loopcounter < headersize; loopcounter++)
+        {
+          hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
+        }
+        /* Check if the header size is modulo 16 */
+        if ((headersize % 16) != 0)
+        {
+          /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
+          for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)
+          {
+            hcryp->Init.pScratch[loopcounter] = 0;
+          }
+          /* Set the header size to modulo 16 */
+          headersize = ((headersize/16) + 1) * 16;
+        }
+        /* Set the pointer headeraddr to hcryp->Init.pScratch */
+        headeraddr = (uint32_t)hcryp->Init.pScratch;
+      }
+      /*********************** Formatting the block B0 ************************/
+      if(headersize != 0)
+      {
+        blockb0[0] = 0x40;
+      }
+      /* Flags byte */
+      /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */
+      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);
+      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
+      
+      for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)
+      {
+        blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];
+      }
+      for ( ; loopcounter < 13; loopcounter++)
+      {
+        blockb0[loopcounter+1] = 0;
+      }
+      
+      blockb0[14] = (Size >> 8);
+      blockb0[15] = (Size & 0xFF);
+      
+      /************************* Formatting the initial counter ***************/
+      /* Byte 0:
+         Bits 7 and 6 are reserved and shall be set to 0
+         Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter 
+         blocks are distinct from B0
+         Bits 0, 1, and 2 contain the same encoding of q as in B0
+      */
+      ctr[0] = blockb0[0] & 0x07;
+      /* byte 1 to NonceSize is the IV (Nonce) */
+      for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)
+      {
+        ctr[loopcounter] = blockb0[loopcounter];
+      }
+      /* Set the LSB to 1 */
+      ctr[15] |= 0x01;
+      
+      /* Set the key */
+      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+      
+      /* Set the CRYP peripheral in AES CCM mode */
+      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYPEx_GCMCCM_SetInitVector(hcryp, ctr, CRYP_KEYSIZE_128B);
+      
+      /* Select init phase */
+      __HAL_CRYP_SET_PHASE(CRYP_PHASE_INIT);
+      
+      b0addr = (uint32_t)blockb0;
+      /* Write the blockb0 block in the IN FIFO */
+      CRYP->DR = *(uint32_t*)(b0addr);
+      b0addr+=4;
+      CRYP->DR = *(uint32_t*)(b0addr);
+      b0addr+=4;
+      CRYP->DR = *(uint32_t*)(b0addr);
+      b0addr+=4;
+      CRYP->DR = *(uint32_t*)(b0addr);
+      
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE();
+      
+      /* Get timeout */
+      timeout = HAL_GetTick() + 1;
+ 
+      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+      {
+        /* Check for the Timeout */
+        
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+          
+          return HAL_TIMEOUT;
+          
+        }
+      }
+      /***************************** Header phase *****************************/
+      if(headersize != 0)
+      {
+        /* Select header phase */
+        __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+        
+        /* Enable Crypto processor */
+        __HAL_CRYP_ENABLE();
+        
+        for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)
+        {
+          /* Get timeout */
+          timeout = HAL_GetTick() + 1;
+ 
+          while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+          {
+            /* Check for the Timeout */
+            if(HAL_GetTick() >= timeout)
+            {
+              /* Change state */
+              hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+              
+              /* Process Unlocked */          
+              __HAL_UNLOCK(hcryp);
+              
+              return HAL_TIMEOUT;
+            }
+          }
+          /* Write the header block in the IN FIFO */
+          CRYP->DR = *(uint32_t*)(headeraddr);
+          headeraddr+=4;
+          CRYP->DR = *(uint32_t*)(headeraddr);
+          headeraddr+=4;
+          CRYP->DR = *(uint32_t*)(headeraddr);
+          headeraddr+=4;
+          CRYP->DR = *(uint32_t*)(headeraddr);
+          headeraddr+=4;
+        }
+        
+/* Get timeout */
+        timeout = HAL_GetTick() + 1;
+
+        while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+        {
+          /* Check for the Timeout */
+          if(HAL_GetTick() >= timeout)
+          {
+            /* Change state */
+            hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+            
+            /* Process Unlocked */          
+            __HAL_UNLOCK(hcryp);
+            
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      /* Save formatted counter into the scratch buffer pScratch */
+      for(loopcounter = 0; (loopcounter < 16); loopcounter++)
+      {
+        hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
+      }
+      /* Reset bit 0 */
+      hcryp->Init.pScratch[15] &= 0xfe;
+      /* Select payload phase once the header phase is performed */
+      __HAL_CRYP_SET_PHASE(CRYP_PHASE_PAYLOAD);
+      
+      /* Flush FIFO */
+      __HAL_CRYP_FIFO_FLUSH();
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Unlock process */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  This function handles CRYP interrupt request.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp)
+{
+  switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
+  {    
+  case CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT:
+    HAL_CRYPEx_AESGCM_Encrypt_IT(hcryp, NULL, 0, NULL);
+    break;
+    
+  case CRYP_CR_ALGOMODE_AES_GCM_DECRYPT:
+    HAL_CRYPEx_AESGCM_Decrypt_IT(hcryp, NULL, 0, NULL);
+    break;
+    
+  case CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT:
+    HAL_CRYPEx_AESCCM_Encrypt_IT(hcryp, NULL, 0, NULL);
+    break;
+    
+  case CRYP_CR_ALGOMODE_AES_CCM_DECRYPT:
+    HAL_CRYPEx_AESCCM_Decrypt_IT(hcryp, NULL, 0, NULL);
+    break;
+    
+  default:
+    break;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  DMA CRYP Input Data process complete callback. 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma)  
+{
+  CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  /* Disable the DMA transfer for input Fifo request by resetting the DIEN bit
+     in the DMACR register */
+  CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
+  
+  /* Call input data transfer complete callback */
+  HAL_CRYP_InCpltCallback(hcryp);
+}
+
+/**
+  * @brief  DMA CRYP Output Data process complete callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma)
+{
+  CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  /* Disable the DMA transfer for output Fifo request by resetting the DOEN bit
+     in the DMACR register */
+  CRYP->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
+  
+  /* Enable the CRYP peripheral */
+  __HAL_CRYP_DISABLE();
+  
+  /* Change the CRYP peripheral state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Call output data transfer complete callback */
+  HAL_CRYP_OutCpltCallback(hcryp);
+}
+
+/**
+  * @brief  DMA CRYP communication error callback. 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  hcryp->State= HAL_CRYP_STATE_READY;
+  HAL_CRYP_ErrorCallback(hcryp);
+}
+
+/**
+  * @brief  Writes the Key in Key registers. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Key: Pointer to Key buffer
+  * @param  KeySize: Size of Key
+  * @retval None
+  */
+static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
+{
+  uint32_t keyaddr = (uint32_t)Key;
+  
+  switch(KeySize)
+  {
+  case CRYP_KEYSIZE_256B:
+    /* Key Initialisation */
+    CRYP->K0LR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K0RR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
+    break;
+  case CRYP_KEYSIZE_192B:
+    CRYP->K1LR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K1RR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
+    break;
+  case CRYP_KEYSIZE_128B:       
+    CRYP->K2LR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K2RR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K3LR = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    CRYP->K3RR = __REV(*(uint32_t*)(keyaddr));
+    break;
+  default:
+    break;
+  }
+}
+
+/**
+  * @brief  Writes the InitVector/InitCounter in IV registers.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  InitVector: Pointer to InitVector/InitCounter buffer
+  * @param  IVSize: Size of the InitVector/InitCounter
+  * @retval None
+  */
+static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)
+{
+  uint32_t ivaddr = (uint32_t)InitVector;
+  
+  switch(IVSize)
+  {
+  case CRYP_KEYSIZE_128B:
+    CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
+    ivaddr+=4;
+    CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
+    ivaddr+=4;
+    CRYP->IV1LR = __REV(*(uint32_t*)(ivaddr));
+    ivaddr+=4;
+    CRYP->IV1RR = __REV(*(uint32_t*)(ivaddr));
+    break;
+    /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */
+  case CRYP_KEYSIZE_192B:
+    CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
+    ivaddr+=4;
+    CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
+    break;
+  case CRYP_KEYSIZE_256B:
+    CRYP->IV0LR = __REV(*(uint32_t*)(ivaddr));
+    ivaddr+=4;
+    CRYP->IV0RR = __REV(*(uint32_t*)(ivaddr));
+    break;
+  default:
+    break;
+  }
+}
+
+/**
+  * @brief  Process Data: Writes Input data in polling mode and read the Output data.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Input: Pointer to the Input buffer.
+  * @param  Ilength: Length of the Input buffer, must be a multiple of 16
+  * @param  Output: Pointer to the returned buffer
+  * @param  Timeout: Timeout value 
+  * @retval None
+  */
+static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  uint32_t i = 0;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+  
+  for(i=0; (i < Ilength); i+=16)
+  {
+    /* Write the Input block in the IN FIFO */
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    CRYP->DR = *(uint32_t*)(inputaddr);
+    inputaddr+=4;
+    
+    /* Get timeout */
+    timeout = HAL_GetTick() + Timeout;
+ 
+    while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_OFNE))
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    /* Read the Output block from the OUT FIFO */
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = CRYP->DOUT;
+    outputaddr+=4;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Sets the header phase
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Input: Pointer to the Input buffer.
+  * @param  Ilength: Length of the Input buffer, must be a multiple of 16
+  * @param  Timeout: Timeout value   
+  * @retval None
+  */
+static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  uint32_t loopcounter = 0;
+  uint32_t headeraddr = (uint32_t)Input;
+  
+  /***************************** Header phase *********************************/
+  if(hcryp->Init.HeaderSize != 0)
+  {
+    /* Select header phase */
+    __HAL_CRYP_SET_PHASE(CRYP_PHASE_HEADER);
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE();
+    
+    for(loopcounter = 0; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=16)
+    {
+      /* Get timeout */
+      timeout = HAL_GetTick() + Timeout;
+      
+      while(HAL_IS_BIT_CLR(CRYP->SR, CRYP_FLAG_IFEM))
+      {
+        /* Check for the Timeout */
+        if(Timeout != HAL_MAX_DELAY)
+        {
+          if(HAL_GetTick() >= timeout)
+          {
+            /* Change state */
+            hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+            
+            /* Process Unlocked */          
+            __HAL_UNLOCK(hcryp);
+            
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      /* Write the Input block in the IN FIFO */
+      CRYP->DR = *(uint32_t*)(headeraddr);
+      headeraddr+=4;
+      CRYP->DR = *(uint32_t*)(headeraddr);
+      headeraddr+=4;
+      CRYP->DR = *(uint32_t*)(headeraddr);
+      headeraddr+=4;
+      CRYP->DR = *(uint32_t*)(headeraddr);
+      headeraddr+=4;
+    }
+    
+    /* Wait until the complete message has been processed */
+
+    /* Get timeout */
+    timeout = HAL_GetTick() + Timeout;
+
+    while((CRYP->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Sets the DMA configuration and start the DMA transfert.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  inputaddr: Address of the Input buffer
+  * @param  Size: Size of the Input buffer, must be a multiple of 16
+  * @param  outputaddr: Address of the Output buffer
+  * @retval None
+  */
+static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
+{
+  /* Set the CRYP DMA transfer complete callback */
+  hcryp->hdmain->XferCpltCallback = CRYPEx_GCMCCM_DMAInCplt;
+  /* Set the DMA error callback */
+  hcryp->hdmain->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
+  
+  /* Set the CRYP DMA transfer complete callback */
+  hcryp->hdmaout->XferCpltCallback = CRYPEx_GCMCCM_DMAOutCplt;
+  /* Set the DMA error callback */
+  hcryp->hdmaout->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
+  
+  /* Enable the CRYP peripheral */
+  __HAL_CRYP_ENABLE();
+  
+  /* Enable the DMA In DMA Stream */
+  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&CRYP->DR, Size/4);
+  
+  /* Enable In DMA request */
+  CRYP->DMACR = CRYP_DMACR_DIEN;
+  
+  /* Enable the DMA Out DMA Stream */
+  HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&CRYP->DOUT, outputaddr, Size/4);
+  
+  /* Enable Out DMA request */
+  CRYP->DMACR |= CRYP_DMACR_DOEN;
+}
+
+/**
+  * @}
+  */
+#endif /* STM32F437xx || STM32F439xx */
+
+#endif /* HAL_CRYP_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_cryp_ex.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,147 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_cryp_ex.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of CRYP HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CRYP_EX_H
+#define __STM32F4xx_HAL_CRYP_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F437xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRYPEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/ 
+/* Exported constants --------------------------------------------------------*/
+   
+/** @defgroup CRYPEx_Exported_Constants
+  * @{
+  */
+
+/** @defgroup CRYPEx_AlgoModeDirection
+  * @{
+  */ 
+#define CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT   ((uint32_t)0x00080000)
+#define CRYP_CR_ALGOMODE_AES_GCM_DECRYPT   ((uint32_t)0x00080004)
+#define CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT   ((uint32_t)0x00080008)
+#define CRYP_CR_ALGOMODE_AES_CCM_DECRYPT   ((uint32_t)0x0008000C)
+/**
+  * @}
+  */
+
+/** @defgroup CRYPEx_PhaseConfig
+  *           The phases are relevant only to AES-GCM and AES-CCM
+  * @{
+  */ 
+#define CRYP_PHASE_INIT           ((uint32_t)0x00000000)
+#define CRYP_PHASE_HEADER         CRYP_CR_GCM_CCMPH_0
+#define CRYP_PHASE_PAYLOAD        CRYP_CR_GCM_CCMPH_1
+#define CRYP_PHASE_FINAL          CRYP_CR_GCM_CCMPH
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+  * @brief  Set the phase: Init, header, payload, final. 
+  *         This is relevant only for GCM and CCM modes.
+  * @param  PHASE: The phase.
+  * @retval None
+  */
+#define __HAL_CRYP_SET_PHASE(PHASE)  do{CRYP->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
+                                        CRYP->CR |= (uint32_t)(PHASE);\
+                                       }while(0)
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/* AES encryption/decryption using polling  ***********************************/
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint16_t Size, uint8_t *AuthTag, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout);
+
+/* AES encryption/decryption using interrupt  *********************************/
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* AES encryption/decryption using DMA  ***************************************/
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+
+/* Processing functions  ********************************************************/
+void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);
+
+#endif /* STM32F437xx || STM32F439xx */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CRYP_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,941 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dac.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   DAC HAL module driver.
+  *         This file provides firmware functions to manage the following 
+  *         functionalities of the Digital to Analog Converter (DAC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Errors functions      
+  *     
+  *
+  @verbatim      
+  ==============================================================================
+                      ##### DAC Peripheral features #####
+  ==============================================================================
+    [..]        
+      *** DAC Channels ***
+      ====================  
+    [..]  
+    The device integrates two 12-bit Digital Analog Converters that can 
+    be used independently or simultaneously (dual mode):
+      (#) DAC channel1 with DAC_OUT1 (PA4) as output
+      (#) DAC channel2 with DAC_OUT2 (PA5) as output
+      
+      *** DAC Triggers ***
+      ====================
+    [..]
+    Digital to Analog conversion can be non-triggered using DAC_Trigger_None
+    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. 
+    [..] 
+    Digital to Analog conversion can be triggered by:
+      (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
+          The used pin (GPIOx_Pin9) must be configured in input mode.
+  
+      (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 
+          (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
+  
+      (#) Software using DAC_Trigger_Software
+  
+      *** DAC Buffer mode feature ***
+      =============================== 
+      [..] 
+      Each DAC channel integrates an output buffer that can be used to 
+      reduce the output impedance, and to drive external loads directly
+      without having to add an external operational amplifier.
+      To enable, the output buffer use  
+      sConfig.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+      [..]           
+      (@) Refer to the device datasheet for more details about output 
+          impedance value with and without output buffer.
+            
+       *** DAC wave generation feature ***
+       =================================== 
+       [..]     
+       Both DAC channels can be used to generate
+         (#) Noise wave 
+         (#) Triangle wave
+            
+       *** DAC data format ***
+       =======================
+       [..]   
+       The DAC data format can be:
+         (#) 8-bit right alignment using DAC_ALIGN_8B_R
+         (#) 12-bit left alignment using DAC_ALIGN_12B_L
+         (#) 12-bit right alignment using DAC_ALIGN_12B_R
+  
+       *** DAC data value to voltage correspondence ***  
+       ================================================ 
+       [..] 
+       The analog output voltage on each DAC channel pin is determined
+       by the following equation: 
+       DAC_OUTx = VREF+ * DOR / 4095
+       with  DOR is the Data Output Register
+          VEF+ is the input voltage reference (refer to the device datasheet)
+        e.g. To set DAC_OUT1 to 0.7V, use
+          Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+  
+       *** DMA requests  ***
+       =====================
+       [..]    
+       A DMA1 request can be generated when an external trigger (but not
+       a software trigger) occurs if DMA1 requests are enabled using
+       HAL_DAC_Start_DMA()
+       [..]
+       DMA1 requests are mapped as following:
+         (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be 
+             already configured
+         (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be 
+             already configured
+       
+    -@- For Dual mode and specific signal (Triangle and noise) generation please 
+        refer to Extension Features Driver description        
+  
+      
+                      ##### How to use this driver #####
+  ==============================================================================
+    [..]          
+      (+) DAC APB clock must be enabled to get write access to DAC
+          registers using HAL_DAC_Init()
+      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
+      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
+      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
+
+     *** Polling mode IO operation ***
+     =================================
+     [..]    
+       (+) Start the DAC peripheral using HAL_DAC_Start() 
+       (+) To read the DAC last data output value value, use the HAL_DAC_GetValue() function.
+       (+) Stop the DAC peripheral using HAL_DAC_Stop()
+       
+     *** DMA mode IO operation ***    
+     ==============================
+     [..]    
+       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length 
+           of data to be transferred at each end of conversion 
+       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()  
+           function is executed and user can add his own code by customization of function pointer 
+           HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
+       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can 
+            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
+       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
+                    
+     *** DAC HAL driver macros list ***
+     ============================================= 
+     [..]
+       Below the list of most used macros in DAC HAL driver.
+       
+      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
+      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
+      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
+      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
+      
+     [..]
+      (@) You can refer to the DAC HAL driver header file for more useful macros  
+   
+ @endverbatim    
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DAC 
+  * @brief DAC driver modules
+  * @{
+  */ 
+
+#ifdef HAL_DAC_MODULE_ENABLED
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); 
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Functions
+  * @{
+  */
+
+/** @defgroup DAC_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the DAC. 
+      (+) De-initialize the DAC. 
+         
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the DAC peripheral according to the specified parameters
+  *         in the DAC_InitStruct.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
+{ 
+  /* Check DAC handle */
+  if(hdac == NULL)
+  {
+     return HAL_ERROR;
+  }
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+  
+  if(hdac->State == HAL_DAC_STATE_RESET)
+  {  
+    /* Init the low level hardware */
+    HAL_DAC_MspInit(hdac);
+  }
+  
+  /* Initialize the DAC state*/
+  hdac->State = HAL_DAC_STATE_BUSY;
+  
+  /* Set DAC error code to none */
+  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+  
+  /* Initialize the DAC state*/
+  hdac->State = HAL_DAC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
+{
+  /* Check DAC handle */
+  if(hdac == NULL)
+  {
+     return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  /* DeInit the low level hardware */
+  HAL_DAC_MspDeInit(hdac);
+
+  /* Set DAC error code to none */
+  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the DAC MSP.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  DeInitializes the DAC MSP.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.  
+  * @retval None
+  */
+__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Group2 IO operation functions
+ *  @brief    IO operation functions 
+ *
+@verbatim   
+  ==============================================================================
+             ##### IO operation functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Start conversion.
+      (+) Stop conversion.
+      (+) Start conversion and enable DMA transfer.
+      (+) Stop conversion and disable DMA transfer.
+      (+) Get result of conversion.
+                     
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables DAC and starts conversion of channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+  uint32_t tmp1 = 0, tmp2 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  
+  /* Process locked */
+  __HAL_LOCK(hdac);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+  
+  /* Enable the Peripharal */
+  __HAL_DAC_ENABLE(hdac, Channel);
+  
+  if(Channel == DAC_CHANNEL_1)
+  {
+    tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
+    tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
+    /* Check if software trigger enabled */
+    if((tmp1 ==  DAC_CR_TEN1) && (tmp2 ==  DAC_CR_TSEL1))
+    {
+      /* Enable the selected DAC software conversion */
+      hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
+    }
+  }
+  else
+  {
+    tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
+    tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;    
+    /* Check if software trigger enabled */
+    if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
+    {
+      /* Enable the selected DAC software conversion*/
+      hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;
+    }
+  }
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+    
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables DAC and stop conversion of channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  
+  /* Disable the Peripheral */
+  __HAL_DAC_DISABLE(hdac, Channel);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables DAC and starts conversion of channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @param  pData: The destination peripheral Buffer address.
+  * @param  Length: The length of data to be transferred from memory to DAC peripheral
+  * @param  Alignment: Specifies the data alignment for DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
+{
+  uint32_t tmpreg = 0;
+    
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_ALIGN(Alignment));
+  
+  /* Process locked */
+  __HAL_LOCK(hdac);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  if(Channel == DAC_CHANNEL_1)
+  {
+    /* Set the DMA transfer complete callback for channel1 */
+    hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+    /* Set the DMA half transfer complete callback for channel1 */
+    hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+    /* Set the DMA error callback for channel1 */
+    hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
+    /* Enable the selected DAC channel1 DMA request */
+    hdac->Instance->CR |= DAC_CR_DMAEN1;
+    
+    /* Case of use of channel 1 */
+    switch(Alignment)
+    {
+      case DAC_ALIGN_12B_R:
+        /* Get DHR12R1 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
+        break;
+      case DAC_ALIGN_12B_L:
+        /* Get DHR12L1 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
+        break;
+      case DAC_ALIGN_8B_R:
+        /* Get DHR8R1 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
+        break;
+      default:
+        break;
+    }
+  }
+  else
+  {
+    /* Set the DMA transfer complete callback for channel2 */
+    hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
+
+    /* Set the DMA half transfer complete callback for channel2 */
+    hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
+
+    /* Set the DMA error callback for channel2 */
+    hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
+
+    /* Enable the selected DAC channel2 DMA request */
+    hdac->Instance->CR |= DAC_CR_DMAEN2;
+
+    /* Case of use of channel 2 */
+    switch(Alignment)
+    {
+      case DAC_ALIGN_12B_R:
+        /* Get DHR12R2 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
+        break;
+      case DAC_ALIGN_12B_L:
+        /* Get DHR12L2 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
+        break;
+      case DAC_ALIGN_8B_R:
+        /* Get DHR8R2 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
+        break;
+      default:
+        break;
+    }
+  }
+  
+  /* Enable the DMA Stream */
+  if(Channel == DAC_CHANNEL_1)
+  {
+    /* Enable the DAC DMA underrun interrupt */
+    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+    
+    /* Enable the DMA Stream */
+    HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+  } 
+  else
+  {
+    /* Enable the DAC DMA underrun interrupt */
+    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
+    
+    /* Enable the DMA Stream */
+    HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
+  }
+  
+  /* Enable the Peripharal */
+  __HAL_DAC_ENABLE(hdac, Channel);
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdac);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables DAC and stop conversion of channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  
+  /* Disable the selected DAC channel DMA request */
+   hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
+    
+  /* Disable the Peripharal */
+  __HAL_DAC_DISABLE(hdac, Channel);
+  
+  /* Disable the DMA Channel */
+  /* Channel1 is used */
+  if(Channel == DAC_CHANNEL_1)
+  { 
+    status = HAL_DMA_Abort(hdac->DMA_Handle1);
+  }
+  else /* Channel2 is used for */
+  { 
+    status = HAL_DMA_Abort(hdac->DMA_Handle2); 
+  }
+
+  /* Check if DMA Channel effectively disabled */
+  if(status == HAL_ERROR)
+  {
+    /* Update ADC state machine to error */
+    hdac->State = HAL_DAC_STATE_ERROR;      
+  }
+  else
+  {
+    /* Change DAC state */
+    hdac->State = HAL_DAC_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @retval The selected DAC channel data output value.
+  */
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  
+  /* Returns the DAC channel data output register value */
+  if(Channel == DAC_CHANNEL_1)
+  {
+    return hdac->Instance->DOR1;
+  }
+  else
+  {
+    return hdac->Instance->DOR2;
+  }
+}
+
+/**
+  * @brief  Handles DAC interrupt request  
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
+{
+  /* Check Overrun flag */
+  if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+  {
+    /* Change DAC state to error state */
+    hdac->State = HAL_DAC_STATE_ERROR;
+    
+    /* Set DAC error code to chanel1 DMA underrun error */
+    hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
+    
+    /* Clear the underrun flag */
+    __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
+    
+    /* Disable the selected DAC channel1 DMA request */
+    hdac->Instance->CR &= ~DAC_CR_DMAEN1;
+    
+    /* Error callback */ 
+    HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+  }
+  else
+  {
+    /* Change DAC state to error state */
+    hdac->State = HAL_DAC_STATE_ERROR;
+    
+    /* Set DAC error code to channel2 DMA underrun error */
+    hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
+    
+    /* Clear the underrun flag */
+    __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
+    
+    /* Disable the selected DAC channel1 DMA request */
+    hdac->Instance->CR &= ~DAC_CR_DMAEN2;
+    
+    /* Error callback */ 
+    HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
+  }
+}
+
+/**
+  * @brief  Conversion complete callback in non blocking mode for Channel1 
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_ConvCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Conversion half DMA transfer callback in non blocking mode for Channel1 
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error DAC callback for Channel1.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA underrun DAC callback for channel1.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_Group3 Peripheral Control functions
+ *  @brief   	Peripheral Control functions 
+ *
+@verbatim   
+  ==============================================================================
+             ##### Peripheral Control functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure channels. 
+      (+) Set the specified data holding register value for DAC channel.
+      
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the selected DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  sConfig: DAC configuration structure.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+  /* Check the DAC parameters */
+  assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
+  assert_param(IS_DAC_CHANNEL(Channel));
+  
+  /* Process locked */
+  __HAL_LOCK(hdac);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+  
+  /* Get the DAC CR value */
+  tmpreg1 = DAC->CR;
+  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+  tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
+  /* Configure for the selected DAC channel: buffer output, trigger */
+  /* Set TSELx and TENx bits according to DAC_Trigger value */
+  /* Set BOFFx bit according to DAC_OutputBuffer value */   
+  tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
+  /* Calculate CR register value depending on DAC_Channel */
+  tmpreg1 |= tmpreg2 << Channel;
+  /* Write to DAC CR */
+  DAC->CR = tmpreg1;
+  /* Disable wave generation */
+  DAC->CR &= ~(DAC_CR_WAVE1 << Channel);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected  
+  * @param  Alignment: Specifies the data alignment.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @param  Data: Data to be loaded in the selected data holding register.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
+{  
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_ALIGN(Alignment));
+  assert_param(IS_DAC_DATA(Data));
+  
+  tmp = (uint32_t)hdac->Instance; 
+  if(Channel == DAC_CHANNEL_1)
+  {
+    tmp += __HAL_DHR12R1_ALIGNEMENT(Alignment);
+  }
+  else
+  {
+    tmp += __HAL_DHR12R2_ALIGNEMENT(Alignment);
+  }
+
+  /* Set the DAC channel1 selected data holding register */
+  *(__IO uint32_t *) tmp = Data;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Group4 Peripheral State and Errors functions
+ *  @brief   Peripheral State and Errors functions 
+ *
+@verbatim   
+  ==============================================================================
+            ##### Peripheral State and Errors functions #####
+  ==============================================================================  
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DAC state.
+      (+) Check the DAC Errors.
+        
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  return the DAC state
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval HAL state
+  */
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
+{
+  /* Return DAC state */
+  return hdac->State;
+}
+
+
+/**
+  * @brief  Return the DAC error code
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval DAC Error Code
+  */
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
+{
+  return hdac->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  DMA conversion complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)   
+{
+  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  HAL_DAC_ConvCpltCallbackCh1(hdac); 
+  
+  hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+  * @brief  DMA half transfer complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)   
+{
+    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    /* Conversion complete callback */
+    HAL_DAC_ConvHalfCpltCallbackCh1(hdac); 
+}
+
+/**
+  * @brief  DMA error callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)   
+{
+  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    
+  /* Set DAC error code to DMA error */
+  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+    
+  HAL_DAC_ErrorCallbackCh1(hdac); 
+    
+  hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+  * @}
+  */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,332 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dac.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of DAC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DAC_H
+#define __STM32F4xx_HAL_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DAC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_DAC_STATE_RESET             = 0x00,  /*!< DAC not yet initialized or disabled  */
+  HAL_DAC_STATE_READY             = 0x01,  /*!< DAC initialized and ready for use    */
+  HAL_DAC_STATE_BUSY              = 0x02,  /*!< DAC internal processing is ongoing   */
+  HAL_DAC_STATE_TIMEOUT           = 0x03,  /*!< DAC timeout state                    */
+  HAL_DAC_STATE_ERROR             = 0x04   /*!< DAC error state                      */
+}HAL_DAC_StateTypeDef;
+ 
+/** 
+  * @brief  DAC handle Structure definition
+  */
+typedef struct
+{
+  DAC_TypeDef                 *Instance;     /*!< Register base address             */
+
+  __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
+
+  HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
+
+  DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
+
+  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */
+
+  __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
+
+}DAC_HandleTypeDef;
+
+/** 
+  * @brief   DAC Configuration regular Channel structure definition
+  */
+typedef struct
+{
+  uint32_t DAC_Trigger;       /*!< Specifies the external trigger for the selected DAC channel.
+                                   This parameter can be a value of @ref DAC_trigger_selection */
+
+  uint32_t DAC_OutputBuffer;  /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                   This parameter can be a value of @ref DAC_output_buffer */
+}DAC_ChannelConfTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Error_Code
+  * @{
+  */
+#define  HAL_DAC_ERROR_NONE              0x00    /*!< No error                          */
+#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01    /*!< DAC channel1 DAM underrun error   */
+#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02    /*!< DAC channel2 DAM underrun error   */
+#define  HAL_DAC_ERROR_DMA               0x04    /*!< DMA error                         */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_trigger_selection
+  * @{
+  */
+
+#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+                                                                       has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T5_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T8_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */                                                                       
+
+#define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_output_buffer 
+  * @{
+  */
+#define DAC_OUTPUTBUFFER_ENABLE            ((uint32_t)0x00000000)
+#define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_CR_BOFF1)
+
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Channel_selection 
+  * @{
+  */
+#define DAC_CHANNEL_1                      ((uint32_t)0x00000000)
+#define DAC_CHANNEL_2                      ((uint32_t)0x00000010)
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+                                 ((CHANNEL) == DAC_CHANNEL_2))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignement 
+  * @{
+  */
+#define DAC_ALIGN_12B_R                    ((uint32_t)0x00000000)
+#define DAC_ALIGN_12B_L                    ((uint32_t)0x00000004)
+#define DAC_ALIGN_8B_R                     ((uint32_t)0x00000008)
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+                             ((ALIGN) == DAC_ALIGN_12B_L) || \
+                             ((ALIGN) == DAC_ALIGN_8B_R))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data 
+  * @{
+  */
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+/**
+  * @}
+  */
+
+/** @defgroup DAC_flags_definition 
+  * @{
+  */ 
+#define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
+
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR1) || \
+                           ((FLAG) == DAC_FLAG_DMAUDR2))  
+/**
+  * @}
+  */
+
+/** @defgroup DAC_IT_definition 
+  * @{
+  */ 
+#define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
+
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR1) || \
+                       ((IT) == DAC_IT_DMAUDR2))  
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset DAC handle state
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @retval None
+  */
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+
+/** @brief Enable the DAC channel
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @param  __DAC_Channel__: specifies the DAC channel
+  * @retval None
+  */
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_Channel__)))
+
+/** @brief Disable the DAC channel
+  * @param  __HANDLE__: specifies the DAC handle
+  * @param  __DAC_Channel__: specifies the DAC channel.
+  * @retval None
+  */
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_Channel__)))
+
+/** @brief Set DHR12R1 alignment
+  * @param  __ALIGNEMENT__: specifies the DAC alignement
+  * @retval None
+  */
+#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__))
+
+/** @brief  Set DHR12R2 alignment
+  * @param  __ALIGNEMENT__: specifies the DAC alignement
+  * @retval None
+  */
+#define __HAL_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__))
+
+/** @brief  Set DHR12RD alignment
+  * @param  __ALIGNEMENT__: specifies the DAC alignement
+  * @retval None
+  */
+#define __HAL_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__))
+
+/** @brief Enable the DAC interrupt
+  * @param  __HANDLE__: specifies the DAC handle
+  * @param  __INTERRUPT__: specifies the DAC interrupt.
+  * @retval None
+  */
+#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+/** @brief Disable the DAC interrupt
+  * @param  __HANDLE__: specifies the DAC handle
+  * @param  __INTERRUPT__: specifies the DAC interrupt.
+  * @retval None
+  */
+#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/** @brief  Get the selected DAC's flag status.
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @retval None
+  */
+#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the DAC's flag.
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @retval None
+  */
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) |= (__FLAG__))
+
+/* Include DAC HAL Extension module */
+#include "stm32f4xx_hal_dac_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions *********************************/
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
+
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
+
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+
+/* Peripheral State functions *************************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_HAL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac_ex.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,379 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dac_ex.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   DAC HAL module driver.
+  *         This file provides firmware functions to manage the following 
+  *         functionalities of DAC extension peripheral:
+  *           + Extended features functions
+  *     
+  *
+  @verbatim      
+  ==============================================================================
+                      ##### How to use this driver #####
+  ==============================================================================
+    [..]          
+      (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
+          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
+          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.  
+      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
+      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
+   
+ @endverbatim    
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DACEx 
+  * @brief DAC driver modules
+  * @{
+  */ 
+
+#ifdef HAL_DAC_MODULE_ENABLED
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DACEx_Private_Functions
+  * @{
+  */
+
+/** @defgroup DACEx_Group1 Extended features functions
+ *  @brief    Extended features functions 
+ *
+@verbatim   
+  ==============================================================================
+                 ##### Extended features functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Start conversion.
+      (+) Stop conversion.
+      (+) Start conversion and enable DMA transfer.
+      (+) Stop conversion and disable DMA transfer.
+      (+) Get result of conversion.
+      (+) Get result of dual mode conversion.
+                     
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval The selected DAC channel data output value.
+  */
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
+{
+  uint32_t tmp = 0;
+  
+  tmp |= hdac->Instance->DOR1;
+  
+  tmp |= hdac->Instance->DOR2 << 16;
+  
+  /* Returns the DAC channel data output register value */
+  return tmp;
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel wave generation.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            DAC_CHANNEL_1 / DAC_CHANNEL_2
+  * @param  Amplitude: Select max triangle amplitude. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
+  *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
+  *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
+  *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
+  *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
+  *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
+  *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
+  *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
+  *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
+  *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
+  *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
+  *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095                               
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+  
+  /* Process locked */
+  __HAL_LOCK(hdac);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+  
+  /* Enable the selected wave generation for the selected DAC channel */
+  hdac->Instance->CR |= (DAC_WAVE_TRIANGLE | Amplitude) << Channel;
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel wave generation.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC. 
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            DAC_CHANNEL_1 / DAC_CHANNEL_2
+  * @param  Amplitude: Unmask DAC channel LFSR for noise wave generation. 
+  *          This parameter can be one of the following values: 
+  *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation  
+  *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+  
+  /* Process locked */
+  __HAL_LOCK(hdac);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+  
+  /* Enable the selected wave generation for the selected DAC channel */
+  hdac->Instance->CR |= (DAC_WAVE_NOISE | Amplitude) << Channel;
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the specified data holding register value for dual DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *               the configuration information for the specified DAC.
+  * @param  Alignment: Specifies the data alignment for dual channel DAC.
+  *          This parameter can be one of the following values:
+  *            DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @param  Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
+  * @param  Data2: Data for DAC Channel1 to be loaded in the selected data  holding register.
+  * @note   In dual mode, a unique register access is required to write in both
+  *          DAC channels at the same time.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
+{  
+  uint32_t data = 0, tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(Alignment));
+  assert_param(IS_DAC_DATA(Data1));
+  assert_param(IS_DAC_DATA(Data2));
+  
+  /* Calculate and set dual DAC data holding register value */
+  if (Alignment == DAC_ALIGN_8B_R)
+  {
+    data = ((uint32_t)Data2 << 8) | Data1; 
+  }
+  else
+  {
+    data = ((uint32_t)Data2 << 16) | Data1;
+  }
+  
+  tmp = (uint32_t)hdac->Instance;
+  tmp += __HAL_DHR12RD_ALIGNEMENT(Alignment);
+
+  /* Set the dual DAC selected data holding register */
+  *(__IO uint32_t *)tmp = data;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Conversion complete callback in non blocking mode for Channel2 
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_ConvCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Conversion half DMA transfer callback in non blocking mode for Channel2 
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_ConvHalfCpltCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error DAC callback for Channel2.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA underrun DAC callback for channel2.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA conversion complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)   
+{
+  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  HAL_DACEx_ConvCpltCallbackCh2(hdac); 
+  
+  hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+  * @brief  DMA half transfer complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)   
+{
+    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    /* Conversion complete callback */
+    HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); 
+}
+
+/**
+  * @brief  DMA error callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)   
+{
+  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    
+  /* Set DAC error code to DMA error */
+  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+    
+  HAL_DACEx_ErrorCallbackCh2(hdac); 
+    
+  hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+  * @}
+  */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dac_ex.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,184 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dac.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of DAC HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DAC_EX_H
+#define __STM32F4xx_HAL_DAC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DACEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+   
+/** 
+  * @brief  HAL State structures definition  
+  */ 
+
+/* Exported constants --------------------------------------------------------*/
+  
+/** @defgroup DACEx_wave_generation 
+  * @{
+  */
+#define DAC_WAVEGENERATION_NONE            ((uint32_t)0x00000000)
+#define DAC_WAVEGENERATION_NOISE           ((uint32_t)DAC_CR_WAVE1_0)
+#define DAC_WAVEGENERATION_TRIANGLE        ((uint32_t)DAC_CR_WAVE1_1)
+
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NONE) || \
+                                    ((WAVE) == DAC_WAVEGENERATION_NOISE) || \
+                                    ((WAVE) == DAC_WAVEGENERATION_TRIANGLE))
+/**
+  * @}
+  */
+
+/** @defgroup DACEx_lfsrunmask_triangleamplitude
+  * @{
+  */
+#define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+/**
+  * @}
+  */
+
+/** @defgroup DACEx_wave_generation 
+  * @{
+  */
+#define DAC_WAVE_NOISE                     ((uint32_t)DAC_CR_WAVE1_0)
+#define DAC_WAVE_TRIANGLE                  ((uint32_t)DAC_CR_WAVE1_1)
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || \
+                           ((WAVE) == DAC_WAVE_TRIANGLE))
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/  
+
+/* Extension features functions ***********************************************/
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
+
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); 
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_HAL_DAC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,819 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dcmi.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   DCMI HAL module driver
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Digital Camera Interface (DCMI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State and Error functions  
+  *           
+  @verbatim      
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+      The sequence below describes how to use this driver to capture image
+      from a camera module connected to the DCMI Interface.
+      This sequence does not take into account the configuration of the
+      camera module, which should be made before to configure and enable
+      the DCMI to capture images.
+
+    (#) Program the required configuration through following parameters:
+        horizontal and vertical polarity, pixel clock polarity, Capture Rate,
+        Synchronization Mode, code of the frame delimiter and data width 
+        using HAL_DCMI_Init() function.
+
+    (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
+        register to the destination memory buffer.
+
+    (#) Program the required configuration through following parameters:
+        DCMI mode, destination memory Buffer address and the data length 
+        and enable capture using HAL_DCMI_Start_DMA() function.
+
+    (#) Optionally, configure and Enable the CROP feature to select a rectangular
+        window from the received image using HAL_DCMI_ConfigCrop() 
+        and HAL_DCMI_EnableCROP() functions
+
+    (#) The capture can be stopped using HAL_DCMI_Stop() function.
+
+    (#) To control DCMI state you can use the function HAL_DCMI_GetState().
+
+     *** DCMI HAL driver macros list ***
+     ============================================= 
+     [..]
+       Below the list of most used macros in DCMI HAL driver.
+       
+      (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
+      (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
+      (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
+      (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
+      (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
+      (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
+      (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.
+ 
+     [..] 
+       (@) You can refer to the DCMI HAL driver header file for more useful macros
+      
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+/** @defgroup DCMI 
+  * @brief DCMI HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define HAL_TIMEOUT_DCMI_STOP    ((uint32_t)1000)  /* 1s  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void       DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma);
+static void       DCMI_DMAError(DMA_HandleTypeDef *hdma);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DCMI_Private_Functions
+  * @{
+  */
+
+/** @defgroup DCMI_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions
+ *
+@verbatim   
+ ===============================================================================
+                ##### Initialization and Configuration functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the DCMI
+      (+) De-initialize the DCMI 
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initializes the DCMI according to the specified
+  *         parameters in the DCMI_InitTypeDef and create the associated handle.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
+{     
+  /* Check the DCMI peripheral state */
+  if(hdcmi == NULL)
+  {
+     return HAL_ERROR;
+  }
+  
+  /* Check function parameters */
+  assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
+  assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
+  assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
+  assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
+  assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
+  assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
+  assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
+  assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
+
+  if(hdcmi->State == HAL_DCMI_STATE_RESET)
+  {
+    /* Init the low level hardware */
+    HAL_DCMI_MspInit(hdcmi);
+  } 
+  
+  /* Change the DCMI state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY; 
+
+  /* Configures the HS, VS, DE and PC polarity */
+  hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL  | DCMI_CR_VSPOL  | DCMI_CR_EDM_0 |
+                           DCMI_CR_EDM_1  | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG  |
+                           DCMI_CR_ESS);
+  hdcmi->Instance->CR |=  (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \
+                                     hdcmi->Init.VSPolarity  | hdcmi->Init.HSPolarity  | \
+                                     hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \
+                                     hdcmi->Init.JPEGMode);
+
+  if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
+  {
+    DCMI->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode)    |
+                  ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8)|
+                  ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16) |
+                  ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24));
+  }
+
+  /* Enable the Line interrupt */
+  __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE);
+
+  /* Enable the VSYNC interrupt */
+  __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_VSYNC);
+
+  /* Enable the Frame capture complete interrupt */
+  __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
+
+  /* Enable the Synchronization error interrupt */
+  __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_ERR);
+
+  /* Enable the Overflow interrupt */
+  __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_OVF);
+
+  /* Enable DCMI by setting DCMIEN bit */
+  __HAL_DCMI_ENABLE(hdcmi);
+
+  /* Update error code */
+  hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
+  
+  /* Initialize the DCMI state*/
+  hdcmi->State  = HAL_DCMI_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deinitializes the DCMI peripheral registers to their default reset
+  *         values.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
+{
+  /* DeInit the low level hardware */
+  HAL_DCMI_MspDeInit(hdcmi);
+
+  /* Update error code */
+  hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
+
+  /* Initialize the DCMI state*/
+  hdcmi->State = HAL_DCMI_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdcmi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the DCMI MSP.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval None
+  */
+__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMI_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  DeInitializes the DCMI MSP.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval None
+  */
+__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMI_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+/** @defgroup DCMI_Group2 IO operation functions 
+ *  @brief   IO operation functions  
+ *
+@verbatim   
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure destination address and data length and 
+          Enables DCMI DMA request and enables DCMI capture
+      (+) Stop the DCMI capture.
+      (+) Handles DCMI interrupt request.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables DCMI DMA request and enables DCMI capture  
+  * @param  hdcmi:     pointer to a DCMI_HandleTypeDef structure that contains
+  *                    the configuration information for DCMI.
+  * @param  DCMI_Mode: DCMI capture mode snapshot or continuous grab.
+  * @param  pData:     The destination memory Buffer address (LCD Frame buffer).
+  * @param  Length:    The length of capture to be transferred.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
+{  
+  /* Initialise the second memory address */
+  uint32_t SecondMemAddress = 0;
+
+  /* Check function parameters */
+  assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
+
+  /* Process Locked */
+  __HAL_LOCK(hdcmi);
+
+  /* Lock the DCMI peripheral state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
+
+  /* Configure the DCMI Mode */
+  hdcmi->Instance->CR &= ~(DCMI_CR_CM);
+  hdcmi->Instance->CR |=  (uint32_t)(DCMI_Mode);
+
+  /* Set the DMA memory0 conversion complete callback */
+  hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAConvCplt;
+
+  /* Set the DMA error callback */
+  hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
+
+  if(Length <= 0xFFFF)
+  {
+    /* Enable the DMA Stream */
+    HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);
+  }
+  else /* DCMI_DOUBLE_BUFFER Mode */
+  {
+    /* Set the DMA memory1 conversion complete callback */
+    hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAConvCplt; 
+
+    /* Initialise transfer parameters */
+    hdcmi->XferCount = 1;
+    hdcmi->XferSize = Length;
+    hdcmi->pBuffPtr = pData;
+      
+    /* Get the number of buffer */
+    while(hdcmi->XferSize > 0xFFFF)
+    {
+      hdcmi->XferSize = (hdcmi->XferSize/2);
+      hdcmi->XferCount = hdcmi->XferCount*2;
+    }
+
+    /* Update DCMI counter  and transfer number*/
+    hdcmi->XferCount = (hdcmi->XferCount - 2);
+    hdcmi->XferTransferNumber = hdcmi->XferCount;
+
+    /* Update second memory address */
+    SecondMemAddress = (uint32_t)(pData + (4*hdcmi->XferSize));
+
+    /* Start DMA multi buffer transfer */
+    HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);
+  }
+
+  /* Enable Capture */
+  DCMI->CR |= DCMI_CR_CAPTURE;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable DCMI DMA request and Disable DCMI capture  
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI. 
+  * @retval HAL status     
+  */
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
+{
+  uint32_t timeout = 0x00;
+
+  /* Lock the DCMI peripheral state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  __HAL_DCMI_DISABLE(hdcmi);
+
+  /* Disable Capture */
+  DCMI->CR &= ~(DCMI_CR_CAPTURE);
+
+  /* Get timeout */
+  timeout = HAL_GetTick() + HAL_TIMEOUT_DCMI_STOP;
+
+  /* Check if the DCMI capture effectively disabled */
+  while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0)
+  {
+    if(HAL_GetTick() >= timeout)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdcmi);
+      
+      /* Update error code */
+      hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
+      
+      /* Change DCMI state */
+      hdcmi->State = HAL_DCMI_STATE_TIMEOUT;
+      
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Disable the DMA */
+  HAL_DMA_Abort(hdcmi->DMA_Handle);
+
+  /* Update error code */
+  hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;
+
+  /* Change DCMI state */
+  hdcmi->State = HAL_DCMI_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handles DCMI interrupt request.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for the DCMI.
+  * @retval None
+  */
+void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
+{  
+  /* Synchronization error interrupt management *******************************/
+  if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_ERRRI) != RESET)
+  {
+    if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_ERR) != RESET)
+    {
+      /* Disable the Synchronization error interrupt */
+      __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_ERR); 
+
+      /* Clear the Synchronization error flag */
+      __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
+
+      /* Update error code */
+      hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
+
+      /* Change DCMI state */
+      hdcmi->State = HAL_DCMI_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdcmi);
+
+      /* Abort the DMA Transfer */
+      HAL_DMA_Abort(hdcmi->DMA_Handle);
+      
+      /* Synchronization error Callback */
+      HAL_DCMI_ErrorCallback(hdcmi);
+    }
+  }
+  /* Overflow interrupt management ********************************************/
+  if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_OVFRI) != RESET) 
+  {
+    if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_OVF) != RESET)
+    {
+      /* Disable the Overflow interrupt */
+      __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_OVF);
+
+      /* Clear the Overflow flag */
+      __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVFRI);
+
+      /* Update error code */
+      hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVF;
+
+      /* Change DCMI state */
+      hdcmi->State = HAL_DCMI_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdcmi);
+
+      /* Abort the DMA Transfer */
+      HAL_DMA_Abort(hdcmi->DMA_Handle);
+
+      /* Overflow Callback */
+      HAL_DCMI_ErrorCallback(hdcmi);
+    }
+  }
+  /* Line Interrupt management ************************************************/
+  if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_LINERI) != RESET)
+  {
+    if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_LINE) != RESET)
+    {
+      /* Clear the Line interrupt flag */  
+      __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdcmi);
+
+      /* Line interrupt Callback */
+      HAL_DCMI_LineEventCallback(hdcmi);
+    }
+  }
+  /* VSYNC interrupt management ***********************************************/
+  if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_VSYNCRI) != RESET)
+  {
+    if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_VSYNC) != RESET)
+    {
+      /* Disable the VSYNC interrupt */
+      __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_VSYNC);   
+
+      /* Clear the VSYNC flag */
+      __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdcmi);
+
+      /* VSYNC Callback */
+      HAL_DCMI_VsyncEventCallback(hdcmi);
+    }
+  }
+  /* End of Frame interrupt management ****************************************/
+  if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET)
+  {
+    if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_FRAME) != RESET)
+    {
+      /* Disable the End of Frame interrupt */
+      __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
+
+      /* Clear the End of Frame flag */
+      __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdcmi);
+
+      /* End of Frame Callback */
+      HAL_DCMI_FrameEventCallback(hdcmi);
+    }
+  }
+}
+
+/**
+  * @brief  Error DCMI callback.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval None
+  */
+__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMI_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Line Event callback.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval None
+  */
+__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMI_LineEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  VSYNC Event callback.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval None
+  */
+__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMI_VsyncEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Frame Event callback.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval None
+  */
+__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMI_FrameEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Group3 Peripheral Control functions
+ *  @brief    Peripheral Control functions 
+ *
+@verbatim   
+ ===============================================================================
+                    ##### Peripheral Control functions #####
+ ===============================================================================  
+[..]  This section provides functions allowing to:
+      (+) Configure the CROP feature.
+      (+) Enable/Disable the CROP feature.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the DCMI CROP coordinate.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @param  YSize: DCMI Line number
+  * @param  XSize: DCMI Pixel per line
+  * @param  X0:    DCMI window X offset
+  * @param  Y0:    DCMI window Y offset
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdcmi);
+
+  /* Lock the DCMI peripheral state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_DCMI_WINDOW_COORDINATE(X0));
+  assert_param(IS_DCMI_WINDOW_COORDINATE(Y0));
+  assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
+  assert_param(IS_DCMI_WINDOW_HEIGHT(YSize));
+
+  /* Configure CROP */
+  DCMI->CWSIZER = (XSize | (YSize << 16));
+  DCMI->CWSTRTR = (X0 | (Y0 << 16));
+
+  /* Initialize the DCMI state*/
+  hdcmi->State  = HAL_DCMI_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Crop feature.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdcmi);
+
+  /* Lock the DCMI peripheral state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  /* Disable DCMI Crop feature */
+  DCMI->CR &= ~(uint32_t)DCMI_CR_CROP;  
+
+  /* Change the DCMI state*/
+  hdcmi->State = HAL_DCMI_STATE_READY;   
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Enable the Crop feature.
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdcmi);
+
+  /* Lock the DCMI peripheral state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  /* Enable DCMI Crop feature */
+  DCMI->CR |= (uint32_t)DCMI_CR_CROP;
+
+  /* Change the DCMI state*/
+  hdcmi->State = HAL_DCMI_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  return HAL_OK;  
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Group4 Peripheral State functions
+ *  @brief    Peripheral State functions 
+ *
+@verbatim   
+ ===============================================================================
+               ##### Peripheral State and Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DCMI state.
+      (+) Get the specific DCMI error flag.  
+
+@endverbatim
+  * @{
+  */ 
+
+/**
+  * @brief  Return the DCMI state
+  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL state
+  */
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)  
+{
+  return hdcmi->State;
+}
+
+/**
+* @brief  Return the DCMI error code
+* @param  hdcmi : pointer to a DCMI_HandleTypeDef structure that contains
+  *               the configuration information for DCMI.
+* @retval DCMI Error Code
+*/
+uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
+{
+  return hdcmi->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+  /**
+  * @brief  DMA conversion complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+  uint32_t tmp = 0;
+ 
+  DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  hdcmi->State= HAL_DCMI_STATE_READY;
+
+  if(hdcmi->XferCount != 0)
+  {
+    /* Update memory 0 address location */
+    tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT);
+    if(((hdcmi->XferCount % 2) == 0) && (tmp != 0))
+    {
+      tmp = hdcmi->DMA_Handle->Instance->M0AR;
+      HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY0);
+      hdcmi->XferCount--;
+    }
+    /* Update memory 1 address location */
+    else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
+    {
+      tmp = hdcmi->DMA_Handle->Instance->M1AR;
+      HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY1);
+      hdcmi->XferCount--;
+    }
+  }
+  /* Update memory 0 address location */
+  else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0)
+  {
+    hdcmi->DMA_Handle->Instance->M0AR = hdcmi->pBuffPtr;
+  }
+  /* Update memory 1 address location */
+  else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
+  {
+    tmp = hdcmi->pBuffPtr;
+    hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4*hdcmi->XferSize));
+    hdcmi->XferCount = hdcmi->XferTransferNumber;
+  }
+
+  if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdcmi);
+
+    /* FRAME Callback */
+    HAL_DCMI_FrameEventCallback(hdcmi);
+  }
+}
+
+/**
+  * @brief  DMA error callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
+{
+    DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;     
+    hdcmi->State= HAL_DCMI_STATE_READY;
+    HAL_DCMI_ErrorCallback(hdcmi);
+}
+
+/**
+  * @}
+  */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* HAL_DCMI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dcmi.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,499 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dcmi.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of DCMI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DCMI_H
+#define __STM32F4xx_HAL_DCMI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DCMI
+  * @{
+  */  
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief DCMI Error source
+  */
+typedef enum
+{ 
+  DCMI_ERROR_SYNC = 1,     /*!< Synchronisation error */
+  DCMI_OVERRUN   = 2,      /*!< DCMI Overrun */
+}DCMI_ErrorTypeDef;
+
+/** 
+  * @brief   DCMI Embedded Synchronisation CODE Init structure definition
+  */ 
+typedef struct
+{
+  uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
+  uint8_t LineStartCode;  /*!< Specifies the code of the line start delimiter.  */
+  uint8_t LineEndCode;    /*!< Specifies the code of the line end delimiter.    */
+  uint8_t FrameEndCode;   /*!< Specifies the code of the frame end delimiter.   */
+}DCMI_CodesInitTypeDef;
+
+/** 
+  * @brief   DCMI Init structure definition
+  */ 
+typedef struct
+{
+  uint32_t  SynchroMode;                /*!< Specifies the Synchronization Mode: Hardware or Embedded.
+                                             This parameter can be a value of @ref DCMI_Synchronization_Mode */
+
+  uint32_t  PCKPolarity;                /*!< Specifies the Pixel clock polarity: Falling or Rising.
+                                             This parameter can be a value of @ref DCMI_PIXCK_Polarity       */
+
+  uint32_t  VSPolarity;                 /*!< Specifies the Vertical synchronization polarity: High or Low.
+                                             This parameter can be a value of @ref DCMI_VSYNC_Polarity       */
+
+  uint32_t  HSPolarity;                 /*!< Specifies the Horizontal synchronization polarity: High or Low.
+                                             This parameter can be a value of @ref DCMI_HSYNC_Polarity       */
+
+  uint32_t  CaptureRate;                /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
+                                             This parameter can be a value of @ref DCMI_Capture_Rate         */
+
+  uint32_t  ExtendedDataMode;           /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
+                                             This parameter can be a value of @ref DCMI_Extended_Data_Mode   */
+
+  DCMI_CodesInitTypeDef SyncroCode;     /*!< Specifies the code of the frame start delimiter.                */
+
+  uint32_t JPEGMode;                    /*!< Enable or Disable the JPEG mode.                                
+                                             This parameter can be a value of @ref DCMI_MODE_JPEG            */
+
+}DCMI_InitTypeDef;
+
+/** 
+  * @brief  HAL DCMI State structures definition
+  */ 
+typedef enum
+{
+  HAL_DCMI_STATE_RESET             = 0x00,  /*!< DCMI not yet initialized or disabled  */
+  HAL_DCMI_STATE_READY             = 0x01,  /*!< DCMI initialized and ready for use    */
+  HAL_DCMI_STATE_BUSY              = 0x02,  /*!< DCMI internal processing is ongoing   */
+  HAL_DCMI_STATE_TIMEOUT           = 0x03,  /*!< DCMI timeout state                    */
+  HAL_DCMI_STATE_ERROR             = 0x04   /*!< DCMI error state                      */
+}HAL_DCMI_StateTypeDef;
+
+/** 
+  * @brief  DCMI handle Structure definition
+  */
+typedef struct
+{
+  DCMI_TypeDef                  *Instance;           /*!< DCMI Register base address   */
+
+  DCMI_InitTypeDef              Init;                /*!< DCMI parameters              */
+
+  HAL_LockTypeDef               Lock;                /*!< DCMI locking object          */
+
+  __IO HAL_DCMI_StateTypeDef    State;               /*!< DCMI state                   */
+
+  __IO uint32_t                 XferCount;           /*!< DMA transfer counter         */
+
+  __IO uint32_t                 XferSize;            /*!< DMA transfer size            */
+
+  uint32_t                      XferTransferNumber;  /*!< DMA transfer number          */
+
+  uint32_t                      pBuffPtr;            /*!< Pointer to DMA output buffer */
+
+  DMA_HandleTypeDef             *DMA_Handle;         /*!< Pointer to the DMA handler   */
+
+  __IO uint32_t                 ErrorCode;           /*!< DCMI Error code              */
+
+}DCMI_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DCMI_Exported_Constants
+  * @{
+  */
+
+/** @defgroup DCMI_Error_Code
+  * @{
+  */
+#define HAL_DCMI_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error              */
+#define HAL_DCMI_ERROR_OVF       ((uint32_t)0x00000001)    /*!< Overflow error        */
+#define HAL_DCMI_ERROR_SYNC      ((uint32_t)0x00000002)    /*!< Synchronization error */
+#define HAL_DCMI_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error         */
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Capture_Mode
+  * @{
+  */ 
+#define DCMI_MODE_CONTINUOUS           ((uint32_t)0x00000000)  /*!< The received data are transferred continuously 
+                                                                    into the destination memory through the DMA             */
+#define DCMI_MODE_SNAPSHOT             ((uint32_t)DCMI_CR_CM)  /*!< Once activated, the interface waits for the start of 
+                                                                    frame and then transfers a single frame through the DMA */
+
+#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
+                                   ((MODE) == DCMI_MODE_SNAPSHOT))
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Synchronization_Mode
+  * @{
+  */ 
+#define DCMI_SYNCHRO_HARDWARE        ((uint32_t)0x00000000)   /*!< Hardware synchronization data capture (frame/line start/stop)
+                                                                   is synchronized with the HSYNC/VSYNC signals                  */
+#define DCMI_SYNCHRO_EMBEDDED        ((uint32_t)DCMI_CR_ESS)  /*!< Embedded synchronization data capture is synchronized with 
+                                                                   synchronization codes embedded in the data flow               */
+
+#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
+                              ((MODE) == DCMI_SYNCHRO_EMBEDDED))
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_PIXCK_Polarity
+  * @{
+  */
+#define DCMI_PCKPOLARITY_FALLING    ((uint32_t)0x00000000)      /*!< Pixel clock active on Falling edge */
+#define DCMI_PCKPOLARITY_RISING     ((uint32_t)DCMI_CR_PCKPOL)  /*!< Pixel clock active on Rising edge  */
+
+#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
+                                      ((POLARITY) == DCMI_PCKPOLARITY_RISING))
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_VSYNC_Polarity
+  * @{
+  */
+#define DCMI_VSPOLARITY_LOW     ((uint32_t)0x00000000)     /*!< Vertical synchronization active Low  */
+#define DCMI_VSPOLARITY_HIGH    ((uint32_t)DCMI_CR_VSPOL)  /*!< Vertical synchronization active High */
+
+#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
+                                     ((POLARITY) == DCMI_VSPOLARITY_HIGH))
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_HSYNC_Polarity
+  * @{
+  */ 
+#define DCMI_HSPOLARITY_LOW     ((uint32_t)0x00000000)     /*!< Horizontal synchronization active Low  */
+#define DCMI_HSPOLARITY_HIGH    ((uint32_t)DCMI_CR_HSPOL)  /*!< Horizontal synchronization active High */
+
+#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
+                                     ((POLARITY) == DCMI_HSPOLARITY_HIGH))
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_MODE_JPEG 
+  * @{
+  */
+#define DCMI_JPEG_DISABLE   ((uint32_t)0x00000000)    /*!< Mode JPEG Disabled  */
+#define DCMI_JPEG_ENABLE    ((uint32_t)DCMI_CR_JPEG)  /*!< Mode JPEG Enabled   */
+
+#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
+                                     ((JPEG_MODE) == DCMI_JPEG_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Capture_Rate 
+  * @{
+  */
+#define DCMI_CR_ALL_FRAME            ((uint32_t)0x00000000)      /*!< All frames are captured        */
+#define DCMI_CR_ALTERNATE_2_FRAME    ((uint32_t)DCMI_CR_FCRC_0)  /*!< Every alternate frame captured */
+#define DCMI_CR_ALTERNATE_4_FRAME    ((uint32_t)DCMI_CR_FCRC_1)  /*!< One frame in 4 frames captured */
+
+#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME)         || \
+                                    ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
+                                    ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Extended_Data_Mode 
+  * @{
+  */
+#define DCMI_EXTEND_DATA_8B     ((uint32_t)0x00000000)                       /*!< Interface captures 8-bit data on every pixel clock  */
+#define DCMI_EXTEND_DATA_10B    ((uint32_t)DCMI_CR_EDM_0)                    /*!< Interface captures 10-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_12B    ((uint32_t)DCMI_CR_EDM_1)                    /*!< Interface captures 12-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_14B    ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))  /*!< Interface captures 14-bit data on every pixel clock */
+
+#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B)  || \
+                                    ((DATA) == DCMI_EXTEND_DATA_10B) || \
+                                    ((DATA) == DCMI_EXTEND_DATA_12B) || \
+                                    ((DATA) == DCMI_EXTEND_DATA_14B))
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Window_Coordinate 
+  * @{
+  */
+#define DCMI_WINDOW_COORDINATE    ((uint32_t)0x3FFF)  /*!< Window coordinate */
+
+#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Window_Height 
+  * @{
+  */ 
+#define DCMI_WINDOW_HEIGHT    ((uint32_t)0x1FFF)  /*!< Window Height */
+
+#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_interrupt_sources
+  * @{
+  */
+#define DCMI_IT_FRAME    ((uint32_t)DCMI_IER_FRAME_IE)
+#define DCMI_IT_OVF      ((uint32_t)DCMI_IER_OVF_IE)
+#define DCMI_IT_ERR      ((uint32_t)DCMI_IER_ERR_IE)
+#define DCMI_IT_VSYNC    ((uint32_t)DCMI_IER_VSYNC_IE)
+#define DCMI_IT_LINE     ((uint32_t)DCMI_IER_LINE_IE)
+
+#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \
+                            ((IT) == DCMI_IT_OVF)   || \
+                            ((IT) == DCMI_IT_ERR)   || \
+                            ((IT) == DCMI_IT_VSYNC) || \
+                            ((IT) == DCMI_IT_LINE))
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Flags
+  * @{
+  */
+
+/** 
+  * @brief   DCMI SR register
+  */ 
+#define DCMI_FLAG_HSYNC     ((uint32_t)0x2001)
+#define DCMI_FLAG_VSYNC     ((uint32_t)0x2002)
+#define DCMI_FLAG_FNE       ((uint32_t)0x2004)
+/** 
+  * @brief   DCMI RISR register  
+  */ 
+#define DCMI_FLAG_FRAMERI    ((uint32_t)DCMI_RISR_FRAME_RIS)
+#define DCMI_FLAG_OVFRI      ((uint32_t)DCMI_RISR_OVF_RIS)
+#define DCMI_FLAG_ERRRI      ((uint32_t)DCMI_RISR_ERR_RIS)
+#define DCMI_FLAG_VSYNCRI    ((uint32_t)DCMI_RISR_VSYNC_RIS)
+#define DCMI_FLAG_LINERI     ((uint32_t)DCMI_RISR_LINE_RIS)
+/** 
+  * @brief   DCMI MISR register  
+  */ 
+#define DCMI_FLAG_FRAMEMI    ((uint32_t)0x1001)
+#define DCMI_FLAG_OVFMI      ((uint32_t)0x1002)
+#define DCMI_FLAG_ERRMI      ((uint32_t)0x1004)
+#define DCMI_FLAG_VSYNCMI    ((uint32_t)0x1008)
+#define DCMI_FLAG_LINEMI     ((uint32_t)0x1010)
+#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC)   || \
+                                ((FLAG) == DCMI_FLAG_VSYNC)   || \
+                                ((FLAG) == DCMI_FLAG_FNE)     || \
+                                ((FLAG) == DCMI_FLAG_FRAMERI) || \
+                                ((FLAG) == DCMI_FLAG_OVFRI)   || \
+                                ((FLAG) == DCMI_FLAG_ERRRI)   || \
+                                ((FLAG) == DCMI_FLAG_VSYNCRI) || \
+                                ((FLAG) == DCMI_FLAG_LINERI)  || \
+                                ((FLAG) == DCMI_FLAG_FRAMEMI) || \
+                                ((FLAG) == DCMI_FLAG_OVFMI)   || \
+                                ((FLAG) == DCMI_FLAG_ERRMI)   || \
+                                ((FLAG) == DCMI_FLAG_VSYNCMI) || \
+                                ((FLAG) == DCMI_FLAG_LINEMI))
+                                
+#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset DCMI handle state
+  * @param  __HANDLE__: specifies the DCMI handle.
+  * @retval None
+  */
+#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
+
+/**
+  * @brief  Enable the DCMI.
+  * @param  __HANDLE__: DCMI handle
+  * @retval None
+  */
+#define __HAL_DCMI_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
+
+/**
+  * @brief  Disable the DCMI.
+  * @param  __HANDLE__: DCMI handle
+  * @retval None
+  */
+#define __HAL_DCMI_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
+
+/* Interrupt & Flag management */
+/**
+  * @brief  Get the DCMI pending flags.
+  * @param  __HANDLE__: DCMI handle
+  * @param  __FLAG__: Get the specified flag.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
+  *            @arg DCMI_FLAG_OVFRI: Overflow flag mask
+  *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
+  *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
+  *            @arg DCMI_FLAG_LINERI: Line flag mask
+  * @retval The state of FLAG.
+  */
+#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
+((((__FLAG__) & 0x3000) == 0x0)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\
+ (((__FLAG__) & 0x2000) == 0x0)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
+
+/**
+  * @brief  Clear the DCMI pending flags.
+  * @param  __HANDLE__: DCMI handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
+  *            @arg DCMI_FLAG_OVFRI: Overflow flag mask
+  *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
+  *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
+  *            @arg DCMI_FLAG_LINERI: Line flag mask
+  * @retval None
+  */
+#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR |= (__FLAG__))
+
+/**
+  * @brief  Enable the specified DCMI interrupts.
+  * @param  __HANDLE__:    DCMI handle
+  * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. 
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+  *            @arg DCMI_IT_OVF: Overflow interrupt mask
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+  *            @arg DCMI_IT_LINE: Line interrupt mask
+  * @retval None
+  */
+#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified DCMI interrupts.
+  * @param  __HANDLE__: DCMI handle
+  * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. 
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+  *            @arg DCMI_IT_OVF: Overflow interrupt mask
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+  *            @arg DCMI_IT_LINE: Line interrupt mask
+  * @retval None
+  */
+#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified DCMI interrupt has occurred or not.
+  * @param  __HANDLE__: DCMI handle
+  * @param  __INTERRUPT__: specifies the DCMI interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+  *            @arg DCMI_IT_OVF: Overflow interrupt mask
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+  *            @arg DCMI_IT_LINE: Line interrupt mask
+  * @retval The state of INTERRUPT.
+  */
+#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
+    
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
+void       HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
+void       HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
+void       HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
+void       HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
+void       HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
+void       HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
+void              HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
+
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef     HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
+HAL_StatusTypeDef     HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef     HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi);
+
+/* Peripheral State functions *************************************************/
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
+uint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DCMI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_def.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,149 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_def.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   This file contains HAL common defines, enumeration, macros and 
+  *          structures definitions. 
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DEF
+#define __STM32F4xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  HAL Status structures definition  
+  */  
+typedef enum 
+{
+  HAL_OK       = 0x00,
+  HAL_ERROR    = 0x01,
+  HAL_BUSY     = 0x02,
+  HAL_TIMEOUT  = 0x03
+} HAL_StatusTypeDef;
+
+/** 
+  * @brief  HAL Lock structures definition  
+  */
+typedef enum 
+{
+  HAL_UNLOCKED = 0x00,
+  HAL_LOCKED   = 0x01  
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+#ifndef NULL
+  #define NULL      (void *) 0
+#endif
+
+#define HAL_MAX_DELAY      0xFFFFFFFF
+
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) != RESET)
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == RESET)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \
+                        do{                                                      \
+                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \
+                          } while(0)
+
+#if (USE_RTOS == 1)
+  /* Reserved for future use */
+#else
+  #define __HAL_LOCK(__HANDLE__)                                           \
+                                do{                                        \
+                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
+                                    {                                      \
+                                       return HAL_BUSY;                    \
+                                    }                                      \
+                                    else                                   \
+                                    {                                      \
+                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
+                                    }                                      \
+                                  }while (0)
+
+  #define __HAL_UNLOCK(__HANDLE__)                                          \
+                                  do{                                       \
+                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
+                                    }while (0)
+#endif /* USE_RTOS */
+
+#if  defined ( __GNUC__ )
+  #ifndef __weak
+    #define __weak   __attribute__((weak))
+  #endif /* __weak */
+  #ifndef __packed
+    #define __packed __attribute__((__packed__))
+  #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined   (__GNUC__)        /* GNU Compiler */
+  #ifndef __ALIGN_END
+    #define __ALIGN_END    __attribute__ ((aligned (4)))
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN  
+    #define __ALIGN_BEGIN
+  #endif /* __ALIGN_BEGIN */
+#else
+  #ifndef __ALIGN_END
+    #define __ALIGN_END
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN      
+    #if defined   (__CC_ARM)      /* ARM Compiler */
+      #define __ALIGN_BEGIN    __align(4)  
+    #elif defined (__ICCARM__)    /* IAR Compiler */
+      #define __ALIGN_BEGIN 
+    #elif defined  (__TASKING__)  /* TASKING Compiler */
+      #define __ALIGN_BEGIN    __align(4) 
+    #endif /* __CC_ARM */
+  #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32F4xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,889 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dma.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   DMA HAL module driver.
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Direct Memory Access (DMA) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and errors functions
+  @verbatim     
+  ==============================================================================      
+                        ##### How to use this driver #####
+  ============================================================================== 
+  [..]
+   (#) Enable and configure the peripheral to be connected to the DMA Stream
+       (except for internal SRAM/FLASH memories: no initialization is 
+       necessary) please refer to Reference manual for connection between peripherals
+       and DMA requests . 
+          
+   (#) For a given Stream, program the required configuration through the following parameters:   
+       Transfer Direction, Source and Destination data formats, 
+       Circular, Normal or peripheral flow control mode, Stream Priority level, 
+       Source and Destination Increment mode, FIFO mode and its Threshold (if needed), 
+       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
+                     
+     *** Polling mode IO operation ***
+     =================================   
+    [..] 
+          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source 
+              address and destination address and the Length of data to be transferred
+          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this  
+              case a fixed Timeout can be configured by User depending from his application.
+               
+     *** Interrupt mode IO operation ***    
+     =================================== 
+    [..]     
+          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() 
+          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of  
+              Source address and destination address and the Length of data to be transferred. In this 
+              case the DMA interrupt is configured 
+          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can 
+              add his own function by customization of function pointer XferCpltCallback and 
+              XferErrorCallback (i.e a member of DMA handle structure). 
+    [..]                
+     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error 
+         detection.
+         
+     (#) Use HAL_DMA_Abort() function to abort the current transfer
+     
+     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
+    
+     -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
+           possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
+           Half-Word data size for the peripheral to access its data register and set Word data size
+           for the Memory to gain in access time. Each two half words will be packed and written in
+           a single access to a Word in the Memory).
+      
+     -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
+           and Destination. In this case the Peripheral Data Size will be applied to both Source
+           and Destination.               
+  
+     *** DMA HAL driver macros list ***
+     ============================================= 
+     [..]
+       Below the list of most used macros in DMA HAL driver.
+       
+      (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
+      (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
+      (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
+      (+) __HAL_DMA_GET_FLAG: Get the DMA Stream pending flags.
+      (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Stream pending flags.
+      (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
+      (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
+      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. 
+     
+     [..] 
+      (@) You can refer to the DMA HAL driver header file for more useful macros  
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMA 
+  * @brief DMA HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define HAL_TIMEOUT_DMA_ABORT    ((uint32_t)1000)  /* 1s  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DMA_Private_Functions
+  * @{
+  */
+
+/** @defgroup DMA_Group1 Initialization and de-initialization functions 
+ *  @brief   Initialization and de-initialization functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### Initialization and de-initialization functions  #####
+ ===============================================================================  
+    [..]
+    This section provides functions allowing to initialize the DMA Stream source
+    and destination addresses, incrementation and data sizes, transfer direction, 
+    circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
+    [..]
+    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+    reference manual.  
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initializes the DMA according to the specified
+  *         parameters in the DMA_InitTypeDef and create the associated handle.
+  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{ 
+  uint32_t tmp = 0;
+  
+  /* Check the DMA peripheral state */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
+  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+  assert_param(IS_DMA_MODE(hdma->Init.Mode));
+  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+  assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
+  /* Check the memory burst, peripheral burst and FIFO threshold parameters only
+     when FIFO mode is enabled */
+  if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
+  {
+    assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
+    assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
+    assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
+  }
+
+  /* Change DMA peripheral state */
+  hdma->State = HAL_DMA_STATE_BUSY;
+
+  /* Get the CR register value */
+  tmp = hdma->Instance->CR;
+
+  /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and CT bits */
+  tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
+                      DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
+                      DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
+                      DMA_SxCR_DIR   | DMA_SxCR_CT  ));
+
+  /* Prepare the DMA Stream configuration */
+  tmp |=  hdma->Init.Channel             | hdma->Init.Direction        |
+          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+          hdma->Init.Mode                | hdma->Init.Priority;
+
+  /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
+  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+  {
+    /* Get memory burst and peripheral burst */
+    tmp |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
+  }
+  
+  /* Write to DMA Stream CR register */
+  hdma->Instance->CR = tmp;  
+
+  /* Get the FCR register value */
+  tmp = hdma->Instance->FCR;
+
+  /* Clear Direct mode and FIFO threshold bits */
+  tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
+
+  /* Prepare the DMA Stream FIFO configuration */
+  tmp |= hdma->Init.FIFOMode;
+
+  /* the FIFO threshold is not used when the FIFO mode is disabled */
+  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+  {
+    /* Get the FIFO threshold */
+    tmp |= hdma->Init.FIFOThreshold;
+  }
+  
+  /* Write to DMA Stream FCR */
+  hdma->Instance->FCR = tmp;
+
+  /* Initialise the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Initialize the DMA state */
+  hdma->State = HAL_DMA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the DMA peripheral 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+  /* Check the DMA peripheral state */
+  if(hdma->State == HAL_DMA_STATE_BUSY)
+  {
+     return HAL_ERROR;
+  }
+
+  /* Disable the selected DMA Streamx */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Reset DMA Streamx control register */
+  hdma->Instance->CR   = 0;
+
+  /* Reset DMA Streamx number of data to transfer register */
+  hdma->Instance->NDTR = 0;
+
+  /* Reset DMA Streamx peripheral address register */
+  hdma->Instance->PAR  = 0;
+
+  /* Reset DMA Streamx memory 0 address register */
+  hdma->Instance->M0AR = 0;
+
+  /* Reset DMA Streamx memory 1 address register */
+  hdma->Instance->M1AR = 0;
+
+  /* Reset DMA Streamx FIFO control register */
+  hdma->Instance->FCR  = (uint32_t)0x00000021;
+
+  /* Clear all flags */
+  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+  /* Initialise the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Initialize the DMA state */
+  hdma->State = HAL_DMA_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Group2 I/O operation functions 
+ *  @brief   I/O operation functions  
+ *
+@verbatim   
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and Start DMA transfer
+      (+) Configure the source, destination address and data length and 
+          Start DMA transfer with interrupt
+      (+) Abort DMA transfer
+      (+) Poll for transfer complete
+      (+) Handle DMA interrupt request  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the DMA Transfer.
+  * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  /* Change DMA peripheral state */
+  hdma->State = HAL_DMA_STATE_BUSY;
+
+   /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Disable the peripheral */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Configure the source, destination address and the data length */
+  DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+  /* Enable the Peripheral */
+  __HAL_DMA_ENABLE(hdma);
+
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Start the DMA Transfer with interrupt enabled.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  /* Change DMA peripheral state */
+  hdma->State = HAL_DMA_STATE_BUSY;
+
+   /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Disable the peripheral */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Configure the source, destination address and the data length */
+  DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+  /* Enable the transfer complete interrupt */
+  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
+
+  /* Enable the Half transfer complete interrupt */
+  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);  
+
+  /* Enable the transfer Error interrupt */
+  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
+
+  /* Enable the FIFO Error interrupt */
+  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE);
+
+  /* Enable the direct mode Error interrupt */
+  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME);
+
+   /* Enable the Peripheral */
+  __HAL_DMA_ENABLE(hdma);
+
+  return HAL_OK;
+} 
+
+/**
+  * @brief  Aborts the DMA Transfer.
+  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Stream.
+  *                   
+  * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is 
+  *        effectively disabled is added. If a Stream is disabled 
+  *        while a data transfer is ongoing, the current data will be transferred
+  *        and the Stream will be effectively disabled only after the transfer of
+  *        this single data is finished.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+  uint32_t timeout = 0x00;
+
+  /* Disable the stream */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Get timeout */
+  timeout = HAL_GetTick() + HAL_TIMEOUT_DMA_ABORT;
+
+  /* Check if the DMA Stream is effectively disabled */
+  while((hdma->Instance->CR & DMA_SxCR_EN) != 0)
+  {
+    /* Check for the Timeout */
+    if(HAL_GetTick() >= timeout)
+    {
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
+      
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+      
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_TIMEOUT;
+      
+      return HAL_TIMEOUT;
+    }
+  }
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma);
+
+  /* Change the DMA state*/
+  hdma->State = HAL_DMA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Polling for transfer complete.
+  * @param  hdma:          pointer to a DMA_HandleTypeDef structure that contains
+  *                        the configuration information for the specified DMA Stream.
+  * @param  CompleteLevel: Specifies the DMA level complete.  
+  * @param  Timeout:       Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
+{
+  uint32_t temp, tmp, tmp1, tmp2;
+  uint32_t timeout = 0x00; 
+
+  /* Get the level transfer complete flag */
+  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+  {
+    /* Transfer Complete flag */
+    temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
+  }
+  else
+  {
+    /* Half Transfer Complete flag */
+    temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
+  }
+
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+
+  while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
+  {
+    tmp  = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+    tmp1 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+    tmp2 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+    if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET))
+    {
+      /* Clear the transfer error flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+      /* Clear the FIFO error flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+      /* Clear the DIrect Mode error flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+
+      /* Change the DMA state */
+      hdma->State= HAL_DMA_STATE_ERROR;
+      
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      return HAL_ERROR;
+    }  
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_TIMEOUT;
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /* Clear the half transfer complete flag */
+  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+  /* Change DMA peripheral state */
+  hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
+
+  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+  {
+    /* Multi_Buffering mode enabled */
+    if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
+    {
+      /* Clear the transfer complete flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+
+      /* Current memory buffer used is Memory 0 */
+      if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
+      {
+        /* Change DMA peripheral state */
+        hdma->State = HAL_DMA_STATE_READY_MEM0;
+      }
+      /* Current memory buffer used is Memory 1 */
+      else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
+      {
+        /* Change DMA peripheral state */
+        hdma->State = HAL_DMA_STATE_READY_MEM1;
+      }
+    }
+    else
+    {
+      /* Clear the transfer complete flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); 
+
+      /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers
+         are complete) */
+      hdma->State = HAL_DMA_STATE_READY_MEM0;
+    }
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+  }
+  else
+  { 
+    /* Multi_Buffering mode enabled */
+    if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
+    {
+      /* Clear the half transfer complete flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+      /* Current memory buffer used is Memory 0 */
+      if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
+      {
+        /* Change DMA peripheral state */
+        hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
+      }
+      /* Current memory buffer used is Memory 1 */
+      else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
+      {
+        /* Change DMA peripheral state */
+        hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
+      }
+    }
+    else
+    {
+      /* Clear the half transfer complete flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+      /* Change DMA peripheral state */
+      hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handles DMA interrupt request.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.  
+  * @retval None
+  */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+  /* Transfer Error Interrupt management ***************************************/
+  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
+    {
+      /* Disable the transfer error interrupt */
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
+
+      /* Clear the transfer error flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma); 
+
+      if(hdma->XferErrorCallback != NULL)
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+      }
+    }
+  }
+  /* FIFO Error Interrupt management ******************************************/
+  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
+    {
+      /* Disable the FIFO Error interrupt */
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE);
+
+      /* Clear the FIFO error flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      if(hdma->XferErrorCallback != NULL)
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+      }
+    }
+  }
+  /* Direct Mode Error Interrupt management ***********************************/
+  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
+    {
+      /* Disable the direct mode Error interrupt */
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME);
+
+      /* Clear the direct mode error flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      if(hdma->XferErrorCallback != NULL)
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+      }
+    }
+  }
+  /* Half Transfer Complete Interrupt management ******************************/
+  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
+    { 
+      /* Multi_Buffering mode enabled */
+      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
+      {
+        /* Clear the half transfer complete flag */
+        __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+        /* Current memory buffer used is Memory 0 */
+        if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
+        {
+          /* Change DMA peripheral state */
+          hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
+        }
+        /* Current memory buffer used is Memory 1 */
+        else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
+        {
+          /* Change DMA peripheral state */
+          hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
+        }
+      }
+      else
+      {
+        /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+        if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+        {
+          /* Disable the half transfer interrupt */
+          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+        }
+        /* Clear the half transfer complete flag */
+        __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+        /* Change DMA peripheral state */
+        hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
+      }
+
+      if(hdma->XferHalfCpltCallback != NULL)
+      {
+        /* Half transfer callback */
+        hdma->XferHalfCpltCallback(hdma);
+      }
+    }
+  }
+  /* Transfer Complete Interrupt management ***********************************/
+  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
+    {
+      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
+      {
+        /* Clear the transfer complete flag */
+        __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+
+        /* Current memory buffer used is Memory 1 */
+        if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
+        {
+          if(hdma->XferM1CpltCallback != NULL)
+          {
+            /* Transfer complete Callback for memory1 */
+            hdma->XferM1CpltCallback(hdma);
+          }
+        }
+        /* Current memory buffer used is Memory 0 */
+        else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) 
+        {
+          if(hdma->XferCpltCallback != NULL)
+          {
+            /* Transfer complete Callback for memory0 */
+            hdma->XferCpltCallback(hdma);
+          }
+        }
+      }
+      /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
+      else
+      {
+        if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+        {
+          /* Disable the transfer complete interrupt */
+          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
+        }
+        /* Clear the transfer complete flag */
+        __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY_MEM0;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);      
+
+        if(hdma->XferCpltCallback != NULL)
+        {
+          /* Transfer complete callback */
+          hdma->XferCpltCallback(hdma);
+        }
+      }
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Group3 Peripheral State functions
+ *  @brief    Peripheral State functions 
+ *
+@verbatim
+ ===============================================================================
+                    ##### State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DMA state
+      (+) Get error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the DMA state.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL state
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+  return hdma->State;
+}
+
+/**
+  * @brief  Return the DMA error code
+  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA Stream.
+  * @retval DMA Error Code
+  */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+  return hdma->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Sets the DMA Transfer parameter.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  /* Configure DMA Stream data length */
+  hdma->Instance->NDTR = DataLength;
+
+  /* Peripheral to Memory */
+  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+  {
+    /* Configure DMA Stream destination address */
+    hdma->Instance->PAR = DstAddress;
+
+    /* Configure DMA Stream source address */
+    hdma->Instance->M0AR = SrcAddress;
+  }
+  /* Memory to Peripheral */
+  else
+  {
+    /* Configure DMA Stream source address */
+    hdma->Instance->PAR = SrcAddress;
+    
+    /* Configure DMA Stream destination address */
+    hdma->Instance->M0AR = DstAddress;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,698 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dma.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DMA_H
+#define __STM32F4xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  DMA Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Channel;              /*!< Specifies the channel used for the specified stream. 
+                                      This parameter can be a value of @ref DMA_Channel_selection                    */
+
+  uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral, 
+                                      from memory to memory or from peripheral to memory.
+                                      This parameter can be a value of @ref DMA_Data_transfer_direction              */
+
+  uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
+                                      This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
+
+  uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
+                                      This parameter can be a value of @ref DMA_Memory_incremented_mode              */
+
+  uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
+                                      This parameter can be a value of @ref DMA_Peripheral_data_size                 */
+
+  uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
+                                      This parameter can be a value of @ref DMA_Memory_data_size                     */
+
+  uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
+                                      This parameter can be a value of @ref DMA_mode
+                                      @note The circular buffer mode cannot be used if the memory-to-memory
+                                            data transfer is configured on the selected Stream                        */
+
+  uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
+                                      This parameter can be a value of @ref DMA_Priority_level                       */
+
+  uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+                                      This parameter can be a value of @ref DMA_FIFO_direct_mode
+                                      @note The Direct mode (FIFO mode disabled) cannot be used if the 
+                                            memory-to-memory data transfer is configured on the selected stream       */
+
+  uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
+                                      This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
+
+  uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers. 
+                                      It specifies the amount of data to be transferred in a single non interruptable 
+                                      transaction.
+                                      This parameter can be a value of @ref DMA_Memory_burst 
+                                      @note The burst mode is possible only if the address Increment mode is enabled. */
+
+  uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers. 
+                                      It specifies the amount of data to be transferred in a single non interruptable 
+                                      transaction. 
+                                      This parameter can be a value of @ref DMA_Peripheral_burst
+                                      @note The burst mode is possible only if the address Increment mode is enabled. */
+}DMA_InitTypeDef;
+
+/** 
+  * @brief  HAL DMA State structures definition
+  */
+typedef enum
+{
+  HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled */
+  HAL_DMA_STATE_READY             = 0x01,  /*!< DMA initialized and ready for use   */
+  HAL_DMA_STATE_READY_MEM0        = 0x11,  /*!< DMA Mem0 process success            */
+  HAL_DMA_STATE_READY_MEM1        = 0x21,  /*!< DMA Mem1 process success            */
+  HAL_DMA_STATE_READY_HALF_MEM0   = 0x31,  /*!< DMA Mem0 Half process success       */
+  HAL_DMA_STATE_READY_HALF_MEM1   = 0x41,  /*!< DMA Mem1 Half process success       */
+  HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing              */
+  HAL_DMA_STATE_BUSY_MEM0         = 0x12,  /*!< DMA Mem0 process is ongoing         */
+  HAL_DMA_STATE_BUSY_MEM1         = 0x22,  /*!< DMA Mem1 process is ongoing         */
+  HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                   */
+  HAL_DMA_STATE_ERROR             = 0x04,  /*!< DMA error state                     */
+}HAL_DMA_StateTypeDef;
+
+/** 
+  * @brief  HAL DMA Error Code structure definition
+  */
+typedef enum
+{
+  HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER      = 0x01,    /*!< Half Transfer     */
+}HAL_DMA_LevelCompleteTypeDef;
+
+/** 
+  * @brief  DMA handle Structure definition
+  */
+typedef struct __DMA_HandleTypeDef
+{
+  DMA_Stream_TypeDef         *Instance;                                                    /*!< Register base address                  */
+
+  DMA_InitTypeDef            Init;                                                         /*!< DMA communication parameters           */ 
+
+  HAL_LockTypeDef            Lock;                                                         /*!< DMA locking object                     */  
+
+  __IO HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
+
+  void                       *Parent;                                                      /*!< Parent object state                    */  
+
+  void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
+
+  void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
+
+  void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer complete Memory1 callback */
+
+  void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
+
+  __IO uint32_t              ErrorCode;                                                    /*!< DMA Error code                         */
+}DMA_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants
+  * @{
+  */
+
+/** @defgroup DMA_Error_Code 
+  * @{
+  */ 
+#define HAL_DMA_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error             */
+#define HAL_DMA_ERROR_TE        ((uint32_t)0x00000001)    /*!< Transfer error       */
+#define HAL_DMA_ERROR_FE        ((uint32_t)0x00000002)    /*!< FIFO error           */
+#define HAL_DMA_ERROR_DME       ((uint32_t)0x00000004)    /*!< Direct Mode error    */
+#define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error        */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Channel_selection 
+  * @{
+  */ 
+#define DMA_CHANNEL_0        ((uint32_t)0x00000000)  /*!< DMA Channel 0 */
+#define DMA_CHANNEL_1        ((uint32_t)0x02000000)  /*!< DMA Channel 1 */
+#define DMA_CHANNEL_2        ((uint32_t)0x04000000)  /*!< DMA Channel 2 */
+#define DMA_CHANNEL_3        ((uint32_t)0x06000000)  /*!< DMA Channel 3 */
+#define DMA_CHANNEL_4        ((uint32_t)0x08000000)  /*!< DMA Channel 4 */
+#define DMA_CHANNEL_5        ((uint32_t)0x0A000000)  /*!< DMA Channel 5 */
+#define DMA_CHANNEL_6        ((uint32_t)0x0C000000)  /*!< DMA Channel 6 */
+#define DMA_CHANNEL_7        ((uint32_t)0x0E000000)  /*!< DMA Channel 7 */
+
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
+                                 ((CHANNEL) == DMA_CHANNEL_1) || \
+                                 ((CHANNEL) == DMA_CHANNEL_2) || \
+                                 ((CHANNEL) == DMA_CHANNEL_3) || \
+                                 ((CHANNEL) == DMA_CHANNEL_4) || \
+                                 ((CHANNEL) == DMA_CHANNEL_5) || \
+                                 ((CHANNEL) == DMA_CHANNEL_6) || \
+                                 ((CHANNEL) == DMA_CHANNEL_7))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Data_transfer_direction 
+  * @{
+  */ 
+#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)      /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 
+/**
+  * @}
+  */
+    
+/** @defgroup DMA_Data_buffer_size 
+  * @{
+  */ 
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+/**
+  * @}
+  */     
+        
+/** @defgroup DMA_Peripheral_incremented_mode 
+  * @{
+  */ 
+#define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */
+#define DMA_PINC_DISABLE       ((uint32_t)0x00000000)     /*!< Peripheral increment mode disable */
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+                                            ((STATE) == DMA_PINC_DISABLE))
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Memory_incremented_mode 
+  * @{
+  */ 
+#define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */
+#define DMA_MINC_DISABLE        ((uint32_t)0x00000000)     /*!< Memory increment mode disable */
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
+                                        ((STATE) == DMA_MINC_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_data_size 
+  * @{
+  */ 
+#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Peripheral data alignment: Byte     */
+#define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord */
+#define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word     */
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
+                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+                                           ((SIZE) == DMA_PDATAALIGN_WORD))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_Memory_data_size
+  * @{ 
+  */
+#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Memory data alignment: Byte     */
+#define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
+                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_mode 
+  * @{
+  */ 
+#define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal mode                  */
+#define DMA_CIRCULAR       ((uint32_t)DMA_SxCR_CIRC)    /*!< Circular mode                */
+#define DMA_PFCTRL         ((uint32_t)DMA_SxCR_PFCTRL)  /*!< Peripheral flow control mode */
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
+                           ((MODE) == DMA_CIRCULAR) || \
+                           ((MODE) == DMA_PFCTRL)) 
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Priority_level 
+  * @{
+  */
+#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)     /*!< Priority level: Low       */
+#define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */
+#define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */
+#define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
+                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
+                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_FIFO_direct_mode 
+  * @{
+  */
+#define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000)       /*!< FIFO mode disable */
+#define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */
+
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
+                                       ((STATE) == DMA_FIFOMODE_ENABLE)) 
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_FIFO_threshold_level 
+  * @{
+  */
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000)       /*!< FIFO threshold 1 quart full configuration  */
+#define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
+#define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
+
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) 
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Memory_burst 
+  * @{
+  */ 
+#define DMA_MBURST_SINGLE       ((uint32_t)0x00000000)  
+#define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)  
+#define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)  
+#define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)  
+
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
+                                    ((BURST) == DMA_MBURST_INC4)   || \
+                                    ((BURST) == DMA_MBURST_INC8)   || \
+                                    ((BURST) == DMA_MBURST_INC16))
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Peripheral_burst 
+  * @{
+  */ 
+#define DMA_PBURST_SINGLE       ((uint32_t)0x00000000)  
+#define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)  
+#define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)  
+#define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)  
+
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
+                                        ((BURST) == DMA_PBURST_INC4)   || \
+                                        ((BURST) == DMA_PBURST_INC8)   || \
+                                        ((BURST) == DMA_PBURST_INC16))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_interrupt_enable_definitions 
+  * @{
+  */
+#define DMA_IT_TC                         ((uint32_t)DMA_SxCR_TCIE)
+#define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)
+#define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)
+#define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)
+#define DMA_IT_FE                         ((uint32_t)0x00000080)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flag_definitions 
+  * @{
+  */ 
+#define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00800001)
+#define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00800004)
+#define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008)
+#define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010)
+#define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020)
+#define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040)
+#define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100)
+#define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200)
+#define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400)
+#define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800)
+#define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000)
+#define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000)
+#define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000)
+#define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000)
+#define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000)
+#define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000)
+#define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000)
+#define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000)
+#define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000)
+#define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000)
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset DMA handle state
+  * @param  __HANDLE__: specifies the DMA handle.
+  * @retval None
+  */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+  * @brief  Return the current DMA Stream FIFO filled level.
+  * @param  __HANDLE__: DMA handle
+  * @retval The FIFO filling state.
+  *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 
+  *                                              and not empty.
+  *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
+  *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
+  *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
+  *           - DMA_FIFOStatus_Empty: when FIFO is empty
+  *           - DMA_FIFOStatus_Full: when FIFO is full
+  */
+#define __HAL_DMA_GET_FS(__HANDLE__)      (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
+
+/**
+  * @brief  Enable the specified DMA Stream.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)
+
+/**
+  * @brief  Disable the specified DMA Stream.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)
+
+/* Interrupt & Flag management */
+
+/**
+  * @brief  Return the current DMA Stream transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer complete flag index.
+  */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
+   DMA_FLAG_TCIF3_7)
+
+/**
+  * @brief  Return the current DMA Stream half transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified half transfer complete flag index.
+  */      
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
+   DMA_FLAG_HTIF3_7)
+
+/**
+  * @brief  Return the current DMA Stream transfer error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
+   DMA_FLAG_TEIF3_7)
+
+/**
+  * @brief  Return the current DMA Stream FIFO error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified FIFO error flag index.
+  */
+#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
+   DMA_FLAG_FEIF3_7)
+
+/**
+  * @brief  Return the current DMA Stream direct mode error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified direct mode error flag index.
+  */
+#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
+   DMA_FLAG_DMEIF3_7)
+
+/**
+  * @brief  Get the DMA Stream pending flags.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
+  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
+  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
+
+/**
+  * @brief  Clear the DMA Stream pending flags.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
+  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
+  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   
+  * @retval None
+  */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR |= (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR |= (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR |= (__FLAG__)) : (DMA1->LIFCR |= (__FLAG__)))
+
+/**
+  * @brief  Enable the specified DMA Stream interrupts.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
+  *        This parameter can be any combination of the following values:
+  *           @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *           @arg DMA_IT_TE: Transfer error interrupt mask.
+  *           @arg DMA_IT_FE: FIFO error interrupt mask.
+  *           @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
+((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
+
+/**
+  * @brief  Disable the specified DMA Stream interrupts.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
+  *         This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *            @arg DMA_IT_TE: Transfer error interrupt mask.
+  *            @arg DMA_IT_FE: FIFO error interrupt mask.
+  *            @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
+((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
+
+/**
+  * @brief  Check whether the specified DMA Stream interrupt has occurred or not.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *            @arg DMA_IT_TE: Transfer error interrupt mask.
+  *            @arg DMA_IT_FE: FIFO error interrupt mask.
+  *            @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval The state of DMA_IT.
+  */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
+                                                        ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
+                                                        ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
+
+/**
+  * @brief  Writes the number of data units to be transferred on the DMA Stream.
+  * @param  __HANDLE__: DMA handle
+  * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535) 
+  *          Number of data items depends only on the Peripheral data format.
+  *            
+  * @note   If Peripheral data format is Bytes: number of data units is equal 
+  *         to total number of bytes to be transferred.
+  *           
+  * @note   If Peripheral data format is Half-Word: number of data units is  
+  *         equal to total number of bytes to be transferred / 2.
+  *           
+  * @note   If Peripheral data format is Word: number of data units is equal 
+  *         to total  number of bytes to be transferred / 4.
+  *      
+  * @retval The number of remaining data units in the current DMAy Streamx transfer.
+  */
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
+
+/**
+  * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
+  * @param  __HANDLE__: DMA handle
+  *   
+  * @retval The number of remaining data units in the current DMA Stream transfer.
+  */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
+
+
+/* Include DMA HAL Extension module */
+#include "stm32f4xx_hal_dma_ex.h"   
+
+/* Exported functions --------------------------------------------------------*/
+  
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
+void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+
+/* Peripheral State and Error functions ***************************************/
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1241 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dma2d.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   DMA2D HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the DMA2D peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State and Errors functions
+  *           
+  @verbatim                 
+  ============================================================================== 
+                        ##### How to use this driver #####
+  ============================================================================== 
+    [..]
+      (#) Program the required configuration through following parameters:   
+          the Transfer Mode, the output color mode and the output offset using 
+          HAL_DMA2D_Init() function.
+
+      (#) Program the required configuration through following parameters:   
+          the input color mode, the input color, input alpha value, alpha mode 
+          and the input offset using HAL_DMA2D_ConfigLayer() function for foreground
+          or/and background layer.
+          
+     *** Polling mode IO operation ***
+     =================================   
+    [..]        
+       (+) Configure the pdata, Destination and data length and Enable 
+           the transfer using HAL_DMA2D_Start() 
+       (+) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
+           user can specify the value of timeout according to his end application.
+               
+     *** Interrupt mode IO operation ***    
+     ===================================
+     [..] 
+       (#) Configure the pdata, Destination and data length and Enable 
+           the transfer using HAL_DMA2D_Start_IT() 
+       (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() Interrupt subroutine
+       (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can 
+           add his own function by customization of function pointer XferCpltCallback and 
+           XferErrorCallback (i.e a member of DMA2D handle structure). 
+
+         -@-   In Register-to-Memory transfer mode, the pdata parameter is the register
+               color, in Memory-to-memory or memory-to-memory with pixel format
+               conversion the pdata is the source address and it is the color value 
+               for the A4 or A8 mode.
+
+         -@-   Configure the foreground source address, the background source address, 
+               the Destination and data length and Enable the transfer using 
+               HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
+               in interrupt mode.
+               
+         -@-   HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
+               are used if the memory to memory with blending transfer mode is selected.
+                   
+      (#) Optionally, configure and enable the CLUT using HAL_DMA2D_ConfigCLUT()
+          HAL_DMA2D_EnableCLUT() functions.
+
+      (#) Optionally, configure and enable LineInterrupt using the following function:
+          HAL_DMA2D_ProgramLineEvent().
+   
+      (#) The transfer can be suspended, continued and aborted using the following
+          functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
+                     
+      (#) To control DMA2D state you can use the following function: HAL_DMA2D_GetState()                   
+
+     *** DMA2D HAL driver macros list ***
+     ============================================= 
+     [..]
+       Below the list of most used macros in DMA2D HAL driver :
+       
+      (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
+      (+) __HAL_DMA2D_DISABLE: Disable the DMA2D peripheral.
+      (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
+      (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
+      (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
+      (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
+      (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt has occurred or not.
+     
+     [..] 
+      (@) You can refer to the DMA2D HAL driver header file for more useful macros
+                                  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+/** @defgroup DMA2D 
+  * @brief DMA2D HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define HAL_TIMEOUT_DMA2D_ABORT      ((uint32_t)1000)  /* 1s  */
+#define HAL_TIMEOUT_DMA2D_SUSPEND    ((uint32_t)1000)  /* 1s  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DMA2D_Private_Functions
+  * @{
+  */
+
+/** @defgroup DMA2D_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions
+ *
+@verbatim   
+ ===============================================================================
+                ##### Initialization and Configuration functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the DMA2D
+      (+) De-initialize the DMA2D 
+
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Initializes the DMA2D according to the specified
+  *         parameters in the DMA2D_InitTypeDef and create the associated handle.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
+{ 
+  uint32_t tmp = 0;
+
+  /* Check the DMA2D peripheral state */
+  if(hdma2d == NULL)
+  {
+     return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
+  assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
+  assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
+  assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
+
+  if(hdma2d->State == HAL_DMA2D_STATE_RESET)
+  {
+    /* Init the low level hardware */
+    HAL_DMA2D_MspInit(hdma2d);
+  }
+  
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;  
+
+/* DMA2D CR register configuration -------------------------------------------*/
+  /* Get the CR register value */
+  tmp = hdma2d->Instance->CR;
+
+  /* Clear Mode bits */
+  tmp &= (uint32_t)~DMA2D_CR_MODE;
+
+  /* Prepare the value to be wrote to the CR register */
+  tmp |= hdma2d->Init.Mode;
+
+  /* Write to DMA2D CR register */
+  hdma2d->Instance->CR = tmp;
+
+/* DMA2D OPFCCR register configuration ---------------------------------------*/
+  /* Get the OPFCCR register value */
+  tmp = hdma2d->Instance->OPFCCR;
+
+  /* Clear Color Mode bits */
+  tmp &= (uint32_t)~DMA2D_OPFCCR_CM;
+
+  /* Prepare the value to be wrote to the OPFCCR register */
+  tmp |= hdma2d->Init.ColorMode;
+
+  /* Write to DMA2D OPFCCR register */
+  hdma2d->Instance->OPFCCR = tmp;
+
+/* DMA2D OOR register configuration ------------------------------------------*/  
+  /* Get the OOR register value */
+  tmp = hdma2d->Instance->OOR;
+
+  /* Clear Offset bits */
+  tmp &= (uint32_t)~DMA2D_OOR_LO;
+
+  /* Prepare the value to be wrote to the OOR register */
+  tmp |= hdma2d->Init.OutputOffset;
+
+  /* Write to DMA2D OOR register */
+  hdma2d->Instance->OOR = tmp;
+
+  /* Update error code */
+  hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
+
+  /* Initialize the DMA2D state*/
+  hdma2d->State  = HAL_DMA2D_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deinitializes the DMA2D peripheral registers to their default reset
+  *         values.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval None
+  */
+
+HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Check the DMA2D peripheral state */
+  if(hdma2d == NULL)
+  {
+     return HAL_ERROR;
+  }
+
+  /* DeInit the low level hardware */
+  HAL_DMA2D_MspDeInit(hdma2d);
+
+  /* Update error code */
+  hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
+
+  /* Initialize the DMA2D state*/
+  hdma2d->State  = HAL_DMA2D_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the DMA2D MSP.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval None
+  */
+__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DMA2D_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  DeInitializes the DMA2D MSP.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval None
+  */
+__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DMA2D_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Group2 IO operation functions 
+ *  @brief   IO operation functions  
+ *
+@verbatim   
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure the pdata, destination address and data size and 
+          Start DMA2D transfer.
+      (+) Configure the source for foreground and background, destination address 
+          and data size and Start MultiBuffer DMA2D transfer.
+      (+) Configure the pdata, destination address and data size and 
+          Start DMA2D transfer with interrupt.
+      (+) Configure the source for foreground and background, destination address 
+          and data size and Start MultiBuffer DMA2D transfer with interrupt.
+      (+) Abort DMA2D transfer.
+      (+) Suspend DMA2D transfer.
+      (+) Continue DMA2D transfer. 
+      (+) Poll for transfer complete.
+      (+) handle DMA2D interrupt request.
+        
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the DMA2D Transfer.
+  * @param  hdma2d:     pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the DMA2D.  
+  * @param  pdata:      Configure the source memory Buffer address if 
+  *                     the memory to memory or memory to memory with pixel format 
+  *                     conversion DMA2D mode is selected, and configure 
+  *                     the color value if register to memory DMA2D mode is selected
+  *                     or the color value for the A4 or A8 mode.
+  * @param  DstAddress: The destination memory Buffer address.
+  * @param  Width:      The width of data to be transferred from source to destination.
+  * @param  Heigh:      The heigh of data to be transferred from source to destination.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Heigh)
+{
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LINE(Heigh));
+  assert_param(IS_DMA2D_PIXEL(Width));
+
+  /* Disable the Peripheral */
+  __HAL_DMA2D_DISABLE(hdma2d);
+
+  /* Configure the source, destination address and the data size */
+  DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Heigh);
+
+  /* Enable the Peripheral */
+  __HAL_DMA2D_ENABLE(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the DMA2D Transfer with interrupt enabled.
+  * @param  hdma2d:     pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the DMA2D.  
+  * @param  pdata:      Configure the source memory Buffer address if 
+  *                     the memory to memory or memory to memory with pixel format 
+  *                     conversion DMA2D mode is selected, and configure 
+  *                     the color value if register to memory DMA2D mode is selected
+  *                     or the color value for the A4 or A8 mode.
+  * @param  DstAddress: The destination memory Buffer address.
+  * @param  Width:      The width of data to be transferred from source to destination.
+  * @param  Heigh:      The heigh of data to be transferred from source to destination.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Heigh)
+{
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LINE(Heigh));
+  assert_param(IS_DMA2D_PIXEL(Width));
+
+  /* Disable the Peripheral */
+  __HAL_DMA2D_DISABLE(hdma2d);
+
+  /* Configure the source, destination address and the data size */
+  DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Heigh);
+
+  /* Enable the transfer complete interrupt */
+  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC);
+
+  /* Enable the transfer Error interrupt */
+  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TE);
+
+  /* Enable the Peripheral */
+  __HAL_DMA2D_ENABLE(hdma2d);
+
+  /* Enable the configuration error interrupt */
+  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CE);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the multi-source DMA2D Transfer.
+  * @param  hdma2d:      pointer to a DMA2D_HandleTypeDef structure that contains
+  *                      the configuration information for the DMA2D.  
+  * @param  SrcAddress1: The source memory Buffer address of the foreground layer.
+  * @param  SrcAddress2: The source memory Buffer address of the background layer
+  *                      or the color value for the A4 or A8 mode.
+  * @param  DstAddress:  The destination memory Buffer address
+  * @param  Width:       The width of data to be transferred from source to destination.
+  * @param  Heigh:       The heigh of data to be transferred from source to destination.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Heigh)
+{
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY; 
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LINE(Heigh));
+  assert_param(IS_DMA2D_PIXEL(Width));
+
+  /* Disable the Peripheral */
+  __HAL_DMA2D_DISABLE(hdma2d);
+
+  if((hdma2d->LayerCfg[0].InputColorMode == CM_A4) || (hdma2d->LayerCfg[0].InputColorMode == CM_A8))
+  {
+    hdma2d->Instance->BGCOLR = SrcAddress2;
+  }
+  else
+  {
+  /* Configure DMA2D Stream source2 address */
+  hdma2d->Instance->BGMAR = SrcAddress2;
+  }
+
+  /* Configure the source, destination address and the data size */
+  DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Heigh);
+
+  /* Enable the Peripheral */
+  __HAL_DMA2D_ENABLE(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the multi-source DMA2D Transfer with interrupt enabled.
+  * @param  hdma2d:     pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the DMA2D.  
+  * @param  SrcAddress1: The source memory Buffer address of the foreground layer.
+  * @param  SrcAddress2: The source memory Buffer address of the background layer
+  *                      or the color value for the A4 or A8 mode.
+  * @param  DstAddress:  The destination memory Buffer address.
+  * @param  Width:       The width of data to be transferred from source to destination.
+  * @param  Heigh:       The heigh of data to be transferred from source to destination.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Heigh)
+{
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LINE(Heigh));
+  assert_param(IS_DMA2D_PIXEL(Width));
+
+  /* Disable the Peripheral */
+  __HAL_DMA2D_DISABLE(hdma2d);
+
+  if ((hdma2d->LayerCfg[0].InputColorMode == CM_A4) || (hdma2d->LayerCfg[0].InputColorMode == CM_A8))
+  {
+    hdma2d->Instance->BGCOLR = SrcAddress2;
+  }
+  else
+  {  
+    /* Configure DMA2D Stream source2 address */
+    hdma2d->Instance->BGMAR = SrcAddress2;
+  }
+
+  /* Configure the source, destination address and the data size */
+  DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Heigh);
+
+  /* Enable the configuration error interrupt */
+  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CE);
+
+  /* Enable the transfer complete interrupt */
+  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC);
+
+  /* Enable the transfer Error interrupt */
+  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TE);
+
+  /* Enable the Peripheral */
+  __HAL_DMA2D_ENABLE(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort the DMA2D Transfer.
+  * @param  hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
+  *                  the configuration information for the DMA2D.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
+{
+  uint32_t timeout = 0x00;
+
+  /* Disable the DMA2D */
+  __HAL_DMA2D_DISABLE(hdma2d);
+
+  /* Get timeout */
+  timeout = HAL_GetTick() + HAL_TIMEOUT_DMA2D_ABORT;
+
+  /* Check if the DMA2D is effectively disabled */
+  while((hdma2d->Instance->CR & DMA2D_CR_START) != 0)
+  {
+    if(HAL_GetTick() >= timeout)
+    {
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+      
+      /* Change the DMA2D state */
+      hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
+      
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);
+      
+      return HAL_TIMEOUT;
+    }
+  }
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  /* Change the DMA2D state*/
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Suspend the DMA2D Transfer.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D. 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
+{
+  uint32_t timeout = 0x00;
+
+  /* Suspend the DMA2D transfer */
+  hdma2d->Instance->CR |= DMA2D_CR_SUSP;
+
+  /* Get timeout */
+  timeout = HAL_GetTick() + HAL_TIMEOUT_DMA2D_SUSPEND;
+
+  /* Check if the DMA2D is effectively suspended */
+  while((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP)
+  {
+    if(HAL_GetTick() >= timeout)
+    {
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+      
+      /* Change the DMA2D state */
+      hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
+      
+      return HAL_TIMEOUT;
+    }
+  }
+  /* Change the DMA2D state*/
+  hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Resume the DMA2D Transfer.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Resume the DMA2D transfer */
+  hdma2d->Instance->CR &= ~DMA2D_CR_SUSP;
+
+  /* Change the DMA2D state*/
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Polling for transfer complete or CLUT loading.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D. 
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
+{
+  uint32_t tmp, tmp1;
+  uint32_t timeout = 0x00;
+
+  /* Polling for DMA2D transfer */
+  if((hdma2d->Instance->CR & DMA2D_CR_START) != 0)
+  {
+    /* Get timeout */
+    timeout = HAL_GetTick() + Timeout;
+
+    while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
+    {
+      tmp  = __HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE);
+      tmp1 = __HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE);
+
+      if((tmp != RESET) || (tmp1 != RESET))
+      {
+        /* Clear the transfer and configuration error flags */
+        __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
+        __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
+
+        /* Change DMA2D state */
+        hdma2d->State= HAL_DMA2D_STATE_ERROR;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hdma2d);
+        
+        return HAL_ERROR;
+      }
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Process unlocked */
+          __HAL_UNLOCK(hdma2d);
+        
+          /* Update error code */
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+          /* Change the DMA2D state */
+          hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
+          
+          return HAL_TIMEOUT;
+        }
+      }        
+    }
+  }
+  /* Polling for CLUT loading */
+  if((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != 0)
+  {
+    /* Get timeout */
+    timeout = HAL_GetTick() + Timeout;
+   
+    while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
+    {
+      if((__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CAE) != RESET))
+      {      
+        /* Clear the transfer and configuration error flags */
+        __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
+        
+        /* Change DMA2D state */
+        hdma2d->State= HAL_DMA2D_STATE_ERROR;
+        
+        return HAL_ERROR;      
+      }      
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Update error code */
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+    
+          /* Change the DMA2D state */
+          hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
+          
+          return HAL_TIMEOUT;
+        }
+      }      
+    }
+  }
+  /* Clear the transfer complete flag */
+  __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
+  
+  /* Clear the CLUT loading flag */
+  __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);  
+  
+  /* Change DMA2D state */
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdma2d);
+  
+  return HAL_OK;
+}
+/**
+  * @brief  Handles DMA2D interrupt request.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.  
+  * @retval HAL status
+  */
+void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
+{    
+  /* Transfer Error Interrupt management ***************************************/
+  if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE) != RESET)
+  {
+    if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TE) != RESET)
+    {
+      /* Disable the transfer Error interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);  
+
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
+    
+      /* Clear the transfer error flag */
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
+
+      /* Change DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);       
+      
+      if(hdma2d->XferErrorCallback != NULL)
+      {
+        /* Transfer error Callback */
+        hdma2d->XferErrorCallback(hdma2d);
+      }
+    }
+  }
+  /* Configuration Error Interrupt management **********************************/
+  if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE) != RESET)
+  {
+    if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_CE) != RESET)
+    {
+      /* Disable the Configuration Error interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
+  
+      /* Clear the Configuration error flag */
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
+
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;    
+    
+      /* Change DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);       
+      
+      if(hdma2d->XferErrorCallback != NULL)
+      {
+        /* Transfer error Callback */
+        hdma2d->XferErrorCallback(hdma2d);
+      }
+    }
+  }
+  /* Transfer Complete Interrupt management ************************************/
+  if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) != RESET)
+  {
+    if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TC) != RESET)
+    { 
+      /* Disable the transfer complete interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
+  
+      /* Clear the transfer complete flag */  
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
+
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;    
+    
+      /* Change DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_READY;
+    
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);       
+      
+      if(hdma2d->XferCpltCallback != NULL)
+      {
+        /* Transfer complete Callback */
+        hdma2d->XferCpltCallback(hdma2d);
+      }         
+    }
+  }
+} 
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Group3 Peripheral Control functions
+ *  @brief    Peripheral Control functions 
+ *
+@verbatim   
+ ===============================================================================
+                    ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure the DMA2D foreground or/and background parameters.
+      (+) Configure the DMA2D CLUT transfer.
+      (+) Enable DMA2D CLUT.
+      (+) Disable DMA2D CLUT.
+      (+) Configure the line watermark
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Configure the DMA2D Layer according to the specified
+  *         parameters in the DMA2D_InitTypeDef and create the associated handle.
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @param  LayerIdx: DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{ 
+  DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
+  
+  uint32_t tmp = 0;
+  
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+  
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY; 
+  
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));  
+  assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));  
+  if(hdma2d->Init.Mode != DMA2D_R2M)
+  {  
+    assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
+    if(hdma2d->Init.Mode != DMA2D_M2M)
+    {
+      assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
+      assert_param(IS_DMA2D_ALPHA_VALUE(pLayerCfg->InputAlpha));
+    }
+  }
+  
+  /* Configure the background DMA2D layer */
+  if(LayerIdx == 0)
+  {
+    /* DMA2D BGPFCR register configuration -----------------------------------*/
+    /* Get the BGPFCCR register value */
+    tmp = hdma2d->Instance->BGPFCCR;
+    
+    /* Clear Input color mode, alpha value and alpha mode bits */
+    tmp &= (uint32_t)~(DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA); 
+    
+    /* Prepare the value to be wrote to the BGPFCCR register */
+    tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24));
+    
+    /* Write to DMA2D BGPFCCR register */
+    hdma2d->Instance->BGPFCCR = tmp; 
+    
+    /* DMA2D BGOR register configuration -------------------------------------*/  
+    /* Get the BGOR register value */
+    tmp = hdma2d->Instance->BGOR;
+    
+    /* Clear colors bits */
+    tmp &= (uint32_t)~DMA2D_BGOR_LO; 
+    
+    /* Prepare the value to be wrote to the BGOR register */
+    tmp |= pLayerCfg->InputOffset;
+    
+    /* Write to DMA2D BGOR register */
+    hdma2d->Instance->BGOR = tmp;
+  }
+  /* Configure the foreground DMA2D layer */
+  else
+  {
+    /* DMA2D FGPFCR register configuration -----------------------------------*/
+    /* Get the FGPFCCR register value */
+    tmp = hdma2d->Instance->FGPFCCR;
+    
+    /* Clear Input color mode, alpha value and alpha mode bits */
+    tmp &= (uint32_t)~(DMA2D_FGPFCCR_CM | DMA2D_FGPFCCR_AM | DMA2D_FGPFCCR_ALPHA); 
+    
+    /* Prepare the value to be wrote to the FGPFCCR register */
+    tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24));
+    
+    /* Write to DMA2D FGPFCCR register */
+    hdma2d->Instance->FGPFCCR = tmp; 
+    
+    /* DMA2D FGOR register configuration -------------------------------------*/  
+    /* Get the FGOR register value */
+    tmp = hdma2d->Instance->FGOR;
+    
+    /* Clear colors bits */
+    tmp &= (uint32_t)~DMA2D_FGOR_LO; 
+    
+    /* Prepare the value to be wrote to the FGOR register */
+    tmp |= pLayerCfg->InputOffset;
+    
+    /* Write to DMA2D FGOR register */
+    hdma2d->Instance->FGOR = tmp;
+  }    
+  /* Initialize the DMA2D state*/
+  hdma2d->State  = HAL_DMA2D_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdma2d);  
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the DMA2D CLUT Transfer.
+  * @param  hdma2d:   pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  CLUTCfg:  pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+  *                   the configuration information for the color look up table.
+  * @param  LayerIdx: DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
+{
+  uint32_t tmp = 0, tmp1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));   
+  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
+  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
+  
+  /* Configure the CLUT of the background DMA2D layer */
+  if(LayerIdx == 0)
+  {
+    /* Get the BGCMAR register value */
+    tmp = hdma2d->Instance->BGCMAR;
+
+    /* Clear CLUT address bits */
+    tmp &= (uint32_t)~DMA2D_BGCMAR_MA; 
+  
+    /* Prepare the value to be wrote to the BGCMAR register */
+    tmp |= (uint32_t)CLUTCfg.pCLUT;
+  
+    /* Write to DMA2D BGCMAR register */
+    hdma2d->Instance->BGCMAR = tmp;
+    
+    /* Get the BGPFCCR register value */
+    tmp = hdma2d->Instance->BGPFCCR;
+
+    /* Clear CLUT size and CLUT address bits */
+    tmp &= (uint32_t)~(DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM); 
+
+    /* Get the CLUT size */
+    tmp1 = CLUTCfg.Size << 16;
+    
+    /* Prepare the value to be wrote to the BGPFCCR register */
+    tmp |= (CLUTCfg.CLUTColorMode | tmp1);
+  
+    /* Write to DMA2D BGPFCCR register */
+    hdma2d->Instance->BGPFCCR = tmp;       
+  }
+  /* Configure the CLUT of the foreground DMA2D layer */
+  else
+  {
+    /* Get the FGCMAR register value */
+    tmp = hdma2d->Instance->FGCMAR;
+
+    /* Clear CLUT address bits */
+    tmp &= (uint32_t)~DMA2D_FGCMAR_MA; 
+  
+    /* Prepare the value to be wrote to the FGCMAR register */
+    tmp |= (uint32_t)CLUTCfg.pCLUT;
+  
+    /* Write to DMA2D FGCMAR register */
+    hdma2d->Instance->FGCMAR = tmp;
+    
+    /* Get the FGPFCCR register value */
+    tmp = hdma2d->Instance->FGPFCCR;
+
+    /* Clear CLUT size and CLUT address bits */
+    tmp &= (uint32_t)~(DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM); 
+
+    /* Get the CLUT size */
+    tmp1 = CLUTCfg.Size << 8;
+    
+    /* Prepare the value to be wrote to the FGPFCCR register */
+    tmp |= (CLUTCfg.CLUTColorMode | tmp1);
+  
+    /* Write to DMA2D FGPFCCR register */
+    hdma2d->Instance->FGPFCCR = tmp;    
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the DMA2D CLUT Transfer.
+  * @param  hdma2d:   pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  LayerIdx: DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{  
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+  
+  if(LayerIdx == 0)
+  {
+    /* Enable the CLUT loading for the background */
+    hdma2d->Instance->BGPFCCR |= DMA2D_BGPFCCR_START;
+  }
+  else
+  {
+    /* Enable the CLUT loading for the foreground */
+    hdma2d->Instance->FGPFCCR |= DMA2D_FGPFCCR_START;
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the DMA2D CLUT Transfer.
+  * @param  hdma2d:   pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  LayerIdx: DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+  
+  if(LayerIdx == 0)
+  {
+    /* Disable the CLUT loading for the background */
+    hdma2d->Instance->BGPFCCR &= ~DMA2D_BGPFCCR_START;
+  }
+  else
+  {
+    /* Disable the CLUT loading for the foreground */
+    hdma2d->Instance->FGPFCCR &= ~DMA2D_FGPFCCR_START;
+  } 
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Define the configuration of the line watermark .
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @param  Line:   Line Watermark configuration.
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
+{
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+  
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LineWatermark(Line));
+
+  /* Sets the Line watermark configuration */
+  DMA2D->LWR = (uint32_t)Line;
+  
+  /* Initialize the DMA2D state*/
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdma2d);  
+  
+  return HAL_OK;  
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Group4 Peripheral State functions
+ *  @brief    Peripheral State functions 
+ *
+@verbatim   
+ ===============================================================================
+                  ##### Peripheral State and Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions allowing to :
+      (+) Check the DMA2D state
+      (+) Get error code  
+
+@endverbatim
+  * @{
+  */ 
+
+/**
+  * @brief  Return the DMA2D state
+  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.  
+  * @retval HAL state
+  */
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
+{  
+  return hdma2d->State;
+}
+
+/**
+  * @brief  Return the DMA2D error code
+  * @param  hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
+  *               the configuration information for DMA2D.
+  * @retval DMA2D Error Code
+  */
+uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
+{
+  return hdma2d->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @brief  Set the DMA2D Transfer parameter.
+  * @param  hdma2d:     pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA2D.  
+  * @param  pdata:      The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  Width:      The width of data to be transferred from source to destination.
+  * @param  Heigh:      The heigh of data to be transferred from source to destination.
+  * @retval HAL status
+  */
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh)
+{  
+  uint32_t tmp = 0;
+  uint32_t tmp1 = 0;
+  uint32_t tmp2 = 0;
+  uint32_t tmp3 = 0;
+  uint32_t tmp4 = 0;
+  
+  tmp = Width << 16;
+  
+  /* Configure DMA2D data size */
+  hdma2d->Instance->NLR = (Heigh | tmp);
+  
+  /* Configure DMA2D destination address */
+  hdma2d->Instance->OMAR = DstAddress;
+ 
+  /* Register to memory DMA2D mode selected */
+  if (hdma2d->Init.Mode == DMA2D_R2M)
+  {    
+    tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
+    tmp2 = pdata & DMA2D_OCOLR_RED_1;
+    tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
+    tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
+    
+    /* Prepare the value to be wrote to the OCOLR register according to the color mode */
+    if (hdma2d->Init.ColorMode == DMA2D_ARGB8888)
+    {
+      tmp = (tmp3 | tmp2 | tmp1| tmp4);
+    }
+    else if (hdma2d->Init.ColorMode == DMA2D_RGB888)
+    {
+      tmp = (tmp3 | tmp2 | tmp4);  
+    }
+    else if (hdma2d->Init.ColorMode == DMA2D_RGB565)
+    {
+      tmp2 = (tmp2 >> 19);
+      tmp3 = (tmp3 >> 10);
+      tmp4 = (tmp4 >> 3 );
+      tmp  = ((tmp3 << 5) | (tmp2 << 11) | tmp4); 
+    }
+    else if (hdma2d->Init.ColorMode == DMA2D_ARGB1555)
+    { 
+      tmp1 = (tmp1 >> 31);
+      tmp2 = (tmp2 >> 19);
+      tmp3 = (tmp3 >> 11);
+      tmp4 = (tmp4 >> 3 );      
+      tmp  = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4);    
+    } 
+    else /* DMA2D_CMode = DMA2D_ARGB4444 */
+    {
+      tmp1 = (tmp1 >> 28);
+      tmp2 = (tmp2 >> 20);
+      tmp3 = (tmp3 >> 12);
+      tmp4 = (tmp4 >> 4 );
+      tmp  = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4);
+    }    
+    /* Write to DMA2D OCOLR register */
+    hdma2d->Instance->OCOLR = tmp;
+  }
+  else if ((hdma2d->LayerCfg[1].InputColorMode == CM_A4) || (hdma2d->LayerCfg[1].InputColorMode == CM_A8))
+  {
+    hdma2d->Instance->FGCOLR = pdata;
+  }  
+  else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
+  {
+    /* Configure DMA2D source address */
+    hdma2d->Instance->FGMAR = pdata;
+  }
+}
+
+/**
+  * @}
+  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,504 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dma2d.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of DMA2D HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DMA2D_H
+#define __STM32F4xx_HAL_DMA2D_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA2D
+  * @{
+  */ 
+  
+/* Exported types ------------------------------------------------------------*/
+
+#define MAX_DMA2D_LAYER  2
+
+/** 
+  * @brief DMA2D color Structure definition
+  */
+typedef struct
+{
+  uint32_t Blue;               /*!< Configures the blue value.
+                                    This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint32_t Green;              /*!< Configures the green value.
+                                    This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint32_t Red;                /*!< Configures the red value.
+                                    This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+} DMA2D_ColorTypeDef;
+
+/** 
+  * @brief DMA2D CLUT Structure definition
+  */
+typedef struct
+{
+  uint32_t *pCLUT;                  /*!< Configures the DMA2D CLUT memory address.*/
+
+  uint32_t CLUTColorMode;           /*!< configures the DMA2D CLUT color mode.
+                                         This parameter can be one value of @ref DMA2D_CLUT_CM */
+
+  uint32_t Size;                    /*!< configures the DMA2D CLUT size. 
+                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
+} DMA2D_CLUTCfgTypeDef;
+
+/** 
+  * @brief DMA2D Init structure definition
+  */
+typedef struct
+{
+  uint32_t             Mode;               /*!< configures the DMA2D transfer mode.
+                                                This parameter can be one value of @ref DMA2D_Mode */
+
+  uint32_t             ColorMode;          /*!< configures the color format of the output image.
+                                                This parameter can be one value of @ref DMA2D_Color_Mode */
+
+  uint32_t             OutputOffset;       /*!< Specifies the Offset value. 
+                                                This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 
+} DMA2D_InitTypeDef;
+
+/** 
+  * @brief DMA2D Layer structure definition
+  */
+typedef struct
+{
+  uint32_t             InputOffset;       /*!< configures the DMA2D foreground offset.
+                                               This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+
+  uint32_t             InputColorMode;    /*!< configures the DMA2D foreground color mode . 
+                                               This parameter can be one value of @ref DMA2D_Input_Color_Mode */
+
+  uint32_t             AlphaMode;         /*!< configures the DMA2D foreground alpha mode. 
+                                               This parameter can be one value of @ref DMA2D_ALPHA_MODE */
+
+  uint32_t             InputAlpha;        /*!< Specifies the DMA2D foreground alpha value. 
+                                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+} DMA2D_LayerCfgTypeDef;
+
+/** 
+  * @brief  HAL DMA2D State structures definition
+  */
+typedef enum
+{
+  HAL_DMA2D_STATE_RESET             = 0x00,    /*!< DMA2D not yet initialized or disabled       */
+  HAL_DMA2D_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use    */
+  HAL_DMA2D_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing              */
+  HAL_DMA2D_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                               */
+  HAL_DMA2D_STATE_ERROR             = 0x04,    /*!< DMA2D state error                           */
+  HAL_DMA2D_STATE_SUSPEND           = 0x05     /*!< DMA2D process is suspended                  */
+}HAL_DMA2D_StateTypeDef;
+
+/** 
+  * @brief  DMA2D handle Structure definition
+  */
+typedef struct __DMA2D_HandleTypeDef
+{
+  DMA2D_TypeDef               *Instance;                                                    /*!< DMA2D Register base address       */
+
+  DMA2D_InitTypeDef           Init;                                                         /*!< DMA2D communication parameters    */ 
+
+  void                        (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d);  /*!< DMA2D transfer complete callback  */
+
+  void                        (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback     */
+
+  DMA2D_LayerCfgTypeDef       LayerCfg[MAX_DMA2D_LAYER];                                    /*!< DMA2D Layers parameters           */  
+
+  HAL_LockTypeDef             Lock;                                                         /*!< DMA2D Lock                        */  
+
+  __IO HAL_DMA2D_StateTypeDef State;                                                        /*!< DMA2D transfer state              */
+
+  __IO uint32_t               ErrorCode;                                                    /*!< DMA2D Error code                  */  
+} DMA2D_HandleTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA2D_Exported_Constants
+  * @{
+  */
+
+/** @defgroup DMA2D_Layer 
+  * @{
+  */
+#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Error_Code 
+  * @{
+  */
+#define HAL_DMA2D_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error             */
+#define HAL_DMA2D_ERROR_TE        ((uint32_t)0x00000001)    /*!< Transfer error       */
+#define HAL_DMA2D_ERROR_CE        ((uint32_t)0x00000002)    /*!< Configuration error  */
+#define HAL_DMA2D_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error        */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Mode 
+  * @{
+  */
+#define DMA2D_M2M                            ((uint32_t)0x00000000)             /*!< DMA2D memory to memory transfer mode */
+#define DMA2D_M2M_PFC                        ((uint32_t)0x00010000)             /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define DMA2D_M2M_BLEND                      ((uint32_t)0x00020000)             /*!< DMA2D memory to memory with blending transfer mode */
+#define DMA2D_R2M                            ((uint32_t)0x00030000)             /*!< DMA2D register to memory transfer mode */
+
+#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M)       || ((MODE) == DMA2D_M2M_PFC) || \
+                             ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Color_Mode 
+  * @{
+  */
+#define DMA2D_ARGB8888                       ((uint32_t)0x00000000)             /*!< ARGB8888 DMA2D color mode */
+#define DMA2D_RGB888                         ((uint32_t)0x00000001)             /*!< RGB888 DMA2D color mode   */
+#define DMA2D_RGB565                         ((uint32_t)0x00000002)             /*!< RGB565 DMA2D color mode   */
+#define DMA2D_ARGB1555                       ((uint32_t)0x00000003)             /*!< ARGB1555 DMA2D color mode */
+#define DMA2D_ARGB4444                       ((uint32_t)0x00000004)             /*!< ARGB4444 DMA2D color mode */
+
+#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888)   || \
+                                   ((MODE_ARGB) == DMA2D_RGB565)   || ((MODE_ARGB) == DMA2D_ARGB1555) || \
+                                   ((MODE_ARGB) == DMA2D_ARGB4444))
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_COLOR_VALUE
+  * @{
+  */
+
+#define COLOR_VALUE             ((uint32_t)0x000000FF)                          /*!< color value mask */
+
+#define IS_DMA2D_ALPHA_VALUE(ALPHA_VALUE) ((ALPHA_VALUE) <= COLOR_VALUE)
+#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE)
+/**
+  * @}
+  */    
+
+/** @defgroup DMA2D_SIZE 
+  * @{
+  */
+#define DMA2D_PIXEL          (DMA2D_NLR_PL >> 16)                               /*!< DMA2D pixel per line */
+#define DMA2D_LINE           DMA2D_NLR_NL                                       /*!< DMA2D number of line */
+
+#define IS_DMA2D_LINE(LINE)  ((LINE) <= DMA2D_LINE)
+#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Offset 
+  * @{
+  */
+#define DMA2D_OFFSET      DMA2D_FGOR_LO            /*!< Line Offset */
+
+#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA2D_Input_Color_Mode
+  * @{
+  */
+#define CM_ARGB8888        ((uint32_t)0x00000000)                               /*!< ARGB8888 color mode */
+#define CM_RGB888          ((uint32_t)0x00000001)                               /*!< RGB888 color mode */
+#define CM_RGB565          ((uint32_t)0x00000002)                               /*!< RGB565 color mode */
+#define CM_ARGB1555        ((uint32_t)0x00000003)                               /*!< ARGB1555 color mode */
+#define CM_ARGB4444        ((uint32_t)0x00000004)                               /*!< ARGB4444 color mode */
+#define CM_L8              ((uint32_t)0x00000005)                               /*!< L8 color mode */
+#define CM_AL44            ((uint32_t)0x00000006)                               /*!< AL44 color mode */
+#define CM_AL88            ((uint32_t)0x00000007)                               /*!< AL88 color mode */
+#define CM_L4              ((uint32_t)0x00000008)                               /*!< L4 color mode */
+#define CM_A8              ((uint32_t)0x00000009)                               /*!< A8 color mode */
+#define CM_A4              ((uint32_t)0x0000000A)                               /*!< A4 color mode */
+
+#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888)   || \
+                                             ((INPUT_CM) == CM_RGB565)   || ((INPUT_CM) == CM_ARGB1555) || \
+                                             ((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8)       || \
+                                             ((INPUT_CM) == CM_AL44)     || ((INPUT_CM) == CM_AL88)     || \
+                                             ((INPUT_CM) == CM_L4)       || ((INPUT_CM) == CM_A8)       || \
+                                             ((INPUT_CM) == CM_A4))
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_ALPHA_MODE
+  * @{
+  */
+#define DMA2D_NO_MODIF_ALPHA       ((uint32_t)0x00000000)  /*!< No modification of the alpha channel value */
+#define DMA2D_REPLACE_ALPHA        ((uint32_t)0x00000001)  /*!< Replace original alpha channel value by programmed alpha value */
+#define DMA2D_COMBINE_ALPHA        ((uint32_t)0x00000002)  /*!< Replace original alpha channel value by programmed alpha value
+                                                                with original alpha channel value                              */
+
+#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
+                                        ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \
+                                        ((AlphaMode) == DMA2D_COMBINE_ALPHA))
+/**
+  * @}
+  */    
+
+/** @defgroup DMA2D_CLUT_CM
+  * @{
+  */
+#define DMA2D_CCM_ARGB8888    ((uint32_t)0x00000000)    /*!< ARGB8888 DMA2D C-LUT color mode */
+#define DMA2D_CCM_RGB888      ((uint32_t)0x00000001)    /*!< RGB888 DMA2D C-LUT color mode   */
+
+#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Size_Clut
+  * @{
+  */
+#define DMA2D_CLUT_SIZE    (DMA2D_FGPFCCR_CS >> 8)    /*!< DMA2D C-LUT size */
+
+#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_DeadTime 
+  * @{
+  */
+#define LINE_WATERMARK            DMA2D_LWR_LW
+
+#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Interrupts 
+  * @{
+  */
+#define DMA2D_IT_CE             DMA2D_CR_CEIE    /*!< Configuration Error Interrupt */
+#define DMA2D_IT_CTC            DMA2D_CR_CTCIE   /*!< C-LUT Transfer Complete Interrupt */
+#define DMA2D_IT_CAE            DMA2D_CR_CAEIE   /*!< C-LUT Access Error Interrupt */
+#define DMA2D_IT_TW             DMA2D_CR_TWIE    /*!< Transfer Watermark Interrupt */
+#define DMA2D_IT_TC             DMA2D_CR_TCIE    /*!< Transfer Complete Interrupt */
+#define DMA2D_IT_TE             DMA2D_CR_TEIE    /*!< Transfer Error Interrupt */
+
+#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
+                        ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
+                        ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Flag 
+  * @{
+  */
+#define DMA2D_FLAG_CE          DMA2D_ISR_CEIF     /*!< Configuration Error Interrupt Flag */
+#define DMA2D_FLAG_CTC         DMA2D_ISR_CTCIF    /*!< C-LUT Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_CAE         DMA2D_ISR_CAEIF    /*!< C-LUT Access Error Interrupt Flag */
+#define DMA2D_FLAG_TW          DMA2D_ISR_TWIF     /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_FLAG_TC          DMA2D_ISR_TCIF     /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_TE          DMA2D_ISR_TEIF     /*!< Transfer Error Interrupt Flag */
+
+#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
+                                ((FLAG) == DMA2D_FLAG_TW)   || ((FLAG) == DMA2D_FLAG_TC)  || \
+                                ((FLAG) == DMA2D_FLAG_TE)   || ((FLAG) == DMA2D_FLAG_CE))
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset DMA2D handle state
+  * @param  __HANDLE__: specifies the DMA2D handle.
+  * @retval None
+  */
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
+
+/**
+  * @brief  Enable the DMA2D.
+  * @param  __HANDLE__: DMA2D handle
+  * @retval None.
+  */
+#define __HAL_DMA2D_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
+
+/**
+  * @brief  Disable the DMA2D.
+  * @param  __HANDLE__: DMA2D handle
+  * @retval None.
+  */
+#define __HAL_DMA2D_DISABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR &= ~DMA2D_CR_START)
+
+/* Interrupt & Flag management */
+/**
+  * @brief  Get the DMA2D pending flags.
+  * @param  __HANDLE__: DMA2D handle
+  * @param  __FLAG__: Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_FLAG_CE:  Configuration error flag
+  *            @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
+  *            @arg DMA2D_FLAG_CAE: C-LUT access error flag
+  *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
+  *            @arg DMA2D_FLAG_TC:  Transfer complete flag
+  *            @arg DMA2D_FLAG_TE:  Transfer error flag   
+  * @retval The state of FLAG.
+  */
+#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/**
+  * @brief  Clears the DMA2D pending flags.
+  * @param  __HANDLE__: DMA2D handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_FLAG_CE:  Configuration error flag
+  *            @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
+  *            @arg DMA2D_FLAG_CAE: C-LUT access error flag
+  *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
+  *            @arg DMA2D_FLAG_TC:  Transfer complete flag
+  *            @arg DMA2D_FLAG_TE:  Transfer error flag    
+  * @retval None
+  */
+#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR |= (__FLAG__))
+
+/**
+  * @brief  Enables the specified DMA2D interrupts.
+  * @param  __HANDLE__: DMA2D handle
+  * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
+  *            @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
+  *            @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
+  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
+  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disables the specified DMA2D interrupts.
+  * @param  __HANDLE__: DMA2D handle
+  * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
+  *            @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
+  *            @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
+  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
+  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified DMA2D interrupt has occurred or not.
+  * @param  __HANDLE__: DMA2D handle
+  * @param  __INTERRUPT__: specifies the DMA2D interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
+  *            @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
+  *            @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
+  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
+  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
+  * @retval The state of INTERRUPT.
+  */
+#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
+
+/* Exported functions --------------------------------------------------------*/  
+
+/* Initialization and de-initialization functions *******************************/
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); 
+HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
+void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
+void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Heigh);
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
+void              HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef  HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef  HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef  HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef  HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef  HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
+
+/* Peripheral State functions ***************************************************/
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
+uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
+
+#endif /* STM32F427xx || STM32F437xx  || STM32F429xx || STM32F439xx */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DMA2D_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,295 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dma_ex.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   DMA Extension HAL module driver
+  *         This file provides firmware functions to manage the following 
+  *         functionalities of the DMA Extension peripheral:
+  *           + Extended features functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+  The DMA Extension HAL driver can be used as follows:
+   (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
+       for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
+                   
+     -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
+     -@-  When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
+     -@-  In Multi (Double) buffer mode, it is possible to update the base address for 
+          the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. 
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMAEx 
+  * @brief DMA Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DMAEx_Private_Functions
+  * @{
+  */
+
+
+/** @defgroup DMAEx_Group1 Extended features functions 
+ *  @brief   Extended features functions   
+ *
+@verbatim   
+ ===============================================================================
+                #####  Extended features functions  #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and 
+          Start MultiBuffer DMA transfer
+      (+) Configure the source, destination address and data length and 
+          Start MultiBuffer DMA transfer with interrupt
+      (+) Change on the fly the memory0 or memory1 address.
+      
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Starts the multi_buffer DMA Transfer.
+  * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer  
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdma);
+
+  /* Current memory buffer used is Memory 0 */
+  if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
+  {
+    hdma->State = HAL_DMA_STATE_BUSY_MEM0;
+  }
+  /* Current memory buffer used is Memory 1 */
+  else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
+  {
+    hdma->State = HAL_DMA_STATE_BUSY_MEM1;
+  }
+
+   /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Disable the peripheral */
+  __HAL_DMA_DISABLE(hdma);  
+
+  /* Enable the double buffer mode */
+  hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
+
+  /* Configure DMA Stream destination address */
+  hdma->Instance->M1AR = SecondMemAddress;
+
+  /* Configure the source, destination address and the data length */
+  DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+  /* Enable the peripheral */
+  __HAL_DMA_ENABLE(hdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer  
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdma);
+
+  /* Current memory buffer used is Memory 0 */
+  if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
+  {
+    hdma->State = HAL_DMA_STATE_BUSY_MEM0;
+  }
+  /* Current memory buffer used is Memory 1 */
+  else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
+  {
+    hdma->State = HAL_DMA_STATE_BUSY_MEM1;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Disable the peripheral */
+  __HAL_DMA_DISABLE(hdma);  
+
+  /* Enable the Double buffer mode */
+  hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
+
+  /* Configure DMA Stream destination address */
+  hdma->Instance->M1AR = SecondMemAddress;
+
+  /* Configure the source, destination address and the data length */
+  DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); 
+
+  /* Enable the transfer complete interrupt */
+  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
+
+  /* Enable the Half transfer interrupt */
+  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
+
+  /* Enable the transfer Error interrupt */
+  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
+
+  /* Enable the fifo Error interrupt */
+  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE);  
+
+  /* Enable the direct mode Error interrupt */
+  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME); 
+
+  /* Enable the peripheral */
+  __HAL_DMA_ENABLE(hdma); 
+
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Change the memory0 or memory1 address on the fly.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  Address:    The new address
+  * @param  memory:     the memory to be changed, This parameter can be one of 
+  *                     the following values:
+  *                      MEMORY0 /
+  *                      MEMORY1
+  * @note   The MEMORY0 address can be changed only when the current transfer use
+  *         MEMORY1 and the MEMORY1 address can be changed only when the current 
+  *         transfer use MEMORY0.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
+{
+  if(memory == MEMORY0)
+  {
+    /* change the memory0 address */
+    hdma->Instance->M0AR = Address;
+  }
+  else
+  {
+    /* change the memory1 address */
+    hdma->Instance->M1AR = Address;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Set the DMA Transfer parameter.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{  
+  /* Configure DMA Stream data length */
+  hdma->Instance->NDTR = DataLength;
+  
+  /* Peripheral to Memory */
+  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+  {   
+    /* Configure DMA Stream destination address */
+    hdma->Instance->PAR = DstAddress;
+    
+    /* Configure DMA Stream source address */
+    hdma->Instance->M0AR = SrcAddress;
+  }
+  /* Memory to Peripheral */
+  else
+  {
+    /* Configure DMA Stream source address */
+    hdma->Instance->PAR = SrcAddress;
+    
+    /* Configure DMA Stream destination address */
+    hdma->Instance->M0AR = DstAddress;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma_ex.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,93 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dma_ex.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of DMA HAL extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DMA_EX_H
+#define __STM32F4xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMAEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  HAL DMA Memory definition  
+  */ 
+typedef enum
+{
+  MEMORY0      = 0x00,    /*!< Memory 0     */
+  MEMORY1      = 0x01,    /*!< Memory 1     */
+
+}HAL_DMA_MemoryTypeDef;
+
+/* Exported constants --------------------------------------------------------*/ 
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1964 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_eth.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   ETH HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Ethernet (ETH) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State and Errors functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#)Declare a ETH_HandleTypeDef handle structure, for example:
+         ETH_HandleTypeDef  heth;
+        
+      (#)Fill parameters of Init structure in heth handle
+  
+      (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) 
+
+      (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
+          (##) Enable the Ethernet interface clock using 
+               (+++) __ETHMAC_CLK_ENABLE();
+               (+++) __ETHMACTX_CLK_ENABLE();
+               (+++) __ETHMACRX_CLK_ENABLE();
+           
+          (##) Initialize the related GPIO clocks
+          (##) Configure Ethernet pin-out
+          (##) Configure Ethernet NVIC interrupt (IT mode)   
+    
+      (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
+          (##) HAL_ETH_DMATxDescListInit(); for Transmission process
+          (##) HAL_ETH_DMARxDescListInit(); for Reception process
+
+      (#)Enable MAC and DMA transmission and reception:
+          (##) HAL_ETH_Start();
+
+      (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer 
+         the frame to MAC TX FIFO:
+         (##) HAL_ETH_TransmitFrame();
+
+      (#)Poll for a received frame in ETH RX DMA Descriptors and get received 
+         frame parameters
+         (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
+
+      (#) Get a received frame when an ETH RX interrupt occurs:
+         (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
+
+      (#) Communicate with external PHY device:
+         (##) Read a specific register from the PHY  
+              HAL_ETH_ReadPHYRegister();
+         (##) Write data to a specific RHY register:
+              HAL_ETH_WritePHYRegister();
+
+      (#) Configure the Ethernet MAC after ETH peripheral initialization
+          HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
+      
+      (#) Configure the Ethernet DMA after ETH peripheral initialization
+          HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ETH 
+  * @brief ETH HAL module driver
+  * @{
+  */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
+static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
+static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
+static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
+static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
+static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
+static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
+static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
+static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
+static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
+static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup ETH_Private_Functions
+  * @{
+  */
+
+/** @defgroup ETH_Group1 Initialization and de-initialization functions 
+  *  @brief    Initialization and Configuration functions 
+  *
+  @verbatim    
+  ===============================================================================
+            ##### Initialization and de-initialization functions #####
+  ===============================================================================
+  [..]  This section provides functions allowing to:
+      (+) Initialize and configure the Ethernet peripheral
+      (+) De-initialize the Ethernet peripheral
+
+  @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the Ethernet MAC and DMA according to default
+  *         parameters.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
+{
+  uint32_t tmpreg = 0, phyreg = 0;
+  uint32_t hclk = 60000000;
+  uint32_t timeout = 0;
+  uint32_t err = ETH_SUCCESS;
+  
+  /* Check the ETH peripheral state */
+  if(heth == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check parameters */
+  assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
+  assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
+  assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
+  assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));  
+  
+  if(heth->State == HAL_ETH_STATE_RESET)
+  {
+    /* Init the low level hardware : GPIO, CLOCK, NVIC. */
+    HAL_ETH_MspInit(heth);
+  }
+  
+  /* Enable SYSCFG Clock */
+  __SYSCFG_CLK_ENABLE();
+  
+  /* Select MII or RMII Mode*/
+  SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
+  SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
+  
+  /* Ethernet Software reset */
+  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
+  /* After reset all the registers holds their respective reset values */
+  (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
+  
+  /* Wait for software reset */
+  while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
+  {
+  }
+  
+  /*-------------------------------- MAC Initialization ----------------------*/
+  /* Get the ETHERNET MACMIIAR value */
+  tmpreg = (heth->Instance)->MACMIIAR;
+  /* Clear CSR Clock Range CR[2:0] bits */
+  tmpreg &= MACMIIAR_CR_MASK;
+  
+  /* Get hclk frequency value */
+  hclk = HAL_RCC_GetHCLKFreq();
+  
+  /* Set CR bits depending on hclk value */
+  if((hclk >= 20000000)&&(hclk < 35000000))
+  {
+    /* CSR Clock Range between 20-35 MHz */
+    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
+  }
+  else if((hclk >= 35000000)&&(hclk < 60000000))
+  {
+    /* CSR Clock Range between 35-60 MHz */ 
+    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
+  }  
+  else if((hclk >= 60000000)&&(hclk < 100000000))
+  {
+    /* CSR Clock Range between 60-100 MHz */ 
+    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
+  }  
+  else if((hclk >= 100000000)&&(hclk < 150000000))
+  {
+    /* CSR Clock Range between 100-150 MHz */ 
+    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
+  }
+  else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */
+  {
+    /* CSR Clock Range between 150-168 MHz */ 
+    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;    
+  }
+  
+  /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
+  (heth->Instance)->MACMIIAR = (uint32_t)tmpreg;
+  
+  /*-------------------- PHY initialization and configuration ----------------*/
+  /* Put the PHY in reset mode */
+  if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
+  {
+    /* In case of write timeout */
+    err = ETH_ERROR;
+    
+    /* Config MAC and DMA */
+    ETH_MACDMAConfig(heth, err);
+    
+    /* Set the ETH peripheral state to READY */
+    heth->State = HAL_ETH_STATE_READY;
+    
+    /* Return HAL_ERROR */
+    return HAL_ERROR;
+  }
+  
+  /* Delay to assure PHY reset */
+  HAL_Delay(PHY_RESET_DELAY);
+  
+  if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
+  {
+    /* We wait for linked status */
+    do
+    {
+      timeout++;
+      HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
+    } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS) && (timeout < PHY_READ_TO));
+    
+    if(timeout == PHY_READ_TO)
+    {
+      /* In case of write timeout */
+      err = ETH_ERROR;
+      
+      /* Config MAC and DMA */
+      ETH_MACDMAConfig(heth, err);
+      
+      /* Set the ETH peripheral state to READY */
+      heth->State = HAL_ETH_STATE_READY;
+      
+      /* Return HAL_ERROR */
+      return HAL_ERROR;
+    }
+    
+    /* Reset Timeout counter */
+    timeout = 0; 
+    
+    /* Enable Auto-Negotiation */
+    if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
+    {
+      /* In case of write timeout */
+      err = ETH_ERROR;
+      
+      /* Config MAC and DMA */
+      ETH_MACDMAConfig(heth, err);
+      
+      /* Set the ETH peripheral state to READY */
+      heth->State = HAL_ETH_STATE_READY;
+      
+      /* Return HAL_ERROR */
+      return HAL_ERROR;   
+    }
+    
+    /* Wait until the auto-negotiation will be completed */
+    do
+    {
+      timeout++;
+      HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
+    } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE) && (timeout < PHY_READ_TO));
+    
+    if(timeout == PHY_READ_TO)
+    {
+      /* In case of timeout */
+      err = ETH_ERROR;
+      
+      /* Config MAC and DMA */
+      ETH_MACDMAConfig(heth, err);
+      
+      /* Set the ETH peripheral state to READY */
+      heth->State = HAL_ETH_STATE_READY;
+      
+      /* Return HAL_ERROR */
+      return HAL_ERROR;
+    }
+    
+    /* Reset Timeout counter */
+    timeout = 0;
+    
+    /* Read the result of the auto-negotiation */
+    HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg);
+    
+    /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
+    if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
+    {
+      /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
+      (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;  
+    }
+    else
+    {
+      /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
+      (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;           
+    }
+    /* Configure the MAC with the speed fixed by the auto-negotiation process */
+    if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
+    {  
+      /* Set Ethernet speed to 10M following the auto-negotiation */
+      (heth->Init).Speed = ETH_SPEED_10M; 
+    }
+    else
+    {   
+      /* Set Ethernet speed to 100M following the auto-negotiation */ 
+      (heth->Init).Speed = ETH_SPEED_100M;
+    }
+  }
+  else /* AutoNegotiation Disable */
+  {
+    /* Check parameters */
+    assert_param(IS_ETH_SPEED(heth->Init.Speed));
+    assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
+    
+    /* Set MAC Speed and Duplex Mode */
+    if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
+                                                (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
+    {
+      /* In case of write timeout */
+      err = ETH_ERROR;
+      
+      /* Config MAC and DMA */
+      ETH_MACDMAConfig(heth, err);
+      
+      /* Set the ETH peripheral state to READY */
+      heth->State = HAL_ETH_STATE_READY;
+      
+      /* Return HAL_ERROR */
+      return HAL_ERROR;
+    }  
+    
+    /* Delay to assure PHY configuration */
+    HAL_Delay(PHY_CONFIG_DELAY);
+  }
+  
+  /* Config MAC and DMA */
+  ETH_MACDMAConfig(heth, err);
+  
+  /* Set ETH HAL State to Ready */
+  heth->State= HAL_ETH_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-Initializes the ETH peripheral. 
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
+{
+  /* Set the ETH peripheral state to BUSY */
+  heth->State = HAL_ETH_STATE_BUSY;
+  
+  /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
+  HAL_ETH_MspDeInit(heth);
+  
+  /* Set ETH HAL state to Disabled */
+  heth->State= HAL_ETH_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(heth);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the DMA Tx descriptors in chain mode.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module  
+  * @param  DMATxDescTab: Pointer to the first Tx desc list 
+  * @param  TxBuff: Pointer to the first TxBuffer list
+  * @param  TxBuffCount: Number of the used Tx desc in the list
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADescTypeDef *dmatxdesc;
+  
+  /* Process Locked */
+  __HAL_LOCK(heth);
+  
+  /* Set the ETH peripheral state to BUSY */
+  heth->State = HAL_ETH_STATE_BUSY;
+  
+  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
+  heth->TxDesc = DMATxDescTab;
+  
+  /* Fill each DMATxDesc descriptor with the right values */   
+  for(i=0; i < TxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Tx Desc list */
+    dmatxdesc = DMATxDescTab + i;
+    
+    /* Set Second Address Chained bit */
+    dmatxdesc->Status = ETH_DMATXDESC_TCH;  
+    
+    /* Set Buffer1 address pointer */
+    dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
+    
+    if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
+    {
+      /* Set the DMA Tx descriptors checksum insertion */
+      dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
+    }
+    
+    /* Initialize the next descriptor with the Next Descriptor Polling Enable */
+    if(i < (TxBuffCount-1))
+    {
+      /* Set next descriptor address register with next descriptor base address */
+      dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
+    }
+    else
+    {
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ 
+      dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;  
+    }
+  }
+  
+  /* Set Transmit Descriptor List Address Register */
+  (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
+  
+  /* Set ETH HAL State to Ready */
+  heth->State= HAL_ETH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(heth);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the DMA Rx descriptors in chain mode.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module  
+  * @param  DMARxDescTab: Pointer to the first Rx desc list 
+  * @param  RxBuff: Pointer to the first RxBuffer list
+  * @param  RxBuffCount: Number of the used Rx desc in the list
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADescTypeDef *DMARxDesc;
+  
+  /* Process Locked */
+  __HAL_LOCK(heth);
+  
+  /* Set the ETH peripheral state to BUSY */
+  heth->State = HAL_ETH_STATE_BUSY;
+  
+  /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
+  heth->RxDesc = DMARxDescTab; 
+  
+  /* Fill each DMARxDesc descriptor with the right values */
+  for(i=0; i < RxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Rx Desc list */
+    DMARxDesc = DMARxDescTab+i;
+    
+    /* Set Own bit of the Rx descriptor Status */
+    DMARxDesc->Status = ETH_DMARXDESC_OWN;
+    
+    /* Set Buffer1 size and Second Address Chained bit */
+    DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;  
+    
+    /* Set Buffer1 address pointer */
+    DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
+    
+    if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
+    {
+      /* Enable Ethernet DMA Rx Descriptor interrupt */
+      DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
+    }
+    
+    /* Initialize the next descriptor with the Next Descriptor Polling Enable */
+    if(i < (RxBuffCount-1))
+    {
+      /* Set next descriptor address register with next descriptor base address */
+      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); 
+    }
+    else
+    {
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ 
+      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); 
+    }
+  }
+  
+  /* Set Receive Descriptor List Address Register */
+  (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
+  
+  /* Set ETH HAL State to Ready */
+  heth->State= HAL_ETH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(heth);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the ETH MSP.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_MspInit could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  DeInitializes ETH MSP.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_MspDeInit could be implemented in the user file
+  */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Group2 IO operation functions 
+  *  @brief   Data transfers functions 
+  *
+  @verbatim   
+  ==============================================================================
+                          ##### IO operation functions #####
+  ==============================================================================  
+  [..]  This section provides functions allowing to:
+        (+) Transmit a frame
+            HAL_ETH_TransmitFrame();
+        (+) Receive a frame
+            HAL_ETH_GetReceivedFrame();
+            HAL_ETH_GetReceivedFrame_IT();
+        (+) Read from an External PHY register
+            HAL_ETH_ReadPHYRegister();
+        (+) Write to an External PHY register
+            HAL_ETH_WritePHYRegister();
+
+  @endverbatim
+  
+  * @{
+  */
+
+/**
+  * @brief  Sends an Ethernet frame. 
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  FrameLength: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
+{
+  uint32_t bufcount = 0, size = 0, i = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(heth);
+  
+  /* Set the ETH peripheral state to BUSY */
+  heth->State = HAL_ETH_STATE_BUSY;
+  
+  if (FrameLength == 0) 
+  {
+    /* Set ETH HAL state to READY */
+    heth->State = HAL_ETH_STATE_READY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(heth);
+    
+    return  HAL_ERROR;                                    
+  }  
+  
+  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+  if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
+  {  
+    /* OWN bit set */
+    heth->State = HAL_ETH_STATE_BUSY_TX;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(heth);
+    
+    return HAL_ERROR;
+  }
+  
+  /* Get the number of needed Tx buffers for the current frame */
+  if (FrameLength > ETH_TX_BUF_SIZE)
+  {
+    bufcount = FrameLength/ETH_TX_BUF_SIZE;
+    if (FrameLength % ETH_TX_BUF_SIZE) 
+    {
+      bufcount++;
+    }
+  }
+  else 
+  {  
+    bufcount = 1;
+  }
+  if (bufcount == 1)
+  {
+    /* Set LAST and FIRST segment */
+    heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
+    /* Set frame size */
+    heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
+    /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
+    heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
+    /* Point to next descriptor */
+    heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
+  }
+  else
+  {
+    for (i=0; i< bufcount; i++)
+    {
+      /* Clear FIRST and LAST segment bits */
+      heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
+      
+      if (i == 0) 
+      {
+        /* Setting the first segment bit */
+        heth->TxDesc->Status |= ETH_DMATXDESC_FS;  
+      }
+      
+      /* Program size */
+      heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
+      
+      if (i == (bufcount-1))
+      {
+        /* Setting the last segment bit */
+        heth->TxDesc->Status |= ETH_DMATXDESC_LS;
+        size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
+        heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
+      }
+      
+      /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
+      heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
+      /* point to next descriptor */
+      heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
+    }
+  }
+  
+  /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
+  if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
+  {
+    /* Clear TBUS ETHERNET DMA flag */
+    (heth->Instance)->DMASR = ETH_DMASR_TBUS;
+    /* Resume DMA transmission*/
+    (heth->Instance)->DMATPDR = 0;
+  }
+  
+  /* Set ETH HAL State to Ready */
+  heth->State = HAL_ETH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(heth);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Checks for received frames. 
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
+{
+  uint32_t framelength = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(heth);
+  
+  /* Check the ETH state to BUSY */
+  heth->State = HAL_ETH_STATE_BUSY;
+  
+  /* Check if segment is not owned by DMA */
+  /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
+  if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
+  {
+    /* Check if last segment */
+    if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) 
+    {
+      /* increment segment count */
+      (heth->RxFrameInfos).SegCount++;
+      
+      /* Check if last segment is first segment: one segment contains the frame */
+      if ((heth->RxFrameInfos).SegCount == 1)
+      {
+        (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
+      }
+      
+      heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
+      
+      /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+      framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
+      heth->RxFrameInfos.length = framelength;
+      
+      /* Get the address of the buffer start address */
+      heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
+      /* point to next descriptor */
+      heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
+      
+      /* Set HAL State to Ready */
+      heth->State = HAL_ETH_STATE_READY;
+      
+      /* Process Unlocked */
+      __HAL_UNLOCK(heth);
+      
+      /* Return function status */
+      return HAL_OK;
+    }
+    /* Check if first segment */
+    else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
+    {
+      (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
+      (heth->RxFrameInfos).LSRxDesc = NULL;
+      (heth->RxFrameInfos).SegCount = 1;
+      /* Point to next descriptor */
+      heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
+    }
+    /* Check if intermediate segment */ 
+    else
+    {
+      (heth->RxFrameInfos).SegCount++;
+      /* Point to next descriptor */
+      heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
+    } 
+  }
+  
+  /* Set ETH HAL State to Ready */
+  heth->State = HAL_ETH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(heth);
+  
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Gets the Received frame in interrupt mode. 
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
+{
+  uint32_t descriptorscancounter = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(heth);
+  
+  /* Set ETH HAL State to BUSY */
+  heth->State = HAL_ETH_STATE_BUSY;
+  
+  /* Scan descriptors owned by CPU */
+  while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
+  {
+    /* Just for security */
+    descriptorscancounter++;
+    
+    /* Check if first segment in frame */
+    /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */  
+    if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
+    { 
+      heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
+      heth->RxFrameInfos.SegCount = 1;   
+      /* Point to next descriptor */
+      heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
+    }
+    /* Check if intermediate segment */
+    /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
+    else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
+    {
+      /* Increment segment count */
+      (heth->RxFrameInfos.SegCount)++;
+      /* Point to next descriptor */
+      heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
+    }
+    /* Should be last segment */
+    else
+    { 
+      /* Last segment */
+      heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
+      
+      /* Increment segment count */
+      (heth->RxFrameInfos.SegCount)++;
+      
+      /* Check if last segment is first segment: one segment contains the frame */
+      if ((heth->RxFrameInfos.SegCount) == 1)
+      {
+        heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
+      }
+      
+      /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+      heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
+      
+      /* Get the address of the buffer start address */ 
+      heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
+      
+      /* Point to next descriptor */      
+      heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
+      
+      /* Set HAL State to Ready */
+      heth->State = HAL_ETH_STATE_READY;
+      
+      /* Process Unlocked */
+      __HAL_UNLOCK(heth);
+  
+      /* Return function status */
+      return HAL_OK;
+    }
+  }
+
+  /* Set HAL State to Ready */
+  heth->State = HAL_ETH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(heth);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles ETH interrupt request.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
+{
+  /* Frame received */
+  if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) 
+  {
+    /* Receive complete callback */
+    HAL_ETH_RxCpltCallback(heth);
+    
+     /* Clear the Eth DMA Rx IT pending bits */
+    __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
+
+    /* Set HAL State to Ready */
+    heth->State = HAL_ETH_STATE_READY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(heth);
+
+  }
+  /* Frame transmitted */
+  else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T)) 
+  {
+    /* Transfer complete callback */
+    HAL_ETH_TxCpltCallback(heth);
+    
+    /* Clear the Eth DMA Tx IT pending bits */
+    __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
+
+    /* Set HAL State to Ready */
+    heth->State = HAL_ETH_STATE_READY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(heth);
+  }
+  
+  /* Clear the interrupt flags */
+  __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
+  
+  /* ETH DMA Error */
+  if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
+  {
+    /* Ethernet Error callback */
+    HAL_ETH_ErrorCallback(heth);
+
+    /* Clear the interrupt flags */
+    __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
+  
+    /* Set HAL State to Ready */
+    heth->State = HAL_ETH_STATE_READY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(heth);
+  }
+}
+
+/**
+  * @brief  Tx Transfer completed callbacks.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_TxCpltCallback could be implemented in the user file
+  */ 
+}
+
+/**
+  * @brief  Rx Transfer completed callbacks.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_TxCpltCallback could be implemented in the user file
+  */ 
+}
+
+/**
+  * @brief  Ethernet transfer error callbacks
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_TxCpltCallback could be implemented in the user file
+  */ 
+}
+
+/**
+  * @brief  Reads a PHY register
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module                  
+  * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. 
+  *                This parameter can be one of the following values: 
+  *                   PHY_BCR: Transceiver Basic Control Register, 
+  *                   PHY_BSR: Transceiver Basic Status Register.   
+  *                   More PHY register could be read depending on the used PHY
+  * @param RegValue: PHY register value                  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
+{
+  uint32_t tmpreg = 0;     
+  uint32_t timeout = 0;
+  
+  /* Check parameters */
+  assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
+  
+  /* Check the ETH peripheral state */
+  if(heth->State == HAL_ETH_STATE_BUSY_RD)
+  {
+    return HAL_BUSY;
+  }
+  /* Set ETH HAL State to BUSY_RD */
+  heth->State = HAL_ETH_STATE_BUSY_RD;
+  
+  /* Get the ETHERNET MACMIIAR value */
+  tmpreg = heth->Instance->MACMIIAR;
+  
+  /* Keep only the CSR Clock Range CR[2:0] bits value */
+  tmpreg &= ~MACMIIAR_CR_MASK;
+  
+  /* Prepare the MII address register value */
+  tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address   */
+  tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR);                   /* Set the PHY register address */
+  tmpreg &= ~ETH_MACMIIAR_MW;                                           /* Set the read mode            */
+  tmpreg |= ETH_MACMIIAR_MB;                                            /* Set the MII Busy bit         */
+  
+  /* Write the result value into the MII Address register */
+  heth->Instance->MACMIIAR = tmpreg;
+  
+  /* Check for the Busy flag */
+  do
+  {
+    timeout++;
+    tmpreg = heth->Instance->MACMIIAR;
+  } while (((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) && (timeout < PHY_READ_TO));
+  
+  /* Return ERROR in case of timeout */
+  if(timeout == PHY_READ_TO)
+  {
+    /* Set ETH HAL State to READY */
+    heth->State = HAL_ETH_STATE_READY;
+    /* Return HAL_TIMEOUT */
+    return HAL_TIMEOUT;
+  }
+  
+  /* Get MACMIIDR value */
+  *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
+  
+  /* Set ETH HAL State to READY */
+  heth->State = HAL_ETH_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Writes to a PHY register.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module  
+  * @param  PHYReg: PHY register address, is the index of one of the 32 PHY register. 
+  *          This parameter can be one of the following values: 
+  *             PHY_BCR: Transceiver Control Register.  
+  *             More PHY register could be written depending on the used PHY
+  * @param  RegValue: the value to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
+{
+  uint32_t tmpreg = 0;
+  uint32_t timeout = 0;
+  
+  /* Check parameters */
+  assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
+  
+  /* Check the ETH peripheral state */
+  if(heth->State == HAL_ETH_STATE_BUSY_WR)
+  {
+    return HAL_BUSY;
+  }
+  /* Set ETH HAL State to BUSY_WR */
+  heth->State = HAL_ETH_STATE_BUSY_WR;
+  
+  /* Get the ETHERNET MACMIIAR value */
+  tmpreg = heth->Instance->MACMIIAR;
+  
+  /* Keep only the CSR Clock Range CR[2:0] bits value */
+  tmpreg &= ~MACMIIAR_CR_MASK;
+  
+  /* Prepare the MII register address value */
+  tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+  tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR);                 /* Set the PHY register address */
+  tmpreg |= ETH_MACMIIAR_MW;                                          /* Set the write mode */
+  tmpreg |= ETH_MACMIIAR_MB;                                          /* Set the MII Busy bit */
+  
+  /* Give the value to the MII data register */
+  heth->Instance->MACMIIDR = (uint16_t)RegValue;
+  
+  /* Write the result value into the MII Address register */
+  heth->Instance->MACMIIAR = tmpreg;
+  
+  /* Check for the Busy flag */
+  do
+  {
+    timeout++;
+    tmpreg = heth->Instance->MACMIIAR;
+  } while (((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) && (timeout < PHY_WRITE_TO));
+  
+  /* Return TIMETOUT in case of timeout */
+  if(timeout == PHY_WRITE_TO)
+  {
+    /* Set ETH HAL State to READY */
+    heth->State = HAL_ETH_STATE_READY;
+    
+    return HAL_TIMEOUT;
+  }
+  
+  /* Set ETH HAL State to READY */
+  heth->State = HAL_ETH_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK; 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Group3 Peripheral Control functions
+ *  @brief    Peripheral Control functions 
+ *
+@verbatim   
+ ===============================================================================
+                  ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Enable MAC and DMA transmission and reception.
+          HAL_ETH_Start();
+      (+) Disable MAC and DMA transmission and reception. 
+          HAL_ETH_Stop();
+      (+) Set the MAC configuration in runtime mode
+          HAL_ETH_ConfigMAC();
+      (+) Set the DMA configuration in runtime mode
+          HAL_ETH_ConfigDMA();
+
+@endverbatim
+  * @{
+  */ 
+
+ /**
+  * @brief  Enables Ethernet MAC and DMA reception/transmission 
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
+{  
+  /* Process Locked */
+  __HAL_LOCK(heth);
+  
+  /* Set the ETH peripheral state to BUSY */
+  heth->State = HAL_ETH_STATE_BUSY;
+  
+  /* Enable transmit state machine of the MAC for transmission on the MII */
+  ETH_MACTransmissionEnable(heth);
+  
+  /* Enable receive state machine of the MAC for reception from the MII */
+  ETH_MACReceptionEnable(heth);
+  
+  /* Flush Transmit FIFO */
+  ETH_FlushTransmitFIFO(heth);
+  
+  /* Start DMA transmission */
+  ETH_DMATransmissionEnable(heth);
+  
+  /* Start DMA reception */
+  ETH_DMAReceptionEnable(heth);
+  
+  /* Set the ETH state to READY*/
+  heth->State= HAL_ETH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(heth);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop Ethernet MAC and DMA reception/transmission 
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
+{  
+  /* Process Locked */
+  __HAL_LOCK(heth);
+  
+  /* Set the ETH peripheral state to BUSY */
+  heth->State = HAL_ETH_STATE_BUSY;
+  
+  /* Stop DMA transmission */
+  ETH_DMATransmissionDisable(heth);
+  
+  /* Stop DMA reception */
+  ETH_DMAReceptionDisable(heth);
+  
+  /* Disable receive state machine of the MAC for reception from the MII */
+  ETH_MACReceptionDisable(heth);
+  
+  /* Flush Transmit FIFO */
+  ETH_FlushTransmitFIFO(heth);
+  
+  /* Disable transmit state machine of the MAC for transmission on the MII */
+  ETH_MACTransmissionDisable(heth);
+  
+  /* Set the ETH state*/
+  heth->State = HAL_ETH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(heth);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set ETH MAC Configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  macconf: MAC Configuration structure  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(heth);
+  
+  /* Set the ETH peripheral state to BUSY */
+  heth->State= HAL_ETH_STATE_BUSY;
+  
+  assert_param(IS_ETH_SPEED(heth->Init.Speed));
+  assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); 
+  
+  if (macconf != NULL)
+  {
+    /* Check the parameters */
+    assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
+    assert_param(IS_ETH_JABBER(macconf->Jabber));
+    assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
+    assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
+    assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
+    assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
+    assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
+    assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
+    assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
+    assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
+    assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
+    assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
+    assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
+    assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
+    assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
+    assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
+    assert_param(IS_ETH_PROMISCIOUS_MODE(macconf->PromiscuousMode));
+    assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
+    assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
+    assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
+    assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
+    assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
+    assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
+    assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
+    assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
+    assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
+    assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
+    
+    /*------------------------ ETHERNET MACCR Configuration --------------------*/
+    /* Get the ETHERNET MACCR value */
+    tmpreg = (heth->Instance)->MACCR;
+    /* Clear WD, PCE, PS, TE and RE bits */
+    tmpreg &= MACCR_CLEAR_MASK;
+    
+    tmpreg |= (uint32_t)(macconf->Watchdog | 
+                         macconf->Jabber | 
+                         macconf->InterFrameGap |
+                         macconf->CarrierSense |
+                         (heth->Init).Speed | 
+                         macconf->ReceiveOwn |
+                         macconf->LoopbackMode |
+                         (heth->Init).DuplexMode | 
+                         macconf->ChecksumOffload |    
+                         macconf->RetryTransmission | 
+                         macconf->AutomaticPadCRCStrip | 
+                         macconf->BackOffLimit | 
+                         macconf->DeferralCheck);
+    
+    /* Write to ETHERNET MACCR */
+    (heth->Instance)->MACCR = (uint32_t)tmpreg;
+    
+    /* Wait until the write operation will be taken into account :
+    at least four TX_CLK/RX_CLK clock cycles */
+    tmpreg = (heth->Instance)->MACCR;
+    HAL_Delay(ETH_REG_WRITE_DELAY);
+    (heth->Instance)->MACCR = tmpreg; 
+    
+    /*----------------------- ETHERNET MACFFR Configuration --------------------*/ 
+    /* Write to ETHERNET MACFFR */  
+    (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll | 
+                                          macconf->SourceAddrFilter |
+                                          macconf->PassControlFrames |
+                                          macconf->BroadcastFramesReception | 
+                                          macconf->DestinationAddrFilter |
+                                          macconf->PromiscuousMode |
+                                          macconf->MulticastFramesFilter |
+                                          macconf->UnicastFramesFilter);
+     
+     /* Wait until the write operation will be taken into account :
+     at least four TX_CLK/RX_CLK clock cycles */
+     tmpreg = (heth->Instance)->MACFFR;
+     HAL_Delay(ETH_REG_WRITE_DELAY);
+     (heth->Instance)->MACFFR = tmpreg;
+     
+     /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
+     /* Write to ETHERNET MACHTHR */
+     (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
+     
+     /* Write to ETHERNET MACHTLR */
+     (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
+     /*----------------------- ETHERNET MACFCR Configuration --------------------*/
+     
+     /* Get the ETHERNET MACFCR value */  
+     tmpreg = (heth->Instance)->MACFCR;
+     /* Clear xx bits */
+     tmpreg &= MACFCR_CLEAR_MASK;
+     
+     tmpreg |= (uint32_t)((macconf->PauseTime << 16) | 
+                          macconf->ZeroQuantaPause |
+                          macconf->PauseLowThreshold |
+                          macconf->UnicastPauseFrameDetect | 
+                          macconf->ReceiveFlowControl |
+                          macconf->TransmitFlowControl); 
+     
+     /* Write to ETHERNET MACFCR */
+     (heth->Instance)->MACFCR = (uint32_t)tmpreg;
+     
+     /* Wait until the write operation will be taken into account :
+     at least four TX_CLK/RX_CLK clock cycles */
+     tmpreg = (heth->Instance)->MACFCR;
+     HAL_Delay(ETH_REG_WRITE_DELAY);
+     (heth->Instance)->MACFCR = tmpreg;
+     
+     /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
+     (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | 
+                                              macconf->VLANTagIdentifier);
+      
+      /* Wait until the write operation will be taken into account :
+      at least four TX_CLK/RX_CLK clock cycles */
+      tmpreg = (heth->Instance)->MACVLANTR;
+      HAL_Delay(ETH_REG_WRITE_DELAY);
+      (heth->Instance)->MACVLANTR = tmpreg;
+  }
+  else /* macconf == NULL : here we just configure Speed and Duplex mode */
+  {
+    /*------------------------ ETHERNET MACCR Configuration --------------------*/
+    /* Get the ETHERNET MACCR value */
+    tmpreg = (heth->Instance)->MACCR;
+    
+    /* Clear FES and DM bits */
+    tmpreg &= ~((uint32_t)0x00004800);
+    
+    tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
+    
+    /* Write to ETHERNET MACCR */
+    (heth->Instance)->MACCR = (uint32_t)tmpreg;
+    
+    /* Wait until the write operation will be taken into account:
+    at least four TX_CLK/RX_CLK clock cycles */
+    tmpreg = (heth->Instance)->MACCR;
+    HAL_Delay(ETH_REG_WRITE_DELAY);
+    (heth->Instance)->MACCR = tmpreg;
+  }
+  
+  /* Set the ETH state to Ready */
+  heth->State= HAL_ETH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(heth);
+  
+  /* Return function status */
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Sets ETH DMA Configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  dmaconf: DMA Configuration structure  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
+{
+  uint32_t tmpreg = 0;
+
+  /* Process Locked */
+  __HAL_LOCK(heth);
+  
+  /* Set the ETH peripheral state to BUSY */
+  heth->State= HAL_ETH_STATE_BUSY;
+
+  /* Check parameters */
+  assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
+  assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
+  assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
+  assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
+  assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
+  assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
+  assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
+  assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
+  assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
+  assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
+  assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
+  assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
+  assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
+  assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
+  assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
+  assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
+  
+  /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
+  /* Get the ETHERNET DMAOMR value */
+  tmpreg = (heth->Instance)->DMAOMR;
+  /* Clear xx bits */
+  tmpreg &= DMAOMR_CLEAR_MASK;
+
+  tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | 
+                       dmaconf->ReceiveStoreForward |
+                       dmaconf->FlushReceivedFrame |
+                       dmaconf->TransmitStoreForward | 
+                       dmaconf->TransmitThresholdControl |
+                       dmaconf->ForwardErrorFrames |
+                       dmaconf->ForwardUndersizedGoodFrames |
+                       dmaconf->ReceiveThresholdControl |
+                       dmaconf->SecondFrameOperate);
+
+  /* Write to ETHERNET DMAOMR */
+  (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
+
+  /* Wait until the write operation will be taken into account:
+  at least four TX_CLK/RX_CLK clock cycles */
+  tmpreg = (heth->Instance)->DMAOMR;
+  HAL_Delay(ETH_REG_WRITE_DELAY);
+  (heth->Instance)->DMAOMR = tmpreg;
+
+  /*----------------------- ETHERNET DMABMR Configuration --------------------*/
+  (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | 
+                                         dmaconf->FixedBurst |
+                                         dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
+                                         dmaconf->TxDMABurstLength |
+                                         dmaconf->EnhancedDescriptorFormat |
+                                         (dmaconf->DescriptorSkipLength << 2) |
+                                         dmaconf->DMAArbitration | 
+                                         ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
+
+   /* Wait until the write operation will be taken into account:
+      at least four TX_CLK/RX_CLK clock cycles */
+   tmpreg = (heth->Instance)->DMABMR;
+   HAL_Delay(ETH_REG_WRITE_DELAY);
+   (heth->Instance)->DMABMR = tmpreg;
+
+   /* Set the ETH state to Ready */
+   heth->State= HAL_ETH_STATE_READY;
+   
+   /* Process Unlocked */
+   __HAL_UNLOCK(heth);
+   
+   /* Return function status */
+   return HAL_OK; 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Group4 Peripheral State functions 
+  *  @brief   Peripheral State functions 
+  *
+  @verbatim   
+  ===============================================================================
+                         ##### Peripheral State functions #####
+  ===============================================================================  
+  [..]
+  This subsection permits to get in run-time the status of the peripheral 
+  and the data flow.
+       (+) Get the ETH handle state:
+           HAL_ETH_GetState();
+           
+
+  @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the ETH HAL state
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL state
+  */
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
+{  
+  /* Return ETH state */
+  return heth->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Configures Ethernet MAC and DMA with default parameters.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  err: Ethernet Init error
+  * @retval HAL status
+  */
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
+{
+  ETH_MACInitTypeDef macinit;
+  ETH_DMAInitTypeDef dmainit;
+  uint32_t tmpreg = 0;
+  
+  if (err != ETH_SUCCESS) /* Auto-negotiation failed */
+  {
+    /* Set Ethernet duplex mode to Full-duplex */
+    (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
+    
+    /* Set Ethernet speed to 100M */
+    (heth->Init).Speed = ETH_SPEED_100M;
+  }
+  
+  /* Ethernet MAC default initialization **************************************/
+  macinit.Watchdog = ETH_WATCHDOG_ENABLE;
+  macinit.Jabber = ETH_JABBER_ENABLE;
+  macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
+  macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
+  macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
+  macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
+  if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
+  {
+    macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
+  }
+  else
+  {
+    macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
+  }
+  macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
+  macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
+  macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
+  macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
+  macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
+  macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
+  macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
+  macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
+  macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
+  macinit.PromiscuousMode = ETH_PROMISCIOUSMODE_DISABLE;
+  macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
+  macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
+  macinit.HashTableHigh = 0x0;
+  macinit.HashTableLow = 0x0;
+  macinit.PauseTime = 0x0;
+  macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
+  macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
+  macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
+  macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
+  macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
+  macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
+  macinit.VLANTagIdentifier = 0x0;
+  
+  /*------------------------ ETHERNET MACCR Configuration --------------------*/
+  /* Get the ETHERNET MACCR value */
+  tmpreg = (heth->Instance)->MACCR;
+  /* Clear WD, PCE, PS, TE and RE bits */
+  tmpreg &= MACCR_CLEAR_MASK;
+  /* Set the WD bit according to ETH Watchdog value */
+  /* Set the JD: bit according to ETH Jabber value */
+  /* Set the IFG bit according to ETH InterFrameGap value */
+  /* Set the DCRS bit according to ETH CarrierSense value */
+  /* Set the FES bit according to ETH Speed value */ 
+  /* Set the DO bit according to ETH ReceiveOwn value */ 
+  /* Set the LM bit according to ETH LoopbackMode value */
+  /* Set the DM bit according to ETH Mode value */ 
+  /* Set the IPCO bit according to ETH ChecksumOffload value */
+  /* Set the DR bit according to ETH RetryTransmission value */
+  /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
+  /* Set the BL bit according to ETH BackOffLimit value */
+  /* Set the DC bit according to ETH DeferralCheck value */
+  tmpreg |= (uint32_t)(macinit.Watchdog | 
+                       macinit.Jabber | 
+                       macinit.InterFrameGap |
+                       macinit.CarrierSense |
+                       (heth->Init).Speed | 
+                       macinit.ReceiveOwn |
+                       macinit.LoopbackMode |
+                       (heth->Init).DuplexMode | 
+                       macinit.ChecksumOffload |    
+                       macinit.RetryTransmission | 
+                       macinit.AutomaticPadCRCStrip | 
+                       macinit.BackOffLimit | 
+                       macinit.DeferralCheck);
+  
+  /* Write to ETHERNET MACCR */
+  (heth->Instance)->MACCR = (uint32_t)tmpreg;
+  
+  /* Wait until the write operation will be taken into account:
+     at least four TX_CLK/RX_CLK clock cycles */
+  tmpreg = (heth->Instance)->MACCR;
+  HAL_Delay(ETH_REG_WRITE_DELAY);
+  (heth->Instance)->MACCR = tmpreg; 
+  
+  /*----------------------- ETHERNET MACFFR Configuration --------------------*/ 
+  /* Set the RA bit according to ETH ReceiveAll value */
+  /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
+  /* Set the PCF bit according to ETH PassControlFrames value */
+  /* Set the DBF bit according to ETH BroadcastFramesReception value */
+  /* Set the DAIF bit according to ETH DestinationAddrFilter value */
+  /* Set the PR bit according to ETH PromiscuousMode value */
+  /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
+  /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
+  /* Write to ETHERNET MACFFR */  
+  (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll | 
+                                        macinit.SourceAddrFilter |
+                                        macinit.PassControlFrames |
+                                        macinit.BroadcastFramesReception | 
+                                        macinit.DestinationAddrFilter |
+                                        macinit.PromiscuousMode |
+                                        macinit.MulticastFramesFilter |
+                                        macinit.UnicastFramesFilter);
+   
+   /* Wait until the write operation will be taken into account:
+      at least four TX_CLK/RX_CLK clock cycles */
+   tmpreg = (heth->Instance)->MACFFR;
+   HAL_Delay(ETH_REG_WRITE_DELAY);
+   (heth->Instance)->MACFFR = tmpreg;
+   
+   /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
+   /* Write to ETHERNET MACHTHR */
+   (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
+   
+   /* Write to ETHERNET MACHTLR */
+   (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
+   /*----------------------- ETHERNET MACFCR Configuration -------------------*/
+   
+   /* Get the ETHERNET MACFCR value */  
+   tmpreg = (heth->Instance)->MACFCR;
+   /* Clear xx bits */
+   tmpreg &= MACFCR_CLEAR_MASK;
+   
+   /* Set the PT bit according to ETH PauseTime value */
+   /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
+   /* Set the PLT bit according to ETH PauseLowThreshold value */
+   /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
+   /* Set the RFE bit according to ETH ReceiveFlowControl value */
+   /* Set the TFE bit according to ETH TransmitFlowControl value */ 
+   tmpreg |= (uint32_t)((macinit.PauseTime << 16) | 
+                        macinit.ZeroQuantaPause |
+                        macinit.PauseLowThreshold |
+                        macinit.UnicastPauseFrameDetect | 
+                        macinit.ReceiveFlowControl |
+                        macinit.TransmitFlowControl); 
+   
+   /* Write to ETHERNET MACFCR */
+   (heth->Instance)->MACFCR = (uint32_t)tmpreg;
+   
+   /* Wait until the write operation will be taken into account:
+   at least four TX_CLK/RX_CLK clock cycles */
+   tmpreg = (heth->Instance)->MACFCR;
+   HAL_Delay(ETH_REG_WRITE_DELAY);
+   (heth->Instance)->MACFCR = tmpreg;
+   
+   /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
+   /* Set the ETV bit according to ETH VLANTagComparison value */
+   /* Set the VL bit according to ETH VLANTagIdentifier value */  
+   (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | 
+                                            macinit.VLANTagIdentifier);
+    
+    /* Wait until the write operation will be taken into account:
+       at least four TX_CLK/RX_CLK clock cycles */
+    tmpreg = (heth->Instance)->MACVLANTR;
+    HAL_Delay(ETH_REG_WRITE_DELAY);
+    (heth->Instance)->MACVLANTR = tmpreg;
+    
+    /* Ethernet DMA default initialization ************************************/
+    dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
+    dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
+    dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
+    dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;  
+    dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
+    dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
+    dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
+    dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
+    dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
+    dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
+    dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
+    dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
+    dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
+    dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
+    dmainit.DescriptorSkipLength = 0x0;
+    dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
+    
+    /* Get the ETHERNET DMAOMR value */
+    tmpreg = (heth->Instance)->DMAOMR;
+    /* Clear xx bits */
+    tmpreg &= DMAOMR_CLEAR_MASK;
+    
+    /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
+    /* Set the RSF bit according to ETH ReceiveStoreForward value */
+    /* Set the DFF bit according to ETH FlushReceivedFrame value */
+    /* Set the TSF bit according to ETH TransmitStoreForward value */
+    /* Set the TTC bit according to ETH TransmitThresholdControl value */
+    /* Set the FEF bit according to ETH ForwardErrorFrames value */
+    /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
+    /* Set the RTC bit according to ETH ReceiveThresholdControl value */
+    /* Set the OSF bit according to ETH SecondFrameOperate value */
+    tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | 
+                         dmainit.ReceiveStoreForward |
+                         dmainit.FlushReceivedFrame |
+                         dmainit.TransmitStoreForward | 
+                         dmainit.TransmitThresholdControl |
+                         dmainit.ForwardErrorFrames |
+                         dmainit.ForwardUndersizedGoodFrames |
+                         dmainit.ReceiveThresholdControl |
+                         dmainit.SecondFrameOperate);
+    
+    /* Write to ETHERNET DMAOMR */
+    (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
+    
+    /* Wait until the write operation will be taken into account:
+       at least four TX_CLK/RX_CLK clock cycles */
+    tmpreg = (heth->Instance)->DMAOMR;
+    HAL_Delay(ETH_REG_WRITE_DELAY);
+    (heth->Instance)->DMAOMR = tmpreg;
+    
+    /*----------------------- ETHERNET DMABMR Configuration ------------------*/
+    /* Set the AAL bit according to ETH AddressAlignedBeats value */
+    /* Set the FB bit according to ETH FixedBurst value */
+    /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
+    /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
+    /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
+    /* Set the DSL bit according to ETH DesciptorSkipLength value */
+    /* Set the PR and DA bits according to ETH DMAArbitration value */
+    (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | 
+                                          dmainit.FixedBurst |
+                                          dmainit.RxDMABurstLength |    /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
+                                          dmainit.TxDMABurstLength |
+                                          dmainit.EnhancedDescriptorFormat |
+                                          (dmainit.DescriptorSkipLength << 2) |
+                                          dmainit.DMAArbitration |
+                                          ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
+     
+     /* Wait until the write operation will be taken into account:
+        at least four TX_CLK/RX_CLK clock cycles */
+     tmpreg = (heth->Instance)->DMABMR;
+     HAL_Delay(ETH_REG_WRITE_DELAY);
+     (heth->Instance)->DMABMR = tmpreg;
+
+     if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
+     {
+       /* Enable the Ethernet Rx Interrupt */
+       __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
+     }
+
+     /* Initialize MAC address in ethernet MAC */ 
+     ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
+}
+
+/**
+  * @brief  Configures the selected MAC address.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  MacAddr: The MAC address to configure
+  *          This parameter can be one of the following values:
+  *             @arg ETH_MAC_Address0: MAC Address0 
+  *             @arg ETH_MAC_Address1: MAC Address1 
+  *             @arg ETH_MAC_Address2: MAC Address2
+  *             @arg ETH_MAC_Address3: MAC Address3
+  * @param  Addr: Pointer to MAC address buffer data (6 bytes)
+  * @retval HAL status
+  */
+static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
+{
+  uint32_t tmpreg;
+  
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
+  
+  /* Calculate the selected MAC address high register */
+  tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
+  /* Load the selected MAC address high register */
+  (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
+  /* Calculate the selected MAC address low register */
+  tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
+  
+  /* Load the selected MAC address low register */
+  (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
+}
+
+/**
+  * @brief  Enables the MAC transmission.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module  
+  * @retval None
+  */
+static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
+{ 
+  __IO uint32_t tmpreg = 0;
+  
+  /* Enable the MAC transmission */
+  (heth->Instance)->MACCR |= ETH_MACCR_TE;
+  
+  /* Wait until the write operation will be taken into account:
+     at least four TX_CLK/RX_CLK clock cycles */
+  tmpreg = (heth->Instance)->MACCR;
+  HAL_Delay(ETH_REG_WRITE_DELAY);
+  (heth->Instance)->MACCR = tmpreg;
+}
+
+/**
+  * @brief  Disables the MAC transmission.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module  
+  * @retval None
+  */
+static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
+{ 
+  __IO uint32_t tmpreg = 0;
+  
+  /* Disable the MAC transmission */
+  (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
+  
+  /* Wait until the write operation will be taken into account:
+     at least four TX_CLK/RX_CLK clock cycles */
+  tmpreg = (heth->Instance)->MACCR;
+  HAL_Delay(ETH_REG_WRITE_DELAY);
+  (heth->Instance)->MACCR = tmpreg;
+}
+
+/**
+  * @brief  Enables the MAC reception.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module   
+  * @retval None
+  */
+static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
+{ 
+  __IO uint32_t tmpreg = 0;
+  
+  /* Enable the MAC reception */
+  (heth->Instance)->MACCR |= ETH_MACCR_RE;
+  
+  /* Wait until the write operation will be taken into account:
+     at least four TX_CLK/RX_CLK clock cycles */
+  tmpreg = (heth->Instance)->MACCR;
+  HAL_Delay(ETH_REG_WRITE_DELAY);
+  (heth->Instance)->MACCR = tmpreg;
+}
+
+/**
+  * @brief  Disables the MAC reception.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module   
+  * @retval None
+  */
+static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
+{ 
+  __IO uint32_t tmpreg = 0;
+  
+  /* Disable the MAC reception */
+  (heth->Instance)->MACCR &= ~ETH_MACCR_RE; 
+  
+  /* Wait until the write operation will be taken into account:
+     at least four TX_CLK/RX_CLK clock cycles */
+  tmpreg = (heth->Instance)->MACCR;
+  HAL_Delay(ETH_REG_WRITE_DELAY);
+  (heth->Instance)->MACCR = tmpreg;
+}
+
+/**
+  * @brief  Enables the DMA transmission.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module   
+  * @retval None
+  */
+static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
+{
+  /* Enable the DMA transmission */
+  (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;  
+}
+
+/**
+  * @brief  Disables the DMA transmission.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module   
+  * @retval None
+  */
+static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
+{ 
+  /* Disable the DMA transmission */
+  (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
+}
+
+/**
+  * @brief  Enables the DMA reception.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module 
+  * @retval None
+  */
+static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
+{  
+  /* Enable the DMA reception */
+  (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;  
+}
+
+/**
+  * @brief  Disables the DMA reception.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module 
+  * @retval None
+  */
+static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
+{ 
+  /* Disable the DMA reception */
+  (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
+}
+
+/**
+  * @brief  Clears the ETHERNET transmit FIFO.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
+{
+  __IO uint32_t tmpreg = 0;
+  
+  /* Set the Flush Transmit FIFO bit */
+  (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
+  
+  /* Wait until the write operation will be taken into account:
+     at least four TX_CLK/RX_CLK clock cycles */
+  tmpreg = (heth->Instance)->DMAOMR;
+  HAL_Delay(ETH_REG_WRITE_DELAY);
+  (heth->Instance)->DMAOMR = tmpreg;
+}
+
+/**
+  * @}
+  */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* HAL_ETH_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,2193 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_eth.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of ETH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_ETH_H
+#define __STM32F4xx_HAL_ETH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ETH
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** 
+  * @brief  HAL State structures definition  
+  */ 
+typedef enum
+{
+  HAL_ETH_STATE_RESET             = 0x00,    /*!< Peripheral not yet Initialized or disabled         */
+  HAL_ETH_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
+  HAL_ETH_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */
+  HAL_ETH_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */
+  HAL_ETH_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
+  HAL_ETH_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
+  HAL_ETH_STATE_BUSY_WR           = 0x42,    /*!< Write process is ongoing                           */
+  HAL_ETH_STATE_BUSY_RD           = 0x82,    /*!< Read process is ongoing                            */
+  HAL_ETH_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
+  HAL_ETH_STATE_ERROR             = 0x04     /*!< Reception process is ongoing                       */
+}HAL_ETH_StateTypeDef;
+
+/** 
+  * @brief  ETH Init Structure definition  
+  */
+
+typedef struct
+{
+  uint32_t             AutoNegotiation;           /*!< Selects or not the AutoNegotiation mode for the external PHY
+                                                           The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
+                                                           and the mode (half/full-duplex).
+                                                           This parameter can be a value of @ref ETH_AutoNegotiation */
+
+  uint32_t             Speed;                     /*!< Sets the Ethernet speed: 10/100 Mbps.
+                                                           This parameter can be a value of @ref ETH_Speed */
+
+  uint32_t             DuplexMode;                /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+                                                           This parameter can be a value of @ref ETH_Duplex_Mode */
+  
+  uint16_t             PhyAddress;                /*!< Ethernet PHY address.
+                                                           This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
+  
+  uint8_t             *MACAddr;                   /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
+  
+  uint32_t             RxMode;                    /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
+                                                           This parameter can be a value of @ref ETH_Rx_Mode */
+  
+  uint32_t             ChecksumMode;              /*!< Selects if the checksum is check by hardware or by software. 
+                                                         This parameter can be a value of @ref ETH_Checksum_Mode */
+  
+  uint32_t             MediaInterface    ;               /*!< Selects the media-independent interface or the reduced media-independent interface. 
+                                                         This parameter can be a value of @ref ETH_Media_Interface */
+
+} ETH_InitTypeDef;
+
+
+ /** 
+  * @brief  ETH MAC Configuration Structure definition  
+  */
+
+typedef struct
+{
+  uint32_t             Watchdog;                  /*!< Selects or not the Watchdog timer
+                                                           When enabled, the MAC allows no more then 2048 bytes to be received.
+                                                           When disabled, the MAC can receive up to 16384 bytes.
+                                                           This parameter can be a value of @ref ETH_watchdog */  
+
+  uint32_t             Jabber;                    /*!< Selects or not Jabber timer
+                                                           When enabled, the MAC allows no more then 2048 bytes to be sent.
+                                                           When disabled, the MAC can send up to 16384 bytes.
+                                                           This parameter can be a value of @ref ETH_Jabber */
+
+  uint32_t             InterFrameGap;             /*!< Selects the minimum IFG between frames during transmission.
+                                                           This parameter can be a value of @ref ETH_Inter_Frame_Gap */   
+
+  uint32_t             CarrierSense;              /*!< Selects or not the Carrier Sense.
+                                                           This parameter can be a value of @ref ETH_Carrier_Sense */
+
+  uint32_t             ReceiveOwn;                /*!< Selects or not the ReceiveOwn,
+                                                           ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
+                                                           in Half-Duplex mode.
+                                                           This parameter can be a value of @ref ETH_Receive_Own */  
+
+  uint32_t             LoopbackMode;              /*!< Selects or not the internal MAC MII Loopback mode.
+                                                           This parameter can be a value of @ref ETH_Loop_Back_Mode */  
+
+  uint32_t             ChecksumOffload;           /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
+                                                           This parameter can be a value of @ref ETH_Checksum_Offload */    
+
+  uint32_t             RetryTransmission;         /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
+                                                           when a collision occurs (Half-Duplex mode).
+                                                           This parameter can be a value of @ref ETH_Retry_Transmission */
+
+  uint32_t             AutomaticPadCRCStrip;      /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
+                                                           This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ 
+
+  uint32_t             BackOffLimit;              /*!< Selects the BackOff limit value.
+                                                           This parameter can be a value of @ref ETH_Back_Off_Limit */
+
+  uint32_t             DeferralCheck;             /*!< Selects or not the deferral check function (Half-Duplex mode).
+                                                           This parameter can be a value of @ref ETH_Deferral_Check */                                                                                                        
+
+  uint32_t             ReceiveAll;                /*!< Selects or not all frames reception by the MAC (No filtering).
+                                                           This parameter can be a value of @ref ETH_Receive_All */   
+
+  uint32_t             SourceAddrFilter;          /*!< Selects the Source Address Filter mode.                                                           
+                                                           This parameter can be a value of @ref ETH_Source_Addr_Filter */                  
+
+  uint32_t             PassControlFrames;         /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)                                                          
+                                                           This parameter can be a value of @ref ETH_Pass_Control_Frames */ 
+
+  uint32_t             BroadcastFramesReception;  /*!< Selects or not the reception of Broadcast Frames.
+                                                           This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
+
+  uint32_t             DestinationAddrFilter;     /*!< Sets the destination filter mode for both unicast and multicast frames.
+                                                           This parameter can be a value of @ref ETH_Destination_Addr_Filter */ 
+
+  uint32_t             PromiscuousMode;           /*!< Selects or not the Promiscuous Mode
+                                                           This parameter can be a value of @ref ETH_Promiscuous_Mode */
+
+  uint32_t             MulticastFramesFilter;     /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
+                                                           This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ 
+
+  uint32_t             UnicastFramesFilter;       /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
+                                                           This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ 
+
+  uint32_t             HashTableHigh;             /*!< This field holds the higher 32 bits of Hash table.
+                                                           This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
+
+  uint32_t             HashTableLow;              /*!< This field holds the lower 32 bits of Hash table.
+                                                           This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF  */    
+
+  uint32_t             PauseTime;                 /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. 
+                                                           This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
+
+  uint32_t             ZeroQuantaPause;           /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
+                                                           This parameter can be a value of @ref ETH_Zero_Quanta_Pause */  
+
+  uint32_t             PauseLowThreshold;         /*!< This field configures the threshold of the PAUSE to be checked for
+                                                           automatic retransmission of PAUSE Frame.
+                                                           This parameter can be a value of @ref ETH_Pause_Low_Threshold */
+                                                           
+  uint32_t             UnicastPauseFrameDetect;   /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
+                                                           unicast address and unique multicast address).
+                                                           This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */  
+
+  uint32_t             ReceiveFlowControl;        /*!< Enables or disables the MAC to decode the received Pause frame and
+                                                           disable its transmitter for a specified time (Pause Time)
+                                                           This parameter can be a value of @ref ETH_Receive_Flow_Control */
+
+  uint32_t             TransmitFlowControl;       /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
+                                                           or the MAC back-pressure operation (Half-Duplex mode)
+                                                           This parameter can be a value of @ref ETH_Transmit_Flow_Control */     
+
+  uint32_t             VLANTagComparison;         /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
+                                                           comparison and filtering.
+                                                           This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ 
+
+  uint32_t             VLANTagIdentifier;         /*!< Holds the VLAN tag identifier for receive frames */
+
+} ETH_MACInitTypeDef;
+
+
+/** 
+  * @brief  ETH DMA Configuration Structure definition  
+  */
+
+typedef struct
+{
+ uint32_t              DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
+                                                             This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ 
+
+  uint32_t             ReceiveStoreForward;         /*!< Enables or disables the Receive store and forward mode.
+                                                             This parameter can be a value of @ref ETH_Receive_Store_Forward */ 
+
+  uint32_t             FlushReceivedFrame;          /*!< Enables or disables the flushing of received frames.
+                                                             This parameter can be a value of @ref ETH_Flush_Received_Frame */ 
+
+  uint32_t             TransmitStoreForward;        /*!< Enables or disables Transmit store and forward mode.
+                                                             This parameter can be a value of @ref ETH_Transmit_Store_Forward */ 
+
+  uint32_t             TransmitThresholdControl;    /*!< Selects or not the Transmit Threshold Control.
+                                                             This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
+
+  uint32_t             ForwardErrorFrames;          /*!< Selects or not the forward to the DMA of erroneous frames.
+                                                             This parameter can be a value of @ref ETH_Forward_Error_Frames */
+
+  uint32_t             ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
+                                                             and length less than 64 bytes) including pad-bytes and CRC)
+                                                             This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
+
+  uint32_t             ReceiveThresholdControl;     /*!< Selects the threshold level of the Receive FIFO.
+                                                             This parameter can be a value of @ref ETH_Receive_Threshold_Control */
+
+  uint32_t             SecondFrameOperate;          /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
+                                                             frame of Transmit data even before obtaining the status for the first frame.
+                                                             This parameter can be a value of @ref ETH_Second_Frame_Operate */
+
+  uint32_t             AddressAlignedBeats;         /*!< Enables or disables the Address Aligned Beats.
+                                                             This parameter can be a value of @ref ETH_Address_Aligned_Beats */
+
+  uint32_t             FixedBurst;                  /*!< Enables or disables the AHB Master interface fixed burst transfers.
+                                                             This parameter can be a value of @ref ETH_Fixed_Burst */
+                       
+  uint32_t             RxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
+                                                             This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 
+
+  uint32_t             TxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
+                                                             This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
+  
+  uint32_t             EnhancedDescriptorFormat;    /*!< Enables the enhanced descriptor format.
+                                                             This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
+
+  uint32_t             DescriptorSkipLength;        /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
+                                                             This parameter must be a number between Min_Data = 0 and Max_Data = 32 */                                                             
+
+  uint32_t             DMAArbitration;              /*!< Selects the DMA Tx/Rx arbitration.
+                                                             This parameter can be a value of @ref ETH_DMA_Arbitration */  
+} ETH_DMAInitTypeDef;
+
+
+/** 
+  * @brief  ETH DMA Descriptors data structure definition
+  */ 
+
+typedef struct  
+{
+  __IO uint32_t   Status;           /*!< Status */
+  
+  uint32_t   ControlBufferSize;     /*!< Control and Buffer1, Buffer2 lengths */
+  
+  uint32_t   Buffer1Addr;           /*!< Buffer1 address pointer */
+  
+  uint32_t   Buffer2NextDescAddr;   /*!< Buffer2 or next descriptor address pointer */
+  
+  /*!< Enhanced ETHERNET DMA PTP Descriptors */
+  uint32_t   ExtendedStatus;        /*!< Extended status for PTP receive descriptor */
+  
+  uint32_t   Reserved1;             /*!< Reserved */
+  
+  uint32_t   TimeStampLow;          /*!< Time Stamp Low value for transmit and receive */
+  
+  uint32_t   TimeStampHigh;         /*!< Time Stamp High value for transmit and receive */
+
+} ETH_DMADescTypeDef;
+
+
+/** 
+  * @brief  Received Frame Informations structure definition
+  */ 
+typedef struct  
+{
+  ETH_DMADescTypeDef *FSRxDesc;          /*!< First Segment Rx Desc */
+  
+  ETH_DMADescTypeDef *LSRxDesc;          /*!< Last Segment Rx Desc */
+  
+  uint32_t  SegCount;                    /*!< Segment count */
+  
+  uint32_t length;                       /*!< Frame length */
+  
+  uint32_t buffer;                       /*!< Frame buffer */
+
+} ETH_DMARxFrameInfos;
+
+
+/** 
+  * @brief  ETH Handle Structure definition  
+  */
+  
+typedef struct
+{
+  ETH_TypeDef                *Instance;     /*!< Register base address       */
+  
+  ETH_InitTypeDef            Init;          /*!< Ethernet Init Configuration */
+  
+  uint32_t                   LinkStatus;    /*!< Ethernet link status        */
+  
+  ETH_DMADescTypeDef         *RxDesc;       /*!< Rx descriptor to Get        */
+  
+  ETH_DMADescTypeDef         *TxDesc;       /*!< Tx descriptor to Set        */
+  
+  ETH_DMARxFrameInfos        RxFrameInfos;  /*!< last Rx frame infos         */
+  
+  __IO HAL_ETH_StateTypeDef  State;         /*!< ETH communication state     */
+  
+  HAL_LockTypeDef            Lock;          /*!< ETH Lock                    */
+
+} ETH_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
+
+/* Delay to wait when writing to some Ethernet registers */
+#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
+
+
+/* ETHERNET Errors */
+#define  ETH_SUCCESS            ((uint32_t)0)
+#define  ETH_ERROR              ((uint32_t)1)
+
+/** @defgroup ETH_Buffers_setting 
+  * @{
+  */ 
+#define ETH_MAX_PACKET_SIZE    ((uint32_t)1524)    /*!< ETH_HEADER + ETH_EXTRA + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER               ((uint32_t)14)    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC                   ((uint32_t)4)    /*!< Ethernet CRC */
+#define ETH_EXTRA                 ((uint32_t)2)    /*!< Extra bytes in some cases */   
+#define VLAN_TAG                  ((uint32_t)4)    /*!< optional 802.1q VLAN Tag */
+#define MIN_ETH_PAYLOAD          ((uint32_t)46)    /*!< Minimum Ethernet payload size */
+#define MAX_ETH_PAYLOAD        ((uint32_t)1500)    /*!< Maximum Ethernet payload size */
+#define JUMBO_FRAME_PAYLOAD    ((uint32_t)9000)    /*!< Jumbo frame payload size */      
+
+ /* Ethernet driver receive buffers are organized in a chained linked-list, when
+    an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
+    to the driver receive buffers memory.
+
+    Depending on the size of the received ethernet packet and the size of 
+    each ethernet driver receive buffer, the received packet can take one or more
+    ethernet driver receive buffer. 
+
+    In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE 
+    and the total count of the driver receive buffers ETH_RXBUFNB.
+
+    The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as 
+    example, they can be reconfigured in the application layer to fit the application 
+    needs */ 
+
+/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
+   packet */
+#ifndef ETH_RX_BUF_SIZE
+ #define ETH_RX_BUF_SIZE         ETH_MAX_PACKET_SIZE 
+#endif
+
+/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ 
+#ifndef ETH_RXBUFNB
+ #define ETH_RXBUFNB             ((uint32_t)5     /*  5 Rx buffers of size ETH_RX_BUF_SIZE */
+#endif
+
+
+ /* Ethernet driver transmit buffers are organized in a chained linked-list, when
+    an ethernet packet is transmitted, Tx-DMA will transfer the packet from the 
+    driver transmit buffers memory to the TxFIFO.
+
+    Depending on the size of the Ethernet packet to be transmitted and the size of 
+    each ethernet driver transmit buffer, the packet to be transmitted can take 
+    one or more ethernet driver transmit buffer. 
+
+    In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE 
+    and the total count of the driver transmit buffers ETH_TXBUFNB.
+
+    The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as 
+    example, they can be reconfigured in the application layer to fit the application 
+    needs */ 
+
+/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
+   packet */
+#ifndef ETH_TX_BUF_SIZE 
+ #define ETH_TX_BUF_SIZE         ETH_MAX_PACKET_SIZE
+#endif
+
+/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ 
+#ifndef ETH_TXBUFNB
+ #define ETH_TXBUFNB             ((uint32_t)5      /* 5  Tx buffers of size ETH_TX_BUF_SIZE */
+#endif
+
+
+/*
+   DMA Tx Desciptor
+  -----------------------------------------------------------------------------------------------
+  TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
+  -----------------------------------------------------------------------------------------------
+  TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
+  -----------------------------------------------------------------------------------------------
+  TDES2 |                         Buffer1 Address [31:0]                                         |
+  -----------------------------------------------------------------------------------------------
+  TDES3 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |
+  -----------------------------------------------------------------------------------------------
+*/
+
+/** 
+  * @brief  Bit definition of TDES0 register: DMA Tx descriptor status register
+  */ 
+#define ETH_DMATXDESC_OWN                     ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXDESC_IC                      ((uint32_t)0x40000000)  /*!< Interrupt on Completion */
+#define ETH_DMATXDESC_LS                      ((uint32_t)0x20000000)  /*!< Last Segment */
+#define ETH_DMATXDESC_FS                      ((uint32_t)0x10000000)  /*!< First Segment */
+#define ETH_DMATXDESC_DC                      ((uint32_t)0x08000000)  /*!< Disable CRC */
+#define ETH_DMATXDESC_DP                      ((uint32_t)0x04000000)  /*!< Disable Padding */
+#define ETH_DMATXDESC_TTSE                    ((uint32_t)0x02000000)  /*!< Transmit Time Stamp Enable */
+#define ETH_DMATXDESC_CIC                     ((uint32_t)0x00C00000)  /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATXDESC_CIC_BYPASS              ((uint32_t)0x00000000)  /*!< Do Nothing: Checksum Engine is bypassed */ 
+#define ETH_DMATXDESC_CIC_IPV4HEADER          ((uint32_t)0x00400000)  /*!< IPV4 header Checksum Insertion */ 
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT  ((uint32_t)0x00800000)  /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL     ((uint32_t)0x00C00000)  /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 
+#define ETH_DMATXDESC_TER                     ((uint32_t)0x00200000)  /*!< Transmit End of Ring */
+#define ETH_DMATXDESC_TCH                     ((uint32_t)0x00100000)  /*!< Second Address Chained */
+#define ETH_DMATXDESC_TTSS                    ((uint32_t)0x00020000)  /*!< Tx Time Stamp Status */
+#define ETH_DMATXDESC_IHE                     ((uint32_t)0x00010000)  /*!< IP Header Error */
+#define ETH_DMATXDESC_ES                      ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define ETH_DMATXDESC_JT                      ((uint32_t)0x00004000)  /*!< Jabber Timeout */
+#define ETH_DMATXDESC_FF                      ((uint32_t)0x00002000)  /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define ETH_DMATXDESC_PCE                     ((uint32_t)0x00001000)  /*!< Payload Checksum Error */
+#define ETH_DMATXDESC_LCA                     ((uint32_t)0x00000800)  /*!< Loss of Carrier: carrier lost during transmission */
+#define ETH_DMATXDESC_NC                      ((uint32_t)0x00000400)  /*!< No Carrier: no carrier signal from the transceiver */
+#define ETH_DMATXDESC_LCO                     ((uint32_t)0x00000200)  /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATXDESC_EC                      ((uint32_t)0x00000100)  /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATXDESC_VF                      ((uint32_t)0x00000080)  /*!< VLAN Frame */
+#define ETH_DMATXDESC_CC                      ((uint32_t)0x00000078)  /*!< Collision Count */
+#define ETH_DMATXDESC_ED                      ((uint32_t)0x00000004)  /*!< Excessive Deferral */
+#define ETH_DMATXDESC_UF                      ((uint32_t)0x00000002)  /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATXDESC_DB                      ((uint32_t)0x00000001)  /*!< Deferred Bit */
+
+/** 
+  * @brief  Bit definition of TDES1 register
+  */ 
+#define ETH_DMATXDESC_TBS2  ((uint32_t)0x1FFF0000)  /*!< Transmit Buffer2 Size */
+#define ETH_DMATXDESC_TBS1  ((uint32_t)0x00001FFF)  /*!< Transmit Buffer1 Size */
+
+/** 
+  * @brief  Bit definition of TDES2 register
+  */ 
+#define ETH_DMATXDESC_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */
+
+/** 
+  * @brief  Bit definition of TDES3 register
+  */ 
+#define ETH_DMATXDESC_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */
+
+  /*---------------------------------------------------------------------------------------------
+  TDES6 |                         Transmit Time Stamp Low [31:0]                                 |
+  -----------------------------------------------------------------------------------------------
+  TDES7 |                         Transmit Time Stamp High [31:0]                                |
+  ----------------------------------------------------------------------------------------------*/
+
+/* Bit definition of TDES6 register */
+ #define ETH_DMAPTPTXDESC_TTSL  ((uint32_t)0xFFFFFFFF)  /* Transmit Time Stamp Low */
+
+/* Bit definition of TDES7 register */
+ #define ETH_DMAPTPTXDESC_TTSH  ((uint32_t)0xFFFFFFFF)  /* Transmit Time Stamp High */
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ETH_DMA_Rx_descriptor 
+  * @{
+  */
+
+/*
+  DMA Rx Descriptor
+  --------------------------------------------------------------------------------------------------------------------
+  RDES0 | OWN(31) |                                             Status [30:0]                                          |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES2 |                                       Buffer1 Address [31:0]                                                 |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES3 |                          Buffer2 Address [31:0] / Next Descriptor Address [31:0]                             |
+  ---------------------------------------------------------------------------------------------------------------------
+*/
+
+/** 
+  * @brief  Bit definition of RDES0 register: DMA Rx descriptor status register
+  */ 
+#define ETH_DMARXDESC_OWN         ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine  */
+#define ETH_DMARXDESC_AFM         ((uint32_t)0x40000000)  /*!< DA Filter Fail for the rx frame  */
+#define ETH_DMARXDESC_FL          ((uint32_t)0x3FFF0000)  /*!< Receive descriptor frame length  */
+#define ETH_DMARXDESC_ES          ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define ETH_DMARXDESC_DE          ((uint32_t)0x00004000)  /*!< Descriptor error: no more descriptors for receive frame  */
+#define ETH_DMARXDESC_SAF         ((uint32_t)0x00002000)  /*!< SA Filter Fail for the received frame */
+#define ETH_DMARXDESC_LE          ((uint32_t)0x00001000)  /*!< Frame size not matching with length field */
+#define ETH_DMARXDESC_OE          ((uint32_t)0x00000800)  /*!< Overflow Error: Frame was damaged due to buffer overflow */
+#define ETH_DMARXDESC_VLAN        ((uint32_t)0x00000400)  /*!< VLAN Tag: received frame is a VLAN frame */
+#define ETH_DMARXDESC_FS          ((uint32_t)0x00000200)  /*!< First descriptor of the frame  */
+#define ETH_DMARXDESC_LS          ((uint32_t)0x00000100)  /*!< Last descriptor of the frame  */ 
+#define ETH_DMARXDESC_IPV4HCE     ((uint32_t)0x00000080)  /*!< IPC Checksum Error: Rx Ipv4 header checksum error   */    
+#define ETH_DMARXDESC_LC          ((uint32_t)0x00000040)  /*!< Late collision occurred during reception   */
+#define ETH_DMARXDESC_FT          ((uint32_t)0x00000020)  /*!< Frame type - Ethernet, otherwise 802.3    */
+#define ETH_DMARXDESC_RWT         ((uint32_t)0x00000010)  /*!< Receive Watchdog Timeout: watchdog timer expired during reception    */
+#define ETH_DMARXDESC_RE          ((uint32_t)0x00000008)  /*!< Receive error: error reported by MII interface  */
+#define ETH_DMARXDESC_DBE         ((uint32_t)0x00000004)  /*!< Dribble bit error: frame contains non int multiple of 8 bits  */
+#define ETH_DMARXDESC_CE          ((uint32_t)0x00000002)  /*!< CRC error */
+#define ETH_DMARXDESC_MAMPCE      ((uint32_t)0x00000001)  /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+
+/** 
+  * @brief  Bit definition of RDES1 register
+  */ 
+#define ETH_DMARXDESC_DIC   ((uint32_t)0x80000000)  /*!< Disable Interrupt on Completion */
+#define ETH_DMARXDESC_RBS2  ((uint32_t)0x1FFF0000)  /*!< Receive Buffer2 Size */
+#define ETH_DMARXDESC_RER   ((uint32_t)0x00008000)  /*!< Receive End of Ring */
+#define ETH_DMARXDESC_RCH   ((uint32_t)0x00004000)  /*!< Second Address Chained */
+#define ETH_DMARXDESC_RBS1  ((uint32_t)0x00001FFF)  /*!< Receive Buffer1 Size */
+
+/** 
+  * @brief  Bit definition of RDES2 register  
+  */ 
+#define ETH_DMARXDESC_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */
+
+/** 
+  * @brief  Bit definition of RDES3 register  
+  */ 
+#define ETH_DMARXDESC_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */
+
+/*---------------------------------------------------------------------------------------------------------------------
+  RDES4 |                   Reserved[31:15]              |             Extended Status [14:0]                          |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES5 |                                            Reserved[31:0]                                                    |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES6 |                                       Receive Time Stamp Low [31:0]                                          |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES7 |                                       Receive Time Stamp High [31:0]                                         |
+  --------------------------------------------------------------------------------------------------------------------*/
+
+/* Bit definition of RDES4 register */
+#define ETH_DMAPTPRXDESC_PTPV     ((uint32_t)0x00002000)  /* PTP Version */
+#define ETH_DMAPTPRXDESC_PTPFT    ((uint32_t)0x00001000)  /* PTP Frame Type */
+#define ETH_DMAPTPRXDESC_PTPMT    ((uint32_t)0x00000F00)  /* PTP Message Type */
+  #define ETH_DMAPTPRXDESC_PTPMT_SYNC                      ((uint32_t)0x00000100)  /* SYNC message (all clock types) */
+  #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP                  ((uint32_t)0x00000200)  /* FollowUp message (all clock types) */ 
+  #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ                  ((uint32_t)0x00000300)  /* DelayReq message (all clock types) */ 
+  #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP                 ((uint32_t)0x00000400)  /* DelayResp message (all clock types) */ 
+  #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE        ((uint32_t)0x00000500)  /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ 
+  #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG          ((uint32_t)0x00000600)  /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock)  */ 
+  #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700)  /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */           
+#define ETH_DMAPTPRXDESC_IPV6PR   ((uint32_t)0x00000080)  /* IPv6 Packet Received */
+#define ETH_DMAPTPRXDESC_IPV4PR   ((uint32_t)0x00000040)  /* IPv4 Packet Received */
+#define ETH_DMAPTPRXDESC_IPCB  ((uint32_t)0x00000020)  /* IP Checksum Bypassed */
+#define ETH_DMAPTPRXDESC_IPPE  ((uint32_t)0x00000010)  /* IP Payload Error */
+#define ETH_DMAPTPRXDESC_IPHE  ((uint32_t)0x00000008)  /* IP Header Error */
+#define ETH_DMAPTPRXDESC_IPPT  ((uint32_t)0x00000007)  /* IP Payload Type */
+  #define ETH_DMAPTPRXDESC_IPPT_UDP                 ((uint32_t)0x00000001)  /* UDP payload encapsulated in the IP datagram */
+  #define ETH_DMAPTPRXDESC_IPPT_TCP                 ((uint32_t)0x00000002)  /* TCP payload encapsulated in the IP datagram */ 
+  #define ETH_DMAPTPRXDESC_IPPT_ICMP                ((uint32_t)0x00000003)  /* ICMP payload encapsulated in the IP datagram */
+
+/* Bit definition of RDES6 register */
+#define ETH_DMAPTPRXDESC_RTSL  ((uint32_t)0xFFFFFFFF)  /* Receive Time Stamp Low */
+
+/* Bit definition of RDES7 register */
+#define ETH_DMAPTPRXDESC_RTSH  ((uint32_t)0xFFFFFFFF)  /* Receive Time Stamp High */
+
+
+ /** @defgroup ETH_AutoNegotiation 
+  * @{
+  */ 
+#define ETH_AUTONEGOTIATION_ENABLE     ((uint32_t)0x00000001)
+#define ETH_AUTONEGOTIATION_DISABLE    ((uint32_t)0x00000000)
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
+                                     ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
+/**
+  * @}
+  */
+/** @defgroup ETH_Speed 
+  * @{
+  */ 
+#define ETH_SPEED_10M        ((uint32_t)0x00000000)
+#define ETH_SPEED_100M       ((uint32_t)0x00004000)
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
+                             ((SPEED) == ETH_SPEED_100M))
+/**
+  * @}
+  */
+/** @defgroup ETH_Duplex_Mode 
+  * @{
+  */ 
+#define ETH_MODE_FULLDUPLEX       ((uint32_t)0x00000800)
+#define ETH_MODE_HALFDUPLEX       ((uint32_t)0x00000000)
+#define IS_ETH_DUPLEX_MODE(MODE)  (((MODE) == ETH_MODE_FULLDUPLEX) || \
+                                  ((MODE) == ETH_MODE_HALFDUPLEX))
+/**
+  * @}
+  */
+/** @defgroup ETH_Rx_Mode 
+  * @{
+  */ 
+#define ETH_RXPOLLING_MODE      ((uint32_t)0x00000000)
+#define ETH_RXINTERRUPT_MODE    ((uint32_t)0x00000001)
+#define IS_ETH_RX_MODE(MODE)    (((MODE) == ETH_RXPOLLING_MODE) || \
+                                 ((MODE) == ETH_RXINTERRUPT_MODE))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Checksum_Mode
+  * @{
+  */ 
+#define ETH_CHECKSUM_BY_HARDWARE      ((uint32_t)0x00000000)
+#define ETH_CHECKSUM_BY_SOFTWARE      ((uint32_t)0x00000001)
+#define IS_ETH_CHECKSUM_MODE(MODE)    (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
+                                      ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Media_Interface
+  * @{
+  */ 
+#define ETH_MEDIA_INTERFACE_MII       ((uint32_t)0x00000000)
+#define ETH_MEDIA_INTERFACE_RMII      ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
+#define IS_ETH_MEDIA_INTERFACE(MODE)         (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
+                                              ((MODE) == ETH_MEDIA_INTERFACE_RMII))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_watchdog 
+  * @{
+  */ 
+#define ETH_WATCHDOG_ENABLE       ((uint32_t)0x00000000)
+#define ETH_WATCHDOG_DISABLE      ((uint32_t)0x00800000)
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
+                              ((CMD) == ETH_WATCHDOG_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Jabber 
+  * @{
+  */ 
+#define ETH_JABBER_ENABLE    ((uint32_t)0x00000000)
+#define ETH_JABBER_DISABLE   ((uint32_t)0x00400000)
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
+                            ((CMD) == ETH_JABBER_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Inter_Frame_Gap 
+  * @{
+  */ 
+#define ETH_INTERFRAMEGAP_96BIT   ((uint32_t)0x00000000)  /*!< minimum IFG between frames during transmission is 96Bit */
+#define ETH_INTERFRAMEGAP_88BIT   ((uint32_t)0x00020000)  /*!< minimum IFG between frames during transmission is 88Bit */
+#define ETH_INTERFRAMEGAP_80BIT   ((uint32_t)0x00040000)  /*!< minimum IFG between frames during transmission is 80Bit */
+#define ETH_INTERFRAMEGAP_72BIT   ((uint32_t)0x00060000)  /*!< minimum IFG between frames during transmission is 72Bit */
+#define ETH_INTERFRAMEGAP_64BIT   ((uint32_t)0x00080000)  /*!< minimum IFG between frames during transmission is 64Bit */
+#define ETH_INTERFRAMEGAP_56BIT   ((uint32_t)0x000A0000)  /*!< minimum IFG between frames during transmission is 56Bit */
+#define ETH_INTERFRAMEGAP_48BIT   ((uint32_t)0x000C0000)  /*!< minimum IFG between frames during transmission is 48Bit */
+#define ETH_INTERFRAMEGAP_40BIT   ((uint32_t)0x000E0000)  /*!< minimum IFG between frames during transmission is 40Bit */
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
+                                     ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
+                                     ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
+                                     ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
+                                     ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
+                                     ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
+                                     ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
+                                     ((GAP) == ETH_INTERFRAMEGAP_40BIT))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Carrier_Sense 
+  * @{
+  */ 
+#define ETH_CARRIERSENCE_ENABLE   ((uint32_t)0x00000000)
+#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
+                                   ((CMD) == ETH_CARRIERSENCE_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Own 
+  * @{
+  */ 
+#define ETH_RECEIVEOWN_ENABLE     ((uint32_t)0x00000000)
+#define ETH_RECEIVEOWN_DISABLE   ((uint32_t)0x00002000)
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
+                                 ((CMD) == ETH_RECEIVEOWN_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Loop_Back_Mode 
+  * @{
+  */ 
+#define ETH_LOOPBACKMODE_ENABLE        ((uint32_t)0x00001000)
+#define ETH_LOOPBACKMODE_DISABLE       ((uint32_t)0x00000000)
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
+                                   ((CMD) == ETH_LOOPBACKMODE_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Checksum_Offload 
+  * @{
+  */ 
+#define ETH_CHECKSUMOFFLAOD_ENABLE     ((uint32_t)0x00000400)
+#define ETH_CHECKSUMOFFLAOD_DISABLE    ((uint32_t)0x00000000)
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
+                                      ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Retry_Transmission 
+  * @{
+  */ 
+#define ETH_RETRYTRANSMISSION_ENABLE   ((uint32_t)0x00000000)
+#define ETH_RETRYTRANSMISSION_DISABLE  ((uint32_t)0x00000200)
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
+                                        ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Automatic_Pad_CRC_Strip 
+  * @{
+  */ 
+#define ETH_AUTOMATICPADCRCSTRIP_ENABLE     ((uint32_t)0x00000080)
+#define ETH_AUTOMATICPADCRCSTRIP_DISABLE    ((uint32_t)0x00000000)
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
+                                            ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Back_Off_Limit 
+  * @{
+  */ 
+#define ETH_BACKOFFLIMIT_10  ((uint32_t)0x00000000)
+#define ETH_BACKOFFLIMIT_8   ((uint32_t)0x00000020)
+#define ETH_BACKOFFLIMIT_4   ((uint32_t)0x00000040)
+#define ETH_BACKOFFLIMIT_1   ((uint32_t)0x00000060)
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
+                                     ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
+                                     ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
+                                     ((LIMIT) == ETH_BACKOFFLIMIT_1))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Deferral_Check 
+  * @{
+  */
+#define ETH_DEFFERRALCHECK_ENABLE       ((uint32_t)0x00000010)
+#define ETH_DEFFERRALCHECK_DISABLE      ((uint32_t)0x00000000)
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
+                                    ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_All 
+  * @{
+  */ 
+#define ETH_RECEIVEALL_ENABLE     ((uint32_t)0x80000000)
+#define ETH_RECEIVEAll_DISABLE    ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
+                                 ((CMD) == ETH_RECEIVEAll_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Source_Addr_Filter 
+  * @{
+  */ 
+#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE       ((uint32_t)0x00000200)
+#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE      ((uint32_t)0x00000300)
+#define ETH_SOURCEADDRFILTER_DISABLE             ((uint32_t)0x00000000)
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
+                                        ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
+                                        ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Pass_Control_Frames 
+  * @{
+  */ 
+#define ETH_PASSCONTROLFRAMES_BLOCKALL                ((uint32_t)0x00000040)  /*!< MAC filters all control frames from reaching the application */
+#define ETH_PASSCONTROLFRAMES_FORWARDALL              ((uint32_t)0x00000080)  /*!< MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0)  /*!< MAC forwards control frames that pass the Address Filter. */ 
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
+                                     ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
+                                     ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Broadcast_Frames_Reception 
+  * @{
+  */ 
+#define ETH_BROADCASTFRAMESRECEPTION_ENABLE     ((uint32_t)0x00000000)
+#define ETH_BROADCASTFRAMESRECEPTION_DISABLE    ((uint32_t)0x00000020)
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
+                                                ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Destination_Addr_Filter 
+  * @{
+  */ 
+#define ETH_DESTINATIONADDRFILTER_NORMAL    ((uint32_t)0x00000000)
+#define ETH_DESTINATIONADDRFILTER_INVERSE   ((uint32_t)0x00000008)
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
+                                                ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Promiscuous_Mode 
+  * @{
+  */ 
+#define ETH_PROMISCIOUSMODE_ENABLE     ((uint32_t)0x00000001)
+#define ETH_PROMISCIOUSMODE_DISABLE    ((uint32_t)0x00000000)
+#define IS_ETH_PROMISCIOUS_MODE(CMD) (((CMD) == ETH_PROMISCIOUSMODE_ENABLE) || \
+                                      ((CMD) == ETH_PROMISCIOUSMODE_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Multicast_Frames_Filter 
+  * @{
+  */ 
+#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE    ((uint32_t)0x00000404)
+#define ETH_MULTICASTFRAMESFILTER_HASHTABLE           ((uint32_t)0x00000004)
+#define ETH_MULTICASTFRAMESFILTER_PERFECT             ((uint32_t)0x00000000)
+#define ETH_MULTICASTFRAMESFILTER_NONE                ((uint32_t)0x00000010)
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
+                                                ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
+                                                ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
+                                                ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Unicast_Frames_Filter 
+  * @{
+  */ 
+#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
+#define ETH_UNICASTFRAMESFILTER_HASHTABLE        ((uint32_t)0x00000002)
+#define ETH_UNICASTFRAMESFILTER_PERFECT          ((uint32_t)0x00000000)
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
+                                              ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
+                                              ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Pause_Time 
+  * @{
+  */ 
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Zero_Quanta_Pause 
+  * @{
+  */ 
+#define ETH_ZEROQUANTAPAUSE_ENABLE     ((uint32_t)0x00000000)
+#define ETH_ZEROQUANTAPAUSE_DISABLE    ((uint32_t)0x00000080)
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD)   (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
+                                        ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Pause_Low_Threshold 
+  * @{
+  */ 
+#define ETH_PAUSELOWTHRESHOLD_MINUS4        ((uint32_t)0x00000000)  /*!< Pause time minus 4 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS28       ((uint32_t)0x00000010)  /*!< Pause time minus 28 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS144      ((uint32_t)0x00000020)  /*!< Pause time minus 144 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS256      ((uint32_t)0x00000030)  /*!< Pause time minus 256 slot times */
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
+                                               ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
+                                               ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
+                                               ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Unicast_Pause_Frame_Detect 
+  * @{
+  */ 
+#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE  ((uint32_t)0x00000008)
+#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
+                                                ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Flow_Control 
+  * @{
+  */ 
+#define ETH_RECEIVEFLOWCONTROL_ENABLE       ((uint32_t)0x00000004)
+#define ETH_RECEIVEFLOWCONTROL_DISABLE      ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
+                                         ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Transmit_Flow_Control 
+  * @{
+  */ 
+#define ETH_TRANSMITFLOWCONTROL_ENABLE      ((uint32_t)0x00000002)
+#define ETH_TRANSMITFLOWCONTROL_DISABLE     ((uint32_t)0x00000000)
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
+                                          ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_VLAN_Tag_Comparison 
+  * @{
+  */ 
+#define ETH_VLANTAGCOMPARISON_12BIT    ((uint32_t)0x00010000)
+#define ETH_VLANTAGCOMPARISON_16BIT    ((uint32_t)0x00000000)
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
+                                                ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_addresses 
+  * @{
+  */ 
+#define ETH_MAC_ADDRESS0     ((uint32_t)0x00000000)
+#define ETH_MAC_ADDRESS1     ((uint32_t)0x00000008)
+#define ETH_MAC_ADDRESS2     ((uint32_t)0x00000010)
+#define ETH_MAC_ADDRESS3     ((uint32_t)0x00000018)
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
+                                         ((ADDRESS) == ETH_MAC_ADDRESS1) || \
+                                         ((ADDRESS) == ETH_MAC_ADDRESS2) || \
+                                         ((ADDRESS) == ETH_MAC_ADDRESS3))
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
+                                        ((ADDRESS) == ETH_MAC_ADDRESS2) || \
+                                        ((ADDRESS) == ETH_MAC_ADDRESS3))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames 
+  * @{
+  */ 
+#define ETH_MAC_ADDRESSFILTER_SA       ((uint32_t)0x00000000)
+#define ETH_MAC_ADDRESSFILTER_DA       ((uint32_t)0x00000008)
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
+                                           ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes 
+  * @{
+  */ 
+#define ETH_MAC_ADDRESSMASK_BYTE6      ((uint32_t)0x20000000)  /*!< Mask MAC Address high reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE5      ((uint32_t)0x10000000)  /*!< Mask MAC Address high reg bits [7:0] */
+#define ETH_MAC_ADDRESSMASK_BYTE4      ((uint32_t)0x08000000)  /*!< Mask MAC Address low reg bits [31:24] */
+#define ETH_MAC_ADDRESSMASK_BYTE3      ((uint32_t)0x04000000)  /*!< Mask MAC Address low reg bits [23:16] */
+#define ETH_MAC_ADDRESSMASK_BYTE2      ((uint32_t)0x02000000)  /*!< Mask MAC Address low reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE1      ((uint32_t)0x01000000)  /*!< Mask MAC Address low reg bits [70] */
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
+                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
+                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
+                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
+                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
+                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_Debug_flags
+  * @{
+  */ 
+#define ETH_MAC_TXFIFO_FULL          ((uint32_t)0x02000000)  /* Tx FIFO full */
+
+#define ETH_MAC_TXFIFONOT_EMPTY      ((uint32_t)0x01000000)  /* Tx FIFO not empty */
+
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE  ((uint32_t)0x00400000)  /* Tx FIFO write active */
+
+#define ETH_MAC_TXFIFO_IDLE     ((uint32_t)0x00000000)  /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ     ((uint32_t)0x00100000)  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING  ((uint32_t)0x00200000)  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING  ((uint32_t)0x00300000)  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+
+#define ETH_MAC_TRANSMISSION_PAUSE     ((uint32_t)0x00080000)  /* MAC transmitter in pause */
+
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            ((uint32_t)0x00000000)  /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         ((uint32_t)0x00020000)  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   ((uint32_t)0x00040000)  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    ((uint32_t)0x00060000)  /* MAC transmit frame controller: Transferring input frame for transmission */
+
+#define ETH_MAC_MII_TRANSMIT_ACTIVE      ((uint32_t)0x00010000)  /* MAC MII transmit engine active */
+
+#define ETH_MAC_RXFIFO_EMPTY             ((uint32_t)0x00000000)  /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD   ((uint32_t)0x00000100)  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD   ((uint32_t)0x00000200)  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL              ((uint32_t)0x00000300)  /* Rx FIFO fill level: full */
+
+#define ETH_MAC_READCONTROLLER_IDLE            ((uint32_t)0x00000060)  /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA    ((uint32_t)0x00000060)  /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS  ((uint32_t)0x00000060)  /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#define ETH_MAC_READCONTROLLER_ FLUSHING       ((uint32_t)0x00000060)  /* Rx FIFO read controller Flushing the frame data and status */
+
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE     ((uint32_t)0x00000010)  /* Rx FIFO write controller active */
+
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE    ((uint32_t)0x00000000)  /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE  ((uint32_t)0x00000002)  /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004)  /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE    ((uint32_t)0x00000006)  /* MAC small FIFO read / write controllers active */
+
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_AVTIVE   ((uint32_t)0x00000001)  /* MAC MII receive protocol engine active */
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame 
+  * @{
+  */ 
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE   ((uint32_t)0x00000000)
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE  ((uint32_t)0x04000000)
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
+                                               ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Store_Forward 
+  * @{
+  */ 
+#define ETH_RECEIVESTOREFORWARD_ENABLE      ((uint32_t)0x02000000)
+#define ETH_RECEIVESTOREFORWARD_DISABLE     ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
+                                           ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Flush_Received_Frame 
+  * @{
+  */ 
+#define ETH_FLUSHRECEIVEDFRAME_ENABLE       ((uint32_t)0x00000000)
+#define ETH_FLUSHRECEIVEDFRAME_DISABLE      ((uint32_t)0x01000000)
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
+                                         ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Transmit_Store_Forward 
+  * @{
+  */ 
+#define ETH_TRANSMITSTOREFORWARD_ENABLE     ((uint32_t)0x00200000)
+#define ETH_TRANSMITSTOREFORWARD_DISABLE    ((uint32_t)0x00000000)
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
+                                            ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Transmit_Threshold_Control 
+  * @{
+  */ 
+#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES     ((uint32_t)0x00000000)  /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES    ((uint32_t)0x00004000)  /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES    ((uint32_t)0x00008000)  /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES    ((uint32_t)0x0000C000)  /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES     ((uint32_t)0x00010000)  /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES     ((uint32_t)0x00014000)  /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES     ((uint32_t)0x00018000)  /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES     ((uint32_t)0x0001C000)  /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
+                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
+                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
+                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
+                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
+                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
+                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
+                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Forward_Error_Frames 
+  * @{
+  */ 
+#define ETH_FORWARDERRORFRAMES_ENABLE       ((uint32_t)0x00000080)
+#define ETH_FORWARDERRORFRAMES_DISABLE      ((uint32_t)0x00000000)
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
+                                          ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Forward_Undersized_Good_Frames 
+  * @{
+  */ 
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE   ((uint32_t)0x00000040)
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE  ((uint32_t)0x00000000)     
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
+                                                    ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Threshold_Control 
+  * @{
+  */ 
+#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES      ((uint32_t)0x00000000)  /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES      ((uint32_t)0x00000008)  /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES      ((uint32_t)0x00000010)  /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES     ((uint32_t)0x00000018)  /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
+                                                     ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
+                                                     ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
+                                                     ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Second_Frame_Operate 
+  * @{
+  */ 
+#define ETH_SECONDFRAMEOPERARTE_ENABLE       ((uint32_t)0x00000004)
+#define ETH_SECONDFRAMEOPERARTE_DISABLE      ((uint32_t)0x00000000)  
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
+                                          ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Address_Aligned_Beats 
+  * @{
+  */ 
+#define ETH_ADDRESSALIGNEDBEATS_ENABLE      ((uint32_t)0x02000000)
+#define ETH_ADDRESSALIGNEDBEATS_DISABLE     ((uint32_t)0x00000000) 
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
+                                           ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Fixed_Burst 
+  * @{
+  */ 
+#define ETH_FIXEDBURST_ENABLE     ((uint32_t)0x00010000)
+#define ETH_FIXEDBURST_DISABLE    ((uint32_t)0x00000000) 
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
+                                 ((CMD) == ETH_FIXEDBURST_DISABLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_DMA_Burst_Length 
+  * @{
+  */ 
+#define ETH_RXDMABURSTLENGTH_1BEAT          ((uint32_t)0x00020000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_RXDMABURSTLENGTH_2BEAT          ((uint32_t)0x00040000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_RXDMABURSTLENGTH_4BEAT          ((uint32_t)0x00080000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_8BEAT          ((uint32_t)0x00100000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_16BEAT         ((uint32_t)0x00200000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_32BEAT         ((uint32_t)0x00400000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT    ((uint32_t)0x01020000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT    ((uint32_t)0x01040000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT   ((uint32_t)0x01080000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT   ((uint32_t)0x01100000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT   ((uint32_t)0x01200000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT  ((uint32_t)0x01400000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
+
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
+                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
+                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
+                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
+                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
+                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
+                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
+                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
+                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
+                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
+                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
+                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
+ 
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_DMA_Burst_Length 
+  * @{
+  */ 
+#define ETH_TXDMABURSTLENGTH_1BEAT          ((uint32_t)0x00000100)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_TXDMABURSTLENGTH_2BEAT          ((uint32_t)0x00000200)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_TXDMABURSTLENGTH_4BEAT          ((uint32_t)0x00000400)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TXDMABURSTLENGTH_8BEAT          ((uint32_t)0x00000800)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TXDMABURSTLENGTH_16BEAT         ((uint32_t)0x00001000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TXDMABURSTLENGTH_32BEAT         ((uint32_t)0x00002000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT    ((uint32_t)0x01000100)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT    ((uint32_t)0x01000200)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT   ((uint32_t)0x01000400)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT   ((uint32_t)0x01000800)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT   ((uint32_t)0x01001000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT  ((uint32_t)0x01002000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
+                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
+                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
+                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
+                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
+                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
+                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
+                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
+                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
+                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
+                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
+                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
+
+/** @defgroup ETH_DMA_Enhanced_descriptor_format 
+  * @{
+  */  
+#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE              ((uint32_t)0x00000080)
+#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE             ((uint32_t)0x00000000)
+
+#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
+                                                ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
+
+/**
+  * @}
+  */
+
+/** 
+  * @brief  ETH DMA Descriptor SkipLength  
+  */ 
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
+
+
+/** @defgroup ETH_DMA_Arbitration 
+  * @{
+  */ 
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1   ((uint32_t)0x00000000)
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1   ((uint32_t)0x00004000)
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1   ((uint32_t)0x00008000)
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1   ((uint32_t)0x0000C000)
+#define ETH_DMAARBITRATION_RXPRIORTX             ((uint32_t)0x00000002)
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
+                                                       ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
+                                                       ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
+                                                       ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
+                                                       ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Tx_descriptor_flags
+  * @{
+  */ 
+#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
+                                         ((FLAG) == ETH_DMATXDESC_IC) || \
+                                         ((FLAG) == ETH_DMATXDESC_LS) || \
+                                         ((FLAG) == ETH_DMATXDESC_FS) || \
+                                         ((FLAG) == ETH_DMATXDESC_DC) || \
+                                         ((FLAG) == ETH_DMATXDESC_DP) || \
+                                         ((FLAG) == ETH_DMATXDESC_TTSE) || \
+                                         ((FLAG) == ETH_DMATXDESC_TER) || \
+                                         ((FLAG) == ETH_DMATXDESC_TCH) || \
+                                         ((FLAG) == ETH_DMATXDESC_TTSS) || \
+                                         ((FLAG) == ETH_DMATXDESC_IHE) || \
+                                         ((FLAG) == ETH_DMATXDESC_ES) || \
+                                         ((FLAG) == ETH_DMATXDESC_JT) || \
+                                         ((FLAG) == ETH_DMATXDESC_FF) || \
+                                         ((FLAG) == ETH_DMATXDESC_PCE) || \
+                                         ((FLAG) == ETH_DMATXDESC_LCA) || \
+                                         ((FLAG) == ETH_DMATXDESC_NC) || \
+                                         ((FLAG) == ETH_DMATXDESC_LCO) || \
+                                         ((FLAG) == ETH_DMATXDESC_EC) || \
+                                         ((FLAG) == ETH_DMATXDESC_VF) || \
+                                         ((FLAG) == ETH_DMATXDESC_CC) || \
+                                         ((FLAG) == ETH_DMATXDESC_ED) || \
+                                         ((FLAG) == ETH_DMATXDESC_UF) || \
+                                         ((FLAG) == ETH_DMATXDESC_DB))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Tx_descriptor_segment 
+  * @{
+  */ 
+#define ETH_DMATXDESC_LASTSEGMENTS      ((uint32_t)0x40000000)  /*!< Last Segment */
+#define ETH_DMATXDESC_FIRSTSEGMENT      ((uint32_t)0x20000000)  /*!< First Segment */
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
+                                            ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
+  * @{
+  */ 
+#define ETH_DMATXDESC_CHECKSUMBYPASS             ((uint32_t)0x00000000)   /*!< Checksum engine bypass */
+#define ETH_DMATXDESC_CHECKSUMIPV4HEADER         ((uint32_t)0x00400000)   /*!< IPv4 header checksum insertion  */
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT  ((uint32_t)0x00800000)   /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL     ((uint32_t)0x00C00000)   /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
+                                              ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
+                                              ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
+                                              ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
+/** 
+  * @brief  ETH DMA Tx Desciptor buffer size
+  */ 
+#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Rx_descriptor_flags
+  * @{
+  */ 
+#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
+                                         ((FLAG) == ETH_DMARXDESC_AFM) || \
+                                         ((FLAG) == ETH_DMARXDESC_ES) || \
+                                         ((FLAG) == ETH_DMARXDESC_DE) || \
+                                         ((FLAG) == ETH_DMARXDESC_SAF) || \
+                                         ((FLAG) == ETH_DMARXDESC_LE) || \
+                                         ((FLAG) == ETH_DMARXDESC_OE) || \
+                                         ((FLAG) == ETH_DMARXDESC_VLAN) || \
+                                         ((FLAG) == ETH_DMARXDESC_FS) || \
+                                         ((FLAG) == ETH_DMARXDESC_LS) || \
+                                         ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
+                                         ((FLAG) == ETH_DMARXDESC_LC) || \
+                                         ((FLAG) == ETH_DMARXDESC_FT) || \
+                                         ((FLAG) == ETH_DMARXDESC_RWT) || \
+                                         ((FLAG) == ETH_DMARXDESC_RE) || \
+                                         ((FLAG) == ETH_DMARXDESC_DBE) || \
+                                         ((FLAG) == ETH_DMARXDESC_CE) || \
+                                         ((FLAG) == ETH_DMARXDESC_MAMPCE))
+
+/* ETHERNET DMA PTP Rx descriptor extended flags  --------------------------------*/
+#define IS_ETH_DMAPTPRXDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRXDESC_PTPV) || \
+                                                     ((FLAG) == ETH_DMAPTPRXDESC_PTPFT) || \
+                                                     ((FLAG) == ETH_DMAPTPRXDESC_PTPMT) || \
+                                                     ((FLAG) == ETH_DMAPTPRXDESC_IPV6PR) || \
+                                                     ((FLAG) == ETH_DMAPTPRXDESC_IPV4PR) || \
+                                                     ((FLAG) == ETH_DMAPTPRXDESC_IPCB) || \
+                                                     ((FLAG) == ETH_DMAPTPRXDESC_IPPE) || \
+                                                     ((FLAG) == ETH_DMAPTPRXDESC_IPHE) || \
+                                                     ((FLAG) == ETH_DMAPTPRXDESC_IPPT))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Rx_descriptor_buffers_ 
+  * @{
+  */ 
+#define ETH_DMARXDESC_BUFFER1     ((uint32_t)0x00000000)  /*!< DMA Rx Desc Buffer1 */
+#define ETH_DMARXDESC_BUFFER2     ((uint32_t)0x00000001)  /*!< DMA Rx Desc Buffer2 */
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
+                                          ((BUFFER) == ETH_DMARXDESC_BUFFER2))
+
+
+/* ETHERNET DMA Tx descriptors Collision Count Shift */
+#define  ETH_DMATXDESC_COLLISION_COUNTSHIFT         ((uint32_t)3)
+
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
+#define  ETH_DMATXDESC_BUFFER2_SIZESHIFT           ((uint32_t)16)
+
+/* ETHERNET DMA Rx descriptors Frame Length Shift */
+#define  ETH_DMARXDESC_FRAME_LENGTHSHIFT           ((uint32_t)16)
+
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
+#define  ETH_DMARXDESC_BUFFER2_SIZESHIFT           ((uint32_t)16)
+
+/* ETHERNET DMA Rx descriptors Frame length Shift */
+#define  ETH_DMARXDESC_FRAMELENGTHSHIFT            ((uint32_t)16)
+ 
+/**
+  * @}
+  */
+
+/** @defgroup ETH_PMT_Flags 
+  * @{
+  */ 
+#define ETH_PMT_FLAG_WUFFRPR      ((uint32_t)0x80000000)  /*!< Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_PMT_FLAG_WUFR         ((uint32_t)0x00000040)  /*!< Wake-Up Frame Received */
+#define ETH_PMT_FLAG_MPR          ((uint32_t)0x00000020)  /*!< Magic Packet Received */
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
+                                   ((FLAG) == ETH_PMT_FLAG_MPR))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MMC_Tx_Interrupts 
+  * @{
+  */ 
+#define ETH_MMC_IT_TGF       ((uint32_t)0x00200000)  /*!< When Tx good frame counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFMSC    ((uint32_t)0x00008000)  /*!< When Tx good multi col counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFSC     ((uint32_t)0x00004000)  /*!< When Tx good single col counter reaches half the maximum value */
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MMC_Rx_Interrupts 
+  * @{
+  */
+#define ETH_MMC_IT_RGUF      ((uint32_t)0x10020000)  /*!< When Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMC_IT_RFAE      ((uint32_t)0x10000040)  /*!< When Rx alignment error counter reaches half the maximum value */
+#define ETH_MMC_IT_RFCE      ((uint32_t)0x10000020)  /*!< When Rx crc error counter reaches half the maximum value */
+#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
+                           ((IT) != 0x00))
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
+                               ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
+                               ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MMC_Registers 
+  * @{
+  */ 
+#define ETH_MMCCR            ((uint32_t)0x00000100)  /*!< MMC CR register */
+#define ETH_MMCRIR           ((uint32_t)0x00000104)  /*!< MMC RIR register */
+#define ETH_MMCTIR           ((uint32_t)0x00000108)  /*!< MMC TIR register */
+#define ETH_MMCRIMR          ((uint32_t)0x0000010C)  /*!< MMC RIMR register */
+#define ETH_MMCTIMR          ((uint32_t)0x00000110)  /*!< MMC TIMR register */ 
+#define ETH_MMCTGFSCCR       ((uint32_t)0x0000014C)  /*!< MMC TGFSCCR register */
+#define ETH_MMCTGFMSCCR      ((uint32_t)0x00000150)  /*!< MMC TGFMSCCR register */ 
+#define ETH_MMCTGFCR         ((uint32_t)0x00000168)  /*!< MMC TGFCR register */
+#define ETH_MMCRFCECR        ((uint32_t)0x00000194)  /*!< MMC RFCECR register */
+#define ETH_MMCRFAECR        ((uint32_t)0x00000198)  /*!< MMC RFAECR register */
+#define ETH_MMCRGUFCR        ((uint32_t)0x000001C4)  /*!< MMC RGUFCR register */
+
+/** 
+  * @brief  ETH MMC registers  
+  */ 
+#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR)  || ((REG) == ETH_MMCRIR) || \
+                                  ((REG) == ETH_MMCTIR)  || ((REG) == ETH_MMCRIMR) || \
+                                  ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
+                                  ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
+                                  ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
+                                  ((REG) == ETH_MMCRGUFCR)) 
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_Flags 
+  * @{
+  */ 
+#define ETH_MAC_FLAG_TST     ((uint32_t)0x00000200)  /*!< Time stamp trigger flag (on MAC) */
+#define ETH_MAC_FLAG_MMCT    ((uint32_t)0x00000040)  /*!< MMC transmit flag  */
+#define ETH_MAC_FLAG_MMCR    ((uint32_t)0x00000020)  /*!< MMC receive flag */
+#define ETH_MAC_FLAG_MMC     ((uint32_t)0x00000010)  /*!< MMC flag (on MAC) */
+#define ETH_MAC_FLAG_PMT     ((uint32_t)0x00000008)  /*!< PMT flag (on MAC) */
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
+                                   ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
+                                   ((FLAG) == ETH_MAC_FLAG_PMT))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Flags 
+  * @{
+  */ 
+#define ETH_DMA_FLAG_TST               ((uint32_t)0x20000000)  /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_FLAG_PMT               ((uint32_t)0x10000000)  /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_FLAG_MMC               ((uint32_t)0x08000000)  /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000)  /*!< Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMA_FLAG_READWRITEERROR    ((uint32_t)0x01000000)  /*!< Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMA_FLAG_ACCESSERROR       ((uint32_t)0x02000000)  /*!< Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMA_FLAG_NIS               ((uint32_t)0x00010000)  /*!< Normal interrupt summary flag */
+#define ETH_DMA_FLAG_AIS               ((uint32_t)0x00008000)  /*!< Abnormal interrupt summary flag */
+#define ETH_DMA_FLAG_ER                ((uint32_t)0x00004000)  /*!< Early receive flag */
+#define ETH_DMA_FLAG_FBE               ((uint32_t)0x00002000)  /*!< Fatal bus error flag */
+#define ETH_DMA_FLAG_ET                ((uint32_t)0x00000400)  /*!< Early transmit flag */
+#define ETH_DMA_FLAG_RWT               ((uint32_t)0x00000200)  /*!< Receive watchdog timeout flag */
+#define ETH_DMA_FLAG_RPS               ((uint32_t)0x00000100)  /*!< Receive process stopped flag */
+#define ETH_DMA_FLAG_RBU               ((uint32_t)0x00000080)  /*!< Receive buffer unavailable flag */
+#define ETH_DMA_FLAG_R                 ((uint32_t)0x00000040)  /*!< Receive flag */
+#define ETH_DMA_FLAG_TU                ((uint32_t)0x00000020)  /*!< Underflow flag */
+#define ETH_DMA_FLAG_RO                ((uint32_t)0x00000010)  /*!< Overflow flag */
+#define ETH_DMA_FLAG_TJT               ((uint32_t)0x00000008)  /*!< Transmit jabber timeout flag */
+#define ETH_DMA_FLAG_TBU               ((uint32_t)0x00000004)  /*!< Transmit buffer unavailable flag */
+#define ETH_DMA_FLAG_TPS               ((uint32_t)0x00000002)  /*!< Transmit process stopped flag */
+#define ETH_DMA_FLAG_T                 ((uint32_t)0x00000001)  /*!< Transmit flag */
+
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00)) 
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
+                                   ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
+                                   ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
+                                   ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
+                                   ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
+                                   ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
+                                   ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
+                                   ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
+                                   ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
+                                   ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
+                                   ((FLAG) == ETH_DMA_FLAG_T))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_Interrupts 
+  * @{
+  */ 
+#define ETH_MAC_IT_TST       ((uint32_t)0x00000200)  /*!< Time stamp trigger interrupt (on MAC) */
+#define ETH_MAC_IT_MMCT      ((uint32_t)0x00000040)  /*!< MMC transmit interrupt */
+#define ETH_MAC_IT_MMCR      ((uint32_t)0x00000020)  /*!< MMC receive interrupt */
+#define ETH_MAC_IT_MMC       ((uint32_t)0x00000010)  /*!< MMC interrupt (on MAC) */
+#define ETH_MAC_IT_PMT       ((uint32_t)0x00000008)  /*!< PMT interrupt (on MAC) */
+#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
+                               ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
+                               ((IT) == ETH_MAC_IT_PMT))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Interrupts 
+  * @{
+  */ 
+#define ETH_DMA_IT_TST       ((uint32_t)0x20000000)  /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_IT_PMT       ((uint32_t)0x10000000)  /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_IT_MMC       ((uint32_t)0x08000000)  /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_IT_NIS       ((uint32_t)0x00010000)  /*!< Normal interrupt summary */
+#define ETH_DMA_IT_AIS       ((uint32_t)0x00008000)  /*!< Abnormal interrupt summary */
+#define ETH_DMA_IT_ER        ((uint32_t)0x00004000)  /*!< Early receive interrupt */
+#define ETH_DMA_IT_FBE       ((uint32_t)0x00002000)  /*!< Fatal bus error interrupt */
+#define ETH_DMA_IT_ET        ((uint32_t)0x00000400)  /*!< Early transmit interrupt */
+#define ETH_DMA_IT_RWT       ((uint32_t)0x00000200)  /*!< Receive watchdog timeout interrupt */
+#define ETH_DMA_IT_RPS       ((uint32_t)0x00000100)  /*!< Receive process stopped interrupt */
+#define ETH_DMA_IT_RBU       ((uint32_t)0x00000080)  /*!< Receive buffer unavailable interrupt */
+#define ETH_DMA_IT_R         ((uint32_t)0x00000040)  /*!< Receive interrupt */
+#define ETH_DMA_IT_TU        ((uint32_t)0x00000020)  /*!< Underflow interrupt */
+#define ETH_DMA_IT_RO        ((uint32_t)0x00000010)  /*!< Overflow interrupt */
+#define ETH_DMA_IT_TJT       ((uint32_t)0x00000008)  /*!< Transmit jabber timeout interrupt */
+#define ETH_DMA_IT_TBU       ((uint32_t)0x00000004)  /*!< Transmit buffer unavailable interrupt */
+#define ETH_DMA_IT_TPS       ((uint32_t)0x00000002)  /*!< Transmit process stopped interrupt */
+#define ETH_DMA_IT_T         ((uint32_t)0x00000001)  /*!< Transmit interrupt */
+
+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
+                               ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
+                               ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
+                               ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
+                               ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
+                               ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
+                               ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
+                               ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
+                               ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_transmit_process_state_ 
+  * @{
+  */ 
+#define ETH_DMA_TRANSMITPROCESS_STOPPED     ((uint32_t)0x00000000)  /*!< Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMA_TRANSMITPROCESS_FETCHING    ((uint32_t)0x00100000)  /*!< Running - fetching the Tx descriptor */
+#define ETH_DMA_TRANSMITPROCESS_WAITING     ((uint32_t)0x00200000)  /*!< Running - waiting for status */
+#define ETH_DMA_TRANSMITPROCESS_READING     ((uint32_t)0x00300000)  /*!< Running - reading the data from host memory */
+#define ETH_DMA_TRANSMITPROCESS_SUSPENDED   ((uint32_t)0x00600000)  /*!< Suspended - Tx Descriptor unavailable */
+#define ETH_DMA_TRANSMITPROCESS_CLOSING     ((uint32_t)0x00700000)  /*!< Running - closing Rx descriptor */
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ETH_DMA_receive_process_state_ 
+  * @{
+  */ 
+#define ETH_DMA_RECEIVEPROCESS_STOPPED      ((uint32_t)0x00000000)  /*!< Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMA_RECEIVEPROCESS_FETCHING     ((uint32_t)0x00020000)  /*!< Running - fetching the Rx descriptor */
+#define ETH_DMA_RECEIVEPROCESS_WAITING      ((uint32_t)0x00060000)  /*!< Running - waiting for packet */
+#define ETH_DMA_RECEIVEPROCESS_SUSPENDED    ((uint32_t)0x00080000)  /*!< Suspended - Rx Descriptor unavailable */
+#define ETH_DMA_RECEIVEPROCESS_CLOSING      ((uint32_t)0x000A0000)  /*!< Running - closing descriptor */
+#define ETH_DMA_RECEIVEPROCESS_QUEUING      ((uint32_t)0x000E0000)  /*!< Running - queuing the receive frame into host memory */
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_overflow_ 
+  * @{
+  */ 
+#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER      ((uint32_t)0x10000000)  /*!< Overflow bit for FIFO overflow counter */
+#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000)  /*!< Overflow bit for missed frame counter */
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
+                                           ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
+/**
+  * @}
+  */ 
+
+/* ETHERNET MAC address offsets */
+#define ETH_MAC_ADDR_HBASE    (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40)  /* ETHERNET MAC address high offset */
+#define ETH_MAC_ADDR_LBASE    (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44)  /* ETHERNET MAC address low offset */
+
+/* ETHERNET MACMIIAR register Mask */
+#define MACMIIAR_CR_MASK    ((uint32_t)0xFFFFFFE3)
+
+/* ETHERNET MACCR register Mask */
+#define MACCR_CLEAR_MASK    ((uint32_t)0xFF20810F)  
+
+/* ETHERNET MACFCR register Mask */
+#define MACFCR_CLEAR_MASK   ((uint32_t)0x0000FF41)
+
+
+/* ETHERNET DMAOMR register Mask */
+#define DMAOMR_CLEAR_MASK   ((uint32_t)0xF8DE3F23)
+
+
+/* ETHERNET Remote Wake-up frame register length */
+#define ETH_WAKEUP_REGISTER_LENGTH      8
+
+/* ETHERNET Missed frames counter Shift */
+#define  ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT     17
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset ETH handle state
+  * @param  __HANDLE__: specifies the ETH handle.
+  * @retval None
+  */
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
+
+/** 
+  * @brief  Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
+  * @param  __HANDLE__: ETH Handle
+  * @param  __FLAG__: specifies the flag to check.
+  * @retval the ETH_DMATxDescFlag (SET or RESET).
+  */
+#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
+
+/**
+  * @brief  Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
+  * @param  __HANDLE__: ETH Handle
+  * @param  __FLAG__: specifies the flag to check.
+  * @retval the ETH_DMATxDescFlag (SET or RESET).
+  */
+#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
+
+/**
+  * @brief  Enables the specified DMA Rx Desc receive interrupt.
+  * @param  __HANDLE__: ETH Handle
+  * @retval None
+  */
+#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__)                          ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
+
+/**
+  * @brief  Disables the specified DMA Rx Desc receive interrupt.
+  * @param  __HANDLE__: ETH Handle
+  * @retval None
+  */
+#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__)                         ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
+
+/**
+  * @brief  Set the specified DMA Rx Desc Own bit.
+  * @param  __HANDLE__: ETH Handle
+  * @retval None
+  */
+#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__)                           ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
+
+/**
+  * @brief  Returns the specified ETHERNET DMA Tx Desc collision count.
+  * @param  __HANDLE__: ETH Handle                     
+  * @retval The Transmit descriptor collision counter value.
+  */
+#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__)                   (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
+
+/**
+  * @brief  Set the specified DMA Tx Desc Own bit.
+  * @param  __HANDLE__: ETH Handle
+  * @retval None
+  */
+#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__)                       ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
+
+/**
+  * @brief  Enables the specified DMA Tx Desc Transmit interrupt.
+  * @param  __HANDLE__: ETH Handle                   
+  * @retval None
+  */
+#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
+
+/**
+  * @brief  Disables the specified DMA Tx Desc Transmit interrupt.
+  * @param  __HANDLE__: ETH Handle             
+  * @retval None
+  */
+#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
+
+/**
+  * @brief  Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
+  * @param  __HANDLE__: ETH Handle  
+  * @param  __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
+  *     @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
+  *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
+  *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header                                                                
+  * @retval None
+  */
+#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__)     ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
+
+/**
+  * @brief  Enables the DMA Tx Desc CRC.
+  * @param  __HANDLE__: ETH Handle 
+  * @retval None
+  */
+#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
+
+/**
+  * @brief  Disables the DMA Tx Desc CRC.
+  * @param  __HANDLE__: ETH Handle 
+  * @retval None
+  */
+#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__)                         ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
+
+/**
+  * @brief  Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
+  * @param  __HANDLE__: ETH Handle 
+  * @retval None
+  */
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__)            ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
+
+/**
+  * @brief  Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
+  * @param  __HANDLE__: ETH Handle 
+  * @retval None
+  */
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__)           ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
+
+/** 
+ * @brief  Enables the specified ETHERNET MAC interrupts.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+  *   enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 
+  *     @arg ETH_MAC_IT_PMT : PMT interrupt 
+  * @retval None
+  */
+#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disables the specified ETHERNET MAC interrupts.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+  *   enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 
+  *     @arg ETH_MAC_IT_PMT : PMT interrupt
+  * @retval None
+  */
+#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Initiate a Pause Control Frame (Full-duplex only).
+  * @param  __HANDLE__: ETH Handle
+  * @retval None
+  */
+#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__)              ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
+
+/**
+  * @brief  Checks whether the ETHERNET flow control busy bit is set or not.
+  * @param  __HANDLE__: ETH Handle
+  * @retval The new state of flow control busy status bit (SET or RESET).
+  */
+#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__)               (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
+
+/**
+  * @brief  Enables the MAC Back Pressure operation activation (Half-duplex only).
+  * @param  __HANDLE__: ETH Handle
+  * @retval None
+  */
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__)          ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
+
+/**
+  * @brief  Disables the MAC BackPressure operation activation (Half-duplex only).
+  * @param  __HANDLE__: ETH Handle
+  * @retval None
+  */
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__)         ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
+
+/**
+  * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
+  * @param  __HANDLE__: ETH Handle
+  * @param  __FLAG__: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag   
+  *     @arg ETH_MAC_FLAG_MMCT : MMC transmit flag  
+  *     @arg ETH_MAC_FLAG_MMCR : MMC receive flag   
+  *     @arg ETH_MAC_FLAG_MMC  : MMC flag  
+  *     @arg ETH_MAC_FLAG_PMT  : PMT flag  
+  * @retval The state of ETHERNET MAC flag.
+  */
+#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
+
+/**
+  * @brief  Clears the specified ETHERNET MAC flag.
+  * @param  __HANDLE__: ETH Handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag   
+  *     @arg ETH_MAC_FLAG_MMCT : MMC transmit flag  
+  *     @arg ETH_MAC_FLAG_MMCR : MMC receive flag   
+  *     @arg ETH_MAC_FLAG_MMC  : MMC flag  
+  *     @arg ETH_MAC_FLAG_PMT  : PMT flag  
+  * @retval None.
+  */
+#define __HAL_ETH_MAC_CLEAR_FLAG(__HANDLE__, __FLAG__)                 ((__HANDLE__)->Instance->MACSR &= ~(__FLAG__))
+
+/** 
+  * @brief  Enables the specified ETHERNET DMA interrupts.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
+  *   enabled @defgroup ETH_DMA_Interrupts
+  * @retval None
+  */
+#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
+
+/**
+  * @brief  Disables the specified ETHERNET DMA interrupts.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
+  *   disabled. @defgroup ETH_DMA_Interrupts
+  * @retval None
+  */
+#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Clears the ETHERNET DMA IT pending bit.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @defgroup ETH_DMA_Interrupts
+  * @retval None
+  */
+#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
+* @param  __HANDLE__: ETH Handle
+  * @param  __FLAG__: specifies the flag to check.
+  * @retval The new state of ETH_DMA_FLAG (SET or RESET).
+  */
+#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
+
+/**
+  * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
+  * @param  __HANDLE__: ETH Handle
+  * @param  __FLAG__: specifies the flag to clear.
+  * @retval The new state of ETH_DMA_FLAG (SET or RESET).
+  */
+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)                 ((__HANDLE__)->Instance->DMASR &= ~(__FLAG__))
+
+/**
+  * @brief  Checks whether the specified ETHERNET DMA overflow flag is set or not.
+  * @param  __HANDLE__: ETH Handle
+  * @param  __OVERFLOW__: specifies the DMA overflow flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
+  *     @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
+  * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
+  */
+#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__)       (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
+
+/**
+  * @brief  Set the DMA Receive status watchdog timer register value
+  * @param  __HANDLE__: ETH Handle
+  * @param  __VALUE__: DMA Receive status watchdog timer register value   
+  * @retval None
+  */
+#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__)       ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
+
+/** 
+  * @brief  Enables any unicast packet filtered by the MAC address
+  *   recognition to be a wake-up frame.
+  * @param  __HANDLE__: ETH Handle.
+  * @retval None
+  */
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
+
+/**
+  * @brief  Disables any unicast packet filtered by the MAC address
+  *   recognition to be a wake-up frame.
+  * @param  __HANDLE__: ETH Handle.
+  * @retval None
+  */
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
+
+/**
+  * @brief  Enables the MAC Wake-Up Frame Detection.
+  * @param  __HANDLE__: ETH Handle.
+  * @retval None
+  */
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
+
+/**
+  * @brief  Disables the MAC Wake-Up Frame Detection.
+  * @param  __HANDLE__: ETH Handle.
+  * @retval None
+  */
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__)             ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
+
+/**
+  * @brief  Enables the MAC Magic Packet Detection.
+  * @param  __HANDLE__: ETH Handle.
+  * @retval None
+  */
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
+
+/**
+  * @brief  Disables the MAC Magic Packet Detection.
+  * @param  __HANDLE__: ETH Handle.
+  * @retval None
+  */
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__)             ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
+
+/**
+  * @brief  Enables the MAC Power Down.
+  * @param  __HANDLE__: ETH Handle
+  * @retval None
+  */
+#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
+
+/**
+  * @brief  Disables the MAC Power Down.
+  * @param  __HANDLE__: ETH Handle
+  * @retval None
+  */
+#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
+
+/**
+  * @brief  Checks whether the specified ETHERNET PMT flag is set or not.
+  * @param  __HANDLE__: ETH Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset 
+  *     @arg ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received 
+  *     @arg ETH_PMT_FLAG_MPR     : Magic Packet Received
+  * @retval The new state of ETHERNET PMT Flag (SET or RESET).
+  */
+#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__)               (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
+
+/** 
+  * @brief  Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
+  * @param   __HANDLE__: ETH Handle.
+  * @retval None
+  */
+#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__)                     ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
+
+/**
+  * @brief  Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
+  * @param  __HANDLE__: ETH Handle.
+  * @retval None
+  */
+#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__)                     do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
+                                                                          (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
+
+/**
+  * @brief  Enables the MMC Counter Freeze.
+  * @param  __HANDLE__: ETH Handle.
+  * @retval None
+  */
+#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__)                  ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
+
+/**
+  * @brief  Disables the MMC Counter Freeze.
+  * @param  __HANDLE__: ETH Handle.
+  * @retval None
+  */
+#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__)                 ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
+
+/**
+  * @brief  Enables the MMC Reset On Read.
+  * @param  __HANDLE__: ETH Handle.
+  * @retval None
+  */
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
+
+/**
+  * @brief  Disables the MMC Reset On Read.
+  * @param  __HANDLE__: ETH Handle.
+  * @retval None
+  */
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
+
+/**
+  * @brief  Enables the MMC Counter Stop Rollover.
+  * @param  __HANDLE__: ETH Handle.
+  * @retval None
+  */
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__)            ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
+
+/**
+  * @brief  Disables the MMC Counter Stop Rollover.
+  * @param  __HANDLE__: ETH Handle.
+  * @retval None
+  */
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__)           ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
+
+/**
+  * @brief  Resets the MMC Counters.
+  * @param   __HANDLE__: ETH Handle.
+  * @retval None
+  */
+#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__)                         ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
+
+/**
+  * @brief  Enables the specified ETHERNET MMC Rx interrupts.
+  * @param   __HANDLE__: ETH Handle.
+  * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+  *   This parameter can be one of the following values:  
+  *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
+  * @retval None
+  */
+#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__)               (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
+/**
+  * @brief  Disables the specified ETHERNET MMC Rx interrupts.
+  * @param   __HANDLE__: ETH Handle.
+  * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+  *   This parameter can be one of the following values: 
+  *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
+  * @retval None
+  */
+#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__)              (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
+/**
+  * @brief  Enables the specified ETHERNET MMC Tx interrupts.
+  * @param   __HANDLE__: ETH Handle.
+  * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+  *   This parameter can be one of the following values:  
+  *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 
+  * @retval None
+  */
+#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__)            ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
+
+/**
+  * @brief  Disables the specified ETHERNET MMC Tx interrupts.
+  * @param   __HANDLE__: ETH Handle.
+  * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+  *   This parameter can be one of the following values:  
+  *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 
+  * @retval None
+  */
+#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__)           ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))                                             
+
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
+void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
+
+/* IO operation functions  ****************************************************/
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
+
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
+
+ /* Callback in non blocking modes (Interrupt) */
+void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
+
+/* Cmmunication with PHY functions*/
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
+
+/* Peripheral Control functions  **********************************************/
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
+
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
+
+/* Peripheral State functions  ************************************************/
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_ETH_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,749 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_flash.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the internal FLASH memory:
+  *           + Program operations functions
+  *           + Memory Control functions 
+  *           + Peripheral Errors functions
+  *         
+  @verbatim
+  ==============================================================================
+                        ##### FLASH peripheral features #####
+  ==============================================================================
+           
+  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses 
+       to the Flash memory. It implements the erase and program Flash memory operations 
+       and the read and write protection mechanisms.
+      
+  [..] The Flash memory interface accelerates code execution with a system of instruction
+       prefetch and cache lines. 
+
+  [..] The FLASH main features are:
+      (+) Flash memory read operations
+      (+) Flash memory program/erase operations
+      (+) Read / write protections
+      (+) Prefetch on I-Code
+      (+) 64 cache lines of 128 bits on I-Code
+      (+) 8 cache lines of 128 bits on D-Code
+      
+      
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]                             
+      This driver provides functions and macros to configure and program the FLASH 
+      memory of all STM32F4xx devices.
+    
+      (#) FLASH Memory IO Programming functions: 
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and 
+                HAL_FLASH_Lock() functions
+           (++) Program functions: byte, half word, word and double word
+           (++) There Two modes of programming :
+            (+++) Polling mode using HAL_FLASH_Program() function
+            (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+    
+      (#) Interrupts and flags management functions : 
+           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+           (++) Wait for last FLASH operation according to its status
+           (++) Get error flag status by calling HAL_SetErrorCode()          
+
+    [..] 
+      In addition to these functions, this driver includes a set of macros allowing
+      to handle the following operations:
+       (+) Set the latency
+       (+) Enable/Disable the prefetch buffer
+       (+) Enable/Disable the Instruction cache and the Data cache
+       (+) Reset the Instruction cache and the Data cache
+       (+) Enable/Disable the FLASH interrupts
+       (+) Monitor the FLASH flags status
+          
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASH
+  * @brief FLASH HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define SECTOR_MASK               ((uint32_t)0xFFFFFF07)
+
+#define HAL_FLASH_TIMEOUT_VALUE   ((uint32_t)50000)/* 50 s */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Variable used for Erase sectors under interruption */
+FLASH_ProcessTypeDef pFlash;
+
+
+/* Private function prototypes -----------------------------------------------*/
+/* Program operations */
+static void   FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
+static void   FLASH_Program_Word(uint32_t Address, uint32_t Data);
+static void   FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
+static void   FLASH_Program_Byte(uint32_t Address, uint8_t Data);
+static void   FLASH_SetErrorCode(void);
+
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private functions
+  * @{
+  */
+  
+/** @defgroup FLASH_Group1 Programming operation functions 
+ *  @brief   Programming operation functions 
+ *
+@verbatim   
+ ===============================================================================
+                  ##### Programming operation functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the FLASH 
+    program operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Program byte, halfword, word or double word at a specified address
+  * @param  TypeProgram:  Indicate the way to program at a specified address.
+  *                           This parameter can be a value of @ref FLASH_Type_Program
+  * @param  Address:  specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed
+  * 
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_TYPEPROGRAM(TypeProgram));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+  
+  if(status == HAL_OK)
+  {
+    if(TypeProgram == TYPEPROGRAM_BYTE)
+    {
+      /*Program byte (8-bit) at a specified address.*/
+        FLASH_Program_Byte(Address, (uint8_t) Data);
+    }
+    else if(TypeProgram == TYPEPROGRAM_HALFWORD)
+    {
+      /*Program halfword (16-bit) at a specified address.*/
+      FLASH_Program_HalfWord(Address, (uint16_t) Data);
+    }
+    else if(TypeProgram == TYPEPROGRAM_WORD)
+    {
+      /*Program word (32-bit) at a specified address.*/
+      FLASH_Program_Word(Address, (uint32_t) Data);
+    }
+    else
+    {
+      /*Program double word (64-bit) at a specified address.*/
+      FLASH_Program_DoubleWord(Address, Data);
+    }
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+    
+    /* If the program operation is completed, disable the PG Bit */
+    FLASH->CR &= (~FLASH_CR_PG);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief   Program byte, halfword, word or double word at a specified address  with interrupt enabled.
+  * @param  TypeProgram:  Indicate the way to program at a specified address.
+  *                           This parameter can be a value of @ref FLASH_Type_Program
+  * @param  Address:  specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_TYPEPROGRAM(TypeProgram));
+
+  /* Enable End of FLASH Operation interrupt */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
+  
+  /* Enable Error source interrupt */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
+  
+  /* Clear pending flags (if any) */  
+  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
+                         FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR);  
+
+  pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
+  pFlash.Address = Address;
+
+  if(TypeProgram == TYPEPROGRAM_BYTE)
+  {
+    /*Program byte (8-bit) at a specified address.*/
+      FLASH_Program_Byte(Address, (uint8_t) Data);
+  }
+  else if(TypeProgram == TYPEPROGRAM_HALFWORD)
+  {
+    /*Program halfword (16-bit) at a specified address.*/
+    FLASH_Program_HalfWord(Address, (uint16_t) Data);
+  }
+  else if(TypeProgram == TYPEPROGRAM_WORD)
+  {
+    /*Program word (32-bit) at a specified address.*/
+    FLASH_Program_Word(Address, (uint32_t) Data);
+  }
+  else
+  {
+    /*Program double word (64-bit) at a specified address.*/
+    FLASH_Program_DoubleWord(Address, Data);
+  }
+
+  return status;
+}
+
+/**
+  * @brief This function handles FLASH interrupt request.
+  * @param  None
+  * @retval None
+  */
+void HAL_FLASH_IRQHandler(void)
+{
+  uint32_t temp;
+  
+  /* If the program operation is completed, disable the PG Bit */
+  FLASH->CR &= (~FLASH_CR_PG);
+
+  /* If the erase operation is completed, disable the SER Bit */
+  FLASH->CR &= (~FLASH_CR_SER);
+  FLASH->CR &= SECTOR_MASK; 
+
+  /* if the erase operation is completed, disable the MER Bit */
+  FLASH->CR &= (~FLASH_MER_BIT);
+
+  /* Check FLASH End of Operation flag  */
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
+  {
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
+    {
+      /*Nb of sector to erased can be decreased*/
+      pFlash.NbSectorsToErase--;
+
+      /* Check if there are still sectors to erase*/
+      if(pFlash.NbSectorsToErase != 0)
+      {
+        temp = pFlash.Sector;
+        /*Indicate user which sector has been erased*/
+        HAL_FLASH_EndOfOperationCallback(temp);
+
+        /* Clear pending flags (if any) */  
+        __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
+         FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR);  
+
+        /*Increment sector number*/
+        temp = ++pFlash.Sector;
+        FLASH_Erase_Sector(temp, pFlash.VoltageForErase);
+      }
+      else
+      {
+        /*No more sectors to Erase, user callback can be called.*/
+        /*Reset Sector and stop Erase sectors procedure*/
+        pFlash.Sector = temp = 0xFFFFFFFF;
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(temp);
+        /* Clear FLASH End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+      }
+    }
+    else 
+    {
+      if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) 
+      {
+        /*MassErase ended. Return the selected bank*/
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
+      }
+      else
+      {
+        /*Program ended. Return the selected address*/
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+      }
+      pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+      /* Clear FLASH End of Operation pending bit */
+      __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+    }
+
+  }
+  
+  /* Check FLASH operation error flags */
+  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+                           FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
+  {
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
+    {
+      /*return the faulty sector*/
+      temp = pFlash.Sector;
+      pFlash.Sector = 0xFFFFFFFF;
+    }
+    else if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+    {
+      /*return the faulty bank*/
+      temp = pFlash.Bank;
+    }
+    else
+    {
+      /*retrun the faulty address*/
+      temp = pFlash.Address;
+    }
+    
+    /*Save the Error code*/
+    FLASH_SetErrorCode();
+
+    /* FLASH error interrupt user callback */
+    HAL_FLASH_OperationErrorCallback(temp);
+    /* Clear FLASH error pending bits */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR  | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR |\
+                           FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR);
+
+    /*Stop the procedure ongoing*/
+    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+  }
+  
+  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+  {
+    /* Disable End of FLASH Operation interrupt */
+    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
+
+    /* Disable Error source interrupt */
+    __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+  
+}
+
+/**
+  * @brief  FLASH end of operation interrupt callback
+  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
+  *                  Mass Erase: Bank number which has been requested to erase
+  *                  Sectors Erase: Sector which has been erased 
+  *                    (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
+  *                  Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  FLASH operation error interrupt callback
+  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
+  *                 Mass Erase: Bank number which has been requested to erase
+  *                 Sectors Erase: Sector number which returned an error
+  *                 Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Group2 Peripheral Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the FLASH 
+    memory operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlock the FLASH control register access
+  * @param  None
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+  if((FLASH->CR & FLASH_CR_LOCK) != RESET)
+  {
+    /* Authorize the FLASH Registers access */
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Locks the FLASH control register access
+  * @param  None
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Registers access */
+  FLASH->CR |= FLASH_CR_LOCK;
+  
+  return HAL_OK;  
+}
+
+
+/**
+  * @brief  Unlock the FLASH Option Control Registers access.
+  * @param  None
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+  if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
+  {
+    /* Authorizes the Option Byte register programming */
+    FLASH->OPTKEYR = FLASH_OPT_KEY1;
+    FLASH->OPTKEYR = FLASH_OPT_KEY2;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }  
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Lock the FLASH Option Control Registers access.
+  * @param  None
+  * @retval HAL Status 
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+  FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Launch the option byte loading.
+  * @param  None
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+  /* Set the OPTSTRT bit in OPTCR register */
+  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
+
+  /* Wait for last operation to be completed */
+  return(FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Group3 Peripheral State and Errors functions 
+ *  @brief   Peripheral Errors functions 
+ *
+@verbatim   
+ ===============================================================================
+                ##### Peripheral Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time Errors of the FLASH peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the specific FLASH error flag.
+  * @param  None
+  * @retval FLASH_ErrorCode: The returned value can be:
+  *            @arg FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
+  *            @arg FLASH_ERROR_PGS: FLASH Programming Sequence error flag 
+  *            @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag  
+  *            @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag
+  *            @arg FLASH_ERROR_WRP: FLASH Write protected error flag
+  *            @arg FLASH_ERROR_OPERATION: FLASH operation Error flag 
+  */
+FLASH_ErrorTypeDef HAL_FLASH_GetError(void)
+{ 
+   return pFlash.ErrorCode;
+}  
+  
+/**
+  * @}
+  */    
+
+/**
+  * @brief  Wait for a FLASH operation to complete.
+  * @param  Timeout: maximum flash operationtimeout
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+{ 
+  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+     Even if the FLASH operation fails, the BUSY flag will be reset and an error
+     flag will be set */
+    
+  uint32_t timeout = HAL_GetTick() + Timeout;
+     
+  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) 
+  { 
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        return HAL_TIMEOUT;
+      }
+    } 
+  }
+  
+  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+                           FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
+  {
+    /*Save the error code*/
+    FLASH_SetErrorCode();
+    return HAL_ERROR;
+  }
+
+  /* If there is an error flag set */
+  return HAL_OK;
+  
+}  
+
+/**
+  * @brief  Program a double word (64-bit) at a specified address.
+  * @note   This function must be used when the device voltage range is from
+  *         2.7V to 3.6V and an External Vpp is present.
+  *
+  * @note   If an erase and a program operations are requested simultaneously,    
+  *         the erase operation is performed before the program one.
+  *  
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  
+  /* If the previous operation is completed, proceed to program the new data */
+  FLASH->CR &= CR_PSIZE_MASK;
+  FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
+  FLASH->CR |= FLASH_CR_PG;
+
+  *(__IO uint64_t*)Address = Data;
+}
+
+
+/**
+  * @brief  Program word (32-bit) at a specified address.
+  * @note   This function must be used when the device voltage range is from
+  *         2.7V to 3.6V.
+  *
+  * @note   If an erase and a program operations are requested simultaneously,    
+  *         the erase operation is performed before the program one.
+  *  
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  
+  /* If the previous operation is completed, proceed to program the new data */
+  FLASH->CR &= CR_PSIZE_MASK;
+  FLASH->CR |= FLASH_PSIZE_WORD;
+  FLASH->CR |= FLASH_CR_PG;
+
+  *(__IO uint32_t*)Address = Data;
+}
+
+/**
+  * @brief  Program a half-word (16-bit) at a specified address.
+  * @note   This function must be used when the device voltage range is from
+  *         2.7V to 3.6V.
+  *
+  * @note   If an erase and a program operations are requested simultaneously,    
+  *         the erase operation is performed before the program one.
+  *  
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  
+  /* If the previous operation is completed, proceed to program the new data */
+  FLASH->CR &= CR_PSIZE_MASK;
+  FLASH->CR |= FLASH_PSIZE_HALF_WORD;
+  FLASH->CR |= FLASH_CR_PG;
+
+  *(__IO uint16_t*)Address = Data;
+}
+
+/**
+  * @brief  Program byte (8-bit) at a specified address.
+  * @note   This function must be used when the device voltage range is from
+  *         2.7V to 3.6V.
+  *
+  * @note   If an erase and a program operations are requested simultaneously,    
+  *         the erase operation is performed before the program one.
+  *  
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  
+  /* If the previous operation is completed, proceed to program the new data */
+  FLASH->CR &= CR_PSIZE_MASK;
+  FLASH->CR |= FLASH_PSIZE_BYTE;
+  FLASH->CR |= FLASH_CR_PG;
+
+  *(__IO uint8_t*)Address = Data;
+}
+
+/**
+  * @brief  Set the specific FLASH error flag.
+  * @param  None
+  * @retval None
+  */
+static void FLASH_SetErrorCode(void)
+{ 
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
+  {
+   pFlash.ErrorCode = FLASH_ERROR_WRP;
+  }
+  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
+  {
+   pFlash.ErrorCode |= FLASH_ERROR_PGA;
+  }
+  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
+  {
+    pFlash.ErrorCode |= FLASH_ERROR_PGP;
+  }
+  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET)
+  {
+    pFlash.ErrorCode |= FLASH_ERROR_PGS;
+  }
+  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
+  {
+    pFlash.ErrorCode |= FLASH_ERROR_RD;
+  }
+  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
+  {
+    pFlash.ErrorCode |= FLASH_ERROR_OPERATION;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,363 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_flash.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of FLASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_FLASH_H
+#define __STM32F4xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/**
+  * @brief  FLASH Error structure definition
+  */
+typedef enum
+{ 
+  FLASH_ERROR_RD =  0x01,
+  FLASH_ERROR_PGS = 0x02,
+  FLASH_ERROR_PGP = 0x04,
+  FLASH_ERROR_PGA = 0x08,
+  FLASH_ERROR_WRP = 0x10,
+  FLASH_ERROR_OPERATION = 0x20
+}FLASH_ErrorTypeDef;
+
+/**
+  * @brief  FLASH Procedure structure definition
+  */
+typedef enum 
+{
+  FLASH_PROC_NONE = 0, 
+  FLASH_PROC_SECTERASE,
+  FLASH_PROC_MASSERASE,
+  FLASH_PROC_PROGRAM
+} FLASH_ProcedureTypeDef;
+
+
+/** 
+  * @brief  FLASH handle Structure definition  
+  */
+typedef struct
+{
+  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /*Internal variable to indicate which procedure is ongoing or not in IT context*/
+  
+  __IO uint32_t               NbSectorsToErase;   /*Internal variable to save the remaining sectors to erase in IT context*/
+  
+  __IO uint8_t                VoltageForErase;    /*Internal variable to provide voltange range selected by user in IT context*/
+  
+  __IO uint32_t               Sector;             /*Internal variable to define the current sector which is erasing*/
+  
+  __IO uint32_t               Bank;               /*Internal variable to save current bank selected during mass erase*/
+  
+  __IO uint32_t               Address;            /*Internal variable to save address selected for program*/
+  
+  HAL_LockTypeDef             Lock;               /* FLASH locking object                */
+
+  __IO FLASH_ErrorTypeDef     ErrorCode;          /* FLASH error code                    */
+
+}FLASH_ProcessTypeDef;
+
+/** 
+  * @brief FLASH Error source  
+  */ 
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+  * @{
+  */  
+
+
+
+/** @defgroup FLASH_Type_Program FLASH Type Program
+  * @{
+  */ 
+#define TYPEPROGRAM_BYTE        ((uint32_t)0x00)  /*!< Program byte (8-bit) at a specified address           */
+#define TYPEPROGRAM_HALFWORD    ((uint32_t)0x01)  /*!< Program a half-word (16-bit) at a specified address   */
+#define TYPEPROGRAM_WORD        ((uint32_t)0x02)  /*!< Program a word (32-bit) at a specified address        */
+#define TYPEPROGRAM_DOUBLEWORD  ((uint32_t)0x03)  /*!< Program a double word (64-bit) at a specified address */
+
+#define IS_TYPEPROGRAM(VALUE)(((VALUE) == TYPEPROGRAM_BYTE) || \
+                              ((VALUE) == TYPEPROGRAM_HALFWORD) || \
+                              ((VALUE) == TYPEPROGRAM_WORD) || \
+                              ((VALUE) == TYPEPROGRAM_DOUBLEWORD))  
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flag_definition FLASH Flag definition
+  * @brief Flag definition
+  * @{
+  */ 
+#define FLASH_FLAG_EOP                 FLASH_SR_EOP            /*!< FLASH End of Operation flag               */
+#define FLASH_FLAG_OPERR               FLASH_SR_SOP            /*!< FLASH operation Error flag                */
+#define FLASH_FLAG_WRPERR              FLASH_SR_WRPERR         /*!< FLASH Write protected error flag          */
+#define FLASH_FLAG_PGAERR              FLASH_SR_PGAERR         /*!< FLASH Programming Alignment error flag    */
+#define FLASH_FLAG_PGPERR              FLASH_SR_PGPERR         /*!< FLASH Programming Parallelism error flag  */
+#define FLASH_FLAG_PGSERR              FLASH_SR_PGSERR         /*!< FLASH Programming Sequence error flag     */
+#define FLASH_FLAG_RDERR               ((uint32_t)0x00000100)  /*!< Read Protection error flag (PCROP)        */
+#define FLASH_FLAG_BSY                 FLASH_SR_BSY            /*!< FLASH Busy flag                           */ 
+
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
+  * @brief FLASH Interrupt definition
+  * @{
+  */ 
+#define FLASH_IT_EOP                   FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_ERR                   ((uint32_t)0x02000000)  /*!< Error Interrupt source                  */
+
+/**
+  * @}
+  */  
+
+/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
+  * @{
+  */
+#define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000)
+#define FLASH_PSIZE_HALF_WORD      ((uint32_t)0x00000100)
+#define FLASH_PSIZE_WORD           ((uint32_t)0x00000200)
+#define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)0x00000300)
+#define CR_PSIZE_MASK              ((uint32_t)0xFFFFFCFF)
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Keys FLASH Keys
+  * @{
+  */ 
+#define RDP_KEY                  ((uint16_t)0x00A5)
+#define FLASH_KEY1               ((uint32_t)0x45670123)
+#define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
+#define FLASH_OPT_KEY1           ((uint32_t)0x08192A3B)
+#define FLASH_OPT_KEY2           ((uint32_t)0x4C5D6E7F)
+/**
+  * @}
+  */ 
+
+/** 
+  * @brief   ACR register byte 0 (Bits[7:0]) base address  
+  */ 
+#define ACR_BYTE0_ADDRESS           ((uint32_t)0x40023C00) 
+/** 
+  * @brief   OPTCR register byte 0 (Bits[7:0]) base address  
+  */ 
+#define OPTCR_BYTE0_ADDRESS         ((uint32_t)0x40023C14)
+/** 
+  * @brief   OPTCR register byte 1 (Bits[15:8]) base address  
+  */ 
+#define OPTCR_BYTE1_ADDRESS         ((uint32_t)0x40023C15)
+/** 
+  * @brief   OPTCR register byte 2 (Bits[23:16]) base address  
+  */ 
+#define OPTCR_BYTE2_ADDRESS         ((uint32_t)0x40023C16)
+/** 
+  * @brief   OPTCR register byte 3 (Bits[31:24]) base address  
+  */ 
+#define OPTCR_BYTE3_ADDRESS         ((uint32_t)0x40023C17)
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+  * @brief  Set the FLASH Latency.
+  * @param  __LATENCY__: FLASH Latency                   
+  *         The value of this parameter depend on device used within the same series
+  * @retval none
+  */ 
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))
+
+/**
+  * @brief  Enable the FLASH prefetch buffer.
+  * @retval none
+  */ 
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()  (FLASH->ACR |= FLASH_ACR_PRFTEN)
+
+/**
+  * @brief  Disable the FLASH prefetch buffer.
+  * @retval none
+  */ 
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
+
+/**
+  * @brief  Enable the FLASH instruction cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  (FLASH->ACR |= FLASH_ACR_ICEN)
+
+/**
+  * @brief  Disable the FLASH instruction cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_ICEN))
+
+/**
+  * @brief  Enable the FLASH data cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_DATA_CACHE_ENABLE()  (FLASH->ACR |= FLASH_ACR_DCEN)
+
+/**
+  * @brief  Disable the FLASH data cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_DATA_CACHE_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_DCEN))
+
+/**
+  * @brief  Resets the FLASH instruction Cache.
+  * @note   This function must be used only when the Instruction Cache is disabled.  
+  * @retval None
+  */
+#define __HAL_FLASH_INSTRUCTION_CACHE_RESET()  (FLASH->ACR |= FLASH_ACR_ICRST)
+
+/**
+  * @brief  Resets the FLASH data Cache.
+  * @note   This function must be used only when the data Cache is disabled.  
+  * @retval None
+  */
+#define __HAL_FLASH_DATA_CACHE_RESET()  (FLASH->ACR |= FLASH_ACR_DCRST)
+
+/**
+  * @brief  Enable the specified FLASH interrupt.
+  * @param  __INTERRUPT__ : FLASH interrupt 
+  *         This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+  *     @arg FLASH_IT_ERR: Error Interrupt    
+  * @retval none
+  */  
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  (FLASH->CR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified FLASH interrupt.
+  * @param  __INTERRUPT__ : FLASH interrupt 
+  *         This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+  *     @arg FLASH_IT_ERR: Error Interrupt    
+  * @retval none
+  */  
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
+
+/**
+  * @brief  Get the specified FLASH flag status. 
+  * @param  __FLAG__: specifies the FLASH flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag 
+  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag 
+  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
+  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
+  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
+  *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
+  *            @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) 
+  *            @arg FLASH_FLAG_BSY   : FLASH Busy flag
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define __HAL_FLASH_GET_FLAG(__FLAG__)   ((FLASH->SR & (__FLAG__)))
+
+/**
+  * @brief  Clear the specified FLASH flag.
+  * @param  __FLAG__: specifies the FLASH flags to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag 
+  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag 
+  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
+  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag 
+  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
+  *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
+  *            @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP)   
+  * @retval none
+  */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   (FLASH->SR = (__FLAG__))
+
+/* Include FLASH HAL Extension module */
+#include "stm32f4xx_hal_flash_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/* Program operation functions  ***********************************************/
+HAL_StatusTypeDef   HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef   HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+/* FLASH IRQ handler method */
+void                HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */ 
+void         HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void         HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+
+/* Peripheral Control functions  **********************************************/
+HAL_StatusTypeDef   HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef   HAL_FLASH_Lock(void);
+HAL_StatusTypeDef   HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef   HAL_FLASH_OB_Lock(void);
+/* Option bytes control */
+HAL_StatusTypeDef   HAL_FLASH_OB_Launch(void);
+
+/* Peripheral State functions  ************************************************/
+FLASH_ErrorTypeDef  HAL_FLASH_GetError(void);
+
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1300 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_flash_ex.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Extended FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the FLASH extension peripheral:
+  *           + Extended programming operations functions
+  *  
+  @verbatim
+  ==============================================================================
+                   ##### Flash Extension features #####
+  ==============================================================================
+           
+  [..] Comparing to other previous devices, the FLASH interface for STM32F427xx/437xx and 
+       STM32F429xx/439xx devices contains the following additional features 
+       
+       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
+           capability (RWW)
+       (+) Dual bank memory organization       
+       (+) PCROP protection for all banks
+   
+                      ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to configure and program the FLASH memory 
+       of all STM32F427xx/437xx andSTM32F429xx/439xx devices. It includes
+      (#) FLASH Memory Erase functions: 
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and 
+                HAL_FLASH_Lock() functions
+           (++) Erase function: Erase sector, erase all sectors
+           (++) There are two modes of erase :
+             (+++) Polling Mode using HAL_FLASHEx_Erase()
+             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
+             
+      (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
+           (++) Set/Reset the write protection
+           (++) Set the Read protection Level
+           (++) Set the BOR level
+           (++) Program the user Option Bytes
+      (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to :  
+       (++) Extended space (bank 2) erase function
+       (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2)
+       (++) Dual Boot actrivation
+       (++) Write protection configuration for bank 2
+       (++) PCROP protection configuration and control for both banks
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASHEx
+  * @brief FLASH HAL Extension module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define SECTOR_MASK               ((uint32_t)0xFFFFFF07)
+
+#define HAL_FLASH_TIMEOUT_VALUE   ((uint32_t)50000)/* 50 s */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+extern FLASH_ProcessTypeDef pFlash;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Option bytes control */
+static void               FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
+static HAL_StatusTypeDef  FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
+static HAL_StatusTypeDef  FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks);
+static HAL_StatusTypeDef  FLASH_OB_RDP_LevelConfig(uint8_t Level);
+static HAL_StatusTypeDef  FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby);
+static HAL_StatusTypeDef  FLASH_OB_BOR_LevelConfig(uint8_t Level);
+static uint8_t            FLASH_OB_GetUser(void);
+static uint16_t           FLASH_OB_GetWRP(void);
+static FlagStatus         FLASH_OB_GetRDP(void);
+static uint8_t            FLASH_OB_GetBOR(void);
+
+#if defined(STM32F401xC) || defined(STM32F401xE)
+static HAL_StatusTypeDef  FLASH_OB_EnablePCROP(uint32_t Sector);
+static HAL_StatusTypeDef  FLASH_OB_DisablePCROP(uint32_t Sector);
+#endif /* STM32F401xC || STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 
+static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
+static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
+static HAL_StatusTypeDef  FLASH_OB_BootConfig(uint8_t BootConfig);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+/* Private functions ---------------------------------------------------------*/
+extern HAL_StatusTypeDef         FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/** @defgroup FLASHEx_Private_Functions Extended FLASH Private functions
+  * @{
+  */
+
+/** @defgroup FLASHEx_Group1 Extended IO operation functions
+ *  @brief   Extended IO operation functions 
+ *
+@verbatim   
+ ===============================================================================
+                ##### Extended programming operation functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the Extension FLASH 
+    programming operations Operations.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory sectors 
+  * @param[in]  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  * 
+  * @param[out]  SectorError: pointer to variable  that
+  *         contains the configuration information on faulty sector in case of error 
+  *         (0xFFFFFFFF means that all the sectors have been correctly erased)
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t index = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    /*Initialization of SectorError variable*/
+    *SectorError = 0xFFFFFFFF;
+    
+    if (pEraseInit->TypeErase == TYPEERASE_MASSERASE)
+    {
+      /*Mass erase to be done*/
+      FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+      
+      /* if the erase operation is completed, disable the MER Bit */
+      FLASH->CR &= (~FLASH_MER_BIT);
+    }
+    else
+    {
+      /* Check the parameters */
+      assert_param(IS_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
+
+      /* Erase by sector by sector to be done*/
+      for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
+      {
+        FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+        
+        /* If the erase operation is completed, disable the SER Bit */
+        FLASH->CR &= (~FLASH_CR_SER);
+        FLASH->CR &= SECTOR_MASK; 
+
+        if (status != HAL_OK) 
+        {
+          /* In case of error, stop erase procedure and return the faulty sector*/
+          *SectorError = index;
+          break;
+        }
+      }
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory sectors  with interrupt enabled
+  * @param  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
+
+  /* Enable End of FLASH Operation interrupt */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
+  
+  /* Enable Error source interrupt */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
+  
+  /* Clear pending flags (if any) */  
+  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
+                         FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR);  
+  
+  if (pEraseInit->TypeErase == TYPEERASE_MASSERASE)
+  {
+    /*Mass erase to be done*/
+    pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
+    pFlash.Bank = pEraseInit->Banks;
+    FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
+  }
+  else
+  {
+    /* Erase by sector to be done*/
+
+    /* Check the parameters */
+    assert_param(IS_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
+
+    pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
+    pFlash.NbSectorsToErase = pEraseInit->NbSectors;
+    pFlash.Sector = pEraseInit->Sector;
+    pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
+
+    /*Erase 1st sector and wait for IT*/
+    FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);
+  }
+
+  return status;
+}
+
+/**
+  * @brief   Program option bytes
+  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+  /*Write protection configuration*/
+  if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
+  {
+    assert_param(IS_WRPSTATE(pOBInit->WRPState));
+    if (pOBInit->WRPState == WRPSTATE_ENABLE)
+    {
+      /*Enable of Write protection on the selected Sector*/
+      status = FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks);
+    }
+    else
+    {
+      /*Disable of Write protection on the selected Sector*/
+      status = FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
+    }
+  }
+
+  /*Read protection configuration*/
+  if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
+  {
+    status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
+  }
+
+  /*USER  configuration*/
+  if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
+  {
+    status = FLASH_OB_UserConfig(pOBInit->USERConfig&OB_IWDG_SW, 
+                                     pOBInit->USERConfig&OB_STOP_NO_RST,
+                                     pOBInit->USERConfig&OB_STDBY_NO_RST);
+  }
+
+  /*BOR Level  configuration*/
+  if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
+  {
+    status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief   Get the Option byte configuration
+  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  * 
+  * @retval None
+  */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR;
+
+  /*Get WRP*/
+  pOBInit->WRPSector = FLASH_OB_GetWRP();
+
+  /*Get RDP Level*/
+  pOBInit->RDPLevel = FLASH_OB_GetRDP();
+
+  /*Get USER*/
+  pOBInit->USERConfig = FLASH_OB_GetUser();
+
+  /*Get BOR Level*/
+  pOBInit->BORLevel = FLASH_OB_GetBOR();
+}
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
+/**
+  * @brief   Program option bytes
+  * @param  pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
+  *         contains the configuration information for the programming.
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_OBEX(pAdvOBInit->OptionType));
+
+  /*Program PCROP option byte*/
+  if (((pAdvOBInit->OptionType) & OBEX_PCROP) == OBEX_PCROP)
+  {
+    /* Check the parameters */
+    assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState));
+    if ((pAdvOBInit->PCROPState) == PCROPSTATE_ENABLE)
+    {
+      /*Enable of Write protection on the selected Sector*/
+#if defined(STM32F401xC) || defined(STM32F401xE) 
+      status = FLASH_OB_EnablePCROP(pAdvOBInit->Sectors);
+#else  /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+      status = FLASH_OB_EnablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
+#endif /* STM32F401xC || STM32F401xE */
+    }
+    else
+    {
+      /*Disable of Write protection on the selected Sector*/
+#if defined(STM32F401xC) || defined(STM32F401xE) 
+      status = FLASH_OB_DisablePCROP(pAdvOBInit->Sectors);
+#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+      status = FLASH_OB_DisablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
+#endif /* STM32F401xC || STM32F401xE */
+    }
+  }
+   
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+  /*Program BOOT config option byte*/
+  if (((pAdvOBInit->OptionType) & OBEX_BOOTCONFIG) == OBEX_BOOTCONFIG)
+  {
+    status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig);
+  }
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+  return status;
+}
+
+/**
+  * @brief   Get the OBEX byte configuration
+  * @param  pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
+  *         contains the configuration information for the programming.
+  * 
+  * @retval None
+  */
+void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
+{
+#if defined(STM32F401xC) || defined(STM32F401xE)
+  /*Get Sector*/
+  pAdvOBInit->Sectors = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
+#else  /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+  /*Get Sector for Bank1*/
+  pAdvOBInit->SectorsBank1 = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
+
+  /*Get Sector for Bank2*/
+  pAdvOBInit->SectorsBank2 = (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
+
+  /*Get Boot config OB*/
+  pAdvOBInit->BootConfig = *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS;
+#endif /* STM32F401xC || STM32F401xE */
+}
+
+/**
+  * @brief  Select the Protection Mode 
+  * 
+  * @note   After PCROP activated Option Byte modification NOT POSSIBLE! excepted 
+  *         Global Read Out Protection modification (from level1 to level0) 
+  * @note   Once SPRMOD bit is active unprotection of a protected sector is not possible 
+  * @note   Read a prtotected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
+  * @note   This function can be used only for STM32F427xx/STM32F429xx/STM32F437xx/STM32F439xx/STM32F401xx devices.     
+  * 
+  * @param  None
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
+{
+  uint8_t optiontmp = 0xFF;
+
+  /* Mask SPRMOD bit */
+  optiontmp =  (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); 
+  
+  /* Update Option Byte */
+  *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_SELECTED | optiontmp); 
+  
+  return HAL_OK;
+  
+}
+
+/**
+  * @brief  Deselect the Protection Mode 
+  * 
+  * @note   After PCROP activated Option Byte modification NOT POSSIBLE! excepted 
+  *         Global Read Out Protection modification (from level1 to level0) 
+  * @note   Once SPRMOD bit is active unprotection of a protected sector is not possible 
+  * @note   Read a prtotected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
+  * @note   This function can be used only for STM32F427xx/STM32F429xx/STM32F437xx/STM32F439xx/STM32F401xx devices.     
+  * 
+  * @param  None
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
+{
+  uint8_t optiontmp = 0xFF;
+  
+  /* Mask SPRMOD bit */
+  optiontmp =  (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); 
+  
+  /* Update Option Byte */
+  *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_DESELECTED | optiontmp);  
+  
+  return HAL_OK;
+}
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+
+/**
+  * @brief  Returns the FLASH Write Protection Option Bytes value for Bank 2
+  * @note   This function can be used only for STM32F427X and STM32F429X devices.  
+  * @param  None
+  * @retval The FLASH Write Protection  Option Bytes value
+  */
+uint16_t HAL_FLASHEx_OB_GetBank2WRP(void)
+{                            
+  /* Return the FLASH write protection Register value */
+  return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/**
+  * @}
+  */
+  
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/**
+  * @brief  Full erase of FLASH memory sectors 
+  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
+  *          This parameter can be one of the following values:
+  *            @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
+  *                                  the operation will be done by byte (8-bit) 
+  *            @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+  *                                  the operation will be done by half word (16-bit)
+  *            @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+  *                                  the operation will be done by word (32-bit)
+  *            @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
+  *                                  the operation will be done by double word (64-bit)
+  * 
+  * @param  Banks: Banks to be erased
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *            @arg FLASH_BANK_2: Bank2 to be erased
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+  *
+  * @retval HAL Status
+  */
+static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
+{
+  uint32_t tmp_psize = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* if the previous operation is completed, proceed to erase all sectors */
+  FLASH->CR &= CR_PSIZE_MASK;
+  FLASH->CR |= tmp_psize;
+  if(Banks == FLASH_BANK_BOTH)
+  {
+    /* bank1 & bank2 will be erased*/
+    FLASH->CR |= FLASH_MER_BIT;
+  }
+  else if(Banks == FLASH_BANK_1)
+  {
+    /*Only bank1 will be erased*/
+    FLASH->CR |= FLASH_CR_MER1;
+  }
+  else
+  {
+    /*Only bank2 will be erased*/
+    FLASH->CR |= FLASH_CR_MER2;
+  }
+  FLASH->CR |= FLASH_CR_STRT;
+}
+
+/**
+  * @brief  Erase the specified FLASH memory sector
+  * @param  Sector: FLASH sector to erase
+  *         The value of this parameter depend on device used within the same series      
+  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
+  *          This parameter can be one of the following values:
+  *            @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
+  *                                  the operation will be done by byte (8-bit) 
+  *            @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+  *                                  the operation will be done by half word (16-bit)
+  *            @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+  *                                  the operation will be done by word (32-bit)
+  *            @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
+  *                                  the operation will be done by double word (64-bit)
+  * 
+  * @retval None
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
+{
+  uint32_t tmp_psize = 0;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_SECTOR(Sector));
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+  
+  if(VoltageRange == VOLTAGE_RANGE_1)
+  {
+     tmp_psize = FLASH_PSIZE_BYTE;
+  }
+  else if(VoltageRange == VOLTAGE_RANGE_2)
+  {
+    tmp_psize = FLASH_PSIZE_HALF_WORD;
+  }
+  else if(VoltageRange == VOLTAGE_RANGE_3)
+  {
+    tmp_psize = FLASH_PSIZE_WORD;
+  }
+  else
+  {
+    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
+  }
+
+  /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
+  if (Sector > FLASH_SECTOR_11) 
+  {
+    Sector += 4;
+  }
+  /* If the previous operation is completed, proceed to erase the sector */
+  FLASH->CR &= CR_PSIZE_MASK;
+  FLASH->CR |= tmp_psize;
+  FLASH->CR &= SECTOR_MASK;
+  FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
+  FLASH->CR |= FLASH_CR_STRT;
+}
+
+/**
+  * @brief  Enable the write protection of the desired bank1 or bank 2 sectors
+  *
+  * @note   When the memory read protection level is selected (RDP level = 1), 
+  *         it is not possible to program or erase the flash sector i if CortexM4  
+  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 
+  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).   
+  * 
+  * @param  WRPSector: specifies the sector(s) to be write protected.
+  *          This parameter can be one of the following values:
+  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23                      
+  *            @arg OB_WRP_SECTOR_All
+  * @note   BANK2 starts from OB_WRP_SECTOR_12
+  *
+  * @param  Banks: Enable write protection on all the sectors for the specific bank
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
+  *            @arg FLASH_BANK_2: WRP on all sectors of bank2
+  *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
+  *
+  * @retval HAL FLASH State   
+  */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  {
+    if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
+         (WRPSector < OB_WRP_SECTOR_12))
+    {
+       if (WRPSector == OB_WRP_SECTOR_All)
+       {
+          /*Write protection on all sector of BANK1*/
+          *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~(WRPSector>>12));  
+       }
+       else
+       {
+          /*Write protection done on sectors of BANK1*/
+          *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector);  
+       }
+    }
+    else 
+    {
+      /*Write protection done on sectors of BANK2*/
+      *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12));  
+    }
+
+    /*Write protection on all sector of BANK2*/
+    if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
+    {
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+      
+      if(status == HAL_OK)
+      { 
+        *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12));  
+      }
+    }
+    
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Disable the write protection of the desired bank1 or bank 2 sectors
+  *
+  * @note   When the memory read protection level is selected (RDP level = 1), 
+  *         it is not possible to program or erase the flash sector i if CortexM4  
+  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 
+  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).   
+  * 
+  * @param  WRPSector: specifies the sector(s) to be write protected.
+  *          This parameter can be one of the following values:
+  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23                      
+  *            @arg OB_WRP_Sector_All
+  * @note   BANK2 starts from OB_WRP_SECTOR_12
+  *
+  * @param  Banks: Disable write protection on all the sectors for the specific bank
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *            @arg FLASH_BANK_2: Bank2 to be erased
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+  *
+  * @retval HAL Staus   
+  */
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  {
+    if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
+         (WRPSector < OB_WRP_SECTOR_12))
+    {
+       if (WRPSector == OB_WRP_SECTOR_All)
+       {
+          /*Write protection on all sector of BANK1*/
+          *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12); 
+       }
+       else
+       {
+          /*Write protection done on sectors of BANK1*/
+          *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; 
+       }
+    }
+    else 
+    {
+      /*Write protection done on sectors of BANK2*/
+      *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12); 
+    }
+
+    /*Write protection on all sector  of BANK2*/
+    if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
+    {
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+      
+      if(status == HAL_OK)
+      { 
+        *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12); 
+      }
+    }
+    
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the Dual Bank Boot.
+  *   
+  * @note   This function can be used only for STM32F42xxx/43xxx devices.
+  *      
+  * @param  BootConfig specifies the Dual Bank Boot Option byte.
+  *          This parameter can be one of the following values:
+  *            @arg OB_Dual_BootEnabled: Dual Bank Boot Enable
+  *            @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled
+  * @retval None
+  */
+static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT(BootConfig));
+
+  /* Wait for last operation to be completed */  
+  status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  { 
+    /* Set Dual Bank Boot */
+    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);
+    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= BootConfig;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Enable the read/write protection (PCROP) of the desired 
+  *         sectors of Bank 1 and/or Bank 2.
+  * @note   This function can be used only for STM32F42xxx/43xxx devices.
+  * @param  SectorBank1 Specifies the sector(s) to be read/write protected or unprotected for bank1.
+  *          This parameter can be one of the following values:
+  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11
+  *            @arg OB_PCROP_SECTOR__All                         
+  * @param  SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2.
+  *          This parameter can be one of the following values:
+  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23
+  *            @arg OB_PCROP_SECTOR__All                         
+  * @param  Banks Enable PCROP protection on all the sectors for the specific bank
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
+  *            @arg FLASH_BANK_2: WRP on all sectors of bank2
+  *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
+  *
+  * @retval HAL Status  
+  */
+static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  assert_param(IS_FLASH_BANK(Banks));
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  {
+    if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
+    {
+      assert_param(IS_OB_PCROP(SectorBank1));
+      /*Write protection done on sectors of BANK1*/
+      *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)SectorBank1; 
+    }
+    else 
+    {
+      assert_param(IS_OB_PCROP(SectorBank2));
+      /*Write protection done on sectors of BANK2*/
+      *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; 
+    }
+
+    /*Write protection on all sector  of BANK2*/
+    if (Banks == FLASH_BANK_BOTH)
+    {
+      assert_param(IS_OB_PCROP(SectorBank2));
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+      
+      if(status == HAL_OK)
+      { 
+        /*Write protection done on sectors of BANK2*/
+        *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; 
+      }
+    }
+    
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  Disable the read/write protection (PCROP) of the desired 
+  *         sectors  of Bank 1 and/or Bank 2.
+  * @note   This function can be used only for STM32F42xxx/43xxx devices.
+  * @param  SectorBank1 specifies the sector(s) to be read/write protected or unprotected for bank1.
+  *          This parameter can be one of the following values:
+  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11
+  *            @arg OB_PCROP_SECTOR__All                         
+  * @param  SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2.
+  *          This parameter can be one of the following values:
+  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23
+  *            @arg OB_PCROP_SECTOR__All                         
+  * @param  Banks Disable PCROP protection on all the sectors for the specific bank
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
+  *            @arg FLASH_BANK_2: WRP on all sectors of bank2
+  *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
+  *
+  * @retval HAL Status  
+  */
+static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
+{  
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK(Banks));
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  {
+    if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
+    {
+      assert_param(IS_OB_PCROP(SectorBank1));
+      /*Write protection done on sectors of BANK1*/
+      *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~SectorBank1); 
+    }
+    else 
+    {
+      /*Write protection done on sectors of BANK2*/
+      assert_param(IS_OB_PCROP(SectorBank2));
+      *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); 
+    }
+
+    /*Write protection on all sector  of BANK2*/
+    if (Banks == FLASH_BANK_BOTH)
+    {
+      assert_param(IS_OB_PCROP(SectorBank2));
+     /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+      
+      if(status == HAL_OK)
+      { 
+        /*Write protection done on sectors of BANK2*/
+        *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); 
+      }
+    }
+    
+  }
+  
+  return status;
+
+}
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE) 
+/**
+  * @brief  Mass erase of FLASH memory
+  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
+  *          This parameter can be one of the following values:
+  *            @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
+  *                                  the operation will be done by byte (8-bit) 
+  *            @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+  *                                  the operation will be done by half word (16-bit)
+  *            @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+  *                                  the operation will be done by word (32-bit)
+  *            @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
+  *                                  the operation will be done by double word (64-bit)
+  * 
+  * @param  Banks: Banks to be erased
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *
+  * @retval None
+  */
+static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
+{
+  uint32_t tmp_psize = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* If the previous operation is completed, proceed to erase all sectors */
+   FLASH->CR &= CR_PSIZE_MASK;
+   FLASH->CR |= tmp_psize;
+   FLASH->CR |= FLASH_CR_MER;
+   FLASH->CR |= FLASH_CR_STRT;
+}
+
+/**
+  * @brief  Erase the specified FLASH memory sector
+  * @param  Sector: FLASH sector to erase
+  *         The value of this parameter depend on device used within the same series      
+  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
+  *          This parameter can be one of the following values:
+  *            @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
+  *                                  the operation will be done by byte (8-bit) 
+  *            @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+  *                                  the operation will be done by half word (16-bit)
+  *            @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+  *                                  the operation will be done by word (32-bit)
+  *            @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
+  *                                  the operation will be done by double word (64-bit)
+  * 
+  * @retval None
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
+{
+  uint32_t tmp_psize = 0;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_SECTOR(Sector));
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+  
+  if(VoltageRange == VOLTAGE_RANGE_1)
+  {
+     tmp_psize = FLASH_PSIZE_BYTE;
+  }
+  else if(VoltageRange == VOLTAGE_RANGE_2)
+  {
+    tmp_psize = FLASH_PSIZE_HALF_WORD;
+  }
+  else if(VoltageRange == VOLTAGE_RANGE_3)
+  {
+    tmp_psize = FLASH_PSIZE_WORD;
+  }
+  else
+  {
+    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
+  }
+
+  /* If the previous operation is completed, proceed to erase the sector */
+  FLASH->CR &= CR_PSIZE_MASK;
+  FLASH->CR |= tmp_psize;
+  FLASH->CR &= SECTOR_MASK;
+  FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
+  FLASH->CR |= FLASH_CR_STRT;
+}
+
+/**
+  * @brief  Enable the write protection of the desired bank 1 sectors
+  *
+  * @note   When the memory read protection level is selected (RDP level = 1), 
+  *         it is not possible to program or erase the flash sector i if CortexM4  
+  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 
+  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).   
+  * 
+  * @param  WRPSector: specifies the sector(s) to be write protected.
+  *         The value of this parameter depend on device used within the same series 
+  * 
+  * @param  Banks: Enable write protection on all the sectors for the specific bank
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
+  *
+  * @retval HAL Status 
+  */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  { 
+    *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector);  
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Disable the write protection of the desired bank 1 sectors
+  *
+  * @note   When the memory read protection level is selected (RDP level = 1), 
+  *         it is not possible to program or erase the flash sector i if CortexM4  
+  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 
+  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).   
+  * 
+  * @param  WRPSector: specifies the sector(s) to be write protected.
+  *         The value of this parameter depend on device used within the same series 
+  * 
+  * @param  Banks: Enable write protection on all the sectors for the specific bank
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
+  *
+  * @retval HAL Status 
+  */
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  { 
+    *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; 
+  }
+  
+  return status;
+}
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
+
+#if defined(STM32F401xC) || defined(STM32F401xE)
+/**
+  * @brief  Enable the read/write protection (PCROP) of the desired sectors.
+  * @note   This function can be used only for STM32F401xx devices.
+  * @param  Sector specifies the sector(s) to be read/write protected or unprotected.
+  *          This parameter can be one of the following values:
+  *            @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
+  *            @arg OB_PCROP_Sector_All                         
+  * @retval HAL Status  
+  */
+static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_PCROP(Sector));
+    
+  /* Wait for last operation to be completed */  
+  status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  { 
+    *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)Sector;
+  }
+  
+  return status;
+}
+
+
+/**
+  * @brief  Disable the read/write protection (PCROP) of the desired sectors.
+  * @note   This function can be used only for STM32F401xx devices.
+  * @param  Sector specifies the sector(s) to be read/write protected or unprotected.
+  *          This parameter can be one of the following values:
+  *            @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
+  *            @arg OB_PCROP_Sector_All                         
+  * @retval HAL Status  
+  */
+static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector)
+{  
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_PCROP(Sector));
+    
+  /* Wait for last operation to be completed */  
+  status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  { 
+    *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~Sector);
+  }
+  
+  return status;
+
+}
+#endif /* STM32F401xC || STM32F401xE */
+
+/**
+  * @brief  Set the read protection level.
+  * @param  Level: specifies the read protection level.
+  *          This parameter can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  *   
+  * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
+  *    
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_RDP_LEVEL(Level));
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  { 
+    *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.    
+  * @param  Iwdg: Selects the IWDG mode
+  *          This parameter can be one of the following values:
+  *            @arg OB_IWDG_SW: Software IWDG selected
+  *            @arg OB_IWDG_HW: Hardware IWDG selected
+  * @param  Stop: Reset event when entering STOP mode.
+  *          This parameter  can be one of the following values:
+  *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP
+  *            @arg OB_STOP_RST: Reset generated when entering in STOP
+  * @param  Stdby: Reset event when entering Standby mode.
+  *          This parameter  can be one of the following values:
+  *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
+  *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby)
+{
+  uint8_t optiontmp = 0xFF;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_IWDG_SOURCE(Iwdg));
+  assert_param(IS_OB_STOP_SOURCE(Stop));
+  assert_param(IS_OB_STDBY_SOURCE(Stdby));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+  
+  if(status == HAL_OK)
+  {     
+    /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
+    optiontmp =  (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);
+
+    /* Update User Option Byte */
+    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp))); 
+  }
+  
+  return status; 
+
+}
+
+/**
+  * @brief  Set the BOR Level. 
+  * @param  Level: specifies the Option Bytes BOR Reset Level.
+  *          This parameter can be one of the following values:
+  *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
+  *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
+  *            @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
+  *            @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_BOR_LEVEL(Level));
+
+  /* Set the BOR Level */
+  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
+  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= Level;
+  
+  return HAL_OK;
+  
+}
+
+/**
+  * @brief  Return the FLASH User Option Byte value.
+  * @param  None
+  * @retval uint8_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
+  *         and RST_STDBY(Bit2).
+  */
+static uint8_t FLASH_OB_GetUser(void)
+{
+  /* Return the User Option Byte */
+  return ((uint8_t)(FLASH->OPTCR & 0xE0));
+}
+
+/**
+  * @brief  Return the FLASH Write Protection Option Bytes value.
+  * @param  None
+  * @retval uint16_t FLASH Write Protection Option Bytes value
+  */
+static uint16_t FLASH_OB_GetWRP(void)
+{
+  /* Return the FLASH write protection Register value */
+  return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
+}
+
+/**
+  * @brief  Returns the FLASH Read Protection level.
+  * @param  None
+  * @retval FlagStatus FLASH ReadOut Protection Status:
+  *           - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
+  *           - RESET, when OB_RDP_Level_0 is set
+  */
+static FlagStatus FLASH_OB_GetRDP(void)
+{
+  FlagStatus readstatus = RESET;
+
+  if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_LEVEL_0))
+  {
+    readstatus = SET;
+  }
+  
+  return readstatus;
+}
+
+/**
+  * @brief  Returns the FLASH BOR level.
+  * @param  None
+  * @retval uint8_t The FLASH BOR level:
+  *           - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
+  *           - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
+  *           - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
+  *           - OB_BOR_OFF   : Supply voltage ranges from 1.62 to 2.1 V  
+  */
+static uint8_t FLASH_OB_GetBOR(void)
+{
+  /* Return the FLASH BOR level */
+  return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
+}
+
+/**
+  * @}
+  */
+  
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_flash_ex.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,736 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_flash_ex.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of FLASH HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_FLASH_EX_H
+#define __STM32F4xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASHEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/**
+  * @brief  FLASH Erase structure definition
+  */
+typedef struct
+{
+  uint32_t TypeErase;   /*!< Mass erase or sector Erase.
+                             This parameter can be a value of @ref FLASHEx_Type_Erase */
+
+  uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
+                             This parameter must be a value of @ref FLASHEx_Banks */        
+
+  uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled
+                             This parameter must be a value of @ref FLASHEx_Sectors */        
+  
+  uint32_t NbSectors;   /*!< Number of sectors to be erased.
+                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/           
+                                                          
+  uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
+                             This parameter must be a value of @ref FLASHEx_Voltage_Range */        
+  
+} FLASH_EraseInitTypeDef;
+
+/**
+  * @brief  FLASH Option Bytes Program structure definition
+  */
+typedef struct
+{
+  uint32_t OptionType;   /*!< Option byte to be configured.
+                              This parameter can be a value of @ref FLASHEx_Option_Type */
+
+  uint32_t WRPState;     /*!< Write protection activation or deactivation.
+                              This parameter can be a value of @ref FLASHEx_WRP_State */
+
+  uint32_t WRPSector;         /*!< Specifies the sector(s) to be write protected.
+                              The value of this parameter depend on device used within the same series */
+
+  uint32_t Banks;        /*!< Select banks for WRP activation/deactivation of all sectors.
+                              This parameter must be a value of @ref FLASHEx_Banks */        
+
+  uint32_t RDPLevel;     /*!< Set the read protection level.
+                              This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
+
+  uint32_t BORLevel;     /*!< Set the BOR Level.
+                              This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
+
+  uint8_t  USERConfig;   /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */
+
+} FLASH_OBProgramInitTypeDef;
+
+/**
+  * @brief  FLASH Advanced Option Bytes Program structure definition
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
+typedef struct
+{
+  uint32_t OptionType;     /*!< Option byte to be configured for extension.
+                                This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */
+
+  uint32_t PCROPState;     /*!< PCROP activation or deactivation.
+                                This parameter can be a value of @ref FLASHEx_PCROP_State */
+
+#if defined (STM32F401xC) || defined (STM32F401xE)
+  uint16_t Sectors;        /*!< specifies the sector(s) set for PCROP.
+                                This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+#endif /* STM32F401xC || STM32F401xE */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+  uint32_t Banks;          /*!< Select banks for PCROP activation/deactivation of all sectors.
+                                This parameter must be a value of @ref FLASHEx_Banks */
+                                
+  uint16_t SectorsBank1;   /*!< Specifies the sector(s) set for PCROP for Bank1.
+                                This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+
+  uint16_t SectorsBank2;   /*!< Specifies the sector(s) set for PCROP for Bank2.
+                                This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+  
+  uint8_t BootConfig;      /*!< Specifies Option bytes for boot config.
+                                This parameter can be a value of @ref FLASHEx_Dual_Boot */
+  
+#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+} FLASH_AdvOBProgramInitTypeDef;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+  * @{
+  */
+
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
+  * @{
+  */ 
+#define TYPEERASE_SECTORS         ((uint32_t)0x00)  /*!< Sectors erase only          */
+#define TYPEERASE_MASSERASE       ((uint32_t)0x01)  /*!< Flash Mass erase activation */
+
+#define IS_TYPEERASE(VALUE)(((VALUE) == TYPEERASE_SECTORS) || \
+                               ((VALUE) == TYPEERASE_MASSERASE))  
+
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
+  * @{
+  */ 
+#define VOLTAGE_RANGE_1        ((uint32_t)0x00)  /*!< Device operating range: 1.8V to 2.1V                */
+#define VOLTAGE_RANGE_2        ((uint32_t)0x01)  /*!< Device operating range: 2.1V to 2.7V                */
+#define VOLTAGE_RANGE_3        ((uint32_t)0x02)  /*!< Device operating range: 2.7V to 3.6V                */
+#define VOLTAGE_RANGE_4        ((uint32_t)0x03)  /*!< Device operating range: 2.7V to 3.6V + External Vpp */
+
+#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VOLTAGE_RANGE_1) || \
+                               ((RANGE) == VOLTAGE_RANGE_2) || \
+                               ((RANGE) == VOLTAGE_RANGE_3) || \
+                               ((RANGE) == VOLTAGE_RANGE_4))  
+                              
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_WRP_State FLASH WRP State
+  * @{
+  */ 
+#define WRPSTATE_DISABLE       ((uint32_t)0x00)  /*!< Disable the write protection of the desired bank 1 sectors */
+#define WRPSTATE_ENABLE        ((uint32_t)0x01)  /*!< Enable the write protection of the desired bank 1 sectors  */
+
+#define IS_WRPSTATE(VALUE)(((VALUE) == WRPSTATE_DISABLE) || \
+                           ((VALUE) == WRPSTATE_ENABLE))  
+
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_Option_Type FLASH Option Type
+  * @{
+  */ 
+#define OPTIONBYTE_WRP        ((uint32_t)0x01)  /*!< WRP option byte configuration  */
+#define OPTIONBYTE_RDP        ((uint32_t)0x02)  /*!< RDP option byte configuration  */
+#define OPTIONBYTE_USER       ((uint32_t)0x04)  /*!< USER option byte configuration */
+#define OPTIONBYTE_BOR        ((uint32_t)0x08)  /*!< BOR option byte configuration  */
+
+#define IS_OPTIONBYTE(VALUE)(((VALUE) < (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
+
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
+  * @{
+  */
+#define OB_RDP_LEVEL_0   ((uint8_t)0xAA)
+#define OB_RDP_LEVEL_1   ((uint8_t)0x55)
+/*#define OB_RDP_LEVEL_2   ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 
+                                                  it s no more possible to go back to level 1 or 0 */
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0)   ||\
+                                ((LEVEL) == OB_RDP_LEVEL_1))/*||\
+                                ((LEVEL) == OB_RDP_LEVEL_2))*/
+/**
+  * @}
+  */ 
+  
+/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
+  * @{
+  */ 
+#define OB_IWDG_SW                     ((uint8_t)0x20)  /*!< Software IWDG selected */
+#define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+/**
+  * @}
+  */ 
+  
+/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
+  * @{
+  */ 
+#define OB_STOP_NO_RST                 ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP    */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
+  * @{
+  */ 
+#define OB_STDBY_NO_RST                ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY    */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+/**
+  * @}
+  */    
+
+/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
+  * @{
+  */  
+#define OB_BOR_LEVEL3          ((uint8_t)0x00)  /*!< Supply voltage ranges from 2.70 to 3.60 V */
+#define OB_BOR_LEVEL2          ((uint8_t)0x04)  /*!< Supply voltage ranges from 2.40 to 2.70 V */
+#define OB_BOR_LEVEL1          ((uint8_t)0x08)  /*!< Supply voltage ranges from 2.10 to 2.40 V */
+#define OB_BOR_OFF             ((uint8_t)0x0C)  /*!< Supply voltage ranges from 1.62 to 2.10 V */
+#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
+                                ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
+/**
+  * @}
+  */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
+/** @defgroup FLASHEx_PCROP_State FLASH PCROP State
+  * @{
+  */ 
+#define PCROPSTATE_DISABLE       ((uint32_t)0x00)  /*!< Disable PCROP */
+#define PCROPSTATE_ENABLE        ((uint32_t)0x01)  /*!< Enable PCROP  */
+  
+#define IS_PCROPSTATE(VALUE)(((VALUE) == PCROPSTATE_DISABLE) || \
+                             ((VALUE) == PCROPSTATE_ENABLE))  
+  
+/**
+  * @}
+  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */
+
+/** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type
+  * @{
+  */ 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#define OBEX_PCROP        ((uint32_t)0x01)  /*!< PCROP option byte configuration      */
+#define OBEX_BOOTCONFIG   ((uint32_t)0x02)  /*!< BOOTConfig option byte configuration */
+
+#define IS_OBEX(VALUE)(((VALUE) == OBEX_PCROP) || \
+                       ((VALUE) == OBEX_BOOTCONFIG))  
+  
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE)
+#define OBEX_PCROP        ((uint32_t)0x01)  /*!<PCROP option byte configuration */
+
+#define IS_OBEX(VALUE)(((VALUE) == OBEX_PCROP))  
+  
+#endif /* STM32F401xC || STM32F401xE */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Latency FLASH Latency
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
+#define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
+#define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
+#define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
+#define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
+#define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
+#define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
+#define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
+#define FLASH_LATENCY_8                FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycles    */
+#define FLASH_LATENCY_9                FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycles     */
+#define FLASH_LATENCY_10               FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */
+#define FLASH_LATENCY_11               FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */
+#define FLASH_LATENCY_12               FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */
+#define FLASH_LATENCY_13               FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */
+#define FLASH_LATENCY_14               FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */
+#define FLASH_LATENCY_15               FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */
+
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \
+                                   ((LATENCY) == FLASH_LATENCY_1)  || \
+                                   ((LATENCY) == FLASH_LATENCY_2)  || \
+                                   ((LATENCY) == FLASH_LATENCY_3)  || \
+                                   ((LATENCY) == FLASH_LATENCY_4)  || \
+                                   ((LATENCY) == FLASH_LATENCY_5)  || \
+                                   ((LATENCY) == FLASH_LATENCY_6)  || \
+                                   ((LATENCY) == FLASH_LATENCY_7)  || \
+                                   ((LATENCY) == FLASH_LATENCY_8)  || \
+                                   ((LATENCY) == FLASH_LATENCY_9)  || \
+                                   ((LATENCY) == FLASH_LATENCY_10) || \
+                                   ((LATENCY) == FLASH_LATENCY_11) || \
+                                   ((LATENCY) == FLASH_LATENCY_12) || \
+                                   ((LATENCY) == FLASH_LATENCY_13) || \
+                                   ((LATENCY) == FLASH_LATENCY_14) || \
+                                   ((LATENCY) == FLASH_LATENCY_15))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
+#define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
+#define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
+#define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
+#define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
+#define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
+#define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
+#define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
+#define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
+
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \
+                                   ((LATENCY) == FLASH_LATENCY_1)  || \
+                                   ((LATENCY) == FLASH_LATENCY_2)  || \
+                                   ((LATENCY) == FLASH_LATENCY_3)  || \
+                                   ((LATENCY) == FLASH_LATENCY_4)  || \
+                                   ((LATENCY) == FLASH_LATENCY_5)  || \
+                                   ((LATENCY) == FLASH_LATENCY_6)  || \
+                                   ((LATENCY) == FLASH_LATENCY_7))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
+
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup FLASHEx_Banks FLASH Banks
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define FLASH_BANK_1     ((uint32_t)1) /*!< Bank 1   */
+#define FLASH_BANK_2     ((uint32_t)2) /*!< Bank 2   */
+#define FLASH_BANK_BOTH  ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
+
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)  || \
+                             ((BANK) == FLASH_BANK_2)  || \
+                             ((BANK) == FLASH_BANK_BOTH))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
+#define FLASH_BANK_1     ((uint32_t)1) /*!< Bank 1   */
+
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
+/**
+  * @}
+  */ 
+    
+/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define FLASH_MER_BIT     (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits here to clear */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
+#define FLASH_MER_BIT     (FLASH_CR_MER) /*!< only 1 MER Bit */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASHEx_Sectors FLASH Sectors
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define FLASH_SECTOR_0     ((uint32_t)0)  /*!< Sector Number 0   */
+#define FLASH_SECTOR_1     ((uint32_t)1)  /*!< Sector Number 1   */
+#define FLASH_SECTOR_2     ((uint32_t)2)  /*!< Sector Number 2   */
+#define FLASH_SECTOR_3     ((uint32_t)3)  /*!< Sector Number 3   */
+#define FLASH_SECTOR_4     ((uint32_t)4)  /*!< Sector Number 4   */
+#define FLASH_SECTOR_5     ((uint32_t)5)  /*!< Sector Number 5   */
+#define FLASH_SECTOR_6     ((uint32_t)6)  /*!< Sector Number 6   */
+#define FLASH_SECTOR_7     ((uint32_t)7)  /*!< Sector Number 7   */
+#define FLASH_SECTOR_8     ((uint32_t)8)  /*!< Sector Number 8   */
+#define FLASH_SECTOR_9     ((uint32_t)9)  /*!< Sector Number 9   */
+#define FLASH_SECTOR_10    ((uint32_t)10) /*!< Sector Number 10  */
+#define FLASH_SECTOR_11    ((uint32_t)11) /*!< Sector Number 11  */
+#define FLASH_SECTOR_12    ((uint32_t)12) /*!< Sector Number 12  */
+#define FLASH_SECTOR_13    ((uint32_t)13) /*!< Sector Number 13  */
+#define FLASH_SECTOR_14    ((uint32_t)14) /*!< Sector Number 14  */
+#define FLASH_SECTOR_15    ((uint32_t)15) /*!< Sector Number 15  */
+#define FLASH_SECTOR_16    ((uint32_t)16) /*!< Sector Number 16  */
+#define FLASH_SECTOR_17    ((uint32_t)17) /*!< Sector Number 17  */
+#define FLASH_SECTOR_18    ((uint32_t)18) /*!< Sector Number 18  */
+#define FLASH_SECTOR_19    ((uint32_t)19) /*!< Sector Number 19  */
+#define FLASH_SECTOR_20    ((uint32_t)20) /*!< Sector Number 20  */
+#define FLASH_SECTOR_21    ((uint32_t)21) /*!< Sector Number 21  */
+#define FLASH_SECTOR_22    ((uint32_t)22) /*!< Sector Number 22  */
+#define FLASH_SECTOR_23    ((uint32_t)23) /*!< Sector Number 23  */
+
+#define FLASH_SECTOR_TOTAL  24
+
+#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_12)  || ((SECTOR) == FLASH_SECTOR_13)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_14)  || ((SECTOR) == FLASH_SECTOR_15)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_16)  || ((SECTOR) == FLASH_SECTOR_17)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_18)  || ((SECTOR) == FLASH_SECTOR_19)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_20)  || ((SECTOR) == FLASH_SECTOR_21)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_22)  || ((SECTOR) == FLASH_SECTOR_23))
+
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x081FFFFF)) ||\
+                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))  
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define FLASH_SECTOR_0     ((uint32_t)0)  /*!< Sector Number 0   */
+#define FLASH_SECTOR_1     ((uint32_t)1)  /*!< Sector Number 1   */
+#define FLASH_SECTOR_2     ((uint32_t)2)  /*!< Sector Number 2   */
+#define FLASH_SECTOR_3     ((uint32_t)3)  /*!< Sector Number 3   */
+#define FLASH_SECTOR_4     ((uint32_t)4)  /*!< Sector Number 4   */
+#define FLASH_SECTOR_5     ((uint32_t)5)  /*!< Sector Number 5   */
+#define FLASH_SECTOR_6     ((uint32_t)6)  /*!< Sector Number 6   */
+#define FLASH_SECTOR_7     ((uint32_t)7)  /*!< Sector Number 7   */
+#define FLASH_SECTOR_8     ((uint32_t)8)  /*!< Sector Number 8   */
+#define FLASH_SECTOR_9     ((uint32_t)9)  /*!< Sector Number 9   */
+#define FLASH_SECTOR_10    ((uint32_t)10) /*!< Sector Number 10  */
+#define FLASH_SECTOR_11    ((uint32_t)11) /*!< Sector Number 11  */
+
+#define FLASH_SECTOR_TOTAL  12
+
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11))
+
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\
+                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F401xC)
+#define FLASH_SECTOR_0     ((uint32_t)0) /*!< Sector Number 0   */
+#define FLASH_SECTOR_1     ((uint32_t)1) /*!< Sector Number 1   */
+#define FLASH_SECTOR_2     ((uint32_t)2) /*!< Sector Number 2   */
+#define FLASH_SECTOR_3     ((uint32_t)3) /*!< Sector Number 3   */
+#define FLASH_SECTOR_4     ((uint32_t)4) /*!< Sector Number 4   */
+#define FLASH_SECTOR_5     ((uint32_t)5) /*!< Sector Number 5   */
+
+#define FLASH_SECTOR_TOTAL  6
+
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5))
+
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0803FFFF)) ||\
+                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
+#endif /* STM32F401xC */
+
+#if defined(STM32F401xE)
+#define FLASH_SECTOR_0     ((uint32_t)0) /*!< Sector Number 0   */
+#define FLASH_SECTOR_1     ((uint32_t)1) /*!< Sector Number 1   */
+#define FLASH_SECTOR_2     ((uint32_t)2) /*!< Sector Number 2   */
+#define FLASH_SECTOR_3     ((uint32_t)3) /*!< Sector Number 3   */
+#define FLASH_SECTOR_4     ((uint32_t)4) /*!< Sector Number 4   */
+#define FLASH_SECTOR_5     ((uint32_t)5) /*!< Sector Number 5   */
+#define FLASH_SECTOR_6     ((uint32_t)6) /*!< Sector Number 6   */
+#define FLASH_SECTOR_7     ((uint32_t)7) /*!< Sector Number 7   */
+
+#define FLASH_SECTOR_TOTAL  8
+
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7))
+
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF)) ||\
+                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
+#endif /* STM32F401xE */
+
+#define IS_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 
+#define OB_WRP_SECTOR_0       ((uint32_t)0x00000001) /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       ((uint32_t)0x00000002) /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_2       ((uint32_t)0x00000004) /*!< Write protection of Sector2     */
+#define OB_WRP_SECTOR_3       ((uint32_t)0x00000008) /*!< Write protection of Sector3     */
+#define OB_WRP_SECTOR_4       ((uint32_t)0x00000010) /*!< Write protection of Sector4     */
+#define OB_WRP_SECTOR_5       ((uint32_t)0x00000020) /*!< Write protection of Sector5     */
+#define OB_WRP_SECTOR_6       ((uint32_t)0x00000040) /*!< Write protection of Sector6     */
+#define OB_WRP_SECTOR_7       ((uint32_t)0x00000080) /*!< Write protection of Sector7     */
+#define OB_WRP_SECTOR_8       ((uint32_t)0x00000100) /*!< Write protection of Sector8     */
+#define OB_WRP_SECTOR_9       ((uint32_t)0x00000200) /*!< Write protection of Sector9     */
+#define OB_WRP_SECTOR_10      ((uint32_t)0x00000400) /*!< Write protection of Sector10    */
+#define OB_WRP_SECTOR_11      ((uint32_t)0x00000800) /*!< Write protection of Sector11    */
+#define OB_WRP_SECTOR_12      ((uint32_t)0x00000001 << 12) /*!< Write protection of Sector12    */
+#define OB_WRP_SECTOR_13      ((uint32_t)0x00000002 << 12) /*!< Write protection of Sector13    */
+#define OB_WRP_SECTOR_14      ((uint32_t)0x00000004 << 12) /*!< Write protection of Sector14    */
+#define OB_WRP_SECTOR_15      ((uint32_t)0x00000008 << 12) /*!< Write protection of Sector15    */
+#define OB_WRP_SECTOR_16      ((uint32_t)0x00000010 << 12) /*!< Write protection of Sector16    */
+#define OB_WRP_SECTOR_17      ((uint32_t)0x00000020 << 12) /*!< Write protection of Sector17    */
+#define OB_WRP_SECTOR_18      ((uint32_t)0x00000040 << 12) /*!< Write protection of Sector18    */
+#define OB_WRP_SECTOR_19      ((uint32_t)0x00000080 << 12) /*!< Write protection of Sector19    */
+#define OB_WRP_SECTOR_20      ((uint32_t)0x00000100 << 12) /*!< Write protection of Sector20    */
+#define OB_WRP_SECTOR_21      ((uint32_t)0x00000200 << 12) /*!< Write protection of Sector21    */
+#define OB_WRP_SECTOR_22      ((uint32_t)0x00000400 << 12) /*!< Write protection of Sector22    */
+#define OB_WRP_SECTOR_23      ((uint32_t)0x00000800 << 12) /*!< Write protection of Sector23    */
+#define OB_WRP_SECTOR_All     ((uint32_t)0x00000FFF << 12) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFF000000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define OB_WRP_SECTOR_0       ((uint32_t)0x00000001) /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       ((uint32_t)0x00000002) /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_2       ((uint32_t)0x00000004) /*!< Write protection of Sector2     */
+#define OB_WRP_SECTOR_3       ((uint32_t)0x00000008) /*!< Write protection of Sector3     */
+#define OB_WRP_SECTOR_4       ((uint32_t)0x00000010) /*!< Write protection of Sector4     */
+#define OB_WRP_SECTOR_5       ((uint32_t)0x00000020) /*!< Write protection of Sector5     */
+#define OB_WRP_SECTOR_6       ((uint32_t)0x00000040) /*!< Write protection of Sector6     */
+#define OB_WRP_SECTOR_7       ((uint32_t)0x00000080) /*!< Write protection of Sector7     */
+#define OB_WRP_SECTOR_8       ((uint32_t)0x00000100) /*!< Write protection of Sector8     */
+#define OB_WRP_SECTOR_9       ((uint32_t)0x00000200) /*!< Write protection of Sector9     */
+#define OB_WRP_SECTOR_10      ((uint32_t)0x00000400) /*!< Write protection of Sector10    */
+#define OB_WRP_SECTOR_11      ((uint32_t)0x00000800) /*!< Write protection of Sector11    */
+#define OB_WRP_SECTOR_All     ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F401xC)
+#define OB_WRP_SECTOR_0       ((uint32_t)0x00000001) /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       ((uint32_t)0x00000002) /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_2       ((uint32_t)0x00000004) /*!< Write protection of Sector2     */
+#define OB_WRP_SECTOR_3       ((uint32_t)0x00000008) /*!< Write protection of Sector3     */
+#define OB_WRP_SECTOR_4       ((uint32_t)0x00000010) /*!< Write protection of Sector4     */
+#define OB_WRP_SECTOR_5       ((uint32_t)0x00000020) /*!< Write protection of Sector5     */
+#define OB_WRP_SECTOR_All     ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F401xC */
+
+#if defined(STM32F401xE)
+#define OB_WRP_SECTOR_0       ((uint32_t)0x00000001) /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       ((uint32_t)0x00000002) /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_2       ((uint32_t)0x00000004) /*!< Write protection of Sector2     */
+#define OB_WRP_SECTOR_3       ((uint32_t)0x00000008) /*!< Write protection of Sector3     */
+#define OB_WRP_SECTOR_4       ((uint32_t)0x00000010) /*!< Write protection of Sector4     */
+#define OB_WRP_SECTOR_5       ((uint32_t)0x00000020) /*!< Write protection of Sector5     */
+#define OB_WRP_SECTOR_6       ((uint32_t)0x00000040) /*!< Write protection of Sector6     */
+#define OB_WRP_SECTOR_7       ((uint32_t)0x00000080) /*!< Write protection of Sector7     */
+#define OB_WRP_SECTOR_All     ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F401xE */
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC ReadWrite Protection
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 
+#define OB_PCROP_SECTOR_0        ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0      */
+#define OB_PCROP_SECTOR_1        ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1      */
+#define OB_PCROP_SECTOR_2        ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2      */
+#define OB_PCROP_SECTOR_3        ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3      */
+#define OB_PCROP_SECTOR_4        ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4      */
+#define OB_PCROP_SECTOR_5        ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5      */
+#define OB_PCROP_SECTOR_6        ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6      */
+#define OB_PCROP_SECTOR_7        ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7      */
+#define OB_PCROP_SECTOR_8        ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8      */
+#define OB_PCROP_SECTOR_9        ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9      */
+#define OB_PCROP_SECTOR_10       ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10     */
+#define OB_PCROP_SECTOR_11       ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11     */
+#define OB_PCROP_SECTOR_12       ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12     */
+#define OB_PCROP_SECTOR_13       ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13     */
+#define OB_PCROP_SECTOR_14       ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14     */
+#define OB_PCROP_SECTOR_15       ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15     */
+#define OB_PCROP_SECTOR_16       ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16     */
+#define OB_PCROP_SECTOR_17       ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17     */
+#define OB_PCROP_SECTOR_18       ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18     */
+#define OB_PCROP_SECTOR_19       ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19     */
+#define OB_PCROP_SECTOR_20       ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20     */
+#define OB_PCROP_SECTOR_21       ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21     */
+#define OB_PCROP_SECTOR_22       ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22     */
+#define OB_PCROP_SECTOR_23       ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23     */
+#define OB_PCROP_SECTOR_All      ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors  */
+
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F401xC)
+#define OB_PCROP_SECTOR_0        ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0      */
+#define OB_PCROP_SECTOR_1        ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1      */
+#define OB_PCROP_SECTOR_2        ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2      */
+#define OB_PCROP_SECTOR_3        ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3      */
+#define OB_PCROP_SECTOR_4        ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4      */
+#define OB_PCROP_SECTOR_5        ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5      */
+#define OB_PCROP_SECTOR_All      ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors  */
+
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F401xC */
+
+#if defined(STM32F401xE)
+#define OB_PCROP_SECTOR_0        ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0      */
+#define OB_PCROP_SECTOR_1        ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1      */
+#define OB_PCROP_SECTOR_2        ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2      */
+#define OB_PCROP_SECTOR_3        ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3      */
+#define OB_PCROP_SECTOR_4        ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4      */
+#define OB_PCROP_SECTOR_5        ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5      */
+#define OB_PCROP_SECTOR_6        ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6      */
+#define OB_PCROP_SECTOR_7        ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7      */
+#define OB_PCROP_SECTOR_All      ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors  */
+
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F401xE */
+
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_Dual_Boot FLASH Dual Boot
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 
+#define OB_DUAL_BOOT_ENABLE   ((uint8_t)0x10) /*!< Dual Bank Boot Enable                             */
+#define OB_DUAL_BOOT_DISABLE  ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
+#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+/**
+  * @}
+  */
+
+/** @defgroup  FLASHEx_Selection_Protection_Mode FLASH Selection Protection Mode
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
+#define OB_PCROP_DESELECTED     ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
+#define OB_PCROP_SELECTED       ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i   */
+#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */
+/**
+  * @}
+  */
+  
+/** 
+  * @brief   OPTCR1 register byte 2 (Bits[23:16]) base address  
+  */ 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)  
+#define OPTCR1_BYTE2_ADDRESS         ((uint32_t)0x40023C1A)
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Extension Program operation functions  *************************************/
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) 
+HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
+void              HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
+HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
+HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+uint16_t          HAL_FLASHEx_OB_GetBank2WRP(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,535 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_gpio.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   GPIO HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### GPIO Peripheral features #####
+  ==============================================================================
+  [..] 
+    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually 
+        configured by software in several modes:
+        (++) Input mode 
+        (++) Analog mode
+        (++) Output mode
+        (++) Alternate function mode
+        (++) External interrupt/event lines
+
+    (+) During and just after reset, the alternate functions and external interrupt  
+        lines are not active and the I/O ports are configured in input floating mode.
+     
+    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be 
+        activated or not.
+
+    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+        type and the IO speed can be selected depending on the VDD value.
+
+    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a 
+        multiplexer that allows only one peripheral alternate function (AF) connected 
+       to an IO pin at a time. In this way, there can be no conflict between peripherals 
+       sharing the same IO pin. 
+
+    (+) All ports have external interrupt/event capability. To use external interrupt 
+        lines, the port must be configured in input mode. All available GPIO pins are 
+        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+    (+) The external interrupt/event controller consists of up to 23 edge detectors 
+        (16 lines are connected to GPIO) for generating event/interrupt requests (each 
+        input line can be independently configured to select the type (interrupt or event) 
+        and the corresponding trigger event (rising or falling or both). Each line can 
+        also be masked independently. 
+
+                     ##### How to use this driver #####
+  ==============================================================================  
+  [..]
+    (#) Enable the GPIO AHB clock using the following function: __GPIOx_CLK_ENABLE(). 
+
+    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef 
+             structure.
+        (++) In case of Output or alternate function mode selection: the speed is 
+             configured through "Speed" member from GPIO_InitTypeDef structure.
+        (++) In alternate mode is selection, the alternate function connected to the IO
+             is configured through "Alternate" member from GPIO_InitTypeDef structure.
+        (++) Analog mode is required when a pin is to be used as ADC channel 
+             or DAC output.
+        (++) In case of external interrupt/event selection the "Mode" member from 
+             GPIO_InitTypeDef structure select the type (interrupt or event) and 
+             the corresponding trigger event (rising or falling or both).
+
+    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority 
+        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+        HAL_NVIC_EnableIRQ().
+         
+    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+            
+    (#) To set/reset the level of a pin configured in output mode use 
+        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+                 
+    (#) During and just after reset, the alternate functions are not 
+        active and the GPIO pins are configured in input floating mode (except JTAG
+        pins).
+  
+    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose 
+        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has 
+        priority over the GPIO function.
+  
+    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as 
+        general purpose PH0 and PH1, respectively, when the HSE oscillator is off. 
+        The HSE has priority over the GPIO function.
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIO
+  * @brief GPIO HAL module driver
+  * @{
+  */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+#define __HAL_GET_GPIO_SOURCE(__GPIOx__) \
+(((uint32_t)(__GPIOx__) == ((uint32_t)GPIOA_BASE))? (uint32_t)0 :\
+ ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0400)))? (uint32_t)1 :\
+ ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0800)))? (uint32_t)2 :\
+ ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0C00)))? (uint32_t)3 :\
+ ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1000)))? (uint32_t)4 :\
+ ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1400)))? (uint32_t)5 :\
+ ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1800)))? (uint32_t)6 :\
+ ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1C00)))? (uint32_t)7 :\
+ ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x2000)))? (uint32_t)8 :\
+ ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x2400)))? (uint32_t)9 : (uint32_t)10)
+
+#define GPIO_MODE             ((uint32_t)0x00000003)
+#define EXTI_MODE             ((uint32_t)0x10000000)
+#define GPIO_MODE_IT          ((uint32_t)0x00010000)
+#define GPIO_MODE_EVT         ((uint32_t)0x00020000)
+#define RISING_EDGE           ((uint32_t)0x00100000)
+#define FALLING_EDGE          ((uint32_t)0x00200000)
+#define GPIO_OUTPUT_TYPE      ((uint32_t)0x00000010)
+
+#define GPIO_NUMBER           ((uint32_t)16)
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup GPIO_Private_Functions
+  * @{
+  */
+
+/** @defgroup GPIO_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+  uint32_t position;
+  uint32_t ioposition = 0x00;
+  uint32_t iocurrent = 0x00;
+  uint32_t temp = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+  /* Configure the port pins */
+  for(position = 0; position < GPIO_NUMBER; position++)
+  {
+    /* Get the IO position */
+    ioposition = ((uint32_t)0x01) << position;
+    /* Get the current IO position */
+    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
+
+    if(iocurrent == ioposition)
+    {
+      /*--------------------- GPIO Mode Configuration ------------------------*/
+      /* In case of Alternate function mode selection */
+      if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+      {
+        /* Check the Alternate function parameter */
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+        /* Configure Alternate function mapped with the current IO */
+        temp = GPIOx->AFR[position >> 3];
+        temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
+        GPIOx->AFR[position >> 3] = temp;
+      }
+
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+      temp = GPIOx->MODER;
+      temp &= ~(GPIO_MODER_MODER0 << (position * 2));
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+      GPIOx->MODER = temp;
+
+      /* In case of Output or Alternate function mode selection */
+      if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+         (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+      {
+        /* Check the Speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        /* Configure the IO Speed */
+        temp = GPIOx->OSPEEDR; 
+        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+        temp |= (GPIO_Init->Speed << (position * 2));
+        GPIOx->OSPEEDR = temp;
+
+        /* Configure the IO Output Type */
+        temp = GPIOx->OTYPER;
+        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
+        GPIOx->OTYPER = temp;
+      }
+
+      /* Activate the Pull-up or Pull down resistor for the current IO */
+      temp = GPIOx->PUPDR;
+      temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+      temp |= ((GPIO_Init->Pull) << (position * 2));
+      GPIOx->PUPDR = temp;
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+      {
+        /* Enable SYSCFG Clock */
+        __SYSCFG_CLK_ENABLE();
+
+        temp = SYSCFG->EXTICR[position >> 2];
+        temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
+        temp |= ((uint32_t)(__HAL_GET_GPIO_SOURCE(GPIOx)) << (4 * (position & 0x03)));
+        SYSCFG->EXTICR[position >> 2] = temp;
+
+        /* Clear EXTI line configuration */
+        temp = EXTI->IMR;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->IMR = temp;
+
+        temp = EXTI->EMR;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->EMR = temp;
+
+        /* Clear Rising Falling edge configuration */
+        temp = EXTI->RTSR;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->RTSR = temp;
+
+        temp = EXTI->FTSR;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->FTSR = temp;
+      }
+    }
+  }
+}
+
+/**
+  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
+{
+  uint32_t position;
+  uint32_t ioposition = 0x00;
+  uint32_t iocurrent = 0x00;
+  uint32_t tmp = 0x00;
+
+  /* Configure the port pins */
+  for(position = 0; position < GPIO_NUMBER; position++)
+  {
+    /* Get the IO position */
+    ioposition = ((uint32_t)0x01) << position;
+    /* Get the current IO position */
+    iocurrent = (GPIO_Pin) & ioposition;
+
+    if(iocurrent == ioposition)
+    {
+      /*------------------------- GPIO Mode Configuration --------------------*/
+      /* Configure IO Direction in Input Floting Mode */
+      GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
+
+      /* Configure the default Alternate Function in current IO */
+      GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+
+      /* Configure the default value for IO Speed */
+      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+
+      /* Configure the default value IO Output Type */
+      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;
+
+      /* Deactivate the Pull-up oand Pull-down resistor for the current IO */
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+
+      /*------------------------- EXTI Mode Configuration --------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
+      SYSCFG->EXTICR[position >> 2] &= ~tmp;
+
+      /* Clear EXTI line configuration */
+      EXTI->IMR &= ~((uint32_t)iocurrent);
+      EXTI->EMR &= ~((uint32_t)iocurrent);
+
+      /* Clear Rising Falling edge configuration */
+      EXTI->RTSR &= ~((uint32_t)iocurrent);
+      EXTI->FTSR &= ~((uint32_t)iocurrent);
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Group2 IO operation functions 
+ *  @brief   GPIO Read and Write
+ *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+  * @param  GPIO_Pin: specifies the port bit to read.
+  *         This parameter can be GPIO_PIN_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  GPIO_PinState bitstatus;
+
+  /* Check the parameters */
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+  if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
+  {
+    bitstatus = GPIO_PIN_SET;
+  }
+  else
+  {
+    bitstatus = GPIO_PIN_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  *
+  * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  *
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @param  PinState: specifies the value to be written to the selected bit.
+  *          This parameter can be one of the GPIO_PinState enum values:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+  /* Check the parameters */
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if(PinState != GPIO_PIN_RESET)
+  {
+    GPIOx->BSRRL = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BSRRH = GPIO_Pin ;
+  }
+}
+
+/**
+  * @brief  Toggles the specified GPIO pins.
+  * @param  GPIOx: Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+  * @param  GPIO_Pin: Specifies the pins to be toggled.
+  * @retval None
+  */
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+  GPIOx->ODR ^= GPIO_Pin;
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified
+  *         until the next reset.
+  * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F4 family
+  * @param  GPIO_Pin: specifies the port bit to be locked.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Apply lock key write sequence */
+  tmp |= GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+  GPIOx->LCKR = GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LCKR;
+
+  if(GPIOx->LCKR & GPIO_LCKR_LCKK)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  This function handles EXTI interrupt request.
+  * @param  GPIO_Pin: Specifies the pins connected EXTI line
+  * @retval None
+  */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+  /* EXTI line interrupt detected */
+  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
+  {
+    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);
+  }
+}
+
+/**
+  * @brief  EXTI line detection callbacks.
+  * @param  GPIO_Pin: Specifies the pins connected EXTI line
+  * @retval None
+  */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_GPIO_EXTI_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,278 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_gpio.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of GPIO HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_GPIO_H
+#define __STM32F4xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief   GPIO Init structure definition  
+  */ 
+typedef struct
+{
+  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
+                           This parameter can be any value of @ref GPIO_pins_define */
+
+  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref GPIO_mode_define */
+
+  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                           This parameter can be a value of @ref GPIO_pull_define */
+
+  uint32_t Speed;     /*!< Specifies the speed for the selected pins.
+                           This parameter can be a value of @ref GPIO_speed_define */
+
+  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins. 
+                            This parameter can be a value of @ref GPIO_Alternat_function_selection */
+}GPIO_InitTypeDef;
+
+/** 
+  * @brief  GPIO Bit SET and Bit RESET enumeration 
+  */
+typedef enum
+{
+  GPIO_PIN_RESET = 0,
+  GPIO_PIN_SET
+}GPIO_PinState;
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+  * @{
+  */
+
+/** @defgroup GPIO_pins_define 
+  * @{
+  */
+#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
+#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
+#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
+#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
+#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
+#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
+#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
+#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
+#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
+#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
+#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
+#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
+#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
+#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
+#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
+#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
+#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint32_t)0x00) == 0x00) && ((PIN) != (uint32_t)0x00))
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_PIN_0)  || \
+                              ((PIN) == GPIO_PIN_1)  || \
+                              ((PIN) == GPIO_PIN_2)  || \
+                              ((PIN) == GPIO_PIN_3)  || \
+                              ((PIN) == GPIO_PIN_4)  || \
+                              ((PIN) == GPIO_PIN_5)  || \
+                              ((PIN) == GPIO_PIN_6)  || \
+                              ((PIN) == GPIO_PIN_7)  || \
+                              ((PIN) == GPIO_PIN_8)  || \
+                              ((PIN) == GPIO_PIN_9)  || \
+                              ((PIN) == GPIO_PIN_10) || \
+                              ((PIN) == GPIO_PIN_11) || \
+                              ((PIN) == GPIO_PIN_12) || \
+                              ((PIN) == GPIO_PIN_13) || \
+                              ((PIN) == GPIO_PIN_14) || \
+                              ((PIN) == GPIO_PIN_15))
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_mode_define
+  * @brief GPIO Configuration Mode 
+  *        Elements values convention: 0xX0yz00YZ
+  *           - X  : GPIO mode or EXTI Mode
+  *           - y  : External IT or Event trigger detection 
+  *           - z  : IO configuration on External IT or Event
+  *           - Y  : Output type (Push Pull or Open Drain)
+  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
+  * @{
+  */ 
+#define  GPIO_MODE_INPUT                        ((uint32_t)0x00000000)   /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                    ((uint32_t)0x00000001)   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                    ((uint32_t)0x00000011)   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                        ((uint32_t)0x00000002)   /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                        ((uint32_t)0x00000012)   /*!< Alternate Function Open Drain Mode    */
+
+#define  GPIO_MODE_ANALOG                       ((uint32_t)0x00000003)   /*!< Analog Mode  */
+    
+#define  GPIO_MODE_IT_RISING                    ((uint32_t)0x10110000)   /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING                   ((uint32_t)0x10210000)   /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING            ((uint32_t)0x10310000)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+ 
+#define  GPIO_MODE_EVT_RISING                   ((uint32_t)0x10120000)   /*!< External Event Mode with Rising edge trigger detection               */
+#define  GPIO_MODE_EVT_FALLING                  ((uint32_t)0x10220000)   /*!< External Event Mode with Falling edge trigger detection              */
+#define  GPIO_MODE_EVT_RISING_FALLING           ((uint32_t)0x10320000)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
+  
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
+                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
+                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
+                            ((MODE) == GPIO_MODE_AF_PP)              ||\
+                            ((MODE) == GPIO_MODE_AF_OD)              ||\
+                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
+                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
+                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
+                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
+                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
+                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+                            ((MODE) == GPIO_MODE_ANALOG))
+
+/**
+  * @}
+  */
+/** @defgroup GPIO_speed_define
+  * @brief GPIO Output Maximum frequency
+  * @{
+  */  
+#define  GPIO_SPEED_LOW         ((uint32_t)0x00000000)  /*!< Low speed     */
+#define  GPIO_SPEED_MEDIUM      ((uint32_t)0x00000001)  /*!< Medium speed  */
+#define  GPIO_SPEED_FAST        ((uint32_t)0x00000002)  /*!< Fast speed    */
+#define  GPIO_SPEED_HIGH        ((uint32_t)0x00000003)  /*!< High speed    */
+
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW)  || ((SPEED) == GPIO_SPEED_MEDIUM) || \
+                              ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH))
+/**
+  * @}
+  */
+
+ /** @defgroup GPIO_pull_define
+   * @brief GPIO Pull-Up or Pull-Down Activation
+   * @{
+   */  
+#define  GPIO_NOPULL        ((uint32_t)0x00000000)   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        ((uint32_t)0x00000001)   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      ((uint32_t)0x00000002)   /*!< Pull-down activation                */
+
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+                            ((PULL) == GPIO_PULLDOWN))
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/* Include GPIO HAL Extension module */
+#include "stm32f4xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/ 
+/* Initialization and de-initialization functions *******************************/
+void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
+
+/* IO operation functions *******************************************************/
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_gpio_ex.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,717 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_gpio_ex.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of GPIO HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_GPIO_EX_H
+#define __STM32F4xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+  * @{
+  */ 
+  
+/** @defgroup GPIO_Alternat_function_selection 
+  * @{
+  */
+  
+/*------------------------- STM32F429xx/STM32F439xx---------------------------*/ 
+#if defined (STM32F429xx) || defined (STM32F439xx)
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
+#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping        */
+#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping        */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */
+#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping    */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping   */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */
+#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LCD-TFT Alternate Function mapping */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0xA)  /* OTG_HS Alternate Function mapping */
+
+/** 
+  * @brief   AF 11 selection  
+  */ 
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_FMC           ((uint8_t)0xC)  /* FMC Alternate Function mapping                      */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0xC)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO          ((uint8_t)0xC)  /* SDIO Alternate Function mapping                     */
+
+/** 
+  * @brief   AF 13 selection  
+  */ 
+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
+
+/** 
+  * @brief   AF 14 selection  
+  */
+#define GPIO_AF14_LTDC          ((uint8_t)0x0E)  /* LCD-TFT Alternate Function mapping */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
+                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
+                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
+                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
+                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
+                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1)      || \
+                          ((AF) == GPIO_AF14_LTDC))
+
+#endif /* STM32F429xx || STM32F439xx */
+/*------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F427xx/STM32F437xx--------------------------------*/
+#if defined (STM32F427xx) || defined (STM32F437xx)
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
+#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping        */
+#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping        */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */
+#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0xA)  /* OTG_HS Alternate Function mapping */
+
+/** 
+  * @brief   AF 11 selection  
+  */ 
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_FMC           ((uint8_t)0xC)  /* FMC Alternate Function mapping                      */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0xC)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO          ((uint8_t)0xC)  /* SDIO Alternate Function mapping                     */
+
+/** 
+  * @brief   AF 13 selection  
+  */ 
+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
+                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
+                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
+                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
+                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
+                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1))
+
+#endif /* STM32F427xx || STM32F437xx */
+/*------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F407xx/STM32F417xx--------------------------------*/
+#if defined (STM32F407xx) || defined (STM32F417xx)
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0xA)  /* OTG_HS Alternate Function mapping */
+
+/** 
+  * @brief   AF 11 selection  
+  */ 
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_FSMC          ((uint8_t)0xC)  /* FSMC Alternate Function mapping                     */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0xC)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO          ((uint8_t)0xC)  /* SDIO Alternate Function mapping                     */
+
+/** 
+  * @brief   AF 13 selection  
+  */ 
+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
+                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
+                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
+                          ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F407xx || STM32F417xx */
+/*------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F405xx/STM32F415xx--------------------------------*/
+#if defined (STM32F405xx) || defined (STM32F415xx)
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext      ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0xA)  /* OTG_HS Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_FSMC          ((uint8_t)0xC)  /* FSMC Alternate Function mapping                     */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0xC)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO          ((uint8_t)0xC)  /* SDIO Alternate Function mapping                     */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
+                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
+                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO)      || \
+                          ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F405xx || STM32F415xx */
+
+/*------------------------------------------------------------------------------------------*/
+
+/*---------------------------------------- STM32F401xx--------------------------------------*/
+#if defined(STM32F401xC) || defined(STM32F401xE) 
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
+#define GPIO_AF5_I2S3ext      ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext      ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping  */
+#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /* I2C3 Alternate Function mapping  */
+
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_SDIO          ((uint8_t)0xC)  /* SDIO Alternate Function mapping  */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF4_I2C1)       || \
+                          ((AF) == GPIO_AF4_I2C2)       || ((AF) == GPIO_AF4_I2C3)       || \
+                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF8_USART6)     || ((AF) == GPIO_AF10_OTG_FS)    || \
+                          ((AF) == GPIO_AF9_I2C2)       || ((AF) == GPIO_AF9_I2C3)       || \
+                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F401xC || STM32F401xE */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1830 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_hash.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   HASH HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the HASH peripheral:
+  *           + Initialization and de-initialization functions
+  *           + HASH/HMAC Processing functions by algorithm using polling mode
+  *           + HASH/HMAC functions by algorithm using interrupt mode
+  *           + HASH/HMAC functions by algorithm using DMA mode
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The HASH HAL driver can be used as follows:
+    (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
+        (##) Enable the HASH interface clock using __HASH_CLK_ENABLE()
+        (##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())
+            (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
+            (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
+            (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
+        (##) In case of using DMA to control data transfer (e.g. HAL_HMAC_SHA1_Start_DMA())
+            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+            (+++) Configure and enable one DMA stream one for managing data transfer from
+                memory to peripheral (input stream). Managing data transfer from
+                peripheral to memory can be performed only using CPU
+            (+++) Associate the initialized DMA handle to the HASH DMA handle
+                using  __HAL_LINKDMA()
+            (+++) Configure the priority and enable the NVIC for the transfer complete
+                interrupt on the DMA Stream using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+    (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
+        (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
+        (##) For HMAC, the encryption key.
+        (##) For HMAC, the key size used for encryption.
+    (#)Three processing functions are available:
+        (##) Polling mode: processing APIs are blocking functions
+             i.e. they process the data and wait till the digest computation is finished
+             e.g. HAL_HASH_SHA1_Start()
+        (##) Interrupt mode: encryption and decryption APIs are not blocking functions
+                i.e. they process the data under interrupt
+                e.g. HAL_HASH_SHA1_Start_IT()
+        (##) DMA mode: processing APIs are not blocking functions and the CPU is
+             not used for data transfer i.e. the data transfer is ensured by DMA
+                e.g. HAL_HASH_SHA1_Start_DMA()
+    (#)When the processing function is called at first time after HAL_HASH_Init()
+       the HASH peripheral is initialized and processes the buffer in input.
+       After that, the digest computation is started.
+       When processing multi-buffer use the accumulate function to write the
+       data in the peripheral without starting the digest computation. In last 
+       buffer use the start function to input the last buffer ans start the digest
+       computation.
+       (##) e.g. HAL_HASH_SHA1_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
+       (##) write (n-1)th data buffer in the peripheral without starting the digest computation
+       (##) HAL_HASH_SHA1_Start() : write (n)th data buffer in the peripheral and start the digest computation
+    (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
+    (#)In case of using DMA, call the DMA start processing e.g. HAL_HASH_SHA1_Start_DMA().
+       After that, call the finish function in order to get the digest value
+       e.g. HAL_HASH_SHA1_Finish()
+    (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HASH 
+  * @brief HASH HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
+static void HASH_DMAError(DMA_HandleTypeDef *hdma);
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
+static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HASH_Private_Functions
+  * @{
+  */
+
+/** @defgroup HASH_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions. 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the HASH according to the specified parameters 
+          in the HASH_InitTypeDef and creates the associated handle.
+      (+) DeInitialize the HASH peripheral.
+      (+) Initialize the HASH MSP.
+      (+) DeInitialize HASH MSP. 
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the HASH according to the specified parameters in the
+            HASH_HandleTypeDef and creates the associated handle.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
+{
+  /* Check the hash handle allocation */
+  if(hhash == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
+   
+  if(hhash->State == HAL_HASH_STATE_RESET)
+  {
+    /* Init the low level hardware */
+    HAL_HASH_MspInit(hhash);
+  }
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Reset HashInCount, HashBuffSize and HashITCounter */
+  hhash->HashInCount = 0;
+  hhash->HashBuffSize = 0;
+  hhash->HashITCounter = 0;
+  
+  /* Set the data type */
+  HASH->CR |= (uint32_t) (hhash->Init.DataType);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+  /* Set the default HASH phase */
+  hhash->Phase = HAL_HASH_PHASE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the HASH peripheral.
+  * @note   This API must be called before starting a new processing. 
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
+{ 
+  /* Check the HASH handle allocation */
+  if(hhash == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Set the default HASH phase */
+  hhash->Phase = HAL_HASH_PHASE_READY;
+  
+  /* Reset HashInCount, HashBuffSize and HashITCounter */
+  hhash->HashInCount = 0;
+  hhash->HashBuffSize = 0;
+  hhash->HashITCounter = 0;
+  
+  /* DeInit the low level hardware */
+  HAL_HASH_MspDeInit(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_RESET;  
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhash);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the HASH MSP.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @retval None
+  */
+__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_HASH_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes HASH MSP.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @retval None
+  */
+__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_HASH_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input data transfer complete callback.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @retval None
+  */
+ __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_HASH_InCpltCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Data transfer Error callback.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @retval None
+  */
+ __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_HASH_ErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Digest computation complete callback. It is used only with interrupt.
+  * @note   This callback is not relevant with DMA.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @retval None
+  */
+ __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_HASH_DgstCpltCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Group2 HASH processing functions using polling mode 
+ *  @brief   processing functions using polling mode 
+ *
+@verbatim   
+ ===============================================================================
+              ##### HASH processing using polling mode functions#####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in polling mode
+          the hash value using one of the following algorithms:
+      (+) MD5
+      (+) SHA1
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
+            The digest is available in pOutBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is multiple of 64 bytes, appending the input buffer is possible.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware
+  *          and appending the input buffer is no more possible.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
+  * @param  Timeout: Timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_AlgoSelection_MD5 | HASH_CR_INIT;
+  }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(pInBuffer, Size);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+  
+  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Read the message digest */
+  HASH_GetDigest(pOutBuffer, 16);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+   
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is multiple of 64 bytes, appending the input buffer is possible.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware
+  *          and appending the input buffer is no more possible.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_AlgoSelection_MD5 | HASH_CR_INIT;
+  }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(pInBuffer, Size);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
+            The digest is available in pOutBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).  
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+  * @param  Timeout: Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_AlgoSelection_SHA1 | HASH_CR_INIT;
+  }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(pInBuffer, Size);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get timeout */
+    timeout = HAL_GetTick() + Timeout;
+
+  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Change state */
+          hhash->State = HAL_HASH_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hhash);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  
+  /* Read the message digest */
+  HASH_GetDigest(pOutBuffer, 20);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
+            The digest is available in pOutBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_AlgoSelection_SHA1 | HASH_CR_INIT;
+  }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(pInBuffer, Size);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Group3 HASH processing functions using interrupt mode
+ *  @brief   processing functions using interrupt mode. 
+ *
+@verbatim   
+ ===============================================================================
+              ##### HASH processing using interrupt mode functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in interrupt mode
+          the hash value using one of the following algorithms:
+      (+) MD5
+      (+) SHA1
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
+  *         The digest is available in pOutBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pOutBuffer: Pointer to the Output buffer (hashed buffer).   
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  uint32_t buffercounter;
+  uint32_t inputcounter;
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  if(hhash->HashITCounter == 0)
+  {
+    hhash->HashITCounter = 1;
+  }
+  else
+  {
+    hhash->HashITCounter = 0;
+  }
+  if(hhash->State == HAL_HASH_STATE_READY)
+  {
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+    
+    hhash->HashInCount = Size;
+    hhash->pHashInBuffPtr = pInBuffer;
+    hhash->pHashOutBuffPtr = pOutBuffer;
+    
+    /* Check if initialization phase has already been performed */
+    if(hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Select the SHA1 mode */
+      HASH->CR |= HASH_AlgoSelection_MD5;
+      /* Reset the HASH processor core, so that the HASH will be ready to compute 
+         the message digest of a new message */
+      HASH->CR |= HASH_CR_INIT;
+    }
+    
+    /* Set the phase */
+    hhash->Phase = HAL_HASH_PHASE_PROCESS;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+    
+    /* Enable Interrupts */
+    HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+  {
+    outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);
+    
+    if(hhash->HashInCount == 0)
+    {
+      /* Disable Interrupts */
+      HASH->IMR = 0;
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_READY;
+      /* Call digest computation complete callback */
+      HAL_HASH_DgstCpltCallback(hhash);
+    }
+  }
+  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+  {
+    if(hhash->HashInCount > 64)
+    {
+      inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+      /* Write the Input block in the Data IN register */
+      for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
+      {
+        HASH->DIN = *(uint32_t*)inputaddr;
+      }
+      if(hhash->HashITCounter == 0)
+      {
+        HASH->DIN = *(uint32_t*)inputaddr;
+
+        if(hhash->HashInCount >= 68)
+        {
+          /* Decrement buffer counter */
+          hhash->HashInCount -= 68;
+          hhash->pHashInBuffPtr+= 68;
+        }
+        else
+        {
+          hhash->HashInCount -= 64;
+        }
+      }
+      else
+      {
+        /* Decrement buffer counter */
+        hhash->HashInCount -= 64;
+        hhash->pHashInBuffPtr+= 64;
+      }
+    }
+    else
+    {
+      /* Get the buffer address */
+      inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+      /* Get the buffer counter */
+      inputcounter = hhash->HashInCount;
+      /* Disable Interrupts */
+      HASH->IMR &= ~(HASH_IT_DINI);
+      /* Configure the number of valid bits in last word of the message */
+      __HAL_HASH_SET_NBVALIDBITS(inputcounter);
+      
+      if((inputcounter > 4) && (inputcounter%4))
+      {
+        inputcounter = (inputcounter+4-inputcounter%4);
+      }
+      
+      /* Write the Input block in the Data IN register */
+      for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
+      {
+        HASH->DIN = *(uint32_t*)inputaddr;
+        inputaddr+=4;
+      }
+      /* Start the digest calculation */
+      __HAL_HASH_START_DIGEST();
+      /* Reset buffer counter */
+      hhash->HashInCount = 0;
+    }
+    /* Call Input data transfer complete callback */
+    HAL_HASH_InCpltCallback(hhash);
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
+  *         The digest is available in pOutBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed). 
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+  uint32_t inputaddr;
+  uint32_t outputaddr;
+  uint32_t buffercounter;
+  uint32_t inputcounter;
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  if(hhash->HashITCounter == 0)
+  {
+    hhash->HashITCounter = 1;
+  }
+  else
+  {
+    hhash->HashITCounter = 0;
+  }
+  if(hhash->State == HAL_HASH_STATE_READY)
+  {
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+    
+    hhash->HashInCount = Size;
+    hhash->pHashInBuffPtr = pInBuffer;
+    hhash->pHashOutBuffPtr = pOutBuffer;
+    
+    /* Check if initialization phase has already been performed */
+    if(hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Select the SHA1 mode */
+      HASH->CR |= HASH_AlgoSelection_SHA1;
+      /* Reset the HASH processor core, so that the HASH will be ready to compute 
+         the message digest of a new message */
+      HASH->CR |= HASH_CR_INIT;
+    }
+    
+    /* Set the phase */
+    hhash->Phase = HAL_HASH_PHASE_PROCESS;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+    
+    /* Enable Interrupts */
+    HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+  {
+    outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
+    /* Read the Output block from the Output FIFO */
+    *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);
+    outputaddr+=4;
+    *(uint32_t*)(outputaddr) = __REV(HASH->HR[4]);
+    if(hhash->HashInCount == 0)
+    {
+      /* Disable Interrupts */
+      HASH->IMR = 0;
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_READY;
+      /* Call digest computation complete callback */
+      HAL_HASH_DgstCpltCallback(hhash);
+    }
+  }
+  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+  {
+    if(hhash->HashInCount > 64)
+    {
+      inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+      /* Write the Input block in the Data IN register */
+      for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
+      {
+        HASH->DIN = *(uint32_t*)inputaddr;
+        inputaddr+=4;
+      }
+      if(hhash->HashITCounter == 0)
+      {
+        HASH->DIN = *(uint32_t*)inputaddr;
+      
+        if(hhash->HashInCount >= 68)
+        {
+          /* Decrement buffer counter */
+          hhash->HashInCount -= 68;
+          hhash->pHashInBuffPtr+= 68;
+        }
+        else
+        {
+          hhash->HashInCount -= 64;
+        }
+      }
+      else
+      {
+        /* Decrement buffer counter */
+        hhash->HashInCount -= 64;
+        hhash->pHashInBuffPtr+= 64;
+      }
+    }
+    else
+    {
+      /* Get the buffer address */
+      inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+      /* Get the buffer counter */
+      inputcounter = hhash->HashInCount;
+      /* Disable Interrupts */
+      HASH->IMR &= ~(HASH_IT_DINI);
+      /* Configure the number of valid bits in last word of the message */
+      __HAL_HASH_SET_NBVALIDBITS(inputcounter);
+      
+      if((inputcounter > 4) && (inputcounter%4))
+      {
+        inputcounter = (inputcounter+4-inputcounter%4);
+      }
+      
+      /* Write the Input block in the Data IN register */
+      for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
+      {
+        HASH->DIN = *(uint32_t*)inputaddr;
+        inputaddr+=4;
+      }
+      /* Start the digest calculation */
+      __HAL_HASH_START_DIGEST();
+      /* Reset buffer counter */
+      hhash->HashInCount = 0;
+    }
+    /* Call Input data transfer complete callback */
+    HAL_HASH_InCpltCallback(hhash);
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief This function handles HASH interrupt request.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @retval None
+  */
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
+{
+  switch(HASH->CR & HASH_CR_ALGO)
+  {
+    case HASH_AlgoSelection_MD5:
+       HAL_HASH_MD5_Start_IT(hhash, NULL, 0, NULL);
+    break;
+    
+    case HASH_AlgoSelection_SHA1:
+      HAL_HASH_SHA1_Start_IT(hhash, NULL, 0, NULL);
+    break;
+    
+    default:
+    break;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Group4 HASH processing functions using DMA mode
+ *  @brief   processing functions using DMA mode. 
+ *
+@verbatim   
+ ===============================================================================
+              ##### HASH processing using DMA mode functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in DMA mode
+          the hash value using one of the following algorithms:
+      (+) MD5
+      (+) SHA1
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the HASH peripheral in MD5 mode then enables DMA to
+            control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  uint32_t inputaddr  = (uint32_t)pInBuffer;
+  
+   /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_AlgoSelection_MD5 | HASH_CR_INIT;
+  }
+   
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+    
+  /* Set the HASH DMA transfer complete callback */
+  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+  /* Set the DMA error callback */
+  hhash->hdmain->XferErrorCallback = HASH_DMAError;
+  
+  /* Enable the DMA In DMA Stream */
+  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
+  
+  /* Enable DMA requests */
+  HASH->CR |= (HASH_CR_DMAE);
+  
+   /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns the computed digest in MD5 mode
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
+  * @param  Timeout: Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  
+   /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change HASH peripheral state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+
+  while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Read the message digest */
+  HASH_GetDigest(pOutBuffer, 16);
+      
+  /* Change HASH peripheral state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+   /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the HASH peripheral in SHA1 mode then enables DMA to
+            control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  uint32_t inputaddr  = (uint32_t)pInBuffer;
+  
+   /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_AlgoSelection_SHA1;
+    HASH->CR |= HASH_CR_INIT;
+  }
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Set the HASH DMA transfer complete callback */
+  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+  /* Set the DMA error callback */
+  hhash->hdmain->XferErrorCallback = HASH_DMAError;
+  
+  /* Enable the DMA In DMA Stream */
+  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
+  
+  /* Enable DMA requests */
+  HASH->CR |= (HASH_CR_DMAE);
+  
+   /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns the computed digest in SHA1 mode.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.  
+  * @param  Timeout: Timeout value    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  
+   /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change HASH peripheral state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+  while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Read the message digest */
+  HASH_GetDigest(pOutBuffer, 20);
+  
+  /* Change HASH peripheral state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+   /* Process UnLock */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Group5 HASH-MAC (HMAC) processing functions using polling mode 
+ *  @brief   HMAC processing functions using polling mode . 
+ *
+@verbatim   
+ ===============================================================================
+              ##### HMAC processing using polling mode functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in polling mode
+          the HMAC value using one of the following algorithms:
+      (+) MD5
+      (+) SHA1
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the HASH peripheral in HMAC MD5 mode
+  *         then processes pInBuffer. The digest is available in pOutBuffer
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+  * @param  Timeout: Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  
+   /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Check if key size is greater than 64 bytes */
+    if(hhash->Init.KeySize > 64)
+    {
+      /* Select the HMAC MD5 mode */
+      HASH->CR |= (HASH_AlgoSelection_MD5 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey | HASH_CR_INIT);
+    }
+    else
+    {
+      /* Select the HMAC MD5 mode */
+      HASH->CR |= (HASH_AlgoSelection_MD5 | HASH_AlgoMode_HMAC | HASH_CR_INIT);
+    }
+  }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /************************** STEP 1 ******************************************/
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+
+  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /************************** STEP 2 ******************************************/
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(pInBuffer, Size);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+  
+  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /************************** STEP 3 ******************************************/
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+  
+  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Read the message digest */
+  HASH_GetDigest(pOutBuffer, 16);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the HASH peripheral in HMAC SHA1 mode
+  *         then processes pInBuffer. The digest is available in pOutBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param   Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+  * @param  Timeout: Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Check if key size is greater than 64 bytes */
+    if(hhash->Init.KeySize > 64)
+    {
+      /* Select the HMAC SHA1 mode */
+      HASH->CR |= (HASH_AlgoSelection_SHA1 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey | HASH_CR_INIT);
+    }
+    else
+    {
+      /* Select the HMAC SHA1 mode */
+      HASH->CR |= (HASH_AlgoSelection_SHA1 | HASH_AlgoMode_HMAC | HASH_CR_INIT);
+    }
+  }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /************************** STEP 1 ******************************************/
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+  
+  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /************************** STEP 2 ******************************************/
+  /* Configure the number of valid bits in last word of the message */  
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(pInBuffer, Size);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+  
+  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /************************** STEP 3 ******************************************/
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+  
+  /* Write input buffer in data register */
+  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+
+  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /* Read the message digest */
+  HASH_GetDigest(pOutBuffer, 20);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Group6 HASH-MAC (HMAC) processing functions using DMA mode 
+ *  @brief   HMAC processing functions using DMA mode . 
+ *
+@verbatim   
+ ===============================================================================
+                ##### HMAC processing using DMA mode functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in DMA mode
+          the HMAC value using one of the following algorithms:
+      (+) MD5
+      (+) SHA1
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the HASH peripheral in HMAC MD5 mode
+  *         then enables DMA to control data transfer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  uint32_t inputaddr  = 0;
+  
+   /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Save buffer pointer and size in handle */
+  hhash->pHashInBuffPtr = pInBuffer;
+  hhash->HashBuffSize = Size;
+  hhash->HashInCount = 0;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Check if key size is greater than 64 bytes */
+    if(hhash->Init.KeySize > 64)
+    {
+      /* Select the HMAC MD5 mode */
+      HASH->CR |= (HASH_AlgoSelection_MD5 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey | HASH_CR_INIT);
+    }
+    else
+    {
+      /* Select the HMAC MD5 mode */
+      HASH->CR |= (HASH_AlgoSelection_MD5 | HASH_AlgoMode_HMAC | HASH_CR_INIT);
+    }
+  }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+  
+  /* Get the key address */
+  inputaddr = (uint32_t)(hhash->Init.pKey);
+  
+  /* Set the HASH DMA transfer complete callback */
+  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+  /* Set the DMA error callback */
+  hhash->hdmain->XferErrorCallback = HASH_DMAError;
+  
+  /* Enable the DMA In DMA Stream */
+  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
+  /* Enable DMA requests */
+  HASH->CR |= (HASH_CR_DMAE);
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the HASH peripheral in HMAC SHA1 mode
+  *         then enables DMA to control data transfer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  uint32_t inputaddr  = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Save buffer pointer and size in handle */
+  hhash->pHashInBuffPtr = pInBuffer;
+  hhash->HashBuffSize = Size;
+  hhash->HashInCount = 0;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Check if key size is greater than 64 bytes */
+    if(hhash->Init.KeySize > 64)
+    {
+      /* Select the HMAC SHA1 mode */
+      HASH->CR |= (HASH_AlgoSelection_SHA1 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey | HASH_CR_INIT);
+    }
+    else
+    {
+      /* Select the HMAC SHA1 mode */
+      HASH->CR |= (HASH_AlgoSelection_SHA1 | HASH_AlgoMode_HMAC | HASH_CR_INIT);
+    }
+  }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+  
+  /* Get the key address */
+  inputaddr = (uint32_t)(hhash->Init.pKey);
+  
+  /* Set the HASH DMA transfer complete callback */
+  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+  /* Set the DMA error callback */
+  hhash->hdmain->XferErrorCallback = HASH_DMAError;
+  
+  /* Enable the DMA In DMA Stream */
+  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
+  /* Enable DMA requests */
+  HASH->CR |= (HASH_CR_DMAE);
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Group7 Peripheral State functions 
+ *  @brief   Peripheral State functions. 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief return the HASH state
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @retval HAL state
+  */
+HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
+{
+  return hhash->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  DMA HASH Input Data complete callback. 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
+{
+  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  uint32_t inputaddr = 0;
+  uint32_t buffersize = 0;
+  
+  if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
+  {
+    /* Disable the DMA transfer */
+    HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
+    
+    /* Change HASH peripheral state */
+    hhash->State = HAL_HASH_STATE_READY;
+    
+    /* Call Input data transfer complete callback */
+    HAL_HASH_InCpltCallback(hhash);
+  }
+  else
+  {
+    /* Increment Interrupt counter */
+    hhash->HashInCount++;
+    /* Disable the DMA transfer before starting the next transfer */
+    HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
+    
+    if(hhash->HashInCount <= 2)
+    {
+      /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
+      if(hhash->HashInCount == 1)
+      {
+        inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+        buffersize = hhash->HashBuffSize;
+      }
+      /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
+      else if(hhash->HashInCount == 2)
+      {
+        inputaddr = (uint32_t)hhash->Init.pKey;
+        buffersize = hhash->Init.KeySize;
+      }
+      /* Configure the number of valid bits in last word of the message */
+      HASH->STR |= 8 * (buffersize % 4);
+      
+      /* Set the HASH DMA transfer complete */
+      hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+      
+      /* Enable the DMA In DMA Stream */
+      HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));
+      
+      /* Enable DMA requests */
+      HASH->CR |= (HASH_CR_DMAE);
+    }
+    else
+    {
+      /* Disable the DMA transfer */
+      HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
+      
+      /* Reset the InCount */
+      hhash->HashInCount = 0;
+      
+      /* Change HASH peripheral state */
+      hhash->State = HAL_HASH_STATE_READY;
+      
+      /* Call Input data transfer complete callback */
+      HAL_HASH_InCpltCallback(hhash);
+    }
+  }
+}
+
+/**
+  * @brief  DMA HASH communication error callback. 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void HASH_DMAError(DMA_HandleTypeDef *hdma)
+{
+  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  hhash->State= HAL_HASH_STATE_READY;
+  HAL_HASH_ErrorCallback(hhash);
+}
+
+/**
+  * @brief  Writes the input buffer in data register.
+  * @param  pInBuffer: Pointer to input buffer
+  * @param  Size: The size of input buffer
+  * @retval None
+  */
+static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)
+{
+  uint32_t buffercounter;
+  uint32_t inputaddr = (uint32_t) pInBuffer;
+  
+  for(buffercounter = 0; buffercounter < Size; buffercounter+=4)
+  {
+    HASH->DIN = *(uint32_t*)inputaddr;
+    inputaddr+=4;
+  }
+}
+
+/**
+  * @brief  Provides the message digest result.
+  * @param  pMsgDigest: Pointer to the message digest
+  * @param  Size: The size of the message digest in bytes
+  * @retval None
+  */
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
+{
+  uint32_t msgdigest = (uint32_t)pMsgDigest;
+  
+  switch(Size)
+  {
+  case 16:
+    /* Read the message digest */
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+    break;
+  case 20:
+    /* Read the message digest */
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+    break;
+  case 28:
+    /* Read the message digest */
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+    break;
+  case 32:
+    /* Read the message digest */
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
+    break;
+  default:
+    break;
+  }
+}
+
+/**
+  * @}
+  */
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+#endif /* HAL_HASH_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,332 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_hash.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of HASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_HASH_H
+#define __STM32F4xx_HAL_HASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HASH
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  HASH Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t DataType;  /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+                           This parameter can be a value of @ref HASH_Data_Type */
+
+  uint32_t KeySize;   /*!< The key size is used only in HMAC operation          */
+
+  uint8_t* pKey;      /*!< The key is used only in HMAC operation               */
+}HASH_InitTypeDef;
+
+/** 
+  * @brief HAL State structures definition
+  */ 
+typedef enum
+{
+  HAL_HASH_STATE_RESET     = 0x00,  /*!< HASH not yet initialized or disabled */
+  HAL_HASH_STATE_READY     = 0x01,  /*!< HASH initialized and ready for use   */
+  HAL_HASH_STATE_BUSY      = 0x02,  /*!< HASH internal process is ongoing     */
+  HAL_HASH_STATE_TIMEOUT   = 0x03,  /*!< HASH timeout state                   */
+  HAL_HASH_STATE_ERROR     = 0x04   /*!< HASH error state                     */
+}HAL_HASH_STATETypeDef;
+
+/** 
+  * @brief HAL phase structures definition
+  */
+typedef enum
+{
+  HAL_HASH_PHASE_READY     = 0x01,  /*!< HASH peripheral is ready for initialization */
+  HAL_HASH_PHASE_PROCESS   = 0x02,  /*!< HASH peripheral is in processing phase      */
+}HAL_HASHPhaseTypeDef;
+
+/** 
+  * @brief  HASH Handle Structure definition
+  */
+typedef struct
+{
+      HASH_InitTypeDef           Init;              /*!< HASH required parameters       */
+
+      uint8_t                    *pHashInBuffPtr;   /*!< Pointer to input buffer        */
+
+      uint8_t                    *pHashOutBuffPtr;  /*!< Pointer to input buffer        */
+
+     __IO uint32_t               HashBuffSize;      /*!< Size of buffer to be processed */
+
+     __IO uint32_t               HashInCount;       /*!< Counter of inputed data        */
+
+     __IO uint32_t               HashITCounter;     /*!< Counter of issued interrupts   */
+
+      HAL_StatusTypeDef          Status;            /*!< HASH peripheral status         */
+
+      HAL_HASHPhaseTypeDef       Phase;             /*!< HASH peripheral phase          */
+
+      DMA_HandleTypeDef          *hdmain;           /*!< HASH In DMA handle parameters  */
+
+      HAL_LockTypeDef            Lock;              /*!< HASH locking object            */
+
+     __IO HAL_HASH_STATETypeDef  State;             /*!< HASH peripheral state          */
+} HASH_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HASH_Exported_Constants
+  * @{
+  */
+
+/** @defgroup HASH_Algo_Selection
+  * @{
+  */
+#define HASH_AlgoSelection_SHA1      ((uint32_t)0x0000)  /*!< HASH function is SHA1   */
+#define HASH_AlgoSelection_SHA224    HASH_CR_ALGO_1      /*!< HASH function is SHA224 */
+#define HASH_AlgoSelection_SHA256    HASH_CR_ALGO        /*!< HASH function is SHA256 */
+#define HASH_AlgoSelection_MD5       HASH_CR_ALGO_0      /*!< HASH function is MD5    */
+
+#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1)   || \
+                                              ((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \
+                                              ((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \
+                                              ((ALGOSELECTION) == HASH_AlgoSelection_MD5))
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Algorithm_Mode
+  * @{
+  */ 
+#define HASH_AlgoMode_HASH         ((uint32_t)0x00000000)  /*!< Algorithm is HASH */ 
+#define HASH_AlgoMode_HMAC         HASH_CR_MODE            /*!< Algorithm is HMAC */
+
+#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \
+                                    ((ALGOMODE) == HASH_AlgoMode_HMAC))
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Data_Type
+  * @{
+  */
+#define HASH_DATATYPE_32B          ((uint32_t)0x0000) /*!< 32-bit data. No swapping                     */
+#define HASH_DATATYPE_16B          HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped       */
+#define HASH_DATATYPE_8B           HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped            */
+#define HASH_DATATYPE_1B           HASH_CR_DATATYPE   /*!< 1-bit data. In the word all bits are swapped */
+
+#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DATATYPE_32B)|| \
+                                    ((DATATYPE) == HASH_DATATYPE_16B)|| \
+                                    ((DATATYPE) == HASH_DATATYPE_8B) || \
+                                    ((DATATYPE) == HASH_DATATYPE_1B))
+/**
+  * @}
+  */
+
+/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode
+  * @{
+  */ 
+#define HASH_HMACKeyType_ShortKey      ((uint32_t)0x00000000)  /*!< HMAC Key is <= 64 bytes */
+#define HASH_HMACKeyType_LongKey       HASH_CR_LKEY            /*!< HMAC Key is > 64 bytes  */
+
+#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \
+                                       ((KEYTYPE) == HASH_HMACKeyType_LongKey))
+/**
+  * @}
+  */
+
+/** @defgroup HASH_flags_definition
+  * @{
+  */
+#define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
+#define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                                         */
+#define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing                          */
+#define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy : processing a block of data                                  */
+#define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : The input buffer contains at least one word of data                 */
+/**
+  * @}
+  */
+
+/** @defgroup HASH_interrupts_definition
+  * @{
+  */  
+#define HASH_IT_DINI               HASH_IMR_DINIM  /*!< A new block can be entered into the input buffer (DIN) */
+#define HASH_IT_DCI                HASH_IMR_DCIM   /*!< Digest calculation complete                            */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset HASH handle state
+  * @param  __HANDLE__: specifies the HASH handle.
+  * @retval None
+  */
+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
+
+/** @brief  Check whether the specified HASH flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer. 
+  *            @arg HASH_FLAG_DCIS: Digest calculation complete
+  *            @arg HASH_FLAG_DMAS: DMA interface is enabled (DMAE=1) or a transfer is ongoing
+  *            @arg HASH_FLAG_BUSY: The hash core is Busy : processing a block of data
+  *            @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_HASH_GET_FLAG(__FLAG__) ((HASH->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Macros for HMAC finish.
+  * @param  None
+  * @retval None
+  */
+#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
+
+/**
+  * @brief  Enable the multiple DMA mode. 
+  *         This feature is available only in STM32F429x and STM32F439x devices.
+  * @param  None
+  * @retval None
+  */
+#define __HAL_HASH_SET_MDMAT()          HASH->CR |= HASH_CR_MDMAT
+
+/**
+  * @brief  Disable the multiple DMA mode.
+  * @param  None
+  * @retval None
+  */
+#define __HAL_HASH_RESET_MDMAT()        HASH->CR &= (uint32_t)(~HASH_CR_MDMAT)
+
+/**
+  * @brief  Start the digest computation
+  * @param  None
+  * @retval None
+  */
+#define __HAL_HASH_START_DIGEST()       HASH->STR |= HASH_STR_DCAL
+
+/**
+  * @brief Set the number of valid bits in last word written in Data register
+  * @param  SIZE: size in byte of last data written in Data register.
+  * @retval None
+*/
+#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBW);\
+                                            HASH->STR |= 8 * ((SIZE) % 4);\
+                                           }while(0)
+
+/* Include HASH HAL Extension module */
+#include "stm32f4xx_hal_hash_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
+
+/* HASH processing using polling  *********************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/* HASH-MAC processing using polling  *****************************************/
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/* HASH processing using interrupt  *******************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+
+/* HASH processing using DMA  *************************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/* HASH-HMAC processing using DMA  ********************************************/
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/* Processing functions  ******************************************************/
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
+
+/* Peripheral State functions  ************************************************/
+HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
+void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
+void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
+void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
+
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_HASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash_ex.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1610 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_hash_ex.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   HASH HAL Extension module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of HASH peripheral:
+  *           + Extended HASH processing functions based on SHA224 Algorithm
+  *           + Extended HASH processing functions based on SHA256 Algorithm
+  *         
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The HASH HAL driver can be used as follows:
+    (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
+        (##) Enable the HASH interface clock using __HASH_CLK_ENABLE()
+        (##) In case of using processing APIs based on interrupts (e.g. HAL_HMACEx_SHA224_Start())
+            (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
+            (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
+            (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
+        (##) In case of using DMA to control data transfer (e.g. HAL_HMACEx_SH224_Start_DMA())
+            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+            (+++) Configure and enable one DMA stream one for managing data transfer from
+                memory to peripheral (input stream). Managing data transfer from
+                peripheral to memory can be performed only using CPU
+            (+++) Associate the initialized DMA handle to the HASH DMA handle
+                using  __HAL_LINKDMA()
+            (+++) Configure the priority and enable the NVIC for the transfer complete
+                interrupt on the DMA Stream: HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+    (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
+        (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
+        (##) For HMAC, the encryption key.
+        (##) For HMAC, the key size used for encryption.
+    (#)Three processing functions are available:
+        (##) Polling mode: processing APIs are blocking functions
+             i.e. they process the data and wait till the digest computation is finished
+             e.g. HAL_HASHEx_SHA224_Start()
+        (##) Interrupt mode: encryption and decryption APIs are not blocking functions
+                i.e. they process the data under interrupt
+                e.g. HAL_HASHEx_SHA224_Start_IT()
+        (##) DMA mode: processing APIs are not blocking functions and the CPU is
+             not used for data transfer i.e. the data transfer is ensured by DMA
+                e.g. HAL_HASHEx_SHA224_Start_DMA()
+    (#)When the processing function is called at first time after HAL_HASH_Init()
+       the HASH peripheral is initialized and processes the buffer in input.
+       After that, the digest computation is started.
+       When processing multi-buffer use the accumulate function to write the
+       data in the peripheral without starting the digest computation. In last 
+       buffer use the start function to input the last buffer ans start the digest
+       computation.
+       (##) e.g. HAL_HASHEx_SHA224_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
+       (##)  write (n-1)th data buffer in the peripheral without starting the digest computation
+       (##)  HAL_HASHEx_SHA224_Start() : write (n)th data buffer in the peripheral and start the digest computation
+    (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
+    (#)In case of using DMA, call the DMA start processing e.g. HAL_HASHEx_SHA224_Start_DMA().
+       After that, call the finish function in order to get the digest value
+       e.g. HAL_HASHEx_SHA224_Finish()
+    (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HASHEx 
+  * @brief HASH Extension HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+
+#if defined(STM32F437xx) || defined(STM32F439xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma);
+static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size);
+static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
+static void HASHEx_DMAError(DMA_HandleTypeDef *hdma);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HASHEx_Private_Functions
+  * @{
+  */
+
+/** @defgroup  HASHEx_Group1 HASH processing functions  
+ *  @brief   processing functions using polling mode 
+ *
+@verbatim   
+ ===============================================================================
+              ##### HASH processing using polling mode functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in polling mode
+          the hash value using one of the following algorithms:
+      (+) SHA224
+      (+) SHA256
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the HASH peripheral in SHA224 mode
+  *         then processes pInBuffer. The digest is available in pOutBuffer
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
+  * @param  Timeout: Specify Timeout value   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_AlgoSelection_SHA224 | HASH_CR_INIT;
+  }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Write input buffer in data register */
+  HASHEx_WriteData(pInBuffer, Size);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+  
+  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Read the message digest */
+  HASHEx_GetDigest(pOutBuffer, 28);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
+            The digest is available in pOutBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed). 
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
+  * @param  Timeout: Specify Timeout value   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_AlgoSelection_SHA256 | HASH_CR_INIT;
+  }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Write input buffer in data register */
+  HASHEx_WriteData(pInBuffer, Size);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+  
+  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Read the message digest */
+  HASHEx_GetDigest(pOutBuffer, 32);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);  
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initializes the HASH peripheral in SHA224 mode
+  *         then processes pInBuffer. The digest is available in pOutBuffer
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_AlgoSelection_SHA224 | HASH_CR_INIT;
+  }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Write input buffer in data register */
+  HASHEx_WriteData(pInBuffer, Size);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
+            The digest is available in pOutBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+   /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_AlgoSelection_SHA256 | HASH_CR_INIT;
+  }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Write input buffer in data register */
+  HASHEx_WriteData(pInBuffer, Size);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HASHEx_Group2 HMAC processing functions using polling mode 
+ *  @brief   HMAC processing functions using polling mode . 
+ *
+@verbatim   
+ ===============================================================================
+            ##### HMAC processing using polling mode functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in polling mode
+          the HMAC value using one of the following algorithms:
+      (+) SHA224
+      (+) SHA256
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the HASH peripheral in HMAC SHA224 mode
+  *         then processes pInBuffer. The digest is available in pOutBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed). 
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+
+   /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Check if key size is greater than 64 bytes */
+    if(hhash->Init.KeySize > 64)
+    {
+      /* Select the HMAC SHA224 mode */
+      HASH->CR |= (HASH_AlgoSelection_SHA224 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey | HASH_CR_INIT);
+    }
+    else
+    {
+      /* Select the HMAC SHA224 mode */
+      HASH->CR |= (HASH_AlgoSelection_SHA224 | HASH_AlgoMode_HMAC | HASH_CR_INIT);
+    }
+  }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /************************** STEP 1 ******************************************/
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+  
+  /* Write input buffer in data register */
+  HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+  
+  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /************************** STEP 2 ******************************************/
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Write input buffer in data register */
+  HASHEx_WriteData(pInBuffer, Size);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+  
+  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /************************** STEP 3 ******************************************/
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+  
+  /* Write input buffer in data register */
+  HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+  
+  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /* Read the message digest */
+  HASHEx_GetDigest(pOutBuffer, 28);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the HASH peripheral in HMAC SHA256 mode
+  *         then processes pInBuffer. The digest is available in pOutBuffer
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed). 
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Check if key size is greater than 64 bytes */
+    if(hhash->Init.KeySize > 64)
+    {
+      /* Select the HMAC SHA256 mode */
+      HASH->CR |= (HASH_AlgoSelection_SHA256 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey);
+    }
+    else
+    {
+      /* Select the HMAC SHA256 mode */
+      HASH->CR |= (HASH_AlgoSelection_SHA256 | HASH_AlgoMode_HMAC);
+    }
+    /* Reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_CR_INIT;
+  }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /************************** STEP 1 ******************************************/
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+  
+  /* Write input buffer in data register */
+  HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+  
+  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /************************** STEP 2 ******************************************/
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Write input buffer in data register */
+  HASHEx_WriteData(pInBuffer, Size);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+  
+  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /************************** STEP 3 ******************************************/
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+  
+  /* Write input buffer in data register */
+  HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+  
+  /* Start the digest calculation */
+  __HAL_HASH_START_DIGEST();
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+  
+  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /* Read the message digest */
+  HASHEx_GetDigest(pOutBuffer, 32);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+   /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HASHEx_Group3 HASH processing functions using interrupt mode
+ *  @brief   processing functions using interrupt mode. 
+ *
+@verbatim   
+ ===============================================================================
+              ##### HASH processing using interrupt functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in interrupt mode
+          the hash value using one of the following algorithms:
+      (+) SHA224
+      (+) SHA256
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the HASH peripheral in SHA224 mode then processes pInBuffer.
+  *         The digest is available in pOutBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+  uint32_t inputaddr;
+  uint32_t buffercounter;
+  uint32_t inputcounter;
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  if(hhash->HashITCounter == 0)
+  {
+    hhash->HashITCounter = 1;
+  }
+  else
+  {
+    hhash->HashITCounter = 0;
+  }
+  if(hhash->State == HAL_HASH_STATE_READY)
+  {
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+    
+    hhash->HashInCount = Size;
+    hhash->pHashInBuffPtr = pInBuffer;
+    hhash->pHashOutBuffPtr = pOutBuffer;
+    
+    /* Check if initialization phase has already been performed */
+    if(hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Select the SHA224 mode */
+      HASH->CR |= HASH_AlgoSelection_SHA224;
+      /* Reset the HASH processor core, so that the HASH will be ready to compute 
+         the message digest of a new message */
+      HASH->CR |= HASH_CR_INIT;
+    }
+    
+    /* Set the phase */
+    hhash->Phase = HAL_HASH_PHASE_PROCESS;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+    
+    /* Enable Interrupts */
+    HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+  {
+    /* Read the message digest */
+    HASHEx_GetDigest(hhash->pHashOutBuffPtr, 28);
+    if(hhash->HashInCount == 0)
+    {
+      /* Disable Interrupts */
+      HASH->IMR = 0;
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_READY;
+      /* Call digest computation complete callback */
+      HAL_HASH_DgstCpltCallback(hhash);
+    }
+  }
+  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+  {
+    if(hhash->HashInCount > 64)
+    {
+      inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+      /* Write the Input block in the Data IN register */
+      for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
+      {
+        HASH->DIN = *(uint32_t*)inputaddr;
+        inputaddr+=4;
+      }
+      if(hhash->HashITCounter == 0)
+      {
+        HASH->DIN = *(uint32_t*)inputaddr;
+        if(hhash->HashInCount >= 68)
+        {
+          /* Decrement buffer counter */
+          hhash->HashInCount -= 68;
+          hhash->pHashInBuffPtr+= 68;
+        }
+        else
+        {
+          hhash->HashInCount -= 64;
+        }
+      }
+      else
+      {
+        /* Decrement buffer counter */
+        hhash->HashInCount -= 64;
+        hhash->pHashInBuffPtr+= 64;
+      }
+    }
+    else
+    {
+      /* Get the buffer address */
+      inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+      /* Get the buffer counter */
+      inputcounter = hhash->HashInCount;
+      /* Disable Interrupts */
+      HASH->IMR &= ~(HASH_IT_DINI);
+      /* Configure the number of valid bits in last word of the message */
+      __HAL_HASH_SET_NBVALIDBITS(inputcounter);
+      
+      if((inputcounter > 4) && (inputcounter%4))
+      {
+        inputcounter = (inputcounter+4-inputcounter%4);
+      }
+      
+      /* Write the Input block in the Data IN register */
+      for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
+      {
+        HASH->DIN = *(uint32_t*)inputaddr;
+        inputaddr+=4;
+      }
+      /* Start the digest calculation */
+      __HAL_HASH_START_DIGEST();
+      /* Reset buffer counter */
+      hhash->HashInCount = 0;
+    }
+    /* Call Input data transfer complete callback */
+    HAL_HASH_InCpltCallback(hhash);
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
+  *         The digest is available in pOutBuffer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+  uint32_t inputaddr;
+  uint32_t buffercounter;
+  uint32_t inputcounter;
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  if(hhash->HashITCounter == 0)
+  {
+    hhash->HashITCounter = 1;
+  }
+  else
+  {
+    hhash->HashITCounter = 0;
+  }
+  if(hhash->State == HAL_HASH_STATE_READY)
+  {
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+    
+    hhash->HashInCount = Size;
+    hhash->pHashInBuffPtr = pInBuffer;
+    hhash->pHashOutBuffPtr = pOutBuffer;
+    
+    /* Check if initialization phase has already been performed */
+    if(hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Select the SHA256 mode */
+      HASH->CR |= HASH_AlgoSelection_SHA256;
+      /* Reset the HASH processor core, so that the HASH will be ready to compute 
+         the message digest of a new message */
+      HASH->CR |= HASH_CR_INIT;
+    }
+    
+    /* Set the phase */
+    hhash->Phase = HAL_HASH_PHASE_PROCESS;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+    
+    /* Enable Interrupts */
+    HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+  {
+    /* Read the message digest */
+    HASHEx_GetDigest(hhash->pHashOutBuffPtr, 32);
+    if(hhash->HashInCount == 0)
+    {
+      /* Disable Interrupts */
+      HASH->IMR = 0;
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_READY;
+      /* Call digest computation complete callback */
+      HAL_HASH_DgstCpltCallback(hhash);
+    }
+  }
+  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+  {
+    if(hhash->HashInCount > 64)
+    {
+      inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+      /* Write the Input block in the Data IN register */
+      for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
+      {
+        HASH->DIN = *(uint32_t*)inputaddr;
+        inputaddr+=4;
+      }
+      if(hhash->HashITCounter == 0)
+      {
+        HASH->DIN = *(uint32_t*)inputaddr;
+        
+        if(hhash->HashInCount >= 68)
+        {
+          /* Decrement buffer counter */
+          hhash->HashInCount -= 68;
+          hhash->pHashInBuffPtr+= 68;
+        }
+        else
+        {
+          hhash->HashInCount -= 64;
+        }
+      }
+      else
+      {
+        /* Decrement buffer counter */
+        hhash->HashInCount -= 64;
+        hhash->pHashInBuffPtr+= 64;
+      }
+    }
+    else
+    {
+      /* Get the buffer address */
+      inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+      /* Get the buffer counter */
+      inputcounter = hhash->HashInCount;
+      /* Disable Interrupts */
+      HASH->IMR &= ~(HASH_IT_DINI);
+      /* Configure the number of valid bits in last word of the message */
+      __HAL_HASH_SET_NBVALIDBITS(inputcounter);
+      
+      if((inputcounter > 4) && (inputcounter%4))
+      {
+        inputcounter = (inputcounter+4-inputcounter%4);
+      }
+      
+      /* Write the Input block in the Data IN register */
+      for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
+      {
+        HASH->DIN = *(uint32_t*)inputaddr;
+        inputaddr+=4;
+      }
+      /* Start the digest calculation */
+      __HAL_HASH_START_DIGEST();
+      /* Reset buffer counter */
+      hhash->HashInCount = 0;
+    }
+    /* Call Input data transfer complete callback */
+    HAL_HASH_InCpltCallback(hhash);
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief This function handles HASH interrupt request.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @retval None
+  */
+void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash)
+{
+  switch(HASH->CR & HASH_CR_ALGO)
+  {
+    
+    case HASH_AlgoSelection_SHA224:
+       HAL_HASHEx_SHA224_Start_IT(hhash, NULL, 0, NULL);
+    break;
+    
+    case HASH_AlgoSelection_SHA256:
+      HAL_HASHEx_SHA256_Start_IT(hhash, NULL, 0, NULL);
+    break;
+    
+    default:
+    break;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HASHEx_Group4 HASH processing functions using DMA mode
+ *  @brief   processing functions using DMA mode. 
+ *
+@verbatim   
+ ===============================================================================
+                ##### HASH processing using DMA functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in DMA mode
+          the hash value using one of the following algorithms:
+      (+) SHA224
+      (+) SHA256
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Initializes the HASH peripheral in SHA224 mode then enables DMA to
+            control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  uint32_t inputaddr  = (uint32_t)pInBuffer;
+  
+   /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_AlgoSelection_SHA224 | HASH_CR_INIT;
+  }
+   
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+    
+  /* Set the HASH DMA transfer complete callback */
+  hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
+  /* Set the DMA error callback */
+  hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
+  
+  /* Enable the DMA In DMA Stream */
+  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
+  
+  /* Enable DMA requests */
+  HASH->CR |= (HASH_CR_DMAE);
+  
+   /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns the computed digest in SHA224
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
+  * @param  Timeout: Timeout value    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change HASH peripheral state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+  
+  while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Read the message digest */
+  HASHEx_GetDigest(pOutBuffer, 28);
+      
+  /* Change HASH peripheral state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+   /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the HASH peripheral in SHA256 mode then enables DMA to
+            control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  uint32_t inputaddr  = (uint32_t)pInBuffer;
+  
+   /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_AlgoSelection_SHA256 | HASH_CR_INIT;
+  }
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(Size);
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+    
+  /* Set the HASH DMA transfer complete callback */
+  hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
+  /* Set the DMA error callback */
+  hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
+  
+  /* Enable the DMA In DMA Stream */
+  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
+  
+  /* Enable DMA requests */
+  HASH->CR |= (HASH_CR_DMAE);
+  
+   /* Process UnLock */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns the computed digest in SHA256.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
+  * @param  Timeout: Timeout value    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+  uint32_t timeout = 0;   
+  
+   /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change HASH peripheral state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + Timeout;
+  
+  while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Change state */
+        hhash->State = HAL_HASH_STATE_TIMEOUT;
+        
+        /* Process Unlocked */          
+        __HAL_UNLOCK(hhash);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Read the message digest */
+  HASHEx_GetDigest(pOutBuffer, 32);
+  
+  /* Change HASH peripheral state */
+  hhash->State = HAL_HASH_STATE_READY;
+  
+   /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @}
+  */
+/** @defgroup HASHEx_Group5 HMAC processing functions using DMA mode 
+ *  @brief   HMAC processing functions using DMA mode . 
+ *
+@verbatim   
+ ===============================================================================
+                ##### HMAC processing using DMA functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to calculate in DMA mode
+          the HMAC value using one of the following algorithms:
+      (+) SHA224
+      (+) SHA256
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the HASH peripheral in HMAC SHA224 mode
+  *         then enables DMA to control data transfer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  uint32_t inputaddr;
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Save buffer pointer and size in handle */
+  hhash->pHashInBuffPtr = pInBuffer;
+  hhash->HashBuffSize = Size;
+  hhash->HashInCount = 0;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Check if key size is greater than 64 bytes */
+    if(hhash->Init.KeySize > 64)
+    {
+      /* Select the HMAC SHA224 mode */
+      HASH->CR |= (HASH_AlgoSelection_SHA224 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey | HASH_CR_INIT);
+    }
+    else
+    {
+      /* Select the HMAC SHA224 mode */
+      HASH->CR |= (HASH_AlgoSelection_SHA224 | HASH_AlgoMode_HMAC | HASH_CR_INIT);
+    }
+  }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+  
+  /* Get the key address */
+  inputaddr = (uint32_t)(hhash->Init.pKey);
+  
+  /* Set the HASH DMA transfer complete callback */
+  hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
+  /* Set the DMA error callback */
+  hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
+  
+  /* Enable the DMA In DMA Stream */
+  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
+  /* Enable DMA requests */
+  HASH->CR |= (HASH_CR_DMAE);
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the HASH peripheral in HMAC SHA256 mode
+  *         then enables DMA to control data transfer.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
+  * @param  Size: Length of the input buffer in bytes.
+  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  uint32_t inputaddr;
+  
+  /* Process Locked */
+  __HAL_LOCK(hhash);
+  
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_BUSY;
+  
+  /* Save buffer pointer and size in handle */
+  hhash->pHashInBuffPtr = pInBuffer;
+  hhash->HashBuffSize = Size;
+  hhash->HashInCount = 0;
+  
+  /* Check if initialization phase has already been performed */
+  if(hhash->Phase == HAL_HASH_PHASE_READY)
+  {
+    /* Check if key size is greater than 64 bytes */
+    if(hhash->Init.KeySize > 64)
+    {
+      /* Select the HMAC SHA256 mode */
+      HASH->CR |= (HASH_AlgoSelection_SHA256 | HASH_AlgoMode_HMAC | HASH_HMACKeyType_LongKey);
+    }
+    else
+    {
+      /* Select the HMAC SHA256 mode */
+      HASH->CR |= (HASH_AlgoSelection_SHA256 | HASH_AlgoMode_HMAC);
+    }
+    /* Reset the HASH processor core, so that the HASH will be ready to compute 
+       the message digest of a new message */
+    HASH->CR |= HASH_CR_INIT;
+  }
+  
+  /* Set the phase */
+  hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  
+  /* Configure the number of valid bits in last word of the message */
+  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+  
+  /* Get the key address */
+  inputaddr = (uint32_t)(hhash->Init.pKey);
+  
+  /* Set the HASH DMA transfer complete callback */
+  hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
+  /* Set the DMA error callback */
+  hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
+  
+  /* Enable the DMA In DMA Stream */
+  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
+  /* Enable DMA requests */
+  HASH->CR |= (HASH_CR_DMAE);
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhash);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Writes the input buffer in data register.
+  * @param  pInBuffer: Pointer to input buffer
+  * @param  Size: The size of input buffer
+  * @retval None
+  */
+static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size)
+{
+  uint32_t buffercounter;
+  uint32_t inputaddr = (uint32_t) pInBuffer;
+  
+  for(buffercounter = 0; buffercounter < Size; buffercounter+=4)
+  {
+    HASH->DIN = *(uint32_t*)inputaddr;
+    inputaddr+=4;
+  }
+}
+
+/**
+  * @brief  Provides the message digest result.
+  * @param  pMsgDigest: Pointer to the message digest
+  * @param  Size: The size of the message digest in bytes
+  * @retval None
+  */
+static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
+{
+  uint32_t msgdigest = (uint32_t)pMsgDigest;
+  
+  switch(Size)
+  {
+  case 16:
+    /* Read the message digest */
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+    break;
+  case 20:
+    /* Read the message digest */
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+    break;
+  case 28:
+    /* Read the message digest */
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+    break;
+  case 32:
+    /* Read the message digest */
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+    msgdigest+=4;
+    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
+    break;
+  default:
+    break;
+  }
+}
+
+/**
+  * @brief  DMA HASH Input Data complete callback. 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma)
+{
+  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  uint32_t inputaddr = 0;
+  uint32_t buffersize = 0;
+  
+  if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
+  {
+    /* Disable the DMA transfer */
+    HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
+    
+    /* Change HASH peripheral state */
+    hhash->State = HAL_HASH_STATE_READY;
+    
+    /* Call Input data transfer complete callback */
+    HAL_HASH_InCpltCallback(hhash);
+  }
+  else
+  {
+    /* Increment Interrupt counter */
+    hhash->HashInCount++;
+    /* Disable the DMA transfer before starting the next transfer */
+    HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
+    
+    if(hhash->HashInCount <= 2)
+    {
+      /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
+      if(hhash->HashInCount == 1)
+      {
+        inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+        buffersize = hhash->HashBuffSize;
+      }
+      /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
+      else if(hhash->HashInCount == 2)
+      {
+        inputaddr = (uint32_t)hhash->Init.pKey;
+        buffersize = hhash->Init.KeySize;
+      }
+      /* Configure the number of valid bits in last word of the message */
+      HASH->STR |= 8 * (buffersize % 4);
+      
+      /* Set the HASH DMA transfer complete */
+      hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
+      
+      /* Enable the DMA In DMA Stream */
+      HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));
+      
+      /* Enable DMA requests */
+      HASH->CR |= (HASH_CR_DMAE);
+    }
+    else
+    {
+      /* Disable the DMA transfer */
+      HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
+      
+      /* Reset the InCount */
+      hhash->HashInCount = 0;
+      
+      /* Change HASH peripheral state */
+      hhash->State = HAL_HASH_STATE_READY;
+      
+      /* Call Input data transfer complete callback */
+      HAL_HASH_InCpltCallback(hhash);
+    }
+  }
+}
+
+/**
+  * @brief  DMA HASH communication error callback. 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void HASHEx_DMAError(DMA_HandleTypeDef *hdma)
+{
+  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  hhash->State= HAL_HASH_STATE_READY;
+  HAL_HASH_ErrorCallback(hhash);
+}
+
+
+/**
+  * @}
+  */
+#endif /* STM32F437xx || STM32F439xx */
+
+#endif /* HAL_HASH_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hash_ex.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,106 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_hash_ex.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of HASH HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_HASH_EX_H
+#define __STM32F4xx_HAL_HASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F437xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HASHEx
+  * @{
+  */ 
+  
+/* Exported types ------------------------------------------------------------*/ 
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* HASH processing using polling  *********************************************/
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/* HASH-MAC processing using polling  *****************************************/
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/* HASH processing using interrupt  *******************************************/
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+
+/* HASH processing using DMA  *************************************************/
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/* HASH-HMAC processing using DMA  ********************************************/
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/* Processing functions  ******************************************************/
+void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash);
+
+#endif /* STM32F437xx || STM32F439xx */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_HASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1192 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_hcd.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   HCD HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the USB Peripheral Controller:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#)Declare a HCD_HandleTypeDef handle structure, for example:
+       HCD_HandleTypeDef  hhcd;
+        
+    (#)Fill parameters of Init structure in HCD handle
+  
+    (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) 
+
+    (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
+        (##) Enable the HCD/USB Low Level interface clock using the following macros
+             (+++) __OTGFS-OTG_CLK_ENABLE() or __OTGHS-OTG_CLK_ENABLE()
+             (+++) __OTGHSULPI_CLK_ENABLE() For High Speed Mode
+           
+        (##) Initialize the related GPIO clocks
+        (##) Configure HCD pin-out
+        (##) Configure HCD NVIC interrupt
+    
+    (#)Associate the Upper USB Host stack to the HAL HCD Driver:
+        (##) hhcd.pData = phost;
+
+    (#)Enable HCD transmission and reception:
+        (##) HAL_HCD_Start();
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HCD 
+  * @brief HCD HAL module driver
+  * @{
+  */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); 
+static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
+static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HCD_Private_Functions
+  * @{
+  */
+
+/** @defgroup HCD_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+          ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the host driver
+  * @param  hhcd: HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
+{ 
+  /* Check the HCD handle allocation */
+  if(hhcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
+
+  hhcd->State = HCD_BUSY;
+  
+  /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+  HAL_HCD_MspInit(hhcd);
+
+  /* Disable the Interrupts */
+ __HAL_HCD_DISABLE(hhcd);
+ 
+ /*Init the Core (common init.) */
+ USB_CoreInit(hhcd->Instance, hhcd->Init);
+ 
+ /* Force Host Mode*/
+ USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE);
+ 
+ /* Init Host */
+ USB_HostInit(hhcd->Instance, hhcd->Init);
+ 
+ hhcd->State= HCD_READY;
+ 
+ return HAL_OK;
+}
+
+/**
+  * @brief  Initialize a host channel
+  * @param  hhcd: HCD handle
+  * @param  ch_num: Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @param  epnum: Endpoint number.
+  *          This parameter can be a value from 1 to 15
+  * @param  dev_address : Current device address
+  *          This parameter can be a value from 0 to 255
+  * @param  speed: Current device speed.
+  *          This parameter can be one of these values:
+  *            HCD_SPEED_HIGH: High speed mode,
+  *            HCD_SPEED_FULL: Full speed mode,
+  *            HCD_SPEED_LOW: Low speed mode
+  * @param  ep_type: Endpoint Type.
+  *          This parameter can be one of these values:
+  *            EP_TYPE_CTRL: Control type,
+  *            EP_TYPE_ISOC: Isochrounous type,
+  *            EP_TYPE_BULK: Bulk type,
+  *            EP_TYPE_INTR: Interrupt type
+  * @param  mps: Max Packet Size.
+  *          This parameter can be a value from 0 to32K
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,  
+                                  uint8_t ch_num,
+                                  uint8_t epnum,
+                                  uint8_t dev_address,
+                                  uint8_t speed,
+                                  uint8_t ep_type,
+                                  uint16_t mps)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  __HAL_LOCK(hhcd); 
+  
+  hhcd->hc[ch_num].dev_addr = dev_address;
+  hhcd->hc[ch_num].max_packet = mps;
+  hhcd->hc[ch_num].ch_num = ch_num;
+  hhcd->hc[ch_num].ep_type = ep_type;
+  hhcd->hc[ch_num].ep_num = epnum & 0x7F;
+  hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);
+  hhcd->hc[ch_num].speed = speed;
+
+  status =  USB_HC_Init(hhcd->Instance, 
+                        ch_num,
+                        epnum,
+                        dev_address,
+                        speed,
+                        ep_type,
+                        mps);
+  __HAL_UNLOCK(hhcd); 
+  
+  return status;
+}
+
+
+
+/**
+  * @brief  Halt a host channel
+  * @param  hhcd: HCD handle
+  * @param  ch_num: Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,  
+                                  uint8_t ch_num)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  __HAL_LOCK(hhcd);   
+  USB_HC_Halt(hhcd->Instance, ch_num);   
+  __HAL_UNLOCK(hhcd);
+  
+  return status;
+}
+/**
+  * @brief  DeInitialize the host driver
+  * @param  hhcd: HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
+{
+  /* Check the HCD handle allocation */
+  if(hhcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  hhcd->State = HCD_BUSY;
+  
+  /* DeInit the low level hardware */
+  HAL_HCD_MspDeInit(hhcd);
+  
+   __HAL_HCD_DISABLE(hhcd);
+  
+  hhcd->State = HCD_READY; 
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the HCD MSP.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+__weak void  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_MspInit could be implenetd in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes HCD MSP.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+__weak void  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhhcd)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_MspDeInit could be implenetd in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Group2 IO operation functions 
+  *  @brief   HCD IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of functions allowing to manage the USB Host Data 
+    Transfer
+       
+@endverbatim
+  * @{
+  */
+  
+/**                                
+  * @brief  Submit a new URB for processing 
+  * @param  hhcd: HCD handle
+  * @param  ch_num: Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @param  direction: Channel number.
+  *          This parameter can be one of these values:
+  *           0 : Output / 1 : Input
+  * @param  ep_type: Endpoint Type.
+  *          This parameter can be one of these values:
+  *            EP_TYPE_CTRL: Control type/
+  *            EP_TYPE_ISOC: Isochrounous type/
+  *            EP_TYPE_BULK: Bulk type/
+  *            EP_TYPE_INTR: Interrupt type/
+  * @param  token: Endpoint Type.
+  *          This parameter can be one of these values:
+  *            0: HC_PID_SETUP / 1: HC_PID_DATA1
+  * @param  pbuff: pointer to URB data
+  * @param  length: Length of URB data
+  * @param  do_ping: activate do ping protocol (for high speed only).
+  *          This parameter can be one of these values:
+  *           0 : do ping inactive / 1 : do ping active 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+                                            uint8_t ch_num, 
+                                            uint8_t direction ,
+                                            uint8_t ep_type,  
+                                            uint8_t token, 
+                                            uint8_t* pbuff, 
+                                            uint16_t length,
+                                            uint8_t do_ping) 
+{
+  hhcd->hc[ch_num].ep_is_in = direction;
+  hhcd->hc[ch_num].ep_type  = ep_type; 
+  
+  if(token == 0)
+  {
+    hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
+  }
+  else
+  {
+    hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+  }
+  
+  /* Manage Data Toggle */
+  switch(ep_type)
+  {
+  case EP_TYPE_CTRL:
+    if((token == 1) && (direction == 0)) /*send data */
+    {
+      if ( length == 0 )
+      { /* For Status OUT stage, Length==0, Status Out PID = 1 */
+        hhcd->hc[ch_num].toggle_out = 1;
+      }
+      
+      /* Set the Data Toggle bit as per the Flag */
+      if ( hhcd->hc[ch_num].toggle_out == 0)
+      { /* Put the PID 0 */
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;    
+      }
+      else
+      { /* Put the PID 1 */
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
+      }
+      if(hhcd->hc[ch_num].urb_state  != URB_NOTREADY)
+      {
+        hhcd->hc[ch_num].do_ping = do_ping;
+      }
+    }
+    break;
+  
+  case EP_TYPE_BULK:
+    if(direction == 0)
+    {
+      /* Set the Data Toggle bit as per the Flag */
+      if ( hhcd->hc[ch_num].toggle_out == 0)
+      { /* Put the PID 0 */
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;    
+      }
+      else
+      { /* Put the PID 1 */
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
+      }
+      if(hhcd->hc[ch_num].urb_state  != URB_NOTREADY)
+      {
+        hhcd->hc[ch_num].do_ping = do_ping;
+      }
+    }
+    else
+    {
+      if( hhcd->hc[ch_num].toggle_in == 0)
+      {
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+      }
+      else
+      {
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+      }
+    }
+    
+    break;
+  case EP_TYPE_INTR:
+    if(direction == 0)
+    {
+      /* Set the Data Toggle bit as per the Flag */
+      if ( hhcd->hc[ch_num].toggle_out == 0)
+      { /* Put the PID 0 */
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;    
+      }
+      else
+      { /* Put the PID 1 */
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
+      }
+    }
+    else
+    {
+      if( hhcd->hc[ch_num].toggle_in == 0)
+      {
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+      }
+      else
+      {
+        hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+      }
+    }
+    break;
+    
+  case EP_TYPE_ISOC: 
+    hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+    break;
+      
+  }
+  
+  hhcd->hc[ch_num].xfer_buff = pbuff;
+  hhcd->hc[ch_num].xfer_len  = length;
+  hhcd->hc[ch_num].urb_state =   URB_IDLE;  
+  hhcd->hc[ch_num].xfer_count = 0 ;
+  hhcd->hc[ch_num].ch_num = ch_num;
+  hhcd->hc[ch_num].state = HC_IDLE;
+  
+  return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable);
+}
+
+/**
+  * @brief  This function handles HCD interrupt request.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  uint32_t i = 0 , interrupt = 0;
+  
+  /* ensure that we are in device mode */
+  if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
+  {
+    /* avoid spurious interrupt */
+    if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) 
+    {
+      return;
+    }
+    
+    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+    {
+     /* incorrect mode, acknowledge the interrupt */
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
+    }
+    
+    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
+    {
+     /* incorrect mode, acknowledge the interrupt */
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
+    }
+
+    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
+    {
+     /* incorrect mode, acknowledge the interrupt */
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
+    }   
+    
+    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
+    {
+     /* incorrect mode, acknowledge the interrupt */
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
+    }     
+    
+    /* Handle Host Disconnect Interrupts */
+    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
+    {
+      
+      /* Cleanup HPRT */
+      USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
+        USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+       
+      /* Handle Host Port Interrupts */
+      HAL_HCD_Disconnect_Callback(hhcd);
+       USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
+    }
+    
+    /* Handle Host Port Interrupts */
+    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
+    {
+      HCD_Port_IRQHandler (hhcd);
+    }
+    
+    /* Handle Host SOF Interrupts */
+    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
+    {
+      HAL_HCD_SOF_Callback(hhcd);
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
+    }
+          
+    /* Handle Host channel Interrupts */
+    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
+    {
+      
+      interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
+      for (i = 0; i < hhcd->Init.Host_channels ; i++)
+      {
+        if (interrupt & (1 << i))
+        {
+          if ((USBx_HC(i)->HCCHAR) &  USB_OTG_HCCHAR_EPDIR)
+          {
+            HCD_HC_IN_IRQHandler (hhcd, i);
+          }
+          else
+          {
+            HCD_HC_OUT_IRQHandler (hhcd, i);
+          }
+        }
+      }
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
+    } 
+    
+        /* Handle Rx Queue Level Interrupts */
+    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))
+    {
+      USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+      
+      HCD_RXQLVL_IRQHandler (hhcd);
+      
+      USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+    }
+    
+  }
+}
+
+/**
+  * @brief  SOF callback.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_HCD_SOF_Callback could be implenetd in the user file
+   */
+}
+
+/**
+  * @brief Connexion Event callback.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_HCD_Connect_Callback could be implenetd in the user file
+   */
+}
+
+/**
+  * @brief  Disonnexion Event callback.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_HCD_Disconnect_Callback could be implenetd in the user file
+   */
+} 
+
+/**
+  * @brief  Notify URB state change callback.
+  * @param  hhcd: HCD handle
+  * @param  chnum: Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @param  urb_state:
+  *          This parameter can be one of these values:
+  *            URB_IDLE/
+  *            URB_DONE/
+  *            URB_NOTREADY/
+  *            URB_NYET/ 
+  *            URB_ERROR/  
+  *            URB_STALL/    
+  * @retval None
+  */
+__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_HCD_HC_NotifyURBChange_Callback could be implenetd in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Group3 Peripheral Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the HCD data 
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the host driver
+  * @param  hhcd: HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
+{ 
+  __HAL_LOCK(hhcd); 
+  __HAL_HCD_ENABLE(hhcd);
+  USB_DriveVbus(hhcd->Instance, 1);  
+  __HAL_UNLOCK(hhcd); 
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the host driver
+  * @param  hhcd: HCD handle
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
+{ 
+  __HAL_LOCK(hhcd); 
+  USB_StopHost(hhcd->Instance);
+  __HAL_UNLOCK(hhcd); 
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reset the host port
+  * @param  hhcd: HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
+{
+  return (USB_ResetPort(hhcd->Instance));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Group4 Peripheral State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the HCD state
+  * @param  hhcd: HCD handle
+  * @retval HAL state
+  */
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
+{
+  return hhcd->State;
+}
+
+/**
+  * @brief  Return  URB state for a channel
+  * @param  hhcd: HCD handle
+  * @param  chnum: Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval URB state.
+  *          This parameter can be one of these values:
+  *            URB_IDLE/
+  *            URB_DONE/
+  *            URB_NOTREADY/
+  *            URB_NYET/ 
+  *            URB_ERROR/  
+  *            URB_STALL      
+  */
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+  return hhcd->hc[chnum].urb_state;
+}
+
+
+/**
+  * @brief  Return the last host transfer size
+  * @param  hhcd: HCD handle
+  * @param  chnum: Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval last transfer size in byte
+  */
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+  return hhcd->hc[chnum].xfer_count; 
+}
+  
+/**
+  * @brief  Return the Host Channel state
+  * @param  hhcd: HCD handle
+  * @param  chnum: Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval Host channel state
+  *          This parameter can be one of the these values:
+  *            HC_IDLE/
+  *            HC_XFRC/
+  *            HC_HALTED/
+  *            HC_NYET/ 
+  *            HC_NAK/  
+  *            HC_STALL/ 
+  *            HC_XACTERR/  
+  *            HC_BBLERR/  
+  *            HC_DATATGLERR/    
+  */
+HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+  return hhcd->hc[chnum].state;
+}
+
+/**
+  * @brief  Return the current Host frame number
+  * @param  hhcd: HCD handle
+  * @retval Current Host frame number
+  */
+uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
+{
+  return (USB_GetCurrentFrame(hhcd->Instance));
+}
+
+/**
+  * @brief  Return the Host enumeration speed
+  * @param  hhcd: HCD handle
+  * @retval Enumeration speed
+  */
+uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
+{
+  return (USB_GetHostSpeed(hhcd->Instance));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  This function handles Host Channel IN interrupt requests.
+  * @param  hhcd: HCD handle
+  * @param  chnum: Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval none
+  */
+static void HCD_HC_IN_IRQHandler   (HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+    
+  if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+  }  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_ACK)
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
+  }
+  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_STALL)  
+  {
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+    hhcd->hc[chnum].state = HC_STALL;
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);    
+    USB_HC_Halt(hhcd->Instance, chnum);    
+  }
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_DTERR)
+  {
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+    USB_HC_Halt(hhcd->Instance, chnum);  
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);    
+    hhcd->hc[chnum].state = HC_DATATGLERR;
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
+  }    
+  
+  if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_FRMOR)
+  {
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+    USB_HC_Halt(hhcd->Instance, chnum);  
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
+  }
+  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_XFRC)
+  {
+    
+    if (hhcd->Init.dma_enable)
+    {
+      hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \
+                               (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
+    }
+    
+    hhcd->hc[chnum].state = HC_XFRC;
+    hhcd->hc[chnum].ErrCnt = 0;
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
+    
+    
+    if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
+        (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+    {
+      __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+      USB_HC_Halt(hhcd->Instance, chnum); 
+      __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+      
+    }
+    else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+    {
+      USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
+      hhcd->hc[chnum].urb_state = URB_DONE; 
+      HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+    }
+    hhcd->hc[chnum].toggle_in ^= 1;
+    
+  }
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_CHH)
+  {
+    __HAL_HCD_MASK_HALT_HC_INT(chnum); 
+    
+    if(hhcd->hc[chnum].state == HC_XFRC)
+    {
+      hhcd->hc[chnum].urb_state  = URB_DONE;      
+    }
+    
+    else if (hhcd->hc[chnum].state == HC_STALL) 
+    {
+      hhcd->hc[chnum].urb_state  = URB_STALL;
+    }   
+    
+    else if((hhcd->hc[chnum].state == HC_XACTERR) ||
+            (hhcd->hc[chnum].state == HC_DATATGLERR))
+    {
+      if(hhcd->hc[chnum].ErrCnt++ > 3)
+      {      
+        hhcd->hc[chnum].ErrCnt = 0;
+        hhcd->hc[chnum].urb_state = URB_ERROR;
+      }
+      else
+      {
+        hhcd->hc[chnum].urb_state = URB_NOTREADY;
+      }
+      
+      /* re-activate the channel  */
+      USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;         
+      USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;      
+    }
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
+    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+  }  
+  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_TXERR)
+  {
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+     hhcd->hc[chnum].ErrCnt++;
+     hhcd->hc[chnum].state = HC_XACTERR;
+     USB_HC_Halt(hhcd->Instance, chnum);     
+     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+  }
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NAK)
+  {  
+    if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+    {
+      __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+      USB_HC_Halt(hhcd->Instance, chnum);  
+    }
+    else if  ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
+              (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+    {
+      /* re-activate the channel  */
+      USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;         
+      USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+   
+    }
+    hhcd->hc[chnum].state = HC_NAK;
+     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+  }
+}
+
+/**
+  * @brief  This function handles Host Channel OUT interrupt requests.
+  * @param  hhcd: HCD handle
+  * @param  chnum: Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval none
+  */
+static void HCD_HC_OUT_IRQHandler  (HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  
+  if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+  }  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_ACK)
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
+    
+    if( hhcd->hc[chnum].do_ping == 1)
+    {
+      hhcd->hc[chnum].state = HC_NYET;     
+      __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+      USB_HC_Halt(hhcd->Instance, chnum); 
+      hhcd->hc[chnum].urb_state  = URB_NOTREADY;
+    }
+  }
+  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NYET)
+  {
+    hhcd->hc[chnum].state = HC_NYET;
+    hhcd->hc[chnum].ErrCnt= 0;    
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+    USB_HC_Halt(hhcd->Instance, chnum);      
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
+    
+  }  
+  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_FRMOR)
+  {
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+    USB_HC_Halt(hhcd->Instance, chnum);  
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
+  }
+  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_XFRC)
+  {
+      hhcd->hc[chnum].ErrCnt = 0;  
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+    USB_HC_Halt(hhcd->Instance, chnum);   
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
+    hhcd->hc[chnum].state = HC_XFRC;
+
+  }  
+
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_STALL)  
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);  
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+    USB_HC_Halt(hhcd->Instance, chnum);   
+    hhcd->hc[chnum].state = HC_STALL;    
+  }
+
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NAK)
+  {  
+    hhcd->hc[chnum].ErrCnt = 0;  
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+    USB_HC_Halt(hhcd->Instance, chnum);   
+    hhcd->hc[chnum].state = HC_NAK;
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+  }
+
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_TXERR)
+  {
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+    USB_HC_Halt(hhcd->Instance, chnum);      
+    hhcd->hc[chnum].state = HC_XACTERR;  
+     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+  }
+  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_DTERR)
+  {
+    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
+    USB_HC_Halt(hhcd->Instance, chnum);      
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);    
+    hhcd->hc[chnum].state = HC_DATATGLERR;
+  }
+  
+  
+  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_CHH)
+  {
+    __HAL_HCD_MASK_HALT_HC_INT(chnum); 
+    
+    if(hhcd->hc[chnum].state == HC_XFRC)
+    {
+      hhcd->hc[chnum].urb_state  = URB_DONE;
+      if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)
+      {
+        hhcd->hc[chnum].toggle_out ^= 1; 
+      }      
+    }
+    else if (hhcd->hc[chnum].state == HC_NAK) 
+    {
+      hhcd->hc[chnum].urb_state  = URB_NOTREADY;
+    }  
+    
+    else if (hhcd->hc[chnum].state == HC_NYET) 
+    {
+      hhcd->hc[chnum].urb_state  = URB_NOTREADY;
+      hhcd->hc[chnum].do_ping = 0;
+    }   
+    
+    else if (hhcd->hc[chnum].state == HC_STALL) 
+    {
+      hhcd->hc[chnum].urb_state  = URB_STALL;
+    } 
+    
+    else if((hhcd->hc[chnum].state == HC_XACTERR) ||
+            (hhcd->hc[chnum].state == HC_DATATGLERR))
+    {
+      if(hhcd->hc[chnum].ErrCnt++ > 3)
+      {      
+        hhcd->hc[chnum].ErrCnt = 0;
+        hhcd->hc[chnum].urb_state = URB_ERROR;
+      }
+      else
+      {
+        hhcd->hc[chnum].urb_state = URB_NOTREADY;
+      }
+      
+      /* re-activate the channel  */
+      USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;         
+      USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;      
+    }
+    
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
+    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);  
+  }
+} 
+
+/**
+  * @brief  This function handles Rx Queue Level interrupt requests.
+  * @param  hhcd: HCD handle
+  * @retval none
+  */
+static void HCD_RXQLVL_IRQHandler  (HCD_HandleTypeDef *hhcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;  
+  uint8_t                       channelnum =0;  
+  uint32_t                      pktsts;
+  uint32_t                      pktcnt; 
+  uint32_t                      temp = 0;
+  
+  temp = hhcd->Instance->GRXSTSP ;
+  channelnum = temp &  USB_OTG_GRXSTSP_EPNUM;  
+  pktsts = (temp &  USB_OTG_GRXSTSP_PKTSTS) >> 17;
+  pktcnt = (temp &  USB_OTG_GRXSTSP_BCNT) >> 4;
+    
+  switch (pktsts)
+  {
+  case GRXSTS_PKTSTS_IN:
+    /* Read the data into the host buffer. */
+    if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void  *)0))
+    {  
+      
+      USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);
+     
+      /*manage multiple Xfer */
+      hhcd->hc[channelnum].xfer_buff += pktcnt;           
+      hhcd->hc[channelnum].xfer_count  += pktcnt;
+        
+      if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)
+      {
+        /* re-activate the channel when more packets are expected */
+        USBx_HC(channelnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS; 
+        USBx_HC(channelnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+        hhcd->hc[channelnum].toggle_in ^= 1;
+      }
+    }
+    break;
+
+  case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
+    break;
+  case GRXSTS_PKTSTS_IN_XFER_COMP:
+  case GRXSTS_PKTSTS_CH_HALTED:
+  default:
+    break;
+  }
+}
+
+/**
+  * @brief  This function handles Host Port interrupt requests.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+static void HCD_Port_IRQHandler  (HCD_HandleTypeDef *hhcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;  
+  __IO uint32_t hprt0, hprt0_dup;
+  
+  /* Handle Host Port Interrupts */
+  hprt0 = USBx_HPRT0;
+  hprt0_dup = USBx_HPRT0;
+  
+  hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
+                 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+  
+  /* Check wether Port Connect Detected */
+  if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
+  {  
+    if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
+    {
+      USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
+      HAL_HCD_Connect_Callback(hhcd);
+    }
+    hprt0_dup  |= USB_OTG_HPRT_PCDET;
+    
+  }
+  
+  /* Check whether Port Enable Changed */
+  if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
+  {
+    hprt0_dup |= USB_OTG_HPRT_PENCHNG;
+    
+    if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
+    {    
+      if(hhcd->Init.phy_itface  == USB_OTG_EMBEDDED_PHY)
+      {
+        if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
+        {
+          USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ );
+        }
+        else
+        {
+          USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
+        }
+      }
+      else
+      {
+        if(hhcd->Init.speed == HCD_SPEED_FULL)
+        {
+          USBx_HOST->HFIR = (uint32_t)60000;
+        }
+      }
+      HAL_HCD_Connect_Callback(hhcd);
+      
+      if(hhcd->Init.speed == HCD_SPEED_HIGH)
+      {
+        USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); 
+      }
+    }
+    else
+    {
+      /* Cleanup HPRT */
+      USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
+        USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+      
+      USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); 
+    }    
+  }
+  
+  /* Check For an overcurrent */
+  if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
+  {
+    hprt0_dup |= USB_OTG_HPRT_POCCHNG;
+  }
+
+  /* Clear Port Interrupts */
+  USBx_HPRT0 = hprt0_dup;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_HCD_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_hcd.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,228 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_hcd.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of HCD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_HCD_H
+#define __STM32F4xx_HAL_HCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_usb.h"
+   
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HCD
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+   /** 
+  * @brief  HCD Status structures structure definition  
+  */  
+typedef enum 
+{
+  HCD_READY    = 0x00,
+  HCD_ERROR    = 0x01,
+  HCD_BUSY     = 0x02,
+  HCD_TIMEOUT  = 0x03
+} HCD_StateTypeDef;
+
+typedef USB_OTG_GlobalTypeDef   HCD_TypeDef;
+typedef USB_OTG_CfgTypeDef      HCD_InitTypeDef;
+typedef USB_OTG_HCTypeDef       HCD_HCTypeDef ;   
+typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
+typedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef ;
+
+/** 
+  * @brief  HCD Handle Structure definition  
+  */ 
+typedef struct
+{
+  HCD_TypeDef               *Instance;  /*!< Register base address    */ 
+  HCD_InitTypeDef           Init;       /*!< HCD required parameters  */
+  HCD_HCTypeDef             hc[15];     /*!< Host channels parameters */
+  HAL_LockTypeDef           Lock;       /*!< HCD peripheral status    */
+  __IO HCD_StateTypeDef     State;      /*!< HCD communication state  */
+  void                      *pData;     /*!< Pointer Stack Handler    */    
+  
+} HCD_HandleTypeDef;
+  
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Constants
+  * @{
+  */
+
+/** @defgroup HCD_Instance_definition 
+  * @{
+  */ 
+   
+#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) |= (__INTERRUPT__))
+#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)   
+
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                        ((INSTANCE) == USB_OTG_HS))
+#elif defined(STM32F401xC) || defined(STM32F401xE)
+ #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Speed
+  * @{
+  */
+#define HCD_SPEED_HIGH               0
+#define HCD_SPEED_LOW                2  
+#define HCD_SPEED_FULL               3
+
+/**
+  * @}
+  */
+  
+  /** @defgroup HCD_PHY_Module
+  * @{
+  */
+#define HCD_PHY_ULPI                 1
+#define HCD_PHY_EMBEDDED             2
+/**
+  * @}
+  */
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup HCD_Interrupt_Clock
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_HCD_ENABLE(__HANDLE__)                   USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_HCD_DISABLE(__HANDLE__)                  USB_DisableGlobalInt ((__HANDLE__)->Instance)
+   
+#define __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) |= (__INTERRUPT__))
+#define __HAL_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)   
+   
+   
+#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)  (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) 
+#define __HAL_HCD_MASK_HALT_HC_INT(chnum)             (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) 
+#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)           (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) 
+#define __HAL_HCD_MASK_ACK_HC_INT(chnum)              (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) 
+#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)            (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) 
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef      HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef      HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef      HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,  
+                                  uint8_t ch_num,
+                                  uint8_t epnum,
+                                  uint8_t dev_address,
+                                  uint8_t speed,
+                                  uint8_t ep_type,
+                                  uint16_t mps);
+
+HAL_StatusTypeDef       HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,  
+                                  uint8_t ch_num);
+
+void            HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void            HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+
+/* I/O operation functions  *****************************************************/
+HAL_StatusTypeDef       HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+                                                 uint8_t pipe, 
+                                                 uint8_t direction ,
+                                                 uint8_t ep_type,  
+                                                 uint8_t token, 
+                                                 uint8_t* pbuff, 
+                                                 uint16_t length,
+                                                 uint8_t do_ping);
+
+ /* Non-Blocking mode: Interrupt */
+void                    HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void             HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void             HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void             HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void             HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, 
+                                                            uint8_t chnum, 
+                                                            HCD_URBStateTypeDef urb_state);
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef       HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef       HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef       HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+
+/* Peripheral State functions  **************************************************/
+HCD_StateTypeDef        HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
+HCD_URBStateTypeDef     HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t                HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+HCD_HCStateTypeDef      HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t                HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
+uint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_HCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,3746 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_i2c.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   I2C HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    The I2C HAL driver can be used as follows:
+
+    (#) Declare a I2C_HandleTypeDef handle structure, for example:
+        I2C_HandleTypeDef  hi2c;
+
+    (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit() API:
+        (##) Enable the I2Cx interface clock
+        (##) I2C pins configuration
+            (+++) Enable the clock for the I2C GPIOs
+            (+++) Configure I2C pins as alternate function open-drain
+        (##) NVIC configuration if you need to use interrupt process
+            (+++) Configure the I2Cx interrupt priority
+            (+++) Enable the NVIC I2C IRQ Channel
+        (##) DMA Configuration if you need to use DMA process
+            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
+            (+++) Enable the DMAx interface clock using
+            (+++) Configure the DMA handle parameters
+            (+++) Configure the DMA Tx or Rx Stream
+            (+++) Associate the initilalized DMA handle to the hi2c DMA Tx or Rx handle
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on 
+                  the DMA Tx or Rx Stream
+
+    (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
+        Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
+
+    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware 
+        (GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API.
+
+    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
+
+    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
+
+    *** Polling mode IO operation ***
+    =================================
+    [..]
+      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
+      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
+      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
+      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
+
+    *** Polling mode IO MEM operation ***
+    =====================================
+    [..]
+      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
+      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
+
+
+    *** Interrupt mode IO operation ***
+    ===================================
+    [..]
+      (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
+      (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
+      (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
+      (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
+      (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
+      (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
+           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
+      (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
+      (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
+           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer HAL_I2C_ErrorCallback
+
+    *** Interrupt mode IO MEM operation ***
+    =======================================
+    [..]
+      (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
+          HAL_I2C_Mem_Write_IT()
+      (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
+      (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
+          HAL_I2C_Mem_Read_IT()
+      (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer HAL_I2C_ErrorCallback
+
+    *** DMA mode IO operation ***
+    ==============================
+    [..]
+      (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
+          HAL_I2C_Master_Transmit_DMA()
+      (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
+      (+) Receive in master mode an amount of data in non blocking mode (DMA) using
+          HAL_I2C_Master_Receive_DMA()
+      (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
+      (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
+          HAL_I2C_Slave_Transmit_DMA()
+      (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
+           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
+      (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
+          HAL_I2C_Slave_Receive_DMA()
+      (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
+           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer HAL_I2C_ErrorCallback
+
+    *** DMA mode IO MEM operation ***
+    =================================
+    [..]
+      (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
+          HAL_I2C_Mem_Write_DMA()
+      (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
+      (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
+          HAL_I2C_Mem_Read_DMA()
+      (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer HAL_I2C_ErrorCallback
+
+
+     *** I2C HAL driver macros list ***
+     ==================================
+     [..]
+       Below the list of most used macros in I2C HAL driver.
+
+      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
+      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
+      (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
+      (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
+      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+     [..]
+       (@) You can refer to the I2C HAL driver header file for more useful macros
+
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2C
+  * @brief I2C HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define I2C_TIMEOUT_FLAG          ((uint32_t)35)     /* 35 ms */
+#define I2C_TIMEOUT_ADDR_SLAVE    ((uint32_t)10000)  /* 10 s  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+
+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout);
+
+static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
+
+static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions
+  * @{
+  */
+
+/** @defgroup I2C_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          de-initialiaze the I2Cx peripheral:
+
+      (+) User must Implement HAL_I2C_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
+
+      (+) Call the function HAL_I2C_Init() to configure the selected device with
+          the selected configuration:
+        (++) Communication Speed
+        (++) Duty cycle
+        (++) Addressing mode
+        (++) Own Address 1
+        (++) Dual Addressing mode
+        (++) Own Address 2
+        (++) General call mode
+        (++) Nostretch mode
+
+      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+          of the selected I2Cx periperal.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the I2C according to the specified parameters
+  *         in the I2C_InitTypeDef and create the associated handle.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t freqrange = 0;
+  uint32_t pclk1 = 0;
+
+  /* Check the I2C handle allocation */
+  if(hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
+  assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
+  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+  if(hi2c->State == HAL_I2C_STATE_RESET)
+  {
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_I2C_MspInit(hi2c);
+  }
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disble the selected I2C peripheral */
+  __HAL_I2C_DISABLE(hi2c);
+
+  /* Get PCLK1 frequency */
+  pclk1 = HAL_RCC_GetPCLK1Freq();
+
+  /* Calculate frequency range */
+  freqrange = __HAL_I2C_FREQRANGE(pclk1);
+
+  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+  /* Configure I2Cx: Frequency range */
+  hi2c->Instance->CR2 = freqrange;
+
+  /*---------------------------- I2Cx TRISE Configuration --------------------*/
+  /* Configure I2Cx: Rise Time */
+  hi2c->Instance->TRISE = __HAL_I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
+
+  /*---------------------------- I2Cx CCR Configuration ----------------------*/
+  /* Configure I2Cx: Speed */
+  hi2c->Instance->CCR = __HAL_I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
+
+  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+  /* Configure I2Cx: Generalcall and NoStretch mode */
+  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+
+  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+  /* Configure I2Cx: Own Address1 and addressing mode */
+  hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1);
+
+  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+  /* Configure I2Cx: Dual mode and Own Address2 */
+  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2);
+
+  /* Enable the selected I2C peripheral */
+  __HAL_I2C_ENABLE(hi2c);
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+  hi2c->State = HAL_I2C_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the I2C peripheral.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the I2C handle allocation */
+  if(hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the I2C Peripheral Clock */
+  __HAL_I2C_DISABLE(hi2c);
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_I2C_MspDeInit(hi2c);
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+  hi2c->State = HAL_I2C_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief I2C MSP Init.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+ __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2C_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief I2C MSP DeInit
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2C_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Group2 IO operation functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the I2C data
+    transfers.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode : The communication is performed in the polling mode.
+            The status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) No-Blocking mode : The communication is performed using Interrupts
+            or DMA. These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the
+            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+            using DMA mode.
+
+    (#) Blocking mode functions are :
+        (++) HAL_I2C_Master_Transmit()
+        (++) HAL_I2C_Master_Receive()
+        (++) HAL_I2C_Slave_Transmit()
+        (++) HAL_I2C_Slave_Receive()
+        (++) HAL_I2C_Mem_Write()
+        (++) HAL_I2C_Mem_Read()
+        (++) HAL_I2C_IsDeviceReady()
+
+    (#) No-Blocking mode functions with Interrupt are :
+        (++) HAL_I2C_Master_Transmit_IT()
+        (++) HAL_I2C_Master_Receive_IT()
+        (++) HAL_I2C_Slave_Transmit_IT()
+        (++) HAL_I2C_Slave_Receive_IT()
+        (++) HAL_I2C_Mem_Write_IT()
+        (++) HAL_I2C_Mem_Read_IT()
+
+    (#) No-Blocking mode functions with DMA are :
+        (++) HAL_I2C_Master_Transmit_DMA()
+        (++) HAL_I2C_Master_Receive_DMA()
+        (++) HAL_I2C_Slave_Transmit_DMA()
+        (++) HAL_I2C_Slave_Receive_DMA()
+        (++) HAL_I2C_Mem_Write_DMA()
+        (++) HAL_I2C_Mem_Read_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_I2C_MemTxCpltCallback()
+        (++) HAL_I2C_MemRxCpltCallback()
+        (++) HAL_I2C_MasterTxCpltCallback()
+        (++) HAL_I2C_MasterRxCpltCallback()
+        (++) HAL_I2C_SlaveTxCpltCallback()
+        (++) HAL_I2C_SlaveRxCpltCallback()
+        (++) HAL_I2C_ErrorCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits in master mode an amount of data in blocking mode.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress: Target device address
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY_TX;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Send Slave Address */
+    if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+    while(Size > 0)
+    {
+      /* Wait until TXE flag is set */
+      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+
+      /* Write data to DR */
+      hi2c->Instance->DR = (*pData++);
+      Size--;
+
+      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
+      {
+        /* Write data to DR */
+        hi2c->Instance->DR = (*pData++);
+        Size--;
+      }
+    }
+
+    /* Wait until TXE flag is set */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Generate Stop */
+    hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+    /* Wait until BUSY flag is reset */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives in master mode an amount of data in blocking mode.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress: Target device address
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY_RX;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Send Slave Address */
+    if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+
+    if(Size == 1)
+    {
+      /* Disable Acknowledge */
+      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Generate Stop */
+      hi2c->Instance->CR1 |= I2C_CR1_STOP;
+    }
+    else if(Size == 2)
+    {
+      /* Disable Acknowledge */
+      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+      /* Enable Pos */
+      hi2c->Instance->CR1 |= I2C_CR1_POS;
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+    else
+    {
+      /* Enable Acknowledge */
+      hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+
+    while(Size > 0)
+    {
+      if(Size <= 3)
+      {
+        /* One byte */
+        if(Size == 1)
+        {
+          /* Wait until RXNE flag is set */
+          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+          {
+            return HAL_TIMEOUT;
+          }
+
+          /* Read data from DR */
+          (*pData++) = hi2c->Instance->DR;
+          Size--;
+        }
+        /* Two bytes */
+        else if(Size == 2)
+        {
+          /* Wait until BTF flag is set */
+          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+          {
+            return HAL_TIMEOUT;
+          }
+
+          /* Generate Stop */
+          hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+          /* Read data from DR */
+          (*pData++) = hi2c->Instance->DR;
+          Size--;
+
+          /* Read data from DR */
+          (*pData++) = hi2c->Instance->DR;
+          Size--;
+        }
+        /* 3 Last bytes */
+        else
+        {
+          /* Wait until BTF flag is set */
+          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+          {
+            return HAL_TIMEOUT;
+          }
+
+          /* Disable Acknowledge */
+          hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+          /* Read data from DR */
+          (*pData++) = hi2c->Instance->DR;
+          Size--;
+
+          /* Wait until BTF flag is set */
+          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+          {
+            return HAL_TIMEOUT;
+          }
+
+          /* Generate Stop */
+          hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+          /* Read data from DR */
+          (*pData++) = hi2c->Instance->DR;
+          Size--;
+
+          /* Read data from DR */
+          (*pData++) = hi2c->Instance->DR;
+          Size--;
+        }
+      }
+      else
+      {
+        /* Wait until RXNE flag is set */
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+
+        /* Read data from DR */
+        (*pData++) = hi2c->Instance->DR;
+        Size--;
+
+        if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+        {
+          /* Read data from DR */
+          (*pData++) = hi2c->Instance->DR;
+          Size--;
+        }
+      }
+    }
+
+    /* Disable Pos */
+    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+    /* Wait until BUSY flag is reset */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmits in slave mode an amount of data in blocking mode.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY_TX;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+    /* Wait until ADDR flag is set */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+    /* If 10bit addressing mode is selected */
+    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    {
+      /* Wait until ADDR flag is set */
+      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+
+    while(Size > 0)
+    {
+      /* Wait until TXE flag is set */
+      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+
+      /* Write data to DR */
+      hi2c->Instance->DR = (*pData++);
+      Size--;
+
+      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
+      {
+        /* Write data to DR */
+        hi2c->Instance->DR = (*pData++);
+        Size--;
+      }
+    }
+
+    /* Wait until AF flag is set */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Clear AF flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Disable Address Acknowledge */
+    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+    /* Wait until BUSY flag is reset */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in blocking mode
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY_RX;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+    /* Wait until ADDR flag is set */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+    while(Size > 0)
+    {
+      /* Wait until RXNE flag is set */
+      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+
+      /* Read data from DR */
+      (*pData++) = hi2c->Instance->DR;
+      Size--;
+
+      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
+      {
+        /* Read data from DR */
+        (*pData++) = hi2c->Instance->DR;
+        Size--;
+      }
+    }
+
+    /* Wait until STOP flag is set */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Clear STOP flag */
+    __HAL_I2C_CLEAR_STOPFLAG(hi2c);
+
+    /* Disable Address Acknowledge */
+    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+    /* Wait until BUSY flag is reset */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in no-blocking mode with Interrupt
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress: Target device address
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY_TX;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    hi2c->pBuffPtr = pData;
+    hi2c->XferSize = Size;
+    hi2c->XferCount = Size;
+
+    /* Send Slave Address */
+    if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable EVT, BUF and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in no-blocking mode with Interrupt
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress: Target device address
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY_RX;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    hi2c->pBuffPtr = pData;
+    hi2c->XferSize = Size;
+    hi2c->XferCount = Size;
+
+    /* Send Slave Address */
+    if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+
+    if(hi2c->XferCount == 1)
+    {
+      /* Disable Acknowledge */
+      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Generate Stop */
+      hi2c->Instance->CR1 |= I2C_CR1_STOP;
+    }
+    else if(hi2c->XferCount == 2)
+    {
+      /* Disable Acknowledge */
+      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+      /* Enable Pos */
+      hi2c->Instance->CR1 |= I2C_CR1_POS;
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+    else
+    {
+      /* Enable Acknowledge */
+      hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable EVT, BUF and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in no-blocking mode with Interrupt
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY_TX;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    hi2c->pBuffPtr = pData;
+    hi2c->XferSize = Size;
+    hi2c->XferCount = Size;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable EVT, BUF and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in no-blocking mode with Interrupt
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY_RX;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    hi2c->pBuffPtr = pData;
+    hi2c->XferSize = Size;
+    hi2c->XferCount = Size;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable EVT, BUF and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in no-blocking mode with DMA
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress: Target device address
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY_TX;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    hi2c->pBuffPtr = pData;
+    hi2c->XferSize = Size;
+    hi2c->XferCount = Size;
+
+    /* Set the I2C DMA transfert complete callback */
+    hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+    /* Set the DMA error callback */
+    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+    /* Enable the DMA Stream */
+    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
+
+    /* Send Slave Address */
+    if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in no-blocking mode with DMA
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress: Target device address
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY_RX;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    hi2c->pBuffPtr = pData;
+    hi2c->XferSize = Size;
+    hi2c->XferCount = Size;
+
+    /* Set the I2C DMA transfert complete callback */
+    hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+    /* Set the DMA error callback */
+    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+    /* Enable the DMA Stream */
+    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
+
+    /* Send Slave Address */
+    if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+
+    if(Size == 1)
+    {
+      /* Disable Acknowledge */
+      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+    }
+    else
+    {
+      /* Enable Last DMA bit */
+      hi2c->Instance->CR2 |= I2C_CR2_LAST;
+    }
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in no-blocking mode with DMA
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY_TX;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    hi2c->pBuffPtr = pData;
+    hi2c->XferSize = Size;
+    hi2c->XferCount = Size;
+
+    /* Set the I2C DMA transfert complete callback */
+    hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+    /* Set the DMA error callback */
+    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+    /* Enable the DMA Stream */
+    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+    /* Wait until ADDR flag is set */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* If 7bit addressing mode is selected */
+    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+    {
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+    else
+    {
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Wait until ADDR flag is set */
+      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in no-blocking mode with DMA
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY_RX;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    hi2c->pBuffPtr = pData;
+    hi2c->XferSize = Size;
+    hi2c->XferCount = Size;
+
+    /* Set the I2C DMA transfert complete callback */
+    hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+    /* Set the DMA error callback */
+    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+    /* Enable the DMA Stream */
+    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+    /* Wait until ADDR flag is set */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in blocking mode to a specific memory address
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress: Target device address
+  * @param  MemAddress: Internal memory address
+  * @param  MemAddSize: Size of internal memory address
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Send Slave Address and Memory Address */
+    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+
+    while(Size > 0)
+    {
+      /* Wait until TXE flag is set */
+      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+
+      /* Write data to DR */
+      hi2c->Instance->DR = (*pData++);
+      Size--;
+
+      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
+      {
+        /* Write data to DR */
+        hi2c->Instance->DR = (*pData++);
+        Size--;
+      }
+    }
+
+    /* Wait until TXE flag is set */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Generate Stop */
+    hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+    /* Wait until BUSY flag is reset */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in blocking mode from a specific memory address
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress: Target device address
+  * @param  MemAddress: Internal memory address
+  * @param  MemAddSize: Size of internal memory address
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Send Slave Address and Memory Address */
+    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+
+    if(Size == 1)
+    {
+      /* Disable Acknowledge */
+      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Generate Stop */
+      hi2c->Instance->CR1 |= I2C_CR1_STOP;
+    }
+    else if(Size == 2)
+    {
+      /* Disable Acknowledge */
+      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+      /* Enable Pos */
+      hi2c->Instance->CR1 |= I2C_CR1_POS;
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+    else
+    {
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+
+    while(Size > 0)
+    {
+      if(Size <= 3)
+      {
+        /* One byte */
+        if(Size== 1)
+        {
+          /* Wait until RXNE flag is set */
+          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+          {
+            return HAL_TIMEOUT;
+          }
+
+          /* Read data from DR */
+          (*pData++) = hi2c->Instance->DR;
+          Size--;
+        }
+        /* Two bytes */
+        else if(Size == 2)
+        {
+          /* Wait until BTF flag is set */
+          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+          {
+            return HAL_TIMEOUT;
+          }
+
+          /* Generate Stop */
+          hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+          /* Read data from DR */
+          (*pData++) = hi2c->Instance->DR;
+          Size--;
+
+          /* Read data from DR */
+          (*pData++) = hi2c->Instance->DR;
+          Size--;
+        }
+        /* 3 Last bytes */
+        else
+        {
+          /* Wait until BTF flag is set */
+          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+          {
+            return HAL_TIMEOUT;
+          }
+
+          /* Disable Acknowledge */
+          hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+          /* Read data from DR */
+          (*pData++) = hi2c->Instance->DR;
+          Size--;
+
+          /* Wait until BTF flag is set */
+          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+          {
+            return HAL_TIMEOUT;
+          }
+
+          /* Generate Stop */
+          hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+          /* Read data from DR */
+          (*pData++) = hi2c->Instance->DR;
+          Size--;
+
+          /* Read data from DR */
+          (*pData++) = hi2c->Instance->DR;
+          Size--;
+        }
+      }
+      else
+      {
+        /* Wait until RXNE flag is set */
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+
+        /* Read data from DR */
+        (*pData++) = hi2c->Instance->DR;
+        Size--;
+
+        if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+        {
+          /* Read data from DR */
+          (*pData++) = hi2c->Instance->DR;
+          Size--;
+        }
+      }
+    }
+
+    /* Disable Pos */
+    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+    /* Wait until BUSY flag is reset */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in no-blocking mode with Interrupt to a specific memory address
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress: Target device address
+  * @param  MemAddress: Internal memory address
+  * @param  MemAddSize: Size of internal memory address
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    hi2c->pBuffPtr = pData;
+    hi2c->XferSize = Size;
+    hi2c->XferCount = Size;
+
+    /* Send Slave Address and Memory Address */
+    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable EVT, BUF and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in no-blocking mode with Interrupt from a specific memory address
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress: Target device address
+  * @param  MemAddress: Internal memory address
+  * @param  MemAddSize: Size of internal memory address
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    hi2c->pBuffPtr = pData;
+    hi2c->XferSize = Size;
+    hi2c->XferCount = Size;
+
+    /* Send Slave Address and Memory Address */
+    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+
+    if(hi2c->XferCount == 1)
+    {
+      /* Disable Acknowledge */
+      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Generate Stop */
+      hi2c->Instance->CR1 |= I2C_CR1_STOP;
+    }
+    else if(hi2c->XferCount == 2)
+    {
+      /* Disable Acknowledge */
+      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+      /* Enable Pos */
+      hi2c->Instance->CR1 |= I2C_CR1_POS;
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+    else
+    {
+      /* Enable Acknowledge */
+      hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable EVT, BUF and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in no-blocking mode with DMA to a specific memory address
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress: Target device address
+  * @param  MemAddress: Internal memory address
+  * @param  MemAddSize: Size of internal memory address
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    hi2c->pBuffPtr = pData;
+    hi2c->XferSize = Size;
+    hi2c->XferCount = Size;
+
+    /* Set the I2C DMA transfert complete callback */
+    hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt;
+
+    /* Set the DMA error callback */
+    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+    /* Enable the DMA Stream */
+    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
+
+    /* Send Slave Address and Memory Address */
+    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Reads an amount of data in no-blocking mode with DMA from a specific memory address.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress: Target device address
+  * @param  MemAddress: Internal memory address
+  * @param  MemAddSize: Size of internal memory address
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    hi2c->pBuffPtr = pData;
+    hi2c->XferSize = Size;
+    hi2c->XferCount = Size;
+
+    /* Set the I2C DMA transfert complete callback */
+    hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt;
+
+    /* Set the DMA error callback */
+    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+    /* Enable the DMA Stream */
+    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
+
+    /* Send Slave Address and Memory Address */
+    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_TIMEOUT;
+      }
+    }
+
+    if(Size == 1)
+    {
+      /* Disable Acknowledge */
+      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+    }
+    else
+    {
+      /* Enable Last DMA bit */
+      hi2c->Instance->CR2 |= I2C_CR2_LAST;
+    }
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Checks if target device is ready for communication.
+  * @note   This function is used with Memory devices
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress: Target device address
+  * @param  Trials: Number of trials
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+  uint32_t timeout = 0, tmp1 = 0, tmp2 = 0, tmp3 = 0, I2C_Trials = 1;
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    do
+    {
+      /* Generate Start */
+      hi2c->Instance->CR1 |= I2C_CR1_START;
+
+      /* Wait until SB flag is set */
+      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+
+      /* Send slave address */
+      hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_WRITE(DevAddress);
+
+      /* Wait until ADDR or AF flag are set */
+      timeout = HAL_GetTick() + Timeout;
+
+      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+      tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+      tmp3 = hi2c->State;
+      while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT))
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          hi2c->State = HAL_I2C_STATE_TIMEOUT;
+        }
+        tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+        tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+        tmp3 = hi2c->State;
+      }
+
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      /* Check if the ADDR flag has been set */
+      if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
+      {
+        /* Generate Stop */
+        hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+        /* Clear ADDR Flag */
+        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+        /* Wait until BUSY flag is reset */
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+
+        hi2c->State = HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_OK;
+      }
+      else
+      {
+        /* Generate Stop */
+        hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+        /* Clear AF Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Wait until BUSY flag is reset */
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }while(I2C_Trials++ < Trials);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  This function handles I2C event interrupt request.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL status
+  */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0, tmp4 = 0;
+  /* Master mode selected */
+  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_MSL) == SET)
+  {
+    /* I2C in mode Transmitter -----------------------------------------------*/
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == SET)
+    {
+      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE);
+      tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
+      tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
+      tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
+      /* TXE set and BTF reset -----------------------------------------------*/
+      if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
+      {
+        I2C_MasterTransmit_TXE(hi2c);
+      }
+      /* BTF set -------------------------------------------------------------*/
+      else if((tmp3 == SET) && (tmp4 == SET))
+      {
+        I2C_MasterTransmit_BTF(hi2c);
+      }
+    }
+    /* I2C in mode Receiver --------------------------------------------------*/
+    else
+    {
+      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE);
+      tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
+      tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
+      tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
+      /* RXNE set and BTF reset -----------------------------------------------*/
+      if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
+      {
+        I2C_MasterReceive_RXNE(hi2c);
+      }
+      /* BTF set -------------------------------------------------------------*/
+      else if((tmp3 == SET) && (tmp4 == SET))
+      {
+        I2C_MasterReceive_BTF(hi2c);
+      }
+    }
+  }
+  /* Slave mode selected */
+  else
+  {
+    tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+    tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_EVT));
+    tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+    tmp4 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA);
+    /* ADDR set --------------------------------------------------------------*/
+    if((tmp1 == SET) && (tmp2 == SET))
+    {
+      I2C_Slave_ADDR(hi2c);
+    }
+    /* STOPF set --------------------------------------------------------------*/
+    else if((tmp3 == SET) && (tmp2 == SET))
+    {
+      I2C_Slave_STOPF(hi2c);
+    }
+    /* I2C in mode Transmitter -----------------------------------------------*/
+    else if(tmp4 == SET)
+    {
+      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE);
+      tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
+      tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
+      tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
+      /* TXE set and BTF reset -----------------------------------------------*/
+      if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
+      {
+        I2C_SlaveTransmit_TXE(hi2c);
+      }
+      /* BTF set -------------------------------------------------------------*/
+      else if((tmp3 == SET) && (tmp4 == SET))
+      {
+        I2C_SlaveTransmit_BTF(hi2c);
+      }
+    }
+    /* I2C in mode Receiver --------------------------------------------------*/
+    else
+    {
+      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE);
+      tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
+      tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
+      tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
+      /* RXNE set and BTF reset ----------------------------------------------*/
+      if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
+      {
+        I2C_SlaveReceive_RXNE(hi2c);
+      }
+      /* BTF set -------------------------------------------------------------*/
+      else if((tmp3 == SET) && (tmp4 == SET))
+      {
+        I2C_SlaveReceive_BTF(hi2c);
+      }
+    }
+  }
+}
+
+/**
+  * @brief  This function handles I2C error interrupt request.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL status
+  */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
+
+  tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR);
+  tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
+  /* I2C Bus error interrupt occurred ----------------------------------------*/
+  if((tmp1 == SET) && (tmp2 == SET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+
+    /* Clear BERR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+  }
+
+  tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO);
+  tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
+  /* I2C Arbitration Loss error interrupt occurred ---------------------------*/
+  if((tmp1 == SET) && (tmp2 == SET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+  }
+
+  tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+  tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
+  /* I2C Acknowledge failure error interrupt occurred ------------------------*/
+  if((tmp1 == SET) && (tmp2 == SET))
+  {
+    tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_MSL);
+    tmp2 = hi2c->XferCount;
+    tmp3 = hi2c->State;
+    if((tmp1 == RESET) && (tmp2 == 0) && (tmp3 == HAL_I2C_STATE_BUSY_TX))
+    {
+      I2C_Slave_AF(hi2c);
+    }
+    else
+    {
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+      /* Clear AF flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+    }
+  }
+
+  tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR);
+  tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
+  /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
+  if((tmp1 == SET) && (tmp2 == SET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+    /* Clear OVR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+  }
+
+  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    
+    HAL_I2C_ErrorCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  Master Tx Transfer completed callbacks.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+ __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2C_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Master Rx Transfer completed callbacks.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2C_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/** @brief  Slave Tx Transfer completed callbacks.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+ __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2C_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Rx Transfer completed callbacks.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2C_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Tx Transfer completed callbacks.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+ __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2C_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Rx Transfer completed callbacks.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2C_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C error callbacks.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+ __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2C_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Group3 Peripheral State and Errors functions
+ *  @brief   Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the I2C state.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL state
+  */
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->State;
+}
+
+/**
+  * @brief  Return the I2C error code
+  * @param  hi2c : pointer to a I2C_HandleTypeDef structure that contains
+  *              the configuration information for the specified I2C.
+* @retval I2C Error Code
+*/
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Handle TXE flag for Master
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
+{
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  /* Write data to DR */
+  hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+  hi2c->XferCount--;
+
+  if(hi2c->XferCount == 0)
+  {
+    /* Disable BUF interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle BTF flag for Master transmitter
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
+{
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if(hi2c->XferCount != 0)
+  {
+    /* Write data to DR */
+    hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+    hi2c->XferCount--;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+  }
+  else
+  {
+    /* Disable EVT, BUF and ERR interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    /* Generate Stop */
+    hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+    /* Wait until BUSY flag is reset */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
+    {
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      HAL_I2C_MemTxCpltCallback(hi2c);
+    }
+    else
+    {
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      HAL_I2C_MasterTxCpltCallback(hi2c);
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle RXNE flag for Master
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t tmp = 0;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  tmp = hi2c->XferCount;
+  if(tmp > 3)
+  {
+    /* Read data from DR */
+    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+    hi2c->XferCount--;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+  }
+  else if((tmp == 2) || (tmp == 3))
+  {
+    /* Disable BUF interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+  }
+  else
+  {
+    /* Disable EVT, BUF and ERR interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    /* Read data from DR */
+    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+    hi2c->XferCount--;
+
+    /* Wait until BUSY flag is reset */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
+    {
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      HAL_I2C_MemRxCpltCallback(hi2c);
+    }
+    else
+    {
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      HAL_I2C_MasterRxCpltCallback(hi2c);
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle BTF flag for Master receiver
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
+{
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if(hi2c->XferCount == 3)
+  {
+    /* Disable Acknowledge */
+    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+    /* Read data from DR */
+    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+    hi2c->XferCount--;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+  }
+  else if(hi2c->XferCount == 2)
+  {
+    /* Generate Stop */
+    hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+    /* Read data from DR */
+    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+    hi2c->XferCount--;
+
+    /* Read data from DR */
+    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+    hi2c->XferCount--;
+
+    /* Disable EVT and ERR interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+    /* Wait until BUSY flag is reset */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
+    {
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      HAL_I2C_MemRxCpltCallback(hi2c);
+    }
+    else
+    {
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      HAL_I2C_MasterRxCpltCallback(hi2c);
+    }
+  }
+  else
+  {
+    /* Read data from DR */
+    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+    hi2c->XferCount--;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle TXE flag for Slave
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
+{
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+    if(hi2c->XferCount != 0)
+  {
+    /* Write data to DR */
+    hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+    hi2c->XferCount--;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle BTF flag for Slave transmitter
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
+{
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+    if(hi2c->XferCount != 0)
+  {
+    /* Write data to DR */
+    hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+    hi2c->XferCount--;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle RXNE flag for Slave
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
+{
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+    if(hi2c->XferCount != 0)
+  {
+    /* Read data from DR */
+    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+    hi2c->XferCount--;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle BTF flag for Slave receiver
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
+{
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+    if(hi2c->XferCount != 0)
+  {
+    /* Read data from DR */
+    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+    hi2c->XferCount--;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle ADD flag for Slave
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
+{
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  /* Clear ADDR flag */
+  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle STOPF flag for Slave
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
+{
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  /* Disable EVT, BUF and ERR interrupt */
+  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+  /* Clear STOPF flag */
+  __HAL_I2C_CLEAR_STOPFLAG(hi2c);
+
+  /* Disable Acknowledge */
+  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+  /* Wait until BUSY flag is reset */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  hi2c->State = HAL_I2C_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  HAL_I2C_SlaveRxCpltCallback(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
+{
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  /* Disable EVT, BUF and ERR interrupt */
+  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+  /* Clear AF flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+  /* Disable Acknowledge */
+  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+  /* Wait until BUSY flag is reset */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  hi2c->State = HAL_I2C_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  HAL_I2C_SlaveTxCpltCallback(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress: Target device address
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
+{
+  /* Generate Start */
+  hi2c->Instance->CR1 |= I2C_CR1_START;
+
+  /* Wait until SB flag is set */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+  {
+    /* Send slave address */
+    hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_WRITE(DevAddress);
+  }
+  else
+  {
+    /* Send header of slave address */
+    hi2c->Instance->DR = __HAL_I2C_10BIT_HEADER_WRITE(DevAddress);
+
+    /* Wait until ADD10 flag is set */
+    if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Send slave address */
+    hi2c->Instance->DR = __HAL_I2C_10BIT_ADDRESS(DevAddress);
+  }
+
+  /* Wait until ADDR flag is set */
+  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+  {
+    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address for read request.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress: Target device address
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
+{
+  /* Enable Acknowledge */
+  hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+  /* Generate Start */
+  hi2c->Instance->CR1 |= I2C_CR1_START;
+
+  /* Wait until SB flag is set */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+  {
+    /* Send slave address */
+    hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_READ(DevAddress);
+  }
+  else
+  {
+    /* Send header of slave address */
+    hi2c->Instance->DR = __HAL_I2C_10BIT_HEADER_WRITE(DevAddress);
+
+    /* Wait until ADD10 flag is set */
+    if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Send slave address */
+    hi2c->Instance->DR = __HAL_I2C_10BIT_ADDRESS(DevAddress);
+
+    /* Wait until ADDR flag is set */
+    if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+    {
+      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+    /* Generate Restart */
+    hi2c->Instance->CR1 |= I2C_CR1_START;
+
+    /* Wait until SB flag is set */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Send header of slave address */
+    hi2c->Instance->DR = __HAL_I2C_10BIT_HEADER_READ(DevAddress);
+  }
+
+  /* Wait until ADDR flag is set */
+  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+  {
+    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for write request.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress: Target device address
+  * @param  MemAddress: Internal memory address
+  * @param  MemAddSize: Size of internal memory address
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+{
+  /* Generate Start */
+  hi2c->Instance->CR1 |= I2C_CR1_START;
+
+  /* Wait until SB flag is set */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* Send slave address */
+  hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_WRITE(DevAddress);
+
+  /* Wait until ADDR flag is set */
+  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+  {
+    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Clear ADDR flag */
+  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+  /* Wait until TXE flag is set */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* If Memory address size is 8Bit */
+  if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->DR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->DR = __HAL_I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXE flag is set */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Send LSB of Memory Address */
+    hi2c->Instance->DR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for read request.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress: Target device address
+  * @param  MemAddress: Internal memory address
+  * @param  MemAddSize: Size of internal memory address
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+{
+  /* Enable Acknowledge */
+  hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+  /* Generate Start */
+  hi2c->Instance->CR1 |= I2C_CR1_START;
+
+  /* Wait until SB flag is set */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* Send slave address */
+  hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_WRITE(DevAddress);
+
+  /* Wait until ADDR flag is set */
+  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+  {
+    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Clear ADDR flag */
+  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+  /* Wait until TXE flag is set */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* If Memory address size is 8Bit */
+  if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->DR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->DR = __HAL_I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXE flag is set */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Send LSB of Memory Address */
+    hi2c->Instance->DR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  /* Wait until TXE flag is set */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* Generate Restart */
+  hi2c->Instance->CR1 |= I2C_CR1_START;
+
+  /* Wait until SB flag is set */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* Send slave address */
+  hi2c->Instance->DR = __HAL_I2C_7BIT_ADD_READ(DevAddress);
+
+  /* Wait until ADDR flag is set */
+  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+  {
+    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DMA I2C master transmit process complete callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Wait until BTF flag is reset */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+  }
+
+  /* Generate Stop */
+  hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+
+  hi2c->XferCount = 0;
+
+  /* Wait until BUSY flag is reset */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+  }
+
+  hi2c->State = HAL_I2C_STATE_READY;
+
+  /* Check if Errors has been detected during transfer */
+  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  {
+    HAL_I2C_ErrorCallback(hi2c);
+  }
+  else
+  {
+    HAL_I2C_MasterTxCpltCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  DMA I2C slave transmit process complete callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Wait until AF flag is reset */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+  }
+
+  /* Clear AF flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+  /* Disable Address Acknowledge */
+  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+
+  hi2c->XferCount = 0;
+
+  /* Wait until BUSY flag is reset */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+  }
+
+  hi2c->State = HAL_I2C_STATE_READY;
+
+  /* Check if Errors has been detected during transfer */
+  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  {
+    HAL_I2C_ErrorCallback(hi2c);
+  }
+  else
+  {
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  DMA I2C master receive process complete callback
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Generate Stop */
+  hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+  /* Disable Last DMA */
+  hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
+
+  /* Disable Acknowledge */
+  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+
+  hi2c->XferCount = 0;
+
+  /* Wait until BUSY flag is reset */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+  }
+
+  hi2c->State = HAL_I2C_STATE_READY;
+
+  /* Check if Errors has been detected during transfer */
+  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  {
+    HAL_I2C_ErrorCallback(hi2c);
+  }
+  else
+  {
+    HAL_I2C_MasterRxCpltCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  DMA I2C slave receive process complete callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Wait until STOPF flag is reset */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+  }
+
+  /* Clear STOPF flag */
+  __HAL_I2C_CLEAR_STOPFLAG(hi2c);
+
+  /* Disable Address Acknowledge */
+  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+
+  hi2c->XferCount = 0;
+
+  /* Wait until BUSY flag is reset */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+  }
+
+  hi2c->State = HAL_I2C_STATE_READY;
+
+  /* Check if Errors has been detected during transfer */
+  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  {
+    HAL_I2C_ErrorCallback(hi2c);
+  }
+  else
+  {
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  DMA I2C Memory Write process complete callback
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Wait until BTF flag is reset */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+  }
+
+  /* Generate Stop */
+  hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+
+  hi2c->XferCount = 0;
+
+  /* Wait until BUSY flag is reset */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+  }
+
+  hi2c->State = HAL_I2C_STATE_READY;
+
+  /* Check if Errors has been detected during transfer */
+  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  {
+    HAL_I2C_ErrorCallback(hi2c);
+  }
+  else
+  {
+    HAL_I2C_MemTxCpltCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  DMA I2C Memory Read process complete callback
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Generate Stop */
+  hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+  /* Disable Last DMA */
+  hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
+
+  /* Disable Acknowledge */
+  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+
+  hi2c->XferCount = 0;
+
+  /* Wait until BUSY flag is reset */
+  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+  }
+
+  hi2c->State = HAL_I2C_STATE_READY;
+
+  /* Check if Errors has been detected during transfer */
+  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  {
+    HAL_I2C_ErrorCallback(hi2c);
+  }
+  else
+  {
+    HAL_I2C_MemRxCpltCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  DMA I2C communication error callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Disable Acknowledge */
+  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+  hi2c->XferCount = 0;
+
+  hi2c->State = HAL_I2C_STATE_READY;
+
+  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+  HAL_I2C_ErrorCallback(hi2c);
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  Flag: specifies the I2C flag to check.
+  * @param  Status: The new Flag status (SET or RESET).
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+  uint32_t timeout = 0;
+
+  timeout = HAL_GetTick() + Timeout;
+
+  /* Wait until flag is set */
+  if(Status == RESET)
+  {
+    while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          hi2c->State= HAL_I2C_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  else
+  {
+    while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          hi2c->State= HAL_I2C_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for Master addressing phase.
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  Flag: specifies the I2C flag to check.
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout)
+{
+  uint32_t timeout = 0;
+
+  timeout = HAL_GetTick() + Timeout;
+
+  while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
+  {
+    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+    {
+      /* Generate Stop */
+      hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+      /* Clear AF Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+      hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+      hi2c->State= HAL_I2C_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        hi2c->State= HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,462 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_i2c.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of I2C HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_I2C_H
+#define __STM32F4xx_HAL_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  I2C Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockSpeed;       /*!< Specifies the clock frequency.
+                                  This parameter must be set to a value lower than 400kHz */
+
+  uint32_t DutyCycle;        /*!< Specifies the I2C fast mode duty cycle.
+                                  This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+  uint32_t OwnAddress1;      /*!< Specifies the first device own address.
+                                  This parameter can be a 7-bit or 10-bit address. */
+
+  uint32_t AddressingMode;   /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_addressing_mode */
+
+  uint32_t DualAddressMode;  /*!< Specifies if dual addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_dual_addressing_mode */
+
+  uint32_t OwnAddress2;      /*!< Specifies the second device own address if dual addressing mode is selected
+                                  This parameter can be a 7-bit address. */
+
+  uint32_t GeneralCallMode;  /*!< Specifies if general call mode is selected.
+                                  This parameter can be a value of @ref I2C_general_call_addressing_mode */
+
+  uint32_t NoStretchMode;    /*!< Specifies if nostretch mode is selected.
+                                  This parameter can be a value of @ref I2C_nostretch_mode */
+
+}I2C_InitTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_I2C_STATE_RESET             = 0x00,  /*!< I2C not yet initialized or disabled         */
+  HAL_I2C_STATE_READY             = 0x01,  /*!< I2C initialized and ready for use           */
+  HAL_I2C_STATE_BUSY              = 0x02,  /*!< I2C internal process is ongoing             */
+  HAL_I2C_STATE_BUSY_TX           = 0x12,  /*!< Data Transmission process is ongoing        */
+  HAL_I2C_STATE_BUSY_RX           = 0x22,  /*!< Data Reception process is ongoing           */
+  HAL_I2C_STATE_MEM_BUSY_TX       = 0x32,  /*!< Memory Data Transmission process is ongoing */
+  HAL_I2C_STATE_MEM_BUSY_RX       = 0x42,  /*!< Memory Data Reception process is ongoing    */
+  HAL_I2C_STATE_TIMEOUT           = 0x03,  /*!< I2C timeout state                           */
+  HAL_I2C_STATE_ERROR             = 0x04   /*!< I2C error state                             */
+
+}HAL_I2C_StateTypeDef;
+
+/**
+  * @brief  HAL I2C Error Code structure definition
+  */
+typedef enum
+{
+  HAL_I2C_ERROR_NONE      = 0x00,    /*!< No error             */
+  HAL_I2C_ERROR_BERR      = 0x01,    /*!< BERR error           */
+  HAL_I2C_ERROR_ARLO      = 0x02,    /*!< ARLO error           */
+  HAL_I2C_ERROR_AF        = 0x04,    /*!< AF error             */
+  HAL_I2C_ERROR_OVR       = 0x08,    /*!< OVR error            */
+  HAL_I2C_ERROR_DMA       = 0x10,    /*!< DMA transfer error   */
+  HAL_I2C_ERROR_TIMEOUT   = 0x20     /*!< Timeout error        */
+
+}HAL_I2C_ErrorTypeDef;
+
+/**
+  * @brief  I2C handle Structure definition
+  */
+typedef struct
+{
+  I2C_TypeDef                *Instance;  /*!< I2C registers base address     */
+
+  I2C_InitTypeDef            Init;       /*!< I2C communication parameters   */
+
+  uint8_t                    *pBuffPtr;  /*!< Pointer to I2C transfer buffer */
+
+  uint16_t                   XferSize;   /*!< I2C transfer size              */
+
+  __IO uint16_t              XferCount;  /*!< I2C transfer counter           */
+
+  DMA_HandleTypeDef          *hdmatx;    /*!< I2C Tx DMA handle parameters   */
+
+  DMA_HandleTypeDef          *hdmarx;    /*!< I2C Rx DMA handle parameters   */
+
+  HAL_LockTypeDef            Lock;       /*!< I2C locking object             */
+
+  __IO HAL_I2C_StateTypeDef  State;      /*!< I2C communication state        */
+
+  __IO HAL_I2C_ErrorTypeDef  ErrorCode;         /* I2C Error code                 */
+
+}I2C_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants
+  * @{
+  */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode
+  * @{
+  */
+#define I2C_DUTYCYCLE_2                 ((uint32_t)0x00000000)
+#define I2C_DUTYCYCLE_16_9              I2C_CCR_DUTY
+
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
+                                  ((CYCLE) == I2C_DUTYCYCLE_16_9))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_addressing_mode
+  * @{
+  */
+#define I2C_ADDRESSINGMODE_7BIT         ((uint32_t)0x00004000)
+#define I2C_ADDRESSINGMODE_10BIT        (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000))
+
+#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
+                                         ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_dual_addressing_mode
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLED        ((uint32_t)0x00000000)
+#define I2C_DUALADDRESS_ENABLED         I2C_OAR2_ENDUAL
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \
+                                      ((ADDRESS) == I2C_DUALADDRESS_ENABLED))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_general_call_addressing_mode
+  * @{
+  */
+#define I2C_GENERALCALL_DISABLED        ((uint32_t)0x00000000)
+#define I2C_GENERALCALL_ENABLED         I2C_CR1_ENGC
+
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \
+                                   ((CALL) == I2C_GENERALCALL_ENABLED))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_nostretch_mode
+  * @{
+  */
+#define I2C_NOSTRETCH_DISABLED          ((uint32_t)0x00000000)
+#define I2C_NOSTRETCH_ENABLED           I2C_CR1_NOSTRETCH
+
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \
+                                    ((STRETCH) == I2C_NOSTRETCH_ENABLED))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Memory_Address_Size
+  * @{
+  */
+#define I2C_MEMADD_SIZE_8BIT            ((uint32_t)0x00000001)
+#define I2C_MEMADD_SIZE_16BIT           ((uint32_t)0x00000010)
+
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+                                  ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Interrupt_configuration_definition
+  * @{
+  */
+#define I2C_IT_BUF                      I2C_CR2_ITBUFEN
+#define I2C_IT_EVT                      I2C_CR2_ITEVTEN
+#define I2C_IT_ERR                      I2C_CR2_ITERREN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Flag_definition
+  * @{
+  */
+#define I2C_FLAG_SMBALERT               ((uint32_t)0x00018000)
+#define I2C_FLAG_TIMEOUT                ((uint32_t)0x00014000)
+#define I2C_FLAG_PECERR                 ((uint32_t)0x00011000)
+#define I2C_FLAG_OVR                    ((uint32_t)0x00010800)
+#define I2C_FLAG_AF                     ((uint32_t)0x00010400)
+#define I2C_FLAG_ARLO                   ((uint32_t)0x00010200)
+#define I2C_FLAG_BERR                   ((uint32_t)0x00010100)
+#define I2C_FLAG_TXE                    ((uint32_t)0x00010080)
+#define I2C_FLAG_RXNE                   ((uint32_t)0x00010040)
+#define I2C_FLAG_STOPF                  ((uint32_t)0x00010010)
+#define I2C_FLAG_ADD10                  ((uint32_t)0x00010008)
+#define I2C_FLAG_BTF                    ((uint32_t)0x00010004)
+#define I2C_FLAG_ADDR                   ((uint32_t)0x00010002)
+#define I2C_FLAG_SB                     ((uint32_t)0x00010001)
+#define I2C_FLAG_DUALF                  ((uint32_t)0x00100080)
+#define I2C_FLAG_SMBHOST                ((uint32_t)0x00100040)
+#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00100020)
+#define I2C_FLAG_GENCALL                ((uint32_t)0x00100010)
+#define I2C_FLAG_TRA                    ((uint32_t)0x00100004)
+#define I2C_FLAG_BUSY                   ((uint32_t)0x00100002)
+#define I2C_FLAG_MSL                    ((uint32_t)0x00100001)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset I2C handle state
+  * @param  __HANDLE__: specifies the I2C Handle.
+  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+  * @retval None
+  */
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+
+/** @brief  Enable or disable the specified I2C interrupts.
+  * @param  __HANDLE__: specifies the I2C Handle.
+  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  *         This parameter can be one of the following values:
+  *            @arg I2C_IT_BUF: Buffer interrupt enable
+  *            @arg I2C_IT_EVT: Event interrupt enable
+  *            @arg I2C_IT_ERR: Error interrupt enable
+  * @retval None
+  */
+
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+
+/** @brief  Checks if the specified I2C interrupt source is enabled or disabled.
+  * @param  __HANDLE__: specifies the I2C Handle.
+  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+  * @param  __INTERRUPT__: specifies the I2C interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_IT_BUF: Buffer interrupt enable
+  *            @arg I2C_IT_EVT: Event interrupt enable
+  *            @arg I2C_IT_ERR: Error interrupt enable
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Checks whether the specified I2C flag is set or not.
+  * @param  __HANDLE__: specifies the I2C Handle.
+  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+  *            @arg I2C_FLAG_PECERR: PEC error in reception flag
+  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag
+  *            @arg I2C_FLAG_AF: Acknowledge failure flag
+  *            @arg I2C_FLAG_ARLO: Arbitration lost flag
+  *            @arg I2C_FLAG_BERR: Bus error flag
+  *            @arg I2C_FLAG_TXE: Data register empty flag
+  *            @arg I2C_FLAG_RXNE: Data register not empty flag
+  *            @arg I2C_FLAG_STOPF: Stop detection flag
+  *            @arg I2C_FLAG_ADD10: 10-bit header sent flag
+  *            @arg I2C_FLAG_BTF: Byte transfer finished flag
+  *            @arg I2C_FLAG_ADDR: Address sent flag
+  *                                Address matched flag
+  *            @arg I2C_FLAG_SB: Start bit flag
+  *            @arg I2C_FLAG_DUALF: Dual flag
+  *            @arg I2C_FLAG_SMBHOST: SMBus host header
+  *            @arg I2C_FLAG_SMBDEFAULT: SMBus default header
+  *            @arg I2C_FLAG_GENCALL: General call header flag
+  *            @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+  *            @arg I2C_FLAG_BUSY: Bus busy flag
+  *            @arg I2C_FLAG_MSL: Master/Slave flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define I2C_FLAG_MASK  ((uint32_t)0x0000FFFF)
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
+                                                 ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
+
+/** @brief  Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
+  * @param  __HANDLE__: specifies the I2C Handle.
+  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+  * @param  __FLAG__: specifies the flag to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+  *            @arg I2C_FLAG_PECERR: PEC error in reception flag
+  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+  *            @arg I2C_FLAG_AF: Acknowledge failure flag
+  *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+  *            @arg I2C_FLAG_BERR: Bus error flag
+  * @retval None
+  */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 &= ~((__FLAG__) & I2C_FLAG_MASK))
+
+/** @brief  Clears the I2C ADDR pending flag.
+  * @param  __HANDLE__: specifies the I2C Handle.
+  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+  * @retval None
+  */
+
+#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\
+                                                (__HANDLE__)->Instance->SR2;}while(0)
+
+/** @brief  Clears the I2C STOPF pending flag.
+  * @param  __HANDLE__: specifies the I2C Handle.
+  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+  * @retval None
+  */
+#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\
+                                                (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE;}while(0)
+
+#define __HAL_I2C_ENABLE(__HANDLE__)                             ((__HANDLE__)->Instance->CR1 |=  I2C_CR1_PE)
+#define __HAL_I2C_DISABLE(__HANDLE__)                            ((__HANDLE__)->Instance->CR1 &=  ~I2C_CR1_PE)
+
+#define __HAL_I2C_FREQRANGE(__PCLK__)                            ((__PCLK__)/1000000)
+#define __HAL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__)            (((__SPEED__) <= 100000) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1))
+#define __HAL_I2C_SPEED_STANDARD(__PCLK__, __SPEED__)            (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1)))
+#define __HAL_I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9))
+#define __HAL_I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)      (((__SPEED__) <= 100000)? (__HAL_I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
+                                                                  ((__HAL_I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \
+                                                                  ((__HAL_I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
+
+#define __HAL_I2C_7BIT_ADD_WRITE(__ADDRESS__)                    ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
+#define __HAL_I2C_7BIT_ADD_READ(__ADDRESS__)                     ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
+
+#define __HAL_I2C_10BIT_ADDRESS(__ADDRESS__)                     ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+#define __HAL_I2C_10BIT_HEADER_WRITE(__ADDRESS__)                ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
+#define __HAL_I2C_10BIT_HEADER_READ(__ADDRESS__)                 ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
+
+#define __HAL_I2C_MEM_ADD_MSB(__ADDRESS__)                       ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
+#define __HAL_I2C_MEM_ADD_LSB(__ADDRESS__)                       ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000))
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0)
+
+/* Include I2C HAL Extension module */
+#include "stm32f4xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* I/O operation functions  *****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+
+/* Peripheral Control and State functions  **************************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,205 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_i2c_ex.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   I2C Extension HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of I2C extension peripheral:
+  *           + Extension features functions
+  *    
+  @verbatim
+  ==============================================================================
+               ##### I2C peripheral extension features  #####
+  ==============================================================================
+           
+  [..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/ 
+       429xx/439xx devices contains the following additional features :
+       
+       (+) Possibility to disable or enable Analog Noise Filter
+       (+) Use of a configured Digital Noise Filter
+   
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to configure Noise Filter
+    (#) Configure I2C Analog noise filter using the function HAL_I2C_AnalogFilter_Config()
+    (#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config()
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2CEx 
+  * @brief I2C HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2CEx_Private_Functions
+  * @{
+  */
+
+
+/** @defgroup I2CEx_Group1 Extension features functions 
+ *  @brief   Extension features functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Extension features functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to:
+      (+) Configure Noise Filters 
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Configures I2C Analog noise filter. 
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  AnalogFilter: new state of the Analog filter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+  uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+  
+  tmp = hi2c->State;
+  if((tmp == HAL_I2C_STATE_BUSY) || (tmp == HAL_I2C_STATE_BUSY_TX) || (tmp == HAL_I2C_STATE_BUSY_RX))
+  {
+    return HAL_BUSY;
+  }
+  
+  hi2c->State = HAL_I2C_STATE_BUSY;
+  
+  /* Disable the selected I2C peripheral */
+  __HAL_I2C_DISABLE(hi2c);    
+  
+  /* Reset I2Cx ANOFF bit */
+  hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF);    
+  
+  /* Disable the analog filter */
+  hi2c->Instance->FLTR |= AnalogFilter;
+  
+  __HAL_I2C_ENABLE(hi2c); 
+  
+  hi2c->State = HAL_I2C_STATE_READY;
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Configures I2C Digital noise filter. 
+  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  DigitalFilter: Coefficient of digital noise filter between 0x00 and 0x0F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+  uint16_t tmpreg = 0;
+  uint32_t tmp = 0;  
+  
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+  
+  tmp = hi2c->State;
+  if((tmp == HAL_I2C_STATE_BUSY) || (tmp == HAL_I2C_STATE_BUSY_TX) || (tmp == HAL_I2C_STATE_BUSY_RX))
+  {
+    return HAL_BUSY;
+  }
+  
+  hi2c->State = HAL_I2C_STATE_BUSY;
+  
+  /* Disable the selected I2C peripheral */
+  __HAL_I2C_DISABLE(hi2c);  
+  
+  /* Get the old register value */
+  tmpreg = hi2c->Instance->FLTR;
+  
+  /* Reset I2Cx DNF bit [3:0] */
+  tmpreg &= ~(I2C_FLTR_DNF);
+  
+  /* Set I2Cx DNF coefficient */
+  tmpreg |= DigitalFilter;
+  
+  /* Store the new register value */
+  hi2c->Instance->FLTR = tmpreg;
+  
+  __HAL_I2C_ENABLE(hi2c); 
+  
+  hi2c->State = HAL_I2C_STATE_READY;
+  
+  return HAL_OK; 
+}  
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC || STM32F401xE */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2c_ex.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,112 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_i2c_ex.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of I2C HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_I2C_EX_H
+#define __STM32F4xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"  
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2CEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Constants
+  * @{
+  */
+
+/** @defgroup I2CEx_Analog_Filter
+  * @{
+  */
+#define I2C_ANALOGFILTER_ENABLED        ((uint32_t)0x00000000)
+#define I2C_ANALOGFILTER_DISABLED       I2C_FLTR_ANOFF
+
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLED) || \
+                                      ((FILTER) == I2C_ANALOGFILTER_DISABLED))
+/**
+  * @}
+  */
+
+/** @defgroup I2CEx_Digital_Filter
+  * @{
+  */
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000F)
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+
+/**
+  * @}
+  */ 
+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC || STM32F401xE */
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_I2C_EX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1669 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_i2s.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   I2S HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  @verbatim
+ ===============================================================================
+                  ##### How to use this driver #####
+ ===============================================================================
+ [..]
+    The I2S HAL driver can be used as follow:
+    
+    (#) Declare a I2S_HandleTypeDef handle structure.
+    (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
+        (##) Enable the SPIx interface clock.                      
+        (##) I2S pins configuration:
+            (+++) Enable the clock for the I2S GPIOs.
+            (+++) Configure these I2S pins as alternate function pull-up.
+        (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
+             and HAL_I2S_Receive_IT() APIs).
+            (+++) Configure the I2Sx interrupt priority.
+            (+++) Enable the NVIC I2S IRQ handle.
+        (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
+             and HAL_I2S_Receive_DMA() APIs:
+            (+++) Declare a DMA handle structure for the Tx/Rx stream.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx Stream.
+            (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the 
+                DMA Tx/Rx Stream.
+  
+   (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
+       using HAL_I2S_Init() function.
+
+   -@- The specific I2S interrupts (Transmission complete interrupt, 
+       RXNE interrupt and Error Interrupts) will be managed using the macros
+       __I2S_ENABLE_IT() and __I2S_DISABLE_IT() inside the transmit and receive process.
+   -@- Make sure that either:
+        (+@) I2S PLL is configured or 
+        (+@) External clock source is configured after setting correctly 
+             the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file. 
+             
+   (#) Three operation modes are available within this driver :
+  
+   *** Polling mode IO operation ***
+   =================================
+   [..]    
+     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() 
+     (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
+   
+   *** Interrupt mode IO operation ***
+   ===================================
+   [..]    
+     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() 
+     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback 
+     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() 
+     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback 
+     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_ErrorCallback
+
+   *** DMA mode IO operation ***
+   ==============================
+   [..] 
+     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() 
+     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback 
+     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() 
+     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback 
+     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_ErrorCallback
+     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
+     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
+     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
+
+   *** I2S HAL driver macros list ***
+   =============================================
+   [..]
+     Below the list of most used macros in USART HAL driver.
+       
+      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) 
+      (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
+      (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
+      (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
+      (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
+
+    [..]
+      (@) You can refer to the I2S HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2S 
+  * @brief I2S HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
+static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2S_Private_Functions
+  * @{
+  */
+
+/** @defgroup  I2S_Group1 Initialization and de-initialization functions 
+  *  @brief    Initialization and Configuration functions 
+  *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and 
+          de-initialiaze the I2Sx peripheral in simplex mode:
+
+      (+) User must Implement HAL_I2S_MspInit() function in which he configures 
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_I2S_Init() to configure the selected device with 
+          the selected configuration:
+        (++) Mode
+        (++) Standard 
+        (++) Data Format
+        (++) MCLK Output
+        (++) Audio frequency
+        (++) Polarity
+        (++) Full duplex mode
+
+      (+) Call the function HAL_I2S_DeInit() to restore the default configuration 
+          of the selected I2Sx periperal. 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Initializes the I2S according to the specified parameters 
+  *         in the I2S_InitTypeDef and create the associated handle.
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+{
+  uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+  uint32_t tmp = 0, i2sclk = 0;
+  
+  /* Check the I2S handle allocation */
+  if(hi2s == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the I2S parameters */
+  assert_param(IS_I2S_MODE(hi2s->Init.Mode));
+  assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
+  assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
+  assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
+  assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
+  assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));  
+  assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
+  assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
+  
+  if(hi2s->State == HAL_I2S_STATE_RESET)
+  {
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_I2S_MspInit(hi2s);
+  }
+  
+  hi2s->State = HAL_I2S_STATE_BUSY;
+  
+  /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
+  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+  hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+                               SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+                               SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD); 
+  hi2s->Instance->I2SPR = 0x0002;
+
+  /* Get the I2SCFGR register value */
+  tmpreg = hi2s->Instance->I2SCFGR;
+
+  /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
+  /* If the requested audio frequency is not the default, compute the prescaler */
+  if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
+  {
+    /* Check the frame length (For the Prescaler computing) *******************/
+    if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
+    {
+      /* Packet length is 32 bits */
+      packetlength = 2;
+    }
+
+    /* Get I2S source Clock frequency  ****************************************/
+    /* If an external I2S clock has to be used, the specific define should be set  
+    in the project configuration or in the stm32f4xx_conf.h file */
+    if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
+    {
+      /* Set external clock as I2S clock source */
+      if((RCC->CFGR & RCC_CFGR_I2SSRC) == 0)
+      {
+        RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
+      }
+
+      /* Set the I2S clock to the external clock  value */
+      i2sclk = EXTERNAL_CLOCK_VALUE;
+    }
+    else
+    { 
+      /* Check if PLLI2S is enabled or Not */
+      if((RCC->CR & RCC_CR_PLLI2SON) != RCC_CR_PLLI2SON)
+      {
+        hi2s->State= HAL_I2S_STATE_READY;
+        
+        return HAL_ERROR;
+      }
+
+      /* Set PLLI2S as I2S clock source */
+      if((RCC->CFGR & RCC_CFGR_I2SSRC) != 0)
+      {
+        RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
+      }
+
+      /* Get the PLLM value */
+      if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+      {
+        /* Get the I2S source clock value */
+        i2sclk = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+      }
+      else
+      {
+        /* Get the I2S source clock value */
+        i2sclk = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+      }
+      i2sclk *= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6));
+      i2sclk /= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28));
+    }
+
+    /* Compute the Real divider depending on the MCLK output state, with a floating point */
+    if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
+    {
+      /* MCLK output is enabled */
+      tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
+    }
+    else
+    {
+      /* MCLK output is disabled */
+      tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
+    }
+
+    /* Remove the flatting point */
+    tmp = tmp / 10;  
+
+    /* Check the parity of the divider */
+    i2sodd = (uint32_t)(tmp & (uint32_t)1);
+
+    /* Compute the i2sdiv prescaler */
+    i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
+
+    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+    i2sodd = (uint32_t) (i2sodd << 8);
+  }
+
+  /* Test if the divider is 1 or 0 or greater than 0xFF */
+  if((i2sdiv < 2) || (i2sdiv > 0xFF))
+  {
+    /* Set the default values */
+    i2sdiv = 2;
+    i2sodd = 0;
+  }
+  
+  /* Write to SPIx I2SPR register the computed value */
+  hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
+  
+  /* Configure the I2S with the I2S_InitStruct values */
+  tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
+  
+  /* Write to SPIx I2SCFGR */  
+  hi2s->Instance->I2SCFGR = tmpreg;
+  
+  /* Configure the I2S extended if the full duplex mode is enabled */
+  if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+  {    
+    /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+    I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+                                          SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+                                          SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
+    I2SxEXT(hi2s->Instance)->I2SPR = 2;
+    
+    /* Get the I2SCFGR register value */
+    tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
+    
+    /* Get the mode to be configured for the extended I2S */
+    if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
+    {
+      tmp = I2S_MODE_SLAVE_RX;
+    }
+    else
+    {
+      if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
+      {
+        tmp = I2S_MODE_SLAVE_TX;
+      }
+    }
+    
+    /* Configure the I2S Slave with the I2S Master parameter values */
+    tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | tmp | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
+    
+    /* Write to SPIx I2SCFGR */  
+    I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg;
+  }
+  
+  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+  hi2s->State= HAL_I2S_STATE_READY;
+  
+  return HAL_OK;
+}
+           
+/**
+  * @brief DeInitializes the I2S peripheral 
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
+{
+  /* Check the I2S handle allocation */
+  if(hi2s == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  hi2s->State = HAL_I2S_STATE_BUSY;
+  
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+  HAL_I2S_MspDeInit(hi2s);
+
+  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+  hi2s->State = HAL_I2S_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2s);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief I2S MSP Init
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+ __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_MspInit could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @brief I2S MSP DeInit
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_MspDeInit could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Group2 IO operation functions 
+  *  @brief Data transfers functions 
+  *
+@verbatim   
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the I2S data 
+    transfers.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode : The communication is performed in the polling mode. 
+            The status of all data processing is returned by the same function 
+            after finishing transfer.  
+       (++) No-Blocking mode : The communication is performed using Interrupts 
+            or DMA. These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the 
+            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when 
+            using DMA mode.
+
+    (#) Blocking mode functions are :
+        (++) HAL_I2S_Transmit()
+        (++) HAL_I2S_Receive()
+        
+    (#) No-Blocking mode functions with Interrupt are :
+        (++) HAL_I2S_Transmit_IT()
+        (++) HAL_I2S_Receive_IT()
+
+    (#) No-Blocking mode functions with DMA are :
+        (++) HAL_I2S_Transmit_DMA()
+        (++) HAL_I2S_Receive_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_I2S_TxCpltCallback()
+        (++) HAL_I2S_RxCpltCallback()
+        (++) HAL_I2S_ErrorCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Transmit an amount of data in blocking mode
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param pData: a 16-bit pointer to data buffer.
+  * @param Size: number of data sample to be sent:
+  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *       configuration phase, the Size parameter means the number of 16-bit data length 
+  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
+  *       the Size parameter means the number of 16-bit data length. 
+  * @param  Timeout: Timeout duration
+  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
+  *       between Master and Slave(example: audio streaming).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tmp1 = 0, tmp2 = 0;  
+  if((pData == NULL ) || (Size == 0)) 
+  {
+    return  HAL_ERROR;
+  }
+  
+  if(hi2s->State == HAL_I2S_STATE_READY)
+  { 
+    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+    tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+    if((tmp1 == I2S_DATAFORMAT_24B)|| \
+       (tmp2 == I2S_DATAFORMAT_32B))
+    {
+      hi2s->TxXferSize = Size*2;
+      hi2s->TxXferCount = Size*2;
+    }
+    else
+    {
+      hi2s->TxXferSize = Size;
+      hi2s->TxXferCount = Size;
+    }
+    
+    /* Process Locked */
+    __HAL_LOCK(hi2s);
+    
+    hi2s->State = HAL_I2S_STATE_BUSY_TX;
+   
+    /* Check if the I2S is already enabled */ 
+    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+    {
+      /* Enable I2S peripheral */
+      __HAL_I2S_ENABLE(hi2s);
+    }
+    
+    while(hi2s->TxXferCount > 0)
+    {
+      hi2s->Instance->DR = (*pData++);
+      hi2s->TxXferCount--;   
+      /* Wait until TXE flag is set */
+      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+    } 
+    /* Wait until Busy flag is reset */
+    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    hi2s->State = HAL_I2S_STATE_READY; 
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode 
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param pData: a 16-bit pointer to data buffer.
+  * @param Size: number of data sample to be sent:
+  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *       configuration phase, the Size parameter means the number of 16-bit data length 
+  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
+  *       the Size parameter means the number of 16-bit data length. 
+  * @param Timeout: Timeout duration
+  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
+  *       between Master and Slave(example: audio streaming).
+  * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
+  *       in continouse way and as the I2S is not disabled at the end of the I2S transaction.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tmp1 = 0, tmp2 = 0;   
+  if((pData == NULL ) || (Size == 0)) 
+  {
+    return  HAL_ERROR;
+  }
+  
+  if(hi2s->State == HAL_I2S_STATE_READY)
+  { 
+    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+    tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+    if((tmp1 == I2S_DATAFORMAT_24B)|| \
+       (tmp2 == I2S_DATAFORMAT_32B))
+    {
+      hi2s->RxXferSize = Size*2;
+      hi2s->RxXferCount = Size*2;
+    }
+    else
+    {
+      hi2s->RxXferSize = Size;
+      hi2s->RxXferCount = Size;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2s);
+
+    hi2s->State = HAL_I2S_STATE_BUSY_RX;
+
+    /* Check if the I2S is already enabled */ 
+    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+    {
+      /* Enable I2S peripheral */
+      __HAL_I2S_ENABLE(hi2s);
+    }
+
+    /* Check if Master Receiver mode is selected */
+    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+    {
+      /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+      access to the SPI_SR register. */ 
+      __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+    }
+
+    /* Receive data */
+    while(hi2s->RxXferCount > 0)
+    {
+      /* Wait until RXNE flag is set */
+      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+
+      (*pData++) = hi2s->Instance->DR;
+      hi2s->RxXferCount--;
+    }
+
+    hi2s->State = HAL_I2S_STATE_READY; 
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Transmit an amount of data in non-blocking mode with Interrupt
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param pData: a 16-bit pointer to data buffer.
+  * @param Size: number of data sample to be sent:
+  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *       configuration phase, the Size parameter means the number of 16-bit data length 
+  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
+  *       the Size parameter means the number of 16-bit data length. 
+  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
+  *       between Master and Slave(example: audio streaming).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+  uint32_t tmp1 = 0, tmp2 = 0;     
+  if(hi2s->State == HAL_I2S_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0)) 
+    {
+      return  HAL_ERROR;
+    }
+
+    hi2s->pTxBuffPtr = pData;
+    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+    tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+    if((tmp1 == I2S_DATAFORMAT_24B)|| \
+      (tmp2 == I2S_DATAFORMAT_32B))
+    {
+      hi2s->TxXferSize = Size*2;
+      hi2s->TxXferCount = Size*2;
+    }
+    else
+    {
+      hi2s->TxXferSize = Size;
+      hi2s->TxXferCount = Size;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2s);
+
+    hi2s->State = HAL_I2S_STATE_BUSY_TX;
+    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+    /* Enable TXE and ERR interrupt */
+    __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+    /* Check if the I2S is already enabled */ 
+    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+    {
+      /* Enable I2S peripheral */
+      __HAL_I2S_ENABLE(hi2s);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in non-blocking mode with Interrupt
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param pData: a 16-bit pointer to the Receive data buffer.
+  * @param Size: number of data sample to be sent:
+  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *       configuration phase, the Size parameter means the number of 16-bit data length 
+  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
+  *       the Size parameter means the number of 16-bit data length. 
+  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
+  *       between Master and Slave(example: audio streaming).
+  * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation 
+  * between Master and Slave otherwise the I2S interrupt should be optimized. 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+  uint32_t tmp1 = 0, tmp2 = 0;     
+  if(hi2s->State == HAL_I2S_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0)) 
+    {
+      return  HAL_ERROR;
+    }
+
+    hi2s->pRxBuffPtr = pData;
+    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+    tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+    if((tmp1 == I2S_DATAFORMAT_24B)||\
+      (tmp2 == I2S_DATAFORMAT_32B))
+    {
+      hi2s->RxXferSize = Size*2;
+      hi2s->RxXferCount = Size*2;
+    }
+    else
+    {
+      hi2s->RxXferSize = Size;
+      hi2s->RxXferCount = Size;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2s);
+    
+    hi2s->State = HAL_I2S_STATE_BUSY_RX;
+    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+    
+    /* Enable TXE and ERR interrupt */
+    __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+    
+    /* Check if the I2S is already enabled */ 
+    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+    {
+      /* Enable I2S peripheral */
+      __HAL_I2S_ENABLE(hi2s);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+
+    return HAL_OK;
+  }
+
+  else
+  {
+    return HAL_BUSY; 
+  } 
+}
+
+/**
+  * @brief Transmit an amount of data in non-blocking mode with DMA
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param pData: a 16-bit pointer to the Transmit data buffer.
+  * @param Size: number of data sample to be sent:
+  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *       configuration phase, the Size parameter means the number of 16-bit data length 
+  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
+  *       the Size parameter means the number of 16-bit data length. 
+  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
+  *       between Master and Slave(example: audio streaming).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+  uint32_t *tmp;
+  uint32_t tmp1 = 0, tmp2 = 0;     
+  
+  if((pData == NULL) || (Size == 0)) 
+  {
+    return  HAL_ERROR;
+  }
+
+  if(hi2s->State == HAL_I2S_STATE_READY)
+  {  
+    hi2s->pTxBuffPtr = pData;
+    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+    tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+    if((tmp1 == I2S_DATAFORMAT_24B)|| \
+      (tmp2 == I2S_DATAFORMAT_32B))
+    {
+      hi2s->TxXferSize = Size*2;
+      hi2s->TxXferCount = Size*2;
+    }
+    else
+    {
+      hi2s->TxXferSize = Size;
+      hi2s->TxXferCount = Size;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2s);
+
+    hi2s->State = HAL_I2S_STATE_BUSY_TX;
+    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+    /* Set the I2S Tx DMA Half transfert complete callback */
+    hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
+
+    /* Set the I2S Tx DMA transfert complete callback */
+    hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
+
+    /* Set the DMA error callback */
+    hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
+
+    /* Enable the Tx DMA Stream */
+    tmp = (uint32_t*)&pData;
+    HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
+
+    /* Check if the I2S is already enabled */ 
+    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+    {
+      /* Enable I2S peripheral */
+      __HAL_I2S_ENABLE(hi2s);
+    }
+
+     /* Check if the I2S Tx request is already enabled */ 
+    if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
+    {
+      /* Enable Tx DMA Request */  
+      hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in non-blocking mode with DMA 
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param pData: a 16-bit pointer to the Receive data buffer.
+  * @param Size: number of data sample to be sent:
+  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *       configuration phase, the Size parameter means the number of 16-bit data length 
+  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
+  *       the Size parameter means the number of 16-bit data length. 
+  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
+  *       between Master and Slave(example: audio streaming).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+  uint32_t *tmp;
+  uint32_t tmp1 = 0, tmp2 = 0;  
+  
+  if((pData == NULL) || (Size == 0))
+  {
+    return  HAL_ERROR;
+  }
+
+  if(hi2s->State == HAL_I2S_STATE_READY)
+  {
+    hi2s->pRxBuffPtr = pData;
+    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+    tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+    if((tmp1 == I2S_DATAFORMAT_24B)|| \
+      (tmp2 == I2S_DATAFORMAT_32B))
+    {
+      hi2s->RxXferSize = Size*2;
+      hi2s->RxXferCount = Size*2;
+    }
+    else
+    {
+      hi2s->RxXferSize = Size;
+      hi2s->RxXferCount = Size;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2s);
+    
+    hi2s->State = HAL_I2S_STATE_BUSY_RX;
+    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+    
+    /* Set the I2S Rx DMA Half transfert complete callback */
+    hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
+    
+    /* Set the I2S Rx DMA transfert complete callback */
+    hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
+    
+    /* Set the DMA error callback */
+    hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
+    
+    /* Check if Master Receiver mode is selected */
+    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+    {
+      /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
+      access to the SPI_SR register. */ 
+      __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+    }
+    
+    /* Enable the Rx DMA Stream */
+    tmp = (uint32_t*)&pData;
+    HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
+    
+    /* Check if the I2S is already enabled */ 
+    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+    {
+      /* Enable I2S peripheral */
+      __HAL_I2S_ENABLE(hi2s);
+    }
+
+     /* Check if the I2S Rx request is already enabled */ 
+    if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
+    {
+      /* Enable Rx DMA Request */  
+      hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Pauses the audio stream playing from the Media.
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
+{
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+  
+  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+  {
+    /* Disable the I2S DMA Tx request */
+    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+  }
+  else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+  {
+    /* Disable the I2S DMA Rx request */
+    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+  }
+  else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+  {
+    if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
+    {
+      /* Disable the I2S DMA Tx request */
+      hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+      /* Disable the I2SEx Rx DMA Request */  
+      I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+    }
+    else
+    {
+      /* Disable the I2S DMA Rx request */
+      hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+      /* Disable the I2SEx Tx DMA Request */  
+      I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2s);
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief Resumes the audio stream playing from the Media.
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
+{
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+  
+  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+  {
+    /* Enable the I2S DMA Tx request */
+    hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+  }
+  else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+  {
+    /* Enable the I2S DMA Rx request */
+    hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+  }
+  else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+  {
+    if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
+    {
+      /* Enable the I2S DMA Tx request */
+      hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+      /* Disable the I2SEx Rx DMA Request */  
+      I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
+    }
+    else
+    {
+      /* Enable the I2S DMA Rx request */
+      hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+      /* Enable the I2SEx Tx DMA Request */  
+      I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
+    }
+  }
+
+  /* If the I2S peripheral is still not enabled, enable it */
+  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
+  {
+    /* Enable I2S peripheral */    
+    __HAL_I2S_ENABLE(hi2s);
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2s);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief Resumes the audio stream playing from the Media.
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
+{
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+  
+  /* Disable the I2S Tx/Rx DMA requests */
+  hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
+  hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
+  
+  if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+  {
+    /* Disable the I2S extended Tx/Rx DMA requests */  
+    I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+    I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+  }
+  
+  /* Abort the I2S DMA Stream tx */
+  if(hi2s->hdmatx != NULL)
+  {
+    HAL_DMA_Abort(hi2s->hdmatx);
+  }
+  /* Abort the I2S DMA Stream rx */
+  if(hi2s->hdmarx != NULL)
+  {
+    HAL_DMA_Abort(hi2s->hdmarx);
+  }
+
+  /* Disable I2S peripheral */
+  __HAL_I2S_DISABLE(hi2s);
+  
+  if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+  {
+    /* Disable the I2Sext peripheral */
+    I2SxEXT(hi2s->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
+  }
+  
+  hi2s->State = HAL_I2S_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2s);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2S interrupt request.
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+{  
+  uint32_t tmp1 = 0, tmp2 = 0;    
+  if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE)
+  {
+    if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+    {
+      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
+      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
+      /* I2S in mode Receiver ------------------------------------------------*/
+      if((tmp1 != RESET) && (tmp2 != RESET))
+      {
+        I2S_Receive_IT(hi2s);
+      }
+
+      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
+      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
+      /* I2S Overrun error interrupt occurred ---------------------------------*/
+      if((tmp1 != RESET) && (tmp2 != RESET))
+      {
+        __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+        hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+      }
+    }
+
+    if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+    {
+      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
+      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
+      /* I2S in mode Tramitter -----------------------------------------------*/
+      if((tmp1 != RESET) && (tmp2 != RESET))
+      {
+        I2S_Transmit_IT(hi2s);
+      } 
+
+      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
+      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
+      /* I2S Underrun error interrupt occurred --------------------------------*/
+      if((tmp1 != RESET) && (tmp2 != RESET))
+      {
+        __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+        hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+      }
+    }
+  }
+  else
+  {
+    tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+    tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+    /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+    if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
+    { 
+      tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE; 
+      tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_RXNE;  
+      /* I2Sext in mode Receiver ---------------------------------------------*/
+      if((tmp1 == SPI_SR_RXNE) && (tmp2 == I2S_IT_RXNE))
+      {
+        tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+        tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+        /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
+        the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
+        if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
+        {
+          I2SEx_TransmitReceive_IT(hi2s);
+        }
+      }
+
+      tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_OVR;
+      tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
+      /* I2Sext Overrun error interrupt occurred ------------------------------*/
+      if((tmp1 == SPI_SR_OVR) && (tmp2 == I2S_IT_ERR))
+      {
+        /* Clear I2Sext OVR Flag */ 
+        I2SxEXT(hi2s->Instance)->DR;
+        I2SxEXT(hi2s->Instance)->SR;
+        hi2s->ErrorCode |= HAL_I2SEX_ERROR_OVR;
+      }
+
+      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
+      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
+      /* I2S in mode Tramitter -----------------------------------------------*/
+      if((tmp1 != RESET) && (tmp2 != RESET))
+      {
+        tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+        tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+        /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
+        the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
+        if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
+        {
+          I2SEx_TransmitReceive_IT(hi2s);
+        }
+      }
+
+      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
+      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
+      /* I2S Underrun error interrupt occurred --------------------------------*/
+      if((tmp1 != RESET) && (tmp2 != RESET))
+      {
+        __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+        hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+      }
+    }
+    /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
+    else
+    {
+      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
+      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
+      /* I2S in mode Receiver ------------------------------------------------*/
+      if((tmp1 != RESET) && (tmp2 != RESET))
+      {
+        tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+        tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+        /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
+        the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
+        if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX))
+        {
+          I2SEx_TransmitReceive_IT(hi2s);
+        }
+      }
+
+      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
+      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
+      /* I2S Overrun error interrupt occurred ---------------------------------*/
+      if((tmp1 != RESET) && (tmp2 != RESET))
+      {
+        __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+        hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+      }
+
+      tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE;
+      tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_TXE; 
+      /* I2Sext in mode Tramitter --------------------------------------------*/
+      if((tmp1 == SPI_SR_TXE) && (tmp2 == I2S_IT_TXE))
+      {
+        tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+        tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+        /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
+        the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
+        if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX))
+        {
+          I2SEx_TransmitReceive_IT(hi2s);
+        }
+      }
+
+      tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_UDR;
+      tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
+      /* I2Sext Underrun error interrupt occurred -----------------------------*/
+      if((tmp1 == SPI_SR_UDR) && (tmp2 == I2S_IT_ERR))
+      {
+        /* Clear I2Sext UDR Flag */ 
+        I2SxEXT(hi2s->Instance)->SR;
+        hi2s->ErrorCode |= HAL_I2SEX_ERROR_UDR;
+      }
+    }
+  }
+
+  /* Call the Error call Back in case of Errors */
+  if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
+  {
+    /* Set the I2S state ready to be able to start again the process */
+    hi2s->State= HAL_I2S_STATE_READY;
+    HAL_I2S_ErrorCallback(hi2s);
+  }
+}
+
+/**
+  * @brief Tx Transfer Half completed callbacks
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+ __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_TxHalfCpltCallback could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @brief Tx Transfer completed callbacks
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+ __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_TxCpltCallback could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @brief Rx Transfer half completed callbacks
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_RxCpltCallback could be implenetd in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callbacks
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_RxCpltCallback could be implenetd in the user file
+   */
+}
+
+/**
+  * @brief I2S error callbacks
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_ErrorCallback could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Group3 Peripheral State and Errors functions 
+  *  @brief   Peripheral State functions 
+  *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State and Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the I2S state
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL state
+  */
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
+{
+  return hi2s->State;
+}
+
+/**
+  * @brief  Return the I2S error code
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval I2S Error Code
+  */
+HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
+{
+  return hi2s->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief DMA I2S transmit process complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  
+  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+  {
+    hi2s->TxXferCount = 0;
+
+    /* Disable Tx DMA Request */
+    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+    
+    if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+    {
+      /* Disable Rx DMA Request for the slave*/  
+      I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+    }
+
+    if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+    {
+      if(hi2s->RxXferCount == 0)
+      {
+        hi2s->State = HAL_I2S_STATE_READY;
+      }
+    }
+    else
+    {
+      hi2s->State = HAL_I2S_STATE_READY; 
+    }
+  }
+  HAL_I2S_TxCpltCallback(hi2s);
+}
+
+/**
+  * @brief DMA I2S transmit process half complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  HAL_I2S_TxHalfCpltCallback(hi2s);
+}
+
+/**
+  * @brief DMA I2S receive process complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+  {
+    /* Disable Rx DMA Request */
+    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+
+    if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+    {
+      /* Disable Tx DMA Request for the slave*/  
+      I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+    }
+
+    hi2s->RxXferCount = 0;
+    if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+    {
+      if(hi2s->TxXferCount == 0)
+      {
+        hi2s->State = HAL_I2S_STATE_READY;
+      }
+    }
+    else
+    {
+      hi2s->State = HAL_I2S_STATE_READY; 
+    }
+  }
+  HAL_I2S_RxCpltCallback(hi2s); 
+}
+
+/**
+  * @brief DMA I2S receive process half complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  HAL_I2S_RxHalfCpltCallback(hi2s); 
+}
+
+/**
+  * @brief DMA I2S communication error callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void I2S_DMAError(DMA_HandleTypeDef *hdma)
+{
+  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  hi2s->TxXferCount = 0;
+  hi2s->RxXferCount = 0;
+
+  hi2s->State= HAL_I2S_STATE_READY;
+
+  hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
+  HAL_I2S_ErrorCallback(hi2s);
+}
+
+/**
+  * @brief Transmit an amount of data in non-blocking mode with Interrupt
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
+{
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2s);
+
+    /* Transmit data */
+    hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+
+    hi2s->TxXferCount--;	
+    
+    if(hi2s->TxXferCount == 0)
+    {
+      /* Disable TXE and ERR interrupt */
+      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+      
+      hi2s->State = HAL_I2S_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2s);
+      HAL_I2S_TxCpltCallback(hi2s);
+    }
+    else
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2s);
+    }
+
+    return HAL_OK;
+  }
+  
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in non-blocking mode with Interrupt
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
+{
+  if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2s);
+
+    /* Receive data */
+    (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
+
+    hi2s->RxXferCount--;
+
+    /* Check if Master Receiver mode is selected */
+    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+    {
+      /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+      access to the SPI_SR register. */ 
+      __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+    }
+
+    if(hi2s->RxXferCount == 0)
+    {
+      /* Disable RXNE and ERR interrupt */
+      __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE | I2S_IT_ERR);
+
+      hi2s->State = HAL_I2S_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2s);
+
+      HAL_I2S_RxCpltCallback(hi2s);
+    }
+    else
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2s);
+    }
+
+    return HAL_OK; 
+  }
+  else
+  {
+    return HAL_BUSY; 
+  } 
+}
+
+/**
+  * @brief This function handles I2S Communication Timeout.
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param Flag: Flag checked
+  * @param State: Value of the flag expected
+  * @param Timeout: Duration of the timeout
+  * @retval HAL status
+  */
+HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
+{
+  uint32_t timeout = 0;
+  
+  timeout = HAL_GetTick() + Timeout;
+  
+  /* Wait until flag is set */
+  if(Status == RESET)
+  {
+    while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
+    {
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Set the I2S State ready */
+          hi2s->State= HAL_I2S_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2s);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  else
+  {
+    while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
+    {
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Set the I2S State ready */
+          hi2s->State= HAL_I2S_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2s);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+  
+#endif /* HAL_I2S_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,446 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_i2s.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of I2S HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_I2S_H
+#define __STM32F4xx_HAL_I2S_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"  
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2S
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** 
+  * @brief I2S Init structure definition  
+  */
+typedef struct
+{
+  uint32_t Mode;         /*!< Specifies the I2S operating mode.
+                              This parameter can be a value of @ref I2S_Mode */
+
+  uint32_t Standard;     /*!< Specifies the standard used for the I2S communication.
+                              This parameter can be a value of @ref I2S_Standard */
+
+  uint32_t DataFormat;   /*!< Specifies the data format for the I2S communication.
+                              This parameter can be a value of @ref I2S_Data_Format */
+
+  uint32_t MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
+                              This parameter can be a value of @ref I2S_MCLK_Output */
+
+  uint32_t AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
+                              This parameter can be a value of @ref I2S_Audio_Frequency */
+
+  uint32_t CPOL;         /*!< Specifies the idle state of the I2S clock.
+                              This parameter can be a value of @ref I2S_Clock_Polarity */
+
+  uint32_t ClockSource;  /*!< Specifies the I2S Clock Source.
+                              This parameter can be a value of @ref I2S_Clock_Source */
+
+  uint32_t FullDuplexMode;  /*!< Specifies the I2S FullDuplex mode.
+                                 This parameter can be a value of @ref I2S_FullDuplex_Mode */
+
+}I2S_InitTypeDef;
+
+/** 
+  * @brief  HAL State structures definition
+  */ 
+typedef enum
+{
+  HAL_I2S_STATE_RESET      = 0x00,  /*!< I2S not yet initialized or disabled                */
+  HAL_I2S_STATE_READY      = 0x01,  /*!< I2S initialized and ready for use                  */
+  HAL_I2S_STATE_BUSY       = 0x02,  /*!< I2S internal process is ongoing                    */
+  HAL_I2S_STATE_BUSY_TX    = 0x12,  /*!< Data Transmission process is ongoing               */
+  HAL_I2S_STATE_BUSY_RX    = 0x22,  /*!< Data Reception process is ongoing                  */
+  HAL_I2S_STATE_BUSY_TX_RX = 0x32,  /*!< Data Transmission and Reception process is ongoing */
+  HAL_I2S_STATE_TIMEOUT    = 0x03,  /*!< I2S timeout state                                  */
+  HAL_I2S_STATE_ERROR      = 0x04   /*!< I2S error state                                    */
+
+}HAL_I2S_StateTypeDef;
+
+/** 
+  * @brief  HAL I2S Error Code structure definition  
+  */ 
+typedef enum
+{
+  HAL_I2S_ERROR_NONE      = 0x00,    /*!< No error                    */
+  HAL_I2S_ERROR_UDR       = 0x01,    /*!< I2S Underrun error          */
+  HAL_I2S_ERROR_OVR       = 0x02,    /*!< I2S Overrun error           */
+  HAL_I2SEX_ERROR_UDR     = 0x04,    /*!< I2S extended Underrun error */
+  HAL_I2SEX_ERROR_OVR     = 0x08,    /*!< I2S extended Overrun error  */
+  HAL_I2S_ERROR_FRE       = 0x10,    /*!< I2S Frame format error      */
+  HAL_I2S_ERROR_DMA       = 0x20     /*!< DMA transfer error          */
+}HAL_I2S_ErrorTypeDef;
+
+/** 
+  * @brief I2S handle Structure definition  
+  */
+typedef struct
+{
+  SPI_TypeDef                *Instance;    /* I2S registers base address        */
+
+  I2S_InitTypeDef            Init;         /* I2S communication parameters      */
+  
+  uint16_t                   *pTxBuffPtr;  /* Pointer to I2S Tx transfer buffer */
+  
+  __IO uint16_t              TxXferSize;   /* I2S Tx transfer size              */
+  
+  __IO uint16_t              TxXferCount;  /* I2S Tx transfer Counter           */
+  
+  uint16_t                   *pRxBuffPtr;  /* Pointer to I2S Rx transfer buffer */
+  
+  __IO uint16_t              RxXferSize;   /* I2S Rx transfer size              */
+  
+  __IO uint16_t              RxXferCount;  /* I2S Rx transfer counter           */
+
+  DMA_HandleTypeDef          *hdmatx;      /* I2S Tx DMA handle parameters      */
+
+  DMA_HandleTypeDef          *hdmarx;      /* I2S Rx DMA handle parameters      */
+  
+  __IO HAL_LockTypeDef       Lock;         /* I2S locking object                */
+  
+  __IO HAL_I2S_StateTypeDef  State;        /* I2S communication state           */
+  
+  __IO HAL_I2S_ErrorTypeDef  ErrorCode;    /* I2S Error code                    */
+
+}I2S_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2S_Exported_Constants
+  * @{
+  */
+#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE)) 
+
+/** @defgroup I2S_Clock_Source 
+  * @{
+  */
+#define I2S_CLOCK_PLL                     ((uint32_t)0x00000000)
+#define I2S_CLOCK_EXTERNAL                ((uint32_t)0x00000001)
+
+#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
+                                   ((CLOCK) == I2S_CLOCK_PLL))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Mode 
+  * @{
+  */
+#define I2S_MODE_SLAVE_TX                ((uint32_t)0x00000000)
+#define I2S_MODE_SLAVE_RX                ((uint32_t)0x00000100)
+#define I2S_MODE_MASTER_TX               ((uint32_t)0x00000200)
+#define I2S_MODE_MASTER_RX               ((uint32_t)0x00000300)
+
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX)  || \
+                           ((MODE) == I2S_MODE_SLAVE_RX)  || \
+                           ((MODE) == I2S_MODE_MASTER_TX) || \
+                           ((MODE) == I2S_MODE_MASTER_RX))
+/**
+  * @}
+  */
+  
+/** @defgroup I2S_Standard 
+  * @{
+  */
+#define I2S_STANDARD_PHILIPS             ((uint32_t)0x00000000)
+#define I2S_STANDARD_MSB                 ((uint32_t)0x00000010)
+#define I2S_STANDARD_LSB                 ((uint32_t)0x00000020)
+#define I2S_STANDARD_PCM_SHORT           ((uint32_t)0x00000030)
+#define I2S_STANDARD_PCM_LONG            ((uint32_t)0x000000B0)
+
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS)  || \
+                                   ((STANDARD) == I2S_STANDARD_MSB)       || \
+                                   ((STANDARD) == I2S_STANDARD_LSB)       || \
+                                   ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
+                                   ((STANDARD) == I2S_STANDARD_PCM_LONG))
+/** @defgroup I2S_Legacy 
+  * @{
+  */
+#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/** @defgroup I2S_Data_Format 
+  * @{
+  */
+#define I2S_DATAFORMAT_16B               ((uint32_t)0x00000000)
+#define I2S_DATAFORMAT_16B_EXTENDED      ((uint32_t)0x00000001)
+#define I2S_DATAFORMAT_24B               ((uint32_t)0x00000003)
+#define I2S_DATAFORMAT_32B               ((uint32_t)0x00000005)
+
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B)          || \
+                                    ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
+                                    ((FORMAT) == I2S_DATAFORMAT_24B)          || \
+                                    ((FORMAT) == I2S_DATAFORMAT_32B))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_MCLK_Output 
+  * @{
+  */
+#define I2S_MCLKOUTPUT_ENABLE           ((uint32_t)SPI_I2SPR_MCKOE)
+#define I2S_MCLKOUTPUT_DISABLE          ((uint32_t)0x00000000)
+
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
+                                    ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Audio_Frequency 
+  * @{
+  */
+#define I2S_AUDIOFREQ_192K               ((uint32_t)192000)
+#define I2S_AUDIOFREQ_96K                ((uint32_t)96000)
+#define I2S_AUDIOFREQ_48K                ((uint32_t)48000)
+#define I2S_AUDIOFREQ_44K                ((uint32_t)44100)
+#define I2S_AUDIOFREQ_32K                ((uint32_t)32000)
+#define I2S_AUDIOFREQ_22K                ((uint32_t)22050)
+#define I2S_AUDIOFREQ_16K                ((uint32_t)16000)
+#define I2S_AUDIOFREQ_11K                ((uint32_t)11025)
+#define I2S_AUDIOFREQ_8K                 ((uint32_t)8000)
+#define I2S_AUDIOFREQ_DEFAULT            ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
+                                  ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
+                                  ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_FullDuplex_Mode 
+  * @{
+  */
+#define I2S_FULLDUPLEXMODE_DISABLE                   ((uint32_t)0x00000000)
+#define I2S_FULLDUPLEXMODE_ENABLE                    ((uint32_t)0x00000001)
+
+#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
+                                      ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Clock_Polarity 
+  * @{
+  */
+#define I2S_CPOL_LOW                    ((uint32_t)0x00000000)
+#define I2S_CPOL_HIGH                   ((uint32_t)SPI_I2SCFGR_CKPOL)
+
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
+                           ((CPOL) == I2S_CPOL_HIGH))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Interrupt_configuration_definition
+  * @{
+  */
+#define I2S_IT_TXE                      SPI_CR2_TXEIE
+#define I2S_IT_RXNE                     SPI_CR2_RXNEIE
+#define I2S_IT_ERR                      SPI_CR2_ERRIE
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Flag_definition 
+  * @{
+  */
+#define I2S_FLAG_TXE                    SPI_SR_TXE
+#define I2S_FLAG_RXNE                   SPI_SR_RXNE
+
+#define I2S_FLAG_UDR                    SPI_SR_UDR
+#define I2S_FLAG_OVR                    SPI_SR_OVR
+#define I2S_FLAG_FRE                    SPI_SR_FRE
+
+#define I2S_FLAG_CHSIDE                 SPI_SR_CHSIDE
+#define I2S_FLAG_BSY                    SPI_SR_BSY
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+
+
+/** @brief Reset I2S handle state
+  * @param  __HANDLE__: specifies the I2S Handle.
+  * @retval None
+  */
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
+
+/** @brief  Enable or disable the specified SPI peripheral (in I2S mode).
+  * @param  __HANDLE__: specifies the I2S Handle. 
+  * @retval None
+  */
+#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
+#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
+
+/** @brief  Enable or disable the specified I2S interrupts.
+  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  *         This parameter can be one of the following values:
+  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg I2S_IT_ERR: Error interrupt enable
+  * @retval None
+  */  
+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
+ 
+/** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
+  * @param  __HANDLE__: specifies the I2S Handle.
+  *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
+  * @param  __INTERRUPT__: specifies the I2S interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg I2S_IT_ERR: Error interrupt enable
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Checks whether the specified I2S flag is set or not.
+  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
+  *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
+  *            @arg I2S_FLAG_UDR: Underrun flag
+  *            @arg I2S_FLAG_OVR: Overrun flag
+  *            @arg I2S_FLAG_FRE: Frame error flag
+  *            @arg I2S_FLAG_CHSIDE: Channel Side flag
+  *            @arg I2S_FLAG_BSY: Busy flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the I2S OVR pending flag.
+  * @param  __HANDLE__: specifies the I2S Handle.
+  * @retval None
+  */
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
+                                               (__HANDLE__)->Instance->SR;}while(0)
+/** @brief Clears the I2S UDR pending flag.
+  * @param  __HANDLE__: specifies the I2S Handle.
+  * @retval None
+  */
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
+
+/* Include I2S Extension module */
+#include "stm32f4xx_hal_i2s_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
+
+/* I/O operation functions  *****************************************************/
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
+
+/* Peripheral Control and State functions  **************************************/
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
+HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
+
+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
+void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
+
+void              I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
+void              I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); 
+void              I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
+void              I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+void              I2S_DMAError(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_I2S_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,751 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_i2s_ex.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   I2S HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of I2S extension peripheral:
+  *           + Extension features Functions
+  *         
+  @verbatim
+  ==============================================================================
+                    ##### I2S Extension features #####
+  ============================================================================== 
+  [..]
+     (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving 
+         data simultaneously using two data lines. Each SPI peripheral has an extended block 
+         called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3).
+     (#) The extension block is not a full SPI IP, it is used only as I2S slave to
+         implement full duplex mode. The extension block uses the same clock sources
+         as its master.
+
+     (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
+
+     [..]
+       (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where 
+         I2Sx can be I2S2 or I2S3.
+
+                  ##### How to use this driver #####
+ ===============================================================================
+ [..]    
+   Three operation modes are available within this driver :     
+  
+   *** Polling mode IO operation ***
+   =================================
+   [..]    
+     (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive() 
+   
+   *** Interrupt mode IO operation ***    
+   ===================================
+   [..]    
+     (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT() 
+     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback 
+     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback 
+     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_RxCpltCallback                                      
+     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_ErrorCallback
+
+   *** DMA mode IO operation ***    
+   ==============================
+   [..] 
+     (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA() 
+     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback 
+     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback 
+     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_RxCpltCallback                                     
+     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_ErrorCallback
+     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()      
+     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()  
+     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()  
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2SEx 
+  * @brief I2S HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2SEx_Private_Functions
+  * @{
+  */
+
+/** @defgroup I2SEx_Group1 Extension features functions 
+  *  @brief   Extension features functions
+  *
+@verbatim    
+ ===============================================================================
+                       ##### Extension features Functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the I2S data 
+    transfers.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode : The communication is performed in the polling mode. 
+            The status of all data processing is returned by the same function 
+            after finishing transfer.  
+       (++) No-Blocking mode : The communication is performed using Interrupts 
+            or DMA. These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the 
+            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when 
+            using DMA mode.
+
+    (#) Blocking mode functions are :
+        (++) HAL_I2S_TransmitReceive()
+        
+    (#) No-Blocking mode functions with Interrupt are :
+        (++) HAL_I2S_TransmitReceive_IT()
+
+    (#) No-Blocking mode functions with DMA are :
+        (++) HAL_I2S_TransmitReceive_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_I2S_TxCpltCallback()
+        (++) HAL_I2S_RxCpltCallback()
+        (++) HAL_I2S_ErrorCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Full-Duplex Transmit/Receive data in blocking mode.
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param pTxData: a 16-bit pointer to the Transmit data buffer.
+  * @param pRxData: a 16-bit pointer to the Receive data buffer.
+  * @param Size: number of data sample to be sent:
+  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *       configuration phase, the Size parameter means the number of 16-bit data length 
+  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
+  *       the Size parameter means the number of 16-bit data length. 
+  * @param Timeout: Timeout duration
+  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
+  *       between Master and Slave(example: audio streaming).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t timeout = 0;
+  uint32_t tmp1 = 0, tmp2 = 0;   
+ 
+  if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) 
+  {
+    return  HAL_ERROR;
+  }
+
+  /* Check the I2S State */
+  if(hi2s->State == HAL_I2S_STATE_READY)
+  {  
+    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+    tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); 
+    /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended 
+       is selected during the I2S configuration phase, the Size parameter means the number
+       of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data 
+       frame is selected the Size parameter means the number of 16-bit data length. */
+    if((tmp1 == I2S_DATAFORMAT_24B)|| \
+       (tmp2 == I2S_DATAFORMAT_32B))
+    {
+      hi2s->TxXferSize = Size*2;
+      hi2s->TxXferCount = Size*2;
+      hi2s->RxXferSize = Size*2;
+      hi2s->RxXferCount = Size*2;
+    }
+    else
+    {
+      hi2s->TxXferSize = Size;
+      hi2s->TxXferCount = Size;
+      hi2s->RxXferSize = Size;
+      hi2s->RxXferCount = Size;
+    }
+    
+    /* Process Locked */
+    __HAL_LOCK(hi2s);
+    
+    /* Set the I2S State busy TX/RX */
+    hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+    
+    tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+    tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+    /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+    if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
+    { 
+      /* Check if the I2S is already enabled: The I2S is kept enabled at the end of transaction
+      to avoid the clock de-synchronization between Master and Slave. */ 
+      if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+      {
+        /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
+        I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
+
+        /* Enable I2Sx peripheral */
+        __HAL_I2S_ENABLE(hi2s);
+      }
+      
+      while(hi2s->TxXferCount > 0)
+      {
+        /* Wait until TXE flag is set */
+        if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+        hi2s->Instance->DR = (*pTxData++);
+
+        /* Wait until RXNE flag is set */
+        timeout = HAL_GetTick() + Timeout;
+
+        while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) != SPI_SR_RXNE)
+        {
+          if(Timeout != HAL_MAX_DELAY)
+          {
+            if(HAL_GetTick() >= timeout)
+            {
+              /* Process Unlocked */
+              __HAL_UNLOCK(hi2s);
+
+              return HAL_TIMEOUT;
+            }
+          }
+        }
+        (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
+        
+        hi2s->TxXferCount--;
+        hi2s->RxXferCount--;
+      }
+    }
+    /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
+    else
+    {
+      /* Check if the I2S is already enabled */ 
+      if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+      {
+        /* Enable I2S peripheral before the I2Sext*/
+        __HAL_I2S_ENABLE(hi2s);
+
+        /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
+        I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
+      }
+      else
+      {
+        /* Check if Master Receiver mode is selected */
+        if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+        {
+          /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+          access to the SPI_SR register. */ 
+          __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+        }
+      }
+      while(hi2s->TxXferCount > 0)
+      {
+        /* Wait until TXE flag is set */
+        timeout = HAL_GetTick() + Timeout;
+
+        while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) != SPI_SR_TXE)
+        {
+          if(Timeout != HAL_MAX_DELAY)
+          {
+            if(HAL_GetTick() >= timeout)
+            {
+              /* Process Unlocked */
+              __HAL_UNLOCK(hi2s);
+
+              return HAL_TIMEOUT;
+            }
+          }
+        }
+        I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
+        
+        /* Wait until RXNE flag is set */
+        if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+        (*pRxData++) = hi2s->Instance->DR;
+
+        hi2s->TxXferCount--;
+        hi2s->RxXferCount--;
+      }
+    }
+
+    /* Set the I2S State ready */
+    hi2s->State = HAL_I2S_STATE_READY; 
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt 
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param pTxData: a 16-bit pointer to the Transmit data buffer.
+  * @param pRxData: a 16-bit pointer to the Receive data buffer.
+  * @param Size: number of data sample to be sent:
+  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *       configuration phase, the Size parameter means the number of 16-bit data length 
+  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
+  *       the Size parameter means the number of 16-bit data length. 
+  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
+  *       between Master and Slave(example: audio streaming).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
+{
+  uint32_t tmp1 = 0, tmp2 = 0;
+  
+  if(hi2s->State == HAL_I2S_STATE_READY)
+  {
+    if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) 
+    {
+      return  HAL_ERROR;
+    }
+
+    hi2s->pTxBuffPtr = pTxData;
+    hi2s->pRxBuffPtr = pRxData;
+
+    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+    tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+    /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended 
+       is selected during the I2S configuration phase, the Size parameter means the number
+       of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data 
+       frame is selected the Size parameter means the number of 16-bit data length. */
+    if((tmp1 == I2S_DATAFORMAT_24B)||\
+       (tmp2 == I2S_DATAFORMAT_32B))
+    {
+      hi2s->TxXferSize = Size*2;
+      hi2s->TxXferCount = Size*2;
+      hi2s->RxXferSize = Size*2;
+      hi2s->RxXferCount = Size*2;
+    }  
+    else
+    {
+      hi2s->TxXferSize = Size;
+      hi2s->TxXferCount = Size;
+      hi2s->RxXferSize = Size;
+      hi2s->RxXferCount = Size;
+    }
+    
+    /* Process Locked */
+    __HAL_LOCK(hi2s);
+    
+    hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+    tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+    tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+    /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+    if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
+    { 
+      /* Enable I2Sext RXNE and ERR interrupts */
+      I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_RXNE | I2S_IT_ERR);
+
+      /* Enable I2Sx TXE and ERR interrupts */
+      __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+      /* Check if the I2S is already enabled */ 
+      if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+      {
+        /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
+        I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
+
+        /* Enable I2Sx peripheral */
+        __HAL_I2S_ENABLE(hi2s);
+      }
+    }
+    /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
+    else
+    {
+      /* Enable I2Sext TXE and ERR interrupts */
+      I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_TXE |I2S_IT_ERR);
+
+      /* Enable I2Sext RXNE and ERR interrupts */
+      __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+      /* Check if the I2S is already enabled */ 
+      if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+      {
+        /* Check if the I2S_MODE_MASTER_RX is selected */
+        if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) 
+        {
+          /* Prepare the First Data before enabling the I2S */
+          if(hi2s->TxXferCount != 0)
+          {
+            /* Transmit First data */
+            I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
+            hi2s->TxXferCount--;	
+
+            if(hi2s->TxXferCount == 0)
+            {
+              /* Disable I2Sext TXE interrupt */
+              I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
+            }
+          }
+        }
+        /* Enable I2S peripheral */
+        __HAL_I2S_ENABLE(hi2s);
+        
+        /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
+        I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
+      }
+    }
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+/**
+  * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA  
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param pTxData: a 16-bit pointer to the Transmit data buffer.
+  * @param pRxData: a 16-bit pointer to the Receive data buffer.
+  * @param Size: number of data sample to be sent:
+  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *       configuration phase, the Size parameter means the number of 16-bit data length 
+  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
+  *       the Size parameter means the number of 16-bit data length. 
+  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
+  *       between Master and Slave(example: audio streaming).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
+{
+  uint32_t *tmp;
+  uint32_t tmp1 = 0, tmp2 = 0;
+    
+  if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) 
+  {
+    return  HAL_ERROR;
+  }
+
+  if(hi2s->State == HAL_I2S_STATE_READY)
+  {
+    hi2s->pTxBuffPtr = pTxData;
+    hi2s->pRxBuffPtr = pRxData;
+
+    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+    tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+    /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended 
+       is selected during the I2S configuration phase, the Size parameter means the number
+       of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data 
+       frame is selected the Size parameter means the number of 16-bit data length. */
+    if((tmp1 == I2S_DATAFORMAT_24B)||\
+       (tmp2 == I2S_DATAFORMAT_32B))
+    {
+      hi2s->TxXferSize = Size*2;
+      hi2s->TxXferCount = Size*2;
+      hi2s->RxXferSize = Size*2;
+      hi2s->RxXferCount = Size*2;
+    }
+    else
+    {
+      hi2s->TxXferSize = Size;
+      hi2s->TxXferCount = Size;
+      hi2s->RxXferSize = Size;
+      hi2s->RxXferCount = Size;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2s);
+
+    hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+    /* Set the I2S Rx DMA Half transfert complete callback */
+    hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
+
+    /* Set the I2S Rx DMA transfert complete callback */
+    hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
+
+    /* Set the I2S Rx DMA error callback */
+    hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
+
+    /* Set the I2S Tx DMA Half transfert complete callback */
+    hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
+
+    /* Set the I2S Tx DMA transfert complete callback */
+    hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
+
+    /* Set the I2S Tx DMA error callback */
+    hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
+
+    tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+    tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+    /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+    if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
+    {
+      /* Enable the Rx DMA Stream */
+      tmp = (uint32_t*)&pRxData;
+      HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
+
+      /* Enable Rx DMA Request */  
+      I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
+
+      /* Enable the Tx DMA Stream */
+      tmp = (uint32_t*)&pTxData;
+      HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
+
+      /* Enable Tx DMA Request */  
+      hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+
+      /* Check if the I2S is already enabled */ 
+      if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+      {
+        /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
+        I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
+
+        /* Enable I2S peripheral after the I2Sext */
+        __HAL_I2S_ENABLE(hi2s);
+      }
+    }
+    else
+    {
+      /* Enable the Tx DMA Stream */
+      tmp = (uint32_t*)&pTxData;
+      HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
+
+      /* Enable Tx DMA Request */  
+      I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
+
+      /* Enable the Rx DMA Stream */
+      tmp = (uint32_t*)&pRxData;
+      HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
+
+      /* Enable Rx DMA Request */  
+      hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+
+      /* Check if the I2S is already enabled */ 
+      if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+      {
+        /* Enable I2S peripheral before the I2Sext */
+        __HAL_I2S_ENABLE(hi2s);
+
+        /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
+        I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
+      }
+      else
+      {
+        /* Check if Master Receiver mode is selected */
+        if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+        {
+          /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+          access to the SPI_SR register. */ 
+          __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+        }
+      }
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt 
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s)
+{
+  uint32_t tmp1 = 0, tmp2 = 0;
+  
+  if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2s);
+
+    tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+    tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+    /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+    if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
+    {
+      if(hi2s->TxXferCount != 0)
+      {
+        if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE) != RESET)
+        {        
+          /* Transmit data */
+          hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+          hi2s->TxXferCount--;
+
+          if(hi2s->TxXferCount == 0)
+          {
+            /* Disable TXE interrupt */
+            __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_TXE);
+          }
+        }
+      }
+
+      if(hi2s->RxXferCount != 0)
+      {
+        if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) == SPI_SR_RXNE)
+        {
+          /* Receive data */
+          (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
+          hi2s->RxXferCount--;
+
+          if(hi2s->RxXferCount == 0)
+          {
+            /* Disable I2Sext RXNE interrupt */
+            I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_RXNE;
+          }
+        }
+      }
+    }
+    /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */ 
+    else
+    {
+      if(hi2s->TxXferCount != 0)
+      {
+        if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) == SPI_SR_TXE)
+        {        
+          /* Transmit data */
+          I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
+          hi2s->TxXferCount--;
+
+          if(hi2s->TxXferCount == 0)
+          {
+            /* Disable I2Sext TXE interrupt */
+            I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
+
+            HAL_I2S_TxCpltCallback(hi2s);
+          }
+        }
+      }
+      if(hi2s->RxXferCount != 0)
+      {
+        if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE) != RESET)
+        {
+          /* Receive data */
+          (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
+          hi2s->RxXferCount--;
+
+          if(hi2s->RxXferCount == 0)
+          {
+            /* Disable RXNE interrupt */
+            __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE);
+
+            HAL_I2S_RxCpltCallback(hi2s);
+          }
+        }
+      }
+    }
+
+    tmp1 = hi2s->RxXferCount;
+    tmp2 = hi2s->TxXferCount;
+    if((tmp1 == 0) && (tmp2 == 0))
+    {
+      /* Disable I2Sx ERR interrupt */
+      __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_ERR);
+      /* Disable I2Sext ERR interrupt */
+      I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_ERR;
+      
+      hi2s->State = HAL_I2S_STATE_READY; 
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY; 
+  }
+}
+
+/**
+  * @}
+  */
+  
+#endif /* HAL_I2S_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,87 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_i2s_ex.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of I2S HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_I2S_EX_H
+#define __STM32F4xx_HAL_I2S_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"  
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2SEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/* Exported constants --------------------------------------------------------*/  
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Extended features functions **************************************************/
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout);
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
+
+HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s);
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_I2S_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1300 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_irda.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   IRDA HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the IrDA SIR ENDEC block (IrDA):
+  *           + Initialization and de-initialization methods
+  *           + IO operation methods
+  *           + Peripheral Control methods
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    The IRDA HAL driver can be used as follows:
+    
+    (#) Declare a IRDA_HandleTypeDef handle structure.
+    (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
+        (##) Enable the USARTx interface clock.
+        (##) IRDA pins configuration:
+            (+++) Enable the clock for the IRDA GPIOs.
+            (+++) Configure these IRDA pins as alternate function pull-up.
+        (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
+             and HAL_IRDA_Receive_IT() APIs):
+            (+++) Configure the USARTx interrupt priority.
+            (+++) Enable the NVIC USART IRQ handle.
+        (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
+             and HAL_IRDA_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx stream.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.                
+            (+++) Configure the DMA Tx/Rx Stream.
+            (+++) Associate the initilalized DMA handle to the IRDA DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
+
+    (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler 
+        and Mode(Receiver/Transmitter) in the hirda Init structure.
+
+    (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
+        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+            by calling the customed HAL_IRDA_MspInit() API.
+    -@@- The specific IRDA interrupts (Transmission complete interrupt, 
+        RXNE interrupt and Error Interrupts) will be managed using the macros
+        __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+        
+    (#) Three operation modes are available within this driver :
+             
+    *** Polling mode IO operation ***
+    =================================
+    [..]    
+      (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit() 
+      (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
+       
+    *** Interrupt mode IO operation ***    
+    ===================================
+    [..]    
+      (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT() 
+      (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can 
+           add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
+      (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT() 
+      (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can 
+           add his own code by customization of function pointer HAL_IRDA_RxCpltCallback                                      
+      (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can 
+           add his own code by customization of function pointer HAL_IRDA_ErrorCallback
+
+    *** DMA mode IO operation ***    
+    =============================
+    [..]
+      (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA() 
+      (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can 
+           add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
+      (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA() 
+      (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can 
+           add his own code by customization of function pointer HAL_IRDA_RxCpltCallback                                      
+      (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can 
+           add his own code by customization of function pointer HAL_IRDA_ErrorCallback    
+
+    *** IRDA HAL driver macros list ***
+    ===================================
+    [..]
+      Below the list of most used macros in IRDA HAL driver.
+       
+     (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral 
+     (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral     
+     (+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not
+     (+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag
+     (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt
+     (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt
+      
+     (@) You can refer to the IRDA HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup IRDA 
+  * @brief HAL IRDA module driver
+  * @{
+  */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define IRDA_TIMEOUT_VALUE  22000
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup IRDA_Private_Functions
+  * @{
+  */
+
+/** @defgroup IRDA_Group1 IrDA Initialization and de-initialization functions 
+  *  @brief    Initialization and Configuration functions 
+  *
+@verbatim 
+
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy 
+    in IrDA mode.
+      (+) For the asynchronous mode only these parameters can be configured: 
+        (++) BaudRate
+        (++) WordLength 
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+             Depending on the frame length defined by the M bit (8-bits or 9-bits),
+             please refer to Reference manual for possible IRDA frame formats.
+        (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
+             not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
+             specification specifies a minimum of 10 ms delay between transmission and 
+             reception (IrDA is a half duplex protocol).
+        (++) Mode: Receiver/transmitter modes
+        (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
+    [..]
+    The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures
+    are available in reference manual).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the IRDA mode according to the specified
+  *         parameters in the IRDA_InitTypeDef and create the associated handle.
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
+{
+  /* Check the IRDA handle allocation */
+  if(hirda == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the IRDA instance parameters */
+  assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+  /* Check the IRDA mode parameter in the IRDA handle */
+  assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode)); 
+  
+  if(hirda->State == HAL_IRDA_STATE_RESET)
+  {
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_IRDA_MspInit(hirda);
+  }
+  
+  hirda->State = HAL_IRDA_STATE_BUSY;
+  
+  /* Disable the IRDA peripheral */
+  __IRDA_DISABLE(hirda);
+  
+  /* Set the IRDA communication parameters */
+  IRDA_SetConfig(hirda);
+  
+  /* In IrDA mode, the following bits must be kept cleared: 
+     - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+     - SCEN and HDSEL bits in the USART_CR3 register.*/
+  hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN);
+  hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL);
+  
+  /* Enable the IRDA peripheral */
+  __IRDA_ENABLE(hirda);
+  
+  /* Set the prescaler */
+  MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
+  
+  /* Configure the IrDA mode */
+  MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.IrDAMode);
+  
+  /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+  hirda->Instance->CR3 |= USART_CR3_IREN;
+  
+  /* Initialize the IRDA state*/
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+  hirda->State= HAL_IRDA_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the IRDA peripheral 
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
+{
+  /* Check the IRDA handle allocation */
+  if(hirda == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_IRDA_INSTANCE(hirda->Instance)); 
+  
+  hirda->State = HAL_IRDA_STATE_BUSY;
+  
+  /* DeInit the low level hardware */
+  HAL_IRDA_MspDeInit(hirda);
+  
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+  hirda->State = HAL_IRDA_STATE_RESET; 
+
+  /* Release Lock */
+  __HAL_UNLOCK(hirda);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  IRDA MSP Init.
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval None
+  */
+ __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_IRDA_MspInit could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @brief  IRDA MSP DeInit.
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval None
+  */
+ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_IRDA_MspDeInit could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Group2 IO operation functions 
+  *  @brief   IRDA Transmit/Receive functions 
+  *
+@verbatim   
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================  
+    This subsection provides a set of functions allowing to manage the IRDA data transfers.
+    [..]
+    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
+    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver 
+    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
+    While receiving data, transmission should be avoided as the data to be transmitted
+    could be corrupted.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode: The communication is performed in polling mode. 
+            The HAL status of all data processing is returned by the same function 
+            after finishing transfer.  
+       (++) No-Blocking mode: The communication is performed using Interrupts 
+           or DMA, These APIs return the HAL status.
+           The end of the data processing will be indicated through the 
+           dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when 
+           using DMA mode.
+           The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks 
+           will be executed respectivelly at the end of the transmit or Receive process
+           The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
+
+    (#) Blocking mode API's are :
+        (++) HAL_IRDA_Transmit()
+        (++) HAL_IRDA_Receive() 
+        
+    (#) Non Blocking mode APIs with Interrupt are :
+        (++) HAL_IRDA_Transmit_IT()
+        (++) HAL_IRDA_Receive_IT()
+        (++) HAL_IRDA_IRQHandler()
+
+    (#) Non Blocking mode functions with DMA are :
+        (++) HAL_IRDA_Transmit_DMA()
+        (++) HAL_IRDA_Receive_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_IRDA_TxCpltCallback()
+        (++) HAL_IRDA_RxCpltCallback()
+        (++) HAL_IRDA_ErrorCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sends an amount of data in blocking mode.
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @param  Timeout: Specify timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+  uint32_t  tmp1 = 0;
+  
+  tmp1 = hirda->State; 
+  if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX))
+  {
+    if((pData == NULL) || (Size == 0)) 
+    {
+      return  HAL_ERROR;
+    }
+    
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+    
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE; 
+    if(hirda->State == HAL_IRDA_STATE_BUSY_RX) 
+    {
+      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      hirda->State = HAL_IRDA_STATE_BUSY_TX;
+    }
+   
+    hirda->TxXferSize = Size;
+    hirda->TxXferCount = Size;
+    while(hirda->TxXferCount > 0)
+    {
+      hirda->TxXferCount--;
+      if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+      {
+        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        { 
+          return HAL_TIMEOUT;
+        }
+        tmp = (uint16_t*) pData;
+        hirda->Instance->DR = (*tmp & (uint16_t)0x01FF);
+        if(hirda->Init.Parity == IRDA_PARITY_NONE)
+        {
+          pData +=2;
+        }
+        else
+        {
+          pData +=1;
+        }
+      } 
+      else
+      {
+        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+        hirda->Instance->DR = (*pData++ & (uint8_t)0xFF);
+      }
+    }
+    
+    if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK)
+    { 
+      return HAL_TIMEOUT;
+    }
+    
+    if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) 
+    {
+      hirda->State = HAL_IRDA_STATE_BUSY_RX;
+    }
+    else
+    {
+      hirda->State = HAL_IRDA_STATE_READY;
+    }
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;   
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in blocking mode. 
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be received
+  * @param  Timeout: Specify timeout value    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{ 
+  uint16_t* tmp;
+  uint32_t  tmp1 = 0;
+  
+  tmp1 = hirda->State; 
+  if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX))
+  {
+    if((pData == NULL) || (Size == 0)) 
+    {
+      return  HAL_ERROR;
+    }
+    
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+    
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE; 
+    if(hirda->State == HAL_IRDA_STATE_BUSY_TX) 
+    {
+      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      hirda->State = HAL_IRDA_STATE_BUSY_RX;
+    }
+    hirda->RxXferSize = Size;
+    hirda->RxXferCount = Size;
+    /* Check the remain data to be received */
+    while(hirda->RxXferCount > 0)
+    {
+      hirda->RxXferCount--;
+      if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+      {
+        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        { 
+          return HAL_TIMEOUT;
+        }
+        tmp = (uint16_t*) pData ;
+        if(hirda->Init.Parity == IRDA_PARITY_NONE)
+        {
+          *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FF);
+           pData +=2;
+        }
+        else
+        {
+          *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FF);
+          pData +=1;
+        }
+      } 
+      else
+      {
+        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        { 
+          return HAL_TIMEOUT;
+        }
+        if(hirda->Init.Parity == IRDA_PARITY_NONE)
+        {
+          *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FF);
+        }
+        else
+        {
+          *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x007F);
+        }
+      }
+    }
+    if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) 
+    {
+      hirda->State = HAL_IRDA_STATE_BUSY_TX;
+    }
+    else
+    {
+      hirda->State = HAL_IRDA_STATE_READY;
+    }
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;   
+  }
+}
+
+/**
+  * @brief  Send an amount of data in non blocking mode. 
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+  uint32_t  tmp1 = 0;
+  
+  tmp1 = hirda->State;   
+  if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX))
+  {
+    if((pData == NULL) || (Size == 0)) 
+    {
+      return HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+    
+    hirda->pTxBuffPtr = pData;
+    hirda->TxXferSize = Size;
+    hirda->TxXferCount = Size;
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE; 
+    if(hirda->State == HAL_IRDA_STATE_BUSY_RX) 
+    {
+      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      hirda->State = HAL_IRDA_STATE_BUSY_TX;
+    }
+    
+    /* Enable the IRDA Parity Error Interrupt */
+    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
+    
+    /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+    
+    /* Enable the IRDA Transmit Complete Interrupt */
+    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;   
+  }
+}
+
+/**
+  * @brief  Receives an amount of data in non blocking mode. 
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+  uint32_t  tmp1 = 0;
+  
+  tmp1 = hirda->State;   
+  if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX))
+  {
+    if((pData == NULL) || (Size == 0)) 
+    {
+      return HAL_ERROR;
+    }
+    
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+    
+    hirda->pRxBuffPtr = pData;
+    hirda->RxXferSize = Size;
+    hirda->RxXferCount = Size;
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE; 
+    if(hirda->State == HAL_IRDA_STATE_BUSY_TX) 
+    {
+      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      hirda->State = HAL_IRDA_STATE_BUSY_RX;
+    }
+    
+    /* Enable the IRDA Data Register not empty Interrupt */
+    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE); 
+    
+    /* Enable the IRDA Parity Error Interrupt */
+    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
+    
+    /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY; 
+  }
+}
+
+/**
+  * @brief  Sends an amount of data in non blocking mode. 
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+  uint32_t *tmp;
+  uint32_t  tmp1 = 0;
+  
+  tmp1 = hirda->State;   
+  if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX))
+  {
+    if((pData == NULL) || (Size == 0)) 
+    {
+      return HAL_ERROR;
+    }
+    
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+    
+    hirda->pTxBuffPtr = pData;
+    hirda->TxXferSize = Size;
+    hirda->TxXferCount = Size;
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE; 
+    
+    if(hirda->State == HAL_IRDA_STATE_BUSY_RX) 
+    {
+      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      hirda->State = HAL_IRDA_STATE_BUSY_TX;
+    }
+    
+    /* Set the IRDA DMA transfert complete callback */
+    hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
+    
+    /* Set the DMA error callback */
+    hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
+    
+    /* Enable the IRDA transmit DMA Stream */
+    tmp = (uint32_t*)&pData;
+    HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size);
+    
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the USART CR3 register */
+    hirda->Instance->CR3 |= USART_CR3_DMAT;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;   
+  }
+}
+
+/**
+  * @brief  Receives an amount of data in non blocking mode. 
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be received
+  * @note   When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+  uint32_t *tmp;
+  uint32_t  tmp1 = 0;
+  
+  tmp1 = hirda->State; 
+  if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX))
+  {
+    if((pData == NULL) || (Size == 0)) 
+    {
+      return HAL_ERROR;
+    }
+    
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+    
+    hirda->pRxBuffPtr = pData;
+    hirda->RxXferSize = Size;   
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE; 
+    if(hirda->State == HAL_IRDA_STATE_BUSY_TX) 
+    {
+      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      hirda->State = HAL_IRDA_STATE_BUSY_RX;
+    }
+    
+    /* Set the IRDA DMA transfert complete callback */
+    hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
+    
+    /* Set the DMA error callback */
+    hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
+    
+    /* Enable the DMA Stream */
+    tmp = (uint32_t*)&pData;
+    HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size);
+    
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
+       in the USART CR3 register */
+    hirda->Instance->CR3 |= USART_CR3_DMAR;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY; 
+  }
+}
+
+/**
+  * @brief  This function handles IRDA interrupt request.
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval None
+  */
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
+{
+  uint32_t  tmp1 = 0, tmp2 =0;
+  
+  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_PE);
+  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE);
+  /* IRDA parity error interrupt occurred -------------------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET))
+  { 
+    __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_PE);
+    hirda->ErrorCode |= HAL_IRDA_ERROR_PE; 
+  }
+  
+  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_FE);
+  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
+  /* IRDA frame error interrupt occurred --------------------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET))
+  { 
+    __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_FE);
+    hirda->ErrorCode |= HAL_IRDA_ERROR_FE; 
+  }
+  
+  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_NE);
+  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
+  /* IRDA noise error interrupt occurred --------------------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET))
+  { 
+    __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_NE);
+    hirda->ErrorCode |= HAL_IRDA_ERROR_NE; 
+  }
+  
+  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_ORE);
+  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
+  /* IRDA Over-Run interrupt occurred -----------------------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET))
+  { 
+    __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_ORE);
+    hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; 
+  }
+
+  /* Call the Error call Back in case of Errors */
+  if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+  {
+    /* Set the IRDA state ready to be able to start again the process */
+    hirda->State = HAL_IRDA_STATE_READY;
+    HAL_IRDA_ErrorCallback(hirda);
+  }
+
+  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_RXNE);
+  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE);
+  /* IRDA in mode Receiver ---------------------------------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET))
+  { 
+    IRDA_Receive_IT(hirda);
+    __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_IT_RXNE);
+  }
+  
+  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TC);
+  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC);
+  /* IRDA in mode Transmitter ------------------------------------------------*/
+  if((tmp1 != RESET) &&(tmp2 != RESET))
+  {
+    IRDA_Transmit_IT(hirda);
+    __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_IT_TC);
+  }
+}
+
+/**
+  * @brief  Tx Transfer complete callbacks.
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval None
+  */
+ __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_IRDA_TxCpltCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Rx Transfer complete callbacks.
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_IRDA_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief IRDA error callbacks.
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval None
+  */
+ __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_IRDA_ErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Group3 Peripheral State and Errors functions 
+  *  @brief   IRDA State and Errors functions 
+  *
+@verbatim   
+  ==============================================================================
+                  ##### Peripheral State and Errors functions #####
+  ==============================================================================  
+  [..]
+    This subsection provides a set of functions allowing to return the State of IrDA 
+    communication process and also return Peripheral Errors occurred during communication process
+     (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IrDA peripheral.
+     (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during communication. 
+     
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the IRDA state.
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval HAL state
+  */
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
+{
+  return hirda->State;
+}
+
+/**
+  * @brief  Return the IARDA error code
+  * @param  hirda : pointer to a IRDA_HandleTypeDef structure that contains
+  *              the configuration information for the specified IRDA.
+  * @retval IRDA Error Code
+  */
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
+{
+  return hirda->ErrorCode;
+}
+
+/**
+  * @}
+  */
+  
+/**
+  * @brief  DMA IRDA transmit process complete callback. 
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  hirda->TxXferCount = 0;
+
+  /* Disable the DMA transfer for transmit request by setting the DMAT bit
+     in the IRDA CR3 register */
+  hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT);
+
+  /* Wait for IRDA TC Flag */
+  if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, IRDA_TIMEOUT_VALUE) != HAL_OK)
+  {
+    /* Timeout occurred */ 
+    hirda->State = HAL_IRDA_STATE_TIMEOUT;
+    HAL_IRDA_ErrorCallback(hirda);
+  }
+  else
+  {
+    /* No Timeout */
+    /* Check if a receive process is ongoing or not */
+    if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+    {
+      hirda->State = HAL_IRDA_STATE_BUSY_RX;
+    }
+    else
+    {
+      hirda->State = HAL_IRDA_STATE_READY;
+    }
+    HAL_IRDA_TxCpltCallback(hirda);
+  }
+}
+
+/**
+  * @brief  DMA IRDA receive process complete callback. 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)   
+{
+  IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  hirda->RxXferCount = 0;
+
+  /* Disable the DMA transfer for the receiver request by setting the DMAR bit 
+     in the IRDA CR3 register */
+  hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR);
+
+  if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) 
+  {
+    hirda->State = HAL_IRDA_STATE_BUSY_TX;
+  }
+  else
+  {
+    hirda->State = HAL_IRDA_STATE_READY;
+  }
+  
+  HAL_IRDA_RxCpltCallback(hirda);
+}
+
+/**
+  * @brief  DMA IRDA communication error callback. 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma)   
+{
+  IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  hirda->RxXferCount = 0;
+  hirda->TxXferCount = 0;
+  hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; 
+  hirda->State= HAL_IRDA_STATE_READY;
+  
+  HAL_IRDA_ErrorCallback(hirda);
+}
+
+/**
+  * @brief  This function handles IRDA Communication Timeout.
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @param  Flag: specifies the IRDA flag to check.
+  * @param  Status: The new Flag status (SET or RESET).
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)  
+{
+  uint32_t timeout = 0;
+  
+  timeout = HAL_GetTick() + Timeout;
+  
+  /* Wait until flag is set */
+  if(Status == RESET)
+  {    
+    while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
+          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
+          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
+          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+        
+          hirda->State= HAL_IRDA_STATE_READY;
+        
+          /* Process Unlocked */
+          __HAL_UNLOCK(hirda);
+        
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  else
+  {
+    while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
+          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
+          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
+          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+
+          hirda->State= HAL_IRDA_STATE_READY;
+        
+          /* Process Unlocked */
+          __HAL_UNLOCK(hirda);
+        
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  return HAL_OK;      
+}
+
+ /**
+  * @brief  Send an amount of data in non blocking mode. 
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
+{
+  uint16_t* tmp;
+  uint32_t tmp1 = 0;
+  
+  tmp1 = hirda->State;
+  if((tmp1 == HAL_IRDA_STATE_BUSY_TX) || (tmp1 == HAL_IRDA_STATE_BUSY_TX_RX))
+  {
+    if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+    {
+      tmp = (uint16_t*) hirda->pTxBuffPtr;
+      hirda->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
+      if(hirda->Init.Parity == IRDA_PARITY_NONE)
+      {
+        hirda->pTxBuffPtr += 2;
+      }
+      else
+      {
+        hirda->pTxBuffPtr += 1;
+      }
+    } 
+    else
+    {
+      hirda->Instance->DR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FF);
+    }
+    
+    if(--hirda->TxXferCount == 0)
+    {
+      /* Disable the IRDA Transmit Complete Interrupt */
+      __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
+      
+      if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) 
+      {
+        hirda->State = HAL_IRDA_STATE_BUSY_RX;
+      }
+      else
+      {
+        /* Disable the IRDA Parity Error Interrupt */
+        __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
+        
+        /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+        __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+        
+        hirda->State = HAL_IRDA_STATE_READY;
+      }
+
+      HAL_IRDA_TxCpltCallback(hirda);
+      
+      return HAL_OK;      
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;   
+  }
+}
+
+/**
+  * @brief  Receives an amount of data in non blocking mode. 
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
+{
+  uint16_t* tmp;
+  uint32_t tmp1 = 0;
+  
+  tmp1 = hirda->State;  
+  if((tmp1 == HAL_IRDA_STATE_BUSY_RX) || (tmp1 == HAL_IRDA_STATE_BUSY_TX_RX))
+  {
+    if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+    {
+      tmp = (uint16_t*) hirda->pRxBuffPtr;
+      if(hirda->Init.Parity == IRDA_PARITY_NONE)
+      {
+        *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FF);
+        hirda->pRxBuffPtr += 2;
+      }
+      else
+      {
+        *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FF);
+        hirda->pRxBuffPtr += 1;
+      }
+    } 
+    else
+    {
+      if(hirda->Init.Parity == IRDA_PARITY_NONE)
+      {
+        *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FF);
+      }
+      else
+      {
+        *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x007F);
+      }
+    }
+    
+    if(--hirda->RxXferCount == 0)
+    {
+      while(HAL_IS_BIT_SET(hirda->Instance->SR, IRDA_FLAG_RXNE))
+      {
+      }
+      __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
+      
+      if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) 
+      {
+        hirda->State = HAL_IRDA_STATE_BUSY_TX;
+      }
+      else
+      {
+        /* Disable the IRDA Parity Error Interrupt */
+        __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
+        
+        /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+        __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+        
+        hirda->State = HAL_IRDA_STATE_READY;
+      }
+      HAL_IRDA_RxCpltCallback(hirda);
+      
+      return HAL_OK;
+    }
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY; 
+  }
+}
+
+/**
+  * @brief  Configures the IRDA peripheral. 
+  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval None
+  */
+static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
+{
+  uint32_t tmpreg = 0x00;
+  
+  /* Check the parameters */
+  assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+  assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));  
+  assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
+  assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
+  assert_param(IS_IRDA_MODE(hirda->Init.Mode));
+  
+  /*-------------------------- IRDA CR2 Configuration ------------------------*/
+  /* Clear STOP[13:12] bits */
+  hirda->Instance->CR2 &= (uint32_t)~((uint32_t)USART_CR2_STOP);
+  
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  tmpreg = hirda->Instance->CR1;
+  
+  /* Clear M, PCE, PS, TE and RE bits */
+  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
+    USART_CR1_RE));
+  
+  /* Configure the USART Word Length, Parity and mode: 
+     Set the M bits according to hirda->Init.WordLength value 
+     Set PCE and PS bits according to hirda->Init.Parity value
+     Set TE and RE bits according to hirda->Init.Mode value */
+  tmpreg |= (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode;
+  
+  /* Write to USART CR1 */
+  hirda->Instance->CR1 = (uint32_t)tmpreg;
+  
+  /*-------------------------- USART CR3 Configuration -----------------------*/  
+  /* Clear CTSE and RTSE bits */
+  hirda->Instance->CR3 &= (uint32_t)~((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
+  
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  if((hirda->Instance == USART1) || (hirda->Instance == USART6))
+  {
+    hirda->Instance->BRR = __IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate);
+  }
+  else
+  {
+    hirda->Instance->BRR = __IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate);
+  }
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_irda.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,396 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_irda.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of IRDA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_IRDA_H
+#define __STM32F4xx_HAL_IRDA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup IRDA
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** 
+  * @brief IRDA Init Structure definition  
+  */ 
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                           - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
+                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref IRDA_Word_Length */
+
+
+  uint32_t Parity;                   /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref IRDA_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+ 
+  uint32_t Mode;                      /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref IRDA_Mode */
+                                            
+  uint8_t  Prescaler;                 /*!< Specifies the Prescaler */
+  
+  uint32_t IrDAMode;                  /*!< Specifies the IrDA mode
+                                           This parameter can be a value of @ref IrDA_Low_Power */
+}IRDA_InitTypeDef;
+
+/** 
+  * @brief HAL State structures definition  
+  */ 
+typedef enum
+{
+  HAL_IRDA_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized */
+  HAL_IRDA_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
+  HAL_IRDA_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing */
+  HAL_IRDA_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing */
+  HAL_IRDA_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing */
+  HAL_IRDA_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
+  HAL_IRDA_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
+  HAL_IRDA_STATE_ERROR             = 0x04     /*!< Error */
+}HAL_IRDA_StateTypeDef;
+
+/** 
+  * @brief  HAL IRDA Error Code structure definition  
+  */ 
+typedef enum
+{
+  HAL_IRDA_ERROR_NONE      = 0x00,    /*!< No error            */
+  HAL_IRDA_ERROR_PE        = 0x01,    /*!< Parity error        */
+  HAL_IRDA_ERROR_NE        = 0x02,    /*!< Noise error         */
+  HAL_IRDA_ERROR_FE        = 0x04,    /*!< frame error         */
+  HAL_IRDA_ERROR_ORE       = 0x08,    /*!< Overrun error       */
+  HAL_IRDA_ERROR_DMA       = 0x10     /*!< DMA transfer error  */
+}HAL_IRDA_ErrorTypeDef;
+
+/** 
+  * @brief  IRDA handle Structure definition  
+  */  
+typedef struct
+{
+  USART_TypeDef               *Instance;        /* USART registers base address       */
+  
+  IRDA_InitTypeDef            Init;             /* IRDA communication parameters      */
+  
+  uint8_t                     *pTxBuffPtr;      /* Pointer to IRDA Tx transfer Buffer */
+  
+  uint16_t                    TxXferSize;       /* IRDA Tx Transfer size              */
+  
+  uint16_t                    TxXferCount;      /* IRDA Tx Transfer Counter           */
+  
+  uint8_t                     *pRxBuffPtr;      /* Pointer to IRDA Rx transfer Buffer */
+  
+  uint16_t                    RxXferSize;       /* IRDA Rx Transfer size              */
+  
+  uint16_t                    RxXferCount;      /* IRDA Rx Transfer Counter           */  
+  
+  DMA_HandleTypeDef           *hdmatx;          /* IRDA Tx DMA Handle parameters      */
+    
+  DMA_HandleTypeDef           *hdmarx;          /* IRDA Rx DMA Handle parameters      */
+  
+  HAL_LockTypeDef             Lock;            /* Locking object                     */
+  
+  __IO HAL_IRDA_StateTypeDef  State;           /* IRDA communication state            */
+  
+  __IO HAL_IRDA_ErrorTypeDef  ErrorCode;        /* IRDA Error code                    */
+  
+}IRDA_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Constants
+  * @{
+  */
+
+/** @defgroup IRDA_Word_Length 
+  * @{
+  */
+#define IRDA_WORDLENGTH_8B                  ((uint32_t)0x00000000)
+#define IRDA_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
+#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
+                                     ((LENGTH) == IRDA_WORDLENGTH_9B))
+/**
+  * @}
+  */
+
+
+/** @defgroup IRDA_Parity 
+  * @{
+  */ 
+#define IRDA_PARITY_NONE                    ((uint32_t)0x00000000)
+#define IRDA_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
+#define IRDA_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
+#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
+                                ((PARITY) == IRDA_PARITY_EVEN) || \
+                                ((PARITY) == IRDA_PARITY_ODD))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup IRDA_Mode 
+  * @{
+  */ 
+#define IRDA_MODE_RX                        ((uint32_t)USART_CR1_RE)
+#define IRDA_MODE_TX                        ((uint32_t)USART_CR1_TE)
+#define IRDA_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define IS_IRDA_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
+/**
+  * @}
+  */
+
+/** @defgroup IrDA_Low_Power 
+  * @{
+  */
+#define IRDA_POWERMODE_LOWPOWER                  ((uint32_t)USART_CR3_IRLP)
+#define IRDA_POWERMODE_NORMAL                    ((uint32_t)0x00000000)
+#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
+                                 ((MODE) == IRDA_POWERMODE_NORMAL))
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Flags 
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the SR register
+  * @{
+  */
+#define IRDA_FLAG_TXE                       ((uint32_t)0x00000080)
+#define IRDA_FLAG_TC                        ((uint32_t)0x00000040)
+#define IRDA_FLAG_RXNE                      ((uint32_t)0x00000020)
+#define IRDA_FLAG_IDLE                      ((uint32_t)0x00000010)
+#define IRDA_FLAG_ORE                       ((uint32_t)0x00000008)
+#define IRDA_FLAG_NE                        ((uint32_t)0x00000004)
+#define IRDA_FLAG_FE                        ((uint32_t)0x00000002)
+#define IRDA_FLAG_PE                        ((uint32_t)0x00000001)
+/**
+  * @}
+  */
+  
+/** @defgroup IRDA_Interrupt_definition 
+  *        Elements values convention: 0xY000XXXX
+  *           - XXXX  : Interrupt mask in the XX register
+  *           - Y  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *
+  * @{
+  */
+  
+#define IRDA_IT_PE                          ((uint32_t)0x10000100)
+#define IRDA_IT_TXE                         ((uint32_t)0x10000080)
+#define IRDA_IT_TC                          ((uint32_t)0x10000040)
+#define IRDA_IT_RXNE                        ((uint32_t)0x10000020)
+#define IRDA_IT_IDLE                        ((uint32_t)0x10000010)
+
+#define IRDA_IT_LBD                         ((uint32_t)0x20000040)
+
+#define IRDA_IT_CTS                         ((uint32_t)0x30000400)
+#define IRDA_IT_ERR                         ((uint32_t)0x30000001)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset IRDA handle state
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
+
+/** @brief  Flushs the IRDA DR register 
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  */
+#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
+
+/** @brief  Checks whether the specified IRDA flag is set or not.
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg IRDA_FLAG_TXE:  Transmit data register empty flag
+  *            @arg IRDA_FLAG_TC:   Transmission Complete flag
+  *            @arg IRDA_FLAG_RXNE: Receive data register not empty flag
+  *            @arg IRDA_FLAG_IDLE: Idle Line detection flag
+  *            @arg IRDA_FLAG_ORE:  OverRun Error flag
+  *            @arg IRDA_FLAG_NE:   Noise Error flag
+  *            @arg IRDA_FLAG_FE:   Framing Error flag
+  *            @arg IRDA_FLAG_PE:   Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clears the specified IRDA pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
+  * @param  __FLAG__: specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg IRDA_FLAG_TC:   Transmission Complete flag.
+  *            @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
+  *   
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
+  *          error) and IDLE (Idle line detected) flags are cleared by software 
+  *          sequence: a read operation to USART_SR register followed by a read
+  *          operation to USART_DR register.
+  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
+  * @note   TC flag can be also cleared by software sequence: a read operation to 
+  *          USART_SR register followed by a write operation to USART_DR register.
+  * @note   TXE flag is cleared only by a write to the USART_DR register.
+  *   
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+
+
+/** @brief  Enables or disables the specified IRDA interrupt.
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
+  * @param  __INTERRUPT__: specifies the IRDA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt
+  *            @arg IRDA_IT_TC:   Transmission complete interrupt
+  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg IRDA_IT_IDLE: Idle line detection interrupt
+  *            @arg IRDA_IT_PE:   Parity Error interrupt
+  *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  * @param  NewState: new state of the specified IRDA interrupt.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+#define IRDA_IT_MASK  ((uint32_t)0x0000FFFF)
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
+                                                        (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & IRDA_IT_MASK)): \
+                                                        ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+                                                        (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+                                                        ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
+    
+/** @brief  Checks whether the specified IRDA interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
+  * @param  __IT__: specifies the IRDA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+  *            @arg IRDA_IT_TC:  Transmission complete interrupt
+  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg IRDA_IT_IDLE: Idle line detection interrupt
+  *            @arg USART_IT_ERR: Error interrupt
+  *            @arg IRDA_IT_PE: Parity Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
+                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
+
+
+
+#define __IRDA_ENABLE(__HANDLE__)                   ( (__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+#define __IRDA_DISABLE(__HANDLE__)                  ( (__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+    
+#define __DIV(_PCLK_, _BAUD_)                       (((_PCLK_)*25)/(4*(_BAUD_)))
+#define __DIVMANT(_PCLK_, _BAUD_)                   (__DIV((_PCLK_), (_BAUD_))/100)
+#define __DIVFRAQ(_PCLK_, _BAUD_)                   (((__DIV((_PCLK_), (_BAUD_)) - (__DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define __IRDA_BRR(_PCLK_, _BAUD_)                  ((__DIVMANT((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201)
+                                
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+
+/* Peripheral State functions  **************************************************/
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
+uint32_t              HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_IRDA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,348 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_iwdg.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   IWDG HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Independent Watchdog (IWDG) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State functions
+  *         
+  @verbatim 
+  ==============================================================================
+                    ##### IWDG Generic features #####
+  ==============================================================================
+    [..] 
+    (+) The IWDG can be started by either software or hardware (configurable
+         through option byte).
+    
+    (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and
+         thus stays active even if the main clock fails.
+         Once the IWDG is started, the LSI is forced ON and cannot be disabled
+         (LSI cannot be disabled too), and the counter starts counting down from 
+         the reset value of 0xFFF. When it reaches the end of count value (0x000)
+         a system reset is generated.
+
+    (+) The IWDG counter should be refreshed at regular intervals, otherwise the
+         watchdog generates an MCU reset when the counter reaches 0.          
+ 
+    (+) The IWDG is implemented in the VDD voltage domain that is still functional
+         in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+         IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
+         reset occurs.
+
+    (+) Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
+         The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
+         devices provide the capability to measure the LSI frequency (LSI clock
+         connected internally to TIM5 CH4 input capture). The measured value
+         can be used to have an IWDG timeout with an acceptable accuracy.
+
+
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (+) Use IWDG using HAL_IWDG_Start() function to:
+          (++) Enable write access to IWDG_PR and IWDG_RLR registers.   
+          (++) Configure the IWDG prescaler and counter reload values.
+          (++) Reload IWDG counter with value defined in the IWDG_RLR register.
+          (++) Start the IWDG, when the IWDG is used in software mode (no need 
+               to enable the LSI, it will be enabled by hardware).
+      (+) Then the application program must refresh the IWDG counter at regular
+          intervals during normal operation to prevent an MCU reset, using
+          HAL_IWDG_Refresh() function.  
+     
+     *** IWDG HAL driver macros list ***
+     ====================================
+     [..]
+       Below the list of most used macros in IWDG HAL driver.
+       
+      (+) __HAL_IWDG_START: Enable the IWDG peripheral
+      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register    
+      (+) __HAL_IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers
+      (+) __HAL_IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers
+      (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
+      (+) __HAL_IWDG_CLEAR_FLAG: Clear the IWDG's pending flags      
+            
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup IWDG 
+  * @brief IWDG HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup IWDG_Private_Functions
+  * @{
+  */
+
+/** @defgroup IWDG_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions. 
+ *
+@verbatim    
+ ===============================================================================
+          ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the IWDG according to the specified parameters 
+          in the IWDG_InitTypeDef and create the associated handle
+      (+) Initialize the IWDG MSP
+      (+) DeInitialize IWDG MSP 
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the IWDG according to the specified
+  *         parameters in the IWDG_InitTypeDef and creates the associated handle.
+  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
+{
+  uint32_t tmp;
+  
+  /* Check the IWDG handle allocation */
+  if(hiwdg == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
+  assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); 
+  
+  if(hiwdg->State == HAL_IWDG_STATE_RESET)
+  {  
+    /* Init the low level hardware */
+    HAL_IWDG_MspInit(hiwdg);
+  }
+  
+  /* Change IWDG peripheral state */
+  hiwdg->State = HAL_IWDG_STATE_BUSY;  
+  
+  /* Set IWDG counter clock prescaler */  
+  /* Get the PR register value */
+  tmp = hiwdg->Instance->PR;
+  
+  /* Clear PR[2:0] bits */
+  tmp &= ((uint32_t)~(IWDG_PR_PR));
+  
+  /* Prepare the IWDG Prescaler parameter */
+  tmp |= hiwdg->Init.Prescaler;
+  
+  /* Enable write access to IWDG_PR and IWDG_RLR registers */  
+  __HAL_IWDG_ENABLE_WRITE_ACCESS(hiwdg);
+  
+  /* Write to IWDG PR */
+  hiwdg->Instance->PR = tmp;
+  
+  /* Set IWDG counter reload value */  
+  /* Get the RLR register value */
+  tmp = hiwdg->Instance->RLR;
+  
+  /* Clear RL[11:0] bits */
+  tmp &= ((uint32_t)~(IWDG_RLR_RL));
+  
+  /* Prepare the IWDG Prescaler parameter */
+  tmp |= hiwdg->Init.Reload;
+  
+  /* Write to IWDG RLR */
+  hiwdg->Instance->RLR = tmp;
+ 
+  /* Change IWDG peripheral state */
+  hiwdg->State = HAL_IWDG_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the IWDG MSP.
+  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @retval None
+  */
+__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_IWDG_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Group2 IO operation functions  
+ *  @brief   IO operation functions  
+ *
+@verbatim   
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Start the IWDG.
+      (+) Refresh the IWDG.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the IWDG.
+  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
+{
+  /* Process Locked */
+  __HAL_LOCK(hiwdg); 
+  
+    /* Change IWDG peripheral state */  
+  hiwdg->State = HAL_IWDG_STATE_BUSY;
+
+  /* Start the IWDG peripheral */
+  __HAL_IWDG_START(hiwdg);
+  
+    /* Reload IWDG counter with value defined in the RLR register */
+  __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+  
+  /* Change IWDG peripheral state */    
+  hiwdg->State = HAL_IWDG_STATE_READY; 
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hiwdg);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Refreshes the IWDG.
+  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
+{
+  /* Process Locked */
+  __HAL_LOCK(hiwdg); 
+  
+    /* Change IWDG peripheral state */
+  hiwdg->State = HAL_IWDG_STATE_BUSY;
+  
+  /* Clear the RVU flag */  
+  __HAL_IWDG_CLEAR_FLAG(hiwdg, IWDG_FLAG_RVU);
+  
+  /* Reload IWDG counter with value defined in the reload register */
+  __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+    
+  /* Change IWDG peripheral state */    
+  hiwdg->State = HAL_IWDG_STATE_READY; 
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hiwdg);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Group3 Peripheral State functions 
+ *  @brief    Peripheral State functions. 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the IWDG state.
+  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @retval HAL state
+  */
+HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
+{
+  return hiwdg->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_IWDG_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_iwdg.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,256 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_iwdg.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of IWDG HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_IWDG_H
+#define __STM32F4xx_HAL_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup IWDG
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  IWDG HAL State Structure definition  
+  */ 
+typedef enum
+{
+  HAL_IWDG_STATE_RESET     = 0x00,  /*!< IWDG not yet initialized or disabled */
+  HAL_IWDG_STATE_READY     = 0x01,  /*!< IWDG initialized and ready for use   */
+  HAL_IWDG_STATE_BUSY      = 0x02,  /*!< IWDG internal process is ongoing     */
+  HAL_IWDG_STATE_TIMEOUT   = 0x03,  /*!< IWDG timeout state                   */
+  HAL_IWDG_STATE_ERROR     = 0x04   /*!< IWDG error state                     */
+    
+}HAL_IWDG_StateTypeDef;
+
+/** 
+  * @brief  IWDG Init structure definition  
+  */ 
+typedef struct
+{
+  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.  
+                            This parameter can be a value of @ref IWDG_Prescaler */
+  
+  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value. 
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+}IWDG_InitTypeDef;
+
+/** 
+  * @brief  IWDG handle Structure definition  
+  */ 
+typedef struct
+{
+  IWDG_TypeDef                 *Instance;  /*!< Register base address    */ 
+  
+  IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
+  
+  HAL_LockTypeDef              Lock;       /*!< IWDG locking object      */
+  
+  __IO HAL_IWDG_StateTypeDef   State;      /*!< IWDG communication state */
+  
+}IWDG_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Constants
+  * @{
+  */
+
+/** @defgroup IWDG_Registers_BitMask
+  * @{
+  */
+/* --- KR Register ---*/
+/* KR register bit mask */
+#define KR_KEY_RELOAD   ((uint32_t)0xAAAA)  /*!< IWDG reload counter enable   */
+#define KR_KEY_ENABLE   ((uint32_t)0xCCCC)  /*!< IWDG peripheral enable       */
+#define KR_KEY_EWA      ((uint32_t)0x5555)  /*!< IWDG KR write Access enable  */
+#define KR_KEY_DWA      ((uint32_t)0x0000)  /*!< IWDG KR write Access disable */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Flag_definition 
+  * @{
+  */ 
+#define IWDG_FLAG_PVU   ((uint32_t)0x0001)  /*!< Watchdog counter prescaler value update flag */
+#define IWDG_FLAG_RVU   ((uint32_t)0x0002)  /*!< Watchdog counter reload value update flag    */
+  
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || \
+                            ((FLAG) == IWDG_FLAG_RVU))
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Prescaler 
+  * @{
+  */ 
+#define IWDG_PRESCALER_4     ((uint8_t)0x00)  /*!< IWDG prescaler set to 4   */
+#define IWDG_PRESCALER_8     ((uint8_t)0x01)  /*!< IWDG prescaler set to 8   */
+#define IWDG_PRESCALER_16    ((uint8_t)0x02)  /*!< IWDG prescaler set to 16  */
+#define IWDG_PRESCALER_32    ((uint8_t)0x03)  /*!< IWDG prescaler set to 32  */
+#define IWDG_PRESCALER_64    ((uint8_t)0x04)  /*!< IWDG prescaler set to 64  */
+#define IWDG_PRESCALER_128   ((uint8_t)0x05)  /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256   ((uint8_t)0x06)  /*!< IWDG prescaler set to 256 */
+
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_PRESCALER_4)  || \
+                                      ((PRESCALER) == IWDG_PRESCALER_8)  || \
+                                      ((PRESCALER) == IWDG_PRESCALER_16) || \
+                                      ((PRESCALER) == IWDG_PRESCALER_32) || \
+                                      ((PRESCALER) == IWDG_PRESCALER_64) || \
+                                      ((PRESCALER) == IWDG_PRESCALER_128)|| \
+                                      ((PRESCALER) == IWDG_PRESCALER_256))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup IWDG_Reload_Value 
+  * @{
+  */ 
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset IWDG handle state
+  * @param  __HANDLE__: IWDG handle
+  * @retval None
+  */
+#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
+
+/**
+  * @brief  Enables the IWDG peripheral.
+  * @param  __HANDLE__: IWDG handle
+  * @retval None
+  */
+#define __HAL_IWDG_START(__HANDLE__) ((__HANDLE__)->Instance->KR |=  KR_KEY_ENABLE)
+
+/**
+  * @brief  Reloads IWDG counter with value defined in the reload register
+  *         (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  __HANDLE__: IWDG handle
+  * @retval None
+  */
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) (((__HANDLE__)->Instance->KR) |= KR_KEY_RELOAD)
+
+/**
+  * @brief  Enables write access to IWDG_PR and IWDG_RLR registers.
+  * @param  __HANDLE__: IWDG handle
+  * @retval None
+  */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) (((__HANDLE__)->Instance->KR) |= KR_KEY_EWA)
+
+/**
+  * @brief  Disables write access to IWDG_PR and IWDG_RLR registers.
+  * @param  __HANDLE__: IWDG handle
+  * @retval None
+  */
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) (((__HANDLE__)->Instance->KR) |= KR_KEY_DWA)
+
+/**
+  * @brief  Gets the selected IWDG's flag status.
+  * @param  __HANDLE__: IWDG handle
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
+  *            @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clears the IWDG's pending flags.
+  * @param  __HANDLE__: IWDG handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *         This parameter can be one of the following values:
+  *            @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
+  *            @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
+  * @retval None
+  */
+#define __HAL_IWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
+
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+
+/* Peripheral State functions  ************************************************/
+HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1183 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_ltdc.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   LTDC HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the LTDC peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions  
+  *           + Peripheral State and Errors functions
+  *           
+  @verbatim      
+  ==============================================================================      
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Program the required configuration through the following parameters:   
+         the LTDC timing, the horizontal and vertical polarity, 
+         the pixel clock polarity, Data Enable polarity and the LTDC background color value 
+         using HAL_LTDC_Init() function
+
+     (#) Program the required configuration through the following parameters:   
+         the pixel format, the blending factors, input alpha value, the window size 
+         and the image size using HAL_LTDC_ConfigLayer() function for foreground
+         or/and background layer.     
+  
+     (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and 
+         HAL_LTDC_EnableCLUT functions.
+       
+     (#) Optionally, enable the Dither using HAL_LTDC_EnableDither().       
+
+     (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()
+         and HAL_LTDC_EnableColorKeying functions.
+
+     (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineInterrupt()
+         function
+
+     (#) If needed, reconfigure and change the pixel format value, the alpha value
+         value, the window size, the window position and the layer start address 
+         for foreground or/and background layer using respectively the following 
+         functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
+         HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.
+                     
+     (#) To control LTDC state you can use the following function: HAL_LTDC_GetState()               
+
+     *** LTDC HAL driver macros list ***
+     ============================================= 
+     [..]
+       Below the list of most used macros in LTDC HAL driver.
+       
+      (+) __HAL_LTDC_ENABLE: Enable the LTDC.
+      (+) __HAL_LTDC_DISABLE: Disable the LTDC.
+      (+) __HAL_LTDC_LAYER_ENABLE: Enable the LTDC Layer.
+      (+) __HAL_LTDC_LAYER_DISABLE: Disable the LTDC Layer.
+      (+) __HAL_LTDC_RELOAD_CONFIG: Reload  Layer Configuration.
+      (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.
+      (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.
+      (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts. 
+      (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
+      (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.
+      
+     [..] 
+       (@) You can refer to the LTDC HAL driver header file for more useful macros
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+/** @defgroup LTDC 
+  * @brief LTDC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+
+#if defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/    
+/* Private function prototypes -----------------------------------------------*/
+static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup LTDC_Private_Functions
+  * @{
+  */
+
+/** @defgroup LTDC_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions
+ *
+@verbatim   
+ ===============================================================================
+                ##### Initialization and Configuration functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the LTDC
+      (+) De-initialize the LTDC 
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initializes the LTDC according to the specified
+  *         parameters in the LTDC_InitTypeDef and create the associated handle.
+  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
+{
+  uint32_t tmp = 0, tmp1 = 0;
+
+  /* Check the LTDC peripheral state */
+  if(hltdc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check function parameters */
+  assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));
+  assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync));
+  assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync));
+  assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP));
+  assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP));
+  assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH));
+  assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW));
+  assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh));
+  assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth));
+  assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity));
+  assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity));
+  assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity));
+  assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity));
+
+  if(hltdc->State == HAL_LTDC_STATE_RESET)
+  {
+    /* Init the low level hardware */
+    HAL_LTDC_MspInit(hltdc);
+  }
+  
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Configures the HS, VS, DE and PC polarity */
+  hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
+  hltdc->Instance->GCR |=  (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
+  hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
+
+  /* Sets Synchronization size */
+  hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
+  tmp = (hltdc->Init.HorizontalSync << 16);
+  hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
+
+  /* Sets Accumulated Back porch */
+  hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
+  tmp = (hltdc->Init.AccumulatedHBP << 16);
+  hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
+
+  /* Sets Accumulated Active Width */
+  hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
+  tmp = (hltdc->Init.AccumulatedActiveW << 16);
+  hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
+
+  /* Sets Total Width */
+  hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
+  tmp = (hltdc->Init.TotalWidth << 16);
+  hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
+
+  /* Sets the background color value */
+  tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8);
+  tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16);
+  hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
+  hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
+
+  /* Enable the transfer Error interrupt */
+  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE);
+
+  /* Enable the FIFO underrun interrupt */
+  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_FU);
+
+  /* Enable LTDC by setting LTDCEN bit */
+  __HAL_LTDC_ENABLE(hltdc);
+
+  /* Initialise the error code */
+  hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;  
+
+  /* Initialize the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deinitializes the LTDC peripheral registers to their default reset
+  *         values.
+  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+
+HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)
+{
+  /* DeInit the low level hardware */
+  HAL_LTDC_MspDeInit(hltdc); 
+
+  /* Initialise the error code */
+  hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
+
+  /* Initialize the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the LTDC MSP.
+  * @param  hltdc : pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_LTDC_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  DeInitializes the LTDC MSP.
+  * @param  hltdc : pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_LTDC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup LTDC_Group2 IO operation functions 
+ *  @brief   IO operation functions  
+ *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================  
+    [..]  This section provides function allowing to:
+      (+) Handle LTDC interrupt request
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Handles LTDC interrupt request.
+  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.  
+  * @retval HAL status
+  */
+void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
+{
+  /* Transfer Error Interrupt management ***************************************/
+  if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_TE) != RESET)
+  {
+    if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_TE) != RESET)
+    {
+      /* Disable the transfer Error interrupt */
+      __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
+
+      /* Clear the transfer error flag */
+      __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
+
+      /* Update error code */
+      hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
+
+      /* Change LTDC state */
+      hltdc->State = HAL_LTDC_STATE_ERROR;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hltdc);
+
+      /* Transfer error Callback */
+      HAL_LTDC_ErrorCallback(hltdc);
+    }
+  }
+  /* FIFO underrun Interrupt management ***************************************/
+  if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_FU) != RESET)
+  {
+    if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_FU) != RESET)
+    {
+      /* Disable the FIFO underrun interrupt */
+      __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
+
+      /* Clear the FIFO underrun flag */
+      __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
+
+      /* Update error code */
+      hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
+
+      /* Change LTDC state */
+      hltdc->State = HAL_LTDC_STATE_ERROR;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hltdc);
+      
+      /* Transfer error Callback */
+      HAL_LTDC_ErrorCallback(hltdc);
+    }
+  }
+  /* Line Interrupt management ************************************************/
+  if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_LI) != RESET)
+  {
+    if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_LI) != RESET)
+    {
+      /* Disable the Line interrupt */
+      __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
+
+      /* Clear the Line interrupt flag */  
+      __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
+
+      /* Change LTDC state */
+      hltdc->State = HAL_LTDC_STATE_READY;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hltdc);
+
+      /* Line interrupt Callback */
+      HAL_LTDC_LineEvenCallback(hltdc);
+    }
+  }
+}
+
+/**
+  * @brief  Error LTDC callback.
+  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_LTDC_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Line Event callback.
+  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+__weak void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_LTDC_LineEvenCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Group3 Peripheral Control functions
+ *  @brief    Peripheral Control functions 
+ *
+@verbatim   
+ ===============================================================================
+                    ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure the LTDC foreground or/and background parameters.
+      (+) Set the active layer.
+      (+) Configure the color keying.
+      (+) Configure the C-LUT.
+      (+) Enable / Disable the color keying.
+      (+) Enable / Disable the C-LUT.
+      (+) Update the layer position.
+      (+) Update the layer size.
+      (+) Update pixel format on the fly. 
+      (+) Update transparency on the fly.
+      (+) Update address on the fly.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the LTDC Layer according to the specified
+  *         parameters in the LTDC_InitTypeDef and create the associated handle.
+  * @param  hltdc:     pointer to a LTDC_HandleTypeDef structure that contains
+  *                    the configuration information for the LTDC.
+  * @param  pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains
+  *                    the configuration information for the Layer.
+  * @param  LayerIdx:  LTDC Layer index.
+  *                    This parameter can be one of the following values:
+  *                    0 or 1
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
+{   
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+  
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
+  assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
+  assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
+  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
+  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
+  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
+  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
+  assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
+  assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
+  assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
+
+  /* Copy new layer configuration into handle structure */
+  hltdc->LayerCfg[LayerIdx] = *pLayerCfg;  
+
+  /* Configure the LTDC Layer */  
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Sets the Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Initialize the LTDC state*/
+  hltdc->State  = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the color keying.
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  RGBValue: the color key value
+  * @param  LayerIdx:  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0 or 1
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
+{
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Configures the default color values */
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->CKCR &=  ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->CKCR  = RGBValue;
+
+  /* Sets the Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Load the color lookup table.
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  pCLUT:    pointer to the color lookup table address.
+  * @param  CLUTSize: the color lookup table size.  
+  * @param  LayerIdx:  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0 or 1
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
+{
+  uint32_t tmp = 0;
+  uint32_t counter = 0;
+  uint32_t pcounter = 0;
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;  
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx)); 
+
+  for(counter = 0; (counter < CLUTSize); counter++)
+  {
+    tmp  = ((counter << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));
+    pcounter = (uint32_t)pCLUT + sizeof(*pCLUT);
+    pCLUT = (uint32_t *)pcounter;
+
+    /* Specifies the C-LUT address and RGB value */
+    __HAL_LTDC_LAYER(hltdc, LayerIdx)->CLUTWR  = tmp;
+  }
+  
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY; 
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);  
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the color keying.
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx:  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0 or 1
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{  
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Enable LTDC color keying by setting COLKEN bit */
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
+
+  /* Sets the Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY; 
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;  
+}
+  
+/**
+  * @brief  Disable the color keying.
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx:  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0 or 1
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Disable LTDC color keying by setting COLKEN bit */
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
+
+  /* Sets the Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY; 
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the color lookup table.
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx:  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0 or 1
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Disable LTDC color lookup table by setting CLUTEN bit */
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
+
+  /* Sets the Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY; 
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the color lookup table.
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx:  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0 or 1   
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+ 
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Disable LTDC color lookup table by setting CLUTEN bit */
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
+
+  /* Sets the Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY; 
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables Dither.
+  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval  HAL status
+  */
+
+HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc)
+{
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Enable Dither by setting DTEN bit */
+  LTDC->GCR |= (uint32_t)LTDC_GCR_DTEN;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY; 
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables Dither.
+  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval  HAL status
+  */
+
+HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc)
+{
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Disable Dither by setting DTEN bit */
+  LTDC->GCR &= ~(uint32_t)LTDC_GCR_DTEN;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the LTDC window size.
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  XSize:    LTDC Pixel per line
+  * @param  YSize:    LTDC Line number
+  * @param  LayerIdx:  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0 or 1
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) 
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY; 
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+  /* Check the parameters (Layers parameters)*/
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
+  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
+  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
+  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
+  assert_param(IS_LTDC_CFBLL(XSize));
+  assert_param(IS_LTDC_CFBLNBR(YSize));
+
+  /* update horizontal start/stop */
+  pLayerCfg->WindowX0 = 0;
+  pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
+
+  /* update vertical start/stop */  
+  pLayerCfg->WindowY0 = 0;
+  pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
+
+  /* Reconfigures the color frame buffer pitch in byte */
+  pLayerCfg->ImageWidth = XSize;
+
+  /* Reconfigures the frame buffer line number */
+  pLayerCfg->ImageHeight = YSize;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Sets the Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the LTDC window position.
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  X0:       LTDC window X offset
+  * @param  Y0:       LTDC window Y offset
+  * @param  LayerIdx:  LTDC Layer index.
+  *                         This parameter can be one of the following values:
+  *                         0 or 1
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+  
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
+  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
+  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
+  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
+
+  /* update horizontal start/stop */
+  pLayerCfg->WindowX0 = X0;
+  pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
+
+  /* update vertical start/stop */
+  pLayerCfg->WindowY0 = Y0;
+  pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Sets the Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reconfigure the pixel format.
+  * @param  hltdc:       pointer to a LTDC_HandleTypeDef structure that contains
+  *                      the configuration information for the LTDC.
+  * @param  Pixelformat: new pixel format value.
+  * @param  LayerIdx:    LTDC Layer index.
+  *                      This parameter can be one of the following values:
+  *                      0 or 1.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];  
+
+  /* Reconfigure the pixel format */
+  pLayerCfg->PixelFormat = Pixelformat;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);   
+
+  /* Sets the Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reconfigure the layer alpha value.
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  Alpha:    new alpha value.
+  * @param  LayerIdx:  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0 or 1
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_ALPHA(Alpha));
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+  /* Reconfigure the Alpha value */
+  pLayerCfg->Alpha = Alpha;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Sets the Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+/**
+  * @brief  Reconfigure the frame buffer Address.
+  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  Address:  new address value.
+  * @param  LayerIdx: LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0 or 1.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+  /* Reconfigure the Address */
+  pLayerCfg->FBStartAdress = Address;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Sets the Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Define the position of the line interrupt .
+  * @param  hltdc:             pointer to a LTDC_HandleTypeDef structure that contains
+  *                            the configuration information for the LTDC.
+  * @param  Line:   Line Interrupt Position.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line)
+{
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LIPOS(Line));
+
+  /* Enable the Line interrupt */
+  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI);
+
+  /* Sets the Line Interrupt position */
+  LTDC->LIPCR = (uint32_t)Line;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Group4 Peripheral State and Errors functions
+ *  @brief    Peripheral State and Errors functions 
+ *
+@verbatim   
+ ===============================================================================
+                  ##### Peripheral State and Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the LTDC state.
+      (+) Get error code.  
+
+@endverbatim
+  * @{
+  */ 
+
+/**
+  * @brief  Return the LTDC state
+  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval HAL state
+  */
+HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
+{
+  return hltdc->State;
+}
+
+/**
+* @brief  Return the LTDC error code
+* @param  hltdc : pointer to a LTDC_HandleTypeDef structure that contains
+  *               the configuration information for the LTDC.
+* @retval LTDC Error Code
+*/
+uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)
+{
+  return hltdc->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Configures the LTDC peripheral 
+  * @param  hltdc   :  Pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  pLayerCfg: Pointer LTDC Layer Configuration strusture
+  * @param  LayerIdx:  LTDC Layer index.
+  *                    This parameter can be one of the following values: 0 or 1
+  * @retval None
+  */
+static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
+{
+  uint32_t tmp = 0;
+  uint32_t tmp1 = 0;
+  uint32_t tmp2 = 0;
+
+  /* Configures the horizontal start and stop position */
+  tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16)) << 16);
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16) + 1) | tmp);
+
+  /* Configures the vertical start and stop position */
+  tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16);
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->WVPCR  = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1) | tmp);  
+
+  /* Specifies the pixel format */
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
+
+  /* Configures the default color values */
+  tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8);
+  tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16);
+  tmp2 = (pLayerCfg->Alpha0 << 24);  
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); 
+
+  /* Specifies the constant alpha value */
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
+
+  /* Specifies the blending factors */
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
+
+  /* Configures the color frame buffer start address */
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
+
+  if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
+  {
+    tmp = 4;
+  }
+  else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
+  {
+    tmp = 3;
+  }
+  else if((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
+    (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \
+      (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
+        (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
+  {
+    tmp = 2;
+  }
+  else
+  {
+    tmp = 1;
+  }
+
+  /* Configures the color frame buffer pitch in byte */
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->CFBLR  &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->CFBLR  = (((pLayerCfg->ImageWidth * tmp) << 16) | ((pLayerCfg->ImageWidth * tmp)  + 3));
+
+  /* Configures the frame buffer line number */
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  &= ~(LTDC_LxCFBLNR_CFBLNBR);
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  = (pLayerCfg->ImageHeight);
+
+  /* Enable LTDC_Layer by setting LEN bit */  
+  __HAL_LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
+}
+
+/**
+  * @}
+  */
+#endif /* STM32F429xx || STM32F439xx */
+#endif /* HAL_LTDC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_ltdc.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,583 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_ltdc.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of LTDC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_LTDC_H
+#define __STM32F4xx_HAL_LTDC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F429xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup LTDC
+  * @{
+  */
+  
+/* Exported types ------------------------------------------------------------*/
+
+#define MAX_LAYER  2
+
+/** 
+  * @brief  LTDC color structure definition
+  */
+typedef struct
+{
+  uint8_t Blue;                    /*!< Configures the blue value.
+                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint8_t Green;                   /*!< Configures the green value.
+                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint8_t Red;                     /*!< Configures the red value. 
+                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint8_t Reserved;                /*!< Reserved 0xFF */
+} LTDC_ColorTypeDef;
+
+/** 
+  * @brief  LTDC Init structure definition
+  */
+typedef struct
+{
+  uint32_t            HSPolarity;                /*!< configures the horizontal synchronization polarity.
+                                                      This parameter can be one value of @ref LTDC_HS_POLARITY */
+
+  uint32_t            VSPolarity;                /*!< configures the vertical synchronization polarity.
+                                                      This parameter can be one value of @ref LTDC_VS_POLARITY */
+
+  uint32_t            DEPolarity;                /*!< configures the data enable polarity. 
+                                                      This parameter can be one of value of @ref LTDC_DE_POLARITY */
+
+  uint32_t            PCPolarity;                /*!< configures the pixel clock polarity. 
+                                                      This parameter can be one of value of @ref LTDC_PC_POLARITY */
+
+  uint32_t            HorizontalSync;            /*!< configures the number of Horizontal synchronization width.
+                                                      This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+  uint32_t            VerticalSync;              /*!< configures the number of Vertical synchronization heigh. 
+                                                      This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
+
+  uint32_t            AccumulatedHBP;            /*!< configures the accumulated horizontal back porch width.
+                                                      This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
+
+  uint32_t            AccumulatedVBP;            /*!< configures the accumulated vertical back porch heigh.
+                                                      This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
+
+  uint32_t            AccumulatedActiveW;        /*!< configures the accumulated active width. 
+                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
+
+  uint32_t            AccumulatedActiveH;        /*!< configures the accumulated active heigh.
+                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
+
+  uint32_t            TotalWidth;                /*!< configures the total width.
+                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
+
+  uint32_t            TotalHeigh;                /*!< configures the total heigh.
+                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
+
+  LTDC_ColorTypeDef   Backcolor;                 /*!< Configures the background color. */
+} LTDC_InitTypeDef;
+
+
+/** 
+  * @brief  LTDC Layer structure definition
+  */
+typedef struct
+{
+  uint32_t WindowX0;                   /*!< Configures the Window Horizontal Start Position.
+                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+  uint32_t WindowX1;                   /*!< Configures the Window Horizontal Stop Position.
+                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+  uint32_t WindowY0;                   /*!< Configures the Window vertical Start Position.
+                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+  uint32_t WindowY1;                   /*!< Configures the Window vertical Stop Position.
+                                            This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+  uint32_t PixelFormat;                /*!< Specifies the pixel format. 
+                                            This parameter can be one of value of @ref LTDC_Pixelformat */
+
+  uint32_t Alpha;                      /*!< Specifies the constant alpha used for blending.
+                                            This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint32_t Alpha0;                     /*!< Configures the default alpha value.
+                                            This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint32_t BlendingFactor1;            /*!< Select the blending factor 1. 
+                                            This parameter can be one of value of @ref LTDC_BlendingFactor1 */
+
+  uint32_t BlendingFactor2;            /*!< Select the blending factor 2. 
+                                            This parameter can be one of value of @ref LTDC_BlendingFactor2 */
+
+  uint32_t FBStartAdress;              /*!< Configures the color frame buffer address */
+
+  uint32_t ImageWidth;                 /*!< Configures the color frame buffer line length. 
+                                            This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */
+
+  uint32_t ImageHeight;                /*!< Specifies the number of line in frame buffer. 
+                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
+
+  LTDC_ColorTypeDef   Backcolor;       /*!< Configures the layer background color. */
+} LTDC_LayerCfgTypeDef;
+
+/** 
+  * @brief  HAL LTDC State structures definition
+  */
+typedef enum
+{
+  HAL_LTDC_STATE_RESET             = 0x00,    /*!< LTDC not yet initialized or disabled */
+  HAL_LTDC_STATE_READY             = 0x01,    /*!< LTDC initialized and ready for use   */
+  HAL_LTDC_STATE_BUSY              = 0x02,    /*!< LTDC internal process is ongoing     */
+  HAL_LTDC_STATE_TIMEOUT           = 0x03,    /*!< LTDC Timeout state                   */
+  HAL_LTDC_STATE_ERROR             = 0x04     /*!< LTDC state error                     */
+}HAL_LTDC_StateTypeDef;
+
+/** 
+  * @brief  LTDC handle Structure definition
+  */
+typedef struct
+{
+  LTDC_TypeDef                *Instance;                /*!< LTDC Register base address                */
+
+  LTDC_InitTypeDef            Init;                     /*!< LTDC parameters                           */
+
+  LTDC_LayerCfgTypeDef        LayerCfg[MAX_LAYER];      /*!< LTDC Layers parameters                    */
+
+  HAL_LockTypeDef             Lock;                     /*!< LTDC Lock                                 */
+
+  __IO HAL_LTDC_StateTypeDef  State;                    /*!< LTDC state                                */
+
+  __IO uint32_t               ErrorCode;                /*!< LTDC Error code                           */
+
+} LTDC_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LTDC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup LTDC_Layer 
+  * @{
+  */  
+#define IS_LTDC_LAYER(LAYER) ((LAYER) <= MAX_LAYER)
+/**
+  * @}
+  */
+
+/** @defgroup LTDC Error Code 
+  * @{
+  */  
+#define HAL_LTDC_ERROR_NONE      ((uint32_t)0x00000000)    /*!< LTDC No error             */
+#define HAL_LTDC_ERROR_TE        ((uint32_t)0x00000001)    /*!< LTDC Transfer error       */
+#define HAL_LTDC_ERROR_FU        ((uint32_t)0x00000002)    /*!< LTDC FIFO Underrun        */
+#define HAL_LTDC_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< LTDC Timeout error        */
+
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_HS_POLARITY 
+  * @{
+  */
+#define LTDC_HSPOLARITY_AL                ((uint32_t)0x00000000)                /*!< Horizontal Synchronization is active low. */
+#define LTDC_HSPOLARITY_AH                LTDC_GCR_HSPOL                        /*!< Horizontal Synchronization is active high. */
+
+#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPOLARITY_AL) || \
+                              ((HSPOL) == LTDC_HSPOLARITY_AH))  
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_VS_POLARITY 
+  * @{
+  */
+#define LTDC_VSPOLARITY_AL                ((uint32_t)0x00000000)                /*!< Vertical Synchronization is active low. */
+#define LTDC_VSPOLARITY_AH                LTDC_GCR_VSPOL                        /*!< Vertical Synchronization is active high. */
+
+#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPOLARITY_AL) || \
+                              ((VSPOL) == LTDC_VSPOLARITY_AH))
+/**
+  * @}
+  */
+  
+/** @defgroup LTDC_DE_POLARITY 
+  * @{
+  */
+#define LTDC_DEPOLARITY_AL                ((uint32_t)0x00000000)                /*!< Data Enable, is active low. */
+#define LTDC_DEPOLARITY_AH                LTDC_GCR_DEPOL                        /*!< Data Enable, is active high. */
+
+#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) ==  LTDC_DEPOLARITY_AL) || \
+                              ((DEPOL) ==  LTDC_DEPOLARITY_AH))
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_PC_POLARITY 
+  * @{
+  */
+#define LTDC_PCPOLARITY_IPC               ((uint32_t)0x00000000)                /*!< input pixel clock. */
+#define LTDC_PCPOLARITY_IIPC              LTDC_GCR_PCPOL                        /*!< inverted input pixel clock. */
+
+#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) ==  LTDC_PCPOLARITY_IPC) || \
+                              ((PCPOL) ==  LTDC_PCPOLARITY_IIPC))
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_SYNC 
+  * @{
+  */
+#define LTDC_HORIZONTALSYNC               (LTDC_SSCR_HSW >> 16)                 /*!< Horizontal synchronization width. */ 
+#define LTDC_VERTICALSYNC                 LTDC_SSCR_VSH                         /*!< Vertical synchronization heigh. */
+
+#define IS_LTDC_HSYNC(HSYNC)   ((HSYNC)  <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_VSYNC(VSYNC)   ((VSYNC)  <= LTDC_VERTICALSYNC)
+#define IS_LTDC_AHBP(AHBP)     ((AHBP)   <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_AVBP(AVBP)     ((AVBP)   <= LTDC_VERTICALSYNC)
+#define IS_LTDC_AAW(AAW)       ((AAW)    <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_AAH(AAH)       ((AAH)    <= LTDC_VERTICALSYNC)
+#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VERTICALSYNC)
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_BACK_COLOR
+  * @{
+  */ 
+#define LTDC_COLOR                   ((uint32_t)0x000000FF)                     /*!< Color mask */
+
+#define IS_LTDC_BLUEVALUE(BBLUE)    ((BBLUE)  <= LTDC_COLOR)
+#define IS_LTDC_GREENVALUE(BGREEN)  ((BGREEN) <= LTDC_COLOR)
+#define IS_LTDC_REDVALUE(BRED)      ((BRED)   <= LTDC_COLOR) 
+/**
+  * @}
+  */
+      
+/** @defgroup LTDC_BlendingFactor1 
+  * @{
+  */
+#define LTDC_BLENDING_FACTOR1_CA                       ((uint32_t)0x00000400)   /*!< Blending factor : Cte Alpha */
+#define LTDC_BLENDING_FACTOR1_PAxCA                    ((uint32_t)0x00000600)   /*!< Blending factor : Cte Alpha x Pixel Alpha*/
+
+#define IS_LTDC_BLENDING_FACTOR1(BlendingFactor1) (((BlendingFactor1) == LTDC_BLENDING_FACTOR1_CA) || \
+                                                   ((BlendingFactor1) == LTDC_BLENDING_FACTOR1_PAxCA))
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_BlendingFactor2
+  * @{
+  */
+#define LTDC_BLENDING_FACTOR2_CA                       ((uint32_t)0x00000005)   /*!< Blending factor : Cte Alpha */
+#define LTDC_BLENDING_FACTOR2_PAxCA                    ((uint32_t)0x00000007)   /*!< Blending factor : Cte Alpha x Pixel Alpha*/
+
+#define IS_LTDC_BLENDING_FACTOR2(BlendingFactor2) (((BlendingFactor2) == LTDC_BLENDING_FACTOR2_CA) || \
+                                                   ((BlendingFactor2) == LTDC_BLENDING_FACTOR2_PAxCA))
+/**
+  * @}
+  */
+      
+/** @defgroup LTDC_Pixelformat 
+  * @{
+  */
+#define LTDC_PIXEL_FORMAT_ARGB8888                  ((uint32_t)0x00000000)      /*!< ARGB8888 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_RGB888                    ((uint32_t)0x00000001)      /*!< RGB888 LTDC pixel format   */
+#define LTDC_PIXEL_FORMAT_RGB565                    ((uint32_t)0x00000002)      /*!< RGB565 LTDC pixel format   */
+#define LTDC_PIXEL_FORMAT_ARGB1555                  ((uint32_t)0x00000003)      /*!< ARGB1555 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_ARGB4444                  ((uint32_t)0x00000004)      /*!< ARGB4444 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_L8                        ((uint32_t)0x00000005)      /*!< L8 LTDC pixel format       */
+#define LTDC_PIXEL_FORMAT_AL44                      ((uint32_t)0x00000006)      /*!< AL44 LTDC pixel format     */
+#define LTDC_PIXEL_FORMAT_AL88                      ((uint32_t)0x00000007)      /*!< AL88 LTDC pixel format     */
+
+#define IS_LTDC_PIXEL_FORMAT(Pixelformat) (((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB8888) || ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB888)   || \
+                                           ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB565)   || ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB1555) || \
+                                           ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB4444) || ((Pixelformat) == LTDC_PIXEL_FORMAT_L8)       || \
+                                           ((Pixelformat) == LTDC_PIXEL_FORMAT_AL44)     || ((Pixelformat) == LTDC_PIXEL_FORMAT_AL88))
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Alpha
+  * @{
+  */
+#define LTDC_ALPHA               LTDC_LxCACR_CONSTA                             /*!< LTDC Cte Alpha mask */
+
+#define IS_LTDC_ALPHA(ALPHA) ((ALPHA) <= LTDC_ALPHA)
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_LAYER_Config
+  * @{
+  */
+#define LTDC_STOPPOSITION                 (LTDC_LxWHPCR_WHSPPOS >> 16)          /*!< LTDC Layer stop position  */
+#define LTDC_STARTPOSITION                LTDC_LxWHPCR_WHSTPOS                  /*!< LTDC Layer start position */
+
+#define LTDC_COLOR_FRAME_BUFFER           LTDC_LxCFBLR_CFBLL                    /*!< LTDC Layer Line length    */ 
+#define LTDC_LINE_NUMBER                  LTDC_LxCFBLNR_CFBLNBR                 /*!< LTDC Layer Line number    */
+
+#define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPOSITION)
+#define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPOSITION)
+#define IS_LTDC_VCONFIGST(VCONFIGST)  ((VCONFIGST) <= LTDC_STARTPOSITION)
+#define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPOSITION)
+
+#define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_COLOR_FRAME_BUFFER)
+#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_COLOR_FRAME_BUFFER)
+
+#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LINE_NUMBER)
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_LIPosition 
+  * @{
+  */
+#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF)
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Interrupts 
+  * @{
+  */
+#define LTDC_IT_LI                      LTDC_IER_LIE
+#define LTDC_IT_FU                      LTDC_IER_FUIE
+#define LTDC_IT_TE                      LTDC_IER_TERRIE
+#define LTDC_IT_RR                      LTDC_IER_RRIE
+
+#define IS_LTDC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF0) == 0x00) && ((IT) != 0x00))
+/**
+  * @}
+  */
+      
+/** @defgroup LTDC_Flag 
+  * @{
+  */
+#define LTDC_FLAG_LI                     LTDC_ISR_LIF
+#define LTDC_FLAG_FU                     LTDC_ISR_FUIF
+#define LTDC_FLAG_TE                     LTDC_ISR_TERRIF
+#define LTDC_FLAG_RR                     LTDC_ISR_RRIF
+
+#define IS_LTDC_FLAG(FLAG) (((FLAG) == LTDC_FLAG_LI) || ((FLAG) == LTDC_FLAG_FU) || \
+                               ((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset LTDC handle state
+  * @param  __HANDLE__: specifies the LTDC handle.
+  * @retval None
+  */
+#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
+
+/**
+  * @brief  Enable the LTDC.
+  * @param  __HANDLE__: LTDC handle
+  * @retval None.
+  */
+#define __HAL_LTDC_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
+
+/**
+  * @brief  Disable the LTDC.
+  * @param  __HANDLE__: LTDC handle
+  * @retval None.
+  */
+#define __HAL_LTDC_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
+
+/**
+  * @brief  Enable the LTDC Layer.
+  * @param  __HANDLE__: LTDC handle
+  * @param  __LAYER__: Specify the layer to be enabled
+                       This parameter can be 0 or 1
+  * @retval None.
+  */
+#define __HAL_LTDC_LAYER(__HANDLE__, __LAYER__)   ((LTDC_Layer_TypeDef *)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__))))
+
+#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__)  ((__HAL_LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
+
+/**
+  * @brief  Disable the LTDC Layer.
+  * @param  __HANDLE__: LTDC handle
+  * @param  __LAYER__: Specify the layer to be disabled
+                       This parameter can be 0 or 1
+  * @retval None.
+  */
+#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((__HAL_LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
+
+/**
+  * @brief  Reload  Layer Configuration.
+  * @param  __HANDLE__: LTDC handle
+  * @retval None.
+  */
+#define __HAL_LTDC_RELOAD_CONFIG(__HANDLE__)   ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
+
+/* Interrupt & Flag management */
+/**
+  * @brief  Get the LTDC pending flags.
+  * @param  __HANDLE__: LTDC handle
+  * @param  __FLAG__: Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg LTDC_FLAG_LI: Line Interrupt flag 
+  *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
+  *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag
+  *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag 
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/**
+  * @brief  Clears the LTDC pending flags.
+  * @param  __HANDLE__: LTDC handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg LTDC_FLAG_LI: Line Interrupt flag 
+  *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
+  *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag
+  *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag 
+  * @retval None
+  */
+#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR |= (__FLAG__))
+
+/**
+  * @brief  Enables the specified LTDC interrupts.
+  * @param  __HANDLE__: LTDC handle
+  * @param __INTERRUPT__: specifies the LTDC interrupt sources to be enabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg LTDC_IT_LI: Line Interrupt flag 
+  *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
+  *            @arg LTDC_IT_TE: Transfer Error interrupt flag
+  *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
+  * @retval None
+  */
+#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+  * @brief  Disables the specified LTDC interrupts.
+  * @param  __HANDLE__: LTDC handle
+  * @param __INTERRUPT__: specifies the LTDC interrupt sources to be disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg LTDC_IT_LI: Line Interrupt flag 
+  *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
+  *            @arg LTDC_IT_TE: Transfer Error interrupt flag
+  *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
+  * @retval None
+  */
+#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified LTDC interrupt has occurred or not.
+  * @param  __HANDLE__: LTDC handle
+  * @param  __INTERRUPT__: specifies the LTDC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg LTDC_IT_LI: Line Interrupt flag 
+  *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
+  *            @arg LTDC_IT_TE: Transfer Error interrupt flag
+  *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
+  * @retval The state of INTERRUPT (SET or RESET).
+  */
+#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);
+void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);
+void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc);
+
+/* IO operation functions *****************************************************/
+void  HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
+
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
+HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
+
+/* Peripheral State functions *************************************************/
+HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
+uint32_t              HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
+
+#endif /* STM32F429xx || STM32F439xx */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_LTDC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1070 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_nand.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   NAND HAL module driver.
+  *          This file provides a generic firmware to drive NAND memories mounted 
+  *          as external device.
+  *         
+  @verbatim
+  ==============================================================================
+                         ##### How to use this driver #####
+  ==============================================================================    
+    [..]
+      This driver is a generic layered driver which contains a set of APIs used to 
+      control NAND flash memories. It uses the FMC/FSMC layer functions to interface 
+      with NAND devices. This driver is used as follows:
+    
+      (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() 
+          with control and timing parameters for both common and attribute spaces.
+            
+      (+) Read NAND flash memory maker and device IDs using the function
+          HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef 
+          structure declared by the function caller. 
+        
+      (+) Access NAND flash memory by read/write operations using the functions
+          HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
+          to read/write page(s)/spare area(s). These functions use specific device 
+          information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef 
+          structure. The read/write address information is contained by the Nand_Address_Typedef
+          structure passed as parameter.
+        
+      (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
+        
+      (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
+          The erase block address information is contained in the Nand_Address_Typedef 
+          structure passed as parameter.
+    
+      (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
+        
+      (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
+          HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
+          feature or the function HAL_NAND_GetECC() to get the ECC correction code. 
+       
+      (+) You can monitor the NAND device HAL state by calling the function
+          HAL_NAND_GetState()  
+
+    [..]
+      (@) This driver is a set of generic APIs which handle standard NAND flash operations.
+          If a NAND flash device contains different operations and/or implementations, 
+          it should be implemented separately.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup NAND 
+  * @brief NAND driver modules
+  * @{
+  */
+#ifdef HAL_NAND_MODULE_ENABLED
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/    
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup NAND_Private_Functions
+  * @{
+  */
+    
+/** @defgroup NAND_Group1 Initialization and de-initialization functions 
+  * @brief    Initialization and Configuration functions 
+  *
+  @verbatim    
+  ==============================================================================
+            ##### NAND Initialization and de-initialization functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to initialize/de-initialize
+    the NAND memory
+  
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Perform NAND memory Initialization sequence
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  ComSpace_Timing: pointer to Common space timing structure
+  * @param  AttSpace_Timing: pointer to Attribute space timing structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
+{
+  /* Check the NAND handle state */
+  if(hnand == NULL)
+  {
+     return HAL_ERROR;
+  }
+
+  if(hnand->State == HAL_NAND_STATE_RESET)
+  {
+    /* Initialize the low level hardware (MSP) */
+    HAL_NAND_MspInit(hnand);
+  } 
+
+  /* Initialize NAND control Interface */
+  FMC_NAND_Init(hnand->Instance, &(hnand->Init));
+  
+  /* Initialize NAND common space timing Interface */  
+  FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
+  
+  /* Initialize NAND attribute space timing Interface */  
+  FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
+  
+  /* Enable the NAND device */
+  __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
+  
+  /* Update the NAND controller state */
+  hnand->State = HAL_NAND_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Perform NAND memory De-Initialization sequence
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)  
+{
+  /* Initialize the low level hardware (MSP) */
+  HAL_NAND_MspDeInit(hnand);
+
+  /* Configure the NAND registers with their reset values */
+  FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
+
+  /* Reset the NAND controller state */
+  hnand->State = HAL_NAND_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hnand);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  NAND MSP Init
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval None
+  */
+__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_NAND_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  NAND MSP DeInit
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval None
+  */
+__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_NAND_MspDeInit could be implemented in the user file
+   */ 
+}
+
+
+/**
+  * @brief  This function handles NAND device interrupt request.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval HAL status
+*/
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
+{
+  /* Check NAND interrupt Rising edge flag */
+  if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
+  {
+    /* NAND interrupt callback*/
+    HAL_NAND_ITCallback(hnand);
+  
+    /* Clear NAND interrupt Rising edge pending bit */
+    __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
+  }
+  
+  /* Check NAND interrupt Level flag */
+  if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
+  {
+    /* NAND interrupt callback*/
+    HAL_NAND_ITCallback(hnand);
+  
+    /* Clear NAND interrupt Level pending bit */
+    __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
+  }
+
+  /* Check NAND interrupt Falling edge flag */
+  if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
+  {
+    /* NAND interrupt callback*/
+    HAL_NAND_ITCallback(hnand);
+  
+    /* Clear NAND interrupt Falling edge pending bit */
+    __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
+  }
+  
+  /* Check NAND interrupt FIFO empty flag */
+  if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
+  {
+    /* NAND interrupt callback*/
+    HAL_NAND_ITCallback(hnand);
+  
+    /* Clear NAND interrupt FIFO empty pending bit */
+    __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
+  }  
+
+}
+
+/**
+  * @brief  NAND interrupt feature callback
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval None
+  */
+__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_NAND_ITCallback could be implemented in the user file
+   */
+}
+ 
+/**
+  * @}
+  */
+  
+/** @defgroup NAND_Group2 Input and Output functions 
+  * @brief    Input Output and memory control functions 
+  *
+  @verbatim    
+  ==============================================================================
+                    ##### NAND Input and Output functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to use and control the NAND 
+    memory
+  
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read the NAND memory electronic signature
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pNAND_ID: NAND ID structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
+{
+  __IO uint32_t data = 0;
+  uint32_t deviceAddress = 0;
+
+  /* Process Locked */
+  __HAL_LOCK(hnand);  
+  
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Identify the device address */
+  if(hnand->Init.NandBank == FMC_NAND_BANK2)
+  {
+    deviceAddress = NAND_DEVICE1;
+  }
+  else
+  {
+    deviceAddress = NAND_DEVICE2;
+  }
+  
+  /* Update the NAND controller state */ 
+  hnand->State = HAL_NAND_STATE_BUSY;
+  
+  /* Send Read ID command sequence */ 	
+  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA))  = 0x90;
+  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
+
+  /* Read the electronic signature from NAND flash */	
+  data = *(__IO uint32_t *)deviceAddress;
+  
+  /* Return the data read */
+  pNAND_ID->Maker_Id   = ADDR_1st_CYCLE(data);
+  pNAND_ID->Device_Id  = ADDR_2nd_CYCLE(data);
+  pNAND_ID->Third_Id   = ADDR_3rd_CYCLE(data);
+  pNAND_ID->Fourth_Id  = ADDR_4th_CYCLE(data);
+  
+  /* Update the NAND controller state */ 
+  hnand->State = HAL_NAND_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnand);   
+   
+  return HAL_OK;
+}
+
+/**
+  * @brief  NAND memory reset
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
+{
+  uint32_t deviceAddress = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hnand);
+    
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+
+  /* Identify the device address */  
+  if(hnand->Init.NandBank == FMC_NAND_BANK2)
+  {
+    deviceAddress = NAND_DEVICE1;
+  }
+  else
+  {
+    deviceAddress = NAND_DEVICE2;
+  }  
+  
+  /* Update the NAND controller state */   
+  hnand->State = HAL_NAND_STATE_BUSY; 
+  
+  /* Send NAND reset command */  
+  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
+    
+  
+  /* Update the NAND controller state */   
+  hnand->State = HAL_NAND_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnand);    
+  
+  return HAL_OK;
+  
+}
+
+  
+/**
+  * @brief  Read Page(s) from NAND memory block 
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress : pointer to NAND address structure
+  * @param  pBuffer : pointer to destination read buffer
+  * @param  NumPageToRead : number of pages to read from block 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
+{   
+  __IO uint32_t index  = 0;
+  uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hnand); 
+  
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Identify the device address */
+  if(hnand->Init.NandBank == FMC_NAND_BANK2)
+  {
+    deviceAddress = NAND_DEVICE1;
+  }
+  else
+  {
+    deviceAddress = NAND_DEVICE2;
+  }
+
+  /* Update the NAND controller state */ 
+  hnand->State = HAL_NAND_STATE_BUSY;
+  
+  /* NAND raw address calculation */
+  nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+  
+  /* Page(s) read loop */  
+  while((NumPageToRead != 0) && (nandAddress < (hnand->Info.BlockSize) * (hnand->Info.PageSize)))
+  {	   
+    /* update the buffer size */
+    size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead);
+    
+    /* Send read page command sequence */
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;  
+   
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; 
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(nandAddress); 
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(nandAddress); 
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(nandAddress);
+  
+    /* for 512 and 1 GB devices, 4th cycle is required */    
+    if(hnand->Info.BlockNbr >= 1024)
+    {
+      *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(nandAddress);
+    }
+  
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA))  = 0x30;
+      
+    /* Get Data into Buffer */    
+    for(; index < size; index++)
+    {
+      *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
+    }
+    
+    /* Increment read pages number */
+    numPagesRead++;
+    
+    /* Decrement pages to read */
+    NumPageToRead--;
+    
+    /* Increment the NAND address */
+    nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));   
+    
+  }
+  
+  /* Update the NAND controller state */ 
+  hnand->State = HAL_NAND_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnand);  
+    
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Write Page(s) to NAND memory block 
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress : pointer to NAND address structure
+  * @param  pBuffer : pointer to source buffer to write  
+  * @param  NumPageToWrite  : number of pages to write to block 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
+{
+  __IO uint32_t index   = 0;
+  uint32_t timeout = 0;
+  uint32_t deviceAddress = 0, size = 0 , numPagesWritten = 0, nandAddress = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hnand);  
+
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Identify the device address */
+  if(hnand->Init.NandBank == FMC_NAND_BANK2)
+  {
+    deviceAddress = NAND_DEVICE1;
+  }
+  else
+  {
+    deviceAddress = NAND_DEVICE2;
+  }
+  
+  /* Update the NAND controller state */ 
+  hnand->State = HAL_NAND_STATE_BUSY;
+  
+  /* NAND raw address calculation */
+  nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+  
+  /* Page(s) write loop */
+  while((NumPageToWrite != 0) && (nandAddress < (hnand->Info.BlockSize) * (hnand->Info.PageSize)))
+  {  
+    /* update the buffer size */
+    size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten);
+ 
+    /* Send write page command sequence */
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x80;
+
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;  
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(nandAddress);  
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(nandAddress);  
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(nandAddress);
+  
+    /* for 512 and 1 GB devices, 4th cycle is required */     
+    if(hnand->Info.BlockNbr >= 1024)
+    {
+      *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(nandAddress);
+    }
+  
+    /* Write data to memory */
+    for(; index < size; index++)
+    {
+      *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
+    }
+   
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x10;
+    
+    /* Read status until NAND is ready */
+    while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+    {
+      /* Check for timeout value */
+      timeout = HAL_GetTick() + NAND_WRITE_TIMEOUT;
+    
+      if(HAL_GetTick() >= timeout)
+      {
+        return HAL_TIMEOUT; 
+      } 
+    }    
+ 
+    /* Increment written pages number */
+    numPagesWritten++;
+    
+    /* Decrement pages to write */
+    NumPageToWrite--;
+    
+    /* Increment the NAND address */
+    nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
+      
+  }
+  
+  /* Update the NAND controller state */ 
+  hnand->State = HAL_NAND_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnand);      
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Read Spare area(s) from NAND memory 
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress : pointer to NAND address structure
+  * @param  pBuffer: pointer to source buffer to write  
+  * @param  NumSpareAreaToRead: Number of spare area to read  
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
+{
+  __IO uint32_t index   = 0; 
+  uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hnand);  
+  
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Identify the device address */
+  if(hnand->Init.NandBank == FMC_NAND_BANK2)
+  {
+    deviceAddress = NAND_DEVICE1;
+  }
+  else
+  {
+    deviceAddress = NAND_DEVICE2;
+  }
+  
+  /* Update the NAND controller state */
+  hnand->State = HAL_NAND_STATE_BUSY; 
+  
+  /* NAND raw address calculation */
+  nandAddress = ARRAY_ADDRESS(pAddress, hnand);    
+  
+  /* Spare area(s) read loop */ 
+  while((NumSpareAreaToRead != 0) && (nandAddress < (hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize)))
+  {     
+    
+    /* update the buffer size */
+    size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numSpareAreaRead);
+    
+    /* Send read spare area command sequence */     
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; 
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(nandAddress);     
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(nandAddress);     
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(nandAddress);
+  
+    /* for 512 and 1 GB devices, 4th cycle is required */    
+    if(hnand->Info.BlockNbr >= 1024)
+    {
+      *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(nandAddress);
+    } 
+
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x30;    
+    
+    /* Get Data into Buffer */
+    for ( ;index < size; index++)
+    {
+      *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
+    }
+    
+    /* Increment read spare areas number */
+    numSpareAreaRead++;
+    
+    /* Decrement spare areas to read */
+    NumSpareAreaToRead--;
+    
+    /* Increment the NAND address */
+    nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize));
+  }
+  
+  /* Update the NAND controller state */
+  hnand->State = HAL_NAND_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnand);     
+
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Write Spare area(s) to NAND memory 
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress : pointer to NAND address structure
+  * @param  pBuffer : pointer to source buffer to write  
+  * @param  NumSpareAreaTowrite  : number of spare areas to write to block
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+{
+  __IO uint32_t index = 0;
+  uint32_t timeout = 0;
+  uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0;
+
+  /* Process Locked */
+  __HAL_LOCK(hnand); 
+  
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Identify the device address */
+  if(hnand->Init.NandBank == FMC_NAND_BANK2)
+  {
+    deviceAddress = NAND_DEVICE1;
+  }
+  else
+  {
+    deviceAddress = NAND_DEVICE2;
+  }
+  
+  /* Update the FMC_NAND controller state */
+  hnand->State = HAL_NAND_STATE_BUSY;
+
+  /* NAND raw address calculation */
+  nandAddress = ARRAY_ADDRESS(pAddress, hnand);  
+  
+  /* Spare area(s) write loop */
+  while((NumSpareAreaTowrite != 0) && (nandAddress < (hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize)))
+  {  
+    /* update the buffer size */
+    size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numSpareAreaWritten);
+
+    /* Send write Spare area command sequence */
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x80;
+
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;  
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(nandAddress);  
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(nandAddress);  
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(nandAddress); 
+  
+    /* for 512 and 1 GB devices, 4th cycle is required */     
+    if(hnand->Info.BlockNbr >= 1024)
+    {
+      *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(nandAddress);
+    }
+  
+    /* Write data to memory */
+    for(; index < size; index++)
+    {
+      *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
+    }
+   
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0x10;
+    
+   
+    /* Read status until NAND is ready */
+    while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+    {
+      /* Check for timeout value */
+      timeout = HAL_GetTick() + NAND_WRITE_TIMEOUT;
+    
+      if(HAL_GetTick() >= timeout)
+      {
+        return HAL_TIMEOUT; 
+      }   
+    }
+
+    /* Increment written spare areas number */
+    numSpareAreaWritten++;
+    
+    /* Decrement spare areas to write */
+    NumSpareAreaTowrite--;
+    
+    /* Increment the NAND address */
+    nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize));   
+      
+  }
+
+  /* Update the NAND controller state */
+  hnand->State = HAL_NAND_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hnand);
+    
+  return HAL_OK;  
+}
+
+/**
+  * @brief  NAND memory Block erase 
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress : pointer to NAND address structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress)
+{
+  uint32_t DeviceAddress = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hnand);
+  
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Identify the device address */
+  if(hnand->Init.NandBank == FMC_NAND_BANK2)
+  {
+    DeviceAddress = NAND_DEVICE1;
+  }
+  else
+  {
+    DeviceAddress = NAND_DEVICE2;
+  }
+  
+  /* Update the NAND controller state */
+  hnand->State = HAL_NAND_STATE_BUSY;  
+  
+  /* Send Erase block command sequence */
+  *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = 0x60;
+
+  *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1st_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+  *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2nd_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+  *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3rd_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+  
+  /* for 512 and 1 GB devices, 4th cycle is required */     
+  if(hnand->Info.BlockNbr >= 1024)
+  {
+    *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_4th_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+  }  
+		
+  *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = 0xD0; 
+  
+  /* Update the NAND controller state */
+  hnand->State = HAL_NAND_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnand);    
+  
+  return HAL_OK;  
+}
+
+
+/**
+  * @brief  NAND memory read status 
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval NAND status
+  */
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
+{
+  uint32_t data = 0;
+  uint32_t DeviceAddress = 0;
+  
+  /* Identify the device address */
+  if(hnand->Init.NandBank == FMC_NAND_BANK2)
+  {
+    DeviceAddress = NAND_DEVICE1;
+  }
+  else
+  {
+    DeviceAddress = NAND_DEVICE2;
+  } 
+
+  /* Send Read status operation command */
+  *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = 0x70;
+  
+  /* Read status register data */
+  data = *(__IO uint8_t *)DeviceAddress;
+
+  /* Return the status */
+  if((data & NAND_ERROR) == NAND_ERROR)
+  {
+    return NAND_ERROR;
+  } 
+  else if((data & NAND_READY) == NAND_READY)
+  {
+    return NAND_READY;
+  }
+
+  return NAND_BUSY; 
+ 
+}
+
+/**
+  * @brief  Increment the NAND memory address
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param pAddress: pointer to NAND adress structure
+  * @retval The new status of the increment address operation. It can be:
+  *           - NAND_VALID_ADDRESS: When the new address is valid address
+  *           - NAND_INVALID_ADDRESS: When the new address is invalid address
+  */
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress)
+{
+  uint32_t status = NAND_VALID_ADDRESS;
+ 
+  /* Increment page address */
+  pAddress->Page++;
+
+  /* Check NAND address is valid */
+  if(pAddress->Page == hnand->Info.BlockSize)
+  {
+    pAddress->Page = 0;
+    pAddress->Block++;
+    
+    if(pAddress->Block == hnand->Info.ZoneSize)
+    {
+      pAddress->Block = 0;
+      pAddress->Zone++;
+
+      if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
+      {
+        status = NAND_INVALID_ADDRESS;
+      }
+    }
+  } 
+  
+  return (status);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup NAND_Group3 Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+  ==============================================================================
+                         ##### NAND Control functions #####
+  ==============================================================================  
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the NAND interface.
+
+@endverbatim
+  * @{
+  */ 
+
+    
+/**
+  * @brief  Enables dynamically NAND ECC feature.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval HAL status
+  */    
+HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
+{
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+
+  /* Update the NAND state */
+  hnand->State = HAL_NAND_STATE_BUSY;
+   
+  /* Enable ECC feature */
+  FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
+  
+  /* Update the NAND state */
+  hnand->State = HAL_NAND_STATE_READY;
+  
+  return HAL_OK;  
+}
+
+
+/**
+  * @brief  Disables dynamically FMC_NAND ECC feature.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval HAL status
+  */  
+HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)  
+{
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+
+  /* Update the NAND state */
+  hnand->State = HAL_NAND_STATE_BUSY;
+    
+  /* Disable ECC feature */
+  FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
+  
+  /* Update the NAND state */
+  hnand->State = HAL_NAND_STATE_READY;
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Disables dynamically NAND ECC feature.
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  ECCval: pointer to ECC value 
+  * @param  Timeout: maximum timeout to wait    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the NAND controller state */
+  if(hnand->State == HAL_NAND_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Update the NAND state */
+  hnand->State = HAL_NAND_STATE_BUSY;  
+   
+  /* Get NAND ECC value */
+  status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
+  
+  /* Update the NAND state */
+  hnand->State = HAL_NAND_STATE_READY;
+
+  return status;  
+}
+                      
+/**
+  * @}
+  */
+  
+    
+/** @defgroup NAND_Group4 State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+  ==============================================================================
+                         ##### NAND State functions #####
+  ==============================================================================  
+  [..]
+    This subsection permits to get in run-time the status of the NAND controller 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  return the NAND state
+  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval HAL state
+  */
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
+{
+  return hnand->State;
+}
+
+/**
+  * @}
+  */  
+
+/**
+  * @}
+  */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* HAL_NAND_MODULE_ENABLED  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,240 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_nand.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of NAND HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_NAND_H
+#define __STM32F4xx_HAL_NAND_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+  #include "stm32f4xx_ll_fsmc.h"
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+  #include "stm32f4xx_ll_fmc.h"
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup NAND
+  * @{
+  */ 
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Exported typedef ----------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  HAL NAND State structures definition
+  */
+typedef enum
+{
+  HAL_NAND_STATE_RESET     = 0x00,  /*!< NAND not yet initialized or disabled */
+  HAL_NAND_STATE_READY     = 0x01,  /*!< NAND initialized and ready for use   */
+  HAL_NAND_STATE_BUSY      = 0x02,  /*!< NAND internal process is ongoing     */
+  HAL_NAND_STATE_ERROR     = 0x03   /*!< NAND error state                     */
+}HAL_NAND_StateTypeDef;
+   
+/** 
+  * @brief  NAND Memory electronic signature Structure definition
+  */
+typedef struct
+{
+  /*<! NAND memory electronic signature maker and device IDs */
+
+  uint8_t Maker_Id; 
+
+  uint8_t Device_Id;
+
+  uint8_t Third_Id;
+
+  uint8_t Fourth_Id;
+}NAND_IDTypeDef;
+
+/** 
+  * @brief  NAND Memory address Structure definition
+  */
+typedef struct 
+{
+  uint16_t Page;   /*!< NAND memory Page address  */
+
+  uint16_t Zone;   /*!< NAND memory Zone address  */
+
+  uint16_t Block;  /*!< NAND memory Block address */
+
+}NAND_AddressTypedef;
+
+/** 
+  * @brief  NAND Memory info Structure definition
+  */ 
+typedef struct
+{
+  uint32_t PageSize;       /*!< NAND memory page (without spare area) size measured in K. bytes */
+
+  uint32_t SpareAreaSize;  /*!< NAND memory spare area size measured in K. bytes                */
+
+  uint32_t BlockSize;      /*!< NAND memory block size number of pages                          */
+
+  uint32_t BlockNbr;       /*!< NAND memory number of blocks                                    */
+
+  uint32_t ZoneSize;       /*!< NAND memory zone size measured in number of blocks              */
+}NAND_InfoTypeDef;
+
+/** 
+  * @brief  NAND handle Structure definition
+  */   
+typedef struct
+{
+  FMC_NAND_TypeDef             *Instance;  /*!< Register base address                        */
+  
+  FMC_NAND_InitTypeDef         Init;       /*!< NAND device control configuration parameters */
+
+  HAL_LockTypeDef              Lock;       /*!< NAND locking object                          */
+
+  __IO HAL_NAND_StateTypeDef   State;      /*!< NAND device access state                     */
+
+  NAND_InfoTypeDef             Info;       /*!< NAND characteristic information structure    */
+}NAND_HandleTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup NAND_Exported_Constants
+ * @{
+ */ 
+#define NAND_DEVICE1               ((uint32_t)0x70000000) 
+#define NAND_DEVICE2               ((uint32_t)0x80000000) 
+#define NAND_WRITE_TIMEOUT         ((uint32_t)0x01000000)
+
+#define CMD_AREA                   ((uint32_t)(1<<16))  /* A16 = CLE high */
+#define ADDR_AREA                  ((uint32_t)(1<<17))  /* A17 = ALE high */
+
+#define	NAND_CMD_AREA_A            ((uint8_t)0x00)
+#define	NAND_CMD_AREA_B            ((uint8_t)0x01)
+#define NAND_CMD_AREA_C            ((uint8_t)0x50)
+
+/* NAND memory status */
+#define NAND_VALID_ADDRESS         ((uint32_t)0x00000100)
+#define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200)
+#define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400)
+#define NAND_BUSY                  ((uint32_t)0x00000000)
+#define NAND_ERROR                 ((uint32_t)0x00000001)
+#define NAND_READY                 ((uint32_t)0x00000040)
+
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset NAND handle state
+  * @param  __HANDLE__: specifies the NAND handle.
+  * @retval None
+  */
+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
+
+/**
+  * @brief  NAND memory address computation.
+  * @param  __ADDRESS__: NAND memory address.
+  * @param  __HANDLE__ : NAND handle.
+  * @retval NAND Raw address value
+  */
+#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.BlockSize)))* ((__HANDLE__)->Info.ZoneSize)))
+
+/**
+  * @brief  NAND memory address cycling.
+  * @param  __ADDRESS__: NAND memory address.
+  * @retval NAND address cycling value.
+  */
+#define ADDR_1st_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__)& 0xFF)               /* 1st addressing cycle */
+#define ADDR_2nd_CYCLE(__ADDRESS__)       (uint8_t)(((__ADDRESS__)& 0xFF00) >> 8)      /* 2nd addressing cycle */
+#define ADDR_3rd_CYCLE(__ADDRESS__)       (uint8_t)(((__ADDRESS__)& 0xFF0000) >> 16)   /* 3rd addressing cycle */
+#define ADDR_4th_CYCLE(__ADDRESS__)       (uint8_t)(((__ADDRESS__)& 0xFF000000) >> 24) /* 4th addressing cycle */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
+void        HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
+void        HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
+void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
+void        HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
+
+/* IO operation functions  ****************************************************/
+HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef  HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef  HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
+uint32_t           HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
+
+/* NAND Control functions  ****************************************************/
+HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
+
+/* NAND State functions *******************************************************/
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_NAND_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,801 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_nor.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   NOR HAL module driver.
+  *          This file provides a generic firmware to drive NOR memories mounted 
+  *          as external device.
+  *         
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================       
+    [..]
+      This driver is a generic layered driver which contains a set of APIs used to 
+      control NOR flash memories. It uses the FMC/FSMC layer functions to interface 
+      with NOR devices. This driver is used as follows:
+    
+      (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() 
+          with control and timing parameters for both normal and extended mode.
+            
+      (+) Read NOR flash memory manufacturer code and device IDs using the function
+          HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef 
+          structure declared by the function caller. 
+        
+      (+) Access NOR flash memory by read/write data unit operations using the functions
+          HAL_NOR_Read(), HAL_NOR_Program().
+        
+      (+) Perform NOR flash erase block/chip operations using the functions 
+          HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
+        
+      (+) Read the NOR flash CFI (common flash interface) IDs using the function
+          HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
+          structure declared by the function caller.
+        
+      (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
+          HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation  
+       
+      (+) You can monitor the NOR device HAL state by calling the function
+          HAL_NOR_GetState() 
+    [..]
+     (@) This driver is a set of generic APIs which handle standard NOR flash operations.
+         If a NOR flash device contains different operations and/or implementations, 
+         it should be implemented separately.
+
+     *** NOR HAL driver macros list ***
+     ============================================= 
+     [..]
+       Below the list of most used macros in NOR HAL driver.
+       
+      (+) __NOR_WRITE : NOR memory write data to specified address
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup NOR 
+  * @brief NOR driver modules
+  * @{
+  */
+#ifdef HAL_NOR_MODULE_ENABLED
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+      
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup NOR_Private_Functions
+  * @{
+  */
+
+/** @defgroup NOR_Group1 Initialization and de-initialization functions 
+  * @brief    Initialization and Configuration functions 
+  *
+  @verbatim    
+  ==============================================================================
+           ##### NOR Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to initialize/de-initialize
+    the NOR memory
+  
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Perform the NOR memory Initialization sequence
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  Timing: pointer to NOR control timing structure 
+  * @param  ExtTiming: pointer to NOR extended mode timing structure    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
+{
+  /* Check the NOR handle parameter */
+  if(hnor == NULL)
+  {
+     return HAL_ERROR;
+  }
+  
+  if(hnor->State == HAL_NOR_STATE_RESET)
+  {
+    /* Initialize the low level hardware (MSP) */
+    HAL_NOR_MspInit(hnor);
+  }
+
+  /* Initialize NOR control Interface */
+  FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
+
+  /* Initialize NOR timing Interface */
+  FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); 
+
+  /* Initialize NOR extended mode timing Interface */
+  FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
+
+  /* Enable the NORSRAM device */
+  __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);  
+
+  /* Check the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY; 
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Perform NOR memory De-Initialization sequence
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)  
+{
+  /* De-Initialize the low level hardware (MSP) */
+  HAL_NOR_MspDeInit(hnor);
+ 
+  /* Configure the NOR registers with their reset values */
+  FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
+  
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hnor);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  NOR MSP Init
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval None
+  */
+__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_NOR_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  NOR MSP DeInit
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval None
+  */
+__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_NOR_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  NOR BSP Wait fro Ready/Busy signal
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  Timeout: Maximum timeout value
+  * @retval None
+  */
+__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_NOR_BspWait could be implemented in the user file
+   */ 
+}
+  
+/**
+  * @}
+  */
+
+/** @defgroup NOR_Group2 Input and Output functions 
+  * @brief    Input Output and memory control functions 
+  *
+  @verbatim    
+  ==============================================================================
+                ##### NOR Input and Output functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to use and control the NOR memory
+  
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Read NOR flash IDs
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  pNOR_ID : pointer to NOR ID structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
+{
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+  
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+    
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_BUSY;
+  
+  /* Send read ID command */
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA);
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055);
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x0090);
+
+  /* Read the NOR IDs */
+  pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) __NOR_ADDR_SHIFT(MC_ADDRESS);
+  pNOR_ID->Device_Code1      = *(__IO uint16_t *) __NOR_ADDR_SHIFT(DEVICE_CODE1_ADDR);
+  pNOR_ID->Device_Code2      = *(__IO uint16_t *) __NOR_ADDR_SHIFT(DEVICE_CODE2_ADDR);
+  pNOR_ID->Device_Code3      = *(__IO uint16_t *) __NOR_ADDR_SHIFT(DEVICE_CODE3_ADDR);
+  
+  /* Check the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor);   
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns the NOR memory to Read mode.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
+{
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+  
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  __NOR_WRITE(NOR_MEMORY_ADRESS, 0x00F0);
+
+  /* Check the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor);   
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read data from NOR memory 
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  pAddress: pointer to Device address
+  * @param  pData : pointer to read data  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
+{
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+  
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+    
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_BUSY;
+  
+  /* Send read data command */
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x00555), 0x00AA); 
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x002AA), 0x0055);  
+  __NOR_WRITE(*pAddress, 0x00F0);
+
+  /* Read the data */
+  *pData = *(__IO uint32_t *)pAddress;
+  
+  /* Check the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Program data to NOR memory 
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  pAddress: Device address
+  * @param  pData : pointer to the data to write   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
+{
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+  
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+    
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_BUSY;
+  
+  /* Send program data command */
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA);
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055);
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00A0);
+
+  /* Write the data */
+  __NOR_WRITE(pAddress, *pData);
+  
+  /* Check the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Reads a block of data from the FMC NOR memory.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  uwAddress: NOR memory internal address to read from.
+  * @param  pData: pointer to the buffer that receives the data read from the 
+  *         NOR memory.
+  * @param  uwBufferSize : number of Half word to read.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+{
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+  
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+    
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_BUSY;
+  
+  /* Send read data command */
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x00555), 0x00AA); 
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x002AA), 0x0055);  
+  __NOR_WRITE(uwAddress, 0x00F0);
+  
+  /* Read buffer */
+  while( uwBufferSize > 0) 
+  {
+    *pData++ = *(__IO uint16_t *)uwAddress;
+    uwAddress += 2;
+    uwBufferSize--;
+  } 
+  
+  /* Check the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Writes a half-word buffer to the FMC NOR memory. This function 
+  *         must be used only with S29GL128P NOR memory. 
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  uwAddress: NOR memory internal address from which the data 
+  * @param  pData: pointer to source data buffer. 
+  * @param  uwBufferSize: number of Half words to write. The maximum allowed 
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+{
+  uint32_t lastloadedaddress = 0;
+  uint32_t currentaddress = 0;
+  uint32_t endaddress = 0;
+
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+  
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+    
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_BUSY;
+  
+  /* Initialize variables */
+  currentaddress    = uwAddress;
+  endaddress        = uwAddress + uwBufferSize - 1;
+  lastloadedaddress = uwAddress;
+
+  /* Issue unlock command sequence */
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA);
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055); 
+
+  /* Write Buffer Load Command */
+  __NOR_WRITE(__NOR_ADDR_SHIFT(uwAddress), 0x25); 
+  __NOR_WRITE(__NOR_ADDR_SHIFT(uwAddress), (uwBufferSize - 1)); 
+
+  /* Load Data into NOR Buffer */
+  while(currentaddress <= endaddress)
+  {
+    /* Store last loaded address & data value (for polling) */
+    lastloadedaddress = currentaddress;
+ 
+    __NOR_WRITE(__NOR_ADDR_SHIFT(currentaddress), *pData++);
+    
+    currentaddress += 1; 
+  }
+
+  __NOR_WRITE(__NOR_ADDR_SHIFT(lastloadedaddress), 0x29); 
+  
+  /* Check the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor);
+  
+  return HAL_OK; 
+  
+}
+
+/**
+  * @brief  Erase the specified block of the NOR memory 
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  BlockAddress : Block to erase address 
+  * @param  Address: Device address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
+{
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+  
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+    
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_BUSY;
+  
+  /* Send block erase command sequence */
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA);
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055);
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x0080);
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA);
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055);
+  __NOR_WRITE((uint32_t)(BlockAddress + Address), 0x30);
+
+  /* Check the NOR memory status and update the controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+    
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor);
+  
+  return HAL_OK;
+ 
+}
+
+/**
+  * @brief  Erase the entire NOR chip.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  Address : Device address  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
+{
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+  
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+    
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_BUSY;  
+    
+  /* Send NOR chip erase command sequence */
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA);
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055);
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x0080);
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x00AA);
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x02AA), 0x0055);  
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x0555), 0x0010);
+  
+  /* Check the NOR memory status and update the controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+    
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Read NOR flash CFI IDs
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  pNOR_CFI : pointer to NOR CFI IDs structure  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
+{
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+  
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+    
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_BUSY;
+  
+  /* Send read CFI query command */
+  __NOR_WRITE(__NOR_ADDR_SHIFT(0x0055), 0x0098);
+
+  /* read the NOR CFI information */
+  pNOR_CFI->CFI_1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(CFI1_ADDRESS);
+  pNOR_CFI->CFI_2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(CFI2_ADDRESS);
+  pNOR_CFI->CFI_3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(CFI3_ADDRESS);
+  pNOR_CFI->CFI_4 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(CFI4_ADDRESS);
+
+  /* Check the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor);
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup NOR_Group3 Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+  ==============================================================================
+                        ##### NOR Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the NOR interface.
+
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Enables dynamically NOR write operation.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
+{
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+
+  /* Enable write operation */
+  FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); 
+  
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor); 
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Disables dynamically NOR write operation.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
+{
+  /* Process Locked */
+  __HAL_LOCK(hnor);
+
+  /* Update the SRAM controller state */
+  hnor->State = HAL_NOR_STATE_BUSY;
+    
+  /* Disable write operation */
+  FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); 
+  
+  /* Update the NOR controller state */
+  hnor->State = HAL_NOR_STATE_PROTECTED;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hnor); 
+  
+  return HAL_OK;  
+}
+
+/**
+  * @}
+  */  
+  
+/** @defgroup NOR_Group4 State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### NOR State functions #####
+  ==============================================================================  
+  [..]
+    This subsection permits to get in run-time the status of the NOR controller 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  return the NOR controller state
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval NOR controller state
+  */
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
+{
+  return hnor->State;
+}
+
+/**
+  * @brief  Returns the NOR operation status.
+  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.   
+  * @param  Address: Device address
+  * @param  Timeout: NOR progamming Timeout
+  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
+  *         or NOR_TIMEOUT
+  */
+NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
+{ 
+  NOR_StatusTypedef status = NOR_ONGOING;
+  uint16_t tmpSR1 = 0, tmpSR2 = 0;
+  uint32_t timeout = 0;
+
+  /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
+  HAL_NOR_MspWait(hnor, timeout);
+  
+  /* Get the NOR memory operation status -------------------------------------*/
+  while(status != NOR_SUCCESS)
+  {
+    /* Check for timeout value */
+    timeout = HAL_GetTick() + Timeout;
+    
+    if(HAL_GetTick() >= timeout)
+    {
+      status = NOR_TIMEOUT; 
+    }  
+    
+    /* Read NOR status register (DQ6 and DQ5) */
+    tmpSR1 = *(__IO uint16_t *)Address;
+    tmpSR2 = *(__IO uint16_t *)Address;
+
+    /* If DQ6 did not toggle between the two reads then return NOR_Success */
+    if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040)) 
+    {
+      return NOR_SUCCESS;
+    }
+    
+    if((tmpSR1 & 0x0020) == 0x0020)
+    {
+      return NOR_ONGOING;
+    }
+    
+    tmpSR1 = *(__IO uint16_t *)Address;
+    tmpSR2 = *(__IO uint16_t *)Address;
+
+    /* If DQ6 did not toggle between the two reads then return NOR_Success */
+    if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040)) 
+    {
+      return NOR_SUCCESS;
+    }
+    
+    if((tmpSR1 & 0x0020) == 0x0020)
+    {
+      return NOR_ERROR;
+    } 
+  }
+
+  /* Return the operation status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* HAL_NOR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,243 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_nor.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of NOR HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_NOR_H
+#define __STM32F4xx_HAL_NOR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+  #include "stm32f4xx_ll_fsmc.h"
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+  #include "stm32f4xx_ll_fmc.h"
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup NOR
+  * @{
+  */ 
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Exported typedef ----------------------------------------------------------*/
+/** 
+  * @brief  HAL SRAM State structures definition  
+  */ 
+typedef enum
+{  
+  HAL_NOR_STATE_RESET             = 0x00,  /*!< NOR not yet initialized or disabled  */
+  HAL_NOR_STATE_READY             = 0x01,  /*!< NOR initialized and ready for use    */
+  HAL_NOR_STATE_BUSY              = 0x02,  /*!< NOR internal processing is ongoing   */
+  HAL_NOR_STATE_ERROR             = 0x03,  /*!< NOR error state                      */
+  HAL_NOR_STATE_PROTECTED         = 0x04   /*!< NOR NORSRAM device write protected   */
+}HAL_NOR_StateTypeDef;
+
+/**
+  * @brief  FMC NOR Status typedef
+  */
+typedef enum
+{
+  NOR_SUCCESS = 0,
+  NOR_ONGOING,
+  NOR_ERROR,
+  NOR_TIMEOUT
+}NOR_StatusTypedef;
+
+/**
+  * @brief  FMC NOR ID typedef
+  */
+typedef struct
+{
+  uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
+
+  uint16_t Device_Code1;
+
+  uint16_t Device_Code2;
+
+  uint16_t Device_Code3;       /*!< Defines the devices' codes used to identify the memory. 
+                                    These codes can be accessed by performing read operations with specific 
+                                    control signals and addresses set.They can also be accessed by issuing 
+                                    an Auto Select command                                                   */
+}NOR_IDTypeDef;
+
+/**
+  * @brief  FMC NOR CFI typedef
+  */
+typedef struct
+{
+  /*!< Defines the information stored in the memory's Common flash interface
+       which contains a description of various electrical and timing parameters, 
+       density information and functions supported by the memory                   */
+
+  uint16_t CFI_1;
+
+  uint16_t CFI_2;
+
+  uint16_t CFI_3;
+
+  uint16_t CFI_4;
+}NOR_CFITypeDef;
+
+/** 
+  * @brief  NOR handle Structure definition
+  */ 
+typedef struct
+{
+  FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
+
+  FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
+
+  FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
+
+  HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
+
+  __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
+
+}NOR_HandleTypeDef; 
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup NOR_Exported_Constants
+  * @{
+  */
+/* NOR device IDs addresses */
+#define MC_ADDRESS               ((uint16_t)0x0000)
+#define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
+#define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
+#define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
+
+/* NOR CFI IDs addresses */
+#define CFI1_ADDRESS             ((uint16_t)0x61)
+#define CFI2_ADDRESS             ((uint16_t)0x62)
+#define CFI3_ADDRESS             ((uint16_t)0x63)
+#define CFI4_ADDRESS             ((uint16_t)0x64)
+
+/* NOR operation wait timeout */
+#define NOR_TMEOUT               ((uint16_t)0xFFFF)
+   
+/* #define NOR_MEMORY_16B */
+#define NOR_MEMORY_8B
+
+/* NOR memory device read/write start address */
+#define NOR_MEMORY_ADRESS        ((uint32_t)0x60000000)
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset NOR handle state
+  * @param  __HANDLE__: specifies the NOR handle.
+  * @retval None
+  */
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
+
+/**
+  * @brief  NOR memory address shifting.
+  * @param  __ADDRESS__: NOR memory address 
+  * @retval NOR shifted address value
+  */
+#ifdef  NOR_MEMORY_8B
+ #define __NOR_ADDR_SHIFT(__ADDRESS__) (uint32_t)(NOR_MEMORY_ADRESS + (2 * (__ADDRESS__)))
+#else /* NOR_MEMORY_16B */
+ #define __NOR_ADDR_SHIFT(__ADDRESS__) (uint32_t)(NOR_MEMORY_ADRESS + (__ADDRESS__))
+#endif /* NOR_MEMORY_8B */ 
+ 
+/**
+  * @brief  NOR memory write data to specified address.
+  * @param  __ADDRESS__: NOR memory address 
+  * @param  __DATA__: Data to write
+  * @retval None
+  */
+#define __NOR_WRITE(__ADDRESS__, __DATA__)  (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
+
+/* I/O operation functions  ***************************************************/
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
+
+/* NOR Control functions  *****************************************************/
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
+
+/* NOR State functions ********************************************************/
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
+NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_NOR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,726 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_pccard.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   PCCARD HAL module driver.
+  *          This file provides a generic firmware to drive PCCARD memories mounted 
+  *          as external device.
+  *         
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================  
+   [..]
+     This driver is a generic layered driver which contains a set of APIs used to 
+     control PCCARD/compact flash memories. It uses the FMC/FSMC layer functions 
+     to interface with PCCARD devices. This driver is used for:
+    
+    (+) PCCARD/compact flash memory configuration sequence using the function 
+        HAL_PCCARD_Init() with control and timing parameters for both common and 
+        attribute spaces.
+            
+    (+) Read PCCARD/compact flash memory maker and device IDs using the function
+        HAL_CF_Read_ID(). The read information is stored in the CompactFlash_ID 
+        structure declared by the function caller. 
+        
+    (+) Access PCCARD/compact flash memory by read/write operations using the functions
+        HAL_CF_Read_Sector()/HAL_CF_Write_Sector(), to read/write sector. 
+        
+    (+) Perform PCCARD/compact flash Reset chip operation using the function HAL_CF_Reset().
+        
+    (+) Perform PCCARD/compact flash erase sector operation using the function 
+        HAL_CF_Erase_Sector().
+    
+    (+) Read the PCCARD/compact flash status operation using the function HAL_CF_ReadStatus().
+     
+    (+) You can monitor the PCCARD/compact flash  device HAL state by calling the function
+        HAL_PCCARD_GetState()     
+        
+   [..]
+     (@) This driver is a set of generic APIs which handle standard PCCARD/compact flash 
+         operations. If a PCCARD/compact flash device contains different operations 
+         and/or implementations, it should be implemented separately.
+   
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PCCARD 
+  * @brief PCCARD driver modules
+  * @{
+  */
+#ifdef HAL_PCCARD_MODULE_ENABLED
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PCCARD_Private_Functions
+  * @{
+  */
+
+/** @defgroup PCCARD_Group1 Initialization and de-initialization functions 
+  * @brief    Initialization and Configuration functions 
+  *
+  @verbatim    
+  ==============================================================================
+          ##### PCCARD Initialization and de-initialization functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to initialize/de-initialize
+    the PCCARD memory
+  
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Perform the PCCARD memory Initialization sequence
+  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  *                the configuration information for PCCARD module.
+  * @param  ComSpaceTiming: Common space timing structure
+  * @param  AttSpaceTiming: Attribute space timing structure
+  * @param  IOSpaceTiming: IO space timing structure     
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
+{
+  /* Check the PCCARD controller state */
+  if(hpccard == NULL)
+  {
+     return HAL_ERROR;
+  }
+  
+  if(hpccard->State == HAL_PCCARD_STATE_RESET)
+  {  
+    /* Initialize the low level hardware (MSP) */
+    HAL_PCCARD_MspInit(hpccard);
+  }
+  
+  /* Initialize the PCCARD state */
+  hpccard->State = HAL_PCCARD_STATE_BUSY;    
+
+  /* Initialize PCCARD control Interface */
+  FMC_PCCARD_Init(hpccard->Instance, &(hpccard->Init));
+  
+  /* Init PCCARD common space timing Interface */
+  FMC_PCCARD_CommonSpace_Timing_Init(hpccard->Instance, ComSpaceTiming);
+  
+  /* Init PCCARD attribute space timing Interface */  
+  FMC_PCCARD_AttributeSpace_Timing_Init(hpccard->Instance, AttSpaceTiming);
+  
+  /* Init PCCARD IO space timing Interface */  
+  FMC_PCCARD_IOSpace_Timing_Init(hpccard->Instance, IOSpaceTiming);
+  
+  /* Enable the PCCARD device */
+  __FMC_PCCARD_ENABLE(hpccard->Instance); 
+  
+  /* Update the PCCARD state */
+  hpccard->State = HAL_PCCARD_STATE_READY;  
+  
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Perform the PCCARD memory De-initialization sequence
+  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  *                the configuration information for PCCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
+{
+  /* De-Initialize the low level hardware (MSP) */
+  HAL_PCCARD_MspDeInit(hpccard);
+   
+  /* Configure the PCCARD registers with their reset values */
+  FMC_PCCARD_DeInit(hpccard->Instance);
+  
+  /* Update the PCCARD controller state */
+  hpccard->State = HAL_PCCARD_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpccard);
+
+  return HAL_OK; 
+}
+
+/**
+  * @brief  PCCARD MSP Init
+  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  *                the configuration information for PCCARD module.
+  * @retval None
+  */
+__weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCCARD_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  PCCARD MSP DeInit
+  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  *                the configuration information for PCCARD module.
+  * @retval None
+  */
+__weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCCARD_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PCCARD_Group2 Input and Output functions 
+  * @brief    Input Output and memory control functions 
+  *
+  @verbatim    
+  ==============================================================================
+                    ##### PCCARD Input and Output functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to use and control the PCCARD memory
+  
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Read Compact Flash's ID.
+  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  *                the configuration information for PCCARD module.
+  * @param  CompactFlash_ID: Compact flash ID structure.  
+  * @param  pStatus: pointer to compact flash status         
+  * @retval HAL status
+  *   
+  */ 
+HAL_StatusTypeDef HAL_CF_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
+{
+  uint32_t timeout = 0xFFFF, index;
+  uint8_t status;
+  
+  /* Process Locked */
+  __HAL_LOCK(hpccard);  
+  
+  /* Check the PCCARD controller state */
+  if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Update the PCCARD controller state */
+  hpccard->State = HAL_PCCARD_STATE_BUSY;
+  
+  /* Initialize the CF status */
+  *pStatus = CF_READY;  
+  
+  /* Send the Identify Command */
+  *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD)  = 0xECEC;
+    
+  /* Read CF IDs and timeout treatment */
+  do 
+  {
+     /* Read the CF status */
+     status = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+     
+     timeout--;
+  }while((status != 0x58) && timeout); 
+  
+  if(timeout == 0)
+  {
+    *pStatus = CF_TIMEOUT_ERROR;
+  }
+  else
+  {
+     /* Read CF ID bytes */
+    for(index = 0; index < 16; index++)
+    {
+      CompactFlash_ID[index] = *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_DATA);
+    }    
+  }
+  
+  /* Update the PCCARD controller state */
+  hpccard->State = HAL_PCCARD_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hpccard);  
+  
+  return HAL_OK;
+}
+   
+/**
+  * @brief  Read sector from PCCARD memory
+  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  *                the configuration information for PCCARD module.
+  * @param  pBuffer: pointer to destination read buffer
+  * @param  SectorAddress: Sector address to read
+  * @param  pStatus: pointer to CF status
+  * @retval HAL status
+  */    
+HAL_StatusTypeDef HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
+{
+  uint32_t timeout = 0xFFFF, index = 0;
+  uint8_t status;
+
+  /* Process Locked */
+  __HAL_LOCK(hpccard);
+  
+  /* Check the PCCARD controller state */
+  if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+  
+  /* Update the PCCARD controller state */
+  hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+  /* Initialize CF status */
+  *pStatus = CF_READY;
+
+  /* Set the parameters to write a sector */
+  *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_HIGH) = (uint16_t)0x00;
+  *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_COUNT)  = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
+  *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD)    = (uint16_t)0xE4A0;  
+
+  do
+  {
+    /* wait till the Status = 0x80 */
+    status =  *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+    timeout--;
+  }while((status == 0x80) && timeout);
+  
+  if(timeout == 0)
+  {
+    *pStatus = CF_TIMEOUT_ERROR;
+  }
+  
+  timeout = 0xFFFF;
+
+  do
+  {
+    /* wait till the Status = 0x58 */
+    status =  *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+    timeout--;
+  }while((status != 0x58) && timeout);
+  
+  if(timeout == 0)
+  {
+    *pStatus = CF_TIMEOUT_ERROR;
+  }
+  
+  /* Read bytes */
+  for(; index < CF_SECTOR_SIZE; index++)
+  {
+    *(uint16_t *)pBuffer++ = *(uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR);
+  } 
+
+  /* Update the PCCARD controller state */
+  hpccard->State = HAL_PCCARD_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hpccard);
+      
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Write sector to PCCARD memory
+  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  *                the configuration information for PCCARD module.
+  * @param  pBuffer: pointer to source write buffer
+  * @param  SectorAddress: Sector address to write
+  * @param  pStatus: pointer to CF status
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CF_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,  uint8_t *pStatus)
+{
+  uint32_t timeout = 0xFFFF, index = 0;
+  uint8_t status;
+
+  /* Process Locked */
+  __HAL_LOCK(hpccard);  
+  
+  /* Check the PCCARD controller state */
+  if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+   
+  /* Update the PCCARD controller state */
+  hpccard->State = HAL_PCCARD_STATE_BUSY;
+    
+  /* Initialize CF status */
+  *pStatus = CF_READY;  
+    
+  /* Set the parameters to write a sector */
+  *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_HIGH) = (uint16_t)0x00;
+  *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_COUNT)  = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
+  *(__IO uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD)    = (uint16_t)0x30A0;
+  
+  do
+  {
+    /* Wait till the Status = 0x58 */
+    status =  *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+    timeout--;
+  }while((status != 0x58) && timeout);
+  
+  if(timeout == 0)
+  {
+    *pStatus = CF_TIMEOUT_ERROR;
+  }
+  
+  /* Write bytes */
+  for(; index < CF_SECTOR_SIZE; index++)
+  {
+    *(uint16_t *)(CF_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
+  }
+
+  do
+  {
+    /* Wait till the Status = 0x50 */
+    status =  *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+    timeout--;
+  }while((status != 0x50) && timeout);
+
+  if(timeout == 0)
+  {
+    *pStatus = CF_TIMEOUT_ERROR;
+  }  
+
+  /* Update the PCCARD controller state */
+  hpccard->State = HAL_PCCARD_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hpccard);  
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Erase sector from PCCARD memory 
+  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  *                the configuration information for PCCARD module.
+  * @param  SectorAddress: Sector address to erase
+  * @param  pStatus: pointer to CF status
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
+{
+  uint32_t timeout = 0x400;
+  uint8_t status;
+  
+  /* Process Locked */
+  __HAL_LOCK(hpccard);  
+  
+  /* Check the PCCARD controller state */
+  if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+
+  /* Update the PCCARD controller state */
+  hpccard->State = HAL_PCCARD_STATE_BUSY;
+  
+  /* Initialize CF status */ 
+  *pStatus = CF_READY;
+    
+  /* Set the parameters to write a sector */
+  *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_LOW)  = 0x00;
+  *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CYLINDER_HIGH) = 0x00;
+  *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_NUMBER) = SectorAddress;
+  *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_SECTOR_COUNT)  = 0x01;
+  *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_CARD_HEAD)     = 0xA0;
+  *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD)    = CF_ERASE_SECTOR_CMD;
+  
+  /* wait till the CF is ready */
+  status =  *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+  
+  while((status != 0x50) && timeout)
+  {
+    status =  *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+    timeout--;
+  } 
+  
+  if(timeout == 0)
+  {
+    *pStatus = CF_TIMEOUT_ERROR;
+  }
+  
+  /* Check the PCCARD controller state */
+  hpccard->State = HAL_PCCARD_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hpccard);   
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reset the PCCARD memory 
+  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  *                the configuration information for PCCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CF_Reset(PCCARD_HandleTypeDef *hpccard)
+{
+
+  /* Process Locked */
+  __HAL_LOCK(hpccard);  
+  
+  /* Check the PCCARD controller state */
+  if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+  {
+     return HAL_BUSY;
+  }
+
+  /* Provide an SW reset and Read and verify the:
+   - CF Configuration Option Register at address 0x98000200 --> 0x80
+   - Card Configuration and Status Register	at address 0x98000202 --> 0x00
+   - Pin Replacement Register  at address 0x98000204 --> 0x0C
+   - Socket and Copy Register at address 0x98000206 --> 0x00
+  */
+
+  /* Check the PCCARD controller state */
+  hpccard->State = HAL_PCCARD_STATE_BUSY;
+  
+  *(__IO uint8_t *)(0x98000202) = 0x01;
+    
+  /* Check the PCCARD controller state */
+  hpccard->State = HAL_PCCARD_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hpccard);  
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles PCCARD device interrupt request.
+  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  *                the configuration information for PCCARD module.
+  * @retval HAL status
+*/
+void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
+{
+  /* Check PCCARD interrupt Rising edge flag */
+  if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE))
+  {
+    /* PCCARD interrupt callback*/
+    HAL_PCCARD_ITCallback(hpccard);
+  
+    /* Clear PCCARD interrupt Rising edge pending bit */
+    __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE);
+  }
+  
+  /* Check PCCARD interrupt Level flag */
+  if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_LEVEL))
+  {
+    /* PCCARD interrupt callback*/
+    HAL_PCCARD_ITCallback(hpccard);
+  
+    /* Clear PCCARD interrupt Level pending bit */
+    __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_LEVEL);
+  }
+
+  /* Check PCCARD interrupt Falling edge flag */
+  if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE))
+  {
+    /* PCCARD interrupt callback*/
+    HAL_PCCARD_ITCallback(hpccard);
+  
+    /* Clear PCCARD interrupt Falling edge pending bit */
+    __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE);
+  }
+  
+  /* Check PCCARD interrupt FIFO empty flag */
+  if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FEMPT))
+  {
+    /* PCCARD interrupt callback*/
+    HAL_PCCARD_ITCallback(hpccard);
+  
+    /* Clear PCCARD interrupt FIFO empty pending bit */
+    __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FEMPT);
+  }  
+
+}
+
+/**
+  * @brief  PCCARD interrupt feature callback
+  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  *                the configuration information for PCCARD module.
+  * @retval None
+  */
+__weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCCARD_ITCallback could be implemented in the user file
+   */
+}
+  
+/**
+  * @}
+  */
+
+/** @defgroup PCCARD_Group4 State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### PCCARD State functions #####
+  ==============================================================================  
+  [..]
+    This subsection permits to get in run-time the status of the PCCARD controller 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */ 
+  
+/**
+  * @brief  return the PCCARD controller state
+  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  *                the configuration information for PCCARD module.
+  * @retval HAL state
+  */
+HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
+{
+  return hpccard->State;
+}  
+ 
+/**
+  * @brief  Get the compact flash memory status
+  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  *                the configuration information for PCCARD module.       
+  * @retval New status of the CF operation. This parameter can be:
+  *          - CompactFlash_TIMEOUT_ERROR: when the previous operation generate 
+  *            a Timeout error
+  *          - CompactFlash_READY: when memory is ready for the next operation     
+  *                
+  */
+CF_StatusTypedef HAL_CF_GetStatus(PCCARD_HandleTypeDef *hpccard)
+{
+  uint32_t timeout = 0x1000000, status_CF;  
+  
+  /* Check the PCCARD controller state */
+  if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+  {
+     return CF_ONGOING;
+  }
+
+  status_CF =  *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+  
+  while((status_CF == CF_BUSY) && timeout)
+  {
+    status_CF =  *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+    timeout--;
+  }
+
+  if(timeout == 0)
+  {          
+    status_CF =  CF_TIMEOUT_ERROR;      
+  }   
+
+  /* Return the operation status */
+  return (CF_StatusTypedef) status_CF;      
+}
+  
+/**
+  * @brief  Reads the Compact Flash memory status using the Read status command
+  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  *                the configuration information for PCCARD module.      
+  * @retval The status of the Compact Flash memory. This parameter can be:
+  *          - CompactFlash_BUSY: when memory is busy
+  *          - CompactFlash_READY: when memory is ready for the next operation    
+  *          - CompactFlash_ERROR: when the previous operation gererates error                
+  */
+CF_StatusTypedef HAL_CF_ReadStatus(PCCARD_HandleTypeDef *hpccard)
+{
+  uint8_t data = 0, status_CF = CF_BUSY;
+  
+  /* Check the PCCARD controller state */
+  if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+  {
+     return CF_ONGOING;
+  } 
+
+  /* Read status operation */
+  data =  *(__IO uint8_t *)(CF_IO_SPACE_PRIMARY_ADDR | CF_STATUS_CMD_ALTERNATE);
+
+  if((data & CF_TIMEOUT_ERROR) == CF_TIMEOUT_ERROR)
+  {
+    status_CF = CF_TIMEOUT_ERROR;
+  } 
+  else if((data & CF_READY) == CF_READY)
+  {
+    status_CF = CF_READY;
+  }
+  
+  return (CF_StatusTypedef) status_CF;
+}  
+ 
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* HAL_PCCARD_MODULE_ENABLED */  
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pccard.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,186 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_pccard.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of PCCARD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PCCARD_H
+#define __STM32F4xx_HAL_PCCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+  #include "stm32f4xx_ll_fsmc.h"
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+  #include "stm32f4xx_ll_fmc.h"
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PCCARD
+  * @{
+  */ 
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** 
+  * @brief  HAL SRAM State structures definition  
+  */ 
+typedef enum
+{
+  HAL_PCCARD_STATE_RESET     = 0x00,    /*!< PCCARD peripheral not yet initialized or disabled */
+  HAL_PCCARD_STATE_READY     = 0x01,    /*!< PCCARD peripheral ready                           */
+  HAL_PCCARD_STATE_BUSY      = 0x02,    /*!< PCCARD peripheral busy                            */   
+  HAL_PCCARD_STATE_ERROR     = 0x04     /*!< PCCARD peripheral error                           */
+}HAL_PCCARD_StateTypeDef;
+ 
+typedef enum
+{
+  CF_SUCCESS = 0,
+  CF_ONGOING,
+  CF_ERROR,
+  CF_TIMEOUT
+}CF_StatusTypedef;
+
+/** 
+  * @brief  FMC_PCCARD handle Structure definition  
+  */   
+typedef struct
+{
+  FMC_PCCARD_TypeDef           *Instance;              /*!< Register base address for PCCARD device          */
+  
+  FMC_PCCARD_InitTypeDef       Init;                   /*!< PCCARD device control configuration parameters   */
+
+  __IO HAL_PCCARD_StateTypeDef State;                  /*!< PCCARD device access state                       */
+   
+  HAL_LockTypeDef              Lock;                   /*!< PCCARD Lock                                      */ 
+ 
+}PCCARD_HandleTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCCARD_Exported_Constants
+  * @{
+  */
+  
+#define CF_DEVICE_ADDRESS             ((uint32_t)0x90000000)
+#define CF_ATTRIBUTE_SPACE_ADDRESS    ((uint32_t)0x98000000)   /* Attribute space size to @0x9BFF FFFF */
+#define CF_COMMON_SPACE_ADDRESS       CF_DEVICE_ADDRESS        /* Common space size to @0x93FF FFFF    */
+#define CF_IO_SPACE_ADDRESS           ((uint32_t)0x9C000000)   /* IO space size to @0x9FFF FFFF        */
+#define CF_IO_SPACE_PRIMARY_ADDR      ((uint32_t)0x9C0001F0)   /* IO space size to @0x9FFF FFFF        */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA                       ((uint8_t)0x00)    /* Data register */
+#define CF_SECTOR_COUNT               ((uint8_t)0x02)    /* Sector Count register */
+#define CF_SECTOR_NUMBER              ((uint8_t)0x03)    /* Sector Number register */
+#define CF_CYLINDER_LOW               ((uint8_t)0x04)    /* Cylinder low register */
+#define CF_CYLINDER_HIGH              ((uint8_t)0x05)    /* Cylinder high register */
+#define CF_CARD_HEAD                  ((uint8_t)0x06)    /* Card/Head register */
+#define CF_STATUS_CMD                 ((uint8_t)0x07)    /* Status(read)/Command(write) register */
+#define CF_STATUS_CMD_ALTERNATE       ((uint8_t)0x0E)    /* Alternate Status(read)/Command(write) register */
+#define CF_COMMON_DATA_AREA           ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD            ((uint8_t)0x20)
+#define CF_WRITE_SECTOR_CMD           ((uint8_t)0x30)
+#define CF_ERASE_SECTOR_CMD           ((uint8_t)0xC0)
+#define CF_IDENTIFY_CMD               ((uint8_t)0xEC)
+
+/* Compact Flash status */
+#define CF_TIMEOUT_ERROR              ((uint8_t)0x60)
+#define CF_BUSY                       ((uint8_t)0x80)
+#define CF_PROGR                      ((uint8_t)0x01)
+#define CF_READY                      ((uint8_t)0x40)
+
+#define CF_SECTOR_SIZE                ((uint32_t)255)    /* In half words */ 
+ 
+/**
+  * @}
+  */ 
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset PCCARD handle state
+  * @param  __HANDLE__: specifies the PCCARD handle.
+  * @retval None
+  */
+#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef  HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
+HAL_StatusTypeDef  HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);   
+void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
+
+/* IO operation functions  *****************************************************/
+HAL_StatusTypeDef  HAL_CF_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
+HAL_StatusTypeDef  HAL_CF_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,  uint8_t *pStatus);
+HAL_StatusTypeDef  HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef  HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef  HAL_CF_Reset(PCCARD_HandleTypeDef *hpccard);
+void               HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
+void        HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
+
+/* PCCARD State functions *******************************************************/
+HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
+CF_StatusTypedef HAL_CF_GetStatus(PCCARD_HandleTypeDef *hpccard);
+CF_StatusTypedef HAL_CF_ReadStatus(PCCARD_HandleTypeDef *hpccard);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_PCCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1209 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_pcd.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   PCD HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the USB Peripheral Controller:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The PCD HAL driver can be used as follows:
+
+     (#) Declare a PCD_HandleTypeDef handle structure, for example:
+         PCD_HandleTypeDef  hpcd;
+        
+     (#) Fill parameters of Init structure in HCD handle
+  
+     (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...) 
+
+     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
+         (##) Enable the PCD/USB Low Level interface clock using 
+              (+++) __OTGFS-OTG_CLK_ENABLE()/__OTGHS-OTG_CLK_ENABLE();
+              (+++) __OTGHSULPI_CLK_ENABLE(); (For High Speed Mode)
+           
+         (##) Initialize the related GPIO clocks
+         (##) Configure PCD pin-out
+         (##) Configure PCD NVIC interrupt
+    
+     (#)Associate the Upper USB device stack to the HAL PCD Driver:
+         (##) hpcd.pData = pdev;
+
+     (#)Enable HCD transmission and reception:
+         (##) HAL_PCD_Start();
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PCD 
+  * @brief PCD HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+#define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
+#define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PCD_Private_Functions
+  * @{
+  */
+
+/** @defgroup PCD_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+            ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the PCD according to the specified
+  *         parameters in the PCD_InitTypeDef and create the associated handle.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
+{ 
+  uint32_t i = 0;
+  
+  /* Check the PCD handle allocation */
+  if(hpcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+
+  hpcd->State = PCD_BUSY;
+  
+  /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+  HAL_PCD_MspInit(hpcd);
+
+  /* Disable the Interrupts */
+ __HAL_PCD_DISABLE(hpcd);
+ 
+ /*Init the Core (common init.) */
+ USB_CoreInit(hpcd->Instance, hpcd->Init);
+ 
+ /* Force Device Mode*/
+ USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE);
+ 
+ /* Init endpoints structures */
+ for (i = 0; i < 15 ; i++)
+ {
+   /* Init ep structure */
+   hpcd->IN_ep[i].is_in = 1;
+   hpcd->IN_ep[i].num = i;
+   hpcd->IN_ep[i].tx_fifo_num = i;
+   /* Control until ep is actvated */
+   hpcd->IN_ep[i].type = EP_TYPE_CTRL;
+   hpcd->IN_ep[i].maxpacket =  0;
+   hpcd->IN_ep[i].xfer_buff = 0;
+   hpcd->IN_ep[i].xfer_len = 0;
+ }
+ 
+ for (i = 0; i < 15 ; i++)
+ {
+   hpcd->OUT_ep[i].is_in = 0;
+   hpcd->OUT_ep[i].num = i;
+   hpcd->IN_ep[i].tx_fifo_num = i;
+   /* Control until ep is activated */
+   hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
+   hpcd->OUT_ep[i].maxpacket = 0;
+   hpcd->OUT_ep[i].xfer_buff = 0;
+   hpcd->OUT_ep[i].xfer_len = 0;
+   
+   hpcd->Instance->DIEPTXF[i] = 0;
+ }
+ 
+ /* Init Device */
+ USB_DevInit(hpcd->Instance, hpcd->Init);
+ 
+ hpcd->State= PCD_READY;
+ 
+ USB_DevDisconnect (hpcd->Instance);  
+ return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the PCD peripheral 
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Check the PCD handle allocation */
+  if(hpcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  hpcd->State = PCD_BUSY;
+  
+  /* Stop Device */
+  HAL_PCD_Stop(hpcd);
+    
+  /* DeInit the low level hardware */
+  HAL_PCD_MspDeInit(hpcd);
+  
+  hpcd->State = PCD_READY; 
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the PCD MSP.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_MspInit could be implenetd in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes PCD MSP.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_MspDeInit could be implenetd in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Group2 IO operation functions 
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the PCD data 
+    transfers.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Start The USB OTG Device.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
+{ 
+  __HAL_LOCK(hpcd); 
+  USB_DevConnect (hpcd->Instance);  
+  __HAL_PCD_ENABLE(hpcd);
+  __HAL_UNLOCK(hpcd); 
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop The USB OTG Device.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
+{ 
+  __HAL_LOCK(hpcd); 
+  __HAL_PCD_DISABLE(hpcd);
+  USB_StopDevice(hpcd->Instance);
+  USB_DevDisconnect (hpcd->Instance);
+  __HAL_UNLOCK(hpcd); 
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles PCD interrupt request.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t i = 0, ep_intr = 0, epint = 0, epnum = 0;
+  uint32_t fifoemptymsk = 0, temp = 0;
+  USB_OTG_EPTypeDef *ep;
+    
+  /* ensure that we are in device mode */
+  if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
+  {
+    /* avoid spurious interrupt */
+    if(__HAL_IS_INVALID_INTERRUPT(hpcd)) 
+    {
+      return;
+    }
+    
+    if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
+    {
+     /* incorrect mode, acknowledge the interrupt */
+      __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
+    }
+    
+    if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
+    {
+      epnum = 0;
+      
+      /* Read in the device interrupt bits */
+      ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
+      
+      while ( ep_intr )
+      {
+        if (ep_intr & 0x1)
+        {
+          epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
+          
+          if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
+            
+            if(hpcd->Init.dma_enable == 1)
+            {
+              hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); 
+              hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;            
+            }
+            
+            HAL_PCD_DataOutStageCallback(hpcd, epnum);
+            if(hpcd->Init.dma_enable == 1)
+            {
+              if((epnum == 0) && (hpcd->OUT_ep[epnum].xfer_len == 0))
+              {
+                 /* this is ZLP, so prepare EP0 for next setup */
+                USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
+              }              
+            }
+          }
+          
+          if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
+          {
+            /* Inform the upper layer that a setup packet is available */
+            HAL_PCD_SetupStageCallback(hpcd);
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
+          }
+          
+          if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
+          }
+        }
+        epnum++;
+        ep_intr >>= 1;
+      }
+    }
+    
+    if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
+    {
+      /* Read in the device interrupt bits */
+      ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
+      
+      epnum = 0;
+      
+      while ( ep_intr )
+      {
+        if (ep_intr & 0x1) /* In ITR */
+        {
+          epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);
+
+           if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
+          {
+            fifoemptymsk = 0x1 << epnum;
+            USBx_DEVICE->DIEPEMPMSK = ~fifoemptymsk;
+            
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
+            
+            if (hpcd->Init.dma_enable == 1)
+            {
+              hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; 
+            }
+                                      
+            HAL_PCD_DataInStageCallback(hpcd, epnum);
+
+            if (hpcd->Init.dma_enable == 1)
+            {
+              /* this is ZLP, so prepare EP0 for next setup */
+              if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0))
+              {
+                /* prepare to rx more setup packets */
+                USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
+              }
+            }           
+          }
+           if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
+          }
+          if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
+          }
+          if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
+          }
+          if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
+          }       
+          if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
+          {
+            PCD_WriteEmptyTxFifo(hpcd , epnum);
+          }
+        }
+        epnum++;
+        ep_intr >>= 1;
+      }
+    }
+    
+    /* Handle Resume Interrupt */
+    if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
+    {    
+     /* Clear the Remote Wake-up Signaling */
+      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+     
+     HAL_PCD_ResumeCallback(hpcd);
+
+     __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
+    }
+    
+    /* Handle Suspend Interrupt */
+    if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
+    {
+
+      if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+      {
+        
+        HAL_PCD_SuspendCallback(hpcd);
+      }
+      __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
+    }
+    
+
+
+    /* Handle Reset Interrupt */
+    if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
+    {
+      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 
+      USB_FlushTxFifo(hpcd->Instance ,  0 );
+      
+      for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
+      {
+        USBx_INEP(i)->DIEPINT = 0xFF;
+        USBx_OUTEP(i)->DOEPINT = 0xFF;
+      }
+      USBx_DEVICE->DAINT = 0xFFFFFFFF;
+      USBx_DEVICE->DAINTMSK |= 0x10001;
+      
+      if(hpcd->Init.use_dedicated_ep1)
+      {
+        USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); 
+        USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);  
+      }
+      else
+      {
+        USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
+        USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
+      }
+      
+      /* Set Default Address to 0 */
+      USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
+      
+      /* setup EP0 to receive SETUP packets */
+      USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
+        
+      __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
+    }
+    
+    /* Handle Enumeration done Interrupt */
+    if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
+    {
+      USB_ActivateSetup(hpcd->Instance);
+      hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
+      
+      if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)
+      {
+        hpcd->Init.speed            = USB_OTG_SPEED_HIGH;
+        hpcd->Init.ep0_mps          = USB_OTG_HS_MAX_PACKET_SIZE ;    
+        hpcd->Instance->GUSBCFG |= (USB_OTG_GUSBCFG_TRDT_0 | USB_OTG_GUSBCFG_TRDT_3);
+      }
+      else
+      {
+        hpcd->Init.speed            = USB_OTG_SPEED_FULL;
+        hpcd->Init.ep0_mps          = USB_OTG_FS_MAX_PACKET_SIZE ;  
+        hpcd->Instance->GUSBCFG |= (USB_OTG_GUSBCFG_TRDT_0 | USB_OTG_GUSBCFG_TRDT_2);
+      }
+      
+      HAL_PCD_ResetCallback(hpcd);
+      
+      __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
+    }
+    
+     
+    /* Handle RxQLevel Interrupt */
+    if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
+    {
+      USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+      temp = USBx->GRXSTSP;
+      ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
+      
+      if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)
+      {
+        if((temp & USB_OTG_GRXSTSP_BCNT) != 0)
+        {
+          USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4);
+          ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+          ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+        }
+      }
+      else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_SETUP_UPDT)
+      {
+        USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8);
+        ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+      }
+      USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+    }
+    
+    /* Handle SOF Interrupt */
+    if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
+    {
+      HAL_PCD_SOFCallback(hpcd);
+      __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
+    }
+    
+    /* Handle Incomplete ISO IN Interrupt */
+    if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
+    {
+      HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);
+      __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
+    } 
+    
+    /* Handle Incomplete ISO OUT Interrupt */
+    if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+    {
+      HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);
+      __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
+    } 
+    
+    /* Handle Connection event Interrupt */
+    if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
+    {
+      HAL_PCD_ConnectCallback(hpcd);
+      __HAL_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
+    } 
+    
+    /* Handle Disconnection event Interrupt */
+    if(__HAL_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
+    {
+      temp = hpcd->Instance->GOTGINT;
+      
+      if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
+      {
+        HAL_PCD_DisconnectCallback(hpcd);
+      }
+      hpcd->Instance->GOTGINT |= temp;
+    }
+  }
+}
+
+/**
+  * @brief  Data out stage callbacks
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @brief  Data IN stage callbacks
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+   */ 
+}
+/**
+  * @brief  Setup stage callback
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @brief  USB Start Of Frame callbacks
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @brief  USB Reset callbacks
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+   */ 
+}
+
+
+/**
+  * @brief  Suspend event callbacks
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @brief  Resume event callbacks
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @brief  Incomplete ISO OUT callbacks
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @brief  Incomplete ISO IN  callbacks
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @brief  Connection event callbacks
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @brief  Disconnection event callbacks
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup PCD_Group3 Peripheral Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the PCD data 
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Send an amount of data in blocking mode 
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd); 
+  USB_DevConnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd); 
+  return HAL_OK;
+}
+
+/**
+  * @brief  Send an amount of data in blocking mode 
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd); 
+  USB_DevDisconnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd); 
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the USB Device address 
+  * @param  hpcd: PCD handle
+  * @param  address: new device address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
+{
+  __HAL_LOCK(hpcd); 
+  USB_SetDevAddress(hpcd->Instance, address);
+  __HAL_UNLOCK(hpcd);   
+  return HAL_OK;
+}
+/**
+  * @brief  Open and configure an endpoint
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @param  ep_mps: endpoint max packert size
+  * @param  ep_type: endpoint type   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
+{
+  HAL_StatusTypeDef  ret = HAL_OK;
+  USB_OTG_EPTypeDef *ep;
+  
+  if ((ep_addr & 0x80) == 0x80)
+  {
+    ep = &hpcd->IN_ep[ep_addr & 0x7F];
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+  }
+  ep->num   = ep_addr & 0x7F;
+  
+  ep->is_in = (0x80 & ep_addr) != 0;
+  ep->maxpacket = ep_mps;
+  ep->type = ep_type;
+  if (ep->is_in)
+  {
+    /* Assign a Tx FIFO */
+    ep->tx_fifo_num = ep->num;
+  }
+  /* Set initial data PID. */
+  if (ep_type == EP_TYPE_BULK )
+  {
+    ep->data_pid_start = 0;
+  }
+  
+  __HAL_LOCK(hpcd); 
+  USB_ActivateEndpoint(hpcd->Instance , ep);
+  __HAL_UNLOCK(hpcd);   
+  return ret;
+}
+
+
+/**
+  * @brief  Deactivate an endpoint
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{  
+  USB_OTG_EPTypeDef *ep;
+  
+  if ((ep_addr & 0x80) == 0x80)
+  {
+    ep = &hpcd->IN_ep[ep_addr & 0x7F];
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+  }
+  ep->num   = ep_addr & 0x7F;
+  
+  ep->is_in = (0x80 & ep_addr) != 0;
+  
+  __HAL_LOCK(hpcd); 
+  USB_DeactivateEndpoint(hpcd->Instance , ep);
+  __HAL_UNLOCK(hpcd);   
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Receive an amount of data  
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @param  pBuf: pointer to the reception buffer   
+  * @param  len: amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+  
+  USB_OTG_EPTypeDef *ep;
+  
+  ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+  
+  /*setup and start the Xfer */
+  ep->xfer_buff = pBuf;  
+  ep->xfer_len = len;
+  ep->xfer_count = 0;
+  ep->is_in = 0;
+  ep->num = ep_addr & 0x7F;
+  
+  if (hpcd->Init.dma_enable == 1)
+  {
+    ep->dma_addr = (uint32_t)pBuf;  
+  }
+  
+  __HAL_LOCK(hpcd); 
+  
+  if ((ep_addr & 0x7F) == 0 )
+  {
+    USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+  }
+  else
+  {
+    USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+  }
+  __HAL_UNLOCK(hpcd); 
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get Received Data Size
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @retval Data Size
+  */
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
+}
+/**
+  * @brief  Send an amount of data  
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @param  pBuf: pointer to the transmission buffer   
+  * @param  len: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+  USB_OTG_EPTypeDef *ep;
+  
+  ep = &hpcd->IN_ep[ep_addr & 0x7F];
+  
+  /*setup and start the Xfer */
+  ep->xfer_buff = pBuf;  
+  ep->xfer_len = len;
+  ep->xfer_count = 0;
+  ep->is_in = 1;
+  ep->num = ep_addr & 0x7F;
+  
+  if (hpcd->Init.dma_enable == 1)
+  {
+    ep->dma_addr = (uint32_t)pBuf;  
+  }
+  
+  __HAL_LOCK(hpcd); 
+  
+  if ((ep_addr & 0x7F) == 0 )
+  {
+    USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+  }
+  else
+  {
+    USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+  }
+  
+  __HAL_UNLOCK(hpcd);
+     
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set a STALL condition over an endpoint
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  USB_OTG_EPTypeDef *ep;
+  
+  if ((0x80 & ep_addr) == 0x80)
+  {
+    ep = &hpcd->IN_ep[ep_addr & 0x7F];
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr];
+  }
+  
+  ep->is_stall = 1;
+  ep->num   = ep_addr & 0x7F;
+  ep->is_in = ((ep_addr & 0x80) == 0x80);
+  
+  
+  __HAL_LOCK(hpcd); 
+  USB_EPSetStall(hpcd->Instance , ep);
+  if((ep_addr & 0x7F) == 0)
+  {
+    USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
+  }
+  __HAL_UNLOCK(hpcd); 
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Clear a STALL condition over in an endpoint
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  USB_OTG_EPTypeDef *ep;
+  
+  if ((0x80 & ep_addr) == 0x80)
+  {
+    ep = &hpcd->IN_ep[ep_addr & 0x7F];
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr];
+  }
+  
+  ep->is_stall = 0;
+  ep->num   = ep_addr & 0x7F;
+  ep->is_in = ((ep_addr & 0x80) == 0x80);
+  
+  __HAL_LOCK(hpcd); 
+  USB_EPClearStall(hpcd->Instance , ep);
+  __HAL_UNLOCK(hpcd); 
+    
+  return HAL_OK;
+}
+
+/**
+  * @brief  Flush an endpoint
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  __HAL_LOCK(hpcd); 
+  
+  if ((ep_addr & 0x80) == 0x80)
+  {
+    USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
+  }
+  else
+  {
+    USB_FlushRxFifo(hpcd->Instance);
+  }
+  
+  __HAL_UNLOCK(hpcd); 
+    
+  return HAL_OK;
+}
+
+/**
+  * @brief  Update FIFO configuration
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
+{
+  uint8_t i = 0;
+  uint32_t Tx_Offset = 0;
+  
+  
+  /*  TXn min size = 16 words. (n  : Transmit FIFO index)
+  *   When a TxFIFO is not used, the Configuration should be as follows: 
+  *       case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)
+  *       --> Txm can use the space allocated for Txn.
+  *       case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)
+  *       --> Txn should be configured with the minimum space of 16 words
+  *  The FIFO is used optimally when used TxFIFOs are allocated in the top 
+  *       of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
+  *   When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
+  
+  Tx_Offset = hpcd->Instance->GRXFSIZ;
+  
+  if(fifo == 0)
+  {
+    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset;
+  }
+  else
+  {
+    Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
+    for (i = 0; i < (fifo - 1); i++)
+    {
+      Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
+    }
+    
+    /* Multiply Tx_Size by 2 to get higher performance */
+    hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset;
+    
+  }
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Update FIFO configuration
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
+{
+  
+  hpcd->Instance->GRXFSIZ = size;
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  HAL_PCD_ActiveRemoteWakeup : active remote wakeup signalling
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
+    
+  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+  {
+    /* active Remote wakeup signaling */
+    USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
+  }
+  return HAL_OK;  
+}
+
+/**
+  * @brief  HAL_PCD_DeActiveRemoteWakeup : de-active remote wakeup signalling
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
+  
+  /* active Remote wakeup signaling */
+   USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
+  return HAL_OK;  
+}
+/**
+  * @}
+  */
+  
+/** @defgroup PCD_Group4 Peripheral State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the PCD state
+  * @param  hpcd: PCD handle
+  * @retval HAL state
+  */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+{
+  return hpcd->State;
+}
+/**
+  * @}
+  */
+
+/**
+  * @brief  DCD_WriteEmptyTxFifo
+  *         check FIFO for the next packet to be loaded
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
+  USB_OTG_EPTypeDef *ep;
+  int32_t len = 0;
+  uint32_t len32b;
+  uint32_t fifoemptymsk = 0;
+
+  ep = &hpcd->IN_ep[epnum];
+  len = ep->xfer_len - ep->xfer_count;
+  
+  if (len > ep->maxpacket)
+  {
+    len = ep->maxpacket;
+  }
+  
+  
+  len32b = (len + 3) / 4;
+ 
+  while  ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
+          ep->xfer_count < ep->xfer_len &&
+            ep->xfer_len != 0)
+  {
+    /* Write the FIFO */
+    len = ep->xfer_len - ep->xfer_count;
+    
+    if (len > ep->maxpacket)
+    {
+      len = ep->maxpacket;
+    }
+    len32b = (len + 3) / 4;
+    
+    USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable); 
+    
+    ep->xfer_buff  += len;
+    ep->xfer_count += len;
+  }
+  
+  if(len <= 0)
+  {
+    fifoemptymsk = 0x1 << epnum;
+    USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
+    
+  }
+  
+  return HAL_OK;  
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PCD_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pcd.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,273 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_pcd.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of PCD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PCD_H
+#define __STM32F4xx_HAL_PCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_usb.h"
+   
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PCD
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+   /** 
+  * @brief  PCD State structures definition  
+  */  
+typedef enum 
+{
+  PCD_READY    = 0x00,
+  PCD_ERROR    = 0x01,
+  PCD_BUSY     = 0x02,
+  PCD_TIMEOUT  = 0x03
+} PCD_StateTypeDef;
+
+
+typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
+typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
+typedef USB_OTG_EPTypeDef      PCD_EPTypeDef ;                          
+
+/** 
+  * @brief  PCD Handle Structure definition  
+  */ 
+typedef struct
+{
+  PCD_TypeDef             *Instance;   /*!< Register base address              */ 
+  PCD_InitTypeDef         Init;       /*!< PCD required parameters            */
+  PCD_EPTypeDef           IN_ep[15];  /*!< IN endpoint parameters             */
+  PCD_EPTypeDef           OUT_ep[15]; /*!< OUT endpoint parameters            */ 
+  HAL_LockTypeDef         Lock;       /*!< PCD peripheral status              */
+  __IO PCD_StateTypeDef   State;      /*!< PCD communication state            */
+  uint32_t                Setup[12];  /*!< Setup packet buffer                */
+  void                    *pData;      /*!< Pointer to upper stack Handler     */    
+  
+} PCD_HandleTypeDef;
+  
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Constants
+  * @{
+  */
+
+/** @defgroup PCD_Speed
+  * @{
+  */
+#define PCD_SPEED_HIGH               0
+#define PCD_SPEED_HIGH_IN_FULL       1
+#define PCD_SPEED_FULL               2
+/**
+  * @}
+  */
+  
+  /** @defgroup PCD_PHY_Module
+  * @{
+  */
+#define PCD_PHY_ULPI                 1
+#define PCD_PHY_EMBEDDED             2
+/**
+  * @}
+  */
+  
+/** @defgroup PCD_Instance_definition 
+  * @{
+  */ 
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                        ((INSTANCE) == USB_OTG_HS))
+#elif defined(STM32F401xC) || defined(STM32F401xE)
+ #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup PCD_Interrupt_Clock
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_PCD_ENABLE(__HANDLE__)                   USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__)                  USB_DisableGlobalInt ((__HANDLE__)->Instance)
+   
+#define __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) |= (__INTERRUPT__))
+#define __HAL_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
+
+
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
+                                                       ~(USB_OTG_PCGCCTL_STOPCLK)
+
+
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
+                                                      
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
+                                                         
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE      ((uint32_t)0x08) 
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE     ((uint32_t)0x0C) 
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE        ((uint32_t)0x10) 
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE      ((uint32_t)0x08) 
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE     ((uint32_t)0x0C) 
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE        ((uint32_t)0x10) 
+
+
+#define USB_HS_EXTI_LINE_WAKEUP              ((uint32_t)0x00100000)  /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
+#define USB_FS_EXTI_LINE_WAKEUP              ((uint32_t)0x00040000)  /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
+
+
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT()    EXTI->IMR |= (USB_HS_EXTI_LINE_WAKEUP)
+#define __HAL_USB_HS_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_HS_EXTI_LINE_WAKEUP)
+#define __HAL_USB_HS_EXTI_GET_FLAG()     EXTI->PR & (USB_HS_EXTI_LINE_WAKEUP)
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG()   EXTI->PR = (USB_HS_EXTI_LINE_WAKEUP)
+
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(USB_HS_EXTI_LINE_WAKEUP);\
+                                                    EXTI->RTSR |= USB_HS_EXTI_LINE_WAKEUP
+
+                                                      
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER()  EXTI->FTSR |= (USB_HS_EXTI_LINE_WAKEUP);\
+                                                      EXTI->RTSR &= ~(USB_HS_EXTI_LINE_WAKEUP)
+
+
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER()   EXTI->RTSR &= ~(USB_HS_EXTI_LINE_WAKEUP);\
+                                                        EXTI->FTSR &= ~(USB_HS_EXTI_LINE_WAKEUP;)\
+                                                        EXTI->RTSR |= USB_HS_EXTI_LINE_WAKEUP;\
+                                                        EXTI->FTSR |= USB_HS_EXTI_LINE_WAKEUP
+
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT()    EXTI->IMR |= USB_FS_EXTI_LINE_WAKEUP
+#define __HAL_USB_FS_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_FS_EXTI_LINE_WAKEUP)
+#define __HAL_USB_FS_EXTI_GET_FLAG()     EXTI->PR & (USB_FS_EXTI_LINE_WAKEUP)
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG()   EXTI->PR = USB_FS_EXTI_LINE_WAKEUP
+
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\
+                                                    EXTI->RTSR |= USB_FS_EXTI_LINE_WAKEUP
+
+                                                      
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER()  EXTI->FTSR |= (USB_FS_EXTI_LINE_WAKEUP);\
+                                                      EXTI->RTSR &= ~(USB_FS_EXTI_LINE_WAKEUP)
+
+
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER()  EXTI->RTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\
+                                                       EXTI->FTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\
+                                                       EXTI->RTSR |= USB_FS_EXTI_LINE_WAKEUP;\
+                                                       EXTI->FTSR |= USB_FS_EXTI_LINE_WAKEUP  
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+
+/* I/O operation functions  *****************************************************/
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+
+
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+uint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
+HAL_StatusTypeDef HAL_PCD_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
+HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
+/* Peripheral State functions  **************************************************/
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_PCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,520 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_pwr.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   PWR HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Power Controller (PWR) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions 
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWR 
+  * @brief PWR HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Private_Functions
+  * @{
+  */
+
+/** @defgroup PWR_Group1 Initialization and de-initialization functions 
+  *  @brief    Initialization and de-initialization functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+      After reset, the backup domain (RTC registers, RTC backup data 
+      registers and backup SRAM) is protected against possible unwanted 
+      write accesses. 
+      To enable access to the RTC Domain and RTC registers, proceed as follows:
+        (+) Enable the Power Controller (PWR) APB1 interface clock using the
+            __PWR_CLK_ENABLE() macro.
+        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
+  * @param None
+  * @retval None
+  */
+void HAL_PWR_DeInit(void)
+{
+  __PWR_FORCE_RESET();
+  __PWR_RELEASE_RESET();
+}
+
+/**
+  * @brief Enables access to the backup domain (RTC registers, RTC 
+  *         backup data registers and backup SRAM).
+  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 
+  *         Backup Domain Access should be kept enabled.
+  * @param None
+  * @retval None
+  */
+void HAL_PWR_EnableBkUpAccess(void)
+{
+  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief Disables access to the backup domain (RTC registers, RTC 
+  *         backup data registers and backup SRAM).
+  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 
+  *         Backup Domain Access should be kept enabled.
+  * @param None
+  * @retval None
+  */
+void HAL_PWR_DisableBkUpAccess(void)
+{
+  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group2 Peripheral Control functions 
+  *  @brief Low Power modes configuration functions 
+  *
+@verbatim
+
+ ===============================================================================
+                 ##### Peripheral Control functions #####
+ ===============================================================================
+     
+    *** PVD configuration ***
+    =========================
+    [..]
+      (+) The PVD is used to monitor the VDD power supply by comparing it to a 
+          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower 
+          than the PVD threshold. This event is internally connected to the EXTI 
+          line16 and can generate an interrupt if enabled. This is done through
+          __HAL_PVD_EXTI_ENABLE_IT() macro.
+      (+) The PVD is stopped in Standby mode.
+
+    *** WakeUp pin configuration ***
+    ================================
+    [..]
+      (+) WakeUp pin is used to wake up the system from Standby mode. This pin is 
+          forced in input pull-down configuration and is active on rising edges.
+      (+) There is only one WakeUp pin: WakeUp Pin 1 on PA.00.
+
+    *** Low Power modes configuration ***
+    =====================================
+    [..]
+      The devices feature 3 low-power modes:
+      (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
+      (+) Stop mode: all clocks are stopped, regulator running, regulator 
+          in low power mode
+      (+) Standby mode: 1.2V domain powered off.
+   
+   *** Sleep mode ***
+   ==================
+    [..]
+      (+) Entry:
+        The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
+              functions with
+          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+      
+      -@@- The Regulator parameter is not used for the STM32F4 family 
+              and is kept as parameter just to maintain compatibility with the 
+              lower power families (STM32L).
+      (+) Exit:
+        Any peripheral interrupt acknowledged by the nested vectored interrupt 
+              controller (NVIC) can wake up the device from Sleep mode.
+
+   *** Stop mode ***
+   =================
+    [..]
+      In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
+      and the HSE RC oscillators are disabled. Internal SRAM and register contents 
+      are preserved.
+      The voltage regulator can be configured either in normal or low-power mode.
+      To minimize the consumption In Stop mode, FLASH can be powered off before 
+      entering the Stop mode using the HAL_PWR_EnableFlashPowerDown() function.
+      It can be switched on again by software after exiting the Stop mode using
+      the HAL_PWR_DisableFlashPowerDown() function. 
+
+      (+) Entry:
+         The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) 
+             function with:
+          (++) Main regulator ON.
+          (++) Low Power regulator ON.
+      (+) Exit:
+        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+
+   *** Standby mode ***
+   ====================
+    [..]
+    (+)
+      The Standby mode allows to achieve the lowest power consumption. It is based 
+      on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. 
+      The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and 
+      the HSE oscillator are also switched off. SRAM and register contents are lost 
+      except for the RTC registers, RTC backup registers, backup SRAM and Standby 
+      circuitry.
+   
+      The voltage regulator is OFF.
+      
+      (++) Entry:
+        (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
+      (++) Exit:
+        (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
+             tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
+
+   *** Auto-wakeup (AWU) from low-power mode ***
+   =============================================
+    [..]
+    
+     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 
+      Wakeup event, a tamper event or a time-stamp event, without depending on 
+      an external interrupt (Auto-wakeup mode).
+
+      (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
+       
+        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to 
+              configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
+
+        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 
+             is necessary to configure the RTC to detect the tamper or time stamp event using the
+                HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
+                  
+        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
+              configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+  * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
+  *        information for the PVD.
+  * @note Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage threshold corresponding to each 
+  *         detection level.
+  * @retval None
+  */
+void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
+  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
+  
+  tmpreg = PWR->CR;
+  
+  /* Clear PLS[7:5] bits */
+  tmpreg &= ~ (uint32_t)PWR_CR_PLS;
+  
+  /* Set PLS[7:5] bits according to PVDLevel value */
+  tmpreg |= sConfigPVD->PVDLevel;
+  
+  /* Store the new value */
+  PWR->CR = tmpreg;
+  
+  /* Configure the EXTI 16 interrupt */
+  if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\
+     (sConfigPVD->Mode == PWR_MODE_IT_FALLING) ||\
+     (sConfigPVD->Mode == PWR_MODE_IT_RISING)) 
+  {
+    __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD);
+  }
+  /* Clear the edge trigger  for the EXTI Line 16 (PVD) */
+  EXTI->RTSR &= ~EXTI_RTSR_TR16;
+  EXTI->FTSR &= ~EXTI_FTSR_TR16;  
+  /* Configure the rising edge */
+  if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\
+     (sConfigPVD->Mode == PWR_MODE_IT_RISING))
+  {
+    EXTI->RTSR |= PWR_EXTI_LINE_PVD;
+  }
+  /* Configure the falling edge */
+  if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\
+     (sConfigPVD->Mode == PWR_MODE_IT_FALLING))
+  {
+    EXTI->FTSR |= PWR_EXTI_LINE_PVD;
+  }
+}
+
+/**
+  * @brief Enables the Power Voltage Detector(PVD).
+  * @param None
+  * @retval None
+  */
+void HAL_PWR_EnablePVD(void)
+{
+  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief Disables the Power Voltage Detector(PVD).
+  * @param None
+  * @retval None
+  */
+void HAL_PWR_DisablePVD(void)
+{
+  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
+}
+
+/**
+  * @brief Enables the WakeUp PINx functionality.
+  * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
+  *         This parameter can be one of the following values:
+  *           @arg PWR_WAKEUP_PIN1
+  * @retval None
+  */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
+{
+  /* Check the parameter */
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+  *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief Disables the WakeUp PINx functionality.
+  * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
+  *         This parameter can be one of the following values:
+  *           @arg PWR_WAKEUP_PIN1
+  * @retval None
+  */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+{
+  /* Check the parameter */
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));  
+  *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)DISABLE;
+}
+  
+/**
+  * @brief Enters Sleep mode.
+  *   
+  * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
+  * 
+  * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
+  *       systick interrupt when used as time base for Timeout 
+  *                
+  * @param Regulator: Specifies the regulator state in SLEEP mode.
+  *            This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
+  *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
+  * @note This parameter is not used for the STM32F4 family and is kept as parameter
+  *       just to maintain compatibility with the lower power families.
+  * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+  *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+  * @retval None
+  */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(Regulator));
+  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+
+  /* Select SLEEP mode entry -------------------------------------------------*/
+  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+}
+
+/**
+  * @brief Enters Stop mode. 
+  * @note In Stop mode, all I/O pins keep the same state as in Run mode.
+  * @note When exiting Stop mode by issuing an interrupt or a wakeup event, 
+  *         the HSI RC oscillator is selected as system clock.
+  * @note When the voltage regulator operates in low power mode, an additional 
+  *         startup delay is incurred when waking up from Stop mode. 
+  *         By keeping the internal regulator ON during Stop mode, the consumption 
+  *         is higher although the startup time is reduced.    
+  * @param Regulator: Specifies the regulator state in Stop mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
+  *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
+  * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
+  *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
+  * @retval None
+  */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+  
+  /* Select the regulator state in Stop mode ---------------------------------*/
+  tmpreg = PWR->CR;
+  /* Clear PDDS and LPDS bits */
+  tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
+  
+  /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */
+  tmpreg |= Regulator;
+  
+  /* Store the new value */
+  PWR->CR = tmpreg;
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+  
+  /* Select Stop mode entry --------------------------------------------------*/
+  if(STOPEntry == PWR_STOPENTRY_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE();
+  }
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);  
+}
+
+/**
+  * @brief Enters Standby mode.
+  * @note In Standby mode, all I/O pins are high impedance except for:
+  *          - Reset pad (still available) 
+  *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC 
+  *            Alarm out, or RTC clock calibration out.
+  *          - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.  
+  *          - WKUP pin 1 (PA0) if enabled.       
+  * @param None
+  * @retval None
+  */
+void HAL_PWR_EnterSTANDBYMode(void)
+{
+  /* Clear Wakeup flag */
+  PWR->CR |= PWR_CR_CWUF;
+  
+  /* Select Standby mode */
+  PWR->CR |= PWR_CR_PDDS;
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+  
+  /* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/**
+  * @brief This function handles the PWR PVD interrupt request.
+  * @note This API should be called under the PVD_IRQHandler().
+  * @param None
+  * @retval None
+  */
+void HAL_PWR_PVD_IRQHandler(void)
+{
+  /* Check PWR exti flag */
+  if(__HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) != RESET)
+  {
+    /* PWR PVD interrupt user callback */
+    HAL_PWR_PVDCallback();
+    
+    /* Clear PWR Exti pending bit */
+    __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD);
+  }
+}
+
+/**
+  * @brief  PWR PVD interrupt callback
+  * @param  None 
+  * @retval None
+  */
+__weak void HAL_PWR_PVDCallback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PWR_PVDCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,334 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_pwr.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of PWR HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PWR_H
+#define __STM32F4xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/**
+  * @brief  PWR PVD configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
+                            This parameter can be a value of @ref PWR_PVD_detection_level */
+
+  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref PWR_PVD_Mode */
+}PWR_PVDTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* ------------- PWR registers bit address in the alias region ---------------*/
+#define PWR_OFFSET      (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+/* Alias word address of DBP bit */
+#define CR_OFFSET       (PWR_OFFSET + 0x00)
+#define DBP_BitNumber   0x08
+#define CR_DBP_BB       (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber  0x04
+#define CR_PVDE_BB      (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* Alias word address of FPDS bit */
+#define FPDS_BitNumber  0x09
+#define CR_FPDS_BB      (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
+
+/* Alias word address of PMODE bit */
+#define PMODE_BitNumber 0x0E
+#define CR_PMODE_BB     (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+/* Alias word address of EWUP bit */
+#define CSR_OFFSET      (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber  0x08
+#define CSR_EWUP_BB     (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+/* Alias word address of BRE bit */
+#define BRE_BitNumber   0x09
+#define CSR_BRE_BB      (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
+   
+/** @defgroup PWR_Exported_Constants
+  * @{
+  */
+ 
+/** @defgroup PWR_WakeUp_Pins
+  * @{
+  */
+
+#define PWR_WAKEUP_PIN1                 PWR_CSR_EWUP
+#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVD_detection_level 
+  * @{
+  */ 
+#define PWR_PVDLEVEL_0                  PWR_CR_PLS_LEV0
+#define PWR_PVDLEVEL_1                  PWR_CR_PLS_LEV1
+#define PWR_PVDLEVEL_2                  PWR_CR_PLS_LEV2
+#define PWR_PVDLEVEL_3                  PWR_CR_PLS_LEV3
+#define PWR_PVDLEVEL_4                  PWR_CR_PLS_LEV4
+#define PWR_PVDLEVEL_5                  PWR_CR_PLS_LEV5
+#define PWR_PVDLEVEL_6                  PWR_CR_PLS_LEV6
+#define PWR_PVDLEVEL_7                  PWR_CR_PLS_LEV7
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+/**
+  * @}
+  */   
+ 
+/** @defgroup PWR_PVD_Mode 
+  * @{
+  */
+#define  PWR_MODE_EVT                  ((uint32_t)0x00000000)   /*!< No Interrupt */
+#define  PWR_MODE_IT_RISING            ((uint32_t)0x00000001)   /*!< External Interrupt Mode with Rising edge trigger detection */
+#define  PWR_MODE_IT_FALLING           ((uint32_t)0x00000002)   /*!< External Interrupt Mode with Falling edge trigger detection */
+#define  PWR_MODE_IT_RISING_FALLING    ((uint32_t)0x00000003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_MODE_EVT) || ((MODE) == PWR_MODE_IT_RISING)|| \
+                               ((MODE) == PWR_MODE_IT_FALLING) || ((MODE) == PWR_MODE_IT_RISING_FALLING))
+/**
+  * @}
+  */ 
+
+/** @defgroup PWR_Regulator_state_in_STOP_mode 
+  * @{
+  */
+#define PWR_MAINREGULATOR_ON                        ((uint32_t)0x00000000)
+#define PWR_LOWPOWERREGULATOR_ON                    PWR_CR_LPDS
+
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+/**
+  * @}
+  */
+    
+/** @defgroup PWR_SLEEP_mode_entry 
+  * @{
+  */
+#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01)
+#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02)
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry 
+  * @{
+  */
+#define PWR_STOPENTRY_WFI               ((uint8_t)0x01)
+#define PWR_STOPENTRY_WFE               ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Regulator_Voltage_Scale 
+  * @{
+  */
+#define PWR_REGULATOR_VOLTAGE_SCALE1    ((uint32_t)0x0000C000)
+#define PWR_REGULATOR_VOLTAGE_SCALE2    ((uint32_t)0x00008000)
+#define PWR_REGULATOR_VOLTAGE_SCALE3    ((uint32_t)0x00004000)
+#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag 
+  * @{
+  */
+#define PWR_FLAG_WU                     PWR_CSR_WUF
+#define PWR_FLAG_SB                     PWR_CSR_SBF
+#define PWR_FLAG_PVDO                   PWR_CSR_PVDO
+#define PWR_FLAG_BRR                    PWR_CSR_BRR
+#define PWR_FLAG_VOSRDY                 PWR_CSR_VOSRDY
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief  macros configure the main internal regulator output voltage.
+  * @param  __REGULATOR__: specifies the regulator output voltage to achieve
+  *         a tradeoff between performance and power consumption when the device does
+  *         not operate at the maximum frequency (refer to the datasheets for more details).
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
+  * @retval None
+  */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
+
+/** @brief  Check PWR flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *           This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 
+  *                  was received from the WKUP pin or from the RTC alarm (Alarm A 
+  *                  or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
+  *                  An additional wakeup event is detected if the WKUP pin is enabled 
+  *                  (by setting the EWUP bit) when the WKUP pin level is already high.  
+  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+  *                  resumed from StandBy mode.    
+  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 
+  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode 
+  *                  For this reason, this bit is equal to 0 after Standby or reset
+  *                  until the PVDE bit is set.
+  *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset 
+  *                  when the device wakes up from Standby mode or by a system reset 
+  *                  or power reset.  
+  *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage 
+  *                 scaling output selection is ready.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the PWR's pending flags.
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WU: Wake Up flag
+  *            @arg PWR_FLAG_SB: StandBy flag
+  */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |=  (__FLAG__) << 2)
+
+#define PWR_EXTI_LINE_PVD  ((uint32_t)0x00010000)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+/**
+  * @brief Enable the PVD Exti Line.
+  * @param  __EXTILINE__: specifies the PVD Exti sources to be enabled.
+  * This parameter can be:
+  *   @arg PWR_EXTI_LINE_PVD     
+  * @retval None.
+  */
+#define __HAL_PVD_EXTI_ENABLE_IT(__EXTILINE__)   (EXTI->IMR |= (__EXTILINE__))
+
+/**
+  * @brief Disable the PVD EXTI Line.
+  * @param  __EXTILINE__: specifies the PVD EXTI sources to be disabled.
+  * This parameter can be:
+  *  @arg PWR_EXTI_LINE_PVD    
+  * @retval None.
+  */
+#define __HAL_PVD_EXTI_DISABLE_IT(__EXTILINE__)  (EXTI->IMR &= ~(__EXTILINE__))
+
+/**
+  * @brief checks whether the specified PVD Exti interrupt flag is set or not.
+  * @param  __EXTILINE__: specifies the PVD Exti sources to be cleared.
+  * This parameter can be:
+  *   @arg PWR_EXTI_LINE_PVD  
+  * @retval EXTI PVD Line Status.
+  */
+#define __HAL_PVD_EXTI_GET_FLAG(__EXTILINE__)  (EXTI->PR & (__EXTILINE__))
+
+/**
+  * @brief Clear the PVD Exti flag.
+  * @param  __EXTILINE__: specifies the PVD Exti sources to be cleared.
+  * This parameter can be:
+  *   @arg PWR_EXTI_LINE_PVD  
+  * @retval None.
+  */
+#define __HAL_PVD_EXTI_CLEAR_FLAG(__EXTILINE__)  (EXTI->PR = (__EXTILINE__))
+
+
+/* Include PWR HAL Extension module */
+#include "stm32f4xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions *******************************/
+void        HAL_PWR_DeInit(void);
+void        HAL_PWR_EnableBkUpAccess(void);
+void        HAL_PWR_DisableBkUpAccess(void);
+
+/* Peripheral Control functions  ************************************************/
+void        HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD);
+void        HAL_PWR_EnablePVD(void);
+void        HAL_PWR_DisablePVD(void);
+void        HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
+void        HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+void        HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void        HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void        HAL_PWR_EnterSTANDBYMode(void);
+
+void        HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,330 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_pwr_ex.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Extended PWR HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of PWR extension peripheral:           
+  *           + Peripheral Extended features functions
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWREx 
+  * @brief PWR HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define PWR_OVERDRIVE_TIMEOUT_VALUE  1000
+#define PWR_BKPREG_TIMEOUT_VALUE     1000
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWREx_Private_Functions
+  * @{
+  */
+
+/** @defgroup PWREx_Group1 Peripheral Extended features functions 
+  *  @brief Peripheral Extended features functions 
+  *
+@verbatim   
+
+ ===============================================================================
+                 ##### Peripheral extended features functions #####
+ ===============================================================================
+
+    *** Main and Backup Regulators configuration ***
+    ================================================
+    [..] 
+      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from 
+          the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is 
+          retained even in Standby or VBAT mode when the low power backup regulator
+          is enabled. It can be considered as an internal EEPROM when VBAT is 
+          always present. You can use the HAL_PWR_EnableBkUpReg() function to 
+          enable the low power backup regulator. 
+
+      (+) When the backup domain is supplied by VDD (analog switch connected to VDD) 
+          the backup SRAM is powered from VDD which replaces the VBAT power supply to 
+          save battery life.
+
+      (+) The backup SRAM is not mass erased by a tamper event. It is read 
+          protected to prevent confidential data, such as cryptographic private 
+          key, from being accessed. The backup SRAM can be erased only through 
+          the Flash interface when a protection level change from level 1 to 
+          level 0 is requested. 
+      -@- Refer to the description of Read protection (RDP) in the Flash 
+          programming manual.
+
+      (+) The main internal regulator can be configured to have a tradeoff between 
+          performance and power consumption when the device does not operate at 
+          the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() 
+          macro which configure VOS bit in PWR_CR register
+          
+        Refer to the product datasheets for more details.
+
+    *** FLASH Power Down configuration ****
+    =======================================
+    [..] 
+      (+) By setting the FPDS bit in the PWR_CR register by using the 
+          HAL_PWR_EnableFlashPowerDown() function, the Flash memory also enters power 
+          down mode when the device enters Stop mode. When the Flash memory 
+          is in power down mode, an additional startup delay is incurred when 
+          waking up from Stop mode.
+          
+           (+) For STM32F42xxx/43xxx Devices, the scale can be modified only when the PLL 
+           is OFF and the HSI or HSE clock source is selected as system clock. 
+           The new value programmed is active only when the PLL is ON.
+           When the PLL is OFF, the voltage scale 3 is automatically selected. 
+        Refer to the datasheets for more details.
+
+    *** Over-Drive and Under-Drive configuration ****
+    =================================================
+    [..]         
+       (+) For STM32F42xxx/43xxx Devices, in Run mode: the main regulator has
+           2 operating modes available:
+        (++) Normal mode: The CPU and core logic operate at maximum frequency at a given 
+             voltage scaling (scale 1, scale 2 or scale 3)
+        (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a 
+            higher frequency than the normal mode for a given voltage scaling (scale 1,  
+            scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
+            disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow 
+            the sequence described in Reference manual.
+             
+       (+) For STM32F42xxx/43xxx Devices, in Stop mode: the main regulator or low power regulator 
+           supplies a low power voltage to the 1.2V domain, thus preserving the content of registers 
+           and internal SRAM. 2 operating modes are available:
+         (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only 
+              available when the main regulator or the low power regulator is used in Scale 3 or 
+              low voltage mode.
+         (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
+              available when the main regulator or the low power regulator is in low voltage mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Enables the Backup Regulator.
+  * @param None
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
+{
+  uint32_t timeout = 0;   
+
+  *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;
+
+  /* Get timeout */
+  timeout = HAL_GetTick() + PWR_BKPREG_TIMEOUT_VALUE;
+  /* Wait till Backup regulator ready flag is set */  
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
+  {
+    if(HAL_GetTick() >= timeout)
+    {
+      return HAL_TIMEOUT;
+    } 
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief Disables the Backup Regulator.
+  * @param None
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
+{
+  uint32_t timeout = 0; 
+
+  *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;
+
+  /* Get timeout */
+  timeout = HAL_GetTick() + PWR_BKPREG_TIMEOUT_VALUE;
+  /* Wait till Backup regulator ready flag is set */  
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
+  {
+    if(HAL_GetTick() >= timeout)
+    {
+      return HAL_TIMEOUT;
+    } 
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief Enables the Flash Power Down in Stop mode.
+  * @param None
+  * @retval None
+  */
+void HAL_PWREx_EnableFlashPowerDown(void)
+{
+  *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief Disables the Flash Power Down in Stop mode.
+  * @param None
+  * @retval None
+  */
+void HAL_PWREx_DisableFlashPowerDown(void)
+{
+  *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;
+}
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/**
+  * @brief  Activates the Over-Drive mode.
+  * @note   These macros can be used only for STM32F42xx/STM32F43xx devices.
+  *         This mode allows the CPU and the core logic to operate at a higher frequency
+  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).   
+  * @note   It is recommended to enter or exit Over-drive mode when the application is not running 
+  *         critical tasks and when the system clock source is either HSI or HSE. 
+  *         During the Over-drive switch activation, no peripheral clocks should be enabled.   
+  *         The peripheral clocks must be enabled once the Over-drive mode is activated.   
+  * @param  None
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_ActivateOverDrive(void)
+{
+  uint32_t timeout = 0;
+  
+  __PWR_CLK_ENABLE();
+  
+  /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
+  __HAL_PWR_OVERDRIVE_ENABLE();
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + PWR_OVERDRIVE_TIMEOUT_VALUE;
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
+  {
+    if(HAL_GetTick() >= timeout)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  
+  /* Enable the Over-drive switch */
+  __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + PWR_OVERDRIVE_TIMEOUT_VALUE;
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
+  {
+    if(HAL_GetTick() >= timeout)
+    {
+      return HAL_TIMEOUT;
+    }
+  } 
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivates the Over-Drive mode.
+  * @note   These macros can be used only for STM32F42xx/STM32F43xx devices.
+  *         This mode allows the CPU and the core logic to operate at a higher frequency
+  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).    
+  * @note   It is recommended to enter or exit Over-drive mode when the application is not running 
+  *         critical tasks and when the system clock source is either HSI or HSE. 
+  *         During the Over-drive switch activation, no peripheral clocks should be enabled.   
+  *         The peripheral clocks must be enabled once the Over-drive mode is activated.
+  * @param  None
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_DeactivateOverDrive(void)
+{
+  uint32_t timeout = 0;
+  
+  __PWR_CLK_ENABLE();
+    
+  /* Disable the Over-drive switch */
+  __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
+  
+  /* Get timeout */
+  timeout = HAL_GetTick() + PWR_OVERDRIVE_TIMEOUT_VALUE;
+ 
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
+  {
+    if(HAL_GetTick() >= timeout)
+    {
+      return HAL_TIMEOUT;
+    }
+  } 
+  
+  /* Disable the Over-drive */
+  __HAL_PWR_OVERDRIVE_DISABLE();
+
+  /* Get timeout */
+  timeout = HAL_GetTick() + PWR_OVERDRIVE_TIMEOUT_VALUE;  
+
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
+  {
+    if(HAL_GetTick() >= timeout)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  
+  return HAL_OK;
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,162 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_pwr_ex.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of PWR HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PWR_EX_H
+#define __STM32F4xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWREx
+  * @{
+  */ 
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Exported types ------------------------------------------------------------*/ 
+/* Exported constants --------------------------------------------------------*/
+/* ------------- PWR registers bit address in the alias region ---------------*/
+/* --- CR Register ---*/
+
+/* Alias word address of ODEN bit   */
+#define ODEN_BitNumber           0x10
+#define CR_ODEN_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4))
+
+/* Alias word address of ODSWEN bit */
+#define ODSWEN_BitNumber         0x11
+#define CR_ODSWEN_BB             (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4))
+    
+
+/** @defgroup PWREx_Over_Under_Drive_Flag 
+  * @{
+  */
+#define PWR_FLAG_ODRDY                  PWR_CSR_ODRDY
+#define PWR_FLAG_ODSWRDY                PWR_CSR_ODSWRDY
+#define PWR_FLAG_UDRDY                  PWR_CSR_UDSWRDY
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+  
+/** @brief Macros to enable or disable the Over drive mode.
+  * @note  These macros can be used only for STM32F42xx/STM3243xx devices.
+  */
+#define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE)
+#define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE)
+
+/** @brief Macros to enable or disable the Over drive switching.
+  * @note  These macros can be used only for STM32F42xx/STM3243xx devices. 
+  */
+#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE)
+#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE)
+
+/** @brief Macros to enable or disable the Under drive mode.
+  * @note  This mode is enabled only with STOP low power mode.
+  *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This 
+  *        mode is only available when the main regulator or the low power regulator 
+  *        is in low voltage mode.      
+  * @note  If the Under-drive mode was enabled, it is automatically disabled after 
+  *        exiting Stop mode. 
+  *        When the voltage regulator operates in Under-drive mode, an additional  
+  *        startup delay is induced when waking up from Stop mode.
+  */
+#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN)
+#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN))
+
+/** @brief  Check PWR flag is set or not.
+  * @note   These macros can be used only for STM32F42xx/STM3243xx devices.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
+  *                                 is ready 
+  *            @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
+  *                                   switching is ready  
+  *            @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
+  *                                 is enabled in Stop mode
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the Under-Drive Ready flag.
+  * @note  These macros can be used only for STM32F42xx/STM3243xx devices.
+  */
+#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/* Exported functions --------------------------------------------------------*/
+void              HAL_PWREx_EnableFlashPowerDown(void);
+void              HAL_PWREx_DisableFlashPowerDown(void); 
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); 
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+HAL_StatusTypeDef HAL_PWREx_ActivateOverDrive(void);
+HAL_StatusTypeDef HAL_PWREx_DeactivateOverDrive(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_PWR_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1187 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_rcc.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   RCC HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Reset and Clock Control (RCC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *       
+  @verbatim                
+  ==============================================================================
+                      ##### RCC specific features #####
+  ==============================================================================
+    [..]  
+      After reset the device is running from Internal High Speed oscillator 
+      (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache 
+      and I-Cache are disabled, and all peripherals are off except internal
+      SRAM, Flash and JTAG.
+      (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
+          all peripherals mapped on these busses are running at HSI speed.
+      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+      (+) All GPIOs are in input floating state, except the JTAG pins which
+          are assigned to be used for debug purpose.
+    
+    [..]          
+      Once the device started from reset, the user application has to:        
+      (+) Configure the clock source to be used to drive the System clock
+          (if the application needs higher frequency/performance)
+      (+) Configure the System clock frequency and Flash settings  
+      (+) Configure the AHB and APB busses prescalers
+      (+) Enable the clock for the peripheral(s) to be used
+      (+) Configure the clock source(s) for peripherals which clocks are not
+          derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCC 
+  * @brief RCC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
+#define LSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
+#define PLL_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
+#define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000) /* 5 s    */
+
+/* Private macro -------------------------------------------------------------*/
+#define __MCO1_CLK_ENABLE()   __GPIOA_CLK_ENABLE()
+#define MCO1_GPIO_PORT        GPIOA
+#define MCO1_PIN              GPIO_PIN_8 
+
+#define __MCO2_CLK_ENABLE()   __GPIOC_CLK_ENABLE()
+#define MCO2_GPIO_PORT         GPIOC
+#define MCO2_PIN               GPIO_PIN_9
+
+/* Private variables ---------------------------------------------------------*/
+const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RCC_Private_Functions
+  * @{
+  */
+
+/** @defgroup RCC_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+           ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to configure the internal/external oscillators
+      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 
+       and APB2).
+
+    [..] Internal/external clock and PLL configuration
+         (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
+             the PLL as System clock source.
+
+         (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
+             clock source.
+
+         (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
+             through the PLL as System clock source. Can be used also as RTC clock source.
+
+         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.   
+
+         (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
+           (++) The first output is used to generate the high speed system clock (up to 168 MHz)
+           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
+                the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
+
+         (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
+             and if a HSE clock failure occurs(HSE used directly or through PLL as System 
+             clock source), the System clockis automatically switched to HSI and an interrupt
+             is generated if enabled. The interrupt is linked to the Cortex-M4 NMI 
+             (Non-Maskable Interrupt) exception vector.   
+
+         (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
+             clock (through a configurable prescaler) on PA8 pin.
+
+         (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
+             clock (through a configurable prescaler) on PC9 pin.
+
+    [..] System, AHB and APB busses clocks configuration  
+         (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+             HSE and PLL.
+             The AHB clock (HCLK) is derived from System clock through configurable 
+             prescaler and used to clock the CPU, memory and peripherals mapped 
+             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived 
+             from AHB clock through configurable prescalers and used to clock 
+             the peripherals mapped on these busses. You can use 
+             "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.  
+
+         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
+           (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
+                from an external clock mapped on the I2S_CKIN pin. 
+                You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
+          (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
+                from an external clock mapped on the I2S_CKIN pin. 
+                You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. 
+           (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
+                divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
+                macros to configure this clock. 
+           (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
+                to work correctly, while the SDIO require a frequency equal or lower than
+                to 48. This clock is derived of the main PLL through PLLQ divider.
+           (+@) IWDG clock which is always the LSI clock.
+       
+         (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
+             frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. 
+             Depending on the device voltage range, the maximum frequency should
+             be adapted accordingly (refer to the product datasheets for more details).
+             
+         (#) For the STM32F42xxx and STM32F43xxx devices, the maximum frequency
+             of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz. 
+             Depending on the device voltage range, the maximum frequency should
+             be adapted accordingly (refer to the product datasheets for more details).
+             
+         (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
+             PCLK2 84 MHz and PCLK1 42 MHz. 
+             Depending on the device voltage range, the maximum frequency should
+             be adapted accordingly (refer to the product datasheets for more details).
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *            - HSI ON and used as system clock source
+  *            - HSE, PLL and PLLI2S OFF
+  *            - AHB, APB1 and APB2 prescaler set to 1.
+  *            - CSS, MCO1 and MCO2 OFF
+  *            - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *            - Peripheral clocks  
+  *            - LSI, LSE and RTC clocks 
+  * @param  None
+  * @retval None
+  */
+void HAL_RCC_DeInit(void)
+{
+  /* Set HSION bit */
+  SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); 
+  
+  /* Reset CFGR register */
+  CLEAR_REG(RCC->CFGR);
+  
+  /* Reset HSEON, CSSON, PLLON, PLLI2S */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON); 
+  
+  /* Reset PLLCFGR register */
+  CLEAR_REG(RCC->PLLCFGR);
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2); 
+  
+  /* Reset PLLI2SCFGR register */
+  CLEAR_REG(RCC->PLLI2SCFGR);
+  SET_BIT(RCC->PLLI2SCFGR,  RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
+  
+  /* Reset HSEBYP bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+  
+  /* Disable all interrupts */
+  CLEAR_REG(RCC->CIR); 
+}
+
+/**
+  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
+  *         RCC_OscInitTypeDef.
+  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC Oscillators.
+  * @note   The PLL is not disabled when used as system clock.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  uint32_t tickstart = 0;  
+ 
+  /* Check the parameters */
+  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+  /*------------------------------- HSE Configuration ------------------------*/ 
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+    {
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON))
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
+      __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
+      
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+      
+      /* Wait till HSE is disabled */  
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+      {
+        if((int32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }       
+      }
+      
+      /* Set the new HSE configuration ---------------------------------------*/
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+      
+      /* Check the HSE State */
+      if((RCC_OscInitStruct->HSEState) == RCC_HSE_ON)
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+      
+        /* Wait till HSE is ready */  
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+        {
+          if((int32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          } 
+        }
+      }
+      else
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is bypassed or disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+        {
+          if((int32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          } 
+        }
+      }
+    }
+  }
+  /*----------------------------- HSI Configuration --------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+    
+    /* When the HSI is used as system clock it will not disabled */
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+    {
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Check the HSI State */
+      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+      {
+        /* Enable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */  
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+        {
+          if((int32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }       
+        } 
+                
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+      
+        /* Wait till HSI is ready */  
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+        {
+          if((int32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          } 
+        } 
+      }
+    }
+  }
+  /*------------------------------ LSI Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+    /* Check the LSI State */
+    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_ENABLE();
+      
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+      
+      /* Wait till LSI is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+      {
+        if((int32_t) (HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        } 
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_DISABLE();
+      
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+      
+      /* Wait till LSI is ready */  
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+      {
+        if((int32_t) (HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }       
+      } 
+    }
+  }
+  /*------------------------------ LSE Configuration -------------------------*/ 
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+    
+    /* Enable Power Clock*/
+    __PWR_CLK_ENABLE();
+    
+    /* Enable write access to Backup domain */
+    PWR->CR |= PWR_CR_DBP;
+    
+    /* Wait for Backup domain Write protection disable */
+    tickstart = HAL_GetTick();
+    
+    while((PWR->CR & PWR_CR_DBP) == RESET)
+    {
+      if((int32_t) (HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }      
+    }
+    
+    /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
+    __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
+    
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+    
+    /* Wait till LSE is ready */  
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+    {
+      if((int32_t) (HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }    
+    } 
+    
+    /* Set the new LSE configuration -----------------------------------------*/
+    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+    /* Check the LSE State */
+    if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+      
+      /* Wait till LSE is ready */  
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+      {
+        if((int32_t) (HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }       
+      }
+    }
+    else
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+      
+      /* Wait till LSE is ready */  
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+      {
+        if((int32_t) (HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }       
+      }
+    }
+  }
+  /*-------------------------------- PLL Configuration -----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+  {
+    /* Check if the PLL is used as system clock or not */
+    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+    { 
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+      {
+        /* Check the parameters */
+        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+        
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+        
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+        
+        /* Wait till PLL is ready */  
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+        {
+          if((int32_t) (HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }        
+
+        /* Configure the main PLL clock source, multiplication and division factors. */
+        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+                             RCC_OscInitStruct->PLL.PLLM,
+                             RCC_OscInitStruct->PLL.PLLN,
+                             RCC_OscInitStruct->PLL.PLLP,
+                             RCC_OscInitStruct->PLL.PLLQ);
+        /* Enable the main PLL. */
+        __HAL_RCC_PLL_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+        
+        /* Wait till PLL is ready */  
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+        {
+          if((int32_t) (HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          } 
+        }
+      }
+      else
+      {
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+ 
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+        
+        /* Wait till PLL is ready */  
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+        {
+          if((int32_t) (HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  return HAL_OK;
+}
+ 
+/**
+  * @brief  Initializes the CPU, AHB and APB busses clocks according to the specified 
+  *         parameters in the RCC_ClkInitStruct.
+  * @param  RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC peripheral.
+  * @param  FLatency: FLASH Latency, this parameter depend on device selected
+  * 
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency 
+  *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
+  *
+  * @note   The HSI is used (enabled by hardware) as system clock source after
+  *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
+  *         of failure of the HSE used directly or indirectly as system clock
+  *         (if the Clock Security System CSS is enabled).
+  *           
+  * @note   A switch from one clock source to another occurs only if the target
+  *         clock source is ready (clock stable after startup delay or PLL locked). 
+  *         If a clock source which is not yet ready is selected, the switch will
+  *         occur when the clock source will be ready. 
+  *           
+  * @note   Depending on the device voltage range, the software has to set correctly
+  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
+  *         (for more details refer to section above "Initialization/de-initialization functions")
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+{
+  uint32_t tickstart = 0;   
+ 
+  /* Check the parameters */
+  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+  assert_param(IS_FLASH_LATENCY(FLatency));
+ 
+  /* To correctly read data from FLASH memory, the number of wait states (LATENCY) 
+    must be correctly programmed according to the frequency of the CPU clock 
+    (HCLK) and the supply voltage of the device. */
+  
+  /* Increasing the CPU frequency */
+  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
+  {    
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+    
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+    {
+      return HAL_ERROR;
+    }
+
+    /*-------------------------- HCLK Configuration --------------------------*/
+    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+    {
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+    }
+
+    /*------------------------- SYSCLK Configuration ---------------------------*/ 
+    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+    {    
+      assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+      
+      /* HSE is selected as System Clock Source */
+      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+      {
+        /* Check the HSE ready flag */  
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+        {
+          return HAL_ERROR;
+        }
+      }
+      /* PLL is selected as System Clock Source */
+      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+      {
+        /* Check the PLL ready flag */  
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+        {
+          return HAL_ERROR;
+        }
+      }
+      /* HSI is selected as System Clock Source */
+      else
+      {
+        /* Check the HSI ready flag */  
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+        {
+          return HAL_ERROR;
+        }
+      }
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+ 
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+      
+      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+      {
+        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
+        {
+          if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+      {
+        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+        {
+          if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
+        {
+          if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }    
+  }
+  /* Decreasing the CPU frequency */
+  else
+  {
+    /*-------------------------- HCLK Configuration --------------------------*/
+    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+    {
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+    }
+
+    /*------------------------- SYSCLK Configuration -------------------------*/
+    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+    {    
+      assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+      
+      /* HSE is selected as System Clock Source */
+      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+      {
+        /* Check the HSE ready flag */  
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+        {
+          return HAL_ERROR;
+        }
+      }
+      /* PLL is selected as System Clock Source */
+      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+      {
+        /* Check the PLL ready flag */  
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+        {
+          return HAL_ERROR;
+        }
+      }
+      /* HSI is selected as System Clock Source */
+      else
+      {
+        /* Check the HSI ready flag */  
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+        {
+          return HAL_ERROR;
+        }
+      }
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+      
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+      
+      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+      {
+        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
+        {
+          if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          } 
+        }
+      }
+      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+      {
+        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+        {
+          if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          } 
+        }
+      }
+      else
+      {
+        while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
+        {
+          if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+    
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+    {
+      return HAL_ERROR;
+    }
+ }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/ 
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+  {
+    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+  }
+  
+  /*-------------------------- PCLK2 Configuration ---------------------------*/ 
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+  {
+    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
+  }
+
+  /* Configure the source of time base considering new system clocks settings*/
+  HAL_InitTick (TICK_INT_PRIORITY);
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Group2 Peripheral Control functions 
+ *  @brief   RCC clocks control functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks 
+    frequencies.
+      
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
+  * @note   PA8/PC9 should be configured in alternate function mode.
+  * @param  RCC_MCOx: specifies the output direction for the clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
+  *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
+  * @param  RCC_MCOSource: specifies the clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
+  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
+  * @param  RCC_MCODiv: specifies the MCOx prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
+  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+  * @retval None
+  */
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+  GPIO_InitTypeDef GPIO_InitStruct;
+  /* Check the parameters */
+  assert_param(IS_RCC_MCO(RCC_MCOx));
+  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+  /* RCC_MCO1 */
+  if(RCC_MCOx == RCC_MCO1)
+  {
+    assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+    
+    /* MCO1 Clock Enable */
+    __MCO1_CLK_ENABLE();
+    
+    /* Configue the MCO1 pin in alternate function mode */    
+    GPIO_InitStruct.Pin = MCO1_PIN;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+    HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
+    
+    /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
+  }
+  else
+  {
+    assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
+    
+    /* MCO2 Clock Enable */
+    __MCO2_CLK_ENABLE();
+    
+    /* Configue the MCO2 pin in alternate function mode */
+    GPIO_InitStruct.Pin = MCO2_PIN;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+    HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
+    
+    /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
+  }
+}
+
+/**
+  * @brief  Enables the Clock Security System.
+  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
+  *         is automatically disabled and an interrupt is generated to inform the
+  *         software about the failure (Clock Security System Interrupt, CSSI),
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to 
+  *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.  
+  * @param  None
+  * @retval None
+  */
+void HAL_RCC_EnableCSS(void)
+{
+  *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief  Disables the Clock Security System.
+  * @param  None
+  * @retval None
+  */
+void HAL_RCC_DisableCSS(void)
+{
+  *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)DISABLE;
+}
+
+/**
+  * @brief  Returns the SYSCLK frequency
+  *        
+  * @note   The system frequency computed by this function is not the real 
+  *         frequency in the chip. It is calculated based on the predefined 
+  *         constant and the selected clock source:
+  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) 
+  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.         
+  * @note     (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *               16 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                have wrong result.
+  *                  
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.
+  *           
+  * @note   This function can be used by the user application to compute the 
+  *         baudrate for the communication peripherals or configure other parameters.
+  *           
+  * @note   Each time SYSCLK changes, this function must be called to update the
+  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *         
+  *               
+  * @param  None
+  * @retval SYSCLK frequency
+  */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+  uint32_t pllm = 0, pllvco = 0, pllp = 0;
+  uint32_t sysclockfreq = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+    {
+      sysclockfreq = HSI_VALUE;
+       break;
+    }
+    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+    {
+      sysclockfreq = HSE_VALUE;
+      break;
+    }
+    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock  source */
+    {
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+      SYSCLK = PLL_VCO / PLLP */
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      if (__RCC_PLLSRC() != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));    
+      }
+      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
+      
+      sysclockfreq = pllvco/pllp;
+      break;
+    }
+    default:
+    {
+      sysclockfreq = HSI_VALUE;
+      break;
+    }
+  }
+  return sysclockfreq;
+}
+
+/**
+  * @brief  Returns the HCLK frequency     
+  * @note   Each time HCLK changes, this function must be called to update the
+  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+  * 
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency 
+  *         and updated within this function
+  * @param  None
+  * @retval HCLK frequency
+  */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
+  return SystemCoreClock;
+}
+
+/**
+  * @brief  Returns the PCLK1 frequency     
+  * @note   Each time PCLK1 changes, this function must be called to update the
+  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  None
+  * @retval PCLK1 frequency
+  */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{  
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
+}
+
+/**
+  * @brief  Returns the PCLK2 frequency     
+  * @note   Each time PCLK2 changes, this function must be called to update the
+  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  None
+  * @retval PCLK2 frequency
+  */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
+} 
+
+/**
+  * @brief  Configures the RCC_OscInitStruct according to the internal 
+  * RCC configuration registers.
+  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that 
+  * will be configured.
+  * @retval None
+  */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  /* Set all possible values for the Oscillator type parameter ---------------*/
+  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+  
+  /* Get the HSE configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+  }
+  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+  }
+  
+  /* Get the HSI configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+  }
+  
+  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
+  
+  /* Get the LSE configuration -----------------------------------------------*/
+  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+  }
+  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+  }
+  
+  /* Get the LSI configuration -----------------------------------------------*/
+  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+  }
+  
+  /* Get the PLL configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+  }
+  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+  RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
+  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
+  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
+  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
+}
+
+/**
+  * @brief  Configures the RCC_ClkInitStruct according to the internal 
+  * RCC configuration registers.
+  * @param  RCC_OscInitStruct: pointer to an RCC_ClkInitTypeDef structure that 
+  * will be configured.
+  * @param  pFLatency: Pointer on the Flash Latency.
+  * @retval None
+  */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+  /* Set all possible values for the Clock type parameter --------------------*/
+  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+   
+  /* Get the SYSCLK configuration --------------------------------------------*/ 
+  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+  
+  /* Get the HCLK configuration ----------------------------------------------*/ 
+  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); 
+  
+  /* Get the APB1 configuration ----------------------------------------------*/ 
+  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);   
+  
+  /* Get the APB2 configuration ----------------------------------------------*/ 
+  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
+  
+  /* Get the Flash Wait State (Latency) configuration ------------------------*/   
+  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 
+}
+
+/**
+  * @brief This function handles the RCC CSS interrupt request.
+  * @note This API should be called under the NMI_Handler().
+  * @param None
+  * @retval None
+  */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+  /* Check RCC CSSF flag  */
+  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+  {
+    /* RCC Clock Security System interrupt user callback */
+    HAL_RCC_CCSCallback();
+
+    /* Clear RCC CSS pending bit */
+    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+  }
+}
+
+/**
+  * @brief  RCC Clock Security System interrupt callback
+  * @param  none 
+  * @retval none
+  */
+__weak void HAL_RCC_CCSCallback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RCC_CCSCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1170 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_rcc.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of RCC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RCC_H
+#define __STM32F4xx_HAL_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/**
+  * @brief  RCC PLL configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PLLState;   /*!< The new state of the PLL.
+                            This parameter can be a value of @ref RCC_PLL_Config                      */
+
+  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
+                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */           
+
+  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 63    */        
+
+  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
+                            This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
+
+  uint32_t PLLP;       /*!< PLLP: Division factor for main system clock (SYSCLK).
+                            This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */
+
+  uint32_t PLLQ;       /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 63    */
+
+}RCC_PLLInitTypeDef;
+
+/**
+  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition  
+  */
+typedef struct
+{
+  uint32_t OscillatorType;       /*!< The oscillators to be configured.
+                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */
+
+  uint32_t HSEState;             /*!< The new state of the HSE.
+                                      This parameter can be a value of @ref RCC_HSE_Config                        */
+
+  uint32_t LSEState;             /*!< The new state of the LSE.
+                                      This parameter can be a value of @ref RCC_LSE_Config                        */
+                                          
+  uint32_t HSIState;             /*!< The new state of the HSI.
+                                      This parameter can be a value of @ref RCC_HSI_Config                        */
+
+  uint32_t HSICalibrationValue;  /*!< The calibration trimming value.
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+                               
+  uint32_t LSIState;             /*!< The new state of the LSI.
+                                      This parameter can be a value of @ref RCC_LSI_Config                        */
+
+  RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */      
+
+}RCC_OscInitTypeDef;
+
+/**
+  * @brief  RCC System, AHB and APB busses clock configuration structure definition  
+  */
+typedef struct
+{
+  uint32_t ClockType;             /*!< The clock to be configured.
+                                       This parameter can be a value of @ref RCC_System_Clock_Type      */
+
+  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
+                                       This parameter can be a value of @ref RCC_System_Clock_Source    */
+
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_AHB_Clock_Source       */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+}RCC_ClkInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup RCC_BitAddress_AliasRegion
+  * @brief RCC registers bit address in the alias region
+  * @{
+  */
+#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
+/* --- CR Register ---*/
+/* Alias word address of HSION bit */
+#define RCC_CR_OFFSET             (RCC_OFFSET + 0x00)
+#define HSION_BitNumber           0x00
+#define CR_HSION_BB               (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
+/* Alias word address of CSSON bit */
+#define CSSON_BitNumber           0x13
+#define CR_CSSON_BB               (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
+/* Alias word address of PLLON bit */
+#define PLLON_BitNumber           0x18
+#define CR_PLLON_BB               (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
+/* Alias word address of PLLI2SON bit */
+#define PLLI2SON_BitNumber        0x1A
+#define CR_PLLI2SON_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+/* Alias word address of I2SSRC bit */
+#define RCC_CFGR_OFFSET           (RCC_OFFSET + 0x08)
+#define I2SSRC_BitNumber          0x17
+#define CFGR_I2SSRC_BB            (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
+
+/* --- BDCR Register ---*/
+/* Alias word address of RTCEN bit */
+#define RCC_BDCR_OFFSET           (RCC_OFFSET + 0x70)
+#define RTCEN_BitNumber           0x0F
+#define BDCR_RTCEN_BB             (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
+/* Alias word address of BDRST bit */
+#define BDRST_BitNumber           0x10
+#define BDCR_BDRST_BB             (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
+
+/* --- CSR Register ---*/
+/* Alias word address of LSION bit */
+#define RCC_CSR_OFFSET            (RCC_OFFSET + 0x74)
+#define LSION_BitNumber           0x00
+#define CSR_LSION_BB              (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
+
+/* CR register byte 3 (Bits[23:16]) base address */
+#define CR_BYTE2_ADDRESS          ((uint32_t)0x40023802)
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define CIR_BYTE1_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x01))
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define CIR_BYTE2_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x02))
+
+/* BDCR register base address */
+#define BDCR_BYTE0_ADDRESS        (PERIPH_BASE + RCC_BDCR_OFFSET)
+
+
+#define DBP_TIMEOUT_VALUE          ((uint32_t)100)
+#define LSE_TIMEOUT_VALUE          ((uint32_t)500)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Oscillator_Type
+  * @{
+  */
+#define RCC_OSCILLATORTYPE_NONE            ((uint32_t)0x00000000)
+#define RCC_OSCILLATORTYPE_HSE             ((uint32_t)0x00000001)
+#define RCC_OSCILLATORTYPE_HSI             ((uint32_t)0x00000002)
+#define RCC_OSCILLATORTYPE_LSE             ((uint32_t)0x00000004)
+#define RCC_OSCILLATORTYPE_LSI             ((uint32_t)0x00000008)
+
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSE_Config
+  * @{
+  */
+#define RCC_HSE_OFF                      ((uint8_t)0x00)
+#define RCC_HSE_ON                       ((uint8_t)0x01)
+#define RCC_HSE_BYPASS                   ((uint8_t)0x05)
+
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_BYPASS))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSE_Config
+  * @{
+  */
+#define RCC_LSE_OFF                      ((uint8_t)0x00)
+#define RCC_LSE_ON                       ((uint8_t)0x01)
+#define RCC_LSE_BYPASS                   ((uint8_t)0x05)
+
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_BYPASS))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI_Config
+  * @{
+  */
+#define RCC_HSI_OFF                      ((uint8_t)0x00)
+#define RCC_HSI_ON                       ((uint8_t)0x01)
+
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSI_Config 
+  * @{
+  */
+#define RCC_LSI_OFF                      ((uint8_t)0x00)
+#define RCC_LSI_ON                       ((uint8_t)0x01)
+
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Config 
+  * @{
+  */
+#define RCC_PLL_NONE                      ((uint8_t)0x00)
+#define RCC_PLL_OFF                       ((uint8_t)0x01)
+#define RCC_PLL_ON                        ((uint8_t)0x02)
+
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLLP_Clock_Divider
+  * @{
+  */
+#define RCC_PLLP_DIV2                  ((uint32_t)0x00000002)
+#define RCC_PLLP_DIV4                  ((uint32_t)0x00000004)
+#define RCC_PLLP_DIV6                  ((uint32_t)0x00000006)
+#define RCC_PLLP_DIV8                  ((uint32_t)0x00000008)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Clock_Source 
+  * @{
+  */
+#define RCC_PLLSOURCE_HSI                RCC_PLLCFGR_PLLSRC_HSI
+#define RCC_PLLSOURCE_HSE                RCC_PLLCFGR_PLLSRC_HSE
+
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
+                                  ((SOURCE) == RCC_PLLSOURCE_HSE))
+#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
+#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
+#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
+
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))  
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Type
+  * @{
+  */
+#define RCC_CLOCKTYPE_SYSCLK             ((uint32_t)0x00000001)
+#define RCC_CLOCKTYPE_HCLK               ((uint32_t)0x00000002)
+#define RCC_CLOCKTYPE_PCLK1              ((uint32_t)0x00000004)
+#define RCC_CLOCKTYPE_PCLK2              ((uint32_t)0x00000008)
+
+#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
+/**
+  * @}
+  */
+  
+/** @defgroup RCC_System_Clock_Source 
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL
+
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
+/**
+  * @}
+  */ 
+
+/** @defgroup RCC_AHB_Clock_Source
+  * @{
+  */
+#define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1
+#define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2
+#define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4
+#define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8
+#define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16
+#define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64
+#define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128
+#define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256
+#define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512
+
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1)   || ((HCLK) == RCC_SYSCLK_DIV2)   || \
+                           ((HCLK) == RCC_SYSCLK_DIV4)   || ((HCLK) == RCC_SYSCLK_DIV8)   || \
+                           ((HCLK) == RCC_SYSCLK_DIV16)  || ((HCLK) == RCC_SYSCLK_DIV64)  || \
+                           ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
+                           ((HCLK) == RCC_SYSCLK_DIV512))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_APB1_APB2_Clock_Source
+  * @{
+  */
+#define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1
+#define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2
+#define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4
+#define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8
+#define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16
+
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
+                           ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
+                           ((PCLK) == RCC_HCLK_DIV16))
+/**
+  * @}
+  */ 
+
+/** @defgroup RCC_RTC_Clock_Source
+  * @{
+  */
+#define RCC_RTCCLKSOURCE_LSE             ((uint32_t)0x00000100)
+#define RCC_RTCCLKSOURCE_LSI             ((uint32_t)0x00000200)
+#define RCC_RTCCLKSOURCE_HSE_DIV2        ((uint32_t)0x00020300)
+#define RCC_RTCCLKSOURCE_HSE_DIV3        ((uint32_t)0x00030300)
+#define RCC_RTCCLKSOURCE_HSE_DIV4        ((uint32_t)0x00040300)
+#define RCC_RTCCLKSOURCE_HSE_DIV5        ((uint32_t)0x00050300)
+#define RCC_RTCCLKSOURCE_HSE_DIV6        ((uint32_t)0x00060300)
+#define RCC_RTCCLKSOURCE_HSE_DIV7        ((uint32_t)0x00070300)
+#define RCC_RTCCLKSOURCE_HSE_DIV8        ((uint32_t)0x00080300)
+#define RCC_RTCCLKSOURCE_HSE_DIV9        ((uint32_t)0x00090300)
+#define RCC_RTCCLKSOURCE_HSE_DIV10       ((uint32_t)0x000A0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV11       ((uint32_t)0x000B0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV12       ((uint32_t)0x000C0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV13       ((uint32_t)0x000D0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV14       ((uint32_t)0x000E0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV15       ((uint32_t)0x000F0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV16       ((uint32_t)0x00100300)
+#define RCC_RTCCLKSOURCE_HSE_DIV17       ((uint32_t)0x00110300)
+#define RCC_RTCCLKSOURCE_HSE_DIV18       ((uint32_t)0x00120300)
+#define RCC_RTCCLKSOURCE_HSE_DIV19       ((uint32_t)0x00130300)
+#define RCC_RTCCLKSOURCE_HSE_DIV20       ((uint32_t)0x00140300)
+#define RCC_RTCCLKSOURCE_HSE_DIV21       ((uint32_t)0x00150300)
+#define RCC_RTCCLKSOURCE_HSE_DIV22       ((uint32_t)0x00160300)
+#define RCC_RTCCLKSOURCE_HSE_DIV23       ((uint32_t)0x00170300)
+#define RCC_RTCCLKSOURCE_HSE_DIV24       ((uint32_t)0x00180300)
+#define RCC_RTCCLKSOURCE_HSE_DIV25       ((uint32_t)0x00190300)
+#define RCC_RTCCLKSOURCE_HSE_DIV26       ((uint32_t)0x001A0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV27       ((uint32_t)0x001B0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV28       ((uint32_t)0x001C0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV29       ((uint32_t)0x001D0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV30       ((uint32_t)0x001E0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV31       ((uint32_t)0x001F0300)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_I2S_Clock_Source
+  * @{
+  */
+#define RCC_I2SCLKSOURCE_PLLI2S         ((uint32_t)0x00000000)
+#define RCC_I2SCLKSOURCE_EXT            ((uint32_t)0x00000001)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO_Index
+  * @{
+  */
+#define RCC_MCO1                         ((uint32_t)0x00000000)
+#define RCC_MCO2                         ((uint32_t)0x00000001)
+
+#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO1_Clock_Source
+  * @{
+  */
+#define RCC_MCO1SOURCE_HSI               ((uint32_t)0x00000000)
+#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0
+#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1
+#define RCC_MCO1SOURCE_PLLCLK            RCC_CFGR_MCO1
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
+                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO2_Clock_Source
+  * @{
+  */
+#define RCC_MCO2SOURCE_SYSCLK            ((uint32_t)0x00000000)
+#define RCC_MCO2SOURCE_PLLI2SCLK         RCC_CFGR_MCO2_0
+#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
+#define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2
+
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
+                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler
+  * @{
+  */
+#define RCC_MCODIV_1                    ((uint32_t)0x00000000)
+#define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_2
+#define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_4                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_5                    RCC_CFGR_MCO1PRE
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2) || \
+                             ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
+                             ((DIV) == RCC_MCODIV_5)) 
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Interrupt 
+  * @{
+  */
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
+#define RCC_IT_PLLI2SRDY                 ((uint8_t)0x20)
+#define RCC_IT_CSS                       ((uint8_t)0x80)
+/**
+  * @}
+  */
+  
+/** @defgroup RCC_Flag
+  *        Elements values convention: 0XXYYYYYb
+  *           - YYYYY  : Flag position in the register
+  *           - 0XX  : Register index
+  *                 - 01: CR register
+  *                 - 10: BDCR register
+  *                 - 11: CSR register
+  * @{
+  */
+/* Flags in the CR register */
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
+#define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3B)
+
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
+
+/* Flags in the CSR register */
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
+#define RCC_FLAG_BORRST                  ((uint8_t)0x79)
+#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
+
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */   
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.   
+  */
+#define __GPIOA_CLK_ENABLE()         (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN))
+#define __GPIOB_CLK_ENABLE()         (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOBEN))
+#define __GPIOC_CLK_ENABLE()         (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOCEN))
+#define __GPIOD_CLK_ENABLE()         (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIODEN))
+#define __GPIOE_CLK_ENABLE()         (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOEEN))
+#define __GPIOH_CLK_ENABLE()         (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOHEN))
+#define __CRC_CLK_ENABLE()           (RCC->AHB1ENR |= (RCC_AHB1ENR_CRCEN))
+#define __BKPSRAM_CLK_ENABLE()       (RCC->AHB1ENR |= (RCC_AHB1ENR_BKPSRAMEN))
+#define __CCMDATARAMEN_CLK_ENABLE()  (RCC->AHB1ENR |= (RCC_AHB1ENR_CCMDATARAMEN))
+#define __DMA1_CLK_ENABLE()          (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA1EN))
+#define __DMA2_CLK_ENABLE()          (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2EN))
+
+#define __GPIOA_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
+#define __GPIOB_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
+#define __GPIOC_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
+#define __GPIOD_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __GPIOE_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __GPIOH_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
+#define __CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+#define __BKPSRAM_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __DMA1_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
+#define __DMA2_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
+
+/** @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  */
+#define __USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+                                       __SYSCFG_CLK_ENABLE();\
+                                    }while(0)
+                                        
+
+#define __USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
+                                         __SYSCFG_CLK_DISABLE();\
+                                    }while(0)
+
+#define __RNG_CLK_ENABLE()    (RCC->AHB2ENR |= (RCC_AHB2ENR_RNGEN))
+#define __RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+/** @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+#define __TIM2_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
+#define __TIM3_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
+#define __TIM4_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN))
+#define __TIM5_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN))
+#define __WWDG_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
+#define __SPI2_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
+#define __SPI3_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
+#define __USART2_CLK_ENABLE()  (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
+#define __I2C1_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
+#define __I2C2_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
+#define __I2C3_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
+#define __PWR_CLK_ENABLE()     (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
+
+#define __TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
+#define __WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#define __SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
+#define __I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define __I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#define __I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __PWR_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) 
+
+/** @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  */
+#define __TIM1_CLK_ENABLE()    (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
+#define __USART1_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
+#define __USART6_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
+#define __ADC1_CLK_ENABLE()    (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
+#define __SDIO_CLK_ENABLE()    (RCC->APB2ENR |= (RCC_APB2ENR_SDIOEN))
+#define __SPI1_CLK_ENABLE()    (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
+#define __SPI4_CLK_ENABLE()    (RCC->APB2ENR |= (RCC_APB2ENR_SPI4EN))
+#define __SYSCFG_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
+#define __TIM9_CLK_ENABLE()    (RCC->APB2ENR |= (RCC_APB2ENR_TIM9EN))
+#define __TIM10_CLK_ENABLE()   (RCC->APB2ENR |= (RCC_APB2ENR_TIM10EN))
+#define __TIM11_CLK_ENABLE()   (RCC->APB2ENR |= (RCC_APB2ENR_TIM11EN))
+
+#define __TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
+#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
+#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
+#define __ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
+#define __SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#define __SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
+#define __TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
+#define __TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __TIM11_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
+
+/** @brief  Force or release AHB1 peripheral reset.
+  */  
+#define __AHB1_FORCE_RESET()    (RCC->AHB1RSTR = 0xFFFFFFFF)
+#define __GPIOA_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
+#define __GPIOB_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
+#define __GPIOC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
+#define __GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __GPIOH_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
+#define __CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+#define __DMA1_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
+#define __DMA2_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
+
+#define __AHB1_RELEASE_RESET()  (RCC->AHB1RSTR = 0x00)
+#define __GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
+#define __GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
+#define __GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
+#define __GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
+#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
+#define __CRC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+#define __DMA1_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
+#define __DMA2_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
+
+/** @brief  Force or release AHB2 peripheral reset.
+  */
+#define __AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFF) 
+#define __OTGFS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+
+#define __AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00)
+#define __OTGFS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+
+#define __RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+
+/** @brief  Force or release APB1 peripheral reset.
+  */
+#define __APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFF)  
+#define __TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __TIM5_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
+#define __WWDG_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
+#define __SPI2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __USART2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __I2C1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+#define __I2C2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+#define __I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+#define __PWR_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
+
+#define __APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00) 
+#define __TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __TIM5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
+#define __WWDG_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
+#define __SPI2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
+#define __I2C1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
+#define __I2C2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#define __I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#define __PWR_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
+
+/** @brief  Force or release APB2 peripheral reset.
+  */
+#define __APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFF)  
+#define __TIM1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
+#define __USART1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
+#define __USART6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
+#define __ADC_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
+#define __SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __SPI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+#define __SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __SYSCFG_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
+#define __TIM9_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
+#define __TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+#define __TIM11_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
+
+#define __APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00)
+#define __TIM1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
+#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
+#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
+#define __ADC_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
+#define __SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __SPI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#define __SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
+#define __TIM9_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
+#define __TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __TIM11_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
+
+/** @brief  Force or release AHB3 peripheral reset.
+  */  
+#define __AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
+#define __AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) 
+
+/** @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#define __GPIOA_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
+#define __GPIOB_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
+#define __GPIOC_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
+#define __GPIOD_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __GPIOE_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __GPIOH_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
+#define __CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __BKPSRAM_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+#define __DMA1_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __DMA2_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+
+#define __GPIOA_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
+#define __GPIOB_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
+#define __GPIOC_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
+#define __GPIOD_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __GPIOE_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __GPIOH_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
+#define __CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+#define __DMA1_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
+#define __DMA2_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
+
+/** @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#define __OTGFS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __OTGFS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+
+/** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#define __TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __TIM5_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
+#define __WWDG_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
+#define __SPI2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
+#define __SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __USART2_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
+#define __I2C1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
+#define __I2C2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
+#define __I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+#define __PWR_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
+
+#define __TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __TIM5_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
+#define __WWDG_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
+#define __SPI2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
+#define __SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
+#define __I2C1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
+#define __I2C2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
+#define __I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+#define __PWR_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
+
+/** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#define __TIM1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
+#define __USART1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
+#define __USART6_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
+#define __ADC1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
+#define __SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __SPI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
+#define __SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __SYSCFG_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
+#define __TIM9_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
+#define __TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+#define __TIM11_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
+
+#define __TIM1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
+#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
+#define __USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
+#define __ADC1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
+#define __SDIO_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __SPI1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
+#define __SPI4_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
+#define __TIM9_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
+#define __TIM10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __TIM11_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
+
+/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  *         It is used (enabled by hardware) as system clock source after startup
+  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+  *         of the HSE used directly or indirectly as system clock (if the Clock
+  *         Security System CSS is enabled).             
+  * @note   HSI can not be stopped if it is used as system clock source. In this case,
+  *         you have to select another source of the system clock then stop the HSI.  
+  * @note   After enabling the HSI, the application software should wait on HSIRDY
+  *         flag to be set indicating that HSI clock is stable and can be used as
+  *         system clock source.  
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.  
+  */
+#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) CR_HSION_BB = ENABLE)
+#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) CR_HSION_BB = DISABLE)
+
+/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI RC.
+  * @param  __HSICalibrationValue__: specifies the calibration trimming value.
+  *         This parameter must be a number between 0 and 0x1F.
+  */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
+        RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
+
+/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
+  * @note   After enabling the LSI, the application software should wait on 
+  *         LSIRDY flag to be set indicating that LSI clock is stable and can
+  *         be used to clock the IWDG and/or the RTC.
+  * @note   LSI can not be disabled if the IWDG is running.
+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+  *         clock cycles. 
+  */
+#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) CSR_LSION_BB = ENABLE)
+#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) CSR_LSION_BB = DISABLE)
+
+/**
+  * @brief  Macro to configure the External High Speed oscillator (HSE).
+  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+  *         software should wait on HSERDY flag to be set indicating that HSE clock
+  *         is stable and can be used to clock the PLL and/or system clock.
+  * @note   HSE state can not be changed if it is used directly or through the
+  *         PLL as system clock. In this case, you have to select another source
+  *         of the system clock then change the HSE state (ex. disable it).
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.  
+  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
+  *         was previously enabled you have to enable it again after calling this
+  *         function.    
+  * @param  __STATE__: specifies the new state of the HSE.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+  *                              6 HSE oscillator clock cycles.
+  *            @arg RCC_HSE_ON: turn ON the HSE oscillator.
+  *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
+  */
+#define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) CR_BYTE2_ADDRESS = (__STATE__))
+
+/**
+  * @brief  Macro to configure the External Low Speed oscillator (LSE).
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using 
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).  
+  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
+  *         software should wait on LSERDY flag to be set indicating that LSE clock
+  *         is stable and can be used to clock the RTC.
+  * @param  __STATE__: specifies the new state of the LSE.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+  *                              6 LSE oscillator clock cycles.
+  *            @arg RCC_LSE_ON: turn ON the LSE oscillator.
+  *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
+  */
+#define __HAL_RCC_LSE_CONFIG(__STATE__)  (*(__IO uint8_t *) BDCR_BYTE0_ADDRESS = (__STATE__))
+
+/** @brief  Macros to enable or disable the the RTC clock.
+  * @note   These macros must be used only after the RTC clock source was selected.
+  */
+#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) BDCR_RTCEN_BB = ENABLE)
+#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) BDCR_RTCEN_BB = DISABLE)
+
+/** @brief  Macros to configure the RTC clock (RTCCLK).
+  * @note   As the RTC clock configuration bits are in the Backup domain and write
+  *         access is denied to this domain after reset, you have to enable write
+  *         access using the Power Backup Access macro before to configure
+  *         the RTC clock source (to be done once after reset).    
+  * @note   Once the RTC clock is configured it can't be changed unless the  
+  *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
+  *         a Power On Reset (POR).
+  * @param  __RTCCLKSource__: specifies the RTC clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
+  *            @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
+  *            @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
+  *                                            as RTC clock, where x:[2,31]
+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
+  *         work in STOP and STANDBY modes, and can be used as wakeup source.
+  *         However, when the HSE clock is used as RTC clock source, the RTC
+  *         cannot be used in STOP and STANDBY modes.    
+  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
+  *         RTC clock source).
+  */
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
+                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
+                                                   
+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
+                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF);  \
+                                                   } while (0)
+
+/** @brief  Macros to force or release the Backup domain reset.
+  * @note   This function resets the RTC peripheral (including the backup registers)
+  *         and the RTC clock source selection in RCC_CSR register.
+  * @note   The BKPSRAM is not affected by this reset.   
+  */
+#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) BDCR_BDRST_BB = ENABLE)
+#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) BDCR_BDRST_BB = DISABLE)
+
+/** @brief  Macros to enable or disable the main PLL.
+  * @note   After enabling the main PLL, the application software should wait on 
+  *         PLLRDY flag to be set indicating that PLL clock is stable and can
+  *         be used as system clock source.
+  * @note   The main PLL can not be disabled if it is used as system clock source
+  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) CR_PLLON_BB = ENABLE)
+#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) CR_PLLON_BB = DISABLE)
+
+/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
+  * @note   This function must be used only when the main PLL is disabled.
+  * @param  __RCC_PLLSource__: specifies the PLL entry clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  
+  * @param  __PLLM__: specifies the division factor for PLL VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 2 MHz to limit PLL jitter.
+  * @param  __PLLN__: specifies the multiplication factor for PLL VCO output clock
+  *         This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
+  *         output frequency is between 192 and 432 MHz.
+  * @param  __PLLP__: specifies the division factor for main system clock (SYSCLK)
+  *         This parameter must be a number in the range {2, 4, 6, or 8}.
+  * @note   You have to set the PLLP parameter correctly to not exceed 168 MHz on
+  *         the System clock frequency.
+  * @param  __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  * @note   If the USB OTG FS is used in your application, you have to set the
+  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+  *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
+  *         correctly.
+  */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
+                            (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
+                            ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \
+                            ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
+
+/** @brief  Macro to configure the I2S clock source (I2SCLK).
+  * @note   This function must be called before enabling the I2S APB clock.
+  * @param  __SOURCE__: specifies the I2S clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
+  *            @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
+  *                                       used as I2S clock source.
+  */
+#define __HAL_RCC_I2SCLK(__SOURCE__) (*(__IO uint32_t *) CFGR_I2SSRC_BB = (__SOURCE__))
+
+/** @brief Macros to enable or disable the PLLI2S. 
+  * @note  The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) CR_PLLI2SON_BB = ENABLE)
+#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) CR_PLLI2SON_BB = DISABLE)
+
+/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
+  * @note   This macro must be used only when the PLLI2S is disabled.
+  * @note   PLLI2S clock source is common with the main PLL (configured in 
+  *         HAL_RCC_ClockConfig() API).  
+  * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
+  *         This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+  * @param  __PLLI2SR__: specifies the division factor for I2S clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+  *         on the I2S clock frequency.
+  */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) | ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
+
+/** @brief  Macro to get the clock source used as system clock.
+  * @retval The clock source used as system clock. The returned value can be one
+  *         of the following:
+  *              - RCC_CFGR_SWS_HSI: HSI used as system clock.
+  *              - RCC_CFGR_SWS_HSE: HSE used as system clock.
+  *              - RCC_CFGR_SWS_PLL: PLL used as system clock.
+  */     
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
+
+/** @brief  Macro to get the oscillator used as PLL clock source.
+  * @retval The oscillator used as PLL clock source. The returned value can be one
+  *         of the following:
+  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+  */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
+
+/** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
+  *         the selected interrupts).
+  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
+  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+  */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable 
+  *        the selected interrupts).
+  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
+  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+  */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
+
+/** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
+  *         bits to clear the selected interrupt pending bits.
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
+  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.  
+  *            @arg RCC_IT_CSS: Clock Security System interrupt
+  */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE2_ADDRESS = (__INTERRUPT__))
+
+/** @brief  Check the RCC's interrupt has occurred or not.
+  * @param  __INTERRUPT__: specifies the RCC interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
+  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+  *            @arg RCC_IT_CSS: Clock Security System interrupt
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, 
+  *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
+  */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
+
+/** @brief  Check RCC flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
+  *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
+  *            @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
+  *            @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
+  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
+  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
+  *            @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
+  *            @arg RCC_FLAG_PINRST: Pin reset.
+  *            @arg RCC_FLAG_PORRST: POR/PDR reset.
+  *            @arg RCC_FLAG_SFTRST: Software reset.
+  *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
+  *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
+  *            @arg RCC_FLAG_LPWRRST: Low Power reset.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define RCC_FLAG_MASK  ((uint8_t)0x1F)
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
+
+#define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
+
+
+/* Include RCC HAL Extension module */
+#include "stm32f4xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+                              
+/* Initialization and de-initialization functions  ******************************/
+void HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+
+/* Peripheral Control functions  ************************************************/
+void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void     HAL_RCC_EnableCSS(void);
+void     HAL_RCC_DisableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+
+/* CSS NMI IRQ handler */
+void HAL_RCC_NMI_IRQHandler(void);
+
+/* User Callbacks in non blocking mode (IT mode) */ 
+void HAL_RCC_CCSCallback(void);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,513 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_rcc_ex.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Extension RCC HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities RCC extension peripheral:
+  *           + Extended Peripheral Control functions
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCC 
+  * @brief RCC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define PLLI2S_TIMEOUT_VALUE    100 /* Timeout value fixed to 100 ms  */
+#define PLLSAI_TIMEOUT_VALUE    100 /* Timeout value fixed to 100 ms  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RCCEx_Private_Functions
+  * @{
+  */
+
+/** @defgroup RCCEx_Group1 Extended Peripheral Control functions 
+ *  @brief  Extended Peripheral Control functions  
+ *
+@verbatim   
+ ===============================================================================
+                ##### Extended Peripheral Control functions  #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks 
+    frequencies.
+    [..] 
+    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+        select the RTC clock source; in this case the Backup domain will be reset in  
+        order to modify the RTC Clock source, as consequence RTC registers (including 
+        the backup registers) and RCC_BDCR register are set to their reset values.
+      
+@endverbatim
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals
+  *         clocks(I2S, SAI, LTDC RTC and TIM).
+  *         
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select 
+  *         the RTC clock source; in this case the Backup domain will be reset in  
+  *         order to modify the RTC Clock source, as consequence RTC registers (including 
+  *         the backup registers) and RCC_BDCR register are set to their reset values.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t timeout = 0;
+  uint32_t tmpreg = 0;
+    
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+  
+  /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------------*/
+  
+  /*----------------------- Common configuration SAI/I2S ---------------------------*/
+  /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division   
+     factor is common parameters for both peripherals */ 
+  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || 
+     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
+  {
+    /* check for Parameters */
+    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+        
+    /* Disable the PLLI2S */
+    __HAL_RCC_PLLI2S_DISABLE();    
+    /* Get new Timeout value */
+    timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE;
+    /* Wait till PLLI2S is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* return in case of Timeout detected */         
+        return HAL_TIMEOUT;
+      }
+    }
+    
+    /*---------------------------- I2S configuration -------------------------------*/
+    /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added   
+      only for I2S configuration */     
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
+      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+  
+    /*---------------------------- SAI configuration -------------------------------*/ 
+    /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must  
+       be added only for SAI configuration */     
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
+    {
+      /* Check the PLLI2S division factors */
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
+      
+      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+      tmpreg = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+      /* Configure the PLLI2S division factors */      
+      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg);
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ 
+      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+    }
+    
+    /* Enable the PLLI2S */
+    __HAL_RCC_PLLI2S_ENABLE();
+    /* Get new Timeout value */
+    timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE;
+    /* Wait till PLLI2S is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* return in case of Timeout detected */         
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /*----------------------- SAI/LTDC Configuration (PLLSAI) -------------------------*/
+  
+  /*----------------------- Common configuration SAI/LTDC ---------------------------*/ 
+  /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division   
+     factor is common parameters for both peripherals */ 
+  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || 
+     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
+  {
+    /* Check the PLLSAI division factors */
+    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+ 
+    /* Disable PLLSAI Clock */
+    __HAL_RCC_PLLSAI_DISABLE(); 
+    /* Get new Timeout value */    
+    timeout = HAL_GetTick() + PLLSAI_TIMEOUT_VALUE;
+    /* Wait till PLLSAI is disabled */
+    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+    {
+      if(HAL_GetTick() >= timeout)
+      { 
+        /* return in case of Timeout detected */        
+        return HAL_TIMEOUT;
+      }
+    }
+    
+    /*---------------------------- SAI configuration -------------------------------*/
+    /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must  
+       be added only for SAI configuration */     
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
+    {
+      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
+      
+      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
+      tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
+      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg);
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ 
+      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
+    }
+    
+    /*---------------------------- LTDC configuration -------------------------------*/
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
+    {
+      assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
+      assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
+      
+      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
+      tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+      /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg, PeriphClkInit->PLLSAI.PLLSAIR);
+      /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ 
+      __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
+    }    
+    /* Enable PLLSAI Clock */
+    __HAL_RCC_PLLSAI_ENABLE();
+    /* Get new Timeout value */    
+    timeout = HAL_GetTick() + PLLSAI_TIMEOUT_VALUE;
+    /* Wait till PLLSAI is ready */
+    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+    {
+      if(HAL_GetTick() >= timeout)
+      { 
+        /* return in case of Timeout detected */        
+        return HAL_TIMEOUT;
+      }
+    }  
+  }
+
+   
+  /*---------------------------- RTC configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+  {
+    /* Enable Power Clock*/
+    __PWR_CLK_ENABLE();
+    
+    /* Enable write access to Backup domain */
+    PWR->CR |= PWR_CR_DBP;
+    
+    /* Wait for Backup domain Write protection disable */
+    timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE;
+    
+    while((PWR->CR & PWR_CR_DBP) == RESET)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        return HAL_TIMEOUT;
+      }      
+    }
+    
+    /* Reset the Backup domain only if the RTC Clock source selction is modified */ 
+    if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+    {
+      /* Store the content of BDCR register before the reset of Backup Domain */
+      tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+      /* Restore the Content of BDCR register */
+      RCC->BDCR = tmpreg;
+    }
+    
+    /* If LSE is selected as RTC clock source, wait for LSE reactivation */
+    if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
+    {
+      /* Get timeout */
+      timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
+      
+      /* Wait till LSE is ready */  
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          return HAL_TIMEOUT;
+        }      
+      }  
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 
+  }
+  
+  /*---------------------------- TIM configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+  {
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the RCC_OscInitStruct according to the internal 
+  * RCC configuration registers.
+  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that 
+  *         will be configured.
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tempreg;
+  
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
+  
+  /* Get the PLLI2S Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
+  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
+  /* Get the PLLSAI Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
+  PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
+  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); 
+  /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
+  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
+  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
+  PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
+  /* Get the RTC Clock configuration -----------------------------------------------*/
+  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+  
+  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE) 
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
+  *         RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
+  *         
+  * @note   A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case 
+  *         the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup 
+  *        domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
+  *              
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t timeout = 0;
+  uint32_t tmpreg = 0;
+    
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+  
+  /*---------------------------- I2S configuration -------------------------------*/      
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+  {
+    /* check for Parameters */
+    assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+      
+    /* Disable the PLLI2S */
+    __HAL_RCC_PLLI2S_DISABLE();    
+    /* Get new Timeout value */
+    timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE;
+    /* Wait till PLLI2S is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* return in case of Timeout detected */         
+        return HAL_TIMEOUT;
+      } 
+    }
+    /* Configure the PLLI2S division factors */
+    /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
+    /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+    __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
+    
+    /* Enable the PLLI2S */
+    __HAL_RCC_PLLI2S_ENABLE();
+    /* Get new Timeout value */
+    timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE;
+    /* Wait till PLLI2S is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* return in case of Timeout detected */         
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /*---------------------------- RTC configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+  {
+    /* Enable Power Clock*/
+    __PWR_CLK_ENABLE();
+    
+    /* Enable write access to Backup domain */
+    PWR->CR |= PWR_CR_DBP;
+    
+    /* Wait for Backup domain Write protection disable */
+    timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE;
+    
+    while((PWR->CR & PWR_CR_DBP) == RESET)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        return HAL_TIMEOUT;
+      }      
+    }
+        
+    /* Reset the Backup domain only if the RTC Clock source selction is modified */ 
+    if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+    {
+      /* Store the content of BDCR register before the reset of Backup Domain */
+      tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+      /* Restore the Content of BDCR register */
+      RCC->BDCR = tmpreg;
+    }
+      
+    /* If LSE is selected as RTC clock source, wait for LSE reactivation */
+    if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
+    {
+      /* Get timeout */
+      timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
+      
+      /* Wait till LSE is ready */  
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          return HAL_TIMEOUT;
+        }      
+      }  
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the RCC_OscInitStruct according to the internal 
+  * RCC configuration registers.
+  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that 
+  * will be configured.
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tempreg;
+  
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
+  
+  /* Get the PLLI2S Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
+  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+  
+  /* Get the RTC Clock configuration -----------------------------------------------*/
+  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+  
+}
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,875 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_rcc_ex.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of RCC HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RCC_EX_H
+#define __STM32F4xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCCEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/** 
+  * @brief  PLLI2S Clock structure definition  
+  */
+typedef struct
+{
+  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+                            This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI1 clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+}RCC_PLLI2SInitTypeDef;
+
+/** 
+  * @brief  PLLSAI Clock structure definition  
+  */
+typedef struct
+{
+  uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+                            This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ 
+                                 
+  uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI1 clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
+                              
+  uint32_t PLLSAIR;    /*!< specifies the division factor for LTDC clock
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+                            This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
+
+}RCC_PLLSAIInitTypeDef;
+/** 
+  * @brief  RCC extended clocks structure definition  
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters. 
+                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters. 
+                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
+
+  uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
+                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+
+  uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
+                                      This parameter will be used only when PLLSAI is selected as Clock Source SAI */
+
+  uint32_t PLLSAIDivR;           /*!< Specifies the PLLSAI division factor for LTDC clock.
+                                      This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection. 
+                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+  uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Prescalers Selection. 
+                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
+/** 
+  * @brief  PLLI2S Clock structure definition  
+  */
+typedef struct
+{
+  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+                            This parameter must be a number between Min_Data = 192 and Max_Data = 432
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+}RCC_PLLI2SInitTypeDef;
+
+ 
+/** 
+  * @brief  RCC extended clocks structure definition  
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters.
+                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection.
+                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Constants
+  * @{
+  */
+
+/** @defgroup RCCEx_Periph_Clock_Selection
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_SAI_PLLI2S      ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_SAI_PLLSAI      ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_LTDC            ((uint32_t)0x00000008)
+#define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000010)
+#define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000020)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE) 
+#define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000002)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
+
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_BitAddress_AliasRegion
+  * @brief RCC registers bit address in the alias region
+  * @{
+  */
+/* --- CR Register ---*/  
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 
+/* Alias word address of PLLSAION bit */
+#define PLLSAION_BitNumber        0x1C
+#define CR_PLLSAION_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
+
+/* --- DCKCFGR Register ---*/
+/* Alias word address of TIMPRE bit */
+#define RCC_DCKCFGR_OFFSET        (RCC_OFFSET + 0x8C)
+#define TIMPRE_BitNumber          0x18
+#define DCKCFGR_TIMPRE_BB         (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_PLLI2S_Clock_Source 
+  * @{
+  */ 
+#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_PLLSAI_Clock_Source 
+  * @{
+  */
+#define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))  
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_PLLSAI_DIVQ 
+  * @{
+  */    
+#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_PLLI2S_DIVQ 
+  * @{
+  */ 
+#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_PLLSAI_DIVR 
+  * @{
+  */
+#define RCC_PLLSAIDIVR_2                ((uint32_t)0x00000000)
+#define RCC_PLLSAIDIVR_4                ((uint32_t)0x00010000)
+#define RCC_PLLSAIDIVR_8                ((uint32_t)0x00020000)
+#define RCC_PLLSAIDIVR_16               ((uint32_t)0x00030000)
+#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
+                                         ((VALUE) == RCC_PLLSAIDIVR_4)  ||\
+                                         ((VALUE) == RCC_PLLSAIDIVR_8)  ||\
+                                         ((VALUE) == RCC_PLLSAIDIVR_16))
+
+/**
+  * @}
+  */
+   
+/** @defgroup RCCEx_SAI_BlockA_Clock_Source
+  * @{
+  */
+#define RCC_SAIACLKSOURCE_PLLSAI             ((uint32_t)0x00000000)
+#define RCC_SAIACLKSOURCE_PLLI2S             ((uint32_t)0x00100000)
+#define RCC_SAIACLKSOURCE_EXT                ((uint32_t)0x00200000)
+/**
+  * @}
+  */ 
+
+/** @defgroup RCCEx_SAI_BlockB_Clock_Source
+  * @{
+  */
+#define RCC_SAIBCLKSOURCE_PLLSAI             ((uint32_t)0x00000000)
+#define RCC_SAIBCLKSOURCE_PLLI2S             ((uint32_t)0x00400000)
+#define RCC_SAIBCLKSOURCE_EXT                ((uint32_t)0x00800000)
+/**
+  * @}
+  */ 
+
+/** @defgroup RCCEx_TIM_PRescaler_Selection
+  * @{
+  */
+#define RCC_TIMPRES_DESACTIVATED        ((uint8_t)0x00)
+#define RCC_TIMPRES_ACTIVATED           ((uint8_t)0x01)
+/**
+  * @}
+  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+     
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief  Enables or disables the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  */
+
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __GPIOI_CLK_ENABLE()      (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
+#define __GPIOF_CLK_ENABLE()      (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
+#define __GPIOG_CLK_ENABLE()      (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
+#define __ETHMAC_CLK_ENABLE()     (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
+#define __ETHMACTX_CLK_ENABLE()   (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
+#define __ETHMACRX_CLK_ENABLE()   (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
+#define __ETHMACPTP_CLK_ENABLE()  (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
+#define __USB_OTG_HS_CLK_ENABLE()      (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
+#define __USB_OTG_HS_ULPI_CLK_ENABLE()  (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
+
+#define __GPIOF_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __GPIOG_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __GPIOI_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
+#define __ETHMAC_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
+#define __ETHMACTX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
+#define __ETHMACRX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
+#define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
+#define __USB_OTG_HS_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
+#define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+#endif /* !(STM32F401xC && STM32F401xE) */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 
+#define __GPIOJ_CLK_ENABLE()      (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOJEN))
+#define __GPIOK_CLK_ENABLE()      (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOKEN))
+#define __DMA2D_CLK_ENABLE()      (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2DEN))
+
+#define __GPIOJ_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
+#define __GPIOK_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
+#define __DMA2D_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+/**
+  * @brief  Enable ETHERNET clock.
+  */
+#define __ETH_CLK_ENABLE()       do {                            \
+                                     __ETHMAC_CLK_ENABLE();      \
+                                     __ETHMACTX_CLK_ENABLE();    \
+                                     __ETHMACRX_CLK_ENABLE();    \
+                                    } while(0)
+
+/**
+  * @brief  Disable ETHERNET clock.
+  */
+#define __ETH_CLK_DISABLE()       do {                             \
+                                      __ETHMACTX_CLK_DISABLE();    \
+                                      __ETHMACRX_CLK_DISABLE();    \
+                                      __ETHMAC_CLK_DISABLE();      \
+                                     } while(0)
+#endif /* !(STM32F401xC && STM32F401xE) */
+ 
+/** @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)  
+#define __DCMI_CLK_ENABLE()   (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
+#define __DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+#endif /* !(STM32F401xC && STM32F401xE) */
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
+#define __CRYP_CLK_ENABLE()   (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
+#define __HASH_CLK_ENABLE()   (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
+
+#define __CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
+#define __HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
+
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+/** @brief  Enables or disables the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#define __FSMC_CLK_ENABLE()  (RCC->AHB3ENR |= (RCC_AHB3ENR_FSMCEN))
+#define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __FMC_CLK_ENABLE()   (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN))
+#define __FMC_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+
+/** @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __TIM6_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
+#define __TIM7_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
+#define __TIM12_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
+#define __TIM13_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
+#define __TIM14_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
+#define __WWDG_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
+#define __USART3_CLK_ENABLE()  (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
+#define __UART4_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
+#define __UART5_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
+#define __CAN1_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
+#define __CAN2_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
+#define __DAC_CLK_ENABLE()     (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
+
+#define __TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#define __DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+#endif /* !(STM32F401xC && STM32F401xE) */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __UART7_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_UART7EN))
+#define __UART8_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_UART8EN))
+
+#define __UART7_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
+#define __UART8_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+/** @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)  
+#define __TIM8_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
+#define __ADC2_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
+#define __ADC3_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
+
+#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#endif /* !(STM32F401xC && STM32F401xE) */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __SPI5_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
+#define __SPI6_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_SPI6EN))
+#define __SAI1_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_SAI1EN))
+#define __LTDC_CLK_ENABLE()  (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN))
+
+#define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+#define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
+#define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
+#define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief  Force or release AHB1 peripheral reset.
+  */  
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __GPIOI_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
+#define __ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
+#define __OTGHS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+
+#define __GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __GPIOI_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
+#define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
+#define __OTGHS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 
+#define __GPIOJ_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
+#define __GPIOK_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
+#define __DMA2D_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
+
+#define __GPIOJ_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
+#define __GPIOK_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
+#define __DMA2D_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+ 
+/** @brief  Force or release AHB2 peripheral reset.
+  */
+#if !defined(STM32F401xC) && !defined(STM32F401xE) 
+#define __DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+#define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx) 
+#define __CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
+#define __HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
+
+#define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
+#define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
+
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+/** @brief  Force or release AHB3 peripheral reset
+  */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#define __FSMC_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
+#define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 
+#define __FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
+#define __FMC_RELEASE_RESET()  (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+ 
+/** @brief  Force or release APB1 peripheral reset.
+  */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)  
+#define __TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+
+#define __TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#define __DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __UART7_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
+#define __UART8_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
+
+#define __UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
+#define __UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief  Force or release APB2 peripheral reset.
+  */
+#if !defined(STM32F401xC) && !defined(STM32F401xE) 
+#define __TIM8_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __SPI5_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#define __SPI6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
+#define __SAI1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
+#define __LTDC_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
+
+#define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+#define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
+#define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
+#define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+
+/** @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)  
+#define __GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
+#define __SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#define __ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
+#define __ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __OTGHS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __OTGHSULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+
+#define __GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
+#define __SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#define __ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
+#define __ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __OTGHS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __GPIOJ_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
+#define __GPIOK_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
+#define __SRAM3_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
+#define __DMA2D_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
+
+#define __GPIOJ_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
+#define __GPIOK_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
+#define __DMA2D_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx) 
+#define __CRYP_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#define __HASH_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+
+#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
+#define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
+
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+/** @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#define __FSMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
+#define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx) 
+#define __FMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)  
+#define __TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#define __UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#define __CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+
+#define __TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#define __UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#define __CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#define __DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __UART7_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
+#define __UART8_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
+
+#define __UART7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
+#define __UART8_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)  
+#define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
+#define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+
+#define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
+#define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
+#define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
+#define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
+
+#define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+#define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
+#define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
+#define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+                           
+/** @brief  Macro to configure the Timers clocks prescalers 
+  * @note   This feature is only available with STM32F429x/439x Devices.  
+  * @param  __PRESC__ : specifies the Timers clocks prescalers selection
+  *         This parameter can be one of the following values:
+  *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is 
+  *                 equal to HPRE if PPREx is corresponding to division by 1 or 2, 
+  *                 else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to 
+  *                 division by 4 or more.       
+  *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is 
+  *                 equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, 
+  *                 else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding 
+  *                 to division by 8 or more.
+  */     
+#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) DCKCFGR_TIMPRE_BB = (__PRESC__))
+
+/** @brief Macros to Enable or Disable the PLLISAI. 
+  * @note  The PLLSAI is only available with STM32F429x/439x Devices.     
+  * @note  The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. 
+  */
+#define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = ENABLE)
+#define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = DISABLE)
+
+/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
+  * @note   The PLLSAI is only available with STM32F429x/439x Devices.     
+  * @note   This function must be used only when the PLLSAI is disabled.
+  * @note   PLLSAI clock source is common with the main PLL (configured in 
+  *         RCC_PLLConfig function )
+  * @param  __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
+  *         This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+  * @param  __PLLSAIQ__: specifies the division factor for SAI1 clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  * @param  __PLLSAIR__: specifies the division factor for LTDC clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  */   
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
+
+/** @brief  Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
+  * @note   This macro must be used only when the PLLI2S is disabled.
+  * @note   PLLI2S clock source is common with the main PLL (configured in 
+  *         HAL_RCC_ClockConfig() API)             
+  * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
+  *         This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+  * @param  __PLLI2SQ__: specifies the division factor for SAI1 clock.
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
+  * @note   the PLLI2SQ parameter is only available with STM32F429x/439x Devices
+  *         and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
+  * @param  __PLLI2SR__: specifies the division factor for I2S clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+  *         on the I2S clock frequency.
+  */
+#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
+    
+/** @brief  Macro to configure the SAI clock Divider coming from PLLI2S.
+  * @note   The SAI peripheral is only available with STM32F429x/439x Devices.    
+  * @note   This function must be called before enabling the PLLI2S.          
+  * @param  __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
+  *          This parameter must be a number between 1 and 32.
+  *          SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ 
+  */
+#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
+
+/** @brief  Macro to configure the SAI clock Divider coming from PLLSAI.
+  * @note   The SAI peripheral is only available with STM32F429x/439x Devices.
+  * @note   This function must be called before enabling the PLLSAI.
+  * @param  __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
+  *         This parameter must be a number between Min_Data = 1 and Max_Data = 32.
+  *         SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__  
+  */
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
+
+/** @brief  Macro to configure the LTDC clock Divider coming from PLLSAI.
+  * 
+  * @note   The LTDC peripheral is only available with STM32F429x/439x Devices.   
+  * @note   This function must be called before enabling the PLLSAI. 
+  * @param  __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
+  *          This parameter must be a number between Min_Data = 2 and Max_Data = 16.
+  *          LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ 
+  */   
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
+
+/** @brief  Macro to configure SAI1BlockA clock source selection.
+  * @note   The SAI peripheral is only available with STM32F429x/439x Devices.      
+  * @note   This function must be called before enabling PLLSAI, PLLI2S and  
+  *         the SAI clock.
+  * @param  __SOURCE__: specifies the SAI Block A clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 
+  *                                           as SAI1 Block A clock. 
+  *            @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 
+  *                                           as SAI1 Block A clock.
+  *            @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
+  *                                        used as SAI1 Block A clock.
+  */
+#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
+
+/** @brief  Macro to configure SAI1BlockB clock source selection.
+  * @note   The SAI peripheral is only available with STM32F429x/439x Devices.      
+  * @note   This function must be called before enabling PLLSAI, PLLI2S and  
+  *         the SAI clock.
+  * @param  __SOURCE__: specifies the SAI Block B clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 
+  *                                           as SAI1 Block B clock. 
+  *            @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 
+  *                                           as SAI1 Block B clock. 
+  *            @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
+  *                                        used as SAI1 Block B clock.
+  */
+#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
+
+/** @brief Enable PLLSAI_RDY interrupt.
+  */
+#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
+
+/** @brief Disable PLLSAI_RDY interrupt.
+  */
+#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
+
+/** @brief Clear the PLLSAI RDY interrupt pending bits.
+  */
+#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
+
+/** @brief Check the PLLSAI RDY interrupt has occurred or not.
+  * @retval The new state (TRUE or FALSE).
+  */
+#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
+
+/** @brief  Check PLLSAI RDY flag is set or not.
+  * @retval The new state (TRUE or FALSE).
+  */
+#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/* Exported functions --------------------------------------------------------*/
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RCC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rng.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,427 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_rng.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   RNG HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Random Number Generator (RNG) peripheral:
+  *           + Initialization/de-initialization functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The RNG HAL driver can be used as follows:
+
+         (#) Enable the RNG controller clock using __RNG_CLK_ENABLE() macro.
+         (#) Activate the RNG peripheral using __HAL_RNG_ENABLE() macro.
+         (#) Wait until the 32 bit Random Number Generator contains a valid 
+             random data using (polling/interrupt) mode.   
+         (#) Get the 32 bit random number using HAL_RNG_GetRandomNumber() function.
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RNG 
+  * @brief RNG HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define RNG_TIMEOUT_VALUE     1000
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RNG_Private_Functions
+  * @{
+  */
+
+/** @defgroup RNG_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions. 
+ *
+@verbatim    
+ ===============================================================================
+          ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the RNG according to the specified parameters 
+          in the RNG_InitTypeDef and create the associated handle
+      (+) DeInitialize the RNG peripheral
+      (+) Initialize the RNG MSP
+      (+) DeInitialize RNG MSP 
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the RNG according to the specified
+  *         parameters in the RNG_InitTypeDef and creates the associated handle.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
+{ 
+  /* Check the RNG handle allocation */
+  if(hrng == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(hrng->State == HAL_RNG_STATE_RESET)
+  {  
+    /* Init the low level hardware */
+    HAL_RNG_MspInit(hrng);
+  }
+  /* Change RNG peripheral state */
+  hrng->State = HAL_RNG_STATE_BUSY;
+
+  /* Enable the RNG Peripheral */
+  __HAL_RNG_ENABLE(hrng);
+
+  /* Initialize the RNG state */
+  hrng->State = HAL_RNG_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the RNG peripheral. 
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
+{ 
+  /* Check the RNG peripheral state */
+  if(hrng->State == HAL_RNG_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  
+  /* Update the RNG state */  
+  hrng->State = HAL_RNG_STATE_BUSY;
+  
+  /* Disable the RNG Peripheral */
+  __HAL_RNG_DISABLE(hrng);
+  
+  /* Set the RNG registers to their reset values */
+  hrng->Instance->CR &= 0xFFFFFFF3;
+  hrng->Instance->SR &= 0xFFFFFF98;
+  hrng->Instance->DR &= 0x0;
+  
+  /* DeInit the low level hardware */
+  HAL_RNG_MspDeInit(hrng);
+  
+  /* Update the RNG state */
+  hrng->State = HAL_RNG_STATE_RESET; 
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrng);
+  
+  /* Return the function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the RNG MSP.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval None
+  */
+__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RNG_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the RNG MSP.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval None
+  */
+__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RNG_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RNG_Group2 Peripheral Control functions 
+ *  @brief    management functions. 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Get the 32 bit Random number
+      (+) Get the 32 bit Random number with interrupt enabled
+      (+) Handle RNG interrupt request 
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns a 32-bit random number.
+  * @note   Each time the random number data is read the RNG_FLAG_DRDY flag 
+  *         is automatically cleared.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval 32-bit random number
+  */
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
+{
+  uint32_t random32bit = 0;
+  uint32_t timeout = 0;   
+  
+  /* Process Locked */
+  __HAL_LOCK(hrng); 
+  
+  timeout = HAL_GetTick() + RNG_TIMEOUT_VALUE;
+  
+  /* Check if data register contains valid random data */
+  while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+  {
+    if(HAL_GetTick() >= timeout)
+    {    
+      return HAL_TIMEOUT;
+    } 
+  }
+  
+  /* Get a 32bit Random number */ 
+  random32bit = hrng->Instance->DR;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrng);
+  
+  /* Return the 32 bit random number */   
+  return random32bit;
+}
+
+/**
+  * @brief  Returns a 32-bit random number with interrupt enabled.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval 32-bit random number
+  */
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
+{
+  uint32_t random32bit = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hrng);
+  
+  /* Change RNG peripheral state */  
+  hrng->State = HAL_RNG_STATE_BUSY;  
+  
+  /* Get a 32bit Random number */ 
+  random32bit = hrng->Instance->DR;
+  
+  /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ 
+  __HAL_RNG_ENABLE_IT(hrng); 
+  
+  /* Return the 32 bit random number */   
+  return random32bit;
+}
+
+/**
+  * @brief  Handles RNG interrupt request.
+  * @note   In the case of a clock error, the RNG is no more able to generate 
+  *         random numbers because the PLL48CLK clock is not correct. User has 
+  *         to check that the clock controller is correctly configured to provide
+  *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_FLAG(). 
+  *         The clock error has no impact on the previously generated 
+  *         random numbers, and the RNG_DR register contents can be used.
+  * @note   In the case of a seed error, the generation of random numbers is 
+  *         interrupted as long as the SECS bit is '1'. If a number is 
+  *         available in the RNG_DR register, it must not be used because it may 
+  *         not have enough entropy. In this case, it is recommended to clear the 
+  *         SEIS bit using __HAL_RNG_CLEAR_FLAG(), then disable and enable 
+  *         the RNG peripheral to reinitialize and restart the RNG.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval None
+
+  */
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
+{
+  /* RNG clock error interrupt occurred */
+  if(__HAL_RNG_GET_FLAG(hrng, RNG_IT_CEI) != RESET)
+  { 
+    HAL_RNG_ErrorCallback(hrng);
+    
+    /* Clear the clock error flag */
+    __HAL_RNG_CLEAR_FLAG(hrng, RNG_IT_CEI);
+    
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_ERROR;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hrng);
+  }
+  
+  /* RNG seed error interrupt occurred */
+  if(__HAL_RNG_GET_FLAG(hrng, RNG_IT_SEI) != RESET)
+  { 
+    HAL_RNG_ErrorCallback(hrng);
+    
+    /* Clear the seed error flag */
+    __HAL_RNG_CLEAR_FLAG(hrng, RNG_IT_SEI);
+    
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_ERROR;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hrng);    
+  }
+  
+  /* Check RNG data ready flag */    
+  if(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != RESET)
+  {
+    /* Data Ready callback */ 
+    HAL_RNG_ReadyCallback(hrng);
+    
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_READY; 
+      
+    /* Clear the RNG Data Ready flag */
+    __HAL_RNG_CLEAR_FLAG(hrng, RNG_FLAG_DRDY);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hrng);
+  }
+} 
+
+/**
+  * @brief  Data Ready callback in non-blocking mode. 
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval None
+  */
+
+__weak void HAL_RNG_ReadyCallback(RNG_HandleTypeDef* hrng)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RNG_ReadyCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RNG error callbacks.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval None
+  */
+__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RNG_ErrorCallback could be implemented in the user file
+   */ 
+}
+ 
+/**
+  * @}
+  */
+
+/** @defgroup RNG_Group3 Peripheral State functions 
+ *  @brief    Peripheral State functions. 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the RNG state.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval HAL state
+  */
+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
+{
+  return hrng->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RNG_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+                  
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rng.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,219 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_rng.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of RNG HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RNG_H
+#define __STM32F4xx_HAL_RNG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RNG
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** 
+  * @brief  RNG HAL State Structure definition  
+  */ 
+typedef enum
+{
+  HAL_RNG_STATE_RESET     = 0x00,  /*!< RNG not yet initialized or disabled */
+  HAL_RNG_STATE_READY     = 0x01,  /*!< RNG initialized and ready for use   */
+  HAL_RNG_STATE_BUSY      = 0x02,  /*!< RNG internal process is ongoing     */ 
+  HAL_RNG_STATE_TIMEOUT   = 0x03,  /*!< RNG timeout state                   */
+  HAL_RNG_STATE_ERROR     = 0x04   /*!< RNG error state                     */
+    
+}HAL_RNG_StateTypeDef;
+
+/** 
+  * @brief  RNG Handle Structure definition  
+  */ 
+typedef struct
+{
+  RNG_TypeDef                 *Instance;  /*!< Register base address   */ 
+  
+  HAL_LockTypeDef             Lock;       /*!< RNG locking object      */
+  
+  __IO HAL_RNG_StateTypeDef   State;      /*!< RNG communication state */
+  
+}RNG_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RNG_Exported_Constants
+  * @{
+  */
+
+/** @defgroup RNG_Interrupt_definition 
+  * @{
+  */ 
+#define RNG_IT_CEI   ((uint32_t)0x20)  /*!< Clock error interrupt */
+#define RNG_IT_SEI   ((uint32_t)0x40)  /*!< Seed error interrupt  */
+
+#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
+                       ((IT) == RNG_IT_SEI))
+/**
+  * @}
+  */
+
+
+/** @defgroup RNG_Flag_definition 
+  * @{
+  */ 
+#define RNG_FLAG_DRDY   ((uint32_t)0x0001)  /*!< Data ready                 */
+#define RNG_FLAG_CECS   ((uint32_t)0x0002)  /*!< Clock error current status */
+#define RNG_FLAG_SECS   ((uint32_t)0x0004)  /*!< Seed error current status  */
+
+#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
+                           ((FLAG) == RNG_FLAG_CECS) || \
+                           ((FLAG) == RNG_FLAG_SECS))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset RNG handle state
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
+
+/**
+  * @brief  Enables the RNG peripheral.
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
+
+/**
+  * @brief  Disables the RNG peripheral.
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
+
+/**
+  * @brief  Gets the selected RNG's flag status.
+  * @param  __HANDLE__: RNG Handle
+  * @param  __FLAG__: RNG flag
+  * @retval The new state of RNG_FLAG (SET or RESET).
+  */
+#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clears the RNG's pending flags.
+  * @param  __HANDLE__: RNG Handle
+  * @param  __FLAG__: RNG flag
+  * @retval None
+  */
+#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) &= ~(__FLAG__))
+    
+/**
+  * @brief  Enables the RNG interrupts.
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
+    
+/**
+  * @brief  Disables the RNG interrupts.
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
+
+/**
+  * @brief  Checks whether the specified RNG interrupt has occurred or not.
+  * @param  __HANDLE__: RNG Handle
+  * @param  __INTERRUPT__: specifies the RNG interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg RNG_FLAG_DRDY: Data ready interrupt
+  *            @arg RNG_FLAG_CECS: Clock error interrupt
+  *            @arg RNG_FLAG_SECS: Seed error interrupt
+  * @retval The new state of RNG_FLAG (SET or RESET).
+  */
+#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))   
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
+HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
+void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
+void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
+
+/* Peripheral Control functions  ************************************************/
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng);
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
+void HAL_RNG_ReadyCallback(RNG_HandleTypeDef* hrng);
+void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
+
+/* Peripheral State functions  **************************************************/
+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RNG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1516 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_rtc.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   RTC HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Real Time Clock (RTC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + RTC Time and Date functions
+  *           + RTC Alarm functions
+  *           + Peripheral Control functions   
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+              ##### Backup Domain Operating Condition #####
+  ==============================================================================
+  [..] The real-time clock (RTC), the RTC backup registers, and the backup 
+       SRAM (BKP SRAM) can be powered from the VBAT voltage when the main 
+       VDD supply is powered off.
+       To retain the content of the RTC backup registers, backup SRAM, and supply 
+       the RTC when VDD is turned off, VBAT pin can be connected to an optional 
+       standby voltage supplied by a battery or by another source.
+
+  [..] To allow the RTC operating even when the main digital supply (VDD) is turned
+       off, the VBAT pin powers the following blocks:
+    (#) The RTC
+    (#) The LSE oscillator
+    (#) The backup SRAM when the low power backup regulator is enabled
+    (#) PC13 to PC15 I/Os, plus PI8 I/O (when available)
+  
+  [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
+       the following pins are available:
+    (#) PC14 and PC15 can be used as either GPIO or LSE pins
+    (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
+    (#) PI8 can be used as a GPIO or as the RTC_AF2 pin
+  
+  [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT 
+       because VDD is not present), the following pins are available:
+    (#) PC14 and PC15 can be used as LSE pins only
+    (#) PC13 can be used as the RTC_AF1 pin 
+    (#) PI8 can be used as the RTC_AF2 pin
+             
+                   ##### Backup Domain Reset #####
+  ==================================================================
+  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register 
+       to their reset values. The BKPSRAM is not affected by this reset. The only
+       way to reset the BKPSRAM is through the Flash interface by requesting 
+       a protection level change from 1 to 0.
+  [..] A backup domain reset is generated when one of the following events occurs:
+    (#) Software reset, triggered by setting the BDRST bit in the 
+        RCC Backup domain control register (RCC_BDCR). 
+    (#) VDD or VBAT power on, if both supplies have previously been powered off.  
+
+                   ##### Backup Domain Access #####
+  ==================================================================
+  [..] After reset, the backup domain (RTC registers, RTC backup data 
+       registers and backup SRAM) is protected against possible unwanted write 
+       accesses. 
+  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
+    (+) Enable the Power Controller (PWR) APB1 interface clock using the
+        __PWR_CLK_ENABLE() function.
+    (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+    (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
+    (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
+  
+  
+                  ##### How to use this driver #####
+  ==================================================================
+  [..] 
+    (+) Enable the RTC domain access (see description in the section above).
+    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour 
+        format using the HAL_RTC_Init() function.
+  
+  *** Time and Date configuration ***
+  ===================================
+  [..] 
+    (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() 
+        and HAL_RTC_SetDate() functions.
+    (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. 
+  
+  *** Alarm configuration ***
+  ===========================
+  [..]
+    (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. 
+        You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
+    (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
+  
+                  ##### RTC and low power modes #####
+  ==================================================================
+  [..] The MCU can be woken up from a low power mode by an RTC alternate 
+       function.
+  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), 
+       RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
+       These RTC alternate functions can wake up the system from the Stop and 
+       Standby low power modes.
+  [..] The system can also wake up from low power modes without depending 
+       on an external interrupt (Auto-wakeup mode), by using the RTC alarm 
+       or the RTC wakeup events.
+  [..] The RTC provides a programmable time base for waking up from the 
+       Stop or Standby mode at regular intervals.
+       Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
+       is LSE or LSI.
+     
+   @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RTC 
+  * @brief RTC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RTC_Private_Functions
+  * @{
+  */
+  
+/** @defgroup RTC_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+   [..] This section provides functions allowing to initialize and configure the 
+         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable 
+         RTC registers Write protection, enter and exit the RTC initialization mode, 
+         RTC registers synchronization check and reference clock detection enable.
+         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. 
+             It is split into 2 programmable prescalers to minimize power consumption.
+             (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.
+             (++) When both prescalers are used, it is recommended to configure the 
+                 asynchronous prescaler to a high value to minimize power consumption.
+         (#) All RTC registers are Write protected. Writing to the RTC registers
+             is enabled by writing a key into the Write Protection register, RTC_WPR.
+         (#) To configure the RTC Calendar, user application should enter 
+             initialization mode. In this mode, the calendar counter is stopped 
+             and its value can be updated. When the initialization sequence is 
+             complete, the calendar restarts counting after 4 RTCCLK cycles.
+         (#) To read the calendar through the shadow registers after Calendar 
+             initialization, calendar update or after wakeup from low power modes 
+             the software must first clear the RSF flag. The software must then 
+             wait until it is set again before reading the calendar, which means 
+             that the calendar registers have been correctly copied into the 
+             RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function 
+             implements the above software sequence (RSF clear and RSF check).
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the RTC peripheral 
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
+{
+  /* Check the RTC peripheral state */
+  if(hrtc == NULL)
+  {
+     return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
+  assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
+  assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
+  assert_param (IS_RTC_OUTPUT(hrtc->Init.OutPut));
+  assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
+  assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
+    
+  if(hrtc->State == HAL_RTC_STATE_RESET)
+  {
+    /* Initialize RTC MSP */
+    HAL_RTC_MspInit(hrtc);
+  }
+  
+  /* Set RTC state */  
+  hrtc->State = HAL_RTC_STATE_BUSY;  
+       
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Set Initialization mode */
+  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  {
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
+    
+    /* Set RTC state */
+    hrtc->State = HAL_RTC_STATE_ERROR;
+    
+    return HAL_ERROR;
+  } 
+  else
+  { 
+    /* Clear RTC_CR FMT, OSEL and POL Bits */
+    hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
+    /* Set RTC_CR register */
+    hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
+    
+    /* Configure the RTC PRER */
+    hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
+    hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);
+    
+    /* Exit Initialization mode */
+    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
+    
+    hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
+    hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); 
+    
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
+    
+    /* Set RTC state */
+    hrtc->State = HAL_RTC_STATE_READY;
+    
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  DeInitializes the RTC peripheral 
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @note   This function doesn't reset the RTC Backup Data registers.   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
+{
+  uint32_t timeout = 0;
+
+  /* Set RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY; 
+  
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  /* Set Initialization mode */
+  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  {
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
+    
+    /* Set RTC state */
+    hrtc->State = HAL_RTC_STATE_ERROR;
+    
+    return HAL_ERROR;
+  }  
+  else
+  {
+    /* Reset TR, DR and CR registers */
+    hrtc->Instance->TR = (uint32_t)0x00000000;
+    hrtc->Instance->DR = (uint32_t)0x00002101;
+    /* Reset All CR bits except CR[2:0] */
+    hrtc->Instance->CR &= (uint32_t)0x00000007;
+       
+    timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+    
+    /* Wait till WUTWF flag is set and if Time out is reached exit */
+    while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
+    {
+      if(HAL_GetTick() >= timeout)
+      { 
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
+        
+        /* Set RTC state */
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        
+        return HAL_TIMEOUT;
+      }      
+    }
+    
+    /* Reset all RTC CR register bits */
+    hrtc->Instance->CR &= (uint32_t)0x00000000;
+    hrtc->Instance->WUTR = (uint32_t)0x0000FFFF;
+    hrtc->Instance->PRER = (uint32_t)0x007F00FF;
+    hrtc->Instance->CALIBR = (uint32_t)0x00000000;
+    hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
+    hrtc->Instance->ALRMBR = (uint32_t)0x00000000;
+    hrtc->Instance->SHIFTR = (uint32_t)0x00000000;
+    hrtc->Instance->CALR = (uint32_t)0x00000000;
+    hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;
+    hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;
+    
+    /* Reset ISR register and exit initialization mode */
+    hrtc->Instance->ISR = (uint32_t)0x00000000;
+    
+    /* Reset Tamper and alternate functions configuration register */
+    hrtc->Instance->TAFCR = 0x00000000;
+    
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+    {
+      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
+        
+        hrtc->State = HAL_RTC_STATE_ERROR;
+        
+        return HAL_ERROR;
+      }
+    }    
+  }
+  
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+  
+  /* De-Initialize RTC MSP */
+  HAL_RTC_MspDeInit(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_RESET; 
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the RTC MSP.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.  
+  * @retval None
+  */
+__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RTC_MspInit could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @brief  DeInitializes the RTC MSP.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC. 
+  * @retval None
+  */
+__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RTC_MspDeInit could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group2 RTC Time and Date functions
+ *  @brief   RTC Time and Date functions
+ *
+@verbatim   
+ ===============================================================================
+                 ##### RTC Time and Date functions #####
+ ===============================================================================  
+ 
+ [..] This section provides functions allowing to configure Time and Date features
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets RTC current time.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  sTime: Pointer to Time structure
+  * @param  Format: Specifies the format of the entered parameters.
+  *          This parameter can be one of the following values:
+  *            @arg FORMAT_BIN: Binary data format 
+  *            @arg FORMAT_BCD: BCD data format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+  uint32_t tmpreg = 0;
+  
+ /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+  assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
+  assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
+  
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  if(Format == FORMAT_BIN)
+  {
+    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      assert_param(IS_RTC_HOUR12(sTime->Hours));
+      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+    } 
+    else
+    {
+      sTime->TimeFormat = 0x00;
+      assert_param(IS_RTC_HOUR24(sTime->Hours));
+    }
+    assert_param(IS_RTC_MINUTES(sTime->Minutes));
+    assert_param(IS_RTC_SECONDS(sTime->Seconds));
+    
+    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
+                        ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
+                        ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
+                        (((uint32_t)sTime->TimeFormat) << 16));  
+  }
+  else
+  {
+    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      tmpreg = RTC_Bcd2ToByte(sTime->Hours);
+      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); 
+    } 
+    else
+    {
+      sTime->TimeFormat = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
+    tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
+              ((uint32_t)(sTime->Minutes) << 8) | \
+              ((uint32_t)sTime->Seconds) | \
+              ((uint32_t)(sTime->TimeFormat) << 16));   
+  }
+  
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  /* Set Initialization mode */
+  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  {
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
+    
+    /* Set RTC state */
+    hrtc->State = HAL_RTC_STATE_ERROR;
+    
+    /* Process Unlocked */ 
+    __HAL_UNLOCK(hrtc);
+    
+    return HAL_ERROR;
+  } 
+  else
+  {
+    /* Set the RTC_TR register */
+    hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
+     
+    /* Clear the bits to be configured */
+    hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;
+    
+    /* Configure the RTC_CR register */
+    hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
+    
+    /* Exit Initialization mode */
+    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;  
+    
+    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+    {
+      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+      {        
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
+        
+        hrtc->State = HAL_RTC_STATE_ERROR;
+        
+        /* Process Unlocked */ 
+        __HAL_UNLOCK(hrtc);
+        
+        return HAL_ERROR;
+      }
+    }
+    
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+    
+   hrtc->State = HAL_RTC_STATE_READY;
+  
+   __HAL_UNLOCK(hrtc); 
+     
+   return HAL_OK;
+  }
+}
+
+/**
+  * @brief  Gets RTC current time.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  sTime: Pointer to Time structure
+  * @param  Format: Specifies the format of the entered parameters.
+  *          This parameter can be one of the following values:
+  *            @arg FORMAT_BIN: Binary data format 
+  *            @arg FORMAT_BCD: BCD data format
+  * @note   Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values 
+  *         in the higher-order calendar shadow registers.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+  
+  /* Get subseconds values from the correspondent registers*/
+  sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
+
+  /* Get the TR register */
+  tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); 
+  
+  /* Fill the structure fields with the read parameters */
+  sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+  sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
+  sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
+  sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); 
+  
+  /* Check the input parameters format */
+  if(Format == FORMAT_BIN)
+  {
+    /* Convert the time structure parameters to Binary format */
+    sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
+    sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
+    sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);  
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Sets RTC current date.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  sDate: Pointer to date structure
+  * @param  Format: specifies the format of the entered parameters.
+  *          This parameter can be one of the following values:
+  *            @arg FORMAT_BIN: Binary data format 
+  *            @arg FORMAT_BCD: BCD data format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+  uint32_t datetmpreg = 0;
+  
+ /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+  
+ /* Process Locked */ 
+ __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY; 
+  
+  if((Format == FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
+  {
+    sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A);
+  }
+  
+  assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
+  
+  if(Format == FORMAT_BIN)
+  {   
+    assert_param(IS_RTC_YEAR(sDate->Year));
+    assert_param(IS_RTC_MONTH(sDate->Month));
+    assert_param(IS_RTC_DATE(sDate->Date)); 
+    
+   datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
+                 ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
+                 ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
+                 ((uint32_t)sDate->WeekDay << 13));   
+  }
+  else
+  {   
+    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
+    datetmpreg = RTC_Bcd2ToByte(sDate->Month);
+    assert_param(IS_RTC_MONTH(datetmpreg));
+    datetmpreg = RTC_Bcd2ToByte(sDate->Date);
+    assert_param(IS_RTC_DATE(datetmpreg));
+    
+    datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
+                  (((uint32_t)sDate->Month) << 8) | \
+                  ((uint32_t)sDate->Date) | \
+                  (((uint32_t)sDate->WeekDay) << 13));  
+  }
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  /* Set Initialization mode */
+  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  {
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
+    
+    /* Set RTC state*/
+    hrtc->State = HAL_RTC_STATE_ERROR;
+    
+    /* Process Unlocked */ 
+    __HAL_UNLOCK(hrtc);
+    
+    return HAL_ERROR;
+  } 
+  else
+  {
+    /* Set the RTC_DR register */
+    hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
+    
+    /* Exit Initialization mode */
+    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;  
+    
+    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+    {
+      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+      { 
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
+        
+        hrtc->State = HAL_RTC_STATE_ERROR;
+        
+        /* Process Unlocked */ 
+        __HAL_UNLOCK(hrtc);
+        
+        return HAL_ERROR;
+      }
+    }
+    
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
+    
+    hrtc->State = HAL_RTC_STATE_READY ;
+    
+    /* Process Unlocked */ 
+    __HAL_UNLOCK(hrtc);
+    
+    return HAL_OK;    
+  }
+}
+
+/**
+  * @brief  Gets RTC current date.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  sDate: Pointer to Date structure
+  * @param  Format: Specifies the format of the entered parameters.
+  *          This parameter can be one of the following values:
+  *            @arg FORMAT_BIN:  Binary data format 
+  *            @arg FORMAT_BCD:  BCD data format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+  uint32_t datetmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+          
+  /* Get the DR register */
+  datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); 
+
+  /* Fill the structure fields with the read parameters */
+  sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
+  sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+  sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
+  sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); 
+
+  /* Check the input parameters format */
+  if(Format == FORMAT_BIN)
+  {    
+    /* Convert the date structure parameters to Binary format */
+    sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
+    sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
+    sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);  
+  }
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group3 RTC Alarm functions
+ *  @brief   RTC Alarm functions
+ *
+@verbatim   
+ ===============================================================================
+                 ##### RTC Alarm functions #####
+ ===============================================================================  
+ 
+ [..] This section provides functions allowing to configure Alarm feature
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Sets the specified RTC Alarm.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  sAlarm: Pointer to Alarm structure
+  * @param  Format: Specifies the format of the entered parameters.
+  *          This parameter can be one of the following values:
+  *             @arg FORMAT_BIN: Binary data format 
+  *             @arg FORMAT_BCD: BCD data format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+  uint32_t timeout = 0;
+  uint32_t tmpreg = 0, subsecondtmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+  assert_param(IS_ALARM(sAlarm->Alarm));
+  assert_param(IS_ALARM_MASK(sAlarm->AlarmMask));
+  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+  
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  if(Format == FORMAT_BIN)
+  {
+    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+    } 
+    else
+    {
+      sAlarm->AlarmTime.TimeFormat = 0x00;
+      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+    }
+    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+    
+    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+    }
+    
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
+              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
+              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
+              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+              ((uint32_t)sAlarm->AlarmMask)); 
+  }
+  else
+  {
+    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+    } 
+    else
+    {
+      sAlarm->AlarmTime.TimeFormat = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+    }
+    
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+    
+    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+    {
+      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    
+    }
+    else
+    {
+      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      
+    }  
+    
+    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
+              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
+              ((uint32_t) sAlarm->AlarmTime.Seconds) | \
+              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
+              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
+              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+              ((uint32_t)sAlarm->AlarmMask));   
+  }
+  
+  /* Configure the Alarm A or Alarm B Sub Second registers */
+  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
+  
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Configure the Alarm register */
+  if(sAlarm->Alarm == RTC_ALARM_A)
+  {
+    /* Disable the Alarm A interrupt */
+    __HAL_RTC_ALARMA_DISABLE(hrtc);
+    
+    /* In case of interrupt mode is used, the interrupt source must disabled */ 
+    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+         
+    timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
+    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+        
+        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
+        
+        /* Process Unlocked */ 
+        __HAL_UNLOCK(hrtc);
+        
+        return HAL_TIMEOUT;
+      }   
+    }
+    
+    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
+    /* Configure the Alarm A Sub Second register */
+    hrtc->Instance->ALRMASSR = subsecondtmpreg;
+    /* Configure the Alarm state: Enable Alarm */
+    __HAL_RTC_ALARMA_ENABLE(hrtc);
+  }
+  else
+  {
+    /* Disable the Alarm B interrupt */
+    __HAL_RTC_ALARMB_DISABLE(hrtc);
+    
+    /* In case of interrupt mode is used, the interrupt source must disabled */ 
+    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
+       
+    timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
+    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+        
+        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
+        
+        /* Process Unlocked */ 
+        __HAL_UNLOCK(hrtc);
+        
+        return HAL_TIMEOUT;
+      }  
+    }    
+    
+    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
+    /* Configure the Alarm B Sub Second register */
+    hrtc->Instance->ALRMBSSR = subsecondtmpreg;
+    /* Configure the Alarm state: Enable Alarm */
+    __HAL_RTC_ALARMB_ENABLE(hrtc); 
+  }
+  
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);   
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Sets the specified RTC Alarm with Interrupt 
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  sAlarm: Pointer to Alarm structure
+  * @param  Format: Specifies the format of the entered parameters.
+  *          This parameter can be one of the following values:
+  *             @arg FORMAT_BIN: Binary data format 
+  *             @arg FORMAT_BCD: BCD data format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+  uint32_t timeout = 0;
+  uint32_t tmpreg = 0, subsecondtmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+  assert_param(IS_ALARM(sAlarm->Alarm));
+  assert_param(IS_ALARM_MASK(sAlarm->AlarmMask));
+  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+      
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  if(Format == FORMAT_BIN)
+  {
+    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+    } 
+    else
+    {
+      sAlarm->AlarmTime.TimeFormat = 0x00;
+      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+    }
+    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+    
+    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+    }
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
+              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
+              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
+              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+              ((uint32_t)sAlarm->AlarmMask)); 
+  }
+  else
+  {
+    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+    } 
+    else
+    {
+      sAlarm->AlarmTime.TimeFormat = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+    }
+    
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+    
+    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+    {
+      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    
+    }
+    else
+    {
+      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      
+    }
+    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
+              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
+              ((uint32_t) sAlarm->AlarmTime.Seconds) | \
+              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
+              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
+              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+              ((uint32_t)sAlarm->AlarmMask));     
+  }
+  /* Configure the Alarm A or Alarm B Sub Second registers */
+  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
+  
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  /* Configure the Alarm register */
+  if(sAlarm->Alarm == RTC_ALARM_A)
+  {
+    /* Disable the Alarm A interrupt */
+    __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+    /* Clear flag alarm A */
+    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+    timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
+    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+        
+        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
+        
+        /* Process Unlocked */ 
+        __HAL_UNLOCK(hrtc);
+        
+        return HAL_TIMEOUT;
+      }  
+    }
+    
+    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
+    /* Configure the Alarm A Sub Second register */
+    hrtc->Instance->ALRMASSR = subsecondtmpreg;
+    /* Configure the Alarm state: Enable Alarm */
+    __HAL_RTC_ALARMA_ENABLE(hrtc);
+    /* Configure the Alarm interrupt */
+    __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
+  }
+  else
+  {
+    /* Disable the Alarm B interrupt */
+    __HAL_RTC_ALARMB_DISABLE(hrtc);
+
+    /* Clear flag alarm B */
+    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
+
+    timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
+    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+        
+        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
+        
+        /* Process Unlocked */ 
+        __HAL_UNLOCK(hrtc);
+        
+        return HAL_TIMEOUT;
+      }  
+    }
+
+    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
+    /* Configure the Alarm B Sub Second register */
+    hrtc->Instance->ALRMBSSR = subsecondtmpreg;
+    /* Configure the Alarm state: Enable Alarm */
+    __HAL_RTC_ALARMB_ENABLE(hrtc);
+    /* Configure the Alarm interrupt */
+    __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
+  }
+
+  /* RTC Alarm Interrupt Configuration: EXTI configuration */
+  __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT);
+  
+  EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;
+  
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
+  
+  hrtc->State = HAL_RTC_STATE_READY; 
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);  
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactive the specified RTC Alarm 
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  Alarm: Specifies the Alarm.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_ALARM_A:  AlarmA
+  *            @arg RTC_ALARM_B:  AlarmB
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
+{
+  uint32_t timeout = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ALARM(Alarm));
+  
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  if(Alarm == RTC_ALARM_A)
+  {
+    /* AlarmA */
+    __HAL_RTC_ALARMA_DISABLE(hrtc);
+    
+    /* In case of interrupt mode is used, the interrupt source must disabled */ 
+    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+    
+    timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+    
+    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+    {
+      if(HAL_GetTick() >= timeout)
+      { 
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+        
+        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
+        
+        /* Process Unlocked */ 
+        __HAL_UNLOCK(hrtc);
+        
+        return HAL_TIMEOUT;
+      }      
+    }
+  }
+  else
+  {
+    /* AlarmB */
+    __HAL_RTC_ALARMB_DISABLE(hrtc);
+    
+    /* In case of interrupt mode is used, the interrupt source must disabled */ 
+    __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
+    
+    timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+    
+    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+        
+        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
+        
+        /* Process Unlocked */ 
+        __HAL_UNLOCK(hrtc);
+        
+        return HAL_TIMEOUT;
+      }    
+    }
+  }
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_READY; 
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);  
+  
+  return HAL_OK; 
+}
+           
+/**
+  * @brief  Gets the RTC Alarm value and masks.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  sAlarm: Pointer to Date structure
+  * @param  Alarm: Specifies the Alarm.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_ALARM_A: AlarmA
+  *             @arg RTC_ALARM_B: AlarmB  
+  * @param  Format: Specifies the format of the entered parameters.
+  *          This parameter can be one of the following values:
+  *             @arg FORMAT_BIN: Binary data format 
+  *             @arg FORMAT_BCD: BCD data format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
+{
+  uint32_t tmpreg = 0, subsecondtmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+  assert_param(IS_ALARM(Alarm));
+  
+  if(Alarm == RTC_ALARM_A)
+  {
+    /* AlarmA */
+    sAlarm->Alarm = RTC_ALARM_A;
+    
+    tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
+    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
+  }
+  else
+  {
+    sAlarm->Alarm = RTC_ALARM_B;
+    
+    tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
+    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
+  }
+    
+  /* Fill the structure with the read parameters */
+  sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);
+  sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);
+  sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
+  sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
+  sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
+  sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
+  sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
+  sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
+    
+  if(Format == FORMAT_BIN)
+  {
+    sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+    sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
+    sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
+    sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+  }  
+    
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles Alarm interrupt request.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @retval None
+  */
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
+{  
+  if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA))
+  {
+    /* Get the status of the Interrupt */
+    if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)
+    {
+      /* AlarmA callback */ 
+      HAL_RTC_AlarmAEventCallback(hrtc);
+      
+      /* Clear the Alarm interrupt pending bit */
+      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
+    }
+  }
+  
+  if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB))
+  {
+    /* Get the status of the Interrupt */
+    if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)
+    {
+      /* AlarmB callback */ 
+      HAL_RTCEx_AlarmBEventCallback(hrtc);
+      
+      /* Clear the Alarm interrupt pending bit */
+      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
+    }
+  }
+  
+  /* Clear the EXTI's line Flag for RTC Alarm */
+  __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT);
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+}
+
+/**
+  * @brief  Alarm A callback.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @retval None
+  */
+__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RTC_AlarmAEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  This function handles AlarmA Polling request.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{  
+
+  uint32_t timeout = 0; 
+
+  /* Get Timeout value */
+  timeout = HAL_GetTick() + Timeout;   
+  
+  while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Clear the Alarm interrupt pending bit */
+  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+  
+  return HAL_OK;  
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group4 Peripheral Control functions 
+ *  @brief   Peripheral Control functions 
+ *
+@verbatim   
+ ===============================================================================
+                     ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions allowing to
+      (+) Wait for RTC Time and Date Synchronization
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are 
+  *         synchronized with RTC APB clock.
+  * @note   The RTC Resynchronization mode is write protected, use the 
+  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. 
+  * @note   To read the calendar through the shadow registers after Calendar 
+  *         initialization, calendar update or after wakeup from low power modes 
+  *         the software must first clear the RSF flag. 
+  *         The software must then wait until it is set again before reading 
+  *         the calendar, which means that the calendar registers have been 
+  *         correctly copied into the RTC_TR and RTC_DR shadow registers.   
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
+{
+  uint32_t timeout = 0;
+
+  /* Clear RSF flag */
+  hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
+  
+  timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+
+  /* Wait the registers to be synchronised */
+  while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
+  {
+    if(HAL_GetTick() >= timeout)
+    {       
+      return HAL_TIMEOUT;
+    } 
+  }
+
+  return HAL_OK;
+}
+
+/** @defgroup RTC_Group5 Peripheral State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+ ===============================================================================
+                     ##### Peripheral State functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions allowing to
+      (+) Get RTC state
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Returns the RTC state.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @retval HAL state
+  */
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
+{
+  return hrtc->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Enters the RTC Initialization mode.
+  * @note   The RTC Initialization mode is write protected, use the
+  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
+{
+  uint32_t timeout = 0; 
+  
+  /* Check if the Initialization mode is set */
+  if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+  {
+    /* Set the Initialization mode */
+    hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
+    
+    timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+    /* Wait till RTC is in INIT state and if Time out is reached exit */
+    while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+    {
+      if(HAL_GetTick() >= timeout)
+      {       
+        return HAL_TIMEOUT;
+      } 
+    }
+  }
+  
+  return HAL_OK;  
+}
+
+
+/**
+  * @brief  Converts a 2 digit decimal to BCD format.
+  * @param  Value: Byte to be converted
+  * @retval Converted byte
+  */
+uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+  uint32_t bcdhigh = 0;
+  
+  while(Value >= 10)
+  {
+    bcdhigh++;
+    Value -= 10;
+  }
+  
+  return  ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+  * @brief  Converts from 2 digit BCD to Binary.
+  * @param  Value: BCD value to be converted
+  * @retval Converted word
+  */
+uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+  uint32_t tmp = 0;
+  tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+  return (tmp + (Value & (uint8_t)0x0F));
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,746 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_rtc.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of RTC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RTC_H
+#define __STM32F4xx_HAL_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RTC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** 
+  * @brief  HAL State structures definition  
+  */ 
+typedef enum
+{
+  HAL_RTC_STATE_RESET             = 0x00,  /*!< RTC not yet initialized or disabled */
+  HAL_RTC_STATE_READY             = 0x01,  /*!< RTC initialized and ready for use   */
+  HAL_RTC_STATE_BUSY              = 0x02,  /*!< RTC process is ongoing              */     
+  HAL_RTC_STATE_TIMEOUT           = 0x03,  /*!< RTC timeout state                   */  
+  HAL_RTC_STATE_ERROR             = 0x04   /*!< RTC error state                     */      
+                                                                        
+}HAL_RTCStateTypeDef;
+
+/** 
+  * @brief  RTC Configuration Structure definition  
+  */
+typedef struct
+{
+  uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.
+                                 This parameter can be a value of @ref RTC_Hour_Formats */         
+
+  uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */        
+                               
+  uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */   
+  
+  uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.   
+                                 This parameter can be a value of @ref RTC_Output_selection_Definitions */      
+  
+  uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.  
+                                 This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ 
+  
+  uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.   
+                                 This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */             
+}RTC_InitTypeDef;
+
+/** 
+  * @brief  RTC Time structure definition  
+  */
+typedef struct
+{
+  uint8_t Hours;            /*!< Specifies the RTC Time Hour.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected  */
+
+  uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+  
+  uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+  
+  uint32_t SubSeconds;      /*!< Specifies the RTC Time SubSeconds.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+  uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
+                                 This parameter can be a value of @ref RTC_AM_PM_Definitions */ 
+  
+  uint32_t DayLightSaving;  /*!< Specifies DayLight Save Operation.
+                                 This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
+  
+  uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit 
+                                 in CR register to store the operation.
+                                 This parameter can be a value of @ref RTC_StoreOperation_Definitions */
+}RTC_TimeTypeDef; 
+  
+/** 
+  * @brief  RTC Date structure definition  
+  */
+typedef struct
+{
+  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
+                         This parameter can be a value of @ref RTC_WeekDay_Definitions */
+  
+  uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
+                         This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+  uint8_t Date;     /*!< Specifies the RTC Date.
+                         This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+  
+  uint8_t Year;     /*!< Specifies the RTC Date Year.
+                         This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
+                        
+}RTC_DateTypeDef;
+
+/** 
+  * @brief  RTC Alarm structure definition  
+  */
+typedef struct
+{
+  RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
+    
+  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
+                                      This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+  
+  uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
+                                      This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */                                   
+
+  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
+                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+  
+  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
+                                      If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
+                                      If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
+                                                                     
+  uint32_t Alarm;                /*!< Specifies the alarm .
+                                      This parameter can be a value of @ref RTC_Alarms_Definitions */                            
+}RTC_AlarmTypeDef;
+
+/** 
+  * @brief  Time Handle Structure definition  
+  */ 
+typedef struct
+{
+  RTC_TypeDef                 *Instance;  /*!< Register base address    */
+   
+  RTC_InitTypeDef             Init;       /*!< RTC required parameters  */ 
+  
+  HAL_LockTypeDef             Lock;       /*!< RTC locking object       */
+  
+  __IO HAL_RTCStateTypeDef    State;      /*!< Time communication state */
+    
+}RTC_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_Exported_Constants
+  * @{
+  */ 
+
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
+#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F) 
+#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFF)  
+#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5F)
+#define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
+                                            RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
+                                            RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
+                                            RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
+                                            RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
+
+#define RTC_TIMEOUT_VALUE       1000
+ 
+/** @defgroup RTC_Hour_Formats 
+  * @{
+  */ 
+#define RTC_HOURFORMAT_24              ((uint32_t)0x00000000)
+#define RTC_HOURFORMAT_12              ((uint32_t)0x00000040)
+
+#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
+                                        ((FORMAT) == RTC_HOURFORMAT_24))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RTC_Output_selection_Definitions 
+  * @{
+  */ 
+#define RTC_OUTPUT_DISABLE             ((uint32_t)0x00000000)
+#define RTC_OUTPUT_ALARMA              ((uint32_t)0x00200000)
+#define RTC_OUTPUT_ALARMB              ((uint32_t)0x00400000)
+#define RTC_OUTPUT_WAKEUP              ((uint32_t)0x00600000)
+ 
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+                               ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
+                               ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
+                               ((OUTPUT) == RTC_OUTPUT_WAKEUP))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_Polarity_Definitions 
+  * @{
+  */ 
+#define RTC_OUTPUT_POLARITY_HIGH       ((uint32_t)0x00000000)
+#define RTC_OUTPUT_POLARITY_LOW        ((uint32_t)0x00100000)
+
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
+                                ((POL) == RTC_OUTPUT_POLARITY_LOW))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_Type_ALARM_OUT 
+  * @{
+  */ 
+#define RTC_OUTPUT_TYPE_OPENDRAIN      ((uint32_t)0x00000000)
+#define RTC_OUTPUT_TYPE_PUSHPULL       ((uint32_t)0x00040000)
+
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
+                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Asynchronous_Predivider 
+  * @{
+  */ 
+#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (uint32_t)0x7F) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Synchronous_Predivider 
+  * @{
+  */ 
+#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (uint32_t)0x7FFF)
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Time_Definitions 
+  * @{
+  */ 
+#define IS_RTC_HOUR12(HOUR)            (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
+#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= (uint32_t)23)
+#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= (uint32_t)59)
+#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= (uint32_t)59)
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_AM_PM_Definitions 
+  * @{
+  */ 
+#define RTC_HOURFORMAT12_AM            ((uint8_t)0x00)
+#define RTC_HOURFORMAT12_PM            ((uint8_t)0x40)
+
+#define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_DayLightSaving_Definitions 
+  * @{
+  */ 
+#define RTC_DAYLIGHTSAVING_SUB1H       ((uint32_t)0x00020000)
+#define RTC_DAYLIGHTSAVING_ADD1H       ((uint32_t)0x00010000)
+#define RTC_DAYLIGHTSAVING_NONE        ((uint32_t)0x00000000)
+
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
+                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
+                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_StoreOperation_Definitions 
+  * @{
+  */ 
+#define RTC_STOREOPERATION_RESET        ((uint32_t)0x00000000)
+#define RTC_STOREOPERATION_SET          ((uint32_t)0x00040000)
+
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
+                                           ((OPERATION) == RTC_STOREOPERATION_SET))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Input_parameter_format_definitions 
+  * @{
+  */ 
+#define FORMAT_BIN                      ((uint32_t)0x000000000)
+#define FORMAT_BCD                      ((uint32_t)0x000000001)
+
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == FORMAT_BIN) || ((FORMAT) == FORMAT_BCD))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Year_Date_Definitions 
+  * @{
+  */ 
+#define IS_RTC_YEAR(YEAR)              ((YEAR) <= (uint32_t)99)
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Month_Date_Definitions 
+  * @{
+  */ 
+
+/* Coded in BCD format */
+#define RTC_MONTH_JANUARY              ((uint8_t)0x01)
+#define RTC_MONTH_FEBRUARY             ((uint8_t)0x02)
+#define RTC_MONTH_MARCH                ((uint8_t)0x03)
+#define RTC_MONTH_APRIL                ((uint8_t)0x04)
+#define RTC_MONTH_MAY                  ((uint8_t)0x05)
+#define RTC_MONTH_JUNE                 ((uint8_t)0x06)
+#define RTC_MONTH_JULY                 ((uint8_t)0x07)
+#define RTC_MONTH_AUGUST               ((uint8_t)0x08)
+#define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09)
+#define RTC_MONTH_OCTOBER              ((uint8_t)0x10)
+#define RTC_MONTH_NOVEMBER             ((uint8_t)0x11)
+#define RTC_MONTH_DECEMBER             ((uint8_t)0x12)
+
+#define IS_RTC_MONTH(MONTH)            (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
+#define IS_RTC_DATE(DATE)              (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_WeekDay_Definitions 
+  * @{
+  */   
+#define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01)
+#define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02)
+#define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03)
+#define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04)
+#define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05)
+#define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06)
+#define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07)
+
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+/**
+  * @}
+  */ 
+                                    
+/** @defgroup RTC_Alarm_Definitions
+  * @{
+  */ 
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions 
+  * @{
+  */ 
+#define RTC_ALARMDATEWEEKDAYSEL_DATE      ((uint32_t)0x00000000)
+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   ((uint32_t)0x40000000)
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
+                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_AlarmMask_Definitions 
+  * @{
+  */ 
+#define RTC_ALARMMASK_NONE                ((uint32_t)0x00000000)
+#define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4
+#define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3
+#define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2
+#define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1
+#define RTC_ALARMMASK_ALL                 ((uint32_t)0x80808080)
+
+#define IS_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarms_Definitions 
+  * @{
+  */ 
+#define RTC_ALARM_A                       RTC_CR_ALRAE
+#define RTC_ALARM_B                       RTC_CR_ALRBE
+
+#define IS_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Value
+  * @{
+  */ 
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
+/**
+  * @}
+  */
+
+  /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
+  * @{
+  */ 
+#define RTC_ALARMSUBSECONDMASK_ALL         ((uint32_t)0x00000000)  /*!< All Alarm SS fields are masked. 
+                                                                        There is no comparison on sub seconds 
+                                                                        for Alarm */
+#define RTC_ALARMSUBSECONDMASK_SS14_1      ((uint32_t)0x01000000)  /*!< SS[14:1] are don't care in Alarm 
+                                                                        comparison. Only SS[0] is compared.    */
+#define RTC_ALARMSUBSECONDMASK_SS14_2      ((uint32_t)0x02000000)  /*!< SS[14:2] are don't care in Alarm 
+                                                                        comparison. Only SS[1:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_3      ((uint32_t)0x03000000)  /*!< SS[14:3] are don't care in Alarm 
+                                                                        comparison. Only SS[2:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_4      ((uint32_t)0x04000000)  /*!< SS[14:4] are don't care in Alarm 
+                                                                        comparison. Only SS[3:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_5      ((uint32_t)0x05000000)  /*!< SS[14:5] are don't care in Alarm 
+                                                                        comparison. Only SS[4:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_6      ((uint32_t)0x06000000)  /*!< SS[14:6] are don't care in Alarm 
+                                                                        comparison. Only SS[5:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_7      ((uint32_t)0x07000000)  /*!< SS[14:7] are don't care in Alarm 
+                                                                        comparison. Only SS[6:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_8      ((uint32_t)0x08000000)  /*!< SS[14:8] are don't care in Alarm 
+                                                                        comparison. Only SS[7:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_9      ((uint32_t)0x09000000)  /*!< SS[14:9] are don't care in Alarm 
+                                                                        comparison. Only SS[8:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_10     ((uint32_t)0x0A000000)  /*!< SS[14:10] are don't care in Alarm 
+                                                                        comparison. Only SS[9:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_11     ((uint32_t)0x0B000000)  /*!< SS[14:11] are don't care in Alarm 
+                                                                        comparison. Only SS[10:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_12     ((uint32_t)0x0C000000)  /*!< SS[14:12] are don't care in Alarm 
+                                                                        comparison.Only SS[11:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_13     ((uint32_t)0x0D000000)  /*!< SS[14:13] are don't care in Alarm 
+                                                                        comparison. Only SS[12:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14        ((uint32_t)0x0E000000)  /*!< SS[14] is don't care in Alarm 
+                                                                        comparison.Only SS[13:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_None        ((uint32_t)0x0F000000)  /*!< SS[14:0] are compared and must match 
+                                                                        to activate alarm. */
+
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_None))
+/**
+  * @}
+  */   
+
+/** @defgroup RTC_Interrupts_Definitions 
+  * @{
+  */ 
+#define RTC_IT_TS                         ((uint32_t)0x00008000)
+#define RTC_IT_WUT                        ((uint32_t)0x00004000)
+#define RTC_IT_ALRB                       ((uint32_t)0x00002000)
+#define RTC_IT_ALRA                       ((uint32_t)0x00001000)
+#define RTC_IT_TAMP                       ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1                      ((uint32_t)0x00020000)
+#define RTC_IT_TAMP2                      ((uint32_t)0x00040000)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Flags_Definitions 
+  * @{
+  */ 
+#define RTC_FLAG_RECALPF                  ((uint32_t)0x00010000)
+#define RTC_FLAG_TAMP2F                   ((uint32_t)0x00004000)
+#define RTC_FLAG_TAMP1F                   ((uint32_t)0x00002000)
+#define RTC_FLAG_TSOVF                    ((uint32_t)0x00001000)
+#define RTC_FLAG_TSF                      ((uint32_t)0x00000800)
+#define RTC_FLAG_WUTF                     ((uint32_t)0x00000400)
+#define RTC_FLAG_ALRBF                    ((uint32_t)0x00000200)
+#define RTC_FLAG_ALRAF                    ((uint32_t)0x00000100)
+#define RTC_FLAG_INITF                    ((uint32_t)0x00000040)
+#define RTC_FLAG_RSF                      ((uint32_t)0x00000020)
+#define RTC_FLAG_INITS                    ((uint32_t)0x00000010)
+#define RTC_FLAG_SHPF                     ((uint32_t)0x00000008)
+#define RTC_FLAG_WUTWF                    ((uint32_t)0x00000004)
+#define RTC_FLAG_ALRBWF                   ((uint32_t)0x00000002)
+#define RTC_FLAG_ALRAWF                   ((uint32_t)0x00000001)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset RTC handle state
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
+
+/**
+  * @brief  Disable the write protection for RTC registers.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
+                        do{                                       \
+                            (__HANDLE__)->Instance->WPR = 0xCA;   \
+                            (__HANDLE__)->Instance->WPR = 0x53;   \
+                          } while(0)
+
+/**
+  * @brief  Enable the write protection for RTC registers.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
+                        do{                                       \
+                            (__HANDLE__)->Instance->WPR = 0xFF;   \
+                          } while(0)                            
+ 
+/**
+  * @brief  Enable the RTC ALARMA peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
+
+/**
+  * @brief  Disable the RTC ALARMA peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
+
+/**
+  * @brief  Enable the RTC ALARMB peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
+
+/**
+  * @brief  Disable the RTC ALARMB peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
+
+/**
+  * @brief  Enable the RTC Alarm interrupt.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
+  *             @arg RTC_IT_ALRA: Alarm A interrupt
+  *             @arg RTC_IT_ALRB: Alarm B interrupt  
+  * @retval None
+  */   
+#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the RTC Alarm interrupt.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. 
+  *         This parameter can be any combination of the following values:
+  *            @arg RTC_IT_ALRA: Alarm A interrupt
+  *            @arg RTC_IT_ALRB: Alarm B interrupt  
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+  *         This parameter can be:
+  *            @arg RTC_IT_ALRA: Alarm A interrupt
+  *            @arg RTC_IT_ALRB: Alarm B interrupt  
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __FLAG__)                  ((((((__HANDLE__)->Instance->ISR)& ((__FLAG__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
+
+/**
+  * @brief  Get the selected RTC Alarm's flag status.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+  *         This parameter can be:
+  *            @arg RTC_FLAG_ALRAF
+  *            @arg RTC_FLAG_ALRBF
+  *            @arg RTC_FLAG_ALRAWF     
+  *            @arg RTC_FLAG_ALRBWF    
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+  * @brief  Clear the RTC Alarm's pending flags.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+  *          This parameter can be:
+  *             @arg RTC_FLAG_ALRAF
+  *             @arg RTC_FLAG_ALRBF 
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)                  ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+  
+  
+#define RTC_EXTI_LINE_ALARM_EVENT             ((uint32_t)0x00020000)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  ((uint32_t)0x00200000)  /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */                                               
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       ((uint32_t)0x00400000)  /*!< External interrupt line 22 Connected to the RTC Wakeup event */                                               
+
+/**
+  * @brief  Enable the RTC Exti line.
+  * @param  __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
+  *         This parameter can be:
+  *            @arg RTC_EXTI_LINE_ALARM_EVENT   
+  *            @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT 
+  *            @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT      
+  * @retval None
+  */                                         
+#define __HAL_RTC_ENABLE_IT(__EXTILINE__)   (EXTI->IMR |= (__EXTILINE__))
+
+/**
+  * @brief  Disable the RTC Exti line.
+  * @param  __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
+  *         This parameter can be:
+  *            @arg RTC_EXTI_LINE_ALARM_EVENT   
+  *            @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT 
+  *            @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT     
+  * @retval None
+  */
+#define __HAL_RTC_DISABLE_IT(__EXTILINE__)  (EXTI->IMR &= ~(__EXTILINE__))
+
+/**
+  * @brief  Clear the RTC Exti flags.
+  * @param  __FLAG__: specifies the RTC Exti sources to be enabled or disabled.
+  *         This parameter can be:
+  *            @arg RTC_EXTI_LINE_ALARM_EVENT   
+  *            @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT 
+  *            @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT      
+  * @retval None
+  */
+#define __HAL_RTC_CLEAR_FLAG(__FLAG__)  (EXTI->PR = (__FLAG__))
+
+/* Include RTC HAL Extension module */
+#include "stm32f4xx_hal_rtc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
+void       HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
+void       HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+
+/* RTC Time and Date functions ************************************************/
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+
+/* RTC Alarm functions ********************************************************/
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
+void                HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef   HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+void         HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
+
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
+
+/* Peripheral State functions *************************************************/
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
+
+HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
+uint8_t            RTC_ByteToBcd2(uint8_t Value);
+uint8_t            RTC_Bcd2ToByte(uint8_t Value);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RTC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1703 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_rtc_ex.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   RTC HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Real Time Clock (RTC) Extension peripheral:
+  *           + RTC Time Stamp functions
+  *           + RTC Tamper functions 
+  *           + RTC Wake-up functions
+  *           + Extension Control functions
+  *           + Extension RTC features functions    
+  *         
+  @verbatim
+  ==============================================================================
+                  ##### How to use this driver #####
+  ==============================================================================
+  [..] 
+    (+) Enable the RTC domain access.
+    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour 
+        format using the HAL_RTC_Init() function.
+  
+  *** RTC Wakeup configuration ***
+  ================================
+  [..] 
+    (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
+        function. You can also configure the RTC Wakeup timer in interrupt mode 
+        using the HAL_RTC_SetWakeUpTimer_IT() function.
+    (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer() 
+        function.
+  
+  *** TimeStamp configuration ***
+  ===============================
+  [..]
+    (+) Configure the RTC_AFx trigger and enable the RTC TimeStamp using the 
+        HAL_RTC_SetTimeStamp() function. You can also configure the RTC TimeStamp with 
+        interrupt mode using the HAL_RTC_SetTimeStamp_IT() function.
+    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
+        function.
+    (+) The TIMESTAMP alternate function can be mapped either to RTC_AF1 (PC13)
+        or RTC_AF2 (PI8) depending on the value of TSINSEL bit in 
+        RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTimeStamp()
+        or HAL_RTC_SetTimeStamp_IT() function.
+  
+  *** Tamper configuration ***
+  ============================
+  [..]
+    (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge 
+        or Level according to the Tamper filter (if equal to 0 Edge else Level) 
+        value, sampling frequency, precharge or discharge and Pull-UP using the 
+        HAL_RTC_SetTamper() function. You can configure RTC Tamper in interrupt 
+        mode using HAL_RTC_SetTamper_IT() function.
+    (+) The TAMPER1 alternate function can be mapped either to RTC_AF1 (PC13)
+        or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in 
+        RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTamper()
+        or HAL_RTC_SetTamper_IT() function.
+  
+  *** Backup Data Registers configuration ***
+  ===========================================
+  [..]
+    (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
+        function.  
+    (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
+        function.
+     
+   @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RTCEx 
+  * @brief RTC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RTCEx_Private_Functions
+  * @{
+  */
+  
+
+/** @defgroup RTCEx_Group1 RTC TimeStamp and Tamper functions
+ *  @brief   RTC TimeStamp and Tamper functions
+ *
+@verbatim   
+ ===============================================================================
+                 ##### RTC TimeStamp and Tamper functions #####
+ ===============================================================================  
+ 
+ [..] This section provides functions allowing to configure TimeStamp feature
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets TimeStamp.
+  * @note   This API must be called before enabling the TimeStamp feature. 
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is 
+  *         activated.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the  
+  *                                        rising edge of the related pin.
+  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the 
+  *                                         falling edge of the related pin.
+  * @param  RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
+  *             @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+  
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  /* Get the RTC_CR register and clear the bits to be configured */
+  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+    
+  tmpreg|= TimeStampEdge;
+  
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL;
+  hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin); 
+  
+  /* Configure the Time Stamp TSEDGE and Enable bits */
+  hrtc->Instance->CR = (uint32_t)tmpreg;
+  
+  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
+  
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);    
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Sets TimeStamp with Interrupt. 
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @note   This API must be called before enabling the TimeStamp feature.
+  * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is 
+  *         activated.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the  
+  *                                        rising edge of the related pin.
+  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the 
+  *                                         falling edge of the related pin.
+  * @param  RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
+  *             @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+  
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  /* Get the RTC_CR register and clear the bits to be configured */
+  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+  
+  tmpreg |= TimeStampEdge;
+  
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  /* Configure the Time Stamp TSEDGE and Enable bits */
+  hrtc->Instance->CR = (uint32_t)tmpreg;
+  
+  hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL;
+  hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin); 
+  
+  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
+  
+  /* Enable IT timestamp */ 
+  __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
+  
+  /* RTC timestamp Interrupt Configuration: EXTI configuration */
+  __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
+  
+  EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
+  
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
+  
+  hrtc->State = HAL_RTC_STATE_READY;  
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivates TimeStamp. 
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  /* In case of interrupt mode is used, the interrupt source must disabled */ 
+  __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
+  
+  /* Get the RTC_CR register and clear the bits to be configured */
+  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+  
+  /* Configure the Time Stamp TSEDGE and Enable bits */
+  hrtc->Instance->CR = (uint32_t)tmpreg;
+  
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ 
+  hrtc->State = HAL_RTC_STATE_READY;  
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Gets the RTC TimeStamp value.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  sTimeStamp: Pointer to Time structure
+  * @param  sTimeStampDate: Pointer to Date structure  
+  * @param  Format: specifies the format of the entered parameters.
+  *          This parameter can be one of the following values:
+  *             FORMAT_BIN: Binary data format 
+  *             FORMAT_BCD: BCD data format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
+{
+  uint32_t tmptime = 0, tmpdate = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+
+  /* Get the TimeStamp time and date registers values */
+  tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
+  tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
+
+  /* Fill the Time structure fields with the read parameters */
+  sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+  sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
+  sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
+  sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);  
+  sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
+  
+  /* Fill the Date structure fields with the read parameters */
+  sTimeStampDate->Year = 0;
+  sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+  sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
+  sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
+
+  /* Check the input parameters format */
+  if(Format == FORMAT_BIN)
+  {
+    /* Convert the TimeStamp structure parameters to Binary format */
+    sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
+    sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
+    sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
+    
+    /* Convert the DateTimeStamp structure parameters to Binary format */
+    sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
+    sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
+    sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
+  }
+  
+  /* Clear the TIMESTAMP Flag */
+  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
+    
+  return HAL_OK;
+}
+
+/**
+  * @brief  Sets Tamper
+  * @note   By calling this API we disable the tamper interrupt for all tampers. 
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  sTamper: Pointer to Tamper Structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TAMPER(sTamper->Tamper)); 
+  assert_param(IS_RTC_TAMPER_PIN(sTamper->PinSelection));
+  assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger));
+  assert_param(IS_TAMPER_FILTER(sTamper->Filter));
+  assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));         
+  assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+  assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+  assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+ 
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+    
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+  { 
+    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); 
+  } 
+        
+  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->PinSelection | (uint32_t)sTamper->Trigger  |\
+            (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
+            (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
+  
+  hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS |\
+                                       (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
+                                       (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPINSEL | (uint32_t)RTC_TAFCR_TAMPIE);
+
+  hrtc->Instance->TAFCR |= tmpreg;
+  
+  hrtc->State = HAL_RTC_STATE_READY; 
+
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+    
+  return HAL_OK;
+}
+
+/**
+  * @brief  Sets Tamper with interrupt.
+  * @note   By calling this API we force the tamper interrupt for all tampers.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  sTamper: Pointer to RTC Tamper.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TAMPER(sTamper->Tamper)); 
+  assert_param(IS_RTC_TAMPER_PIN(sTamper->PinSelection));
+  assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger));
+  assert_param(IS_TAMPER_FILTER(sTamper->Filter));
+  assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));         
+  assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+  assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+  assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+ 
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+      
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  /* Configure the tamper trigger */
+  if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+  { 
+    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); 
+  } 
+       
+  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->PinSelection | (uint32_t)sTamper->Trigger  |\
+            (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
+            (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
+  
+  hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS |\
+                                       (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
+                                       (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPINSEL);
+    
+  hrtc->Instance->TAFCR |= tmpreg;
+  
+  /* Configure the Tamper Interrupt in the RTC_TAFCR */
+  hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
+  
+  /* RTC Tamper Interrupt Configuration: EXTI configuration */
+  __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
+  
+  EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
+  
+  hrtc->State = HAL_RTC_STATE_READY;   
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivates Tamper.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  Tamper: Selected tamper pin.
+  *          This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
+{
+  assert_param(IS_TAMPER(Tamper)); 
+  
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+      
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  /* Disable the selected Tamper pin */
+  hrtc->Instance->TAFCR &= (uint32_t)~Tamper;  
+  
+  hrtc->State = HAL_RTC_STATE_READY;   
+  
+  /* Process Unlocked */  
+  __HAL_UNLOCK(hrtc);
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  This function handles TimeStamp interrupt request.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @retval None
+  */
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
+{  
+  if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS))
+  {
+    /* Get the status of the Interrupt */
+    if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)
+    {
+      /* TIMESTAMP callback */ 
+      HAL_RTCEx_TimeStampEventCallback(hrtc);
+  
+      /* Clear the TIMESTAMP interrupt pending bit */
+      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);
+    }
+  }
+  
+  /* Get the status of the Interrupt */
+  if(__HAL_RTC_TAMPER_GET_IT(hrtc,RTC_IT_TAMP1))
+  {
+    /* Get the TAMPER Interrupt enable bit and pending bit */
+    if(((hrtc->Instance->TAFCR & (RTC_TAFCR_TAMPIE))) != (uint32_t)RESET) 
+    {
+      /* Tamper callback */ 
+      HAL_RTCEx_Tamper1EventCallback(hrtc);
+  
+      /* Clear the Tamper interrupt pending bit */
+      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
+    }
+  }
+  
+  /* Get the status of the Interrupt */
+  if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP2))
+  {
+    /* Get the TAMPER Interrupt enable bit and pending bit */
+    if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET) 
+    {
+      /* Tamper callback */ 
+      HAL_RTCEx_Tamper2EventCallback(hrtc);
+  
+      /* Clear the Tamper interrupt pending bit */
+      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
+    }
+  }
+  /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
+  __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+}
+
+/**
+  * @brief  TimeStamp callback. 
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @retval None
+  */
+__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RTC_TimeStampEventCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Tamper 1 callback. 
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @retval None
+  */
+__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RTC_Tamper1EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tamper 2 callback. 
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @retval None
+  */
+__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RTC_Tamper2EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  This function handles TimeStamp polling request.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{ 
+  uint32_t timeout = 0; 
+
+  /* Get Timeout value */
+  timeout = HAL_GetTick() + Timeout;   
+
+  while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
+  {
+    if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
+    {
+      /* Clear the TIMESTAMP OverRun Flag */
+      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
+      
+      /* Change TIMESTAMP state */
+      hrtc->State = HAL_RTC_STATE_ERROR; 
+      
+      return HAL_ERROR; 
+    }
+    
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+  
+  return HAL_OK; 
+}
+  
+/**
+  * @brief  This function handles Tamper1 Polling.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{  
+  uint32_t timeout = 0; 
+
+  /* Get Timeout value */
+  timeout = HAL_GetTick() + Timeout;
+  
+  /* Get the status of the Interrupt */
+  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET)
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Clear the Tamper Flag */
+  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  This function handles Tamper2 Polling.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{  
+  uint32_t timeout = 0; 
+
+  /* Get Timeout value */
+  timeout = HAL_GetTick() + Timeout;
+  
+  /* Get the status of the Interrupt */
+  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Clear the Tamper Flag */
+  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTCEx_Group2 RTC Wake-up functions
+ *  @brief   RTC Wake-up functions
+ *
+@verbatim   
+ ===============================================================================
+                        ##### RTC Wake-up functions #####
+ ===============================================================================  
+ 
+ [..] This section provides functions allowing to configure Wake-up feature
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets wake up timer. 
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  WakeUpCounter: Wake up counter
+  * @param  WakeUpClock: Wake up clock  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
+{
+  uint32_t timeout = 0;
+
+  /* Check the parameters */
+  assert_param(IS_WAKEUP_CLOCK(WakeUpClock));
+  assert_param(IS_WAKEUP_COUNTER(WakeUpCounter));
+ 
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+    
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+     
+  timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+
+  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+  {
+    if(HAL_GetTick() >= timeout)
+    {
+      /* Enable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+      
+      hrtc->State = HAL_RTC_STATE_TIMEOUT; 
+      
+      /* Process Unlocked */ 
+      __HAL_UNLOCK(hrtc);
+      
+      return HAL_TIMEOUT;
+    }  
+  }
+  
+  /* Clear the Wakeup Timer clock source bits in CR register */
+  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+  
+  /* Configure the clock source */
+  hrtc->Instance->CR |= (uint32_t)WakeUpClock;
+  
+  /* Configure the Wakeup Timer counter */
+  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
+  
+   /* Enable the Wakeup Timer */
+  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);   
+  
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
+  
+  hrtc->State = HAL_RTC_STATE_READY;   
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Sets wake up timer with interrupt
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  WakeUpCounter: Wake up counter
+  * @param  WakeUpClock: Wake up clock  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
+{
+  uint32_t timeout = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_WAKEUP_CLOCK(WakeUpClock));
+  assert_param(IS_WAKEUP_COUNTER(WakeUpCounter));
+  
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+       
+  timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+  
+  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+  {
+    if(HAL_GetTick() >= timeout)
+    {
+      /* Enable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+      
+      hrtc->State = HAL_RTC_STATE_TIMEOUT; 
+      
+      /* Process Unlocked */ 
+      __HAL_UNLOCK(hrtc);
+      
+      return HAL_TIMEOUT;
+    }  
+  }
+  
+  /* Configure the Wakeup Timer counter */
+  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
+
+  /* Clear the Wakeup Timer clock source bits in CR register */
+  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+  /* Configure the clock source */
+  hrtc->Instance->CR |= (uint32_t)WakeUpClock;
+  
+  /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
+  __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+  
+  EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
+  
+  /* Configure the Interrupt in the RTC_CR register */
+  __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
+  
+  /* Enable the Wakeup Timer */
+  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
+    
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
+  
+  hrtc->State = HAL_RTC_STATE_READY;   
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+ 
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivates wake up timer counter.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC. 
+  * @retval HAL status
+  */
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
+{
+  uint32_t timeout = 0;
+  
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  /* Disable the Wakeup Timer */
+  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+  
+  /* In case of interrupt mode is used, the interrupt source must disabled */ 
+  __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
+      
+  timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+  {
+    if(HAL_GetTick() >= timeout)
+    {
+      /* Enable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+      
+      hrtc->State = HAL_RTC_STATE_TIMEOUT; 
+      
+      /* Process Unlocked */ 
+      __HAL_UNLOCK(hrtc);
+      
+      return HAL_TIMEOUT;
+    }   
+  }
+  
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_READY;   
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Gets wake up timer counter.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC. 
+  * @retval Counter value
+  */
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
+{
+  /* Get the counter value */
+  return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); 
+}
+
+/**
+  * @brief  This function handles Wake Up Timer interrupt request.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @retval None
+  */
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
+{  
+  if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT))
+  {
+    /* Get the status of the Interrupt */
+    if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)
+    {
+      /* WAKEUPTIMER callback */ 
+      HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
+      
+      /* Clear the WAKEUPTIMER interrupt pending bit */
+      __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+    }
+  }
+  
+  /* Clear the EXTI's line Flag for RTC WakeUpTimer */
+  __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+}
+
+/**
+  * @brief  Wake Up Timer callback.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @retval None
+  */
+__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  This function handles Wake Up Timer Polling.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{  
+  uint32_t timeout = 0; 
+
+  /* Get Timeout value */
+  timeout = HAL_GetTick() + Timeout;
+  
+  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+      
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Clear the WAKEUPTIMER Flag */
+  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+  
+  return HAL_OK; 
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RTCEx_Group3 Extension Peripheral Control functions 
+ *  @brief   Extension Peripheral Control functions 
+ *
+@verbatim   
+ ===============================================================================
+              ##### Extension Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions allowing to
+      (+) Write a data in a specified RTC Backup data register
+      (+) Read a data in a specified RTC Backup data register
+      (+) Set the Coarse calibration parameters.
+      (+) Deactivate the Coarse calibration parameters
+      (+) Set the Smooth calibration parameters.
+      (+) Configure the Synchronization Shift Control Settings.
+      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+      (+) Enable the RTC reference clock detection.
+      (+) Disable the RTC reference clock detection.
+      (+) Enable the Bypass Shadow feature.
+      (+) Disable the Bypass Shadow feature.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Writes a data in a specified RTC Backup data register.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC. 
+  * @param  BackupRegister: RTC Backup data Register number.
+  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
+  *                                 specify the register.
+  * @param  Data: Data to be written in the specified RTC Backup data register.                     
+  * @retval None
+  */
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
+{
+  uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_BKP(BackupRegister));
+  
+  tmp = (uint32_t)&(hrtc->Instance->BKP0R);
+  tmp += (BackupRegister * 4);
+  
+  /* Write the specified register */
+  *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+  * @brief  Reads data from the specified RTC Backup data Register.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC. 
+  * @param  BackupRegister: RTC Backup data Register number.
+  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
+  *                                 specify the register.                   
+  * @retval Read value
+  */
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
+{
+  uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_BKP(BackupRegister));
+
+  tmp = (uint32_t)&(hrtc->Instance->BKP0R);
+  tmp += (BackupRegister * 4);
+  
+  /* Read the specified register */
+  return (*(__IO uint32_t *)tmp);
+}
+      
+/**
+  * @brief  Sets the Coarse calibration parameters.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.  
+  * @param  CalibSign: Specifies the sign of the coarse calibration value.
+  *          This parameter can be  one of the following values :
+  *             @arg RTC_CALIBSIGN_POSITIVE: The value sign is positive 
+  *             @arg RTC_CALIBSIGN_NEGATIVE: The value sign is negative
+  * @param  Value: value of coarse calibration expressed in ppm (coded on 5 bits).
+  *    
+  * @note   This Calibration value should be between 0 and 63 when using negative
+  *         sign with a 2-ppm step.
+  *           
+  * @note   This Calibration value should be between 0 and 126 when using positive
+  *         sign with a 4-ppm step.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef* hrtc, uint32_t CalibSign, uint32_t Value)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CALIB_SIGN(CalibSign));
+  assert_param(IS_RTC_CALIB_VALUE(Value)); 
+  
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Set Initialization mode */
+  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  {
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
+    
+    /* Set RTC state*/
+    hrtc->State = HAL_RTC_STATE_ERROR;
+    
+    /* Process Unlocked */ 
+    __HAL_UNLOCK(hrtc);
+    
+    return HAL_ERROR;
+  } 
+  else
+  { 
+    /* Enable the Coarse Calibration */
+    __HAL_RTC_COARSE_CALIB_ENABLE(hrtc);
+    
+    /* Set the coarse calibration value */
+    hrtc->Instance->CALIBR = (uint32_t)(CalibSign|Value);
+    
+    /* Exit Initialization mode */
+    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
+  } 
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+  
+  /* Change state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivates the Coarse calibration parameters.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc)
+{ 
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Set Initialization mode */
+  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  {
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
+    
+    /* Set RTC state*/
+    hrtc->State = HAL_RTC_STATE_ERROR;
+    
+    /* Process Unlocked */ 
+    __HAL_UNLOCK(hrtc);
+    
+    return HAL_ERROR;
+  } 
+  else
+  { 
+    /* Enable the Coarse Calibration */
+    __HAL_RTC_COARSE_CALIB_DISABLE(hrtc);
+    
+    /* Exit Initialization mode */
+    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
+  } 
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+  
+  /* Change state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Sets the Smooth calibration parameters.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.  
+  * @param  SmoothCalibPeriod: Select the Smooth Calibration Period.
+  *          This parameter can be can be one of the following values :
+  *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration periode is 32s.
+  *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration periode is 16s.
+  *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibartion periode is 8s.
+  * @param  SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK puls every 2*11 pulses.
+  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
+  * @param  SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
+  *          This parameter can be one any value from 0 to 0x000001FF.
+  * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses 
+  *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field 
+  *         SmouthCalibMinusPulsesValue must be equal to 0.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
+{
+  uint32_t timeout = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
+  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
+  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));
+  
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  /* check if a calibration is pending*/
+  if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
+  {
+    timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+  
+    /* check if a calibration is pending*/
+    while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+        
+        /* Change RTC state */
+        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
+        
+        /* Process Unlocked */ 
+        __HAL_UNLOCK(hrtc);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Configure the Smooth calibration settings */
+  hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue);
+  
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the Synchronization Shift Control Settings.
+  * @note   When REFCKON is set, firmware must not write to Shift control register. 
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.    
+  * @param  ShiftAdd1S: Select to add or not 1 second to the time calendar.
+  *          This parameter can be one of the following values :
+  *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. 
+  *             @arg RTC_SHIFTADD1S_RESET: No effect.
+  * @param  ShiftSubFS: Select the number of Second Fractions to substitute.
+  *          This parameter can be one any value from 0 to 0x7FFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
+{
+  uint32_t timeout = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
+  assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
+
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+    timeout = HAL_GetTick() + RTC_TIMEOUT_VALUE;
+
+    /* Wait until the shift is completed*/
+    while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
+    {
+      if(HAL_GetTick() >= timeout)
+      {  
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
+        
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        
+        /* Process Unlocked */ 
+        __HAL_UNLOCK(hrtc);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  
+    /* Check if the reference clock detection is disabled */
+    if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
+    {
+      /* Configure the Shift settings */
+      hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
+      
+      /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+      if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+      {
+        if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+        {
+          /* Enable the write protection for RTC registers */
+          __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
+          
+          hrtc->State = HAL_RTC_STATE_ERROR;
+          
+          /* Process Unlocked */ 
+          __HAL_UNLOCK(hrtc);
+          
+          return HAL_ERROR;
+        }
+      }
+    }
+    else
+    {
+      /* Enable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+      
+      /* Change RTC state */
+      hrtc->State = HAL_RTC_STATE_ERROR; 
+      
+      /* Process Unlocked */ 
+      __HAL_UNLOCK(hrtc);
+      
+      return HAL_ERROR;
+    }
+  
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.    
+  * @param  CalibOutput: Select the Calibration output Selection .
+  *          This parameter can be one of the following values:
+  *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. 
+  *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
+  
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  /* Clear flags before config */
+  hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
+  
+  /* Configure the RTC_CR register */
+  hrtc->Instance->CR |= (uint32_t)CalibOutput;
+  
+  __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
+  
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
+{
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
+    
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables the RTC reference clock detection.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
+{
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  /* Set Initialization mode */
+  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  {
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
+    
+    /* Set RTC state*/
+    hrtc->State = HAL_RTC_STATE_ERROR;
+    
+    /* Process Unlocked */ 
+    __HAL_UNLOCK(hrtc);
+    
+    return HAL_ERROR;
+  } 
+  else
+  {
+    __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
+
+    /* Exit Initialization mode */
+    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
+  }
+  
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+  
+   /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the RTC reference clock detection.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
+{ 
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  /* Set Initialization mode */
+  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  {
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
+    
+    /* Set RTC state*/
+    hrtc->State = HAL_RTC_STATE_ERROR;
+    
+    /* Process Unlocked */ 
+    __HAL_UNLOCK(hrtc);
+    
+    return HAL_ERROR;
+  } 
+  else
+  {
+    __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
+    
+    /* Exit Initialization mode */
+    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
+  }
+  
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables the Bypass Shadow feature.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.  
+  * @note   When the Bypass Shadow is enabled the calendar value are taken 
+  *         directly from the Calendar counter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
+{
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  /* Set the BYPSHAD bit */
+  hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
+  
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables the Bypass Shadow feature.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.  
+  * @note   When the Bypass Shadow is enabled the calendar value are taken 
+  *         directly from the Calendar counter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
+{
+  /* Process Locked */ 
+  __HAL_LOCK(hrtc);
+  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+  
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+  
+  /* Reset the BYPSHAD bit */
+  hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD;
+  
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+  
+  /* Process Unlocked */ 
+  __HAL_UNLOCK(hrtc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+  /** @defgroup RTCEx_Group4 Extended features functions 
+ *  @brief    Extended features functions  
+ *
+@verbatim   
+ ===============================================================================
+                 ##### Extended features functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) RTC Alram B callback
+      (+) RTC Poll for Alarm B request
+               
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Alarm B callback.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @retval None
+  */
+__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RTC_AlarmBEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  This function handles AlarmB Polling request.
+  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{  
+  uint32_t timeout = 0; 
+
+  /* Get Timeout value */
+  timeout = HAL_GetTick() + Timeout;   
+  
+  while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Clear the Alarm Flag */
+  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
+  
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY; 
+  
+  return HAL_OK; 
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rtc_ex.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,692 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_rtc_ex.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of RTC HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RTC_EX_H
+#define __STM32F4xx_HAL_RTC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RTCEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** 
+  * @brief  RTC Tamper structure definition  
+  */
+typedef struct 
+{
+  uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
+                                             This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */
+  
+  uint32_t PinSelection;                /*!< Specifies the Tamper Pin.
+                                             This parameter can be a value of @ref  RTCEx_Tamper_Pins_Selection */                                        
+                                             
+  uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
+                                             This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */
+
+  uint32_t Filter;                      /*!< Specifies the RTC Filter Tamper.
+                                             This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
+  
+  uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
+                                             This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
+                                      
+  uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .
+                                             This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */ 
+ 
+  uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .
+                                             This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */           
+ 
+  uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
+                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */                      
+}RTC_TamperTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup RTCEx_Backup_Registers_Definitions 
+  * @{
+  */
+#define RTC_BKP_DR0                       ((uint32_t)0x00000000)
+#define RTC_BKP_DR1                       ((uint32_t)0x00000001)
+#define RTC_BKP_DR2                       ((uint32_t)0x00000002)
+#define RTC_BKP_DR3                       ((uint32_t)0x00000003)
+#define RTC_BKP_DR4                       ((uint32_t)0x00000004)
+#define RTC_BKP_DR5                       ((uint32_t)0x00000005)
+#define RTC_BKP_DR6                       ((uint32_t)0x00000006)
+#define RTC_BKP_DR7                       ((uint32_t)0x00000007)
+#define RTC_BKP_DR8                       ((uint32_t)0x00000008)
+#define RTC_BKP_DR9                       ((uint32_t)0x00000009)
+#define RTC_BKP_DR10                      ((uint32_t)0x0000000A)
+#define RTC_BKP_DR11                      ((uint32_t)0x0000000B)
+#define RTC_BKP_DR12                      ((uint32_t)0x0000000C)
+#define RTC_BKP_DR13                      ((uint32_t)0x0000000D)
+#define RTC_BKP_DR14                      ((uint32_t)0x0000000E)
+#define RTC_BKP_DR15                      ((uint32_t)0x0000000F)
+#define RTC_BKP_DR16                      ((uint32_t)0x00000010)
+#define RTC_BKP_DR17                      ((uint32_t)0x00000011)
+#define RTC_BKP_DR18                      ((uint32_t)0x00000012)
+#define RTC_BKP_DR19                      ((uint32_t)0x00000013)
+
+#define IS_RTC_BKP(BKP)                   (((BKP) == RTC_BKP_DR0)  || \
+                                           ((BKP) == RTC_BKP_DR1)  || \
+                                           ((BKP) == RTC_BKP_DR2)  || \
+                                           ((BKP) == RTC_BKP_DR3)  || \
+                                           ((BKP) == RTC_BKP_DR4)  || \
+                                           ((BKP) == RTC_BKP_DR5)  || \
+                                           ((BKP) == RTC_BKP_DR6)  || \
+                                           ((BKP) == RTC_BKP_DR7)  || \
+                                           ((BKP) == RTC_BKP_DR8)  || \
+                                           ((BKP) == RTC_BKP_DR9)  || \
+                                           ((BKP) == RTC_BKP_DR10) || \
+                                           ((BKP) == RTC_BKP_DR11) || \
+                                           ((BKP) == RTC_BKP_DR12) || \
+                                           ((BKP) == RTC_BKP_DR13) || \
+                                           ((BKP) == RTC_BKP_DR14) || \
+                                           ((BKP) == RTC_BKP_DR15) || \
+                                           ((BKP) == RTC_BKP_DR16) || \
+                                           ((BKP) == RTC_BKP_DR17) || \
+                                           ((BKP) == RTC_BKP_DR18) || \
+                                           ((BKP) == RTC_BKP_DR19))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTCEx_Time_Stamp_Edges_definitions 
+  * @{
+  */ 
+#define RTC_TIMESTAMPEDGE_RISING          ((uint32_t)0x00000000)
+#define RTC_TIMESTAMPEDGE_FALLING         ((uint32_t)0x00000008)
+
+#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
+                                 ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
+/**
+  * @}
+  */
+  
+/** @defgroup RTCEx_Tamper_Pins_Definitions 
+  * @{
+  */ 
+#define RTC_TAMPER_1                    RTC_TAFCR_TAMP1E
+#define RTC_TAMPER_2                    RTC_TAFCR_TAMP2E
+
+#define IS_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFF6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_Pins_Selection 
+  * @{
+  */ 
+#define RTC_TAMPERPIN_PC13                 ((uint32_t)0x00000000)
+#define RTC_TAMPERPIN_PI8                  ((uint32_t)0x00010000)
+
+#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_PC13) || \
+                                ((PIN) == RTC_TAMPERPIN_PI8))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTCEx_TimeStamp_Pin_Selection 
+  * @{
+  */ 
+#define RTC_TIMESTAMPPIN_PC13              ((uint32_t)0x00000000)
+#define RTC_TIMESTAMPPIN_PI8               ((uint32_t)0x00020000)
+
+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_PC13) || \
+                                   ((PIN) == RTC_TIMESTAMPPIN_PI8))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTCEx_Tamper_Trigger_Definitions 
+  * @{
+  */ 
+#define RTC_TAMPERTRIGGER_RISINGEDGE       ((uint32_t)0x00000000)
+#define RTC_TAMPERTRIGGER_FALLINGEDGE      ((uint32_t)0x00000002)
+#define RTC_TAMPERTRIGGER_LOWLEVEL         RTC_TAMPERTRIGGER_RISINGEDGE
+#define RTC_TAMPERTRIGGER_HIGHLEVEL        RTC_TAMPERTRIGGER_FALLINGEDGE
+
+#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
+                                        ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
+                                        ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
+                                        ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) 
+
+/**
+  * @}
+  */  
+
+/** @defgroup RTCEx_Tamper_Filter_Definitions 
+  * @{
+  */ 
+#define RTC_TAMPERFILTER_DISABLE   ((uint32_t)0x00000000)  /*!< Tamper filter is disabled */
+
+#define RTC_TAMPERFILTER_2SAMPLE   ((uint32_t)0x00000800)  /*!< Tamper is activated after 2 
+                                                                consecutive samples at the active level */
+#define RTC_TAMPERFILTER_4SAMPLE   ((uint32_t)0x00001000)  /*!< Tamper is activated after 4 
+                                                                consecutive samples at the active level */
+#define RTC_TAMPERFILTER_8SAMPLE   ((uint32_t)0x00001800)  /*!< Tamper is activated after 8 
+                                                                consecutive samples at the active leve. */
+
+#define IS_TAMPER_FILTER(FILTER)  (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
+                                   ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
+                                   ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
+                                   ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions 
+  * @{
+  */ 
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  ((uint32_t)0x00000000)  /*!< Each of the tamper inputs are sampled
+                                                                             with a frequency =  RTCCLK / 32768 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  ((uint32_t)0x00000100)  /*!< Each of the tamper inputs are sampled
+                                                                             with a frequency =  RTCCLK / 16384 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   ((uint32_t)0x00000200)  /*!< Each of the tamper inputs are sampled
+                                                                             with a frequency =  RTCCLK / 8192  */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   ((uint32_t)0x00000300)  /*!< Each of the tamper inputs are sampled
+                                                                             with a frequency =  RTCCLK / 4096  */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   ((uint32_t)0x00000400)  /*!< Each of the tamper inputs are sampled
+                                                                             with a frequency =  RTCCLK / 2048  */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   ((uint32_t)0x00000500)  /*!< Each of the tamper inputs are sampled
+                                                                             with a frequency =  RTCCLK / 1024  */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    ((uint32_t)0x00000600)  /*!< Each of the tamper inputs are sampled
+                                                                             with a frequency =  RTCCLK / 512   */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    ((uint32_t)0x00000700)  /*!< Each of the tamper inputs are sampled
+                                                                             with a frequency =  RTCCLK / 256   */
+
+#define IS_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
+                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
+                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
+                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
+                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
+                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
+                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
+                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions 
+  * @{
+  */ 
+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 1 RTCCLK cycle */
+#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 2 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 4 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 8 RTCCLK cycles */
+
+#define IS_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
+                                                ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
+                                                ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
+                                                ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
+/**
+  * @}
+  */
+  
+/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions 
+  * @{
+  */ 
+#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE  ((uint32_t)RTC_TAFCR_TAMPTS)  /*!< TimeStamp on Tamper Detection event saved        */
+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000)        /*!< TimeStamp on Tamper Detection event is not saved */
+                                                                         
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
+                                                          ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+/**
+  * @}
+  */
+  
+/** @defgroup  RTCEx_Tamper_Pull_UP_Definitions
+  * @{
+  */ 
+#define RTC_TAMPER_PULLUP_ENABLE  ((uint32_t)0x00000000)            /*!< TimeStamp on Tamper Detection event saved        */
+#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS)   /*!< TimeStamp on Tamper Detection event is not saved */
+                                                                         
+#define IS_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
+                                       ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Wakeup_Timer_Definitions 
+  * @{
+  */ 
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV16        ((uint32_t)0x00000000)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV8         ((uint32_t)0x00000001)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV4         ((uint32_t)0x00000002)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV2         ((uint32_t)0x00000003)
+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      ((uint32_t)0x00000004)
+#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      ((uint32_t)0x00000006)
+
+#define IS_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)       || \
+                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
+                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
+                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
+                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
+                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
+
+#define IS_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
+/**
+  * @}
+  */ 
+
+/** @defgroup RTCEx_Digital_Calibration_Definitions 
+  * @{
+  */ 
+#define RTC_CALIBSIGN_POSITIVE            ((uint32_t)0x00000000) 
+#define RTC_CALIBSIGN_NEGATIVE            ((uint32_t)0x00000080)
+
+#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
+                                 ((SIGN) == RTC_CALIBSIGN_NEGATIVE))
+
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Smooth_calib_period_Definitions 
+  * @{
+  */ 
+#define RTC_SMOOTHCALIB_PERIOD_32SEC   ((uint32_t)0x00000000)  /*!< If RTCCLK = 32768 Hz, Smooth calibation
+                                                                    period is 32s,  else 2exp20 RTCCLK seconds */
+#define RTC_SMOOTHCALIB_PERIOD_16SEC   ((uint32_t)0x00002000)  /*!< If RTCCLK = 32768 Hz, Smooth calibation 
+                                                                    period is 16s, else 2exp19 RTCCLK seconds */
+#define RTC_SMOOTHCALIB_PERIOD_8SEC    ((uint32_t)0x00004000)  /*!< If RTCCLK = 32768 Hz, Smooth calibation 
+                                                                    period is 8s, else 2exp18 RTCCLK seconds */
+
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
+                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
+                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))                                         
+/**
+  * @}
+  */ 
+
+/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions 
+  * @{
+  */ 
+#define RTC_SMOOTHCALIB_PLUSPULSES_SET    ((uint32_t)0x00008000)  /*!< The number of RTCCLK pulses added  
+                                                                       during a X -second window = Y - CALM[8:0] 
+                                                                       with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET  ((uint32_t)0x00000000)  /*!< The number of RTCCLK pulses subbstited
+                                                                       during a 32-second window = CALM[8:0] */
+
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
+                                        ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTCEx_Smooth_calib_Minus_pulses_Definitions 
+  * @{
+  */ 
+#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions
+  * @{
+  */ 
+#define RTC_SHIFTADD1S_RESET      ((uint32_t)0x00000000)
+#define RTC_SHIFTADD1S_SET        ((uint32_t)0x80000000)
+
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
+                                 ((SEL) == RTC_SHIFTADD1S_SET))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value
+  * @{
+  */ 
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+/**
+  * @}
+  */
+
+ /** @defgroup RTCEx_Calib_Output_selection_Definitions 
+  * @{
+  */ 
+#define RTC_CALIBOUTPUT_512HZ            ((uint32_t)0x00000000) 
+#define RTC_CALIBOUTPUT_1HZ              ((uint32_t)0x00080000)
+
+#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
+                                      ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+  * @brief  Enable the RTC WakeUp Timer peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
+
+/**
+  * @brief  Enable the RTC TimeStamp peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                        ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
+
+/**
+  * @brief  Disable the RTC WakeUp Timer peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
+
+/**
+  * @brief  Disable the RTC TimeStamp peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
+
+/**
+  * @brief  Enable the Coarse calibration process.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE))
+
+/**
+  * @brief  Disable the Coarse calibration process.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE))
+
+/**
+  * @brief  Enable the RTC calibration output.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
+
+/**
+  * @brief  Disable the calibration output.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
+
+/**
+  * @brief  Enable the clock reference detection.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
+
+/**
+  * @brief  Disable the clock reference detection.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
+
+/**
+  * @brief  Enable the RTC TimeStamp interrupt.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. 
+  *         This parameter can be:
+  *            @arg RTC_IT_TS: TimeStamp interrupt
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+  * @brief  Enable the RTC WakeUpTimer interrupt.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. 
+  *         This parameter can be:
+  *            @arg RTC_IT_WUT: WakeUpTimer A interrupt
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the RTC TimeStamp interrupt.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. 
+  *         This parameter can be:
+  *            @arg RTC_IT_TS: TimeStamp interrupt
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Disable the RTC WakeUpTimer interrupt.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. 
+  *         This parameter can be:
+  *            @arg RTC_IT_WUT: WakeUpTimer A interrupt
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled.
+  *         This parameter can be:
+  *            @arg  RTC_IT_TAMP1  
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __FLAG__)                 (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
+
+/**
+  * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+  *         This parameter can be:
+  *            @arg RTC_IT_WUT:  WakeUpTimer A interrupt
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __FLAG__)            (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
+
+/**
+  * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+  *         This parameter can be:
+  *            @arg RTC_IT_TS: TimeStamp interrupt
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __FLAG__)              (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
+
+/**
+  * @brief  Get the selected RTC TimeStamp's flag status.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC TimeStamp Flag sources to be enabled or disabled.
+  *         This parameter can be:
+  *            @arg RTC_FLAG_TSF   
+  *            @arg RTC_FLAG_TSOVF     
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)            (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+  * @brief  Get the selected RTC WakeUpTimer's flag status.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC WakeUpTimer Flag sources to be enabled or disabled.
+  *          This parameter can be:
+  *             @arg RTC_FLAG_WUTF   
+  *             @arg RTC_FLAG_WUTWF     
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)          (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+  * @brief  Get the selected RTC Tamper's flag status.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+  *          This parameter can be:
+  *             @arg RTC_FLAG_TAMP1F      
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+  * @brief  Get the selected RTC shift operation's flag status.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC shift operation Flag is pending or not.
+  *          This parameter can be:
+  *             @arg RTC_FLAG_SHPF   
+  * @retval None
+  */
+#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+  * @brief  Clear the RTC Time Stamp's pending flags.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+  *          This parameter can be:
+  *             @arg RTC_FLAG_TSF  
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)              ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+  * @brief  Clear the RTC Tamper's pending flags.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+  *          This parameter can be:
+  *             @arg RTC_FLAG_TAMP1F  
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)                 ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+  * @brief  Clear the RTC Wake Up timer's pending flags.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+  *         This parameter can be:
+  *            @arg RTC_FLAG_WUTF   
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__)            ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) 
+
+/* Exported functions --------------------------------------------------------*/
+
+/* RTC TimeStamp and Tamper functions *****************************************/
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
+
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
+void              HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
+
+void       HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
+void       HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
+void       HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+
+/* RTC Wake-up functions ******************************************************/
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
+uint32_t          HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
+uint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
+void       HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+
+/* Extension Control functions ************************************************/
+void              HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
+uint32_t          HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
+
+HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
+
+/* Extension RTC features functions *******************************************/
+void       HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); 
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RTC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1364 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_sai.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   SAI HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Serial Audio Interface (SAI) peripheral:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+ ==============================================================================
+                  ##### How to use this driver #####
+  ==============================================================================
+           
+  [..]
+    The SAI HAL driver can be used as follows:
+    
+    (#) Declare a SAI_HandleTypeDef handle structure.
+    (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
+        (##) Enable the SAI interface clock.                      
+        (##) SAI pins configuration:
+            (+++) Enable the clock for the SAI GPIOs.
+            (+++) Configure these SAI pins as alternate function pull-up.
+        (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
+             and HAL_SAI_Receive_IT() APIs):
+            (+++) Configure the SAI interrupt priority.
+            (+++) Enable the NVIC SAI IRQ handle.
+
+        (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
+             and HAL_SAI_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx stream.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.                
+            (+++) Configure the DMA Tx/Rx Stream.
+            (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the 
+                DMA Tx/Rx Stream.
+  
+   (#) Program the SAI Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
+       using HAL_SAI_Init() function.
+   
+   -@- The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
+       will be managed using the macros __SAI_ENABLE_IT() and __SAI_DISABLE_IT()
+       inside the transmit and receive process.   
+       
+  [..]           
+   (@) Make sure that either:
+       (+@) I2S PLL is configured or 
+       (+@) SAI PLL is configured or 
+       (+@) External clock source is configured after setting correctly 
+            the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file. 
+                        
+  [..]           
+    (@) In master Tx mode: enabling the audio block immediately generates the bit clock 
+        for the external slaves even if there is no data in the FIFO, However FS signal 
+        generation is conditioned by the presence of data in the FIFO.
+                 
+  [..]           
+    (@) In master Rx mode: enabling the audio block immediately generates the bit clock 
+        and FS signal for the external slaves. 
+                
+  [..]           
+    (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior: 
+        (+@)  First bit Offset <= (SLOT size - Data size)
+        (+@)  Data size <= SLOT size
+        (+@)  Number of SLOT x SLOT size = Frame length
+        (+@)  The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.  
+
+  [..]         
+     Three operation modes are available within this driver :     
+  
+   *** Polling mode IO operation ***
+   =================================
+   [..]    
+     (+) Send an amount of data in blocking mode using HAL_SAI_Transmit() 
+     (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()
+   
+   *** Interrupt mode IO operation ***    
+   ===================================
+   [..]    
+     (+) Send an amount of data in non blocking mode using HAL_SAI_Transmit_IT() 
+     (+) At transmission end of transfer HAL_SAI_TxCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_SAI_TxCpltCallback
+     (+) Receive an amount of data in non blocking mode using HAL_SAI_Receive_IT() 
+     (+) At reception end of transfer HAL_SAI_RxCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_SAI_RxCpltCallback                                      
+     (+) In case of transfer Error, HAL_SAI_ErrorCallback() function is executed and user can 
+         add his own code by customization of function pointer HAL_SAI_ErrorCallback
+
+   *** DMA mode IO operation ***    
+   ==============================
+   [..] 
+     (+) Send an amount of data in non blocking mode (DMA) using HAL_SAI_Transmit_DMA() 
+     (+) At transmission end of transfer HAL_SAI_TxCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_SAI_TxCpltCallback
+     (+) Receive an amount of data in non blocking mode (DMA) using HAL_SAI_Receive_DMA() 
+     (+) At reception end of transfer HAL_SAI_RxCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_SAI_RxCpltCallback                                  
+     (+) In case of transfer Error, HAL_SAI_ErrorCallback() function is executed and user can 
+         add his own code by customization of function pointer HAL_SAI_ErrorCallback
+     (+) Pause the DMA Transfer using HAL_SAI_DMAPause()      
+     (+) Resume the DMA Transfer using HAL_SAI_DMAResume()  
+     (+) Stop the DMA Transfer using HAL_SAI_DMAStop()      
+   
+   *** SAI HAL driver macros list ***
+   ============================================= 
+   [..]
+     Below the list of most used macros in USART HAL driver :
+       
+      (+) __HAL_SAI_ENABLE: Enable the SAI peripheral
+      (+) __HAL_SAI_DISABLE: Disable the SAI peripheral
+      (+) __HAL_SAI_ENABLE_IT : Enable the specified SAI interrupts
+      (+) __HAL_SAI_DISABLE_IT : Disable the specified SAI interrupts
+      (+) __HAL_SAI_GET_IT_SOURCE: Check if the specified SAI interrupt source is 
+          enabled or disabled
+      (+) __HAL_SAI_GET_FLAG: Check whether the specified SAI flag is set or not
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SAI 
+  * @brief SAI HAL module driver
+  * @{
+  */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* SAI registers Masks */
+#define CR1_CLEAR_MASK            ((uint32_t)0xFF07C010)
+#define FRCR_CLEAR_MASK           ((uint32_t)0xFFF88000)
+#define SLOTR_CLEAR_MASK          ((uint32_t)0x0000F020)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMAError(DMA_HandleTypeDef *hdma);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SAI_Private_Functions
+  * @{
+  */
+
+/** @defgroup SAI_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and 
+          de-initialize the SAIx peripheral:
+
+      (+) User must implement HAL_SAI_MspInit() function in which he configures 
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_SAI_Init() to configure the selected device with 
+          the selected configuration:
+        (++) Mode (Master/slave TX/RX)
+        (++) Protocol 
+        (++) Data Size
+        (++) MCLK Output
+        (++) Audio frequency
+        (++) FIFO Threshold
+        (++) Frame Config
+        (++) Slot Config
+
+      (+) Call the function HAL_SAI_DeInit() to restore the default configuration 
+          of the selected SAI peripheral.     
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SAI according to the specified parameters 
+  *         in the SAI_InitTypeDef and create the associated handle.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
+{ 
+  uint32_t tmpreg = 0;
+  uint32_t tmpclock = 0, tmp2clock = 0;
+  /* This variable used to store the VCO Input (value in Hz) */
+  uint32_t vcoinput = 0;
+  /* This variable used to store the SAI_CK_x (value in Hz) */
+  uint32_t saiclocksource = 0;
+  
+  /* Check the SAI handle allocation */
+  if(hsai == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the SAI Block parameters */
+  assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));
+  assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));
+  assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));
+  assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));
+  assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));
+  assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));
+  assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));
+  assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));
+  assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));
+  assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
+  
+  /* Check the SAI Block Frame parameters */
+  assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));
+  assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength));
+  assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition));
+  assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity));
+  assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset));
+  
+  /* Check the SAI Block Slot parameters */
+  assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset));
+  assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize));
+  assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber));
+  assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive));
+  
+  if(hsai->State == HAL_SAI_STATE_RESET)
+  {
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_SAI_MspInit(hsai);
+  }
+  
+  hsai->State = HAL_SAI_STATE_BUSY;
+  
+  /* Disable the selected SAI peripheral */
+  __HAL_SAI_DISABLE(hsai);
+    
+  /* SAI Block Configuration ------------------------------------------------------------*/
+  /* SAI Block_x CR1 Configuration */
+  /* Get the SAI Block_x CR1 value */
+  tmpreg = hsai->Instance->CR1;
+  /* Clear MODE, PRTCFG, DS, LSBFIRST, CKSTR, SYNCEN, OUTDRIV, NODIV, and MCKDIV bits */
+  tmpreg &= CR1_CLEAR_MASK;
+  /* Configure SAI_Block_x: Audio Protocol, Data Size, first transmitted bit, Clock strobing 
+     edge, Synchronization mode, Output drive, Master Divider and FIFO level */  
+  /* Set PRTCFG bits according to Protocol value      */
+  /* Set DS bits according to DataSize value          */
+  /* Set LSBFIRST bit according to FirstBit value     */
+  /* Set CKSTR bit according to ClockStrobing value   */
+  /* Set SYNCEN bit according to Synchro value        */
+  /* Set OUTDRIV bit according to OutputDrive value   */
+  /* Set NODIV bit according to NoDivider value       */
+  tmpreg |= (uint32_t)(hsai->Init.Protocol      |
+                       hsai->Init.AudioMode     |
+                       hsai->Init.DataSize      | 
+                       hsai->Init.FirstBit      |  
+                       hsai->Init.ClockStrobing | 
+                       hsai->Init.Synchro       |  
+                       hsai->Init.OutputDrive   | 
+                       hsai->Init.NoDivider);      
+  /* Write to SAI_Block_x CR1 */
+  hsai->Instance->CR1 = tmpreg;
+  
+  /* SAI Block_x CR2 Configuration */
+  /* Get the SAIBlock_x CR2 value */
+  tmpreg = hsai->Instance->CR2;
+  /* Clear FTH bits */
+  tmpreg &= ~(SAI_xCR2_FTH);
+  /* Configure the FIFO Level */
+  /* Set FTH bits according to SAI_FIFOThreshold value */ 
+  tmpreg |= (uint32_t)(hsai->Init.FIFOThreshold);
+  /* Write to SAI_Block_x CR2 */
+  hsai->Instance->CR2 = tmpreg;
+
+  /* SAI Block_x Frame Configuration -----------------------------------------*/
+  /* Get the SAI Block_x FRCR value */
+  tmpreg = hsai->Instance->FRCR;
+  /* Clear FRL, FSALL, FSDEF, FSPOL, FSOFF bits */
+  tmpreg &= FRCR_CLEAR_MASK;
+  /* Configure SAI_Block_x Frame: Frame Length, Active Frame Length, Frame Synchronization
+     Definition, Frame Synchronization Polarity and Frame Synchronization Polarity */
+  /* Set FRL bits according to SAI_FrameLength value         */
+  /* Set FSALL bits according to SAI_ActiveFrameLength value */
+  /* Set FSDEF bit according to SAI_FSDefinition value       */
+  /* Set FSPOL bit according to SAI_FSPolarity value         */
+  /* Set FSOFF bit according to SAI_FSOffset value           */
+  tmpreg |= (uint32_t)((uint32_t)(hsai->FrameInit.FrameLength - 1)  | 
+                        hsai->FrameInit.FSOffset     | 
+                        hsai->FrameInit.FSDefinition | 
+                        hsai->FrameInit.FSPolarity   | 
+                        (uint32_t)((hsai->FrameInit.ActiveFrameLength - 1) << 8));
+
+  /* Write to SAI_Block_x FRCR */
+  hsai->Instance->FRCR = tmpreg;
+
+  /* SAI Block_x SLOT Configuration ------------------------------------------*/
+  /* Get the SAI Block_x SLOTR value */
+  tmpreg = hsai->Instance->SLOTR;
+  /* Clear FBOFF, SLOTSZ, NBSLOT, SLOTEN bits */
+  tmpreg &= SLOTR_CLEAR_MASK;
+  /* Configure SAI_Block_x Slot: First bit offset, Slot size, Number of Slot in  
+     audio frame and slots activated in audio frame */
+  /* Set FBOFF bits according to SAI_FirstBitOffset value  */
+  /* Set SLOTSZ bits according to SAI_SlotSize value       */
+  /* Set NBSLOT bits according to SAI_SlotNumber value     */
+  /* Set SLOTEN bits according to SAI_SlotActive value     */
+  tmpreg |= (uint32_t)(hsai->SlotInit.FirstBitOffset | 
+                       hsai->SlotInit.SlotSize       | 
+                       hsai->SlotInit.SlotActive     |    
+                       (uint32_t)((hsai->SlotInit.SlotNumber - 1) <<  8));
+
+  /* Write to SAI_Block_x SLOTR */
+  hsai->Instance->SLOTR = tmpreg;
+  
+  /* SAI Block_x Clock Configuration -----------------------------------------*/
+  /* Check the Clock parameters */
+  assert_param(IS_SAI_CLK_SOURCE(hsai->Init.ClockSource));
+
+  /* SAI Block clock source selection */
+  if(hsai->Instance == SAI1_Block_A)
+  {
+     __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(hsai->Init.ClockSource);
+  }
+  else
+  {
+     __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG((uint32_t)(hsai->Init.ClockSource << 2));
+  }
+  
+  /* VCO Input Clock value calculation */
+  if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+  {
+    /* In Case the PLL Source is HSI (Internal Clock) */
+    vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+  }
+  else
+  {
+    /* In Case the PLL Source is HSE (External Clock) */
+    vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+  }
+  
+  /* SAI_CLK_x : SAI Block Clock configuration for different clock sources selected */
+  if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLSAI)
+  {    
+    /* Configure the PLLI2S division factor */
+    /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+    /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+    /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+    tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
+    saiclocksource = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
+    
+    /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+    tmpreg = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8) + 1);
+    saiclocksource = saiclocksource/(tmpreg); 
+
+  }
+  else if(hsai->Init.ClockSource == SAI_CLKSOURCE_PLLI2S)
+  {        
+    /* Configure the PLLI2S division factor */
+    /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+    /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+    /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+    tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
+    saiclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
+    
+    /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+    tmpreg = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1); 
+    saiclocksource = saiclocksource/(tmpreg);
+  }
+  else /* sConfig->ClockSource == SAI_CLKSource_Ext */
+  {
+    /* Enable the External Clock selection */
+    __HAL_RCC_I2SCLK(RCC_I2SCLKSOURCE_EXT);
+    
+    saiclocksource = EXTERNAL_CLOCK_VALUE;
+  }
+  
+  /* Configure Master Clock using the following formula :
+     MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS
+     FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256
+     MCKDIV[3:0] = SAI_CK_x / FS * 512 */
+  if(hsai->Init.NoDivider == SAI_MASTERDIVIDER_ENABLED) 
+  { 
+    /* (saiclocksource x 10) to keep Significant digits */
+    tmpclock = (((saiclocksource * 10) / ((hsai->Init.AudioFrequency) * 512)));
+    
+    /* Get the result of modulo division */
+    tmp2clock = (tmpclock % 10);
+    
+    /* Round result to the nearest integer*/
+    if (tmp2clock > 8) 
+    {
+      tmpclock = ((tmpclock / 10) + 1);  
+    }
+    else 
+    {
+      tmpclock = (tmpclock / 10); 
+    }
+    /*Set MCKDIV value in CR1 register*/
+    hsai->Instance->CR1 |= (tmpclock << 20);
+
+  }
+
+  /* Initialise the error code */
+  hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+
+  /* Initialize the SAI state */
+  hsai->State= HAL_SAI_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the SAI peripheral. 
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
+{
+  /* Check the SAI handle allocation */
+  if(hsai == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  hsai->State = HAL_SAI_STATE_BUSY;
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_SAI_MspDeInit(hsai);
+
+  /* Initialize the error code */
+  hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+  
+  /* Initialize the SAI state */
+  hsai->State = HAL_SAI_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsai);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief SAI MSP Init.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SAI_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief SAI MSP DeInit.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SAI_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Group2 IO operation functions 
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+  ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the SAI data 
+    transfers.
+
+    (+) There are two modes of transfer:
+       (++) Blocking mode : The communication is performed in the polling mode. 
+            The status of all data processing is returned by the same function 
+            after finishing transfer.  
+       (++) No-Blocking mode : The communication is performed using Interrupts 
+            or DMA. These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the 
+            dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when 
+            using DMA mode.
+
+    (+) Blocking mode functions are :
+        (++) HAL_SAI_Transmit()
+        (++) HAL_SAI_Receive()
+        (++) HAL_SAI_TransmitReceive()
+        
+    (+) Non Blocking mode functions with Interrupt are :
+        (++) HAL_SAI_Transmit_IT()
+        (++) HAL_SAI_Receive_IT()
+        (++) HAL_SAI_TransmitReceive_IT()
+
+    (+) Non Blocking mode functions with DMA are :
+        (++) HAL_SAI_Transmit_DMA()
+        (++) HAL_SAI_Receive_DMA()
+        (++) HAL_SAI_TransmitReceive_DMA()
+
+    (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_SAI_TxCpltCallback()
+        (++) HAL_SAI_RxCpltCallback()
+        (++) HAL_SAI_ErrorCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits an amount of data in blocking mode.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint16_t* pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t timeout = 0x00; 
+  
+  if((pData == NULL ) || (Size == 0)) 
+  {
+    return  HAL_ERROR;
+  }
+  
+  if(hsai->State == HAL_SAI_STATE_READY)
+  {  
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+    
+    hsai->State = HAL_SAI_STATE_BUSY_TX;
+   
+    /* Check if the SAI is already enabled */ 
+    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
+    {
+      /* Enable SAI peripheral */    
+      __HAL_SAI_ENABLE(hsai);
+    }
+    
+    while(Size > 0)
+    { 
+      /* Wait the FIFO to be empty */
+      /* Get timeout */
+      timeout = HAL_GetTick() + Timeout; 
+      while(__HAL_SAI_GET_FLAG(hsai, SAI_xSR_FREQ) == RESET)
+      {
+        /* Check for the Timeout */
+        if(Timeout != HAL_MAX_DELAY)
+        {
+          if(HAL_GetTick() >= timeout)
+          {         
+            
+            /* Update error code */
+            hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+            
+            /* Process Unlocked */
+            __HAL_UNLOCK(hsai);
+            
+            /* Change the SAI state */
+            hsai->State = HAL_SAI_STATE_TIMEOUT;
+            
+            return HAL_TIMEOUT;
+          }
+        } 
+      } 
+      hsai->Instance->DR = (*pData++);
+      Size--; 
+    }      
+      
+    hsai->State = HAL_SAI_STATE_READY; 
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives an amount of data in blocking mode. 
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be received
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t timeout = 0x00;
+ 
+  if((pData == NULL ) || (Size == 0)) 
+  {
+    return  HAL_ERROR;
+  }
+  
+  if(hsai->State == HAL_SAI_STATE_READY)
+  { 
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+    
+    hsai->State = HAL_SAI_STATE_BUSY_RX;
+        
+    /* Check if the SAI is already enabled */ 
+    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
+    {
+      /* Enable SAI peripheral */    
+      __HAL_SAI_ENABLE(hsai);
+    }
+       
+    /* Receive data */
+    while(Size > 0)
+    {
+      /* Wait until RXNE flag is set */
+      /* Get timeout */
+      timeout = HAL_GetTick() + Timeout; 
+      
+      while(__HAL_SAI_GET_FLAG(hsai, SAI_xSR_FREQ) == RESET)
+      {
+        /* Check for the Timeout */
+        if(Timeout != HAL_MAX_DELAY)
+        {
+          if(HAL_GetTick() >= timeout)
+          {         
+            
+            /* Update error code */
+            hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+            
+            /* Process Unlocked */
+            __HAL_UNLOCK(hsai);
+            
+            /* Change the SAI state */
+            hsai->State = HAL_SAI_STATE_TIMEOUT;
+            
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      
+      (*pData++) = hsai->Instance->DR;
+      Size--; 
+    }      
+
+    hsai->State = HAL_SAI_STATE_READY; 
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmits an amount of data in no-blocking mode with Interrupt.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size)
+{
+ if(hsai->State == HAL_SAI_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0)) 
+    {
+      return  HAL_ERROR;
+    }
+    
+    hsai->pTxBuffPtr = pData;
+    hsai->TxXferSize = Size;
+    hsai->TxXferCount = Size;
+    
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+    
+    hsai->State = HAL_SAI_STATE_BUSY_TX;
+    
+    /* Transmit data */
+    hsai->Instance->DR = (*hsai->pTxBuffPtr++);
+    hsai->TxXferCount--;
+      
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+    
+    /* Enable FRQ and OVRUDR interrupts */
+    __HAL_SAI_ENABLE_IT(hsai, (SAI_IT_FREQ | SAI_IT_OVRUDR));
+      
+    /* Check if the SAI is already enabled */ 
+    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
+    {
+      /* Enable SAI peripheral */    
+      __HAL_SAI_ENABLE(hsai);
+    }
+
+   
+    return HAL_OK;
+  }
+  else if(hsai->State == HAL_SAI_STATE_BUSY_TX)
+  {   
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+    
+    /* Transmit data */
+    hsai->Instance->DR = (*hsai->pTxBuffPtr++);
+    
+    hsai->TxXferCount--;	
+    
+    if(hsai->TxXferCount == 0)
+    {
+      /* Disable FREQ and OVRUDR interrupts */
+      __HAL_SAI_DISABLE_IT(hsai, (SAI_IT_FREQ | SAI_IT_OVRUDR));
+      
+      hsai->State = HAL_SAI_STATE_READY;
+      
+      HAL_SAI_TxCpltCallback(hsai);
+    }
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+    
+    return HAL_OK;
+  }
+  
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives an amount of data in no-blocking mode with Interrupt.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size)
+{
+  if(hsai->State == HAL_SAI_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0)) 
+    {
+      return  HAL_ERROR;
+    }
+    
+    hsai->pRxBuffPtr = pData;
+    hsai->RxXferSize = Size;
+    hsai->RxXferCount = Size;
+    
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+    
+    hsai->State = HAL_SAI_STATE_BUSY_RX;
+
+    /* Enable TXE and OVRUDR interrupts */
+    __HAL_SAI_ENABLE_IT(hsai, (SAI_IT_FREQ | SAI_IT_OVRUDR));
+    
+    /* Check if the SAI is already enabled */ 
+    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
+    {
+      /* Enable SAI peripheral */    
+      __HAL_SAI_ENABLE(hsai);
+    }
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+    
+    return HAL_OK;
+  }
+  else if(hsai->State == HAL_SAI_STATE_BUSY_RX)
+  {
+     /* Process Locked */
+    __HAL_LOCK(hsai);
+    
+    /* Receive data */    
+    (*hsai->pRxBuffPtr++) = hsai->Instance->DR;
+    
+    hsai->RxXferCount--;
+    
+    if(hsai->RxXferCount == 0)
+    {    
+      /* Disable TXE and OVRUDR interrupts */
+      __HAL_SAI_DISABLE_IT(hsai, (SAI_IT_FREQ | SAI_IT_OVRUDR));
+      
+      hsai->State = HAL_SAI_STATE_READY;     
+      HAL_SAI_RxCpltCallback(hsai); 
+    }
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+    
+    return HAL_OK;
+  }
+
+  else
+  {
+    return HAL_BUSY; 
+  } 
+}
+
+/**
+  * @brief Pauses the audio stream playing from the Media.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsai);
+  
+  /* Pause the audio file playing by disabling the SAI DMA requests */
+  hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+  
+ 
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsai);
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief Resumes the audio stream playing from the Media.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsai);
+  
+  /* Enable the SAI DMA requests */
+  hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+  
+  
+  /* If the SAI peripheral is still not enabled, enable it */
+  if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0)
+  {
+    /* Enable SAI peripheral */    
+    __HAL_SAI_ENABLE(hsai);
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsai);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief Stops the audio stream playing from the Media.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsai);
+  
+  /* Disable the SAI DMA request */
+  hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+  
+  /* Abort the SAI DMA Tx Stream */
+  if(hsai->hdmatx != NULL)
+  {
+    HAL_DMA_Abort(hsai->hdmatx);
+  }
+  /* Abort the SAI DMA Rx Stream */
+  if(hsai->hdmarx != NULL)
+  {  
+    HAL_DMA_Abort(hsai->hdmarx);
+  }
+
+  /* Disable SAI peripheral */
+  __HAL_SAI_DISABLE(hsai);
+  
+  hsai->State = HAL_SAI_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsai);
+  
+  return HAL_OK;
+}
+/**
+  * @brief  Transmits an amount of data in no-blocking mode with DMA.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size)
+{
+  uint32_t *tmp;
+
+  if((pData == NULL) || (Size == 0)) 
+  {
+    return  HAL_ERROR;
+  }
+
+  if(hsai->State == HAL_SAI_STATE_READY)
+  {  
+    hsai->pTxBuffPtr = pData;
+    hsai->TxXferSize = Size;
+    hsai->TxXferCount = Size;
+
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+
+    hsai->State = HAL_SAI_STATE_BUSY_TX;
+
+    /* Set the SAI Tx DMA Half transfert complete callback */
+    hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;
+
+    /* Set the SAI TxDMA transfer complete callback */
+    hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;
+
+    /* Set the DMA error callback */
+    hsai->hdmatx->XferErrorCallback = SAI_DMAError;
+
+    /* Enable the Tx DMA Stream */
+    tmp = (uint32_t*)&pData;
+    HAL_DMA_Start_IT(hsai->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsai->Instance->DR, hsai->TxXferSize);
+
+    /* Check if the SAI is already enabled */ 
+    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
+    {
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+
+    /* Enable SAI Tx DMA Request */  
+    hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives an amount of data in no-blocking mode with DMA. 
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size)
+{
+  uint32_t *tmp;
+  
+  if((pData == NULL) || (Size == 0))
+  {
+    return  HAL_ERROR;
+  } 
+    
+  if(hsai->State == HAL_SAI_STATE_READY)
+  {    
+    hsai->pRxBuffPtr = pData;
+    hsai->RxXferSize = Size;
+    hsai->RxXferCount = Size;
+
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+    
+    hsai->State = HAL_SAI_STATE_BUSY_RX;
+
+    /* Set the SAI Rx DMA Half transfert complete callback */
+    hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;
+
+    /* Set the SAI Rx DMA transfert complete callback */
+    hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;
+
+    /* Set the DMA error callback */
+    hsai->hdmarx->XferErrorCallback = SAI_DMAError;
+
+    /* Enable the Rx DMA Stream */
+    tmp = (uint32_t*)&pData;
+    HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, *(uint32_t*)tmp, hsai->RxXferSize);
+
+    /* Check if the SAI is already enabled */
+    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != SAI_xCR1_SAIEN)
+    {
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+
+    /* Enable SAI Rx DMA Request */
+    hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  This function handles SAI interrupt request.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval HAL status
+  */
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
+{
+  uint32_t tmp1 = 0, tmp2 = 0; 
+  
+  if(hsai->State == HAL_SAI_STATE_BUSY_RX)
+  {
+    tmp1 = __HAL_SAI_GET_FLAG(hsai, SAI_xSR_FREQ);
+    tmp2 = __HAL_SAI_GET_IT_SOURCE(hsai, SAI_IT_FREQ);
+    /* SAI in mode Receiver --------------------------------------------------*/
+    if((tmp1  != RESET) && (tmp2 != RESET))
+    {
+      HAL_SAI_Receive_IT(hsai, NULL, 0);
+    }
+
+    tmp1 = __HAL_SAI_GET_FLAG(hsai, SAI_FLAG_OVRUDR);
+    tmp2 = __HAL_SAI_GET_IT_SOURCE(hsai, SAI_IT_OVRUDR);
+    /* SAI Overrun error interrupt occurred ----------------------------------*/
+    if((tmp1 != RESET) && (tmp2 != RESET))
+    {
+      /* Change the SAI error code */
+      hsai->ErrorCode = HAL_SAI_ERROR_OVR;
+
+      /* Clear the SAI Overrun flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+      /* Set the SAI state ready to be able to start again the process */
+      hsai->State = HAL_SAI_STATE_READY;
+      HAL_SAI_ErrorCallback(hsai);
+    }
+  }
+  
+  if(hsai->State == HAL_SAI_STATE_BUSY_TX)
+  {  
+    tmp1 = __HAL_SAI_GET_FLAG(hsai, SAI_xSR_FREQ);
+    tmp2 = __HAL_SAI_GET_IT_SOURCE(hsai, SAI_IT_FREQ);
+    /* SAI in mode Transmitter -----------------------------------------------*/
+    if((tmp1 != RESET) && (tmp2 != RESET))
+    {     
+      HAL_SAI_Transmit_IT(hsai, NULL, 0);
+    } 
+    
+    tmp1 = __HAL_SAI_GET_FLAG(hsai, SAI_FLAG_OVRUDR);
+    tmp2 = __HAL_SAI_GET_IT_SOURCE(hsai, SAI_IT_OVRUDR);
+    /* SAI Underrun error interrupt occurred ---------------------------------*/
+    if((tmp1 != RESET) && (tmp2 != RESET))
+    {
+      /* Change the SAI error code */
+      hsai->ErrorCode = HAL_SAI_ERROR_UDR;
+
+      /* Clear the SAI Underrun flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+      /* Set the SAI state ready to be able to start again the process */
+      hsai->State = HAL_SAI_STATE_READY;
+      HAL_SAI_ErrorCallback(hsai);
+    }
+  } 
+}
+
+/**
+  * @brief Tx Transfer completed callbacks.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+ __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SAI_TxCpltCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief Tx Transfer Half completed callbacks
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+ __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SAI_TxHalfCpltCallback could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @brief Rx Transfer completed callbacks.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SAI_RxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer half completed callbacks
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SAI_RxCpltCallback could be implenetd in the user file
+   */
+}
+
+/**
+  * @brief SAI error callbacks.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SAI_ErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup SAI_Group3 Peripheral State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+ ===============================================================================
+                ##### Peripheral State and Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the SAI state.
+  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval HAL state
+  */
+HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
+{
+  return hsai->State;
+}
+
+/**
+* @brief  Return the SAI error code
+* @param  hsai : pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for the specified SAI Block.
+* @retval SAI Error Code
+*/
+uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
+{
+  return hsai->ErrorCode;
+}
+/**
+  * @}
+  */
+
+/**
+  * @brief DMA SAI transmit process complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)   
+{
+  uint32_t timeout = 0x00;
+  
+  SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent;
+
+  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+  { 
+    hsai->TxXferCount = 0;
+    hsai->RxXferCount = 0;
+    
+    /* Disable SAI Tx DMA Request */  
+    hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
+
+    /* Set timeout: 10 is the max delay to send the remaining data in the SAI FIFO */
+    timeout = HAL_GetTick() + 10;
+    
+    /* Wait until FIFO is empty */    
+    while(__HAL_SAI_GET_FLAG(hsai, SAI_xSR_FLVL) != RESET)
+    {
+      /* Check for the Timeout */
+      if(HAL_GetTick() >= timeout)
+      {         
+        /* Update error code */
+        hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+        
+        /* Change the SAI state */
+        HAL_SAI_ErrorCallback(hsai);
+      }
+    } 
+    
+    hsai->State= HAL_SAI_STATE_READY;
+  }
+  HAL_SAI_TxCpltCallback(hsai);
+}
+
+/**
+  * @brief DMA SAI transmit process half complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  HAL_SAI_TxHalfCpltCallback(hsai);
+}
+
+/**
+  * @brief DMA SAI receive process complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)   
+{
+  SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+  {
+    /* Disable Rx DMA Request */
+    hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
+    hsai->RxXferCount = 0;
+    
+    hsai->State = HAL_SAI_STATE_READY;
+  }
+  HAL_SAI_RxCpltCallback(hsai); 
+}
+
+/**
+  * @brief DMA SAI receive process half complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  HAL_SAI_RxHalfCpltCallback(hsai); 
+}
+/**
+  * @brief DMA SAI communication error callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMAError(DMA_HandleTypeDef *hdma)   
+{
+  SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  /* Set the SAI state ready to be able to start again the process */
+  hsai->State= HAL_SAI_STATE_READY;
+  HAL_SAI_ErrorCallback(hsai);
+  
+  hsai->TxXferCount = 0;
+  hsai->RxXferCount = 0;
+}
+
+/**
+  * @}
+  */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* HAL_SAI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sai.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,768 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_sai.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of SAI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SAI_H
+#define __STM32F4xx_HAL_SAI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"  
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SAI
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** 
+  * @brief  SAI Init Structure definition  
+  */
+typedef struct
+{                                    
+  uint32_t Protocol;        /*!< Specifies the SAI Block protocol.
+                                 This parameter can be a value of @ref SAI_Block_Protocol             */
+                                      
+  uint32_t AudioMode;       /*!< Specifies the SAI Block audio Mode. 
+                                 This parameter can be a value of @ref SAI_Block_Mode                 */
+
+  uint32_t DataSize;        /*!< Specifies the SAI Block data size.
+                                 This parameter can be a value of @ref SAI_Block_Data_Size            */
+
+  uint32_t FirstBit;        /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                 This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
+
+  uint32_t ClockStrobing;   /*!< Specifies the SAI Block clock strobing edge sensitivity.
+                                 This parameter can be a value of @ref SAI_Block_Clock_Strobing       */
+
+  uint32_t Synchro;         /*!< Specifies SAI Block synchronization
+                                 This parameter can be a value of @ref SAI_Block_Synchronization      */
+ 
+  uint32_t OutputDrive;     /*!< Specifies when SAI Block outputs are driven.
+                                 This parameter can be a value of @ref SAI_Block_Output_Drive
+                                 @note this value has to be set before enabling the audio block  
+                                       but after the audio block configuration.                       */
+
+  uint32_t NoDivider;       /*!< Specifies whether master clock will be divided or not.
+                                 This parameter can be a value of @ref SAI_Block_NoDivider
+                                 @note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length 
+                                        should be aligned to a number equal to a power of 2, from 8 to 256.
+                                        If bit NODIV in the SAI_xCR1 register is set, the frame length can 
+                                        take any of the values without constraint since the input clock of 
+                                        the audio block should be equal to the bit clock.
+                                        There is no MCLK_x clock which can be output.                 */
+  
+  uint32_t FIFOThreshold;   /*!< Specifies SAI Block FIFO threshold.
+                                 This parameter can be a value of @ref SAI_Block_Fifo_Threshold       */
+
+  uint32_t ClockSource;     /*!< Specifies the SAI Block x Clock source.    
+                                 This parameter can be a value of @ref SAI_Clock_Source 
+                                 @note: If ClockSource is equal to SAI_CLKSource_Ext, the PLLI2S 
+                                       and PLLSAI divisions factors will be ignored.                  */ 
+                                     
+  uint32_t AudioFrequency;  /*!< Specifies the audio frequency sampling.     
+                                 This parameter can be a value of @ref SAI_Audio_Frequency            */
+                                                                                                                              
+}SAI_InitTypeDef;
+
+/** 
+  * @brief  SAI Block Frame Init structure definition  
+  */
+ 
+typedef struct
+{
+
+  uint32_t FrameLength;         /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
+                                     This parameter must be a number between Min_Data = 8 and Max_Data = 256.
+                                     @note: If master clock MCLK_x pin is declared as an output, the frame length
+                                            should be aligned to a number equal to power of 2 in order to keep 
+                                            in an audio frame, an integer number of MCLK pulses by bit Clock. */                                               
+                                                                            
+  uint32_t ActiveFrameLength;  /*!< Specifies the Frame synchronization active level length.
+                                    This Parameter specifies the length in number of bit clock (SCK + 1)  
+                                    of the active level of FS signal in audio frame.
+                                    This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+                                         
+  uint32_t FSDefinition;       /*!< Specifies the Frame synchronization definition.
+                                    This parameter can be a value of @ref SAI_Block_FS_Definition             */
+                                         
+  uint32_t FSPolarity;         /*!< Specifies the Frame synchronization Polarity.
+                                    This parameter can be a value of @ref SAI_Block_FS_Polarity               */
+
+  uint32_t FSOffset;           /*!< Specifies the Frame synchronization Offset.
+                                    This parameter can be a value of @ref SAI_Block_FS_Offset                 */
+
+}SAI_FrameInitTypeDef;
+
+/**
+  * @brief   SAI Block Slot Init Structure definition
+  */    
+
+typedef struct
+{
+  uint32_t FirstBitOffset;  /*!< Specifies the position of first data transfer bit in the slot.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
+
+  uint32_t SlotSize;        /*!< Specifies the Slot Size.
+                                 This parameter can be a value of @ref SAI_Block_Slot_Size              */
+
+  uint32_t SlotNumber;      /*!< Specifies the number of slot in the audio frame.
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+
+  uint32_t SlotActive;      /*!< Specifies the slots in audio frame that will be activated.
+                                 This parameter can be a value of @ref SAI_Block_Slot_Active            */
+}SAI_SlotInitTypeDef;
+
+/** 
+  * @brief  HAL State structures definition  
+  */ 
+typedef enum
+{
+  HAL_SAI_STATE_RESET      = 0x00,  /*!< SAI not yet initialized or disabled                */
+  HAL_SAI_STATE_READY      = 0x01,  /*!< SAI initialized and ready for use                  */
+  HAL_SAI_STATE_BUSY       = 0x02,  /*!< SAI internal process is ongoing                    */
+  HAL_SAI_STATE_BUSY_TX    = 0x12,  /*!< Data transmission process is ongoing               */ 
+  HAL_SAI_STATE_BUSY_RX    = 0x22,  /*!< Data reception process is ongoing                  */  
+  HAL_SAI_STATE_TIMEOUT    = 0x03,  /*!< SAI timeout state                                  */
+  HAL_SAI_STATE_ERROR      = 0x04   /*!< SAI error state                                    */
+                                                                        
+}HAL_SAI_StateTypeDef;
+
+/** 
+  * @brief  SAI handle Structure definition  
+  */
+typedef struct
+{
+  SAI_Block_TypeDef         *Instance;  /*!< SAI Blockx registers base address        */
+
+  SAI_InitTypeDef           Init;       /*!< SAI communication parameters             */
+
+  SAI_FrameInitTypeDef      FrameInit;  /*!< SAI Frame configuration parameters       */
+
+  SAI_SlotInitTypeDef       SlotInit;   /*!< SAI Slot configuration parameters        */
+
+  uint16_t                  *pTxBuffPtr; /*!< Pointer to SAI Tx transfer Buffer       */
+
+  uint16_t                  TxXferSize;  /*!< SAI Tx transfer size                    */
+
+  uint16_t                  TxXferCount; /*!< SAI Tx transfer counter                 */
+
+  uint16_t                  *pRxBuffPtr; /*!< Pointer to SAI Rx transfer buffer       */
+
+  uint16_t                  RxXferSize;  /*!< SAI Rx transfer size                    */
+
+  uint16_t                  RxXferCount; /*!< SAI Rx transfer counter                 */
+
+  DMA_HandleTypeDef         *hdmatx;     /*!< SAI Tx DMA handle parameters            */
+
+  DMA_HandleTypeDef         *hdmarx;     /*!< SAI Rx DMA handle parameters            */
+
+  HAL_LockTypeDef           Lock;        /*!< SAI locking object                      */
+
+  __IO HAL_SAI_StateTypeDef State;       /*!< SAI communication state                 */
+
+  __IO uint32_t             ErrorCode;   /*!< SAI Error code                          */
+}SAI_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SAI_Exported_Constants
+  * @{
+  */
+/** @defgroup SAI Error Code 
+  * @{
+  */ 
+#define HAL_SAI_ERROR_NONE      ((uint32_t)0x00000000)     /*!< No error             */
+#define HAL_SAI_ERROR_OVR       ((uint32_t)0x00000001)     /*!< Overrun Error        */
+#define HAL_SAI_ERROR_UDR       ((uint32_t)0x00000002)     /*!< Underrun error       */
+#define HAL_SAI_ERROR_TIMEOUT   ((uint32_t)0x00000020)     /*!< Timeout error        */
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Clock_Source
+  * @{
+  */
+#define SAI_CLKSOURCE_PLLSAI             ((uint32_t)RCC_SAIACLKSOURCE_PLLSAI)
+#define SAI_CLKSOURCE_PLLI2S             ((uint32_t)RCC_SAIACLKSOURCE_PLLI2S)
+#define SAI_CLKSOURCE_EXT                ((uint32_t)RCC_SAIACLKSOURCE_EXT)
+
+#define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLSAI) ||\
+                                   ((SOURCE) == SAI_CLKSOURCE_PLLI2S) ||\
+                                   ((SOURCE) == SAI_CLKSOURCE_EXT))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Audio_Frequency
+  * @{
+  */
+#define SAI_AUDIO_FREQUENCY_192K          ((uint32_t)192000)
+#define SAI_AUDIO_FREQUENCY_96K           ((uint32_t)96000)
+#define SAI_AUDIO_FREQUENCY_48K           ((uint32_t)48000)
+#define SAI_AUDIO_FREQUENCY_44K           ((uint32_t)44100)
+#define SAI_AUDIO_FREQUENCY_32K           ((uint32_t)32000)
+#define SAI_AUDIO_FREQUENCY_22K           ((uint32_t)22050)
+#define SAI_AUDIO_FREQUENCY_16K           ((uint32_t)16000)
+#define SAI_AUDIO_FREQUENCY_11K           ((uint32_t)11025)
+#define SAI_AUDIO_FREQUENCY_8K            ((uint32_t)8000)    
+
+#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_8K))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Mode 
+  * @{
+  */
+#define SAI_MODEMASTER_TX         ((uint32_t)0x00000000)
+#define SAI_MODEMASTER_RX         ((uint32_t)0x00000001)
+#define SAI_MODESLAVE_TX          ((uint32_t)0x00000002)
+#define SAI_MODESLAVE_RX          ((uint32_t)0x00000003)
+#define IS_SAI_BLOCK_MODE(MODE)    (((MODE) == SAI_MODEMASTER_TX) || \
+                                    ((MODE) == SAI_MODEMASTER_RX) || \
+                                    ((MODE) == SAI_MODESLAVE_TX)  || \
+                                    ((MODE) == SAI_MODESLAVE_RX))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Protocol 
+  * @{
+  */
+
+#define SAI_FREE_PROTOCOL                 ((uint32_t)0x00000000)
+#define SAI_AC97_PROTOCOL                 ((uint32_t)SAI_xCR1_PRTCFG_1)
+
+#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL)  || \
+                                         ((PROTOCOL) == SAI_AC97_PROTOCOL))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Data_Size 
+  * @{
+  */
+#define SAI_DATASIZE_8                   ((uint32_t)0x00000040)
+#define SAI_DATASIZE_10                  ((uint32_t)0x00000060)
+#define SAI_DATASIZE_16                  ((uint32_t)0x00000080)
+#define SAI_DATASIZE_20                  ((uint32_t)0x000000A0)
+#define SAI_DATASIZE_24                  ((uint32_t)0x000000C0)
+#define SAI_DATASIZE_32                  ((uint32_t)0x000000E0)
+
+#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8)  || \
+                                         ((DATASIZE) == SAI_DATASIZE_10) || \
+                                         ((DATASIZE) == SAI_DATASIZE_16) || \
+                                         ((DATASIZE) == SAI_DATASIZE_20) || \
+                                         ((DATASIZE) == SAI_DATASIZE_24) || \
+                                         ((DATASIZE) == SAI_DATASIZE_32))
+/**
+  * @}
+  */ 
+
+/** @defgroup SAI_Block_MSB_LSB_transmission 
+  * @{
+  */
+
+#define SAI_FIRSTBIT_MSB                  ((uint32_t)0x00000000)
+#define SAI_FIRSTBIT_LSB                  ((uint32_t)SAI_xCR1_LSBFIRST)
+
+#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
+                                     ((BIT) == SAI_FIRSTBIT_LSB))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Clock_Strobing 
+  * @{
+  */
+#define SAI_CLOCKSTROBING_FALLINGEDGE     ((uint32_t)0x00000000)
+#define SAI_CLOCKSTROBING_RISINGEDGE      ((uint32_t)SAI_xCR1_CKSTR)
+
+#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
+                                            ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Synchronization 
+  * @{
+  */
+#define SAI_ASYNCHRONOUS                  ((uint32_t)0x00000000)
+#define SAI_SYNCHRONOUS                   ((uint32_t)SAI_xCR1_SYNCEN_0)
+
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS))
+/**
+  * @}
+  */ 
+
+/** @defgroup SAI_Block_Output_Drive 
+  * @{
+  */
+#define SAI_OUTPUTDRIVE_DISABLED          ((uint32_t)0x00000000)
+#define SAI_OUTPUTDRIVE_ENABLED           ((uint32_t)SAI_xCR1_OUTDRIV)
+
+#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLED) || \
+                                          ((DRIVE) == SAI_OUTPUTDRIVE_ENABLED))
+/**
+  * @}
+  */ 
+
+/** @defgroup SAI_Block_NoDivider 
+  * @{
+  */
+#define SAI_MASTERDIVIDER_ENABLED         ((uint32_t)0x00000000)
+#define SAI_MASTERDIVIDER_DISABLED        ((uint32_t)SAI_xCR1_NODIV)
+
+#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLED) || \
+                                           ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLED))
+/**
+  * @}
+  */
+  
+/** @defgroup SAI_Block_Master_Divider 
+  * @{
+  */
+#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
+/**
+  * @}
+  */
+  
+/** @defgroup SAI_Block_Frame_Length 
+  * @{
+  */
+#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
+/**
+  * @}
+  */
+    
+/** @defgroup SAI_Block_Active_FrameLength 
+  * @{
+  */
+#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_FS_Definition 
+  * @{
+  */
+#define SAI_FS_STARTFRAME                 ((uint32_t)0x00000000)
+#define SAI_FS_CHANNEL_IDENTIFICATION     ((uint32_t)SAI_xFRCR_FSDEF)
+
+#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
+                                                ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_FS_Polarity 
+  * @{
+  */
+#define SAI_FS_ACTIVE_LOW                  ((uint32_t)0x00000000)
+#define SAI_FS_ACTIVE_HIGH                 ((uint32_t)SAI_xFRCR_FSPO)
+
+#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
+                                            ((POLARITY) == SAI_FS_ACTIVE_HIGH))
+/**
+  * @}
+  */
+            
+/** @defgroup SAI_Block_FS_Offset 
+  * @{
+  */
+#define SAI_FS_FIRSTBIT                   ((uint32_t)0x00000000)
+#define SAI_FS_BEFOREFIRSTBIT             ((uint32_t)SAI_xFRCR_FSOFF)
+
+#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
+                                        ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
+/**
+  * @}
+  */
+  
+/** @defgroup SAI_Block_Slot_FirstBit_Offset
+  * @{
+  */
+#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
+/**
+  * @}
+  */
+
+  /** @defgroup SAI_Block_Slot_Size
+  * @{
+  */
+#define SAI_SLOTSIZE_DATASIZE             ((uint32_t)0x00000000)  
+#define SAI_SLOTSIZE_16B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
+#define SAI_SLOTSIZE_32B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
+
+#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
+                                      ((SIZE) == SAI_SLOTSIZE_16B)      || \
+                                      ((SIZE) == SAI_SLOTSIZE_32B))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Slot_Number
+  * @{
+  */
+#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
+/**
+  * @}
+  */
+  
+/** @defgroup SAI_Block_Slot_Active
+  * @{
+  */
+#define SAI_SLOT_NOTACTIVE           ((uint32_t)0x00000000)
+#define SAI_SLOTACTIVE_0             ((uint32_t)0x00010000)
+#define SAI_SLOTACTIVE_1             ((uint32_t)0x00020000)
+#define SAI_SLOTACTIVE_2             ((uint32_t)0x00040000)
+#define SAI_SLOTACTIVE_3             ((uint32_t)0x00080000)
+#define SAI_SLOTACTIVE_4             ((uint32_t)0x00100000)
+#define SAI_SLOTACTIVE_5             ((uint32_t)0x00200000)
+#define SAI_SLOTACTIVE_6             ((uint32_t)0x00400000)
+#define SAI_SLOTACTIVE_7             ((uint32_t)0x00800000)
+#define SAI_SLOTACTIVE_8             ((uint32_t)0x01000000)
+#define SAI_SLOTACTIVE_9             ((uint32_t)0x02000000)
+#define SAI_SLOTACTIVE_10            ((uint32_t)0x04000000)
+#define SAI_SLOTACTIVE_11            ((uint32_t)0x08000000)
+#define SAI_SLOTACTIVE_12            ((uint32_t)0x10000000)
+#define SAI_SLOTACTIVE_13            ((uint32_t)0x20000000)
+#define SAI_SLOTACTIVE_14            ((uint32_t)0x40000000)
+#define SAI_SLOTACTIVE_15            ((uint32_t)0x80000000)
+#define SAI_SLOTACTIVE_ALL           ((uint32_t)0xFFFF0000)
+
+#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) != 0)
+
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Mono_Stereo_Mode
+  * @{
+  */
+#define SAI_MONOMODE                      ((uint32_t)SAI_xCR1_MONO)
+#define SAI_STREOMODE                     ((uint32_t)0x00000000)
+
+#define IS_SAI_BLOCK_MONO_STREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
+                                            ((MODE) == SAI_STREOMODE))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_TRIState_Management
+  * @{
+  */
+#define SAI_OUTPUT_NOTRELEASED              ((uint32_t)0x00000000)
+#define SAI_OUTPUT_RELEASED                 ((uint32_t)SAI_xCR2_TRIS)
+
+#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
+                                                 ((STATE) == SAI_OUTPUT_RELEASED))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Fifo_Threshold 
+  * @{
+  */
+#define SAI_FIFOTHRESHOLD_EMPTY  ((uint32_t)0x00000000)
+#define SAI_FIFOTHRESHOLD_1QF    ((uint32_t)0x00000001)
+#define SAI_FIFOTHRESHOLD_HF     ((uint32_t)0x00000002) 
+#define SAI_FIFOTHRESHOLD_3QF    ((uint32_t)0x00000003)
+#define SAI_FIFOTHRESHOLD_FULL   ((uint32_t)0x00000004)
+
+#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
+/**
+  * @}
+  */
+  
+/** @defgroup SAI_Block_Companding_Mode
+  * @{
+  */
+#define SAI_NOCOMPANDING                  ((uint32_t)0x00000000)
+#define SAI_ULAW_1CPL_COMPANDING          ((uint32_t)0x00008000)
+#define SAI_ALAW_1CPL_COMPANDING          ((uint32_t)0x0000C000)
+#define SAI_ULAW_2CPL_COMPANDING          ((uint32_t)0x0000A000)
+#define SAI_ALAW_2CPL_COMPANDING          ((uint32_t)0x0000E000)
+
+#define IS_SAI_BLOCK_COMPANDING_MODE(MODE)    (((MODE) == SAI_NOCOMPANDING)         || \
+                                               ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
+                                               ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
+                                               ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
+                                               ((MODE) == SAI_ALAW_2CPL_COMPANDING))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Mute_Value
+  * @{
+  */
+#define SAI_ZERO_VALUE                     ((uint32_t)0x00000000)
+#define SAI_LAST_SENT_VALUE                 ((uint32_t)SAI_xCR2_MUTEVAL)
+
+#define IS_SAI_BLOCK_MUTE_VALUE(VALUE)    (((VALUE) == SAI_ZERO_VALUE)     || \
+                                           ((VALUE) == SAI_LAST_SENT_VALUE))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Mute_Frame_Counter
+  * @{
+  */ 
+#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Interrupts_Definition 
+  * @{
+  */
+#define SAI_IT_OVRUDR                     ((uint32_t)SAI_xIMR_OVRUDRIE)
+#define SAI_IT_MUTEDET                    ((uint32_t)SAI_xIMR_MUTEDETIE)
+#define SAI_IT_WCKCFG                     ((uint32_t)SAI_xIMR_WCKCFGIE)
+#define SAI_IT_FREQ                       ((uint32_t)SAI_xIMR_FREQIE)
+#define SAI_IT_CNRDY                      ((uint32_t)SAI_xIMR_CNRDYIE)
+#define SAI_IT_AFSDET                     ((uint32_t)SAI_xIMR_AFSDETIE)
+#define SAI_IT_LFSDET                     ((uint32_t)SAI_xIMR_LFSDETIE)
+
+#define IS_SAI_BLOCK_CONFIG_IT(IT) (((IT) == SAI_IT_OVRUDR)  || \
+                                    ((IT) == SAI_IT_MUTEDET) || \
+                                    ((IT) == SAI_IT_WCKCFG)  || \
+                                    ((IT) == SAI_IT_FREQ)    || \
+                                    ((IT) == SAI_IT_CNRDY)   || \
+                                    ((IT) == SAI_IT_AFSDET)  || \
+                                    ((IT) == SAI_IT_LFSDET))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Flags_Definition 
+  * @{
+  */
+#define SAI_FLAG_OVRUDR                   ((uint32_t)SAI_xSR_OVRUDR)
+#define SAI_FLAG_MUTEDET                  ((uint32_t)SAI_xSR_MUTEDET)
+#define SAI_FLAG_WCKCFG                   ((uint32_t)SAI_xSR_WCKCFG)
+#define SAI_FLAG_FREQ                     ((uint32_t)SAI_xSR_FREQ)
+#define SAI_FLAG_CNRDY                    ((uint32_t)SAI_xSR_CNRDY)
+#define SAI_FLAG_AFSDET                   ((uint32_t)SAI_xSR_AFSDET)
+#define SAI_FLAG_LFSDET                   ((uint32_t)SAI_xSR_LFSDET)
+
+#define IS_SAI_BLOCK_GET_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR)  || \
+                                    ((FLAG) == SAI_FLAG_MUTEDET)  || \
+                                    ((FLAG) == SAI_FLAG_WCKCFG)   || \
+                                    ((FLAG) == SAI_FLAG_FREQ)     || \
+                                    ((FLAG) == SAI_FLAG_CNRDY)    || \
+                                    ((FLAG) == SAI_FLAG_AFSDET)   || \
+                                    ((FLAG) == SAI_FLAG_LFSDET))
+                                   
+#define IS_SAI_BLOCK_CLEAR_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR)  || \
+                                       ((FLAG) == SAI_FLAG_MUTEDET) || \
+                                       ((FLAG) == SAI_FLAG_WCKCFG)  || \
+                                       ((FLAG) == SAI_FLAG_FREQ)    || \
+                                       ((FLAG) == SAI_FLAG_CNRDY)   || \
+                                       ((FLAG) == SAI_FLAG_AFSDET)  || \
+                                       ((FLAG) == SAI_FLAG_LFSDET))
+/**
+  * @}
+  */
+  
+/** @defgroup SAI_Block_Fifo_Status_Level 
+  * @{
+  */
+#define SAI_FIFOStatus_Empty              ((uint32_t)0x00000000)
+#define SAI_FIFOStatus_Less1QuarterFull   ((uint32_t)0x00010000)
+#define SAI_FIFOStatus_1QuarterFull       ((uint32_t)0x00020000)
+#define SAI_FIFOStatus_HalfFull           ((uint32_t)0x00030000) 
+#define SAI_FIFOStatus_3QuartersFull      ((uint32_t)0x00040000)
+#define SAI_FIFOStatus_Full               ((uint32_t)0x00050000)
+
+#define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOStatus_Less1QuarterFull ) || \
+                                          ((STATUS) == SAI_FIFOStatus_HalfFull)          || \
+                                          ((STATUS) == SAI_FIFOStatus_1QuarterFull)      || \
+                                          ((STATUS) == SAI_FIFOStatus_3QuartersFull)     || \
+                                          ((STATUS) == SAI_FIFOStatus_Full)              || \
+                                          ((STATUS) == SAI_FIFOStatus_Empty)) 
+/**
+  * @}
+  */
+
+  
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @brief Reset SAI handle state
+  * @param  __HANDLE__: specifies the SAI Handle.
+  * @retval None
+  */
+#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
+
+/** @brief  Enable or disable the specified SAI interrupts.
+  * @param  __HANDLE__: specifies the SAI Handle.
+  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  *         This parameter can be one of the following values:
+  *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable                              
+  *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable                               
+  *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable                    
+  *            @arg SAI_IT_FREQ: FIFO request interrupt enable                                  
+  *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable                               
+  *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable   
+  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enabl
+  * @retval None
+  */
+  
+#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
+#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
+ 
+/** @brief  Check if the specified SAI interrupt source is enabled or disabled.
+  * @param  __HANDLE__: specifies the SAI Handle.
+  *         This parameter can be SAI where x: 1, 2, or 3 to select the SAI peripheral.
+  * @param  __INTERRUPT__: specifies the SAI interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg SAI_IT_TXE: Tx buffer empty interrupt enable.
+  *            @arg SAI_IT_RXNE: Rx buffer not empty interrupt enable.
+  *            @arg SAI_IT_ERR: Error interrupt enable.
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified SAI flag is set or not.
+  * @param  __HANDLE__: specifies the SAI Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
+  *            @arg SAI_FLAG_MUTEDET: Mute detection flag.
+  *            @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
+  *            @arg SAI_FLAG_FREQ: FIFO request flag.
+  *            @arg SAI_FLAG_CNRDY: Codec not ready flag.
+  *            @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
+  *            @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.  
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clears the specified SAI pending flag.
+  * @param  __HANDLE__: specifies the SAI Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg SAI_FLAG_OVRUDR: Clear Overrun underrun  
+  *            @arg SAI_FLAG_MUTEDET: Clear Mute detection 
+  *            @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration  
+  *            @arg SAI_FLAG_FREQ: Clear FIFO request   
+  *            @arg SAI_FLAG_CNRDY: Clear Codec not ready
+  *            @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
+  *            @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
+  *   
+  * @retval None
+  */
+#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR |= (__FLAG__))                                        
+
+#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SAI_xCR1_SAIEN)
+#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SAI_xCR1_SAIEN)
+                                                                               
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
+void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
+void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
+
+/* I/O operation functions  *****************************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
+
+/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
+void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
+
+/* Peripheral State functions  **************************************************/
+HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
+uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SAI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,3368 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_sd.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   SD card HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Secure Digital (SD) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    This driver implements a high level communication layer for read and write from/to 
+    this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by 
+    the user in HAL_SD_MspInit() function (MSP layer).                             
+    Basically, the MSP layer configuration should be the same as we provide in the 
+    examples.
+    You can easily tailor this configuration according to hardware resources.
+
+  [..]
+    This driver is a generic layered driver for SDIO memories which uses the HAL 
+    SDIO driver functions to interface with SD and uSD cards devices. 
+    It is used as follows:
+ 
+    (#)Initialize the SDIO low level resources by implement the HAL_SD_MspInit() API:
+        (##) Enable the SDIO interface clock using __SDIO_CLK_ENABLE(); 
+        (##) SDIO pins configuration for SD card
+            (+++) Enable the clock for the SDIO GPIOs using the functions __GPIOx_CLK_ENABLE();   
+            (+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()
+                  and according to your pin assignment;
+        (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
+             and HAL_SD_WriteBlocks_DMA() APIs).
+            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE(); 
+            (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. 
+        (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
+            (+++) Configure the SDIO and DMA interrupt priorities using functions
+                  HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority
+            (+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ()
+            (+++) SDIO interrupts are managed using the macros __HAL_SD_SDIO_ENABLE_IT() 
+                  and __HAL_SD_SDIO_DISABLE_IT() inside the communication process.
+            (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_SDIO_GET_IT()
+                  and __HAL_SD_SDIO_CLEAR_IT()
+    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization  
+
+         
+  *** SD Card Initialization and configuration ***
+  ================================================    
+  [..]
+    To initialize the SD Card, use the HAL_SD_Init() function.  It Initializes 
+    the SD Card and put it into StandBy State (Ready for data transfer). 
+    This function provide the following operations:
+  
+    (#) Apply the SD Card initialization process at 400KHz and check the SD Card 
+        type (Standard Capacity or High Capacity). You can change or adapt this 
+        frequency by adjusting the "ClockDiv" field. 
+        The SD Card frequency (SDIO_CK) is computed as follows:
+  
+           SDIO_CK = SDIOCLK / (ClockDiv + 2)
+  
+        In initialization mode and according to the SD Card standard, 
+        make sure that the SDIO_CK frequency doesn't exceed 400KHz.
+  
+    (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo 
+        structure. This structure provide also ready computed SD Card capacity 
+        and Block size.
+        
+        -@- These information are stored in SD handle structure in case of future use.  
+  
+    (#) Configure the SD Card Data transfer frequency. By Default, the card transfer 
+        frequency is set to 24MHz. You can change or adapt this frequency by adjusting 
+        the "ClockDiv" field.
+        The SD Card frequency (SDIO_CK) is computed as follows:
+
+           SDIO_CK = SDIOCLK / (ClockDiv + 2) 
+
+        In transfer mode and according to the SD Card standard, make sure that the 
+        SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
+        To be able to use a frequency higher than 24MHz, you should use the SDIO 
+        peripheral in bypass mode. Refer to the corresponding reference manual 
+        for more details.
+  
+    (#) Select the corresponding SD Card according to the address read with the step 2.
+    
+    (#) Configure the SD Card in wide bus mode: 4-bits data.
+  
+  *** SD Card Read operation ***
+  ==============================
+  [..] 
+    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). 
+        This function support only 512-byte block length (the block size should be 
+        chosen as 512 byte).
+        You can choose either one block read operation or multiple block read operation 
+        by adjusting the "NumberOfBlocks" parameter.
+
+    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
+        This function support only 512-byte block length (the block size should be 
+        chosen as 512 byte).
+        You can choose either one block read operation or multiple block read operation 
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to call the function HAL_SD_CheckReadOperation(), to insure
+        that the read transfer is done correctly in both DMA and SD sides.
+  
+  *** SD Card Write operation ***
+  =============================== 
+  [..] 
+    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). 
+        This function support only 512-byte block length (the block size should be 
+        chosen as 512 byte).
+        You can choose either one block read operation or multiple block read operation 
+        by adjusting the "NumberOfBlocks" parameter.
+
+    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
+        This function support only 512-byte block length (the block size should be 
+        chosen as 512 byte).
+        You can choose either one block read operation or multiple block read operation 
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure
+        that the write transfer is done correctly in both DMA and SD sides.  
+  
+  *** SD card status ***
+  ====================== 
+  [..]
+    (+) At any time, you can check the SD Card status and get the SD card state 
+        by using the HAL_SD_GetStatus() function. This function checks first if the 
+        SD card is still connected and then get the internal SD Card transfer state.     
+    (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus() 
+        function.    
+
+  *** SD HAL driver macros list ***
+  ==================================
+  [..]
+    Below the list of most used macros in SD HAL driver.
+       
+    (+) __HAL_SD_SDIO_ENABLE : Enable the SD device
+    (+) __HAL_SD_SDIO_DISABLE : Disable the SD device
+    (+) __HAL_SD_SDIO_DMA_ENABLE: Enable the SDIO DMA transfer
+    (+) __HAL_SD_SDIO_DMA_DISABLE: Disable the SDIO DMA transfer
+    (+) __HAL_SD_SDIO_ENABLE_IT: Enable the SD device interrupt
+    (+) __HAL_SD_SDIO_DISABLE_IT: Disable the SD device interrupt
+    (+) __HAL_SD_SDIO_GET_FLAG:Check whether the specified SD flag is set or not
+    (+) __HAL_SD_SDIO_CLEAR_FLAG: Clear the SD's pending flags
+      
+    (@) You can refer to the SD HAL driver header file for more useful macros 
+      
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SD
+  * @brief SD HAL module driver
+  * @{
+  */
+
+#ifdef HAL_SD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** 
+  * @brief  SDIO Static flags, TimeOut, FIFO Address  
+  */
+#define SDIO_STATIC_FLAGS               ((uint32_t)0x000005FF)
+#define SDIO_CMD0TIMEOUT                ((uint32_t)0x00010000)
+
+/** 
+  * @brief  Mask for errors Card Status R1 (OCR Register) 
+  */
+#define SD_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000)
+#define SD_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000)
+#define SD_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000)
+#define SD_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000)
+#define SD_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000)
+#define SD_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000)
+#define SD_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000)
+#define SD_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000)
+#define SD_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000)
+#define SD_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000)
+#define SD_OCR_CC_ERROR                 ((uint32_t)0x00100000)
+#define SD_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000)
+#define SD_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000)
+#define SD_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000)
+#define SD_OCR_CID_CSD_OVERWRIETE       ((uint32_t)0x00010000)
+#define SD_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000)
+#define SD_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000)
+#define SD_OCR_ERASE_RESET              ((uint32_t)0x00002000)
+#define SD_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008)
+#define SD_OCR_ERRORBITS                ((uint32_t)0xFDFFE008)
+
+/** 
+  * @brief  Masks for R6 Response 
+  */
+#define SD_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000)
+#define SD_R6_ILLEGAL_CMD               ((uint32_t)0x00004000)
+#define SD_R6_COM_CRC_FAILED            ((uint32_t)0x00008000)
+
+#define SD_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000)
+#define SD_HIGH_CAPACITY                ((uint32_t)0x40000000)
+#define SD_STD_CAPACITY                 ((uint32_t)0x00000000)
+#define SD_CHECK_PATTERN                ((uint32_t)0x000001AA)
+
+#define SD_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFF)
+#define SD_ALLZERO                      ((uint32_t)0x00000000)
+
+#define SD_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000)
+#define SD_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000)
+#define SD_CARD_LOCKED                  ((uint32_t)0x02000000)
+
+#define SD_DATATIMEOUT                  ((uint32_t)0xFFFFFFFF)
+#define SD_0TO7BITS                     ((uint32_t)0x000000FF)
+#define SD_8TO15BITS                    ((uint32_t)0x0000FF00)
+#define SD_16TO23BITS                   ((uint32_t)0x00FF0000)
+#define SD_24TO31BITS                   ((uint32_t)0xFF000000)
+#define SD_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFF)
+
+#define SD_HALFFIFO                     ((uint32_t)0x00000008)
+#define SD_HALFFIFOBYTES                ((uint32_t)0x00000020)
+
+/** 
+  * @brief  Command Class Supported 
+  */
+#define SD_CCCC_LOCK_UNLOCK             ((uint32_t)0x00000080)
+#define SD_CCCC_WRITE_PROT              ((uint32_t)0x00000040)
+#define SD_CCCC_ERASE                   ((uint32_t)0x00000020)
+
+/** 
+  * @brief  Following commands are SD Card Specific commands.
+  *         SDIO_APP_CMD should be sent before sending these commands. 
+  */
+#define SD_SDIO_SEND_IF_COND            ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)
+
+  
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr);
+static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd); 
+static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
+static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus);
+static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD);
+static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA);
+static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd);
+static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);  
+static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma);
+static void SD_DMA_RxError(DMA_HandleTypeDef *hdma);
+static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma);
+static void SD_DMA_TxError(DMA_HandleTypeDef *hdma);
+
+/** @defgroup SD_Private_Functions
+  * @{
+  */
+
+/** @defgroup SD_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+  ==============================================================================
+          ##### Initialization and de-initialization functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to initialize/de-initialize the SD
+    card device to be ready for use.
+      
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SD card according to the specified parameters in the 
+            SD_HandleTypeDef and create the associated handle.
+  * @param  hsd: SD handle
+  * @param  SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information   
+  * @retval HAL SD error state
+  */
+HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)
+{ 
+  __IO HAL_SD_ErrorTypedef errorState = SD_OK;
+  SD_InitTypeDef tmpInit;
+  
+  /* Initialize the low level hardware (MSP) */
+  HAL_SD_MspInit(hsd);
+  
+  /* Default SDIO peripheral configuration for SD card initialization */
+  tmpInit.ClockEdge           = SDIO_CLOCK_EDGE_RISING;
+  tmpInit.ClockBypass         = SDIO_CLOCK_BYPASS_DISABLE;
+  tmpInit.ClockPowerSave      = SDIO_CLOCK_POWER_SAVE_DISABLE;
+  tmpInit.BusWide             = SDIO_BUS_WIDE_1B;
+  tmpInit.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
+  tmpInit.ClockDiv            = SDIO_INIT_CLK_DIV;
+  
+  /* Initialize SDIO peripheral interface with default configuration */
+  SDIO_Init(hsd->Instance, tmpInit);
+  
+  /* Identify card operating voltage */
+  errorState = SD_PowerON(hsd); 
+  
+  if(errorState != SD_OK)     
+  {
+    return errorState;
+  }
+  
+  /* Initialize the present SDIO card(s) and put them in idle state */
+  errorState = SD_Initialize_Cards(hsd);
+  
+  if (errorState != SD_OK)
+  {
+    return errorState;
+  }
+  
+  /* Read CSD/CID MSD registers */
+  errorState = HAL_SD_Get_CardInfo(hsd, SDCardInfo);
+  
+  if (errorState == SD_OK)
+  {
+    /* Select the Card */
+    errorState = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16));
+  }
+  
+  /* Configure SDIO peripheral interface */
+  SDIO_Init(hsd->Instance, hsd->Init);   
+  
+  return errorState;
+}
+
+/**
+  * @brief  De-Initializes the SD card.
+  * @param  hsd: SD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
+{
+  
+  /* Set SD power state to off */ 
+  SD_PowerOFF(hsd);
+  
+  /* De-Initialize the MSP layer */
+  HAL_SD_MspDeInit(hsd);
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initializes the SD MSP.
+  * @param  hsd: SD handle
+  * @retval None
+  */
+__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SD_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  De-Initialize SD MSP.
+  * @param  hsd: SD handle
+  * @retval None
+  */
+__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SD_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SD_Group2 IO operation functions 
+ *  @brief   Data transfer functions 
+ *
+@verbatim   
+  ==============================================================================
+                        ##### IO operation functions #####
+  ==============================================================================  
+  [..]
+    This subsection provides a set of functions allowing to manage the data 
+    transfer from/to SD card.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer 
+  *         is managed by polling mode.  
+  * @param  hsd: SD handle
+  * @param  pReadBuffer: pointer to the buffer that will contain the received data
+  * @param  ReadAddr: Address from where data is to be read  
+  * @param  BlockSize: SD card Data block size 
+  *          This parameter should be 512
+  * @param  NumberOfBlocks: Number of SD blocks to read   
+  * @retval SD Card error state
+  */
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
+{
+  SDIO_CmdInitTypeDef  SDIO_CmdInitStructure;
+  SDIO_DataInitTypeDef SDIO_DataInitStructure;
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer;
+  
+  /* Initialize data control register */
+  hsd->Instance->DCTRL = 0;
+  
+  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
+  {
+    BlockSize = 512;
+    ReadAddr /= 512;
+  }
+  
+  /* Set Block Size for Card */ 
+  SDIO_CmdInitStructure.Argument         = (uint32_t) BlockSize;
+  SDIO_CmdInitStructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
+  SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_SHORT;
+  SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
+  SDIO_CmdInitStructure.CPSM             = SDIO_CPSM_ENABLE;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Check for error conditions */
+  errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+  
+  if (errorState != SD_OK)
+  {
+    return errorState;
+  }
+  
+  /* Configure the SD DPSM (Data Path State Machine) */
+  SDIO_DataInitStructure.DataTimeOut   = SD_DATATIMEOUT;
+  SDIO_DataInitStructure.DataLength    = NumberOfBlocks * BlockSize;
+  SDIO_DataInitStructure.DataBlockSize = (uint32_t)(9 << 4);
+  SDIO_DataInitStructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
+  SDIO_DataInitStructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+  SDIO_DataInitStructure.DPSM          = SDIO_DPSM_ENABLE;
+  SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure);
+  
+  if(NumberOfBlocks > 1)
+  {
+    /* Send CMD18 READ_MULT_BLOCK with argument data address */
+    SDIO_CmdInitStructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
+  }
+  else
+  {
+    /* Send CMD17 READ_SINGLE_BLOCK */
+    SDIO_CmdInitStructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;    
+  }
+  
+  SDIO_CmdInitStructure.Argument         = (uint32_t)ReadAddr;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Read block(s) in polling mode */
+  if(NumberOfBlocks > 1)
+  {
+    /* Check for error conditions */
+    errorState = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
+    
+    if (errorState != SD_OK)
+    {
+      return errorState;
+    }
+    
+    /* Poll on SDIO flags */
+    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+    {
+      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+      {
+        /* Read data from SDIO Rx FIFO */
+        for (count = 0; count < 8; count++)
+        {
+          *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
+        }
+        
+        tempbuff += 8;
+      }
+    }      
+  }
+  else
+  {
+    /* Check for error conditions */
+    errorState = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); 
+    
+    if (errorState != SD_OK)
+    {
+      return errorState;
+    }    
+    
+    /* In case of single block transfer, no need of stop transfer at all */
+    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+    {
+      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+      {
+        /* Read data from SDIO Rx FIFO */
+        for (count = 0; count < 8; count++)
+        {
+          *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
+        }
+        
+        tempbuff += 8;
+      }
+    }   
+  }
+  
+  /* Send stop transmission command in case of multiblock read */
+  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1))
+  {    
+    if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\
+      (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
+        (hsd->CardType == HIGH_CAPACITY_SD_CARD))
+    {
+      /* Send stop transmission command */
+      errorState = HAL_SD_StopTransfer(hsd);
+    }
+  }
+  
+  /* Get error state */
+  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
+    
+    errorState = SD_DATA_TIMEOUT;
+    
+    return errorState;
+  }
+  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+    
+    errorState = SD_DATA_CRC_FAIL;
+    
+    return errorState;
+  }
+  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
+    
+    errorState = SD_RX_OVERRUN;
+    
+    return errorState;
+  }
+  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
+    
+    errorState = SD_START_BIT_ERR;
+    
+    return errorState;
+  }
+  
+  count = SD_DATATIMEOUT;
+  
+  /* Empty FIFO if there is still any data */
+  while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0))
+  {
+    *tempbuff = SDIO_ReadFIFO(hsd->Instance);
+    tempbuff++;
+    count--;
+  }
+  
+  /* Clear all the static flags */
+  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+  
+  return errorState;
+}
+
+/**
+  * @brief  Allows to write block(s) to a specified address in a card. The Data
+  *         transfer is managed by polling mode.  
+  * @param  hsd: SD handle
+  * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit
+  * @param  WriteAddr: Address from where data is to be written 
+  * @param  BlockSize: SD card Data block size 
+  *          This parameter should be 512.
+  * @param  NumberOfBlocks: Number of SD blocks to write 
+  * @retval SD Card error state
+  */
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
+{
+  SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
+  SDIO_DataInitTypeDef SDIO_DataInitStructure;
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  uint32_t TotalNumberOfBytes = 0, bytestransferred = 0, count = 0, restwords = 0;
+  uint32_t *tempbuff = (uint32_t *)pWriteBuffer;
+  uint8_t cardstate  = 0;
+  
+  /* Initialize data control register */
+  hsd->Instance->DCTRL = 0;
+  
+  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
+  {
+    BlockSize = 512;
+    WriteAddr /= 512;
+  }
+  
+  /* Set Block Size for Card */ 
+  SDIO_CmdInitStructure.Argument         = (uint32_t)BlockSize;
+  SDIO_CmdInitStructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
+  SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_SHORT;
+  SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
+  SDIO_CmdInitStructure.CPSM             = SDIO_CPSM_ENABLE;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Check for error conditions */
+  errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+  
+  if (errorState != SD_OK)
+  {
+    return errorState;
+  }
+  
+  if(NumberOfBlocks > 1)
+  {
+    /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
+    SDIO_CmdInitStructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
+  }
+  else
+  {
+    /* Send CMD24 WRITE_SINGLE_BLOCK */
+    SDIO_CmdInitStructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
+  }
+  
+  SDIO_CmdInitStructure.Argument         = (uint32_t)WriteAddr;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Check for error conditions */
+  if(NumberOfBlocks > 1)
+  {
+    errorState = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
+  }
+  else
+  {
+    errorState = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
+  }  
+  
+  if (errorState != SD_OK)
+  {
+    return errorState;
+  }
+  
+  /* Set total number of bytes to write */
+  TotalNumberOfBytes = NumberOfBlocks * BlockSize;
+  
+  /* Configure the SD DPSM (Data Path State Machine) */ 
+  SDIO_DataInitStructure.DataTimeOut   = SD_DATATIMEOUT;
+  SDIO_DataInitStructure.DataLength    = NumberOfBlocks * BlockSize;
+  SDIO_DataInitStructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+  SDIO_DataInitStructure.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
+  SDIO_DataInitStructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+  SDIO_DataInitStructure.DPSM          = SDIO_DPSM_ENABLE;
+  SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure);
+  
+  /* Write block(s) in polling mode */
+  if(NumberOfBlocks > 1)
+  {
+    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+    {
+      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
+      {
+        if ((TotalNumberOfBytes - bytestransferred) < 32)
+        {
+          restwords = ((TotalNumberOfBytes - bytestransferred) % 4 == 0) ? ((TotalNumberOfBytes - bytestransferred) / 4) : (( TotalNumberOfBytes -  bytestransferred) / 4 + 1);
+          
+          /* Write data to SDIO Tx FIFO */
+          for (count = 0; count < restwords; count++)
+          {
+            SDIO_WriteFIFO(hsd->Instance, tempbuff);
+            tempbuff++;
+            bytestransferred += 4;
+          }
+        }
+        else
+        {
+          /* Write data to SDIO Tx FIFO */
+          for (count = 0; count < 8; count++)
+          {
+            SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
+          }
+          
+          tempbuff += 8;
+          bytestransferred += 32;
+        }
+      }
+    }   
+  }
+  else
+  {
+    /* In case of single data block transfer no need of stop command at all */ 
+    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+    {
+      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
+      {
+        if ((TotalNumberOfBytes - bytestransferred) < 32)
+        {
+          restwords = ((TotalNumberOfBytes - bytestransferred) % 4 == 0) ? ((TotalNumberOfBytes - bytestransferred) / 4) : (( TotalNumberOfBytes -  bytestransferred) / 4 + 1);
+          
+          /* Write data to SDIO Tx FIFO */
+          for (count = 0; count < restwords; count++)
+          {
+            SDIO_WriteFIFO(hsd->Instance, tempbuff);
+            tempbuff++; 
+            bytestransferred += 4;
+          }
+        }
+        else
+        {
+          /* Write data to SDIO Tx FIFO */
+          for (count = 0; count < 8; count++)
+          {
+            SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
+          }
+          
+          tempbuff += 8;
+          bytestransferred += 32;
+        }
+      }
+    }  
+  }
+  
+  /* Send stop transmission command in case of multiblock write */
+  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1))
+  {    
+    if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
+      (hsd->CardType == HIGH_CAPACITY_SD_CARD))
+    {
+      /* Send stop transmission command */
+      errorState = HAL_SD_StopTransfer(hsd);
+    }
+  }
+  
+  /* Get error state */
+  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
+    
+    errorState = SD_DATA_TIMEOUT;
+    
+    return errorState;
+  }
+  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+    
+    errorState = SD_DATA_CRC_FAIL;
+    
+    return errorState;
+  }
+  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR);
+    
+    errorState = SD_TX_UNDERRUN;
+    
+    return errorState;
+  }
+  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
+    
+    errorState = SD_START_BIT_ERR;
+    
+    return errorState;
+  }
+  
+  /* Clear all the static flags */
+  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+  
+  /* Wait till the card is in programming state */
+  errorState = SD_IsCardProgramming(hsd, &cardstate);
+  
+  while ((errorState == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
+  {
+    errorState = SD_IsCardProgramming(hsd, &cardstate);
+  }
+  
+  return errorState;
+}
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer 
+  *         is managed by DMA mode. 
+  * @note   This API should be followed by the function HAL_SD_CheckReadOperation()
+  *         to check the completion of the read process   
+  * @param  hsd: SD handle                 
+  * @param  pReadBuffer: Pointer to the buffer that will contain the received data
+  * @param  ReadAddr: Address from where data is to be read  
+  * @param  BlockSize: SD card Data block size 
+  *         This paramater should be 512.
+  * @param  NumberOfBlocks: Number of blocks to read.
+  * @retval SD Card error state
+  */
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
+{
+  SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
+  SDIO_DataInitTypeDef SDIO_DataInitStructure;
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  
+  /* Initialize data control register */
+  hsd->Instance->DCTRL = 0;
+  
+  /* Initialize handle flags */
+  hsd->SdTransferCplt  = 0;
+  hsd->DmaTransferCplt = 0;
+  hsd->SdTransferErr   = SD_OK; 
+  
+  /* Initialize SD Read operation */
+  if(NumberOfBlocks > 1)
+  {
+    hsd->SdOperation = SD_READ_MULTIPLE_BLOCK;
+  }
+  else
+  {
+    hsd->SdOperation = SD_READ_SINGLE_BLOCK;
+  }
+  
+  /* Enable transfer interrupts */
+  __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
+                                SDIO_IT_DTIMEOUT |\
+                                SDIO_IT_DATAEND  |\
+                                SDIO_IT_RXOVERR  |\
+                                SDIO_IT_STBITERR));
+  
+  /* Enable SDIO DMA transfer */
+  __HAL_SD_SDIO_DMA_ENABLE();
+  
+  /* Configure DMA user callbacks */
+  hsd->hdmarx->XferCpltCallback  = SD_DMA_RxCplt;
+  hsd->hdmarx->XferErrorCallback = SD_DMA_RxError;
+  
+  /* Enable the DMA Stream */
+  HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)SDIO_FIFO_ADDRESS, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks));
+  
+  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
+  {
+    BlockSize = 512;
+    ReadAddr /= 512;
+  }
+  
+  /* Set Block Size for Card */ 
+  SDIO_CmdInitStructure.Argument         = (uint32_t)BlockSize;
+  SDIO_CmdInitStructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
+  SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_SHORT;
+  SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
+  SDIO_CmdInitStructure.CPSM             = SDIO_CPSM_ENABLE;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Check for error conditions */
+  errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+  
+  if (errorState != SD_OK)
+  {
+    return errorState;
+  }
+  
+  /* Configure the SD DPSM (Data Path State Machine) */ 
+  SDIO_DataInitStructure.DataTimeOut   = SD_DATATIMEOUT;
+  SDIO_DataInitStructure.DataLength    = BlockSize * NumberOfBlocks;
+  SDIO_DataInitStructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+  SDIO_DataInitStructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
+  SDIO_DataInitStructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+  SDIO_DataInitStructure.DPSM          = SDIO_DPSM_ENABLE;
+  SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure);
+  
+  /* Check number of blocks command */
+  if(NumberOfBlocks > 1)
+  {
+    /* Send CMD18 READ_MULT_BLOCK with argument data address */
+    SDIO_CmdInitStructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
+  }
+  else
+  {
+    /* Send CMD17 READ_SINGLE_BLOCK */
+    SDIO_CmdInitStructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
+  }
+  
+  SDIO_CmdInitStructure.Argument         = (uint32_t)ReadAddr;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Check for error conditions */
+  if(NumberOfBlocks > 1)
+  {
+    errorState = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
+  }
+  else
+  {
+    errorState = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
+  }
+  
+  /* Update the SD transfer error in SD handle */
+  hsd->SdTransferErr = errorState;
+  
+  return errorState;
+}
+
+
+/**
+  * @brief  Writes block(s) to a specified address in a card. The Data transfer 
+  *         is managed by DMA mode. 
+  * @note   This API should be followed by the function HAL_SD_CheckWriteOperation()
+  *         to check the completion of the write process (by SD current status polling).  
+  * @param  hsd: SD handle
+  * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit
+  * @param  WriteAddr: Address from where data is to be read   
+  * @param  BlockSize: the SD card Data block size 
+  *          This parameter should be 512.
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @retval SD Card error state
+  */
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
+{
+  SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
+  SDIO_DataInitTypeDef SDIO_DataInitStructure;
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  
+  /* Initialize data control register */
+  hsd->Instance->DCTRL = 0;
+  
+  /* Initialize handle flags */
+  hsd->SdTransferCplt  = 0;
+  hsd->DmaTransferCplt = 0;
+  hsd->SdTransferErr   = SD_OK;
+  
+  /* Initialize SD Write operation */
+  if(NumberOfBlocks > 1)
+  {
+    hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK;
+  }
+  else
+  {
+    hsd->SdOperation = SD_WRITE_SINGLE_BLOCK;
+  }  
+  
+  /* Enable transfer interrupts */
+  __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
+                                SDIO_IT_DTIMEOUT |\
+                                SDIO_IT_DATAEND  |\
+                                SDIO_IT_TXUNDERR |\
+                                SDIO_IT_STBITERR)); 
+  
+  /* Configure DMA user callbacks */
+  hsd->hdmatx->XferCpltCallback  = SD_DMA_TxCplt;
+  hsd->hdmatx->XferErrorCallback = SD_DMA_TxError;
+  
+  /* Enable the DMA Stream */
+  HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)SDIO_FIFO_ADDRESS, (uint32_t)(BlockSize * NumberOfBlocks));
+
+  /* Enable SDIO DMA transfer */
+  __HAL_SD_SDIO_DMA_ENABLE();
+  
+  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
+  {
+    BlockSize = 512;
+    WriteAddr /= 512;
+  }
+
+  /* Set Block Size for Card */ 
+  SDIO_CmdInitStructure.Argument         = (uint32_t)BlockSize;
+  SDIO_CmdInitStructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
+  SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_SHORT;
+  SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
+  SDIO_CmdInitStructure.CPSM             = SDIO_CPSM_ENABLE;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+
+  /* Check for error conditions */
+  errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+
+  if (errorState != SD_OK)
+  {
+    return errorState;
+  }
+  
+  /* Check number of blocks command */
+  if(NumberOfBlocks <= 1)
+  {
+    /* Send CMD24 WRITE_SINGLE_BLOCK */
+    SDIO_CmdInitStructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
+  }
+  else
+  {
+    /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
+    SDIO_CmdInitStructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
+  }
+  
+  SDIO_CmdInitStructure.Argument         = (uint32_t)WriteAddr;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+
+  /* Check for error conditions */
+  if(NumberOfBlocks > 1)
+  {
+    errorState = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
+  }
+  else
+  {
+    errorState = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
+  }
+  
+  if (errorState != SD_OK)
+  {
+    return errorState;
+  }
+  
+  /* Configure the SD DPSM (Data Path State Machine) */ 
+  SDIO_DataInitStructure.DataTimeOut   = SD_DATATIMEOUT;
+  SDIO_DataInitStructure.DataLength    = BlockSize * NumberOfBlocks;
+  SDIO_DataInitStructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+  SDIO_DataInitStructure.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
+  SDIO_DataInitStructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+  SDIO_DataInitStructure.DPSM          = SDIO_DPSM_ENABLE;
+  SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure);
+  
+  hsd->SdTransferErr = errorState;
+  
+  return errorState;
+}
+
+/**
+  * @brief  This function waits until the SD DMA data read transfer is finished. 
+  *         This API should be called after HAL_SD_ReadBlocks_DMA() function
+  *         to insure that all data sent by the card is already transferred by the 
+  *         DMA controller.
+  * @param  hsd: SD handle
+  * @param  Timeout: Timeout duration  
+  * @retval SD Card error state
+  */
+HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
+{
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  uint32_t timeout = Timeout;
+  uint32_t tmp1, tmp2;
+  HAL_SD_ErrorTypedef tmp3;
+  
+  /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
+  tmp1 = hsd->DmaTransferCplt; 
+  tmp2 = hsd->SdTransferCplt;
+  tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
+    
+  while ((tmp1 == 0) && (tmp2 == 0) && (tmp3 == SD_OK) && (timeout > 0))
+  {
+    tmp1 = hsd->DmaTransferCplt; 
+    tmp2 = hsd->SdTransferCplt;
+    tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;    
+    timeout--;
+  }
+  
+  timeout = Timeout;
+  
+  /* Wait until the Rx transfer is no longer active */
+  while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXACT)) && (timeout > 0))
+  {
+    timeout--;  
+  }
+  
+  /* Send stop command in multiblock read */
+  if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK)
+  {
+    errorState = HAL_SD_StopTransfer(hsd);
+  }
+  
+  if ((timeout == 0) && (errorState == SD_OK))
+  {
+    errorState = SD_DATA_TIMEOUT;
+  }
+  
+  /* Clear all the static flags */
+  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+  
+  /* Return error state */
+  if (hsd->SdTransferErr != SD_OK)
+  {
+    return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
+  }
+  
+  return errorState;
+}
+
+/**
+  * @brief  This function waits until the SD DMA data write transfer is finished. 
+  *         This API should be called after HAL_SD_WriteBlocks_DMA() function
+  *         to insure that all data sent by the card is already transferred by the 
+  *         DMA controller.
+  * @param  hsd: SD handle
+  * @param  Timeout: Timeout duration  
+  * @retval SD Card error state
+  */
+HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
+{
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  uint32_t timeout = Timeout;
+  uint32_t tmp1, tmp2;
+  HAL_SD_ErrorTypedef tmp3;
+
+  /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
+  tmp1 = hsd->DmaTransferCplt; 
+  tmp2 = hsd->SdTransferCplt;
+  tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
+    
+  while ((tmp1 == 0) && (tmp2 == 0) && (tmp3 == SD_OK) && (timeout > 0))
+  {
+    tmp1 = hsd->DmaTransferCplt; 
+    tmp2 = hsd->SdTransferCplt;
+    tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
+    timeout--;
+  }
+  
+  timeout = Timeout;
+  
+  /* Wait until the Tx transfer is no longer active */
+  while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXACT))  && (timeout > 0))
+  {
+    timeout--;  
+  }
+
+  /* Send stop command in multiblock write */
+  if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK)
+  {
+    errorState = HAL_SD_StopTransfer(hsd);
+  }
+  
+  if ((timeout == 0) && (errorState == SD_OK))
+  {
+    errorState = SD_DATA_TIMEOUT;
+  }
+  
+  /* Clear all the static flags */
+  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+  
+  /* Return error state */
+  if (hsd->SdTransferErr != SD_OK)
+  {
+    return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
+  }
+  
+  /* Wait until write is complete */
+  while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK)
+  {    
+  }
+
+  return errorState; 
+}
+
+/**
+  * @brief  Erases the specified memory area of the given SD card.
+  * @param  hsd: SD handle 
+  * @param  startaddr: Start byte address
+  * @param  endaddr: End byte address
+  * @retval SD Card error state
+  */
+HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr)
+{
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
+  
+  uint32_t delay         = 0;
+  __IO uint32_t maxdelay = 0;
+  uint8_t cardstate      = 0;
+  
+  /* Check if the card command class supports erase command */
+  if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0)
+  {
+    errorState = SD_REQUEST_NOT_APPLICABLE;
+    
+    return errorState;
+  }
+  
+  /* Get max delay value */
+  maxdelay = 120000 / (((hsd->Instance->CLKCR) & 0xFF) + 2);
+  
+  if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
+  {
+    errorState = SD_LOCK_UNLOCK_FAILED;
+    
+    return errorState;
+  }
+  
+  /* Get start and end block for high capacity cards */
+  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
+  {
+    startaddr /= 512;
+    endaddr   /= 512;
+  }
+  
+  /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
+  if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
+    (hsd->CardType == HIGH_CAPACITY_SD_CARD))
+  {
+    /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
+    SDIO_CmdInitStructure.Argument         =(uint32_t)startaddr;
+    SDIO_CmdInitStructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_START;
+    SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_SHORT;
+    SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
+    SDIO_CmdInitStructure.CPSM             = SDIO_CPSM_ENABLE;
+    SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+    
+    /* Check for error conditions */
+    errorState = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START);
+    
+    if (errorState != SD_OK)
+    {
+      return errorState;
+    }
+    
+    /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
+    SDIO_CmdInitStructure.Argument         = (uint32_t)endaddr;
+    SDIO_CmdInitStructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_END;
+    SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+    
+    /* Check for error conditions */
+    errorState = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END);
+    
+    if (errorState != SD_OK)
+    {
+      return errorState;
+    }
+  }
+  
+  /* Send CMD38 ERASE */
+  SDIO_CmdInitStructure.Argument         = 0;
+  SDIO_CmdInitStructure.CmdIndex         = SD_CMD_ERASE;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Check for error conditions */
+  errorState = SD_CmdResp1Error(hsd, SD_CMD_ERASE);
+  
+  if (errorState != SD_OK)
+  {
+    return errorState;
+  }
+  
+  for (; delay < maxdelay; delay++)
+  {
+  }
+  
+  /* Wait untill the card is in programming state */
+  errorState = SD_IsCardProgramming(hsd, &cardstate);
+  
+  delay = SD_DATATIMEOUT;
+  
+  while ((delay > 0) && (errorState == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
+  {
+    errorState = SD_IsCardProgramming(hsd, &cardstate);
+    delay--;
+  }
+  
+  return errorState;
+}
+
+/**
+  * @brief  This function handles SD card interrupt request.
+  * @param  hsd: SD handle
+  * @retval None
+  */
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
+{  
+  /* Check for SDIO interrupt flags */
+  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DATAEND))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_IT_DATAEND);  
+      
+    /* SD transfer is complete */
+    hsd->SdTransferCplt = 1;
+
+    /* No transfer error */ 
+    hsd->SdTransferErr  = SD_OK;
+
+    HAL_SD_XferCpltCallback(hsd);  
+  }  
+  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DCRCFAIL))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+    
+    hsd->SdTransferErr = SD_DATA_CRC_FAIL;
+    
+    HAL_SD_XferErrorCallback(hsd);
+    
+  }
+  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DTIMEOUT))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
+    
+    hsd->SdTransferErr = SD_DATA_TIMEOUT;
+    
+    HAL_SD_XferErrorCallback(hsd);
+  }
+  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_RXOVERR))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
+    
+    hsd->SdTransferErr = SD_RX_OVERRUN;
+    
+    HAL_SD_XferErrorCallback(hsd);
+  }
+  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_TXUNDERR))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR);
+    
+    hsd->SdTransferErr = SD_TX_UNDERRUN;
+    
+    HAL_SD_XferErrorCallback(hsd);
+  }
+  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_STBITERR))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
+    
+    hsd->SdTransferErr = SD_START_BIT_ERR;
+    
+    HAL_SD_XferErrorCallback(hsd);
+  }
+
+  /* Disable all SDIO peripheral interrupt sources */
+  __HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND  |\
+                                SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |\
+                                SDIO_IT_RXOVERR  | SDIO_IT_STBITERR);                               
+}
+
+
+/**
+  * @brief  SD end of transfer callback.
+  * @param  hsd: SD handle 
+  * @retval None
+  */
+__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SD_XferCpltCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  SD Transfer Error callback.
+  * @param  hsd: SD handle
+  * @retval None
+  */
+__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SD_XferErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  SD Transfer complete Rx callback in non blocking mode.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SD_DMA_RxCpltCallback could be implemented in the user file
+   */ 
+}  
+
+/**
+  * @brief  SD DMA transfer complete Rx error callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SD_DMA_RxErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  SD Transfer complete Tx callback in non blocking mode.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SD_DMA_TxCpltCallback could be implemented in the user file
+   */ 
+}  
+
+/**
+  * @brief  SD DMA transfer complete error Tx callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SD_DMA_TxErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SD_Group3 Peripheral Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================  
+  [..]
+    This subsection provides a set of functions allowing to control the SD card 
+    operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns information about specific card.
+  * @param  hsd: SD handle
+  * @param  pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that  
+  *         contains all SD cardinformation  
+  * @retval SD Card error state
+  */
+HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)
+{
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  uint32_t tmp = 0;
+  
+  pCardInfo->CardType = (uint8_t)(hsd->CardType);
+  pCardInfo->RCA      = (uint16_t)(hsd->RCA);
+  
+  /* Byte 0 */
+  tmp = (hsd->CSD[0] & 0xFF000000) >> 24;
+  pCardInfo->SD_csd.CSDStruct      = (uint8_t)((tmp & 0xC0) >> 6);
+  pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);
+  pCardInfo->SD_csd.Reserved1      = tmp & 0x03;
+  
+  /* Byte 1 */
+  tmp = (hsd->CSD[0] & 0x00FF0000) >> 16;
+  pCardInfo->SD_csd.TAAC = (uint8_t)tmp;
+  
+  /* Byte 2 */
+  tmp = (hsd->CSD[0] & 0x0000FF00) >> 8;
+  pCardInfo->SD_csd.NSAC = (uint8_t)tmp;
+  
+  /* Byte 3 */
+  tmp = hsd->CSD[0] & 0x000000FF;
+  pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp;
+  
+  /* Byte 4 */
+  tmp = (hsd->CSD[1] & 0xFF000000) >> 24;
+  pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4);
+  
+  /* Byte 5 */
+  tmp = (hsd->CSD[1] & 0x00FF0000) >> 16;
+  pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);
+  pCardInfo->SD_csd.RdBlockLen       = (uint8_t)(tmp & 0x0F);
+  
+  /* Byte 6 */
+  tmp = (hsd->CSD[1] & 0x0000FF00) >> 8;
+  pCardInfo->SD_csd.PartBlockRead   = (uint8_t)((tmp & 0x80) >> 7);
+  pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);
+  pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);
+  pCardInfo->SD_csd.DSRImpl         = (uint8_t)((tmp & 0x10) >> 4);
+  pCardInfo->SD_csd.Reserved2       = 0; /*!< Reserved */
+  
+  if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0))
+  {
+    pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10;
+    
+    /* Byte 7 */
+    tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
+    pCardInfo->SD_csd.DeviceSize |= (tmp) << 2;
+    
+    /* Byte 8 */
+    tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
+    pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;
+    
+    pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
+    pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);
+    
+    /* Byte 9 */
+    tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
+    pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
+    pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
+    pCardInfo->SD_csd.DeviceSizeMul      = (tmp & 0x03) << 1;
+    /* Byte 10 */
+    tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
+    pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;
+    
+    pCardInfo->CardCapacity  = (pCardInfo->SD_csd.DeviceSize + 1) ;
+    pCardInfo->CardCapacity *= (1 << (pCardInfo->SD_csd.DeviceSizeMul + 2));
+    pCardInfo->CardBlockSize = 1 << (pCardInfo->SD_csd.RdBlockLen);
+    pCardInfo->CardCapacity *= pCardInfo->CardBlockSize;
+  }
+  else if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
+  {
+    /* Byte 7 */
+    tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
+    pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16;
+    
+    /* Byte 8 */
+    tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
+    
+    pCardInfo->SD_csd.DeviceSize |= (tmp << 8);
+    
+    /* Byte 9 */
+    tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
+    
+    pCardInfo->SD_csd.DeviceSize |= (tmp);
+    
+    /* Byte 10 */
+    tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
+    
+    pCardInfo->CardCapacity  = ((pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024;
+    pCardInfo->CardBlockSize = 512;    
+  }
+    
+  pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;
+  pCardInfo->SD_csd.EraseGrMul  = (tmp & 0x3F) << 1;
+  
+  /* Byte 11 */
+  tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF);
+  pCardInfo->SD_csd.EraseGrMul     |= (tmp & 0x80) >> 7;
+  pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F);
+  
+  /* Byte 12 */
+  tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000) >> 24);
+  pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;
+  pCardInfo->SD_csd.ManDeflECC        = (tmp & 0x60) >> 5;
+  pCardInfo->SD_csd.WrSpeedFact       = (tmp & 0x1C) >> 2;
+  pCardInfo->SD_csd.MaxWrBlockLen     = (tmp & 0x03) << 2;
+  
+  /* Byte 13 */
+  tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16);
+  pCardInfo->SD_csd.MaxWrBlockLen      |= (tmp & 0xC0) >> 6;
+  pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5;
+  pCardInfo->SD_csd.Reserved3           = 0;
+  pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01);
+  
+  /* Byte 14 */
+  tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8);
+  pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7;
+  pCardInfo->SD_csd.CopyFlag         = (tmp & 0x40) >> 6;
+  pCardInfo->SD_csd.PermWrProtect    = (tmp & 0x20) >> 5;
+  pCardInfo->SD_csd.TempWrProtect    = (tmp & 0x10) >> 4;
+  pCardInfo->SD_csd.FileFormat       = (tmp & 0x0C) >> 2;
+  pCardInfo->SD_csd.ECC              = (tmp & 0x03);
+  
+  /* Byte 15 */
+  tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF);
+  pCardInfo->SD_csd.CSD_CRC   = (tmp & 0xFE) >> 1;
+  pCardInfo->SD_csd.Reserved4 = 1;
+  
+  /* Byte 0 */
+  tmp = (uint8_t)((hsd->CID[0] & 0xFF000000) >> 24);
+  pCardInfo->SD_cid.ManufacturerID = tmp;
+  
+  /* Byte 1 */
+  tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16);
+  pCardInfo->SD_cid.OEM_AppliID = tmp << 8;
+  
+  /* Byte 2 */
+  tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8);
+  pCardInfo->SD_cid.OEM_AppliID |= tmp;
+  
+  /* Byte 3 */
+  tmp = (uint8_t)(hsd->CID[0] & 0x000000FF);
+  pCardInfo->SD_cid.ProdName1 = tmp << 24;
+  
+  /* Byte 4 */
+  tmp = (uint8_t)((hsd->CID[1] & 0xFF000000) >> 24);
+  pCardInfo->SD_cid.ProdName1 |= tmp << 16;
+  
+  /* Byte 5 */
+  tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16);
+  pCardInfo->SD_cid.ProdName1 |= tmp << 8;
+  
+  /* Byte 6 */
+  tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8);
+  pCardInfo->SD_cid.ProdName1 |= tmp;
+  
+  /* Byte 7 */
+  tmp = (uint8_t)(hsd->CID[1] & 0x000000FF);
+  pCardInfo->SD_cid.ProdName2 = tmp;
+  
+  /* Byte 8 */
+  tmp = (uint8_t)((hsd->CID[2] & 0xFF000000) >> 24);
+  pCardInfo->SD_cid.ProdRev = tmp;
+  
+  /* Byte 9 */
+  tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16);
+  pCardInfo->SD_cid.ProdSN = tmp << 24;
+  
+  /* Byte 10 */
+  tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8);
+  pCardInfo->SD_cid.ProdSN |= tmp << 16;
+  
+  /* Byte 11 */
+  tmp = (uint8_t)(hsd->CID[2] & 0x000000FF);
+  pCardInfo->SD_cid.ProdSN |= tmp << 8;
+  
+  /* Byte 12 */
+  tmp = (uint8_t)((hsd->CID[3] & 0xFF000000) >> 24);
+  pCardInfo->SD_cid.ProdSN |= tmp;
+  
+  /* Byte 13 */
+  tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16);
+  pCardInfo->SD_cid.Reserved1   |= (tmp & 0xF0) >> 4;
+  pCardInfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8;
+  
+  /* Byte 14 */
+  tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8);
+  pCardInfo->SD_cid.ManufactDate |= tmp;
+  
+  /* Byte 15 */
+  tmp = (uint8_t)(hsd->CID[3] & 0x000000FF);
+  pCardInfo->SD_cid.CID_CRC   = (tmp & 0xFE) >> 1;
+  pCardInfo->SD_cid.Reserved2 = 1;
+  
+  return errorState;
+}
+
+/**
+  * @brief  Enables wide bus operation for the requested card if supported by 
+  *         card.
+  * @param  hsd: SD handle       
+  * @param  WideMode: Specifies the SD card wide bus mode 
+  *          This parameter can be one of the following values:
+  *            @arg SDIO_BUS_WIDE_8B: 8-bit data transfer (Only for MMC)
+  *            @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
+  *            @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
+  * @retval SD Card error state
+  */
+HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode)
+{
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  SDIO_InitTypeDef Init;
+  
+  /* MMC Card does not support this feature */
+  if (hsd->CardType == MULTIMEDIA_CARD)
+  {
+    errorState = SD_UNSUPPORTED_FEATURE;
+    
+    return errorState;
+  }
+  else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
+    (hsd->CardType == HIGH_CAPACITY_SD_CARD))
+  {
+    if (WideMode == SDIO_BUS_WIDE_8B)
+    {
+      errorState = SD_UNSUPPORTED_FEATURE;
+      
+      return errorState;
+    }
+    else if (WideMode == SDIO_BUS_WIDE_4B)
+    {
+      errorState = SD_WideBus_Enable(hsd);
+      
+      if (errorState == SD_OK)
+      {
+        /* Configure the SDIO peripheral */
+        Init.ClockEdge           = SDIO_CLOCK_EDGE_RISING;
+        Init.ClockBypass         = SDIO_CLOCK_BYPASS_DISABLE;
+        Init.ClockPowerSave      = SDIO_CLOCK_POWER_SAVE_DISABLE;
+        Init.BusWide             = SDIO_BUS_WIDE_4B;
+        Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
+        Init.ClockDiv            = SDIO_TRANSFER_CLK_DIV;
+        
+        /* Configure SDIO peripheral interface */
+        SDIO_Init(hsd->Instance, Init);
+      }
+    }
+    else
+    {
+      errorState = SD_WideBus_Disable(hsd);
+      
+      if (errorState == SD_OK)
+      {
+        /* Configure the SDIO peripheral */
+        Init.ClockEdge           = SDIO_CLOCK_EDGE_RISING;
+        Init.ClockBypass         = SDIO_CLOCK_BYPASS_DISABLE;
+        Init.ClockPowerSave      = SDIO_CLOCK_POWER_SAVE_DISABLE;
+        Init.BusWide             = SDIO_BUS_WIDE_1B;
+        Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
+        Init.ClockDiv            = SDIO_TRANSFER_CLK_DIV;
+        
+        /* Configure SDIO peripheral interface */
+        SDIO_Init(hsd->Instance, Init);
+      }
+    }
+  }
+  
+  return errorState;
+}
+
+/**
+  * @brief  Aborts an ongoing data transfer.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd)
+{
+  SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  
+  /* Send CMD12 STOP_TRANSMISSION  */
+  SDIO_CmdInitStructure.Argument         = 0;
+  SDIO_CmdInitStructure.CmdIndex         = SD_CMD_STOP_TRANSMISSION;
+  SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_SHORT;
+  SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
+  SDIO_CmdInitStructure.CPSM             = SDIO_CPSM_ENABLE;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Check for error conditions */
+  errorState = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION);
+  
+  return errorState;
+}
+
+/**
+  * @brief  Switches the SD card to High Speed mode.
+  *         This API must be used after "Transfer State"
+  * @note   This operation should be followed by the configuration 
+  *         of PLL to have SDIOCK clock between 67 and 75 MHz
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
+{
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
+  SDIO_DataInitTypeDef SDIO_DataInitStructure;
+  
+  uint8_t SD_hs[64]  = {0};
+  uint32_t SD_scr[2] = {0, 0};
+  uint32_t SD_SPEC   = 0 ;
+  uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs;
+  
+  /* Initialize the Data control register */
+  hsd->Instance->DCTRL = 0;
+  
+  /* Get SCR Register */
+  errorState = SD_FindSCR(hsd, SD_scr);
+  
+  if (errorState != SD_OK)
+  {
+    return errorState;
+  }
+  
+  /* Test the Version supported by the card*/ 
+  SD_SPEC = (SD_scr[1]  & 0x01000000) | (SD_scr[1]  & 0x02000000);
+  
+  if (SD_SPEC != SD_ALLZERO)
+  {
+    /* Set Block Size for Card */
+    SDIO_CmdInitStructure.Argument         = (uint32_t)64;
+    SDIO_CmdInitStructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
+    SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_SHORT;
+    SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
+    SDIO_CmdInitStructure.CPSM             = SDIO_CPSM_ENABLE;
+    SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+    
+    /* Check for error conditions */
+    errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+    
+    if (errorState != SD_OK)
+    {
+      return errorState;
+    }
+    
+    /* Configure the SD DPSM (Data Path State Machine) */
+    SDIO_DataInitStructure.DataTimeOut   = SD_DATATIMEOUT;
+    SDIO_DataInitStructure.DataLength    = 64;
+    SDIO_DataInitStructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B ;
+    SDIO_DataInitStructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
+    SDIO_DataInitStructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+    SDIO_DataInitStructure.DPSM          = SDIO_DPSM_ENABLE;
+    SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure);
+    
+    /* Send CMD6 switch mode */
+    SDIO_CmdInitStructure.Argument         = 0x80FFFF01;
+    SDIO_CmdInitStructure.CmdIndex         = SD_CMD_HS_SWITCH;
+    SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure); 
+    
+    /* Check for error conditions */
+    errorState = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH);
+    
+    if (errorState != SD_OK)
+    {
+      return errorState;
+    }
+        
+    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+    {
+      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+      {
+        for (count = 0; count < 8; count++)
+        {
+          *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
+        }
+        
+        tempbuff += 8;
+      }
+    }
+    
+    if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+    {
+      __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
+      
+      errorState = SD_DATA_TIMEOUT;
+      
+      return errorState;
+    }
+    else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+    {
+      __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+      
+      errorState = SD_DATA_CRC_FAIL;
+      
+      return errorState;
+    }
+    else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+    {
+      __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
+      
+      errorState = SD_RX_OVERRUN;
+      
+      return errorState;
+    }
+    else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
+    {
+      __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
+      
+      errorState = SD_START_BIT_ERR;
+      
+      return errorState;
+    }
+    
+    count = SD_DATATIMEOUT;
+    
+    while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0))
+    {
+      *tempbuff = SDIO_ReadFIFO(hsd->Instance);
+      tempbuff++;
+      count--;
+    }
+    
+    /* Clear all the static flags */
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+    
+    /* Test if the switch mode HS is ok */
+    if ((SD_hs[13]& 2) != 2)
+    {
+      errorState = SD_UNSUPPORTED_FEATURE;
+    } 
+  }
+  
+  return errorState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SD_Group4 Peripheral State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### Peripheral State functions #####
+  ==============================================================================  
+  [..]
+    This subsection permits to get in runtime the status of the peripheral 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the current SD card's status.
+  * @param  hsd: SD handle
+  * @param  pSDstatus: Pointer to the buffer that will contain the SD card status 
+  *         SD Status register)
+  * @retval SD Card error state
+  */
+HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
+{
+  SDIO_CmdInitTypeDef  SDIO_CmdInitStructure;
+  SDIO_DataInitTypeDef SDIO_DataInitStructure;
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  uint32_t count = 0;
+  
+  /* Check SD response */
+  if ((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
+  {
+    errorState = SD_LOCK_UNLOCK_FAILED;
+    
+    return errorState;
+  }
+  
+  /* Set block size for card if it is not equal to current block size for card */
+  SDIO_CmdInitStructure.Argument         = 64;
+  SDIO_CmdInitStructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
+  SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_SHORT;
+  SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
+  SDIO_CmdInitStructure.CPSM             = SDIO_CPSM_ENABLE;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Check for error conditions */
+  errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+  
+  if (errorState != SD_OK)
+  {
+    return errorState;
+  }
+  
+  /* Send CMD55 */
+  SDIO_CmdInitStructure.Argument         = (uint32_t)(hsd->RCA << 16);
+  SDIO_CmdInitStructure.CmdIndex         = SD_CMD_APP_CMD;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Check for error conditions */
+  errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+  
+  if (errorState != SD_OK)
+  {
+    return errorState;
+  }
+  
+  /* Configure the SD DPSM (Data Path State Machine) */ 
+  SDIO_DataInitStructure.DataTimeOut   = SD_DATATIMEOUT;
+  SDIO_DataInitStructure.DataLength    = 64;
+  SDIO_DataInitStructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;
+  SDIO_DataInitStructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
+  SDIO_DataInitStructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+  SDIO_DataInitStructure.DPSM          = SDIO_DPSM_ENABLE;
+  SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure);
+  
+  /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */
+  SDIO_CmdInitStructure.Argument         = 0;
+  SDIO_CmdInitStructure.CmdIndex         = SD_CMD_SD_APP_STAUS;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Check for error conditions */
+  errorState = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STAUS);
+  
+  if (errorState != SD_OK)
+  {
+    return errorState;
+  }
+  
+  /* Get status data */
+  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+  {
+    if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+    {
+      for (count = 0; count < 8; count++)
+      {
+        *(pSDstatus + count) = SDIO_ReadFIFO(hsd->Instance);
+      }
+      
+      pSDstatus += 8;
+    }
+  }
+  
+  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
+    
+    errorState = SD_DATA_TIMEOUT;
+    
+    return errorState;
+  }
+  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+    
+    errorState = SD_DATA_CRC_FAIL;
+    
+    return errorState;
+  }
+  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
+    
+    errorState = SD_RX_OVERRUN;
+    
+    return errorState;
+  }
+  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
+    
+    errorState = SD_START_BIT_ERR;
+    
+    return errorState;
+  }
+  
+  count = SD_DATATIMEOUT;
+  while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0))
+  {
+    *pSDstatus = SDIO_ReadFIFO(hsd->Instance);
+    pSDstatus++;
+    count--;
+  }
+  
+  /* Clear all the static status flags*/
+  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+  
+  return errorState;
+}
+
+/**
+  * @brief  Gets the current sd card data status.
+  * @param  hsd: SD handle
+  * @retval Data Transfer state
+  */
+HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_CardStateTypedef cardstate =  SD_CARD_TRANSFER;
+
+  /* Get SD card state */
+  cardstate = SD_GetState(hsd);
+  
+  /* Find SD status according to card state*/
+  if (cardstate == SD_CARD_TRANSFER)
+  {
+    return SD_TRANSFER_OK;
+  }
+  else if(cardstate == SD_CARD_ERROR)
+  {
+    return SD_TRANSFER_ERROR;
+  }
+  else
+  {
+    return SD_TRANSFER_BUSY;
+  }
+}
+
+/**
+  * @brief  Gets the SD card status.
+  * @param  hsd: SD handle      
+  * @param  pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that 
+  *         will contain the SD card status information 
+  * @retval SD Card error state
+  */
+HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)
+{
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  uint32_t tmp = 0;
+  uint32_t SD_STATUS[16];
+  
+  errorState = HAL_SD_SendSDStatus(hsd, SD_STATUS);
+  
+  if (errorState  != SD_OK)
+  {
+    return errorState;
+  }
+  
+  /* Byte 0 */
+  tmp = (SD_STATUS[0] & 0xC0) >> 6;
+  pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp;
+  
+  /* Byte 0 */
+  tmp = (SD_STATUS[0] & 0x20) >> 5;
+  pCardStatus->SECURED_MODE = (uint8_t)tmp;
+  
+  /* Byte 2 */
+  tmp = (SD_STATUS[2] & 0xFF);
+  pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8);
+  
+  /* Byte 3 */
+  tmp = (SD_STATUS[3] & 0xFF);
+  pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp;
+  
+  /* Byte 4 */
+  tmp = (SD_STATUS[4] & 0xFF);
+  pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24);
+  
+  /* Byte 5 */
+  tmp = (SD_STATUS[5] & 0xFF);
+  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16);
+  
+  /* Byte 6 */
+  tmp = (SD_STATUS[6] & 0xFF);
+  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8);
+  
+  /* Byte 7 */
+  tmp = (SD_STATUS[7] & 0xFF);
+  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp;
+  
+  /* Byte 8 */
+  tmp = (SD_STATUS[8] & 0xFF);
+  pCardStatus->SPEED_CLASS = (uint8_t)tmp;
+  
+  /* Byte 9 */
+  tmp = (SD_STATUS[9] & 0xFF);
+  pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp;
+  
+  /* Byte 10 */
+  tmp = (SD_STATUS[10] & 0xF0) >> 4;
+  pCardStatus->AU_SIZE = (uint8_t)tmp;
+  
+  /* Byte 11 */
+  tmp = (SD_STATUS[11] & 0xFF);
+  pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8);
+  
+  /* Byte 12 */
+  tmp = (SD_STATUS[12] & 0xFF);
+  pCardStatus->ERASE_SIZE |= (uint8_t)tmp;
+  
+  /* Byte 13 */
+  tmp = (SD_STATUS[13] & 0xFC) >> 2;
+  pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp;
+  
+  /* Byte 13 */
+  tmp = (SD_STATUS[13] & 0x3);
+  pCardStatus->ERASE_OFFSET = (uint8_t)tmp;
+  
+  return errorState;
+}
+         
+/**
+  * @}
+  */
+
+/**
+  * @brief  SD DMA transfer complete Rx callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma)
+{
+  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  
+  /* DMA transfer is complete */
+  hsd->DmaTransferCplt = 1;
+  
+  /* Wait until SD transfer is complete */
+  while(hsd->SdTransferCplt == 0)
+  {
+  }
+  
+  /* Transfer complete user callback */
+  HAL_SD_DMA_RxCpltCallback(hsd->hdmarx);   
+}
+
+/**
+  * @brief  SD DMA transfer Error Rx callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SD_DMA_RxError(DMA_HandleTypeDef *hdma)
+{
+  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  
+  /* Transfer complete user callback */
+  HAL_SD_DMA_RxErrorCallback(hsd->hdmarx);
+}
+
+/**
+  * @brief  SD DMA transfer complete Tx callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma)
+{
+  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  
+  /* DMA transfer is complete */
+  hsd->DmaTransferCplt = 1;
+  
+  /* Wait until SD transfer is complete */
+  while(hsd->SdTransferCplt == 0)
+  {
+  }
+  
+  /* Transfer complete user callback */
+  HAL_SD_DMA_TxCpltCallback(hsd->hdmatx);  
+}
+
+/**
+  * @brief  SD DMA transfer Error Tx callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SD_DMA_TxError(DMA_HandleTypeDef *hdma)
+{
+  SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  /* Transfer complete user callback */
+  HAL_SD_DMA_TxErrorCallback(hsd->hdmatx);
+}
+
+/**
+  * @brief  Returns the SD current state.
+  * @param  hsd: SD handle
+  * @retval SD card current state
+  */
+static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd)
+{
+  uint32_t resp1 = 0;
+  
+  if (SD_SendStatus(hsd, &resp1) != SD_OK)
+  {
+    return SD_CARD_ERROR;
+  }
+  else
+  {
+    return (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F);
+  }
+}
+
+/**
+  * @brief  Initializes all cards or single card as the case may be Card(s) come 
+  *         into standby state.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)
+{
+  SDIO_CmdInitTypeDef SDIO_CmdInitStructure; 
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  uint16_t sd_rca = 1;
+  
+  if(SDIO_GetPowerState(hsd->Instance) == 0) /* Power off */
+  {
+    errorState = SD_REQUEST_NOT_APPLICABLE;
+    
+    return errorState;
+  }
+  
+  if(hsd->CardType != SECURE_DIGITAL_IO_CARD)
+  {
+    /* Send CMD2 ALL_SEND_CID */
+    SDIO_CmdInitStructure.Argument         = 0;
+    SDIO_CmdInitStructure.CmdIndex         = SD_CMD_ALL_SEND_CID;
+    SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_LONG;
+    SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
+    SDIO_CmdInitStructure.CPSM             = SDIO_CPSM_ENABLE;
+    SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+    
+    /* Check for error conditions */
+    errorState = SD_CmdResp2Error(hsd);
+    
+    if(errorState != SD_OK)
+    {
+      return errorState;
+    }
+    
+    /* Get Card identification number data */
+    hsd->CID[0] = SDIO_GetResponse(SDIO_RESP1);
+    hsd->CID[1] = SDIO_GetResponse(SDIO_RESP2);
+    hsd->CID[2] = SDIO_GetResponse(SDIO_RESP3);
+    hsd->CID[3] = SDIO_GetResponse(SDIO_RESP4);
+  }
+  
+  if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1)    || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
+     (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD))
+  {
+    /* Send CMD3 SET_REL_ADDR with argument 0 */
+    /* SD Card publishes its RCA. */
+    SDIO_CmdInitStructure.CmdIndex         = SD_CMD_SET_REL_ADDR;
+    SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_SHORT;
+    SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+    
+    /* Check for error conditions */
+    errorState = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca);
+    
+    if(errorState != SD_OK)
+    {
+      return errorState;
+    }
+  }
+  
+  if (hsd->CardType != SECURE_DIGITAL_IO_CARD)
+  {
+    /* Get the SD card RCA */
+    hsd->RCA = sd_rca;
+    
+    /* Send CMD9 SEND_CSD with argument as card's RCA */
+    SDIO_CmdInitStructure.Argument         = (uint32_t)(hsd->RCA << 16);
+    SDIO_CmdInitStructure.CmdIndex         = SD_CMD_SEND_CSD;
+    SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_LONG;
+    SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+    
+    /* Check for error conditions */
+    errorState = SD_CmdResp2Error(hsd);
+    
+    if(errorState != SD_OK)
+    {
+      return errorState;
+    }
+    
+    /* Get Card Specific Data */
+    hsd->CSD[0] = SDIO_GetResponse(SDIO_RESP1);
+    hsd->CSD[1] = SDIO_GetResponse(SDIO_RESP2);
+    hsd->CSD[2] = SDIO_GetResponse(SDIO_RESP3);
+    hsd->CSD[3] = SDIO_GetResponse(SDIO_RESP4);
+  }
+  
+  /* All cards are initialized */
+  return errorState;
+}
+
+/**
+  * @brief  Selects od Deselects the corresponding card.
+  * @param  hsd: SD handle
+  * @param  addr: Address of the card to be selected  
+  * @retval SD Card error state
+  */
+static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr)
+{
+  SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  
+  /* Send CMD7 SDIO_SEL_DESEL_CARD */
+  SDIO_CmdInitStructure.Argument         = (uint32_t)addr;
+  SDIO_CmdInitStructure.CmdIndex         = SD_CMD_SEL_DESEL_CARD;
+  SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_SHORT;
+  SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
+  SDIO_CmdInitStructure.CPSM             = SDIO_CPSM_ENABLE;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Check for error conditions */
+  errorState = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD);
+  
+  return errorState;
+}
+
+/**
+  * @brief  Enquires cards about their operating voltage and configures clock
+  *         controls and stores SD information that will be needed in future
+  *         in the SD handle.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
+{
+  SDIO_CmdInitTypeDef SDIO_CmdInitStructure; 
+  __IO HAL_SD_ErrorTypedef errorState = SD_OK; 
+  uint32_t response = 0, count = 0, validvoltage = 0;
+  uint32_t SDType = SD_STD_CAPACITY;
+  
+  /* Power ON Sequence -------------------------------------------------------*/
+  /* Disable SDIO Clock */
+  __HAL_SD_SDIO_DISABLE(); 
+  
+  /* Set Power State to ON */
+  SDIO_PowerState_ON(hsd->Instance);
+  
+  /* Enable SDIO Clock */
+  __HAL_SD_SDIO_ENABLE();
+  
+  /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/
+  /* No CMD response required */
+  SDIO_CmdInitStructure.Argument         = 0;
+  SDIO_CmdInitStructure.CmdIndex         = SD_CMD_GO_IDLE_STATE;
+  SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_NO;
+  SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
+  SDIO_CmdInitStructure.CPSM             = SDIO_CPSM_ENABLE;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Check for error conditions */
+  errorState = SD_CmdError(hsd);
+  
+  if(errorState != SD_OK)
+  {
+    /* CMD Response TimeOut (wait for CMDSENT flag) */
+    return errorState;
+  }
+  
+  /* CMD8: SEND_IF_COND ------------------------------------------------------*/
+  /* Send CMD8 to verify SD card interface operating condition */
+  /* Argument: - [31:12]: Reserved (shall be set to '0')
+  - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
+  - [7:0]: Check Pattern (recommended 0xAA) */
+  /* CMD Response: R7 */
+  SDIO_CmdInitStructure.Argument         = SD_CHECK_PATTERN;
+  SDIO_CmdInitStructure.CmdIndex         = SD_SDIO_SEND_IF_COND;
+  SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_SHORT;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Check for error conditions */ 
+  errorState = SD_CmdResp7Error(hsd);
+  
+  if (errorState == SD_OK)
+  {
+    /* SD Card 2.0 */
+    hsd->CardType = STD_CAPACITY_SD_CARD_V2_0; 
+    SDType        = SD_HIGH_CAPACITY;
+  }
+  
+  /* Send CMD55 */
+  SDIO_CmdInitStructure.Argument         = 0;
+  SDIO_CmdInitStructure.CmdIndex         = SD_CMD_APP_CMD;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Check for error conditions */
+  errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+  
+  /* If errorState is Command TimeOut, it is a MMC card */
+  /* If errorState is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
+     or SD card 1.x */
+  if(errorState == SD_OK)
+  {
+    /* SD CARD */
+    /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+    while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))
+    {
+      
+      /* SEND CMD55 APP_CMD with RCA as 0 */
+      SDIO_CmdInitStructure.Argument         = 0;
+      SDIO_CmdInitStructure.CmdIndex         = SD_CMD_APP_CMD;
+      SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_SHORT;
+      SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
+      SDIO_CmdInitStructure.CPSM             = SDIO_CPSM_ENABLE;
+      SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+      
+      /* Check for error conditions */
+      errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+      
+      if(errorState != SD_OK)
+      {
+        return errorState;
+      }
+      
+      /* Send CMD41 */
+      SDIO_CmdInitStructure.Argument         = SD_VOLTAGE_WINDOW_SD | SDType;
+      SDIO_CmdInitStructure.CmdIndex         = SD_CMD_SD_APP_OP_COND;
+      SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_SHORT;
+      SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
+      SDIO_CmdInitStructure.CPSM             = SDIO_CPSM_ENABLE;
+      SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+      
+      /* Check for error conditions */
+      errorState = SD_CmdResp3Error(hsd);
+      
+      if(errorState != SD_OK)
+      {
+        return errorState;
+      }
+      
+      /* Get command response */
+      response = SDIO_GetResponse(SDIO_RESP1);
+      
+      /* Get operating voltage*/
+      validvoltage = (((response >> 31) == 1) ? 1 : 0);
+      
+      count++;
+    }
+    
+    if(count >= SD_MAX_VOLT_TRIAL)
+    {
+      errorState = SD_INVALID_VOLTRANGE;
+      
+      return errorState;
+    }
+    
+    if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
+    {
+      hsd->CardType = HIGH_CAPACITY_SD_CARD;
+    }
+    
+  } /* else MMC Card */
+  
+  return errorState;
+}
+
+/**
+  * @brief  Turns the SDIO output signals off.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  
+  /* Set Power State to OFF */
+  SDIO_PowerState_OFF(hsd->Instance);
+  
+  return errorState;
+}
+
+/**
+  * @brief  Returns the current card's status.
+  * @param  hsd: SD handle
+  * @param  pCardStatus: pointer to the buffer that will contain the SD card 
+  *         status (Card Status register)  
+  * @retval SD Card error state
+  */
+static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
+{
+  SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  
+  if(pCardStatus == NULL)
+  {
+    errorState = SD_INVALID_PARAMETER;
+    
+    return errorState;
+  }
+  
+  /* Send Status command */
+  SDIO_CmdInitStructure.Argument         = (uint32_t)(hsd->RCA << 16);
+  SDIO_CmdInitStructure.CmdIndex         = SD_CMD_SEND_STATUS;
+  SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_SHORT;
+  SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
+  SDIO_CmdInitStructure.CPSM             = SDIO_CPSM_ENABLE;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Check for error conditions */
+  errorState = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS);
+  
+  if(errorState != SD_OK)
+  {
+    return errorState;
+  }
+  
+  /* Get SD card status */
+  *pCardStatus = SDIO_GetResponse(SDIO_RESP1);
+  
+  return errorState;
+}
+
+/**
+  * @brief  Checks for error conditions for CMD0.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  uint32_t timeout, tmp;
+  
+  timeout = SDIO_CMD0TIMEOUT;
+  
+  tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT);
+    
+  while((timeout > 0) && (!tmp))
+  {
+    tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT);
+    timeout--;
+  }
+  
+  if(timeout == 0)
+  {
+    errorState = SD_CMD_RSP_TIMEOUT;
+    return errorState;
+  }
+  
+  /* Clear all the static flags */
+  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+  
+  return errorState;
+}
+
+/**
+  * @brief  Checks for error conditions for R7 response.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_ErrorTypedef errorState = SD_ERROR;
+  uint32_t timeout = SDIO_CMD0TIMEOUT, tmp;
+  
+  tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT); 
+  
+  while((!tmp) && (timeout > 0))
+  {
+    tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT);
+    timeout--;
+  }
+  
+  tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT); 
+  
+  if((timeout == 0) || tmp)
+  {
+    /* Card is not V2.0 compliant or card does not support the set voltage range */
+    errorState = SD_CMD_RSP_TIMEOUT;
+    
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
+    
+    return errorState;
+  }
+  
+  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDREND))
+  {
+    /* Card is SD V2.0 compliant */
+    errorState = SD_OK;
+    
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CMDREND);
+    
+    return errorState;
+  }
+  
+  return errorState;
+}
+
+/**
+  * @brief  Checks for error conditions for R1 response.
+  * @param  hsd: SD handle
+  * @param  SD_CMD: The sent command index  
+  * @retval SD Card error state
+  */
+static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD)
+{
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  uint32_t response_R1;
+  
+  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
+  {
+  }
+  
+  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
+  {
+    errorState = SD_CMD_RSP_TIMEOUT;
+    
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
+    
+    return errorState;
+  }
+  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
+  {
+    errorState = SD_CMD_CRC_FAIL;
+    
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
+    
+    return errorState;
+  }
+  
+  /* Check response received is of desired command */
+  if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD)
+  {
+    errorState = SD_ILLEGAL_CMD;
+    
+    return errorState;
+  }
+  
+  /* Clear all the static flags */
+  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+  
+  /* We have received response, retrieve it for analysis  */
+  response_R1 = SDIO_GetResponse(SDIO_RESP1);
+  
+  if((response_R1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
+  {
+    return errorState;
+  }
+  
+  if((response_R1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
+  {
+    return(SD_ADDR_OUT_OF_RANGE);
+  }
+  
+  if((response_R1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
+  {
+    return(SD_ADDR_MISALIGNED);
+  }
+  
+  if((response_R1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
+  {
+    return(SD_BLOCK_LEN_ERR);
+  }
+  
+  if((response_R1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
+  {
+    return(SD_ERASE_SEQ_ERR);
+  }
+  
+  if((response_R1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
+  {
+    return(SD_BAD_ERASE_PARAM);
+  }
+  
+  if((response_R1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
+  {
+    return(SD_WRITE_PROT_VIOLATION);
+  }
+  
+  if((response_R1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
+  {
+    return(SD_LOCK_UNLOCK_FAILED);
+  }
+  
+  if((response_R1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
+  {
+    return(SD_COM_CRC_FAILED);
+  }
+  
+  if((response_R1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
+  {
+    return(SD_ILLEGAL_CMD);
+  }
+  
+  if((response_R1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
+  {
+    return(SD_CARD_ECC_FAILED);
+  }
+  
+  if((response_R1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
+  {
+    return(SD_CC_ERROR);
+  }
+  
+  if((response_R1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
+  {
+    return(SD_GENERAL_UNKNOWN_ERROR);
+  }
+  
+  if((response_R1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
+  {
+    return(SD_STREAM_READ_UNDERRUN);
+  }
+  
+  if((response_R1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
+  {
+    return(SD_STREAM_WRITE_OVERRUN);
+  }
+  
+  if((response_R1 & SD_OCR_CID_CSD_OVERWRIETE) == SD_OCR_CID_CSD_OVERWRIETE)
+  {
+    return(SD_CID_CSD_OVERWRITE);
+  }
+  
+  if((response_R1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
+  {
+    return(SD_WP_ERASE_SKIP);
+  }
+  
+  if((response_R1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
+  {
+    return(SD_CARD_ECC_DISABLED);
+  }
+  
+  if((response_R1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
+  {
+    return(SD_ERASE_RESET);
+  }
+  
+  if((response_R1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
+  {
+    return(SD_AKE_SEQ_ERROR);
+  }
+  
+  return errorState;
+}
+
+/**
+  * @brief  Checks for error conditions for R3 (OCR) response.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  
+  while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
+  {
+  }
+  
+  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
+  {
+    errorState = SD_CMD_RSP_TIMEOUT;
+    
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
+    
+    return errorState;
+  }
+  
+  /* Clear all the static flags */
+  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+  
+  return errorState;
+}
+
+/**
+  * @brief  Checks for error conditions for R2 (CID or CSD) response.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  
+  while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
+  {
+  }
+    
+  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
+  {
+    errorState = SD_CMD_RSP_TIMEOUT;
+    
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
+    
+    return errorState;
+  }
+  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
+  {
+    errorState = SD_CMD_CRC_FAIL;
+    
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
+    
+    return errorState;
+  }
+  
+  /* Clear all the static flags */
+  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+  
+  return errorState;
+}
+
+/**
+  * @brief  Checks for error conditions for R6 (RCA) response.
+  * @param  hsd: SD handle
+  * @param  SD_CMD: The sent command index
+  * @param  pRCA: Pointer to the variable that will contain the SD card relative 
+  *         address RCA   
+  * @retval SD Card error state
+  */
+static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)
+{
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  uint32_t response_R1;
+  
+  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
+  {
+  }
+  
+  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
+  {
+    errorState = SD_CMD_RSP_TIMEOUT;
+    
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
+    
+    return errorState;
+  }
+  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
+  {
+    errorState = SD_CMD_CRC_FAIL;
+    
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
+    
+    return errorState;
+  }
+  
+  /* Check response received is of desired command */
+  if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD)
+  {
+    errorState = SD_ILLEGAL_CMD;
+    
+    return errorState;
+  }
+  
+  /* Clear all the static flags */
+  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+  
+  /* We have received response, retrieve it.  */
+  response_R1 = SDIO_GetResponse(SDIO_RESP1);
+  
+  if((response_R1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO)
+  {
+    *pRCA = (uint16_t) (response_R1 >> 16);
+    
+    return errorState;
+  }
+  
+  if((response_R1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR)
+  {
+    return(SD_GENERAL_UNKNOWN_ERROR);
+  }
+  
+  if((response_R1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD)
+  {
+    return(SD_ILLEGAL_CMD);
+  }
+  
+  if((response_R1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED)
+  {
+    return(SD_COM_CRC_FAILED);
+  }
+  
+  return errorState;
+}
+
+/**
+  * @brief  Enables the SDIO wide bus mode.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd)
+{
+  SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  
+  uint32_t scr[2] = {0, 0};
+  
+  if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
+  {
+    errorState = SD_LOCK_UNLOCK_FAILED;
+    
+    return errorState;
+  }
+  
+  /* Get SCR Register */
+  errorState = SD_FindSCR(hsd, scr);
+  
+  if(errorState != SD_OK)
+  {
+    return errorState;
+  }
+  
+  /* If requested card supports wide bus operation */
+  if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)
+  {
+    /* Send CMD55 APP_CMD with argument as card's RCA.*/
+    SDIO_CmdInitStructure.Argument         = (uint32_t)(hsd->RCA << 16);
+    SDIO_CmdInitStructure.CmdIndex         = SD_CMD_APP_CMD;
+    SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_SHORT;
+    SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
+    SDIO_CmdInitStructure.CPSM             = SDIO_CPSM_ENABLE;
+    SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+    
+    /* Check for error conditions */
+    errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+    
+    if(errorState != SD_OK)
+    {
+      return errorState;
+    }
+    
+    /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
+    SDIO_CmdInitStructure.Argument         = 2;
+    SDIO_CmdInitStructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;
+    SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+    
+    /* Check for error conditions */
+    errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
+    
+    if(errorState != SD_OK)
+    {
+      return errorState;
+    }
+    
+    return errorState;
+  }
+  else
+  {
+    errorState = SD_REQUEST_NOT_APPLICABLE;
+    
+    return errorState;
+  }
+}   
+
+/**
+  * @brief  Disables the SDIO wide bus mode.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd)
+{
+  SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  
+  uint32_t scr[2] = {0, 0};
+  
+  if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
+  {
+    errorState = SD_LOCK_UNLOCK_FAILED;
+    
+    return errorState;
+  }
+  
+  /* Get SCR Register */
+  errorState = SD_FindSCR(hsd, scr);
+  
+  if(errorState != SD_OK)
+  {
+    return errorState;
+  }
+  
+  /* If requested card supports 1 bit mode operation */
+  if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)
+  {
+    /* Send CMD55 APP_CMD with argument as card's RCA */
+    SDIO_CmdInitStructure.Argument         = (uint32_t)(hsd->RCA << 16);
+    SDIO_CmdInitStructure.CmdIndex         = SD_CMD_APP_CMD;
+    SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_SHORT;
+    SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
+    SDIO_CmdInitStructure.CPSM             = SDIO_CPSM_ENABLE;
+    SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+    
+    /* Check for error conditions */
+    errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+    
+    if(errorState != SD_OK)
+    {
+      return errorState;
+    }
+    
+    /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
+    SDIO_CmdInitStructure.Argument         = 0;
+    SDIO_CmdInitStructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;
+    SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+    
+    /* Check for error conditions */
+    errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
+    
+    if(errorState != SD_OK)
+    {
+      return errorState;
+    }
+    
+    return errorState;
+  }
+  else
+  {
+    errorState = SD_REQUEST_NOT_APPLICABLE;
+    
+    return errorState;
+  }
+}
+  
+  
+/**
+  * @brief  Finds the SD card SCR register value.
+  * @param  hsd: SD handle
+  * @param  pSCR: pointer to the buffer that will contain the SCR value  
+  * @retval SD Card error state
+  */
+static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
+{
+  SDIO_CmdInitTypeDef  SDIO_CmdInitStructure;
+  SDIO_DataInitTypeDef SDIO_DataInitStructure;
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  uint32_t index = 0;
+  uint32_t tempscr[2] = {0, 0};
+  
+  /* Set Block Size To 8 Bytes */
+  /* Send CMD55 APP_CMD with argument as card's RCA */
+  SDIO_CmdInitStructure.Argument         = (uint32_t)8;
+  SDIO_CmdInitStructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
+  SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_SHORT;
+  SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
+  SDIO_CmdInitStructure.CPSM             = SDIO_CPSM_ENABLE;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Check for error conditions */
+  errorState = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+  
+  if(errorState != SD_OK)
+  {
+    return errorState;
+  }
+  
+  /* Send CMD55 APP_CMD with argument as card's RCA */
+  SDIO_CmdInitStructure.Argument         = (uint32_t)((hsd->RCA) << 16);
+  SDIO_CmdInitStructure.CmdIndex         = SD_CMD_APP_CMD;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Check for error conditions */
+  errorState = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+  
+  if(errorState != SD_OK)
+  {
+    return errorState;
+  }
+  SDIO_DataInitStructure.DataTimeOut   = SD_DATATIMEOUT;
+  SDIO_DataInitStructure.DataLength    = 8;
+  SDIO_DataInitStructure.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;
+  SDIO_DataInitStructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
+  SDIO_DataInitStructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+  SDIO_DataInitStructure.DPSM          = SDIO_DPSM_ENABLE;
+  SDIO_DataConfig(hsd->Instance, &SDIO_DataInitStructure);
+  
+  /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
+  SDIO_CmdInitStructure.Argument         = 0;
+  SDIO_CmdInitStructure.CmdIndex         = SD_CMD_SD_APP_SEND_SCR;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  /* Check for error conditions */
+  errorState = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR);
+  
+  if(errorState != SD_OK)
+  {
+    return errorState;
+  }
+  
+  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+  {
+    if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
+    {
+      *(tempscr + index) = SDIO_ReadFIFO(hsd->Instance);
+      index++;
+    }
+  }
+  
+  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
+    
+    errorState = SD_DATA_TIMEOUT;
+    
+    return errorState;
+  }
+  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+    
+    errorState = SD_DATA_CRC_FAIL;
+    
+    return errorState;
+  }
+  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
+    
+    errorState = SD_RX_OVERRUN;
+    
+    return errorState;
+  }
+  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
+  {
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
+    
+    errorState = SD_START_BIT_ERR;
+    
+    return errorState;
+  }
+  
+  /* Clear all the static flags */
+  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+  
+  *(pSCR + 1) = ((tempscr[0] & SD_0TO7BITS) << 24)  | ((tempscr[0] & SD_8TO15BITS) << 8) |\
+    ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24);
+  
+  *(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24)  | ((tempscr[1] & SD_8TO15BITS) << 8) |\
+    ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24);
+  
+  return errorState;
+}
+
+/**
+  * @brief  Checks if the SD card is in programming state.
+  * @param  hsd: SD handle
+  * @param  pStatus: pointer to the variable that will contain the SD card state  
+  * @retval SD Card error state
+  */
+static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus)
+{
+  SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
+  HAL_SD_ErrorTypedef errorState = SD_OK;
+  __IO uint32_t responseR1 = 0;
+  
+  SDIO_CmdInitStructure.Argument         = (uint32_t)(hsd->RCA << 16);
+  SDIO_CmdInitStructure.CmdIndex         = SD_CMD_SEND_STATUS;
+  SDIO_CmdInitStructure.Response         = SDIO_RESPONSE_SHORT;
+  SDIO_CmdInitStructure.WaitForInterrupt = SDIO_WAIT_NO;
+  SDIO_CmdInitStructure.CPSM             = SDIO_CPSM_ENABLE;
+  SDIO_SendCommand(hsd->Instance, &SDIO_CmdInitStructure);
+  
+  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
+  {
+  }
+  
+  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
+  {
+    errorState = SD_CMD_RSP_TIMEOUT;
+    
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
+    
+    return errorState;
+  }
+  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
+  {
+    errorState = SD_CMD_CRC_FAIL;
+    
+    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
+    
+    return errorState;
+  }
+  
+  /* Check response received is of desired command */
+  if((uint32_t)SDIO_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS)
+  {
+    errorState = SD_ILLEGAL_CMD;
+    
+    return errorState;
+  }
+  
+  /* Clear all the static flags */
+  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+  
+  
+  /* We have received response, retrieve it for analysis */
+  responseR1 = SDIO_GetResponse(SDIO_RESP1);
+  
+  /* Find out card status */
+  *pStatus = (uint8_t)((responseR1 >> 9) & 0x0000000F);
+  
+  if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
+  {
+    return errorState;
+  }
+  
+  if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
+  {
+    return(SD_ADDR_OUT_OF_RANGE);
+  }
+  
+  if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
+  {
+    return(SD_ADDR_MISALIGNED);
+  }
+  
+  if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
+  {
+    return(SD_BLOCK_LEN_ERR);
+  }
+  
+  if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
+  {
+    return(SD_ERASE_SEQ_ERR);
+  }
+  
+  if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
+  {
+    return(SD_BAD_ERASE_PARAM);
+  }
+  
+  if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
+  {
+    return(SD_WRITE_PROT_VIOLATION);
+  }
+  
+  if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
+  {
+    return(SD_LOCK_UNLOCK_FAILED);
+  }
+  
+  if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
+  {
+    return(SD_COM_CRC_FAILED);
+  }
+  
+  if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
+  {
+    return(SD_ILLEGAL_CMD);
+  }
+  
+  if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
+  {
+    return(SD_CARD_ECC_FAILED);
+  }
+  
+  if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
+  {
+    return(SD_CC_ERROR);
+  }
+  
+  if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
+  {
+    return(SD_GENERAL_UNKNOWN_ERROR);
+  }
+  
+  if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
+  {
+    return(SD_STREAM_READ_UNDERRUN);
+  }
+  
+  if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
+  {
+    return(SD_STREAM_WRITE_OVERRUN);
+  }
+  
+  if((responseR1 & SD_OCR_CID_CSD_OVERWRIETE) == SD_OCR_CID_CSD_OVERWRIETE)
+  {
+    return(SD_CID_CSD_OVERWRITE);
+  }
+  
+  if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
+  {
+    return(SD_WP_ERASE_SKIP);
+  }
+  
+  if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
+  {
+    return(SD_CARD_ECC_DISABLED);
+  }
+  
+  if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
+  {
+    return(SD_ERASE_RESET);
+  }
+  
+  if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
+  {
+    return(SD_AKE_SEQ_ERROR);
+  }
+  
+  return errorState;
+}   
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SD_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sd.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,666 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_sd.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of SD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SD_H
+#define __STM32F4xx_HAL_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_sdmmc.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SD
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+#define SD_InitTypeDef      SDIO_InitTypeDef 
+#define SD_TypeDef          SDIO_TypeDef
+
+/** 
+  * @brief  SDIO Handle Structure definition  
+  */ 
+typedef struct
+{
+  SD_TypeDef                   *Instance;        /*!< SDIO register base address                     */
+  
+  SD_InitTypeDef               Init;             /*!< SD required parameters                         */
+  
+  HAL_LockTypeDef              Lock;             /*!< SD locking object                              */
+  
+  uint32_t                     CardType;         /*!< SD card type                                   */
+  
+  uint32_t                     RCA;              /*!< SD relative card address                       */
+  
+  uint32_t                     CSD[4];           /*!< SD card specific data table                    */
+  
+  uint32_t                     CID[4];           /*!< SD card identification number table            */
+  
+  __IO uint32_t                SdTransferCplt;   /*!< SD transfer complete flag in non blocking mode */
+  
+  __IO uint32_t                SdTransferErr;    /*!< SD transfer error flag in non blocking mode    */
+  
+  __IO uint32_t                DmaTransferCplt;  /*!< SD DMA transfer complete flag                  */
+  
+  __IO uint32_t                SdOperation;      /*!< SD transfer operation (read/write)             */
+  
+  DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters                    */
+  
+  DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters                    */
+  
+}SD_HandleTypeDef;
+
+/** 
+  * @brief  Card Specific Data: CSD Register   
+  */ 
+typedef struct
+{
+  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
+  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
+  __IO uint8_t  Reserved1;            /*!< Reserved                              */
+  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
+  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
+  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
+  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
+  __IO uint8_t  Reserved2;            /*!< Reserved                              */
+  __IO uint32_t DeviceSize;           /*!< Device Size                           */
+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
+  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
+  __IO uint8_t  Reserved3;            /*!< Reserved                              */
+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
+  __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */
+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
+  __IO uint8_t  FileFormat;           /*!< File format                           */
+  __IO uint8_t  ECC;                  /*!< ECC code                              */
+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
+  __IO uint8_t  Reserved4;            /*!< Always 1                              */
+
+}HAL_SD_CSDTypedef;
+
+/** 
+  * @brief  Card Identification Data: CID Register   
+  */
+typedef struct
+{
+  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
+  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
+  __IO uint32_t ProdName1;       /*!< Product Name part1    */
+  __IO uint8_t  ProdName2;       /*!< Product Name part2    */
+  __IO uint8_t  ProdRev;         /*!< Product Revision      */
+  __IO uint32_t ProdSN;          /*!< Product Serial Number */
+  __IO uint8_t  Reserved1;       /*!< Reserved1             */
+  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
+  __IO uint8_t  CID_CRC;         /*!< CID CRC               */
+  __IO uint8_t  Reserved2;       /*!< Always 1              */
+
+}HAL_SD_CIDTypedef;
+
+/** 
+  * @brief SD Card Status returned by ACMD13  
+  */
+typedef struct
+{
+  __IO uint8_t  DAT_BUS_WIDTH;           /*!< Shows the currently defined data bus width                 */
+  __IO uint8_t  SECURED_MODE;            /*!< Card is in secured mode of operation                       */
+  __IO uint16_t SD_CARD_TYPE;            /*!< Carries information about card type                        */
+  __IO uint32_t SIZE_OF_PROTECTED_AREA;  /*!< Carries information about the capacity of protected area   */
+  __IO uint8_t  SPEED_CLASS;             /*!< Carries information about the speed class of the card      */
+  __IO uint8_t  PERFORMANCE_MOVE;        /*!< Carries information about the card's performance move      */
+  __IO uint8_t  AU_SIZE;                 /*!< Carries information about the card's allocation unit size  */
+  __IO uint16_t ERASE_SIZE;              /*!< Determines the number of AUs to be erased in one operation */
+  __IO uint8_t  ERASE_TIMEOUT;           /*!< Determines the timeout for any number of AU erase          */
+  __IO uint8_t  ERASE_OFFSET;            /*!< Carries information about the erase offset                 */
+
+}HAL_SD_CardStatusTypedef;
+
+/** 
+  * @brief SD Card information structure 
+  */
+typedef struct
+{
+  HAL_SD_CSDTypedef   SD_csd;         /*!< SD card specific data register         */
+  HAL_SD_CIDTypedef   SD_cid;         /*!< SD card identification number register */
+  uint64_t            CardCapacity;   /*!< Card capacity                          */
+  uint32_t            CardBlockSize;  /*!< Card block size                        */
+  uint16_t            RCA;            /*!< SD relative card address               */
+  uint8_t             CardType;       /*!< SD card type                           */
+
+}HAL_SD_CardInfoTypedef;
+
+/** 
+  * @brief  SD Error status enumeration Structure definition  
+  */
+typedef enum
+{
+/** 
+  * @brief  SD specific error defines  
+  */   
+  SD_CMD_CRC_FAIL                    = (1),   /*!< Command response received (but CRC check failed)              */
+  SD_DATA_CRC_FAIL                   = (2),   /*!< Data block sent/received (CRC check failed)                   */
+  SD_CMD_RSP_TIMEOUT                 = (3),   /*!< Command response timeout                                      */
+  SD_DATA_TIMEOUT                    = (4),   /*!< Data timeout                                                  */
+  SD_TX_UNDERRUN                     = (5),   /*!< Transmit FIFO underrun                                        */
+  SD_RX_OVERRUN                      = (6),   /*!< Receive FIFO overrun                                          */
+  SD_START_BIT_ERR                   = (7),   /*!< Start bit not detected on all data signals in wide bus mode   */
+  SD_CMD_OUT_OF_RANGE                = (8),   /*!< Command's argument was out of range.                          */
+  SD_ADDR_MISALIGNED                 = (9),   /*!< Misaligned address                                            */
+  SD_BLOCK_LEN_ERR                   = (10),  /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
+  SD_ERASE_SEQ_ERR                   = (11),  /*!< An error in the sequence of erase command occurs.            */
+  SD_BAD_ERASE_PARAM                 = (12),  /*!< An invalid selection for erase groups                        */
+  SD_WRITE_PROT_VIOLATION            = (13),  /*!< Attempt to program a write protect block                     */
+  SD_LOCK_UNLOCK_FAILED              = (14),  /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
+  SD_COM_CRC_FAILED                  = (15),  /*!< CRC check of the previous command failed                     */
+  SD_ILLEGAL_CMD                     = (16),  /*!< Command is not legal for the card state                      */
+  SD_CARD_ECC_FAILED                 = (17),  /*!< Card internal ECC was applied but failed to correct the data */
+  SD_CC_ERROR                        = (18),  /*!< Internal card controller error                               */
+  SD_GENERAL_UNKNOWN_ERROR           = (19),  /*!< General or unknown error                                     */
+  SD_STREAM_READ_UNDERRUN            = (20),  /*!< The card could not sustain data transfer in stream read operation. */
+  SD_STREAM_WRITE_OVERRUN            = (21),  /*!< The card could not sustain data programming in stream mode   */
+  SD_CID_CSD_OVERWRITE               = (22),  /*!< CID/CSD overwrite error                                      */
+  SD_WP_ERASE_SKIP                   = (23),  /*!< Only partial address space was erased                        */
+  SD_CARD_ECC_DISABLED               = (24),  /*!< Command has been executed without using internal ECC         */
+  SD_ERASE_RESET                     = (25),  /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
+  SD_AKE_SEQ_ERROR                   = (26),  /*!< Error in sequence of authentication.                         */
+  SD_INVALID_VOLTRANGE               = (27),
+  SD_ADDR_OUT_OF_RANGE               = (28),
+  SD_SWITCH_ERROR                    = (29),
+  SD_SDIO_DISABLED                   = (30),
+  SD_SDIO_FUNCTION_BUSY              = (31),
+  SD_SDIO_FUNCTION_FAILED            = (32),
+  SD_SDIO_UNKNOWN_FUNCTION           = (33),
+
+/** 
+  * @brief  Standard error defines   
+  */ 
+  SD_INTERNAL_ERROR                  = (34),
+  SD_NOT_CONFIGURED                  = (35),
+  SD_REQUEST_PENDING                 = (36),
+  SD_REQUEST_NOT_APPLICABLE          = (37),
+  SD_INVALID_PARAMETER               = (38),
+  SD_UNSUPPORTED_FEATURE             = (39),
+  SD_UNSUPPORTED_HW                  = (40),
+  SD_ERROR                           = (41),
+  SD_OK                              = (0) 
+
+}HAL_SD_ErrorTypedef;
+
+/** 
+  * @brief  SD Transfer state enumeration structure
+  */   
+typedef enum
+{
+  SD_TRANSFER_OK    = 0,  /*!< Transfer success      */
+  SD_TRANSFER_BUSY  = 1,  /*!< Transfer is occurring */
+  SD_TRANSFER_ERROR = 2   /*!< Transfer failed       */
+
+}HAL_SD_TransferStateTypedef;
+
+/** 
+  * @brief  SD Card State enumeration structure 
+  */   
+typedef enum
+{
+  SD_CARD_READY                  = ((uint32_t)0x00000001),  /*!< Card state is ready                     */
+  SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002),  /*!< Card is in identification state         */
+  SD_CARD_STANDBY                = ((uint32_t)0x00000003),  /*!< Card is in standby state                */
+  SD_CARD_TRANSFER               = ((uint32_t)0x00000004),  /*!< Card is in transfer state               */  
+  SD_CARD_SENDING                = ((uint32_t)0x00000005),  /*!< Card is sending an operation            */
+  SD_CARD_RECEIVING              = ((uint32_t)0x00000006),  /*!< Card is receiving operation information */
+  SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007),  /*!< Card is in programming state            */
+  SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008),  /*!< Card is disconnected                    */
+  SD_CARD_ERROR                  = ((uint32_t)0x000000FF)   /*!< Card is in error state                  */
+
+}HAL_SD_CardStateTypedef;
+
+/** 
+  * @brief  SD Operation enumeration structure   
+  */   
+typedef enum
+{
+  SD_READ_SINGLE_BLOCK    = 0,  /*!< Read single block operation      */
+  SD_READ_MULTIPLE_BLOCK  = 1,  /*!< Read multiple blocks operation   */
+  SD_WRITE_SINGLE_BLOCK   = 2,  /*!< Write single block operation     */
+  SD_WRITE_MULTIPLE_BLOCK = 3   /*!< Write multiple blocks operation  */
+
+}HAL_SD_OperationTypedef;
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SD_Exported_Constants
+  * @{
+  */
+
+/** 
+  * @brief SD Commands Index 
+  */
+#define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0)   /*!< Resets the SD memory card.                                                               */
+#define SD_CMD_SEND_OP_COND                        ((uint8_t)1)   /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SD_CMD_ALL_SEND_CID                        ((uint8_t)2)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
+#define SD_CMD_SET_REL_ADDR                        ((uint8_t)3)   /*!< Asks the card to publish a new relative address (RCA).                                   */
+#define SD_CMD_SET_DSR                             ((uint8_t)4)   /*!< Programs the DSR of all cards.                                                           */
+#define SD_CMD_SDIO_SEN_OP_COND                    ((uint8_t)5)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its 
+                                                                       operating condition register (OCR) content in the response on the CMD line.              */
+#define SD_CMD_HS_SWITCH                           ((uint8_t)6)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
+#define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7)   /*!< Selects the card by its own relative address and gets deselected by any other address    */
+#define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information 
+                                                                       and asks the card whether card supports voltage.                                         */
+#define SD_CMD_SEND_CSD                            ((uint8_t)9)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
+#define SD_CMD_SEND_CID                            ((uint8_t)10)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
+#define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11)  /*!< SD card doesn't support it.                                                              */
+#define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12)  /*!< Forces the card to stop transmission.                                                    */
+#define SD_CMD_SEND_STATUS                         ((uint8_t)13)  /*!< Addressed card sends its status register.                                                */
+#define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14) 
+#define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15)  /*!< Sends an addressed card into the inactive state.                                         */
+#define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16)  /*!< Sets the block length (in bytes for SDSC) for all following block commands 
+                                                                       (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 
+                                                                       for SDHS and SDXC.                                                                       */
+#define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 
+                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */
+#define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18)  /*!< Continuously transfers data blocks from card to host until interrupted by 
+                                                                       STOP_TRANSMISSION command.                                                               */
+#define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
+#define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20)  /*!< Speed class control command.                                                             */
+#define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23)  /*!< Specify block count for CMD18 and CMD25.                                                 */
+#define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 
+                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */
+#define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
+#define SD_CMD_PROG_CID                            ((uint8_t)26)  /*!< Reserved for manufacturers.                                                              */
+#define SD_CMD_PROG_CSD                            ((uint8_t)27)  /*!< Programming of the programmable bits of the CSD.                                         */
+#define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28)  /*!< Sets the write protection bit of the addressed group.                                    */
+#define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29)  /*!< Clears the write protection bit of the addressed group.                                  */
+#define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30)  /*!< Asks the card to send the status of the write protection bits.                           */
+#define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
+#define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33)  /*!< Sets the address of the last write block of the continuous range to be erased.           */
+#define SD_CMD_ERASE_GRP_START                     ((uint8_t)35)  /*!< Sets the address of the first write block to be erased. Reserved for each command 
+                                                                       system set by switch function command (CMD6).                                            */
+#define SD_CMD_ERASE_GRP_END                       ((uint8_t)36)  /*!< Sets the address of the last write block of the continuous range to be erased. 
+                                                                       Reserved for each command system set by switch function command (CMD6).                  */
+#define SD_CMD_ERASE                               ((uint8_t)38)  /*!< Reserved for SD security applications.                                                   */
+#define SD_CMD_FAST_IO                             ((uint8_t)39)  /*!< SD card doesn't support it (Reserved).                                                   */
+#define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40)  /*!< SD card doesn't support it (Reserved).                                                   */
+#define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by 
+                                                                       the SET_BLOCK_LEN command.                                                               */
+#define SD_CMD_APP_CMD                             ((uint8_t)55)  /*!< Indicates to the card that the next command is an application specific command rather 
+                                                                       than a standard command.                                                                 */
+#define SD_CMD_GEN_CMD                             ((uint8_t)56)  /*!< Used either to transfer a data block to the card or to get a data block from the card 
+                                                                       for general purpose/application specific commands.                                       */
+#define SD_CMD_NO_CMD                              ((uint8_t)64) 
+
+/** 
+  * @brief Following commands are SD Card Specific commands.
+  *        SDIO_APP_CMD should be sent before sending these commands. 
+  */
+#define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus 
+                                                                       widths are given in SCR register.                                                          */
+#define SD_CMD_SD_APP_STAUS                        ((uint8_t)13)  /*!< (ACMD13) Sends the SD status.                                                              */
+#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 
+                                                                       32bit+CRC data block.                                                                      */
+#define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to 
+                                                                       send its operating condition register (OCR) content in the response on the CMD line.       */
+#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42)  /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
+#define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51)  /*!< Reads the SD Configuration Register (SCR).                                                 */
+#define SD_CMD_SDIO_RW_DIRECT                      ((uint8_t)52)  /*!< For SD I/O card only, reserved for security specification.                                 */
+#define SD_CMD_SDIO_RW_EXTENDED                    ((uint8_t)53)  /*!< For SD I/O card only, reserved for security specification.                                 */
+
+/** 
+  * @brief Following commands are SD Card Specific security commands.
+  *        SD_CMD_APP_CMD should be sent before sending these commands. 
+  */
+#define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43)  /*!< For SD card only */
+#define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44)  /*!< For SD card only */
+#define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45)  /*!< For SD card only */
+#define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46)  /*!< For SD card only */
+#define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47)  /*!< For SD card only */
+#define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48)  /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18)  /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25)  /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38)  /*!< For SD card only */
+#define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49)  /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48)  /*!< For SD card only */
+
+/** 
+  * @brief Supported SD Memory Cards 
+  */
+#define STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000)
+#define STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001)
+#define HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002)
+#define MULTIMEDIA_CARD                       ((uint32_t)0x00000003)
+#define SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004)
+#define HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005)
+#define SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006)
+#define HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007)
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SD_Interrupt_Clock
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+ 
+/**
+  * @brief  Enable the SD device.
+  * @retval None
+  */ 
+#define __HAL_SD_SDIO_ENABLE() __SDIO_ENABLE()
+
+/**
+  * @brief  Disable the SD device.
+  * @retval None
+  */
+#define __HAL_SD_SDIO_DISABLE() __SDIO_DISABLE()
+
+/**
+  * @brief  Enable the SDIO DMA transfer.
+  * @retval None
+  */ 
+#define __HAL_SD_SDIO_DMA_ENABLE() __SDIO_DMA_ENABLE()
+
+/**
+  * @brief  Disable the SDIO DMA transfer.
+  * @retval None
+  */
+#define __HAL_SD_SDIO_DMA_DISABLE()  __SDIO_DMA_DISABLE()
+ 
+/**
+  * @brief  Enable the SD device interrupt.
+  * @param  __HANDLE__: SD Handle  
+  * @param  __INTERRUPT__: specifies the SDIO interrupt sources to be enabled.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                                   bus mode interrupt
+  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
+  * @retval None
+  */
+#define __HAL_SD_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SD device interrupt.
+  * @param  __HANDLE__: SD Handle   
+  * @param  __INTERRUPT__: specifies the SDIO interrupt sources to be disabled.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                                   bus mode interrupt
+  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
+  * @retval None
+  */
+#define __HAL_SD_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified SD flag is set or not. 
+  * @param  __HANDLE__: SD Handle   
+  * @param  __FLAG__: specifies the flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
+  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
+  *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
+  *            @arg SDIO_FLAG_RXACT:    Data receive in progress
+  *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+  *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+  *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
+  *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
+  *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
+  *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
+  *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
+  *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
+  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
+  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+  * @retval The new state of SD FLAG (SET or RESET).
+  */
+#define __HAL_SD_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Clear the SD's pending flags.
+  * @param  __HANDLE__: SD Handle  
+  * @param  __FLAG__: specifies the flag to clear.  
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
+  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
+  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+  * @retval None
+  */
+#define __HAL_SD_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Check whether the specified SD interrupt has occurred or not.
+  * @param  __HANDLE__: SD Handle   
+  * @param  __INTERRUPT__: specifies the SDIO interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                                   bus mode interrupt
+  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+  * @retval The new state of SD IT (SET or RESET).
+  */
+#define __HAL_SD_SDIO_GET_IT  (__HANDLE__, __INTERRUPT__) __SDIO_GET_IT  ((__HANDLE__)->Instance, __INTERRUPT__)
+
+/**
+  * @brief  Clear the SD's interrupt pending bits.
+  * @param  __HANDLE__ : SD Handle
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIO_DCOUNT, is zero) interrupt
+  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                                   bus mode interrupt
+  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
+  * @retval None
+  */
+#define __HAL_SD_SDIO_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+/**
+  * @}
+  */
+  
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions  **********************************/
+HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
+HAL_StatusTypeDef   HAL_SD_DeInit (SD_HandleTypeDef *hsd);
+void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
+void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
+
+/* I/O operation functions  *****************************************************/
+/* Blocking mode: Polling */
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);
+
+/* Non-Blocking mode: Interrupt */
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
+
+/* Callback in non blocking modes (DMA) */
+void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
+
+/* Non-Blocking mode: DMA */
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
+HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
+
+/* Peripheral Control functions  ************************************************/
+HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
+HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
+HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
+HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
+
+/* Peripheral State functions  **************************************************/
+HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
+HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_SD_H */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,847 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_sdram.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   SDRAM HAL module driver.
+  *          This file provides a generic firmware to drive SDRAM memories mounted 
+  *          as external device.
+  *         
+  @verbatim
+  ==============================================================================
+                       ##### How to use this driver #####
+  ============================================================================== 
+  [..]
+    This driver is a generic layered driver which contains a set of APIs used to 
+    control SDRAM memories. It uses the FMC layer functions to interface 
+    with SDRAM devices.  
+    The following sequence should be followed to configure the FMC to interface
+    with SDRAM memories: 
+      
+   (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
+          SDRAM_HandleTypeDef  hdsram 
+          
+       (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed 
+            values of the structure member.
+            
+       (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined 
+            base register instance for NOR or SDRAM device 
+             
+   (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
+          FMC_SDRAM_TimingTypeDef  Timing;
+      and fill its fields with the allowed values of the structure member.
+      
+   (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
+       performs the following sequence:
+          
+       (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
+       (##) Control register configuration using the FMC SDRAM interface function 
+            FMC_SDRAM_Init()
+       (##) Timing register configuration using the FMC SDRAM interface function 
+            FMC_SDRAM_Timing_Init()
+       (##) Program the SDRAM external device by applying its initialization sequence
+            according to the device plugged in your hardware. This step is mandatory
+            for accessing the SDRAM device.   
+
+   (#) At this stage you can perform read/write accesses from/to the memory connected 
+       to the SDRAM Bank. You can perform either polling or DMA transfer using the
+       following APIs:
+       (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
+       (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
+       
+   (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
+       HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or 
+       the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
+       device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef 
+       structure.   
+       
+   (#) You can continuously monitor the SDRAM device HAL state by calling the function
+       HAL_SDRAM_GetState()         
+      
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SDRAM 
+  * @brief SDRAM driver modules
+  * @{
+  */
+#ifdef HAL_SDRAM_MODULE_ENABLED
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/    
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SDRAM_Private_Functions
+  * @{
+  */
+
+/** @defgroup SDRAM_Group1 Initialization and de-initialization functions 
+  * @brief    Initialization and Configuration functions 
+  *
+  @verbatim    
+  ==============================================================================
+           ##### SDRAM Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to initialize/de-initialize
+    the SDRAM memory
+  
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Performs the SDRAM device initialization sequence.
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  Timing: Pointer to SDRAM control timing structure 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
+{   
+  /* Check the SDRAM handle parameter */
+  if(hsdram == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  if(hsdram->State == HAL_SDRAM_STATE_RESET)
+  {  
+    /* Initialize the low level hardware (MSP) */
+    HAL_SDRAM_MspInit(hsdram);
+  }
+  
+  /* Initialize the SDRAM controller state */
+  hsdram->State = HAL_SDRAM_STATE_BUSY;
+  
+  /* Initialize SDRAM control Interface */
+  FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
+  
+  /* Initialize SDRAM timing Interface */
+  FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); 
+  
+  /* Update the SDRAM controller state */
+  hsdram->State = HAL_SDRAM_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Perform the SDRAM device initialization sequence.
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
+{
+  /* Initialize the low level hardware (MSP) */
+  HAL_SDRAM_MspDeInit(hsdram);
+
+  /* Configure the SDRAM registers with their reset values */
+  FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
+
+  /* Reset the SDRAM controller state */
+  hsdram->State = HAL_SDRAM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsdram);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  SDRAM MSP Init.
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval None
+  */
+__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_SDRAM_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  SDRAM MSP DeInit.
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval None
+  */
+__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_SDRAM_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  This function handles SDRAM refresh error interrupt request.
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval HAL status
+*/
+void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
+{
+  /* Check SDRAM interrupt Rising edge flag */
+  if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
+  {
+    /* SDRAM refresh error interrupt callback */
+    HAL_SDRAM_RefreshErrorCallback(hsdram);
+    
+    /* Clear SDRAM refresh error interrupt pending bit */
+    __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
+  }
+}
+
+/**
+  * @brief  SDRAM Refresh error callback.
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module. 
+  * @retval None
+  */
+__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  DMA transfer complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  DMA transfer complete error callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SDRAM_Group2 Input and Output functions 
+  * @brief    Input Output and memory control functions 
+  *
+  @verbatim    
+  ==============================================================================
+                    ##### SDRAM Input and Output functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to use and control the SDRAM memory
+  
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads 8-bit data buffer from the SDRAM memory.
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress: Pointer to read start address
+  * @param  pDstBuffer: Pointer to destination buffer  
+  * @param  BufferSize: Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
+{
+  __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
+  
+  /* Process Locked */
+  __HAL_LOCK(hsdram);
+  
+  /* Check the SDRAM controller state */
+  if(hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
+  {
+    return  HAL_ERROR; 
+  }  
+  
+  /* Read data from source */
+  for(; BufferSize != 0; BufferSize--)
+  {
+    *pDstBuffer = *(__IO uint8_t *)pSdramAddress;  
+    pDstBuffer++;
+    pSdramAddress++;
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsdram);
+  
+  return HAL_OK; 
+}
+
+
+/**
+  * @brief  Writes 8-bit data buffer to SDRAM memory.
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress: Pointer to write start address
+  * @param  pSrcBuffer: Pointer to source buffer to write  
+  * @param  BufferSize: Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
+{
+  __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
+  uint32_t tmp = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hsdram);
+  
+  /* Check the SDRAM controller state */
+  tmp = hsdram->State;
+  
+  if(tmp == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
+  {
+    return  HAL_ERROR; 
+  }
+  
+  /* Write data to memory */
+  for(; BufferSize != 0; BufferSize--)
+  {
+    *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
+    pSrcBuffer++;
+    pSdramAddress++;
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsdram);    
+  
+  return HAL_OK;   
+}
+
+
+/**
+  * @brief  Reads 16-bit data buffer from the SDRAM memory. 
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress: Pointer to read start address
+  * @param  pDstBuffer: Pointer to destination buffer  
+  * @param  BufferSize: Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
+{
+  __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
+  
+  /* Process Locked */
+  __HAL_LOCK(hsdram);
+  
+  /* Check the SDRAM controller state */
+  if(hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
+  {
+    return  HAL_ERROR; 
+  }  
+  
+  /* Read data from source */
+  for(; BufferSize != 0; BufferSize--)
+  {
+    *pDstBuffer = *(__IO uint16_t *)pSdramAddress;  
+    pDstBuffer++;
+    pSdramAddress++;               
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsdram);       
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Writes 16-bit data buffer to SDRAM memory. 
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress: Pointer to write start address
+  * @param  pSrcBuffer: Pointer to source buffer to write  
+  * @param  BufferSize: Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
+{
+  __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
+  uint32_t tmp = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hsdram);
+  
+  /* Check the SDRAM controller state */
+  tmp = hsdram->State;
+  
+  if(tmp == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
+  {
+    return  HAL_ERROR; 
+  }
+  
+  /* Write data to memory */
+  for(; BufferSize != 0; BufferSize--)
+  {
+    *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
+    pSrcBuffer++;
+    pSdramAddress++;            
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsdram);    
+  
+  return HAL_OK;   
+}
+
+/**
+  * @brief  Reads 32-bit data buffer from the SDRAM memory. 
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress: Pointer to read start address
+  * @param  pDstBuffer: Pointer to destination buffer  
+  * @param  BufferSize: Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+{
+  __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
+  
+  /* Process Locked */
+  __HAL_LOCK(hsdram);
+  
+  /* Check the SDRAM controller state */
+  if(hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
+  {
+    return  HAL_ERROR; 
+  }  
+  
+  /* Read data from source */
+  for(; BufferSize != 0; BufferSize--)
+  {
+    *pDstBuffer = *(__IO uint32_t *)pSdramAddress;  
+    pDstBuffer++;
+    pSdramAddress++;               
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsdram);       
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Writes 32-bit data buffer to SDRAM memory. 
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress: Pointer to write start address
+  * @param  pSrcBuffer: Pointer to source buffer to write  
+  * @param  BufferSize: Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+{
+  __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
+  uint32_t tmp = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hsdram);
+  
+  /* Check the SDRAM controller state */
+  tmp = hsdram->State;
+  
+  if(tmp == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
+  {
+    return  HAL_ERROR; 
+  }
+  
+  /* Write data to memory */
+  for(; BufferSize != 0; BufferSize--)
+  {
+    *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
+    pSrcBuffer++;
+    pSdramAddress++;          
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsdram);    
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Reads a Words data from the SDRAM memory using DMA transfer. 
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress: Pointer to read start address
+  * @param  pDstBuffer: Pointer to destination buffer  
+  * @param  BufferSize: Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+{
+  uint32_t tmp = 0;
+    
+  /* Process Locked */
+  __HAL_LOCK(hsdram);
+  
+  /* Check the SDRAM controller state */  
+  tmp = hsdram->State;
+  
+  if(tmp == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
+  {
+    return  HAL_ERROR; 
+  }  
+  
+  /* Configure DMA user callbacks */
+  hsdram->hdma->XferCpltCallback  = HAL_SDRAM_DMA_XferCpltCallback;
+  hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
+  
+  /* Enable the DMA Stream */
+  HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsdram);  
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Writes a Words data buffer to SDRAM memory using DMA transfer.
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress: Pointer to write start address
+  * @param  pSrcBuffer: Pointer to source buffer to write  
+  * @param  BufferSize: Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+{
+  uint32_t tmp = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(hsdram);
+  
+  /* Check the SDRAM controller state */  
+  tmp = hsdram->State;
+  
+  if(tmp == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
+  {
+    return  HAL_ERROR; 
+  }  
+  
+  /* Configure DMA user callbacks */
+  hsdram->hdma->XferCpltCallback  = HAL_SDRAM_DMA_XferCpltCallback;
+  hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
+  
+  /* Enable the DMA Stream */
+  HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsdram);
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup SDRAM_Group3 Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+  ==============================================================================
+                         ##### SDRAM Control functions #####
+  ==============================================================================  
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the SDRAM interface.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables dynamically SDRAM write protection.
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
+{ 
+  /* Check the SDRAM controller state */ 
+  if(hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  
+  /* Update the SDRAM state */
+  hsdram->State = HAL_SDRAM_STATE_BUSY;
+  
+  /* Enable write protection */
+  FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
+  
+  /* Update the SDRAM state */
+  hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Disables dynamically SDRAM write protection.
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
+{
+  /* Check the SDRAM controller state */
+  if(hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  
+  /* Update the SDRAM state */
+  hsdram->State = HAL_SDRAM_STATE_BUSY;
+  
+  /* Disable write protection */
+  FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
+  
+  /* Update the SDRAM state */
+  hsdram->State = HAL_SDRAM_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Sends Command to the SDRAM bank.
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  Command: SDRAM command structure
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */  
+HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
+{
+  /* Check the SDRAM controller state */
+  if(hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  
+  /* Update the SDRAM state */
+  hsdram->State = HAL_SDRAM_STATE_BUSY;
+  
+  /* Send SDRAM command */
+  FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
+  
+  /* Update the SDRAM controller state state */
+  if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
+  {
+    hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
+  }
+  else
+  {
+    hsdram->State = HAL_SDRAM_STATE_READY;
+  }
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Programs the SDRAM Memory Refresh rate.
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.  
+  * @param  RefreshRate: The SDRAM refresh rate value       
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
+{
+  /* Check the SDRAM controller state */
+  if(hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  } 
+  
+  /* Update the SDRAM state */
+  hsdram->State = HAL_SDRAM_STATE_BUSY;
+  
+  /* Program the refresh rate */
+  FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
+  
+  /* Update the SDRAM state */
+  hsdram->State = HAL_SDRAM_STATE_READY;
+  
+  return HAL_OK;   
+}
+
+/**
+  * @brief  Sets the Number of consecutive SDRAM Memory auto Refresh commands.
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.  
+  * @param  AutoRefreshNumber: The SDRAM auto Refresh number       
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
+{
+  /* Check the SDRAM controller state */
+  if(hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  } 
+  
+  /* Update the SDRAM state */
+  hsdram->State = HAL_SDRAM_STATE_BUSY;
+  
+  /* Set the Auto-Refresh number */
+  FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
+  
+  /* Update the SDRAM state */
+  hsdram->State = HAL_SDRAM_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns the SDRAM memory current mode.
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval The SDRAM memory mode.        
+  */
+uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
+{
+  /* Return the SDRAM memory current mode */
+  return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup SDRAM_Group4 State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### SDRAM State functions #####
+  ==============================================================================  
+  [..]
+    This subsection permits to get in run-time the status of the SDRAM controller 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the SDRAM state.
+  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval HAL state
+  */
+HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
+{
+  return hsdram->State;
+}
+
+/**
+  * @}
+  */    
+
+/**
+  * @}
+  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,152 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_sdram.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of SDRAM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SDRAM_H
+#define __STM32F4xx_HAL_SDRAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_fmc.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SDRAM
+  * @{
+  */ 
+
+/* Exported typedef ----------------------------------------------------------*/   
+
+/** 
+  * @brief  HAL SDRAM State structure definition  
+  */ 
+typedef enum
+{
+  HAL_SDRAM_STATE_RESET             = 0x00,  /*!< SDRAM not yet initialized or disabled */
+  HAL_SDRAM_STATE_READY             = 0x01,  /*!< SDRAM initialized and ready for use   */
+  HAL_SDRAM_STATE_BUSY              = 0x02,  /*!< SDRAM internal process is ongoing     */
+  HAL_SDRAM_STATE_ERROR             = 0x03,  /*!< SDRAM error state                     */
+  HAL_SDRAM_STATE_WRITE_PROTECTED   = 0x04,  /*!< SDRAM device write protected          */
+  HAL_SDRAM_STATE_PRECHARGED        = 0x05   /*!< SDRAM device precharged               */
+  
+}HAL_SDRAM_StateTypeDef;
+
+/** 
+  * @brief  SDRAM handle Structure definition  
+  */ 
+typedef struct
+{
+  FMC_SDRAM_TypeDef             *Instance;  /*!< Register base address                 */
+  
+  FMC_SDRAM_InitTypeDef         Init;       /*!< SDRAM device configuration parameters */
+  
+  __IO HAL_SDRAM_StateTypeDef   State;      /*!< SDRAM access state                    */
+  
+  HAL_LockTypeDef               Lock;       /*!< SDRAM locking object                  */ 
+
+  DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                   */
+  
+}SDRAM_HandleTypeDef;
+         
+/* Exported types ------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset SDRAM handle state
+  * @param  __HANDLE__: specifies the SDRAM handle.
+  * @retval None
+  */
+#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
+HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
+
+void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+
+/* I/O operation functions  *****************************************************/
+HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+
+HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+
+/* SDRAM Control functions  *****************************************************/
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
+HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
+HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
+uint32_t          HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
+
+/* SDRAM State functions ********************************************************/
+HAL_SDRAM_StateTypeDef  HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SDRAM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1366 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_smartcard.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   SMARTCARD HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the SMARTCARD peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions 
+  *           
+  @verbatim       
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The SMARTCARD HAL driver can be used as follows:
+    
+    (#) Declare a SMARTCARD_HandleTypeDef handle structure.
+    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
+        (##) Enable the USARTx interface clock.
+        (##) SMARTCARD pins configuration:
+            (+++) Enable the clock for the SMARTCARD GPIOs.
+            (+++) Configure these SMARTCARD pins as alternate function pull-up.
+        (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
+             and HAL_SMARTCARD_Receive_IT() APIs):
+            (+++) Configure the USARTx interrupt priority.
+            (+++) Enable the NVIC USART IRQ handle.
+        (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
+             and HAL_SMARTCARD_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx stream.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.                
+            (+++) Configure the DMA Tx/Rx Stream.
+            (+++) Associate the initilalized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
+
+    (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware 
+        flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure.
+
+    (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
+        (++) These APIs configure also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+             by calling the customed HAL_SMARTCARD_MspInit() API.
+    [..]  
+    (@) The specific SMARTCARD interrupts (Transmission complete interrupt, 
+        RXNE interrupt and Error Interrupts) will be managed using the macros
+        __SMARTCARD_ENABLE_IT() and __SMARTCARD_DISABLE_IT() inside the transmit and receive process.
+                   
+    [..]   
+    Three operation modes are available within this driver :     
+  
+    *** Polling mode IO operation ***
+    =================================
+    [..]    
+      (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit() 
+      (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
+       
+    *** Interrupt mode IO operation ***    
+    ===================================
+    [..]    
+      (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT() 
+      (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can 
+          add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
+      (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT() 
+      (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can 
+          add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
+      (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can 
+          add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
+
+    *** DMA mode IO operation ***    
+    ==============================
+    [..] 
+      (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA() 
+      (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can 
+          add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
+      (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA() 
+      (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can 
+          add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
+      (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can 
+          add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback    
+
+    *** SMARTCARD HAL driver macros list ***
+    ============================================= 
+    [..]
+      Below the list of most used macros in SMARTCARD HAL driver.
+       
+      (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral 
+      (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral     
+      (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not
+      (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
+      (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
+      (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
+    
+    [..]  
+      (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+          
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SMARTCARD 
+  * @brief HAL USART SMARTCARD module driver
+  * @{
+  */
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define SMARTCARD_TIMEOUT_VALUE  22000
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc);
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SMARTCARD_Private_Functions
+  * @{
+  */
+
+/** @defgroup SMARTCARD_Group1 SmartCard Initialization and de-initialization functions 
+  *  @brief    Initialization and Configuration functions 
+  *
+@verbatim 
+ ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USART 
+    in Smartcard mode.
+    [..]
+    The Smartcard interface is designed to support asynchronous protocol Smartcards as
+    defined in the ISO 7816-3 standard.
+    [..]
+    The USART can provide a clock to the smartcard through the SCLK output.
+    In smartcard mode, SCLK is not associated to the communication but is simply derived 
+    from the internal peripheral input clock through a 5-bit prescaler.
+    [..]
+      (+) For the asynchronous mode only these parameters can be configured:
+        (++) Baud Rate
+        (++) Word Length 
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+             Depending on the frame length defined by the M bit (8-bits or 9-bits),
+             please refer to Reference manual for possible SMARTDARD frame formats.
+        (++) USART polarity
+        (++) USART phase
+        (++) USART LastBit
+        (++) Receiver/transmitter modes
+        (++) Prescaler
+        (++) GuardTime
+        (++) NACKState: The Smartcard NACK state
+
+     (+) Recommended SmartCard interface configuration to get the Answer to Reset from the Card:
+        (++) Word Length = 9 Bits
+        (++) 1.5 Stop Bit
+        (++) Even parity
+        (++) BaudRate = 12096 baud
+        (++) Tx and Rx enabled
+    [..]
+    Please refer to the ISO 7816-3 specification for more details.
+
+      -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended 
+          to use 1.5 stop bits for both transmitting and receiving to avoid switching 
+          between the two configurations.
+    [..]
+    The HAL_SMARTCARD_Init() function follows the USART  SmartCard configuration 
+    procedure (details for the procedure are available in reference manual (RM0329)).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Initializes the SmartCard mode according to the specified
+  *         parameters in the SMARTCARD_InitTypeDef and create the associated handle .
+  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
+{
+  /* Check the SMARTCARD handle allocation */
+  if(hsc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
+  assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
+
+  if(hsc->State == HAL_SMARTCARD_STATE_RESET)
+  {  
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_SMARTCARD_MspInit(hsc);
+  }
+  
+  hsc->State = HAL_SMARTCARD_STATE_BUSY;
+
+  /* Set the Prescaler */
+  MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_PSC, hsc->Init.Prescaler);
+
+  /* Set the Guard Time */
+  MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8));
+
+  /* Set the Smartcard Communication parameters */
+  SMARTCARD_SetConfig(hsc);
+
+  /* In SmartCard mode, the following bits must be kept cleared: 
+  - LINEN bit in the USART_CR2 register
+  - HDSEL and IREN bits in the USART_CR3 register.*/
+  hsc->Instance->CR2 &= ~USART_CR2_LINEN;
+  hsc->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_HDSEL);
+
+  /* Enable the SMARTCARD Parity Error Interrupt */
+  __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
+
+  /* Enable the SMARTCARD Framing Error Interrupt */
+  __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
+
+  /* Enable the Peripharal */
+  __SMARTCARD_ENABLE(hsc);
+
+  /* Configure the Smartcard NACK state */
+  MODIFY_REG(hsc->Instance->CR3, USART_CR3_NACK, hsc->Init.NACKState);
+
+  /* Enable the SC mode by setting the SCEN bit in the CR3 register */
+  hsc->Instance->CR3 |= (USART_CR3_SCEN);
+
+  /* Initialize the SMARTCARD state*/
+  hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+  hsc->State= HAL_SMARTCARD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief DeInitializes the USART SmartCard peripheral 
+  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
+{
+  /* Check the SMARTCARD handle allocation */
+  if(hsc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
+
+  hsc->State = HAL_SMARTCARD_STATE_BUSY;
+
+  /* DeInit the low level hardware */
+  HAL_SMARTCARD_MspDeInit(hsc);
+
+  hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+  hsc->State = HAL_SMARTCARD_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief SMARTCARD MSP Init
+  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @retval None
+  */
+ __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_MspInit could be implenetd in the user file
+   */
+}
+
+/**
+  * @brief SMARTCARD MSP DeInit
+  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @retval None
+  */
+ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_MspDeInit could be implenetd in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Group2 IO operation functions 
+  *  @brief   SMARTCARD Transmit and Receive functions 
+  *
+@verbatim   
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
+    [..]
+    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
+    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver 
+    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
+    While receiving data, transmission should be avoided as the data to be transmitted
+    could be corrupted.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode: The communication is performed in polling mode. 
+            The HAL status of all data processing is returned by the same function 
+            after finishing transfer.  
+       (++) Non Blocking mode: The communication is performed using Interrupts 
+           or DMA, These APIs return the HAL status.
+           The end of the data processing will be indicated through the 
+           dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when 
+           using DMA mode.
+           The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks 
+           will be executed respectivelly at the end of the Transmit or Receive process
+           The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected
+
+    (#) Blocking mode APIs are :
+        (++) HAL_SMARTCARD_Transmit()
+        (++) HAL_SMARTCARD_Receive() 
+
+    (#) Non Blocking mode APIs with Interrupt are :
+        (++) HAL_SMARTCARD_Transmit_IT()
+        (++) HAL_SMARTCARD_Receive_IT()
+        (++) HAL_SMARTCARD_IRQHandler()
+
+    (#) Non Blocking mode functions with DMA are :
+        (++) HAL_SMARTCARD_Transmit_DMA()
+        (++) HAL_SMARTCARD_Receive_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_SMARTCARD_TxCpltCallback()
+        (++) HAL_SMARTCARD_RxCpltCallback()
+        (++) HAL_SMARTCARD_ErrorCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Send an amount of data in blocking mode 
+  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @param pData: pointer to data buffer
+  * @param Size: amount of data to be sent
+  * @param Timeout: Timeout duration 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+  uint32_t tmp1 = 0;
+  
+  tmp1 = hsc->State;
+  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
+  {
+    if((pData == NULL) || (Size == 0)) 
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsc);
+
+    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    /* Check if a non-blocking receive process is ongoing or not */
+    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) 
+    {
+      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+    }
+    
+    hsc->TxXferSize = Size;
+    hsc->TxXferCount = Size;
+    while(hsc->TxXferCount > 0)
+    {
+      hsc->TxXferCount--;
+      if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
+      {
+        if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+        tmp = (uint16_t*) pData;
+        hsc->Instance->DR = (*tmp & (uint16_t)0x01FF);
+        if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
+        {
+          pData +=2;
+        }
+        else
+        {
+          pData +=1;
+        }
+      }
+      else
+      {
+        if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+        hsc->Instance->DR = (*pData++ & (uint8_t)0xFF);
+      }
+    }
+
+    if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Check if a non-blocking receive process is ongoing or not */
+    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) 
+    {
+      hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+    }
+    else
+    {
+      hsc->State = HAL_SMARTCARD_STATE_READY;
+    }
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsc);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode 
+  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @param pData: pointer to data buffer
+  * @param Size: amount of data to be received
+  * @param Timeout: Timeout duration   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+  uint32_t tmp1 = 0;
+  
+  tmp1 = hsc->State;
+  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
+  {
+    if((pData == NULL) || (Size == 0)) 
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsc);
+    
+    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+    /* Check if a non-blocking transmit process is ongoing or not */
+    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) 
+    {
+      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+    }
+
+    hsc->RxXferSize = Size;
+    hsc->RxXferCount = Size;
+    /* Check the remain data to be received */
+    while(hsc->RxXferCount > 0)
+    {
+      hsc->RxXferCount--;
+      if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
+      {
+        if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+        tmp = (uint16_t*) pData;
+        if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
+        {
+          *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x01FF);
+          pData +=2;
+        }
+        else
+        {
+          *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
+          pData +=1;
+        }
+      }
+      else
+      {
+        if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+        if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
+        {
+          *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
+        }
+        else
+        {
+          *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x007F);
+        }
+      }
+    }
+
+    /* Check if a non-blocking transmit process is ongoing or not */
+    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) 
+    {
+      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+    }
+    else
+    {
+      hsc->State = HAL_SMARTCARD_STATE_READY;
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsc);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Send an amount of data in non blocking mode 
+  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @param pData: pointer to data buffer
+  * @param Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tmp1 = 0;
+  
+  tmp1 = hsc->State;
+  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
+  {
+    if((pData == NULL) || (Size == 0)) 
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsc);
+
+    hsc->pTxBuffPtr = pData;
+    hsc->TxXferSize = Size;
+    hsc->TxXferCount = Size;
+
+    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    /* Check if a non-blocking receive process is ongoing or not */
+    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) 
+    {
+      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+    }
+
+    /* Enable the SMARTCARD Parity Error Interrupt */
+    __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
+
+    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+    __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsc);
+
+    /* Enable the SMARTCARD Transmit Complete Interrupt */
+    __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in non blocking mode 
+  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @param pData: pointer to data buffer
+  * @param Size: amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tmp1 = 0;
+  
+  tmp1 = hsc->State;
+  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
+  {
+    if((pData == NULL) || (Size == 0)) 
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsc);
+
+    hsc->pRxBuffPtr = pData;
+    hsc->RxXferSize = Size;
+    hsc->RxXferCount = Size;
+
+    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    /* Check if a non-blocking transmit process is ongoing or not */
+    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) 
+    {
+      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+    }
+
+    /* Enable the SMARTCARD Data Register not empty Interrupt */
+    __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE); 
+
+    /* Enable the SMARTCARD Parity Error Interrupt */
+    __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
+
+    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+    __SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsc);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Send an amount of data in non blocking mode 
+  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @param pData: pointer to data buffer
+  * @param Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
+{
+  uint32_t *tmp;
+  uint32_t tmp1 = 0;
+  
+  tmp1 = hsc->State;
+  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
+  {
+    if((pData == NULL) || (Size == 0)) 
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsc);
+
+    hsc->pTxBuffPtr = pData;
+    hsc->TxXferSize = Size;
+    hsc->TxXferCount = Size;
+
+    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    /* Check if a non-blocking receive process is ongoing or not */
+    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) 
+    {
+      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+    }
+
+    /* Set the SMARTCARD DMA transfert complete callback */
+    hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
+
+    /* Set the DMA error callback */
+    hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
+
+    /* Enable the SMARTCARD transmit DMA Stream */
+    tmp = (uint32_t*)&pData;
+    HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+    in the SMARTCARD CR3 register */
+    hsc->Instance->CR3 |= USART_CR3_DMAT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsc);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in non blocking mode 
+  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @param pData: pointer to data buffer
+  * @param Size: amount of data to be received
+  * @note   When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.s
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
+{
+  uint32_t *tmp;
+  uint32_t tmp1 = 0;
+  
+  tmp1 = hsc->State;
+  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
+  {
+    if((pData == NULL) || (Size == 0)) 
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsc);
+
+    hsc->pRxBuffPtr = pData;
+    hsc->RxXferSize = Size;
+
+    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    /* Check if a non-blocking transmit process is ongoing or not */
+    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) 
+    {
+      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+    }
+
+    /* Set the SMARTCARD DMA transfert complete callback */
+    hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
+
+    /* Set the DMA error callback */
+    hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
+
+    /* Enable the DMA Stream */
+    tmp = (uint32_t*)&pData;
+    HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
+    in the SMARTCARD CR3 register */
+    hsc->Instance->CR3 |= USART_CR3_DMAR;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsc);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief This function handles SMARTCARD interrupt request.
+  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @retval None
+  */
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
+{
+  uint32_t tmp1 = 0, tmp2 = 0; 
+  
+  tmp1 = hsc->Instance->SR;  
+  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE);
+
+  /* SMARTCARD parity error interrupt occured --------------------------------*/
+  if(((tmp1 & SMARTCARD_FLAG_PE) != RESET) && (tmp2 != RESET))
+  { 
+    __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_PE);
+    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
+  }
+  
+  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
+  /* SMARTCARD frame error interrupt occured ---------------------------------*/
+  if(((tmp1 & SMARTCARD_FLAG_FE) != RESET) && (tmp2 != RESET))
+  { 
+    __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_FE);
+    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+  }
+  
+  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
+  /* SMARTCARD noise error interrupt occured ---------------------------------*/
+  if(((tmp1 & SMARTCARD_FLAG_NE) != RESET) && (tmp2 != RESET))
+  { 
+    __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_NE);
+    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+  }
+
+  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
+  /* SMARTCARD Over-Run interrupt occured ------------------------------------*/
+  if(((tmp1 & SMARTCARD_FLAG_ORE) != RESET) && (tmp2 != RESET))
+  { 
+    __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_ORE);
+    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+  }
+  
+  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RXNE);
+  /* SMARTCARD in mode Receiver ----------------------------------------------*/
+  if(((tmp1 & SMARTCARD_FLAG_RXNE) != RESET) && (tmp2 != RESET))
+  { 
+    SMARTCARD_Receive_IT(hsc);
+    __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_RXNE);
+  }
+
+  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC);
+  /* SMARTCARD in mode Transmitter -------------------------------------------*/
+  if(((tmp1 & SMARTCARD_FLAG_TC) != RESET) && (tmp2 != RESET))
+  {
+    SMARTCARD_Transmit_IT(hsc);
+    __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC);
+  }
+  
+  /* Call the Error call Back in case of Errors */
+  if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+  {
+    /* Set the SMARTCARD state ready to be able to start again the process */
+    hsc->State= HAL_SMARTCARD_STATE_READY;
+    HAL_SMARTCARD_ErrorCallback(hsc);
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callbacks
+  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @retval None
+  */
+ __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief Rx Transfer completed callbacks
+  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief SMARTCARD error callbacks
+  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @retval None
+  */
+ __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_ErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Group3 Peripheral State and Errors functions 
+  *  @brief   SMARTCARD State and Errors functions 
+  *
+@verbatim   
+ ===============================================================================
+                ##### Peripheral State and Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the SmartCard.
+     (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SmartCard peripheral.
+     (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occured durung communication. 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief return the SMARTCARD state
+  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @retval HAL state
+  */
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)
+{
+  return hsc->State;
+}
+
+/**
+  * @brief  Return the SMARTCARD error code
+  * @param  hsc : pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *              the configuration information for the specified SMARTCARD.
+  * @retval SMARTCARD Error Code
+  */
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)
+{
+  return hsc->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief DMA SMARTCARD transmit process complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  hsc->TxXferCount = 0;
+  
+  /* Disable the DMA transfer for transmit request by setting the DMAT bit
+  in the USART CR3 register */
+  hsc->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
+
+  /* Wait for SMARTCARD TC Flag */
+  if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, SMARTCARD_TIMEOUT_VALUE) != HAL_OK)
+  {
+    /* Timeout Occured */ 
+    hsc->State = HAL_SMARTCARD_STATE_TIMEOUT;
+    HAL_SMARTCARD_ErrorCallback(hsc);
+  }
+  else
+  {
+    /* No Timeout */
+    /* Check if a non-blocking receive process is ongoing or not */
+    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) 
+    {
+      hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+    }
+    else
+    {
+      hsc->State = HAL_SMARTCARD_STATE_READY;
+    }
+    HAL_SMARTCARD_TxCpltCallback(hsc);
+  }
+}
+
+/**
+  * @brief DMA SMARTCARD receive process complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)   
+{
+  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  hsc->RxXferCount = 0;
+  
+  /* Disable the DMA transfer for the receiver request by setting the DMAR bit 
+  in the USART CR3 register */
+  hsc->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
+  
+  /* Check if a non-blocking transmit process is ongoing or not */
+  if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) 
+  {
+    hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+  }
+  else
+  {
+    hsc->State = HAL_SMARTCARD_STATE_READY;
+  }
+  
+  HAL_SMARTCARD_RxCpltCallback(hsc);
+}
+
+/**
+  * @brief DMA SMARTCARD communication error callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)   
+{
+  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  hsc->RxXferCount = 0;
+  hsc->TxXferCount = 0;
+  hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+  hsc->State= HAL_SMARTCARD_STATE_READY;
+
+  HAL_SMARTCARD_ErrorCallback(hsc);
+}
+
+/**
+  * @brief  This function handles SMARTCARD Communication Timeout.
+  * @param  hsc: SMARTCARD handle
+  * @param  Flag: specifies the SMARTCARD flag to check.
+  * @param  Status: The new Flag status (SET or RESET).
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+  uint32_t timeout = 0;
+  
+  timeout = HAL_GetTick() + Timeout;
+  
+  /* Wait until flag is set */
+  if(Status == RESET)
+  {    
+    while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) == RESET)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Disable TXE and RXNE interrupts for the interrupt process */
+          __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
+          __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
+          
+          hsc->State= HAL_SMARTCARD_STATE_READY;
+          
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsc);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  else
+  {
+    while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) != RESET)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Disable TXE and RXNE interrupts for the interrupt process */
+          __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
+          __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
+          
+          hsc->State= HAL_SMARTCARD_STATE_READY;
+          
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsc);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief Send an amount of data in non blocking mode 
+  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
+{
+  uint16_t* tmp;
+  uint32_t tmp1 = 0;
+  
+  tmp1 = hsc->State;
+  if((tmp1 == HAL_SMARTCARD_STATE_BUSY_TX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX))
+  {
+    if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
+    {
+      tmp = (uint16_t*) hsc->pTxBuffPtr;
+      hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
+      if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
+      {
+        hsc->pTxBuffPtr += 2;
+      }
+      else
+      {
+        hsc->pTxBuffPtr += 1;
+      }
+    } 
+    else
+    {
+      hsc->Instance->DR = (uint8_t)(*hsc->pTxBuffPtr++ & (uint8_t)0x00FF);
+    }
+    
+    if(--hsc->TxXferCount == 0)
+    {
+      /* Disable the SMARTCARD Transmit Complete Interrupt */
+      __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TC);
+      
+      /* Disable the SMARTCARD Parity Error Interrupt */
+      __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
+      
+      /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+      __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
+      
+      /* Check if a non-blocking receive process is ongoing or not */
+      if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) 
+      {
+        hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+      }
+      else
+      {
+        hsc->State = HAL_SMARTCARD_STATE_READY;
+      }
+      
+      HAL_SMARTCARD_TxCpltCallback(hsc);
+      
+      return HAL_OK;
+    }
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;   
+  }
+}
+
+/**
+  * @brief Receive an amount of data in non blocking mode 
+  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
+{
+  uint16_t* tmp;
+  uint32_t tmp1 = 0;
+  
+  tmp1 = hsc->State;
+  if((tmp1 == HAL_SMARTCARD_STATE_BUSY_RX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX))
+  {
+    if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
+    {
+      tmp = (uint16_t*) hsc->pRxBuffPtr;
+      if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
+      {
+        *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x01FF);
+        hsc->pRxBuffPtr += 2;
+      }
+      else
+      {
+        *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
+        hsc->pRxBuffPtr += 1;
+      }
+    } 
+    else
+    {
+      if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
+      {
+        *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
+      }
+      else
+      {
+        *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x007F);
+      }
+    }
+    
+    if(--hsc->RxXferCount == 0)
+    {
+      while(HAL_IS_BIT_SET(hsc->Instance->SR, SMARTCARD_FLAG_RXNE))
+      {
+      }
+      __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
+      
+      /* Disable the SMARTCARD Parity Error Interrupt */
+      __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
+      
+      /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+      __SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
+      
+      /* Check if a non-blocking transmit process is ongoing or not */
+      if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) 
+      {
+        hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+      }
+      else
+      {
+        hsc->State = HAL_SMARTCARD_STATE_READY;
+      }
+      
+      HAL_SMARTCARD_RxCpltCallback(hsc);
+      
+      return HAL_OK;
+    }
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY; 
+  }
+}
+
+/**
+  * @brief Configure the SMARTCARD peripheral 
+  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
+{
+  uint32_t tmpreg = 0x00;
+  
+  /* Check the parameters */
+  assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
+  assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity));
+  assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase));
+  assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit));
+  assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate));  
+  assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength));
+  assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits));
+  assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity));
+  assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode));
+  assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
+
+  /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
+     receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
+  hsc->Instance->CR1 &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
+  
+  /*---------------------------- USART CR2 Configuration ---------------------*/
+  tmpreg = hsc->Instance->CR2;
+  /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+  tmpreg &= (uint32_t)~((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL));
+  /* Configure the SMARTCARD Clock, CPOL, CPHA and LastBit -----------------------*/
+  /* Set CPOL bit according to hsc->Init.CLKPolarity value */
+  /* Set CPHA bit according to hsc->Init.CLKPhase value */
+  /* Set LBCL bit according to hsc->Init.CLKLastBit value */
+  /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
+  tmpreg |= (uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity | 
+                      hsc->Init.CLKPhase| hsc->Init.CLKLastBit | hsc->Init.StopBits);
+  /* Write to USART CR2 */
+  hsc->Instance->CR2 = (uint32_t)tmpreg;
+  
+  tmpreg = hsc->Instance->CR2;
+
+  /* Clear STOP[13:12] bits */
+  tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
+
+  /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
+  tmpreg |= (uint32_t)(hsc->Init.StopBits);
+  
+  /* Write to USART CR2 */
+  hsc->Instance->CR2 = (uint32_t)tmpreg;
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  tmpreg = hsc->Instance->CR1;
+
+  /* Clear M, PCE, PS, TE and RE bits */
+  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
+                                   USART_CR1_RE));
+
+  /* Configure the SMARTCARD Word Length, Parity and mode: 
+     Set the M bits according to hsc->Init.WordLength value 
+     Set PCE and PS bits according to hsc->Init.Parity value
+     Set TE and RE bits according to hsc->Init.Mode value */
+  tmpreg |= (uint32_t)hsc->Init.WordLength | hsc->Init.Parity | hsc->Init.Mode;
+
+  /* Write to USART CR1 */
+  hsc->Instance->CR1 = (uint32_t)tmpreg;
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/  
+  /* Clear CTSE and RTSE bits */
+  hsc->Instance->CR3 &= (uint32_t)~((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  if((hsc->Instance == USART1) || (hsc->Instance == USART6))
+  {
+    hsc->Instance->BRR = __SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
+  }
+  else
+  {
+    hsc->Instance->BRR = __SMARTCARD_BRR(HAL_RCC_GetPCLK1Freq(), hsc->Init.BaudRate);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_smartcard.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,453 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_smartcard.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of SMARTCARD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SMARTCARD_H
+#define __STM32F4xx_HAL_SMARTCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SMARTCARD
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** 
+  * @brief SMARTCARD Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This member configures the SmartCard communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                           - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
+                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref SMARTCARD_Word_Length */
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref SMARTCARD_Stop_Bits */
+
+  uint32_t Parity;                   /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref SMARTCARD_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits).*/
+
+  uint32_t Mode;                      /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref SMARTCARD_Mode */
+
+  uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
+
+  uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref SMARTCARD_Clock_Phase */
+
+  uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref SMARTCARD_Last_Bit */
+
+  uint32_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler. 
+                                           This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
+
+  uint32_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time. 
+                                            This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
+
+  uint32_t NACKState;                 /*!< Specifies the SmartCard NACK Transmission state.
+                                           This parameter can be a value of @ref SmartCard_NACK_State */
+}SMARTCARD_InitTypeDef;
+
+/** 
+  * @brief HAL State structures definition
+  */
+typedef enum
+{
+  HAL_SMARTCARD_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized                  */
+  HAL_SMARTCARD_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
+  HAL_SMARTCARD_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */
+  HAL_SMARTCARD_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */
+  HAL_SMARTCARD_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
+  HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */ 
+  HAL_SMARTCARD_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
+  HAL_SMARTCARD_STATE_ERROR             = 0x04     /*!< Error                                              */
+}HAL_SMARTCARD_StateTypeDef;
+
+/** 
+  * @brief  HAL SMARTCARD Error Code structure definition
+  */
+typedef enum
+{
+  HAL_SMARTCARD_ERROR_NONE      = 0x00,    /*!< No error            */
+  HAL_SMARTCARD_ERROR_PE        = 0x01,    /*!< Parity error        */
+  HAL_SMARTCARD_ERROR_NE        = 0x02,    /*!< Noise error         */
+  HAL_SMARTCARD_ERROR_FE        = 0x04,    /*!< frame error         */
+  HAL_SMARTCARD_ERROR_ORE       = 0x08,    /*!< Overrun error       */
+  HAL_SMARTCARD_ERROR_DMA       = 0x10     /*!< DMA transfer error  */
+}HAL_SMARTCARD_ErrorTypeDef;
+
+/** 
+  * @brief  SMARTCARD handle Structure definition
+  */
+typedef struct
+{
+  USART_TypeDef                    *Instance;        /* USART registers base address */
+
+  SMARTCARD_InitTypeDef            Init;            /* SmartCard communication parameters */
+
+  uint8_t                          *pTxBuffPtr;      /* Pointer to SmartCard Tx transfer Buffer */
+
+  uint16_t                         TxXferSize;       /* SmartCard Tx Transfer size */
+
+  uint16_t                         TxXferCount;      /* SmartCard Tx Transfer Counter */
+
+  uint8_t                          *pRxBuffPtr;      /* Pointer to SmartCard Rx transfer Buffer */
+
+  uint16_t                         RxXferSize;       /* SmartCard Rx Transfer size */
+
+  uint16_t                         RxXferCount;      /* SmartCard Rx Transfer Counter */
+
+  DMA_HandleTypeDef                *hdmatx;          /* SmartCard Tx DMA Handle parameters */
+
+  DMA_HandleTypeDef                *hdmarx;          /* SmartCard Rx DMA Handle parameters */
+
+  HAL_LockTypeDef                  Lock;            /* Locking object */
+
+  __IO HAL_SMARTCARD_StateTypeDef  State;           /* SmartCard communication state */
+
+  __IO HAL_SMARTCARD_ErrorTypeDef  ErrorCode;       /* SMARTCARD Error code */
+}SMARTCARD_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Constants
+  * @{
+  */
+
+/** @defgroup SMARTCARD_Word_Length 
+  * @{
+  */
+#define SMARTCARD_WORDLENGTH_8B                  ((uint32_t)0x00000000)
+#define SMARTCARD_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
+#define IS_SMARTCARD_WORD_LENGTH(LENGTH) (((LENGTH) == SMARTCARD_WORDLENGTH_8B) || \
+                                          ((LENGTH) == SMARTCARD_WORDLENGTH_9B))
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Stop_Bits 
+  * @{
+  */
+#define SMARTCARD_STOPBITS_1                     ((uint32_t)0x00000000)
+#define SMARTCARD_STOPBITS_0_5                   ((uint32_t)USART_CR2_STOP_0)
+#define SMARTCARD_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
+#define SMARTCARD_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_1) || \
+                                         ((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
+                                         ((STOPBITS) == SMARTCARD_STOPBITS_1_5) || \
+                                         ((STOPBITS) == SMARTCARD_STOPBITS_2))
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Parity 
+  * @{
+  */
+#define SMARTCARD_PARITY_NONE                    ((uint32_t)0x00000000)
+#define SMARTCARD_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
+#define SMARTCARD_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
+#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_NONE) || \
+                                     ((PARITY) == SMARTCARD_PARITY_EVEN) || \
+                                     ((PARITY) == SMARTCARD_PARITY_ODD))
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Mode 
+  * @{
+  */
+#define SMARTCARD_MODE_RX                        ((uint32_t)USART_CR1_RE)
+#define SMARTCARD_MODE_TX                        ((uint32_t)USART_CR1_TE)
+#define SMARTCARD_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Clock_Polarity 
+  * @{
+  */
+#define SMARTCARD_POLARITY_LOW                   ((uint32_t)0x00000000)
+#define SMARTCARD_POLARITY_HIGH                  ((uint32_t)USART_CR2_CPOL)
+#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
+/**
+  * @}
+  */ 
+
+/** @defgroup SMARTCARD_Clock_Phase
+  * @{
+  */
+#define SMARTCARD_PHASE_1EDGE                    ((uint32_t)0x00000000)
+#define SMARTCARD_PHASE_2EDGE                    ((uint32_t)USART_CR2_CPHA)
+#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Last_Bit
+  * @{
+  */
+#define SMARTCARD_LASTBIT_DISABLE                ((uint32_t)0x00000000)
+#define SMARTCARD_LASTBIT_ENABLE                 ((uint32_t)USART_CR2_LBCL)
+#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
+                                       ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup SmartCard_NACK_State 
+  * @{
+  */
+#define SMARTCARD_NACK_ENABLED                  ((uint32_t)USART_CR3_NACK)
+#define SMARTCARD_NACK_DISABLED                 ((uint32_t)0x00000000)
+#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLED) || \
+                                       ((NACK) == SMARTCARD_NACK_DISABLED))
+/**
+  * @}
+  */
+
+/** @defgroup SmartCard_DMA_Requests 
+  * @{
+  */
+
+#define SMARTCARD_DMAREQ_TX                    ((uint32_t)USART_CR3_DMAT)
+#define SMARTCARD_DMAREQ_RX                    ((uint32_t)USART_CR3_DMAR)
+
+/**
+  * @}
+  */
+
+/** @defgroup SmartCard_Flags 
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the SR register
+  * @{
+  */
+
+#define SMARTCARD_FLAG_TXE                       ((uint32_t)0x00000080)
+#define SMARTCARD_FLAG_TC                        ((uint32_t)0x00000040)
+#define SMARTCARD_FLAG_RXNE                      ((uint32_t)0x00000020)
+#define SMARTCARD_FLAG_IDLE                      ((uint32_t)0x00000010)
+#define SMARTCARD_FLAG_ORE                       ((uint32_t)0x00000008)
+#define SMARTCARD_FLAG_NE                        ((uint32_t)0x00000004)
+#define SMARTCARD_FLAG_FE                        ((uint32_t)0x00000002)
+#define SMARTCARD_FLAG_PE                        ((uint32_t)0x00000001)
+/**
+  * @}
+  */
+
+/** @defgroup SmartCard_Interrupt_definition 
+  *        Elements values convention: 0xY000XXXX
+  *           - XXXX  : Interrupt mask in the XX register
+  *           - Y  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR3 register
+
+  *
+  * @{
+  */
+#define SMARTCARD_IT_PE                          ((uint32_t)0x10000100)
+#define SMARTCARD_IT_TXE                         ((uint32_t)0x10000080)
+#define SMARTCARD_IT_TC                          ((uint32_t)0x10000040)
+#define SMARTCARD_IT_RXNE                        ((uint32_t)0x10000020)
+#define SMARTCARD_IT_IDLE                        ((uint32_t)0x10000010)
+#define SMARTCARD_IT_ERR                         ((uint32_t)0x20000001)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset SMARTCARD handle state
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
+
+/** @brief  Flushs the Smartcard DR register 
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  */
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
+    
+/** @brief  Checks whether the specified Smartcard flag is set or not.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg SMARTCARD_FLAG_TXE:  Transmit data register empty flag
+  *            @arg SMARTCARD_FLAG_TC:   Transmission Complete flag
+  *            @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
+  *            @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
+  *            @arg SMARTCARD_FLAG_ORE:  OverRun Error flag
+  *            @arg SMARTCARD_FLAG_NE:   Noise Error flag
+  *            @arg SMARTCARD_FLAG_FE:   Framing Error flag
+  *            @arg SMARTCARD_FLAG_PE:   Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clears the specified Smartcard pending flags.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg SMARTCARD_FLAG_TC:   Transmission Complete flag.
+  *            @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
+  *   
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error) and ORE (OverRun 
+  *          error) flags are cleared by software sequence: a read operation to 
+  *          USART_SR register followed by a read operation to USART_DR register.
+  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
+  * @note   TC flag can be also cleared by software sequence: a read operation to 
+  *          USART_SR register followed by a write operation to USART_DR register.
+  * @note   TXE flag is cleared only by a write to the USART_DR register.
+  */
+#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+
+/** @brief  Enables or disables the specified SmartCard interrupts.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __INTERRUPT__: specifies the SMARTCARD interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt
+  *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt
+  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+  *            @arg SMARTCARD_IT_PE:   Parity Error interrupt
+  *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  */
+#define SMARTCARD_IT_MASK  ((uint32_t)0x0000FFFF)
+#define __SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+                                                             ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
+#define __SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+                                                             ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
+
+/** @brief  Checks whether the specified SmartCard interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the SmartCard Handle.
+  * @param  __IT__: specifies the SMARTCARD interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
+  *            @arg SMARTCARD_IT_TC:  Transmission complete interrupt
+  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+  *            @arg SMARTCARD_IT_ERR: Error interrupt
+  *            @arg SMARTCARD_IT_PE: Parity Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
+
+/** @brief  Macros to enable or disable the SmartCard interface.
+  * @param  __HANDLE__: specifies the SmartCard Handle.
+  */
+#define __SMARTCARD_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+#define __SMARTCARD_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+
+/** @brief  Macros to enable or disable the SmartCard DMA request.
+  * @param  __HANDLE__: specifies the SmartCard Handle.
+  * @param  __REQUEST__: specifies the SmartCard DMA request.
+  *          This parameter can be one of the following values:
+  *            @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
+  *            @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
+  */
+#define __SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__)    ((__HANDLE__)->Instance->CR3 |=  (__REQUEST__))
+#define __SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__)   ((__HANDLE__)->Instance->CR3 &=  ~(__REQUEST__))
+
+#define __DIV(_PCLK_, _BAUD_)                        (((_PCLK_)*25)/(4*(_BAUD_)))
+#define __DIVMANT(_PCLK_, _BAUD_)                    (__DIV((_PCLK_), (_BAUD_))/100)
+#define __DIVFRAQ(_PCLK_, _BAUD_)                    (((__DIV((_PCLK_), (_BAUD_)) - (__DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define __SMARTCARD_BRR(_PCLK_, _BAUD_)              ((__DIVMANT((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
+
+/* Peripheral State functions  **************************************************/
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
+uint32_t                   HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SMARTCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,2065 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_spi.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   SPI HAL module driver.
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The SPI HAL driver can be used as follows:
+
+      (#) Declare a SPI_HandleTypeDef handle structure, for example:
+          SPI_HandleTypeDef  hspi; 
+
+      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
+          (##) Enable the SPIx interface clock 
+          (##) SPI pins configuration
+              (+++) Enable the clock for the SPI GPIOs 
+              (+++) Configure these SPI pins as alternate function push-pull
+          (##) NVIC configuration if you need to use interrupt process
+              (+++) Configure the SPIx interrupt priority
+              (+++) Enable the NVIC SPI IRQ handle
+          (##) DMA Configuration if you need to use DMA process
+              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
+              (+++) Enable the DMAx interface clock using 
+              (+++) Configure the DMA handle parameters 
+              (+++) Configure the DMA Tx or Rx Stream
+              (+++) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle
+              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
+
+      (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS 
+          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
+
+      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
+          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+              by calling the customed HAL_SPI_MspInit() API.
+            
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SPI 
+  * @brief SPI HAL module driver
+  * @{
+  */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define SPI_TIMEOUT_VALUE  10
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
+static void SPI_TxISR(SPI_HandleTypeDef *hspi);
+static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
+static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
+static void SPI_RxISR(SPI_HandleTypeDef *hspi);
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SPI_Private_Functions
+  * @{
+  */
+
+/** @defgroup SPI_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and 
+          de-initialiaze the SPIx peripheral:
+
+      (+) User must implement HAL_SPI_MspInit() function in which he configures 
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_SPI_Init() to configure the selected device with 
+          the selected configuration:
+        (++) Mode
+        (++) Direction 
+        (++) Data Size
+        (++) Clock Polarity and Phase
+        (++) NSS Management
+        (++) BaudRate Prescaler
+        (++) FirstBit
+        (++) TIMode
+        (++) CRC Calculation
+        (++) CRC Polynomial if CRC enabled
+
+      (+) Call the function HAL_SPI_DeInit() to restore the default configuration 
+          of the selected SPIx periperal.       
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SPI according to the specified parameters 
+  *         in the SPI_InitTypeDef and create the associated handle.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
+{
+  /* Check the SPI handle allocation */
+  if(hspi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SPI_MODE(hspi->Init.Mode));
+  assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
+  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
+  assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
+  assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+  assert_param(IS_SPI_NSS(hspi->Init.NSS));
+  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
+  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
+  assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+
+  if(hspi->State == HAL_SPI_STATE_RESET)
+  {
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    HAL_SPI_MspInit(hspi);
+  }
+  
+  hspi->State = HAL_SPI_STATE_BUSY;
+
+  /* Disble the selected SPI peripheral */
+  __HAL_SPI_DISABLE(hspi);
+
+  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
+  /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
+  Communication speed, First bit and CRC calculation state */
+  hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
+                         hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
+                         hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation);
+
+  /* Configure : NSS management */
+  hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode);
+
+  /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
+  /* Configure : CRC Polynomial */
+  hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
+
+  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
+  hspi->Instance->I2SCFGR &= (uint32_t)(~SPI_I2SCFGR_I2SMOD);
+
+  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+  hspi->State = HAL_SPI_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the SPI peripheral 
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
+{
+  /* Check the SPI handle allocation */
+  if(hspi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the SPI Peripheral Clock */
+  __HAL_SPI_DISABLE(hspi);
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+  HAL_SPI_MspDeInit(hspi);
+
+  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+  hspi->State = HAL_SPI_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hspi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief SPI MSP Init
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @retval None
+  */
+ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
+ {
+   /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SPI_MspInit could be implenetd in the user file
+   */
+}
+
+/**
+  * @brief SPI MSP DeInit
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @retval None
+  */
+ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SPI_MspDeInit could be implenetd in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group2 IO operation functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of functions allowing to manage the SPI
+    data transfers.
+
+    [..] The SPI supports master and slave mode :
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode: The communication is performed in polling mode.
+            The HAL status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) No-Blocking mode: The communication is performed using Interrupts
+           or DMA, These APIs return the HAL status.
+           The end of the data processing will be indicated through the 
+           dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when 
+           using DMA mode.
+           The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks 
+           will be executed respectivelly at the end of the transmit or Receive process
+           The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
+
+    (#) Blocking mode APIs are :
+        (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
+        (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
+        (++) HAL_SPI_TransmitReceive() in full duplex mode
+
+    (#) Non Blocking mode API's with Interrupt are :
+        (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
+        (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
+        (++) HAL_SPI_TransmitReceive_IT()in full duplex mode
+        (++) HAL_SPI_IRQHandler()
+
+    (#) Non Blocking mode functions with DMA are :
+        (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
+        (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
+        (++) HAL_SPI_TransmitReceie_DMA() in full duplex mode
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_SPI_TxCpltCallback()
+        (++) HAL_SPI_RxCpltCallback()
+        (++) HAL_SPI_ErrorCallback()
+        (++) HAL_SPI_TxRxCpltCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmit an amount of data in blocking mode
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size: amount of data to be sent
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+
+  if(hspi->State == HAL_SPI_STATE_READY)
+  {
+    if((pData == NULL ) || (Size == 0)) 
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Check the parameters */
+    assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+    /* Process Locked */
+    __HAL_LOCK(hspi);
+
+    /* Configure communication */
+    hspi->State = HAL_SPI_STATE_BUSY_TX;
+    hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+
+    hspi->pTxBuffPtr = pData;
+    hspi->TxXferSize = Size;
+    hspi->TxXferCount = Size;
+
+    /*Init field not used in handle to zero */
+    hspi->TxISR = 0;
+    hspi->RxISR = 0;
+    hspi->RxXferSize   = 0;
+    hspi->RxXferCount  = 0;
+
+    /* Reset CRC Calculation */
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+    {
+      __HAL_SPI_RESET_CRC(hspi);
+    }
+
+    if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+    {
+      /* Configure communication direction : 1Line */
+      __HAL_SPI_1LINE_TX(hspi);
+    }
+
+    /* Check if the SPI is already enabled */ 
+    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+    {
+      /* Enable SPI peripheral */
+      __HAL_SPI_ENABLE(hspi);
+    }
+
+    /* Transmit data in 8 Bit mode */
+    if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+    {
+
+      hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+      hspi->TxXferCount--;
+
+      while(hspi->TxXferCount > 0)
+      {
+        /* Wait until TXE flag is set to send data */
+        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        { 
+          return HAL_TIMEOUT;
+        }
+        hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+        hspi->TxXferCount--;
+      }
+      /* Enable CRC Transmission */
+      if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) 
+      {
+        hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+      }
+    }
+    /* Transmit data in 16 Bit mode */
+    else
+    {
+      hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+      hspi->pTxBuffPtr+=2;
+      hspi->TxXferCount--;
+
+      while(hspi->TxXferCount > 0)
+      {
+        /* Wait until TXE flag is set to send data */
+        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        { 
+          return HAL_TIMEOUT;
+        }
+        hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+        hspi->pTxBuffPtr+=2;
+        hspi->TxXferCount--;
+      }
+      /* Enable CRC Transmission */
+      if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) 
+      {
+        hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+      }
+    }
+
+    /* Wait until TXE flag is set to send data */
+    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
+    {
+      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+      return HAL_TIMEOUT;
+    }
+
+    /* Wait until Busy flag is reset before disabling SPI */
+    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
+    { 
+      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+      return HAL_TIMEOUT;
+    }
+ 
+    /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
+    if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+    {
+      __HAL_SPI_CLEAR_OVRFLAG(hspi);
+    }
+
+    hspi->State = HAL_SPI_STATE_READY; 
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspi);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in blocking mode 
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size: amount of data to be sent
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  __IO uint16_t tmpreg;
+  uint32_t tmp = 0;
+
+  if(hspi->State == HAL_SPI_STATE_READY)
+  {
+    if((pData == NULL ) || (Size == 0)) 
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hspi);
+
+    /* Configure communication */
+    hspi->State       = HAL_SPI_STATE_BUSY_RX;
+    hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+
+    hspi->pRxBuffPtr  = pData;
+    hspi->RxXferSize  = Size;
+    hspi->RxXferCount = Size;
+
+    /*Init field not used in handle to zero */
+    hspi->RxISR = 0;
+    hspi->TxISR = 0;
+    hspi->TxXferSize   = 0;
+    hspi->TxXferCount  = 0;
+
+    /* Configure communication direction : 1Line */
+    if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+    {
+      __HAL_SPI_1LINE_RX(hspi);
+    }
+
+    /* Reset CRC Calculation */
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+    {
+      __HAL_SPI_RESET_CRC(hspi);
+    }
+    
+    if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hspi);
+
+      /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+      return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
+    }
+
+    /* Check if the SPI is already enabled */ 
+    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+    {
+      /* Enable SPI peripheral */
+      __HAL_SPI_ENABLE(hspi);
+    }
+
+    /* Receive data in 8 Bit mode */
+    if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+    {
+      while(hspi->RxXferCount > 1)
+      {
+        /* Wait until RXNE flag is set */
+        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        { 
+          return HAL_TIMEOUT;
+        }
+
+        (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
+        hspi->RxXferCount--;
+      }
+      /* Enable CRC Transmission */
+      if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) 
+      {
+        hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+      }
+    }
+    /* Receive data in 16 Bit mode */
+    else
+    {
+      while(hspi->RxXferCount > 1)
+      {
+        /* Wait until RXNE flag is set to read data */
+        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        { 
+          return HAL_TIMEOUT;
+        }
+
+        *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+        hspi->pRxBuffPtr+=2;
+        hspi->RxXferCount--;
+      }
+      /* Enable CRC Transmission */
+      if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) 
+      {
+        hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+      }
+    }
+
+    /* Wait until RXNE flag is set */
+    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+    { 
+      return HAL_TIMEOUT;
+    }
+
+    /* Receive last data in 8 Bit mode */
+    if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+    {
+      (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
+    }
+    /* Receive last data in 16 Bit mode */
+    else
+    {
+      *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+      hspi->pRxBuffPtr+=2;
+    }
+    hspi->RxXferCount--;
+
+    /* Wait until RXNE flag is set: CRC Received */
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+    {
+      if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+      {
+        hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
+        return HAL_TIMEOUT;
+      }
+
+      /* Read CRC to Flush RXNE flag */
+      tmpreg = hspi->Instance->DR;
+    }
+    
+    if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+    {
+      /* Disable SPI peripheral */
+      __HAL_SPI_DISABLE(hspi);
+    }
+
+    hspi->State = HAL_SPI_STATE_READY;
+
+    tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
+    /* Check if CRC error occurred */
+    if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
+    {  
+      hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
+
+      /* Reset CRC Calculation */
+      __HAL_SPI_RESET_CRC(hspi);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hspi);
+
+      return HAL_ERROR; 
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspi);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit and Receive an amount of data in blocking mode 
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @param  pTxData: pointer to transmission data buffer
+  * @param  pRxData: pointer to reception data buffer to be
+  * @param  Size: amount of data to be sent
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+  __IO uint16_t tmpreg;
+  uint32_t tmp = 0;
+  
+  tmp = hspi->State; 
+  if((tmp == HAL_SPI_STATE_READY) || (tmp == HAL_SPI_STATE_BUSY_RX))
+  {
+    if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Check the parameters */
+    assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+    /* Process Locked */
+    __HAL_LOCK(hspi);
+ 
+    /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+    if(hspi->State == HAL_SPI_STATE_READY)
+    {
+      hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+    }
+
+     /* Configure communication */   
+    hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+
+    hspi->pRxBuffPtr  = pRxData;
+    hspi->RxXferSize  = Size;
+    hspi->RxXferCount = Size;  
+    
+    hspi->pTxBuffPtr  = pTxData;
+    hspi->TxXferSize  = Size; 
+    hspi->TxXferCount = Size;
+
+    /*Init field not used in handle to zero */
+    hspi->RxISR = 0;
+    hspi->TxISR = 0;
+
+    /* Reset CRC Calculation */
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+    {
+      __HAL_SPI_RESET_CRC(hspi);
+    }
+
+    /* Check if the SPI is already enabled */ 
+    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+    {
+      /* Enable SPI peripheral */
+      __HAL_SPI_ENABLE(hspi);
+    }
+
+    /* Transmit and Receive data in 16 Bit mode */
+    if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+    {
+      hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+      hspi->pTxBuffPtr+=2;
+      hspi->TxXferCount--;
+
+      if(hspi->TxXferCount == 0)
+      {
+        /* Enable CRC Transmission */
+        if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+        {
+          hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+        }
+
+        /* Wait until RXNE flag is set */
+        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        { 
+          return HAL_TIMEOUT;
+        }
+
+        *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+        hspi->pRxBuffPtr+=2;
+        hspi->RxXferCount--;
+      }
+      else
+      {
+        while(hspi->TxXferCount > 0)
+        {
+          /* Wait until TXE flag is set to send data */
+          if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
+          { 
+            return HAL_TIMEOUT;
+          }
+
+          hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+          hspi->pTxBuffPtr+=2;
+          hspi->TxXferCount--;
+
+          /* Enable CRC Transmission */
+          if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
+          {
+            hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+          }
+
+          /* Wait until RXNE flag is set */
+          if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+          { 
+            return HAL_TIMEOUT;
+          }
+
+          *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+          hspi->pRxBuffPtr+=2;
+          hspi->RxXferCount--;
+        }
+
+        /* Wait until RXNE flag is set */
+        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+
+        *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+        hspi->pRxBuffPtr+=2;
+        hspi->RxXferCount--;
+      }
+    }
+    /* Transmit and Receive data in 8 Bit mode */
+    else
+    {
+
+      hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+      hspi->TxXferCount--;
+
+      if(hspi->TxXferCount == 0)
+      {
+        /* Enable CRC Transmission */
+        if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+        {
+          hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+        }
+
+        /* Wait until RXNE flag is set */
+        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+
+        (*hspi->pRxBuffPtr) = hspi->Instance->DR;
+        hspi->RxXferCount--;
+      }
+      else
+      {
+        while(hspi->TxXferCount > 0)
+        {
+          /* Wait until TXE flag is set to send data */
+          if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
+          {
+            return HAL_TIMEOUT;
+          }
+
+          hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+          hspi->TxXferCount--;
+
+          /* Enable CRC Transmission */
+          if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
+          {
+            hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+          }
+
+          /* Wait until RXNE flag is set */
+          if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+          {
+            return HAL_TIMEOUT;
+          }
+
+          (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
+          hspi->RxXferCount--;
+        }
+
+        /* Wait until RXNE flag is set */
+        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+
+        (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
+        hspi->RxXferCount--;
+      }
+    }
+
+    /* Read CRC from DR to close CRC calculation process */
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+    {
+      /* Wait until RXNE flag is set */
+      if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+      {
+        hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
+        return HAL_TIMEOUT;
+      }
+      /* Read CRC */
+      tmpreg = hspi->Instance->DR;
+    }
+
+    /* Wait until Busy flag is reset before disabling SPI */
+    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
+    {
+      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+      return HAL_TIMEOUT;
+    }
+    
+    hspi->State = HAL_SPI_STATE_READY;
+
+    tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
+    /* Check if CRC error occurred */
+    if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
+    {
+      hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
+
+      /* Reset CRC Calculation */
+      if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+      {
+        __HAL_SPI_RESET_CRC(hspi);
+      }
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hspi);
+      
+      return HAL_ERROR; 
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspi);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit an amount of data in no-blocking mode with Interrupt
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+  if(hspi->State == HAL_SPI_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Check the parameters */
+    assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+    /* Process Locked */
+    __HAL_LOCK(hspi);
+
+    /* Configure communication */
+    hspi->State        = HAL_SPI_STATE_BUSY_TX;
+    hspi->ErrorCode    = HAL_SPI_ERROR_NONE;
+
+    hspi->TxISR = &SPI_TxISR;
+    hspi->pTxBuffPtr   = pData;
+    hspi->TxXferSize   = Size;
+    hspi->TxXferCount  = Size;
+
+    /*Init field not used in handle to zero */
+    hspi->RxISR = 0;
+    hspi->RxXferSize   = 0;
+    hspi->RxXferCount  = 0;
+
+    /* Configure communication direction : 1Line */
+    if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+    {
+      __HAL_SPI_1LINE_TX(hspi);
+    }
+
+    /* Reset CRC Calculation */
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+    {
+      __HAL_SPI_RESET_CRC(hspi);
+    }
+
+    if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
+    {
+      __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
+    }else
+    {
+      /* Enable TXE and ERR interrupt */
+      __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+    }
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspi);
+
+    /* Check if the SPI is already enabled */ 
+    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+    {
+      /* Enable SPI peripheral */
+      __HAL_SPI_ENABLE(hspi);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in no-blocking mode with Interrupt
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+  if(hspi->State == HAL_SPI_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0)) 
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hspi);
+
+    /* Configure communication */
+    hspi->State        = HAL_SPI_STATE_BUSY_RX;
+    hspi->ErrorCode    = HAL_SPI_ERROR_NONE;
+
+    hspi->RxISR = &SPI_RxISR;
+    hspi->pRxBuffPtr   = pData;
+    hspi->RxXferSize   = Size;
+    hspi->RxXferCount  = Size ; 
+
+   /*Init field not used in handle to zero */
+    hspi->TxISR = 0;
+    hspi->TxXferSize   = 0;
+    hspi->TxXferCount  = 0;
+
+    /* Configure communication direction : 1Line */
+    if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+    {
+       __HAL_SPI_1LINE_RX(hspi);
+    }
+    else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+    {
+       /* Process Unlocked */
+       __HAL_UNLOCK(hspi);
+
+       /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+       return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
+    }
+
+    /* Reset CRC Calculation */
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+    {
+      __HAL_SPI_RESET_CRC(hspi);
+    }
+
+    /* Enable TXE and ERR interrupt */
+    __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspi);
+
+    /* Note : The SPI must be enabled after unlocking current process 
+              to avoid the risk of SPI interrupt handle execution before current
+              process unlock */
+
+        /* Check if the SPI is already enabled */ 
+    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+    {
+      /* Enable SPI peripheral */
+      __HAL_SPI_ENABLE(hspi);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY; 
+  }
+}
+
+/**
+  * @brief  Transmit and Receive an amount of data in no-blocking mode with Interrupt 
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @param  pTxData: pointer to transmission data buffer
+  * @param  pRxData: pointer to reception data buffer to be
+  * @param  Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ uint32_t tmp = 0;
+
+ tmp = hspi->State;
+ if((tmp == HAL_SPI_STATE_READY) || (tmp == HAL_SPI_STATE_BUSY_RX))
+  {
+    if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) 
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Check the parameters */
+    assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+    /* Process locked */
+    __HAL_LOCK(hspi);
+
+    /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+    if(hspi->State == HAL_SPI_STATE_READY)
+    {
+      hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+    }
+
+    /* Configure communication */
+    hspi->ErrorCode    = HAL_SPI_ERROR_NONE;
+
+    hspi->TxISR = &SPI_TxISR;
+    hspi->pTxBuffPtr   = pTxData;
+    hspi->TxXferSize   = Size;
+    hspi->TxXferCount  = Size;
+
+    hspi->RxISR = &SPI_2LinesRxISR;
+    hspi->pRxBuffPtr   = pRxData;
+    hspi->RxXferSize   = Size;
+    hspi->RxXferCount  = Size;
+
+    /* Reset CRC Calculation */
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+    {
+      __HAL_SPI_RESET_CRC(hspi);
+    }
+
+    /* Enable TXE, RXNE and ERR interrupt */
+    __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspi);
+
+    /* Check if the SPI is already enabled */ 
+    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+    {
+      /* Enable SPI peripheral */
+      __HAL_SPI_ENABLE(hspi);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY; 
+  }
+}
+
+/**
+  * @brief  Transmit an amount of data in no-blocking mode with DMA
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+  if(hspi->State == HAL_SPI_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Check the parameters */
+    assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+    /* Process Locked */
+    __HAL_LOCK(hspi);
+
+    /* Configure communication */
+    hspi->State       = HAL_SPI_STATE_BUSY_TX;
+    hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+
+    hspi->pTxBuffPtr  = pData;
+    hspi->TxXferSize  = Size;
+    hspi->TxXferCount = Size;
+
+    /*Init field not used in handle to zero */
+    hspi->TxISR = 0;
+    hspi->RxISR = 0;
+    hspi->RxXferSize   = 0;
+    hspi->RxXferCount  = 0;
+
+    /* Configure communication direction : 1Line */
+    if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+    {
+      __HAL_SPI_1LINE_TX(hspi);
+    }
+
+    /* Reset CRC Calculation */
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+    {
+      __HAL_SPI_RESET_CRC(hspi);
+    }
+
+    /* Set the SPI TxDMA transfer complete callback */
+    hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
+
+    /* Set the DMA error callback */
+    hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+
+    /* Enable the Tx DMA Stream */
+    HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+    /* Enable Tx DMA Request */
+    hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspi);
+
+    /* Check if the SPI is already enabled */ 
+    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+    {
+      /* Enable SPI peripheral */
+      __HAL_SPI_ENABLE(hspi);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in no-blocking mode with DMA 
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @note  When the CRC feature is enabled the pData Length must be Size + 1. 
+  * @param  Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+  if(hspi->State == HAL_SPI_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hspi);
+
+    /* Configure communication */
+    hspi->State       = HAL_SPI_STATE_BUSY_RX;
+    hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+
+    hspi->pRxBuffPtr  = pData;
+    hspi->RxXferSize  = Size;
+    hspi->RxXferCount = Size;
+
+    /*Init field not used in handle to zero */
+    hspi->RxISR = 0;
+    hspi->TxISR = 0;
+    hspi->TxXferSize   = 0;
+    hspi->TxXferCount  = 0;
+
+    /* Configure communication direction : 1Line */
+    if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+    {
+       __HAL_SPI_1LINE_RX(hspi);
+    }
+    else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
+    {
+       /* Process Unlocked */
+       __HAL_UNLOCK(hspi);
+
+       /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+       return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
+    }
+
+    /* Reset CRC Calculation */
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+    {
+      __HAL_SPI_RESET_CRC(hspi);
+    }
+
+    /* Set the SPI Rx DMA transfer complete callback */
+    hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+
+    /* Set the DMA error callback */
+    hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+    /* Enable the Rx DMA Stream */
+    HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+
+    /* Enable Rx DMA Request */  
+    hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;  
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspi);
+
+    /* Check if the SPI is already enabled */ 
+    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+    {
+      /* Enable SPI peripheral */
+      __HAL_SPI_ENABLE(hspi);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit and Receive an amount of data in no-blocking mode with DMA 
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @param  pTxData: pointer to transmission data buffer
+  * @param  pRxData: pointer to reception data buffer
+  * @note  When the CRC feature is enabled the pRxData Length must be Size + 1 
+  * @param  Size: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+  uint32_t tmpstate = 0;
+  tmpstate = hspi->State;
+  if((tmpstate == HAL_SPI_STATE_READY) || (tmpstate == HAL_SPI_STATE_BUSY_RX))
+  {
+    if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Check the parameters */
+    assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+    
+    /* Process locked */
+    __HAL_LOCK(hspi);
+
+    /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+    if(hspi->State == HAL_SPI_STATE_READY)
+    {
+      hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+    }
+
+    /* Configure communication */
+    hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+
+    hspi->pTxBuffPtr  = (uint8_t*)pTxData;
+    hspi->TxXferSize  = Size;
+    hspi->TxXferCount = Size;
+
+    hspi->pRxBuffPtr  = (uint8_t*)pRxData;
+    hspi->RxXferSize  = Size;
+    hspi->RxXferCount = Size;
+
+    /*Init field not used in handle to zero */
+    hspi->RxISR = 0;
+    hspi->TxISR = 0;
+
+    /* Reset CRC Calculation */
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+    {
+      __HAL_SPI_RESET_CRC(hspi);
+    }
+
+    /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
+    if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+    {
+      hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+    }
+    else
+    {
+      hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
+    }
+
+    /* Set the DMA error callback */
+    hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+    /* Enable the Rx DMA Stream */
+    HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+
+    /* Enable Rx DMA Request */  
+    hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
+
+    /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
+    is performed in DMA reception complete callback  */
+    hspi->hdmatx->XferCpltCallback = NULL;
+
+    /* Set the DMA error callback */
+    hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+
+    /* Enable the Tx DMA Stream */
+    HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+    /* Enable Tx DMA Request */  
+    hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspi);
+
+        /* Check if the SPI is already enabled */ 
+    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+    {
+      /* Enable SPI peripheral */
+      __HAL_SPI_ENABLE(hspi);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  This function handles SPI interrupt request.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @retval HAL status
+  */
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
+{
+  uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
+
+  tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE);
+  tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE);
+  tmp3 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR);
+  /* SPI in mode Receiver and Overrun not occurred ---------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET) && (tmp3 == RESET))
+  {
+    hspi->RxISR(hspi);
+    return;
+  } 
+
+  tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE);
+  tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE);
+  /* SPI in mode Tramitter ---------------------------------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET))
+  {
+    hspi->TxISR(hspi);
+    return;
+  }
+
+  if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
+  {
+    /* SPI CRC error interrupt occurred ---------------------------------------*/
+    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+    {
+      hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
+      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+    }
+    /* SPI Mode Fault error interrupt occurred --------------------------------*/
+    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
+    {
+      hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
+      __HAL_SPI_CLEAR_MODFFLAG(hspi);
+    }
+    
+    /* SPI Overrun error interrupt occurred -----------------------------------*/
+    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
+    {
+      if(hspi->State != HAL_SPI_STATE_BUSY_TX)
+      {
+        hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
+        __HAL_SPI_CLEAR_OVRFLAG(hspi);      
+      }
+    }
+
+    /* SPI Frame error interrupt occurred -------------------------------------*/
+    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
+    {
+      hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
+      __HAL_SPI_CLEAR_FREFLAG(hspi);
+    }
+
+    /* Call the Error call Back in case of Errors */
+    if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
+    {
+      hspi->State = HAL_SPI_STATE_READY;
+      HAL_SPI_ErrorCallback(hspi);
+    }
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callbacks
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SPI_TxCpltCallback could be implenetd in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callbacks
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SPI_RxCpltCallback() could be implenetd in the user file
+   */
+}
+
+/**
+  * @brief Tx and Rx Transfer completed callbacks
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
+   */
+}
+
+/**
+  * @brief SPI error callbacks
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @retval None
+  */
+ __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+{
+  /* NOTE : - This function Should not be modified, when the callback is needed,
+            the HAL_SPI_ErrorCallback() could be implenetd in the user file.
+            - The ErrorCode parameter in the hspi handle is updated by the SPI processes
+            and user can use HAL_SPI_GetError() API to check the latest error occurred.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group3 Peripheral State and Errors functions 
+  *  @brief   SPI control functions 
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State and Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the SPI.
+     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
+     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the SPI state
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @retval HAL state
+  */
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
+{
+  return hspi->State;
+}
+
+/**
+  * @brief  Return the SPI error code
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @retval SPI Error Code
+  */
+HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+{
+  return hspi->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+  /**
+  * @brief  Interrupt Handler to close Tx transfer 
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @retval void
+  */
+static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
+{
+  /* Wait until TXE flag is set to send data */
+  if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+  {
+    hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+  }
+
+  /* Disable TXE interrupt */
+  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE ));
+
+  /* Disable ERR interrupt if Receive process is finished */
+  if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
+  {
+    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
+
+    /* Wait until Busy flag is reset before disabling SPI */
+    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+    {
+      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+    }
+
+    /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
+    if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+    {
+      __HAL_SPI_CLEAR_OVRFLAG(hspi);
+    }
+    
+    /* Check if Errors has been detected during transfer */
+    if(hspi->ErrorCode ==  HAL_SPI_ERROR_NONE)
+    {
+      /* Check if we are in Tx or in Rx/Tx Mode */
+      if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
+      {
+        /* Set state to READY before run the Callback Complete */
+        hspi->State = HAL_SPI_STATE_READY;
+        HAL_SPI_TxRxCpltCallback(hspi);
+      }
+      else
+      {
+        /* Set state to READY before run the Callback Complete */
+        hspi->State = HAL_SPI_STATE_READY;
+        HAL_SPI_TxCpltCallback(hspi);
+      }
+    }
+    else
+    {
+      /* Set state to READY before run the Callback Complete */
+      hspi->State = HAL_SPI_STATE_READY;
+      /* Call Error call back in case of Error */
+      HAL_SPI_ErrorCallback(hspi);
+    }
+  }
+}
+
+/**
+  * @brief  Interrupt Handler to transmit amount of data in no-blocking mode 
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @retval void
+  */
+static void SPI_TxISR(SPI_HandleTypeDef *hspi)
+{
+  /* Transmit data in 8 Bit mode */
+  if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+  {
+    hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+  }
+  /* Transmit data in 16 Bit mode */
+  else
+  {
+    hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+    hspi->pTxBuffPtr+=2;
+  }
+  hspi->TxXferCount--;
+
+  if(hspi->TxXferCount == 0)
+  {
+    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+    {
+      /* calculate and transfer CRC on Tx line */
+      hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+    }
+    SPI_TxCloseIRQHandler(hspi);
+  }
+}
+
+/**
+  * @brief  Interrupt Handler to close Rx transfer 
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @retval void
+  */
+static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
+{
+  __IO uint16_t tmpreg;
+
+  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+  {
+    /* Wait until RXNE flag is set to send data */
+    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+    {
+      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+    }
+
+    /* Read CRC to reset RXNE flag */
+    tmpreg = hspi->Instance->DR;
+
+    /* Wait until RXNE flag is set to send data */
+    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+    {
+      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+    }
+
+    /* Check if CRC error occurred */
+    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+    {
+      hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
+
+      /* Reset CRC Calculation */
+      __HAL_SPI_RESET_CRC(hspi);
+    }
+  }
+
+  /* Disable RXNE and ERR interrupt */
+  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
+
+  /* if Transmit process is finished */
+  if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
+  {
+    /* Disable ERR interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
+
+    if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+    {
+      /* Disable SPI peripheral */
+      __HAL_SPI_DISABLE(hspi);
+    }
+    
+    /* Check if Errors has been detected during transfer */
+    if(hspi->ErrorCode ==  HAL_SPI_ERROR_NONE)
+    {
+      /* Check if we are in Rx or in Rx/Tx Mode */
+      if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
+      {
+        /* Set state to READY before run the Callback Complete */
+        hspi->State = HAL_SPI_STATE_READY;
+        HAL_SPI_TxRxCpltCallback(hspi);
+      }else
+      {
+        /* Set state to READY before run the Callback Complete */
+        hspi->State = HAL_SPI_STATE_READY;
+        HAL_SPI_RxCpltCallback(hspi);
+      }
+    }
+    else
+    {
+      /* Set state to READY before run the Callback Complete */
+      hspi->State = HAL_SPI_STATE_READY;
+      /* Call Error call back in case of Error */
+      HAL_SPI_ErrorCallback(hspi);
+    }
+  }
+}
+
+/**
+  * @brief  Interrupt Handler to receive amount of data in 2Lines mode 
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @retval void
+  */
+static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
+{
+  /* Receive data in 8 Bit mode */
+  if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+  {
+    (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
+  }
+  /* Receive data in 16 Bit mode */
+  else
+  {
+    *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+    hspi->pRxBuffPtr+=2;
+  }
+  hspi->RxXferCount--;
+
+  if(hspi->RxXferCount==0)
+  {
+    SPI_RxCloseIRQHandler(hspi);
+  }
+}
+
+/**
+  * @brief  Interrupt Handler to receive amount of data in no-blocking mode 
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @retval void
+  */
+static void SPI_RxISR(SPI_HandleTypeDef *hspi)
+{
+  /* Receive data in 8 Bit mode */
+  if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+  {
+    (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
+  }
+  /* Receive data in 16 Bit mode */
+  else
+  {
+    *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+    hspi->pRxBuffPtr+=2;
+  }
+    hspi->RxXferCount--;
+
+  /* Enable CRC Transmission */
+  if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
+  {
+    /* Set CRC Next to calculate CRC on Rx side */
+    hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;  
+  }
+
+  if(hspi->RxXferCount == 0)
+  {
+    SPI_RxCloseIRQHandler(hspi);
+  }
+}
+
+/**
+  * @brief DMA SPI transmit process complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  /* Wait until TXE flag is set to send data */
+  if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+  {
+    hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+  }
+
+  /* Disable Tx DMA Request */
+  hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+
+  /* Wait until Busy flag is reset before disabling SPI */
+  if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+  {
+    hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+  }
+
+  hspi->TxXferCount = 0;
+
+  hspi->State = HAL_SPI_STATE_READY;
+
+  /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
+  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+  {
+    __HAL_SPI_CLEAR_OVRFLAG(hspi);
+  }
+
+  /* Check if Errors has been detected during transfer */
+  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+  {
+    HAL_SPI_ErrorCallback(hspi);
+  }
+  else
+  {
+    HAL_SPI_TxCpltCallback(hspi);
+  }
+}
+
+/**
+  * @brief DMA SPI receive process complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  __IO uint16_t tmpreg;
+
+  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+  {
+    /* Disable SPI peripheral */
+    __HAL_SPI_DISABLE(hspi);
+  }
+
+  /* Disable Rx DMA Request */
+  hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+
+  /* Reset CRC Calculation */
+  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+  {
+    /* Wait until RXNE flag is set to send data */
+    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+    {
+      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+    }
+
+    /* Read CRC */
+    tmpreg = hspi->Instance->DR;
+
+    /* Wait until RXNE flag is set to send data */
+    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+    {
+      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+    }
+  }
+
+  hspi->RxXferCount = 0;
+  hspi->State = HAL_SPI_STATE_READY;
+
+  /* Check if CRC error occurred */
+  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+  {
+    hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
+    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+  }
+
+  /* Check if Errors has been detected during transfer */
+  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+  {
+    HAL_SPI_ErrorCallback(hspi);
+  }
+  else
+  {
+    HAL_SPI_RxCpltCallback(hspi);
+  }
+}
+
+/**
+  * @brief DMA SPI transmit receive process complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)   
+{
+  __IO uint16_t tmpreg;
+
+  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  /* Reset CRC Calculation */
+  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+  {
+    /* Check if CRC is done on going (RXNE flag set) */
+    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
+    {
+      /* Wait until RXNE flag is set to send data */
+      if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+      {
+        hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+      }
+    }
+    /* Read CRC */
+    tmpreg = hspi->Instance->DR;
+  }
+
+  /* Wait until TXE flag is set to send data */
+  if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+  {
+    hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+  }
+  /* Disable Tx DMA Request */
+  hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+
+  /* Wait until Busy flag is reset before disabling SPI */
+  if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+  {
+    hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+  }
+
+  /* Disable Rx DMA Request */
+  hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+
+  hspi->TxXferCount = 0;
+  hspi->RxXferCount = 0;
+
+  hspi->State = HAL_SPI_STATE_READY;
+
+  /* Check if CRC error occurred */
+  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+  {
+    hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
+    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+  }
+
+  /* Check if Errors has been detected during transfer */
+  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+  {
+    HAL_SPI_ErrorCallback(hspi);
+  }
+  else
+  {
+    HAL_SPI_TxRxCpltCallback(hspi);
+  }
+}
+
+/**
+  * @brief DMA SPI communication error callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  hspi->TxXferCount = 0;
+  hspi->RxXferCount = 0;
+  hspi->State= HAL_SPI_STATE_READY;
+  hspi->ErrorCode |= HAL_SPI_ERROR_DMA;
+  HAL_SPI_ErrorCallback(hspi);
+}
+
+/**
+  * @brief This function handles SPI Communication Timeout.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)  
+{
+  uint32_t timeout = 0;
+
+  timeout = HAL_GetTick() + Timeout;
+
+  /* Wait until flag is set */
+  if(Status == RESET)
+  {
+    while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
+    {
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Disable the SPI and reset the CRC: the CRC value should be cleared
+             on both master and slave sides in order to resynchronize the master
+             and slave for their respective CRC calculation */
+
+          /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+          __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+          /* Disable SPI peripheral */
+          __HAL_SPI_DISABLE(hspi);
+
+          /* Reset CRC Calculation */
+          if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+          {
+            __HAL_SPI_RESET_CRC(hspi);
+          }
+
+          hspi->State= HAL_SPI_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hspi);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  else
+  {
+    while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
+    {
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Disable the SPI and reset the CRC: the CRC value should be cleared
+             on both master and slave sides in order to resynchronize the master
+             and slave for their respective CRC calculation */
+
+          /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+          __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+          /* Disable SPI peripheral */
+          __HAL_SPI_DISABLE(hspi);
+
+          /* Reset CRC Calculation */
+          if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+          {
+            __HAL_SPI_RESET_CRC(hspi);
+          }
+
+          hspi->State= HAL_SPI_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hspi);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,482 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_spi.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of SPI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SPI_H
+#define __STM32F4xx_HAL_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"  
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SPI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  SPI Configuration Structure definition  
+  */
+typedef struct
+{
+  uint32_t Mode;               /*!< Specifies the SPI operating mode.
+                                    This parameter can be a value of @ref SPI_mode */
+
+  uint32_t Direction;          /*!< Specifies the SPI Directional mode state.
+                                    This parameter can be a value of @ref SPI_Direction_mode */
+
+  uint32_t DataSize;           /*!< Specifies the SPI data size.
+                                    This parameter can be a value of @ref SPI_data_size */
+
+  uint32_t CLKPolarity;        /*!< Specifies the serial clock steady state.
+                                    This parameter can be a value of @ref SPI_Clock_Polarity */
+
+  uint32_t CLKPhase;           /*!< Specifies the clock active edge for the bit capture.
+                                    This parameter can be a value of @ref SPI_Clock_Phase */
+
+  uint32_t NSS;                /*!< Specifies whether the NSS signal is managed by
+                                    hardware (NSS pin) or by software using the SSI bit.
+                                    This parameter can be a value of @ref SPI_Slave_Select_management */
+
+  uint32_t BaudRatePrescaler;  /*!< Specifies the Baud Rate prescaler value which will be
+                                    used to configure the transmit and receive SCK clock.
+                                    This parameter can be a value of @ref SPI_BaudRate_Prescaler
+                                    @note The communication clock is derived from the master
+                                    clock. The slave clock does not need to be set */
+
+  uint32_t FirstBit;           /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                    This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+  uint32_t TIMode;             /*!< Specifies if the TI mode is enabled or not.
+                                    This parameter can be a value of @ref SPI_TI_mode */
+
+  uint32_t CRCCalculation;     /*!< Specifies if the CRC calculation is enabled or not.
+                                    This parameter can be a value of @ref SPI_CRC_Calculation */
+
+  uint32_t CRCPolynomial;      /*!< Specifies the polynomial used for the CRC calculation.
+                                    This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
+
+}SPI_InitTypeDef;
+
+/**
+  * @brief  HAL SPI State structure definition
+  */
+typedef enum
+{
+  HAL_SPI_STATE_RESET      = 0x00,  /*!< SPI not yet initialized or disabled                */
+  HAL_SPI_STATE_READY      = 0x01,  /*!< SPI initialized and ready for use                  */
+  HAL_SPI_STATE_BUSY       = 0x02,  /*!< SPI process is ongoing                             */
+  HAL_SPI_STATE_BUSY_TX    = 0x12,  /*!< Data Transmission process is ongoing               */
+  HAL_SPI_STATE_BUSY_RX    = 0x22,  /*!< Data Reception process is ongoing                  */
+  HAL_SPI_STATE_BUSY_TX_RX = 0x32,  /*!< Data Transmission and Reception process is ongoing */
+  HAL_SPI_STATE_ERROR      = 0x03   /*!< SPI error state                                    */
+    
+}HAL_SPI_StateTypeDef;
+
+/** 
+  * @brief  HAL SPI Error Code structure definition  
+  */ 
+typedef enum
+{
+  HAL_SPI_ERROR_NONE      = 0x00,    /*!< No error             */
+  HAL_SPI_ERROR_MODF      = 0x01,    /*!< MODF error           */
+  HAL_SPI_ERROR_CRC       = 0x02,    /*!< CRC error            */
+  HAL_SPI_ERROR_OVR       = 0x04,    /*!< OVR error            */
+  HAL_SPI_ERROR_FRE       = 0x08,    /*!< FRE error            */
+  HAL_SPI_ERROR_DMA       = 0x10,    /*!< DMA transfer error   */
+  HAL_SPI_ERROR_FLAG      = 0x20     /*!< Flag: RXNE,TXE, BSY  */
+
+}HAL_SPI_ErrorTypeDef;
+
+/** 
+  * @brief  SPI handle Structure definition
+  */
+typedef struct __SPI_HandleTypeDef
+{
+  SPI_TypeDef                *Instance;    /* SPI registers base address */
+
+  SPI_InitTypeDef            Init;         /* SPI communication parameters */
+
+  uint8_t                    *pTxBuffPtr;  /* Pointer to SPI Tx transfer Buffer */
+
+  uint16_t                   TxXferSize;   /* SPI Tx transfer size */
+  
+  uint16_t                   TxXferCount;  /* SPI Tx Transfer Counter */
+
+  uint8_t                    *pRxBuffPtr;  /* Pointer to SPI Rx transfer Buffer */
+
+  uint16_t                   RxXferSize;   /* SPI Rx transfer size */
+
+  uint16_t                   RxXferCount;  /* SPI Rx Transfer Counter */
+
+  DMA_HandleTypeDef          *hdmatx;      /* SPI Tx DMA handle parameters */
+
+  DMA_HandleTypeDef          *hdmarx;      /* SPI Rx DMA handle parameters */
+
+  void                       (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
+
+  void                       (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
+
+  HAL_LockTypeDef            Lock;         /* SPI locking object */
+
+  __IO HAL_SPI_StateTypeDef  State;        /* SPI communication state */
+
+  __IO HAL_SPI_ErrorTypeDef  ErrorCode;         /* SPI Error code */
+
+}SPI_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants
+  * @{
+  */
+
+/** @defgroup SPI_mode 
+  * @{
+  */
+#define SPI_MODE_SLAVE                  ((uint32_t)0x00000000)
+#define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
+
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
+                           ((MODE) == SPI_MODE_MASTER))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Direction_mode 
+  * @{
+  */
+#define SPI_DIRECTION_2LINES             ((uint32_t)0x00000000)
+#define SPI_DIRECTION_2LINES_RXONLY      SPI_CR1_RXONLY
+#define SPI_DIRECTION_1LINE              SPI_CR1_BIDIMODE
+
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES)        || \
+                                     ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
+                                     ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)  || \
+                                                ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_data_size 
+  * @{
+  */
+#define SPI_DATASIZE_8BIT               ((uint32_t)0x00000000)
+#define SPI_DATASIZE_16BIT              SPI_CR1_DFF
+
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_8BIT))
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_Clock_Polarity 
+  * @{
+  */
+#define SPI_POLARITY_LOW                ((uint32_t)0x00000000)
+#define SPI_POLARITY_HIGH               SPI_CR1_CPOL
+
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
+                           ((CPOL) == SPI_POLARITY_HIGH))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Phase 
+  * @{
+  */
+#define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000)
+#define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
+
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
+                           ((CPHA) == SPI_PHASE_2EDGE))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Slave_Select_management 
+  * @{
+  */
+#define SPI_NSS_SOFT                    SPI_CR1_SSM
+#define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000)
+#define SPI_NSS_HARD_OUTPUT             ((uint32_t)0x00040000)
+
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \
+                         ((NSS) == SPI_NSS_HARD_INPUT) || \
+                         ((NSS) == SPI_NSS_HARD_OUTPUT))
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_BaudRate_Prescaler 
+  * @{
+  */
+#define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000)
+#define SPI_BAUDRATEPRESCALER_4         ((uint32_t)0x00000008)
+#define SPI_BAUDRATEPRESCALER_8         ((uint32_t)0x00000010)
+#define SPI_BAUDRATEPRESCALER_16        ((uint32_t)0x00000018)
+#define SPI_BAUDRATEPRESCALER_32        ((uint32_t)0x00000020)
+#define SPI_BAUDRATEPRESCALER_64        ((uint32_t)0x00000028)
+#define SPI_BAUDRATEPRESCALER_128       ((uint32_t)0x00000030)
+#define SPI_BAUDRATEPRESCALER_256       ((uint32_t)0x00000038)
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_MSB_LSB_transmission 
+  * @{
+  */
+#define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000)
+#define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
+
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
+                               ((BIT) == SPI_FIRSTBIT_LSB))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_TI_mode 
+  * @{
+  */
+#define SPI_TIMODE_DISABLED             ((uint32_t)0x00000000)
+#define SPI_TIMODE_ENABLED              SPI_CR2_FRF
+
+#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \
+                             ((MODE) == SPI_TIMODE_ENABLED))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_Calculation 
+  * @{
+  */
+#define SPI_CRCCALCULATION_DISABLED     ((uint32_t)0x00000000)
+#define SPI_CRCCALCULATION_ENABLED      SPI_CR1_CRCEN
+
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
+                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Interrupt_configuration_definition
+  * @{
+  */
+#define SPI_IT_TXE                      SPI_CR2_TXEIE
+#define SPI_IT_RXNE                     SPI_CR2_RXNEIE
+#define SPI_IT_ERR                      SPI_CR2_ERRIE
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Flag_definition 
+  * @{
+  */
+#define SPI_FLAG_RXNE                   SPI_SR_RXNE
+#define SPI_FLAG_TXE                    SPI_SR_TXE
+#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR
+#define SPI_FLAG_MODF                   SPI_SR_MODF
+#define SPI_FLAG_OVR                    SPI_SR_OVR
+#define SPI_FLAG_BSY                    SPI_SR_BSY
+#define SPI_FLAG_FRE                    SPI_SR_FRE
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset SPI handle state
+  * @param  __HANDLE__: specifies the SPI handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
+
+/** @brief  Enable or disable the specified SPI interrupts.
+  * @param  __HANDLE__: specifies the SPI handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  *         This parameter can be one of the following values:
+  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg SPI_IT_ERR: Error interrupt enable
+  * @retval None
+  */
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+
+/** @brief  Check if the specified SPI interrupt source is enabled or disabled.
+  * @param  __HANDLE__: specifies the SPI handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
+  *          This parameter can be one of the following values:
+  *             @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+  *             @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+  *             @arg SPI_IT_ERR: Error interrupt enable
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified SPI flag is set or not.
+  * @param  __HANDLE__: specifies the SPI handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
+  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
+  *            @arg SPI_FLAG_CRCERR: CRC error flag
+  *            @arg SPI_FLAG_MODF: Mode fault flag
+  *            @arg SPI_FLAG_OVR: Overrun flag
+  *            @arg SPI_FLAG_BSY: Busy flag
+  *            @arg SPI_FLAG_FRE: Frame format error flag  
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the SPI CRCERR pending flag.
+  * @param  __HANDLE__: specifies the SPI handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR &= ~(SPI_FLAG_CRCERR))
+
+/** @brief  Clear the SPI MODF pending flag.
+  * @param  __HANDLE__: specifies the SPI handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
+                                                (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);}while(0) 
+
+/** @brief  Clear the SPI OVR pending flag.
+  * @param  __HANDLE__: specifies the SPI handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
+                                               (__HANDLE__)->Instance->SR;}while(0) 
+
+/** @brief  Clear the SPI FRE pending flag.
+  * @param  __HANDLE__: specifies the SPI handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR)
+
+#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)
+#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SPI_CR1_SPE)
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
+
+#define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
+
+#define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE) 
+
+#define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\
+                                           (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+
+/* I/O operation functions  *****************************************************/
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+
+/* Peripheral State and Control functions  **************************************/
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
+HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,682 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_sram.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   SRAM HAL module driver.
+  *          This file provides a generic firmware to drive SRAM memories  
+  *          mounted as external device.
+  *         
+  @verbatim
+  ==============================================================================
+                          ##### How to use this driver #####
+  ==============================================================================  
+  [..]
+    This driver is a generic layered driver which contains a set of APIs used to 
+    control SRAM memories. It uses the FMC layer functions to interface 
+    with SRAM devices.  
+    The following sequence should be followed to configure the FMC/FSMC to interface
+    with SRAM/PSRAM memories: 
+      
+   (#) Declare a SRAM_HandleTypeDef handle structure, for example:
+          SRAM_HandleTypeDef  hsram; and: 
+          
+       (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed 
+            values of the structure member.
+            
+       (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined 
+            base register instance for NOR or SRAM device 
+                         
+       (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
+            base register instance for NOR or SRAM extended mode 
+             
+   (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended 
+       mode timings; for example:
+          FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
+      and fill its fields with the allowed values of the structure member.
+      
+   (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
+       performs the following sequence:
+          
+       (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
+       (##) Control register configuration using the FMC NORSRAM interface function 
+            FMC_NORSRAM_Init()
+       (##) Timing register configuration using the FMC NORSRAM interface function 
+            FMC_NORSRAM_Timing_Init()
+       (##) Extended mode Timing register configuration using the FMC NORSRAM interface function 
+            FMC_NORSRAM_Extended_Timing_Init()
+       (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()    
+
+   (#) At this stage you can perform read/write accesses from/to the memory connected 
+       to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
+       following APIs:
+       (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
+       (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
+       
+   (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
+       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation  
+       
+   (#) You can continuously monitor the SRAM device HAL state by calling the function
+       HAL_SRAM_GetState()              
+                             
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SRAM 
+  * @brief SRAM driver modules
+  * @{
+  */
+#ifdef HAL_SRAM_MODULE_ENABLED
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/    
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SRAM_Private_Functions
+  * @{
+  */
+
+/** @defgroup SRAM_Group1 Initialization and de-initialization functions 
+  * @brief    Initialization and Configuration functions 
+  *
+  @verbatim    
+  ==============================================================================
+           ##### SRAM Initialization and de_initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to initialize/de-initialize
+          the SRAM memory
+  
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Performs the SRAM device initialization sequence
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  Timing: Pointer to SRAM control timing structure 
+  * @param  ExtTiming: Pointer to SRAM extended mode timing structure  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
+{ 
+  /* Check the SRAM handle parameter */
+  if(hsram == NULL)
+  {
+     return HAL_ERROR;
+  }
+  
+  if(hsram->State == HAL_SRAM_STATE_RESET)
+  {  
+    /* Initialize the low level hardware (MSP) */
+    HAL_SRAM_MspInit(hsram);
+  }
+  
+  /* Initialize SRAM control Interface */
+  FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
+
+  /* Initialize SRAM timing Interface */
+  FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); 
+
+  /* Initialize SRAM extended mode timing Interface */
+  FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,  hsram->Init.ExtendedMode);  
+  
+  /* Enable the NORSRAM device */
+  __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); 
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Performs the SRAM device De-initialization sequence.
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
+{ 
+  /* De-Initialize the low level hardware (MSP) */
+  HAL_SRAM_MspDeInit(hsram);
+   
+  /* Configure the SRAM registers with their reset values */
+  FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
+
+  hsram->State = HAL_SRAM_STATE_RESET;
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hsram);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  SRAM MSP Init.
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval None
+  */
+__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SRAM_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  SRAM MSP DeInit.
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval None
+  */
+__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SRAM_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  DMA transfer complete callback.
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval None
+  */
+__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  DMA transfer complete error callback.
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval None
+  */
+__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SRAM_Group2 Input and Output functions 
+  * @brief    Input Output and memory control functions 
+  *
+  @verbatim    
+  ==============================================================================
+                  ##### SRAM Input and Output functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to use and control the SRAM memory
+  
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads 8-bit buffer from SRAM memory. 
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress: Pointer to read start address
+  * @param  pDstBuffer: Pointer to destination buffer  
+  * @param  BufferSize: Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
+{
+  __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
+  
+  /* Process Locked */
+  __HAL_LOCK(hsram);
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_BUSY;  
+  
+  /* Read data from memory */
+  for(; BufferSize != 0; BufferSize--)
+  {
+    *pDstBuffer = *(__IO uint8_t *)pSramAddress;
+    pDstBuffer++;
+    pSramAddress++;
+  }
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY;    
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram); 
+    
+  return HAL_OK;   
+}
+
+/**
+  * @brief  Writes 8-bit buffer to SRAM memory. 
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress: Pointer to write start address
+  * @param  pSrcBuffer: Pointer to source buffer to write  
+  * @param  BufferSize: Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
+{
+  __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
+  
+  /* Check the SRAM controller state */
+  if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+  {
+    return  HAL_ERROR; 
+  }
+  
+  /* Process Locked */
+  __HAL_LOCK(hsram);
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_BUSY; 
+
+  /* Write data to memory */
+  for(; BufferSize != 0; BufferSize--)
+  {
+    *(__IO uint8_t *)pSramAddress = *pSrcBuffer; 
+    pSrcBuffer++;
+    pSramAddress++;    
+  }    
+
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY; 
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram);
+    
+  return HAL_OK;   
+}
+
+/**
+  * @brief  Reads 16-bit buffer from SRAM memory. 
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress: Pointer to read start address
+  * @param  pDstBuffer: Pointer to destination buffer  
+  * @param  BufferSize: Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
+{
+  __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
+  
+  /* Process Locked */
+  __HAL_LOCK(hsram);
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_BUSY;  
+  
+  /* Read data from memory */
+  for(; BufferSize != 0; BufferSize--)
+  {
+    *pDstBuffer = *(__IO uint16_t *)pSramAddress;
+    pDstBuffer++;
+    pSramAddress++;
+  }
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY;    
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram); 
+    
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Writes 16-bit buffer to SRAM memory. 
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress: Pointer to write start address
+  * @param  pSrcBuffer: Pointer to source buffer to write  
+  * @param  BufferSize: Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
+{
+  __IO uint16_t * pSramAddress = (uint16_t *)pAddress; 
+  
+  /* Check the SRAM controller state */
+  if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+  {
+    return  HAL_ERROR; 
+  }
+  
+  /* Process Locked */
+  __HAL_LOCK(hsram);
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_BUSY; 
+
+  /* Write data to memory */
+  for(; BufferSize != 0; BufferSize--)
+  {
+    *(__IO uint16_t *)pSramAddress = *pSrcBuffer; 
+    pSrcBuffer++;
+    pSramAddress++;    
+  }    
+
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY; 
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram);
+    
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Reads 32-bit buffer from SRAM memory. 
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress: Pointer to read start address
+  * @param  pDstBuffer: Pointer to destination buffer  
+  * @param  BufferSize: Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsram);
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_BUSY;  
+  
+  /* Read data from memory */
+  for(; BufferSize != 0; BufferSize--)
+  {
+    *pDstBuffer = *(__IO uint32_t *)pAddress;
+    pDstBuffer++;
+    pAddress++;
+  }
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY;    
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram); 
+    
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Writes 32-bit buffer to SRAM memory. 
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress: Pointer to write start address
+  * @param  pSrcBuffer: Pointer to source buffer to write  
+  * @param  BufferSize: Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+{
+  /* Check the SRAM controller state */
+  if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+  {
+    return  HAL_ERROR; 
+  }
+  
+  /* Process Locked */
+  __HAL_LOCK(hsram);
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_BUSY; 
+
+  /* Write data to memory */
+  for(; BufferSize != 0; BufferSize--)
+  {
+    *(__IO uint32_t *)pAddress = *pSrcBuffer; 
+    pSrcBuffer++;
+    pAddress++;    
+  }    
+
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY; 
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram);
+    
+  return HAL_OK;   
+}
+
+/**
+  * @brief  Reads a Words data from the SRAM memory using DMA transfer.
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress: Pointer to read start address
+  * @param  pDstBuffer: Pointer to destination buffer  
+  * @param  BufferSize: Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsram);  
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_BUSY;   
+  
+  /* Configure DMA user callbacks */
+  hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
+  hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+
+  /* Enable the DMA Stream */
+  HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY; 
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram);  
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Writes a Words data buffer to SRAM memory using DMA transfer.
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress: Pointer to write start address
+  * @param  pSrcBuffer: Pointer to source buffer to write  
+  * @param  BufferSize: Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+{
+  /* Check the SRAM controller state */
+  if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+  {
+    return  HAL_ERROR; 
+  }
+  
+  /* Process Locked */
+  __HAL_LOCK(hsram);
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_BUSY; 
+  
+  /* Configure DMA user callbacks */
+  hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
+  hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+
+  /* Enable the DMA Stream */
+  HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY;  
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram);  
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup SRAM_Group3 Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+  ==============================================================================
+                        ##### SRAM Control functions #####
+  ==============================================================================  
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the SRAM interface.
+
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Enables dynamically SRAM write operation.
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsram);
+
+  /* Enable write operation */
+  FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); 
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram); 
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Disables dynamically SRAM write operation.
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsram);
+
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_BUSY;
+    
+  /* Disable write operation */
+  FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); 
+  
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_PROTECTED;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hsram); 
+  
+  return HAL_OK;  
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SRAM_Group4 State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### SRAM State functions #####
+  ==============================================================================  
+  [..]
+    This subsection permits to get in run-time the status of the SRAM controller 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Returns the SRAM controller state
+  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval HAL state
+  */
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
+{
+  return hsram->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* HAL_SRAM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,153 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_sram.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of SRAM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SRAM_H
+#define __STM32F4xx_HAL_SRAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+  #include "stm32f4xx_ll_fsmc.h"
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+  #include "stm32f4xx_ll_fmc.h"
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SRAM
+  * @{
+  */ 
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** 
+  * @brief  HAL SRAM State structures definition  
+  */ 
+typedef enum
+{
+  HAL_SRAM_STATE_RESET     = 0x00,  /*!< SRAM not yet initialized or disabled           */
+  HAL_SRAM_STATE_READY     = 0x01,  /*!< SRAM initialized and ready for use             */
+  HAL_SRAM_STATE_BUSY      = 0x02,  /*!< SRAM internal process is ongoing               */
+  HAL_SRAM_STATE_ERROR     = 0x03,  /*!< SRAM error state                               */
+  HAL_SRAM_STATE_PROTECTED = 0x04   /*!< SRAM peripheral NORSRAM device write protected */
+  
+}HAL_SRAM_StateTypeDef;
+
+/** 
+  * @brief  SRAM handle Structure definition  
+  */ 
+typedef struct
+{
+  FMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */ 
+  
+  FMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
+  
+  FMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
+
+  HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */ 
+  
+  __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
+  
+  DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
+  
+}SRAM_HandleTypeDef; 
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset SRAM handle state
+  * @param  __HANDLE__: SRAM handle
+  * @retval None
+  */
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
+
+/* I/O operation functions  *****************************************************/
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+
+void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+
+/* SRAM Control functions  ******************************************************/
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
+
+/* SRAM State functions *********************************************************/
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SRAM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,5127 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_tim.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Timer (TIM) peripheral:
+  *           + Time Base Initialization
+  *           + Time Base Start
+  *           + Time Base Start Interruption
+  *           + Time Base Start DMA
+  *           + Time Output Compare/PWM Initialization
+  *           + Time Output Compare/PWM Channel Configuration
+  *           + Time Output Compare/PWM  Start
+  *           + Time Output Compare/PWM  Start Interruption
+  *           + Time Output Compare/PWM Start DMA
+  *           + Time Input Capture Initialization
+  *           + Time Input Capture Channel Configuration
+  *           + Time Input Capture Start
+  *           + Time Input Capture Start Interruption 
+  *           + Time Input Capture Start DMA
+  *           + Time One Pulse Initialization
+  *           + Time One Pulse Channel Configuration
+  *           + Time One Pulse Start 
+  *           + Time Encoder Interface Initialization
+  *           + Time Encoder Interface Start
+  *           + Time Encoder Interface Start Interruption
+  *           + Time Encoder Interface Start DMA
+  *           + Commutation Event configuration with Interruption and DMA
+  *           + Time OCRef clear configuration
+  *           + Time External Clock configuration
+  @verbatim 
+  ==============================================================================
+                      ##### TIMER Generic features #####
+  ==============================================================================
+  [..] The Timer features include: 
+       (#) 16-bit up, down, up/down auto-reload counter.
+       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the 
+           counter clock frequency either by any factor between 1 and 65536.
+       (#) Up to 4 independent channels for:
+           (++) Input Capture
+           (++) Output Compare
+           (++) PWM generation (Edge and Center-aligned Mode)
+           (++) One-pulse mode output               
+   
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions 
+         depending from feature used :
+           (++) Time Base : HAL_TIM_Base_MspInit() 
+           (++) Input Capture : HAL_TIM_IC_MspInit()
+           (++) Output Compare : HAL_TIM_OC_MspInit()
+           (++) PWM generation : HAL_TIM_PWM_MspInit()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+           
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); 
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+                 __GPIOx_CLK_ENABLE();   
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();  
+
+     (#) The external Clock can be configured, if needed (the default clock is the 
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before 
+         any start function.
+  
+     (#) Configure the TIM in the desired functioning mode using one of the 
+         initialization function of this driver:
+         (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+         (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an 
+              Output Compare signal.
+         (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a 
+              PWM signal.
+         (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an 
+              external signal.
+         (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer 
+              in One Pulse Mode.
+         (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+         
+     (#) Activate the TIM peripheral using one of the start functions depending from the feature used: 
+           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+     (#) The DMA Burst is managed with the two following functions:
+         HAL_TIM_DMABurst_WriteStart()
+         HAL_TIM_DMABurst_ReadStart()
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIM 
+  * @brief TIM HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter);
+
+static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+
+static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup TIM_Private_Functions
+  * @{
+  */
+
+/** @defgroup TIM_Group1 Time Base functions 
+ *  @brief    Time Base functions 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Time Base functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM base. 
+    (+) De-initialize the TIM base.
+    (+) Start the Time Base.
+    (+) Stop the Time Base.
+    (+) Start the Time Base and enable interrupt.
+    (+) Stop the Time Base and disable interrupt.
+    (+) Start the Time Base and enable DMA transfer.
+    (+) Stop the Time Base and disable DMA transfer.
+ 
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Time base Unit according to the specified
+  *         parameters in the TIM_HandleTypeDef and create the associated handle.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{ 
+  /* Check the TIM handle allocation */
+  if(htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance)); 
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  
+  if(htim->State == HAL_TIM_STATE_RESET)
+  {  
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_TIM_Base_MspInit(htim);
+  }
+  
+  /* Set the TIM state */
+  htim->State= HAL_TIM_STATE_BUSY;
+  
+  /* Set the Time Base configuration */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init); 
+  
+  /* Initialize the TIM state*/
+  htim->State= HAL_TIM_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Base peripheral 
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{  
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+   
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+    
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Base_MspDeInit(htim);
+  
+  /* Change TIM state */  
+  htim->State = HAL_TIM_STATE_RESET; 
+  
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Base MSP.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Base MSP.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Base generation.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  
+  /* Set the TIM state */
+  htim->State= HAL_TIM_STATE_BUSY;
+  
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+  
+  /* Change the TIM state*/
+  htim->State= HAL_TIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  
+  /* Set the TIM state */
+  htim->State= HAL_TIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* Change the TIM state*/
+  htim->State= HAL_TIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in interrupt mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  
+  /* Enable the TIM Update interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+      
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+      
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in interrupt mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  /* Disable the TIM Update interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+      
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+    
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in DMA mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  pData: The source Buffer address.
+  * @param  Length: The length of data to be transferred from memory to peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); 
+  
+  if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if((pData == 0 ) && (Length > 0)) 
+    {
+      return HAL_ERROR;                                    
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }  
+  /* Set the DMA Period elapsed callback */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+     
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
+  
+  /* Enable the DMA Stream */
+  HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
+  
+  /* Enable the TIM Update DMA request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);  
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in DMA mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+  
+  /* Disable the TIM Update DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+      
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+    
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+      
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM_Group2 Time Output Compare functions 
+ *  @brief    Time Output Compare functions 
+ *
+@verbatim    
+  ==============================================================================
+                  ##### Time Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Output Compare. 
+    (+) De-initialize the TIM Output Compare.
+    (+) Start the Time Output Compare.
+    (+) Stop the Time Output Compare.
+    (+) Start the Time Output Compare and enable interrupt.
+    (+) Stop the Time Output Compare and disable interrupt.
+    (+) Start the Time Output Compare and enable DMA transfer.
+    (+) Stop the Time Output Compare and disable DMA transfer.
+ 
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Output Compare according to the specified
+  *         parameters in the TIM_HandleTypeDef and create the associated handle.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
+{
+  /* Check the TIM handle allocation */
+  if(htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ 
+  if(htim->State == HAL_TIM_STATE_RESET)
+  {   
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OC_MspInit(htim);
+  }
+  
+  /* Set the TIM state */
+  htim->State= HAL_TIM_STATE_BUSY;
+  
+  /* Init the base time for the Output Compare */  
+  TIM_Base_SetConfig(htim->Instance,  &htim->Init); 
+  
+  /* Initialize the TIM state*/
+  htim->State= HAL_TIM_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral 
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  
+   htim->State = HAL_TIM_STATE_BUSY;
+   
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_OC_MspDeInit(htim);
+    
+  /* Change TIM state */  
+  htim->State = HAL_TIM_STATE_RESET; 
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Output Compare MSP.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Output Compare MSP.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.  
+  * @param  Channel: TIM Channel to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+  
+  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+  
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim); 
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channel to be disabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+  
+  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+  {
+    /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }  
+  
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);  
+  
+  /* Return function status */
+  return HAL_OK;
+}  
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channel to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {       
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+    
+    default:
+    break;
+  } 
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+  
+  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channel to be disabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {       
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+    
+    default:
+    break; 
+  } 
+  
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 
+  
+  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+  {
+    /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+  
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);  
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channel to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData: The source Buffer address.
+  * @param  Length: The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  
+  if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if(((uint32_t)pData == 0 ) && (Length > 0)) 
+    {
+      return HAL_ERROR;                                    
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }    
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {      
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+      
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+      
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+      
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+     /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+      
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+    
+    default:
+    break;
+  }
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+  
+  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }  
+  
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim); 
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channel to be disabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {       
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+    
+    default:
+    break;
+  } 
+  
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+  
+  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+  {
+    /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+  
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group3 Time PWM functions 
+ *  @brief    Time PWM functions 
+ *
+@verbatim    
+  ==============================================================================
+                          ##### Time PWM functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM OPWM. 
+    (+) De-initialize the TIM PWM.
+    (+) Start the Time PWM.
+    (+) Stop the Time PWM.
+    (+) Start the Time PWM and enable interrupt.
+    (+) Stop the Time PWM and disable interrupt.
+    (+) Start the Time PWM and enable DMA transfer.
+    (+) Stop the Time PWM and disable DMA transfer.
+ 
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM PWM Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and create the associated handle.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if(htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+  if(htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_PWM_MspInit(htim);
+  }
+
+  /* Set the TIM state */
+  htim->State= HAL_TIM_STATE_BUSY;  
+  
+  /* Init the base time for the PWM */  
+  TIM_Base_SetConfig(htim->Instance, &htim->Init); 
+   
+  /* Initialize the TIM state*/
+  htim->State= HAL_TIM_STATE_READY;
+  
+  return HAL_OK;
+}  
+
+/**
+  * @brief  DeInitializes the TIM peripheral 
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  
+  htim->State = HAL_TIM_STATE_BUSY;
+  
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+    
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_PWM_MspDeInit(htim);
+    
+  /* Change TIM state */  
+  htim->State = HAL_TIM_STATE_RESET; 
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM PWM MSP.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM PWM MSP.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the PWM signal generation.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+  
+  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+    
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+} 
+
+/**
+  * @brief  Stops the PWM signal generation.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channels to be disabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+    
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+  
+  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+  {
+    /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+  
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+} 
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channel to be disabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {       
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+    
+    default:
+    break;
+  } 
+  
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+  
+  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+} 
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channels to be disabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {       
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+    
+    default:
+    break; 
+  }
+  
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+  
+  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+  {
+    /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+  
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+} 
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData: The source Buffer address.
+  * @param  Length: The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  
+  if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if(((uint32_t)pData == 0 ) && (Length > 0)) 
+    {
+      return HAL_ERROR;                                    
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }    
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {      
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+      
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+      
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+      
+      /* Enable the TIM Output Capture/Compare 3 request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+     /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+      
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+    
+    default:
+    break;
+  }
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+    
+  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+  
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim); 
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channels to be disabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {       
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+    
+    default:
+    break;
+  } 
+  
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+  
+  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+  {
+    /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+  
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group4 Time Input Capture functions 
+ *  @brief    Time Input Capture functions 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Time Input Capture functions #####
+  ==============================================================================
+ [..]  
+   This section provides functions allowing to:
+   (+) Initialize and configure the TIM Input Capture. 
+   (+) De-initialize the TIM Input Capture.
+   (+) Start the Time Input Capture.
+   (+) Stop the Time Input Capture.
+   (+) Start the Time Input Capture and enable interrupt.
+   (+) Stop the Time Input Capture and disable interrupt.
+   (+) Start the Time Input Capture and enable DMA transfer.
+   (+) Stop the Time Input Capture and disable DMA transfer.
+ 
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Input Capture Time base according to the specified
+  *         parameters in the TIM_HandleTypeDef and create the associated handle.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if(htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 
+
+  if(htim->State == HAL_TIM_STATE_RESET)
+  {  
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_IC_MspInit(htim);
+  }
+  
+  /* Set the TIM state */
+  htim->State= HAL_TIM_STATE_BUSY;   
+  
+  /* Init the base time for the input capture */  
+  TIM_Base_SetConfig(htim->Instance, &htim->Init); 
+   
+  /* Initialize the TIM state*/
+  htim->State= HAL_TIM_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral 
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+  
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+    
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_IC_MspDeInit(htim);
+    
+  /* Change TIM state */  
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM INput Capture MSP.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Input Capture MSP.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+    
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);  
+
+  /* Return function status */
+  return HAL_OK;  
+} 
+
+/**
+  * @brief  Stops the TIM Input Capture measurement.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channels to be disabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+  
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim); 
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in interrupt mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {       
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+    
+    default:
+    break;
+  }  
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+    
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);  
+
+  /* Return function status */
+  return HAL_OK;  
+} 
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in interrupt mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channels to be disabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {       
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+    
+    default:
+    break; 
+  } 
+  
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 
+  
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim); 
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement on in DMA mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData: The destination Buffer address.
+  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+  
+  if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if((pData == 0 ) && (Length > 0)) 
+    {
+      return HAL_ERROR;                                    
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }  
+   
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); 
+      
+      /* Enable the TIM Capture/Compare 1 DMA request */      
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
+      
+      /* Enable the TIM Capture/Compare 2  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
+      
+      /* Enable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
+      
+      /* Enable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+    
+    default:
+    break;
+  }
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+   
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim); 
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement on in DMA mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channels to be disabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+  
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {       
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+    
+    default:
+    break;
+  }
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+  
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim); 
+  
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}  
+/**
+  * @}
+  */
+  
+/** @defgroup TIM_Group5 Time One Pulse functions 
+ *  @brief    Time One Pulse functions 
+ *
+@verbatim    
+  ==============================================================================
+                        ##### Time One Pulse functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM One Pulse. 
+    (+) De-initialize the TIM One Pulse.
+    (+) Start the Time One Pulse.
+    (+) Stop the Time One Pulse.
+    (+) Start the Time One Pulse and enable interrupt.
+    (+) Stop the Time One Pulse and disable interrupt.
+    (+) Start the Time One Pulse and enable DMA transfer.
+    (+) Stop the Time One Pulse and disable DMA transfer.
+ 
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM One Pulse Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and create the associated handle.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  OnePulseMode: Select the One pulse mode.
+  *         This parameter can be one of the following values:
+  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+  /* Check the TIM handle allocation */
+  if(htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+  
+  if(htim->State == HAL_TIM_STATE_RESET)
+  {   
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OnePulse_MspInit(htim);
+  }
+  
+  /* Set the TIM state */
+  htim->State= HAL_TIM_STATE_BUSY;  
+  
+  /* Configure the Time base in the One Pulse Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+  
+  /* Reset the OPM Bit */
+  htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+  /* Configure the OPM Mode */
+  htim->Instance->CR1 |= OnePulseMode;
+   
+  /* Initialize the TIM state*/
+  htim->State= HAL_TIM_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM One Pulse  
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  
+  htim->State = HAL_TIM_STATE_BUSY;
+  
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_OnePulse_MspDeInit(htim);
+    
+  /* Change TIM state */  
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse MSP.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM One Pulse MSP.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  OutputChannel : TIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Enable the Capture compare and the Input Capture channels 
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 
+    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together 
+    
+    No need to enable the counter, it's enabled automatically by hardware 
+    (the counter starts in response to a stimulus and generate a pulse */
+  
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 
+  
+  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  OutputChannel : TIM Channels to be disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Disable the Capture compare and the Input Capture channels 
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 
+  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+  
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
+    
+  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+  {
+    /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+    
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim); 
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  OutputChannel : TIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Enable the Capture compare and the Input Capture channels 
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 
+    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together 
+    
+    No need to enable the counter, it's enabled automatically by hardware 
+    (the counter starts in response to a stimulus and generate a pulse */
+ 
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+  
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+  
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 
+  
+  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  OutputChannel : TIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);  
+  
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  
+  /* Disable the Capture compare and the Input Capture channels 
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 
+  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */  
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
+    
+  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+  {
+    /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+    
+  /* Disable the Peripheral */
+   __HAL_TIM_DISABLE(htim);  
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group6 Time Encoder functions 
+ *  @brief    Time Encoder functions 
+ *
+@verbatim    
+  ==============================================================================
+                          ##### Time Encoder functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Encoder. 
+    (+) De-initialize the TIM Encoder.
+    (+) Start the Time Encoder.
+    (+) Stop the Time Encoder.
+    (+) Start the Time Encoder and enable interrupt.
+    (+) Stop the Time Encoder and disable interrupt.
+    (+) Start the Time Encoder and enable DMA transfer.
+    (+) Stop the Time Encoder and disable DMA transfer.
+ 
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Encoder Interface and create the associated handle.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  sConfig: TIM Encoder Interface configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig)
+{
+  uint32_t tmpsmcr = 0;
+  uint32_t tmpccmr1 = 0;
+  uint32_t tmpccer = 0;
+  
+  /* Check the TIM handle allocation */
+  if(htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+
+  if(htim->State == HAL_TIM_STATE_RESET)
+  { 
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_Encoder_MspInit(htim);
+  }
+  
+  /* Set the TIM state */
+  htim->State= HAL_TIM_STATE_BUSY;   
+    
+  /* Reset the SMS bits */
+  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+  
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);  
+  
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = htim->Instance->CCMR1;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = htim->Instance->CCER;
+
+  /* Set the encoder Mode */
+  tmpsmcr |= sConfig->EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
+  
+  /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
+  tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
+
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
+  
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Write to TIMx CCMR1 */
+  htim->Instance->CCMR1 = tmpccmr1;
+
+  /* Write to TIMx CCER */
+  htim->Instance->CCER = tmpccer;
+  
+  /* Initialize the TIM state*/
+  htim->State= HAL_TIM_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Encoder interface  
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  
+  htim->State = HAL_TIM_STATE_BUSY;
+  
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Encoder_MspDeInit(htim);
+    
+  /* Change TIM state */  
+  htim->State = HAL_TIM_STATE_RESET;
+ 
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Encoder Interface MSP.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Encoder Interface MSP.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+  
+  /* Enable the encoder interface channels */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      break; 
+    }
+    case TIM_CHANNEL_2:
+    { 
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 
+      break;
+    }  
+    default :
+    {
+     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+     break; 
+    }
+  }  
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channels to be disabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+    
+   /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ 
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      break; 
+    }
+    case TIM_CHANNEL_2:
+    { 
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
+      break;
+    }  
+    default :
+    {
+     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+     break; 
+    }
+  }  
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in interrupt mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+  
+  /* Enable the encoder interface channels */
+  /* Enable the capture compare Interrupts 1 and/or 2 */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break; 
+    }
+    case TIM_CHANNEL_2:
+    { 
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 
+      break;
+    }  
+    default :
+    {
+     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+     break; 
+    }
+  }
+  
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in interrupt mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channels to be disabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+    
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ 
+  if(Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
+    
+    /* Disable the capture compare Interrupts 1 */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+  }  
+  else if(Channel == TIM_CHANNEL_2)
+  {  
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
+    
+    /* Disable the capture compare Interrupts 2 */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }  
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
+    
+    /* Disable the capture compare Interrupts 1 and 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+    
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in DMA mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @param  pData1: The destination Buffer address for IC1.
+  * @param  pData2: The destination Buffer address for IC2.
+  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+  
+  if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) 
+    {
+      return HAL_ERROR;                                    
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }  
+   
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); 
+      
+      /* Enable the TIM Input Capture DMA request */      
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+            
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+      
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
+      
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+     
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+      
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+    }
+    break;
+    
+    case TIM_CHANNEL_ALL:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
+      
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
+          
+     /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+      
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+    
+    default:
+    break;
+  }  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in DMA mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+  
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ 
+  if(Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
+    
+    /* Disable the capture compare DMA Request 1 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+  }  
+  else if(Channel == TIM_CHANNEL_2)
+  {  
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
+    
+    /* Disable the capture compare DMA Request 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+  }  
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
+    
+    /* Disable the capture compare DMA Request 1 and 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+  }
+  
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+/** @defgroup TIM_Group7 TIM IRQ handler management 
+ *  @brief    IRQ handler management 
+ *
+@verbatim   
+  ==============================================================================
+                        ##### IRQ handler management #####
+  ==============================================================================  
+  [..]  
+    This section provides Timer IRQ handler function.
+               
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  This function handles TIM interrupts requests.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+  /* Capture compare 1 event */
+  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+  {
+    if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
+    {
+      {
+        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+        
+        /* Input capture event */
+        if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
+        {
+          HAL_TIM_IC_CaptureCallback(htim);
+        }
+        /* Output compare event */
+        else
+        {
+          HAL_TIM_OC_DelayElapsedCallback(htim);
+          HAL_TIM_PWM_PulseFinishedCallback(htim);
+        }
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+      }
+    }
+  }
+  /* Capture compare 2 event */
+  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+  {
+    if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+      /* Input capture event */
+      if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
+      {          
+        HAL_TIM_IC_CaptureCallback(htim);
+      }
+      /* Output compare event */
+      else
+      {
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 3 event */
+  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+  {
+    if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+      /* Input capture event */
+      if((htim->Instance->CCMR1 & TIM_CCMR2_CC3S) != 0x00)
+      {          
+        HAL_TIM_IC_CaptureCallback(htim);
+      }
+      /* Output compare event */
+      else
+      {
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim); 
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 4 event */
+  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+  {
+    if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+      /* Input capture event */
+      if((htim->Instance->CCMR1 & TIM_CCMR2_CC4S) != 0x00)
+      {          
+        HAL_TIM_IC_CaptureCallback(htim);
+      }
+      /* Output compare event */
+      else
+      {
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* TIM Update event */
+  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+  {
+    if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+      HAL_TIM_PeriodElapsedCallback(htim);
+    }
+  }
+  /* TIM Break input event */
+  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+  {
+    if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_BREAK) !=RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+      HAL_TIMEx_BreakCallback(htim);
+    }
+  }
+  /* TIM Trigger detection event */
+  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+  {
+    if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+      HAL_TIM_TriggerCallback(htim);
+    }
+  }
+  /* TIM commutation event */
+  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+  {
+    if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_COM) !=RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+      HAL_TIMEx_CommutationCallback(htim);
+    }
+  }
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM_Group8 Peripheral Control functions
+ *  @brief   	Peripheral Control functions 
+ *
+@verbatim   
+  ==============================================================================
+                   ##### Peripheral Control functions #####
+  ==============================================================================  
+ [..] 
+   This section provides functions allowing to:
+   (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. 
+   (+) Configure External Clock source.
+   (+) Configure Complementary channels, break features and dead time.
+   (+) Configure Master and the Slave synchronization.
+   (+) Configure the DMA Burst Mode.
+      
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initializes the TIM Output Compare Channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  sConfig: TIM Output Compare configuration structure
+  * @param  Channel: TIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+{
+  /* Check the parameters */ 
+  assert_param(IS_TIM_CHANNELS(Channel)); 
+  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+  assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
+  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+  assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
+  assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
+  
+  /* Check input state */
+  __HAL_LOCK(htim); 
+  
+  htim->State = HAL_TIM_STATE_BUSY;
+  
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      /* Configure the TIM Channel 1 in Output Compare */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      /* Configure the TIM Channel 2 in Output Compare */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+      /* Configure the TIM Channel 3 in Output Compare */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+      /* Configure the TIM Channel 4 in Output Compare */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+    }
+    break;
+    
+    default:
+    break;    
+  }
+  htim->State = HAL_TIM_STATE_READY;
+  
+  __HAL_UNLOCK(htim); 
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture Channels according to the specified
+  *         parameters in the TIM_IC_InitTypeDef.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  sConfig: TIM Input Capture configuration structure
+  * @param  Channel: TIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+  
+  __HAL_LOCK(htim);
+  
+  htim->State = HAL_TIM_STATE_BUSY;
+  
+  if (Channel == TIM_CHANNEL_1)
+  {
+    /* TI1 Configuration */
+    TIM_TI1_SetConfig(htim->Instance,
+               sConfig->ICPolarity,
+               sConfig->ICSelection,
+               sConfig->ICFilter);
+               
+    /* Reset the IC1PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+    /* Set the IC1PSC value */
+    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    /* TI2 Configuration */
+    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+    
+    TIM_TI2_SetConfig(htim->Instance, 
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+               
+    /* Reset the IC2PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+    /* Set the IC2PSC value */
+    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
+  }
+  else if (Channel == TIM_CHANNEL_3)
+  {
+    /* TI3 Configuration */
+    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+    
+    TIM_TI3_SetConfig(htim->Instance,  
+               sConfig->ICPolarity,
+               sConfig->ICSelection,
+               sConfig->ICFilter);
+               
+    /* Reset the IC3PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+    /* Set the IC3PSC value */
+    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+  }
+  else
+  {
+    /* TI4 Configuration */
+    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+    
+    TIM_TI4_SetConfig(htim->Instance, 
+               sConfig->ICPolarity,
+               sConfig->ICSelection,
+               sConfig->ICFilter);
+               
+    /* Reset the IC4PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+    /* Set the IC4PSC value */
+    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
+  }
+  
+  htim->State = HAL_TIM_STATE_READY;
+    
+  __HAL_UNLOCK(htim);
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Initializes the TIM PWM  channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  sConfig: TIM PWM configuration structure
+  * @param  Channel: TIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+{
+  __HAL_LOCK(htim);
+  
+  /* Check the parameters */ 
+  assert_param(IS_TIM_CHANNELS(Channel)); 
+  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+  assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
+  assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
+  assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
+  
+  htim->State = HAL_TIM_STATE_BUSY;
+    
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      /* Configure the Channel 1 in PWM mode */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+      
+      /* Set the Preload enable bit for channel1 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+      
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode;
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      /* Configure the Channel 2 in PWM mode */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+      
+      /* Set the Preload enable bit for channel2 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+      
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+      /* Configure the Channel 3 in PWM mode */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+      
+      /* Set the Preload enable bit for channel3 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+      
+     /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode;  
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+      /* Configure the Channel 4 in PWM mode */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+      
+      /* Set the Preload enable bit for channel4 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+      
+     /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;  
+    }
+    break;
+    
+    default:
+    break;    
+  }
+  
+  htim->State = HAL_TIM_STATE_READY;
+    
+  __HAL_UNLOCK(htim);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse Channels according to the specified
+  *         parameters in the TIM_OnePulse_InitTypeDef.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  sConfig: TIM One Pulse configuration structure
+  * @param  OutputChannel: TIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @param  InputChannel: TIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel)
+{
+  TIM_OC_InitTypeDef temp1;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+  if(OutputChannel != InputChannel)  
+  {
+    __HAL_LOCK(htim);
+  
+    htim->State = HAL_TIM_STATE_BUSY;
+
+    /* Extract the Ouput compare configuration from sConfig structure */  
+    temp1.OCMode = sConfig->OCMode;
+    temp1.Pulse = sConfig->Pulse;
+    temp1.OCPolarity = sConfig->OCPolarity;
+    temp1.OCNPolarity = sConfig->OCNPolarity;
+    temp1.OCIdleState = sConfig->OCIdleState;
+    temp1.OCNIdleState = sConfig->OCNIdleState; 
+    
+    switch (OutputChannel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      
+        TIM_OC1_SetConfig(htim->Instance, &temp1); 
+      }
+      break;
+      case TIM_CHANNEL_2:
+      {
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      
+        TIM_OC2_SetConfig(htim->Instance, &temp1);
+      }
+      break;
+      default:
+      break;  
+    } 
+    switch (InputChannel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      
+        TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+                        sConfig->ICSelection, sConfig->ICFilter);
+               
+        /* Reset the IC1PSC Bits */
+        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+        /* Select the Trigger source */
+        htim->Instance->SMCR &= ~TIM_SMCR_TS;
+        htim->Instance->SMCR |= TIM_TS_TI1FP1;
+      
+        /* Select the Slave Mode */      
+        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+      }
+      break;
+      case TIM_CHANNEL_2:
+      {
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      
+        TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+                 sConfig->ICSelection, sConfig->ICFilter);
+               
+        /* Reset the IC2PSC Bits */
+        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+        /* Select the Trigger source */
+        htim->Instance->SMCR &= ~TIM_SMCR_TS;
+        htim->Instance->SMCR |= TIM_TS_TI2FP2;
+      
+        /* Select the Slave Mode */      
+        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+      }
+      break;
+    
+      default:
+      break;  
+    }
+  
+    htim->State = HAL_TIM_STATE_READY;
+    
+    __HAL_UNLOCK(htim);
+  
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+} 
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral  
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
+  *         This parameters can be on of the following values:
+  *            @arg TIM_DMABase_CR1  
+  *            @arg TIM_DMABase_CR2
+  *            @arg TIM_DMABase_SMCR
+  *            @arg TIM_DMABase_DIER
+  *            @arg TIM_DMABase_SR
+  *            @arg TIM_DMABase_EGR
+  *            @arg TIM_DMABase_CCMR1
+  *            @arg TIM_DMABase_CCMR2
+  *            @arg TIM_DMABase_CCER
+  *            @arg TIM_DMABase_CNT   
+  *            @arg TIM_DMABase_PSC   
+  *            @arg TIM_DMABase_ARR
+  *            @arg TIM_DMABase_RCR
+  *            @arg TIM_DMABase_CCR1
+  *            @arg TIM_DMABase_CCR2
+  *            @arg TIM_DMABase_CCR3  
+  *            @arg TIM_DMABase_CCR4
+  *            @arg TIM_DMABase_BDTR
+  *            @arg TIM_DMABase_DCR
+  * @param  BurstRequestSrc: TIM DMA Request sources.
+  *         This parameters can be on of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer: The Buffer address.
+  * @param  BurstLength: DMA Burst length. This parameter can be one value
+  *         between TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+                                              uint32_t* BurstBuffer, uint32_t  BurstLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  
+  if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if((BurstBuffer == 0 ) && (BurstLength > 0)) 
+    {
+      return HAL_ERROR;                                    
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  switch(BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {  
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
+  
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); 
+    }
+    break;
+    case TIM_DMA_CC1:
+    {  
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+  
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     
+    }
+    break;
+    case TIM_DMA_CC2:
+    {  
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+  
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     
+    }
+    break;
+    case TIM_DMA_CC3:
+    {  
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+  
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     
+    }
+    break;
+    case TIM_DMA_CC4:
+    {  
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+  
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     
+    }
+    break;
+    case TIM_DMA_COM:
+    {  
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
+  
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     
+    }
+    break;
+    case TIM_DMA_TRIGGER:
+    {  
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
+  
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     
+    }
+    break;
+    default:
+    break;  
+  }
+   /* configure the DMA Burst Mode */
+   htim->Instance->DCR = BurstBaseAddress | BurstLength;  
+   
+   /* Enable the TIM DMA Request */
+   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);  
+   
+   htim->State = HAL_TIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM DMA Burst mode 
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  BurstRequestSrc: TIM DMA Request sources to disable
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  
+  /* Disable the TIM Update DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+      
+  /* Return function status */
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory 
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
+  *         This parameters can be on of the following values:
+  *            @arg TIM_DMABase_CR1  
+  *            @arg TIM_DMABase_CR2
+  *            @arg TIM_DMABase_SMCR
+  *            @arg TIM_DMABase_DIER
+  *            @arg TIM_DMABase_SR
+  *            @arg TIM_DMABase_EGR
+  *            @arg TIM_DMABase_CCMR1
+  *            @arg TIM_DMABase_CCMR2
+  *            @arg TIM_DMABase_CCER
+  *            @arg TIM_DMABase_CNT   
+  *            @arg TIM_DMABase_PSC   
+  *            @arg TIM_DMABase_ARR
+  *            @arg TIM_DMABase_RCR
+  *            @arg TIM_DMABase_CCR1
+  *            @arg TIM_DMABase_CCR2
+  *            @arg TIM_DMABase_CCR3  
+  *            @arg TIM_DMABase_CCR4
+  *            @arg TIM_DMABase_BDTR
+  *            @arg TIM_DMABase_DCR
+  * @param  BurstRequestSrc: TIM DMA Request sources.
+  *         This parameters can be on of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer: The Buffer address.
+  * @param  BurstLength: DMA Burst length. This parameter can be one value
+  *         between TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+                                             uint32_t  *BurstBuffer, uint32_t  BurstLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  
+  if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if((BurstBuffer == 0 ) && (BurstLength > 0)) 
+    {
+      return HAL_ERROR;                                    
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }  
+  switch(BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {  
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
+  
+      /* Enable the DMA Stream */
+       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);     
+    }
+    break;
+    case TIM_DMA_CC1:
+    {  
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+  
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      
+    }
+    break;
+    case TIM_DMA_CC2:
+    {  
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+  
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);     
+    }
+    break;
+    case TIM_DMA_CC3:
+    {  
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+  
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      
+    }
+    break;
+    case TIM_DMA_CC4:
+    {  
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+  
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      
+    }
+    break;
+    case TIM_DMA_COM:
+    {  
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
+  
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      
+    }
+    break;
+    case TIM_DMA_TRIGGER:
+    {  
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
+  
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      
+    }
+    break;
+    default:
+    break;  
+  }
+
+  /* configure the DMA Burst Mode */
+  htim->Instance->DCR = BurstBaseAddress | BurstLength;  
+  
+  /* Enable the TIM DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+  
+  htim->State = HAL_TIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the DMA burst reading 
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  BurstRequestSrc: TIM DMA Request sources to disable.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  
+  /* Disable the TIM Update DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+      
+  /* Return function status */
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Generate a software event
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  EventSource: specifies the event source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_EventSource_Update: Timer update Event source
+  *            @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
+  *            @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
+  *            @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
+  *            @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
+  *            @arg TIM_EventSource_COM: Timer COM event source  
+  *            @arg TIM_EventSource_Trigger: Timer Trigger Event source
+  *            @arg TIM_EventSource_Break: Timer Break event source
+  * @note   TIM6 and TIM7 can only generate an update event. 
+  * @note   TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
+  * @retval HAL status
+  */ 
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+  
+  /* Process Locked */
+  __HAL_LOCK(htim);
+  
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+  
+  /* Set the event sources */
+  htim->Instance->EGR = EventSource;
+  
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+  
+  __HAL_UNLOCK(htim);
+  
+  /* Return function status */
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Configures the OCRef clear feature
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
+  *         contains the OCREF clear feature and parameters for the TIM peripheral. 
+  * @param  Channel: specifies the TIM Channel.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+  assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+  assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+  assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+   
+  /* Process Locked */
+  __HAL_LOCK(htim);
+  
+  htim->State = HAL_TIM_STATE_BUSY;
+  
+  if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
+  {
+    TIM_ETR_SetConfig(htim->Instance, 
+                      sClearInputConfig->ClearInputPrescaler,
+                      sClearInputConfig->ClearInputPolarity,
+                      sClearInputConfig->ClearInputFilter);
+  }
+  
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {        
+      if(sClearInputConfig->ClearInputState != RESET)  
+      {
+        /* Enable the Ocref clear feature for Channel 1 */
+        htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
+      }
+      else
+      {
+        /* Disable the Ocref clear feature for Channel 1 */
+        htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;      
+      }
+    }    
+    break;
+    case TIM_CHANNEL_2:    
+    { 
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 
+      if(sClearInputConfig->ClearInputState != RESET)  
+      {
+        /* Enable the Ocref clear feature for Channel 2 */
+        htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
+      }
+      else
+      {
+        /* Disable the Ocref clear feature for Channel 2 */
+        htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;      
+      }
+    } 
+    break;
+    case TIM_CHANNEL_3:   
+    {  
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+      if(sClearInputConfig->ClearInputState != RESET)  
+      {
+        /* Enable the Ocref clear feature for Channel 3 */
+        htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
+      }
+      else
+      {
+        /* Disable the Ocref clear feature for Channel 3 */
+        htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;      
+      }
+    } 
+    break;
+    case TIM_CHANNEL_4:    
+    {  
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+      if(sClearInputConfig->ClearInputState != RESET)  
+      {
+        /* Enable the Ocref clear feature for Channel 4 */
+        htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
+      }
+      else
+      {
+        /* Disable the Ocref clear feature for Channel 4 */
+        htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;      
+      }
+    } 
+    break;
+    default:  
+    break;
+  } 
+
+  htim->State = HAL_TIM_STATE_READY;
+  
+  __HAL_UNLOCK(htim);
+  
+  return HAL_OK;  
+}  
+
+/**
+  * @brief   Configures the clock source to be used
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
+  *         contains the clock source information for the TIM peripheral. 
+  * @retval HAL status
+  */ 
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)    
+{
+  uint32_t tmpsmcr = 0;
+    
+  /* Process Locked */
+  __HAL_LOCK(htim);
+  
+  htim->State = HAL_TIM_STATE_BUSY;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+  assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+  assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+  assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+  
+  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+  tmpsmcr = htim->Instance->SMCR;
+  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+  htim->Instance->SMCR = tmpsmcr;
+  
+  switch (sClockSourceConfig->ClockSource)
+  {
+    case TIM_CLOCKSOURCE_INTERNAL:
+    { 
+      assert_param(IS_TIM_INSTANCE(htim->Instance));      
+      /* Disable slave mode to clock the prescaler directly with the internal clock */
+      htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+    }
+    break;
+    
+    case TIM_CLOCKSOURCE_ETRMODE1:
+    {
+      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance, 
+                        sClockSourceConfig->ClockPrescaler, 
+                        sClockSourceConfig->ClockPolarity, 
+                        sClockSourceConfig->ClockFilter);
+      /* Get the TIMx SMCR register value */
+      tmpsmcr = htim->Instance->SMCR;
+      /* Reset the SMS and TS Bits */
+      tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+      /* Select the External clock mode1 and the ETRF trigger */
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+      /* Write to TIMx SMCR */
+      htim->Instance->SMCR = tmpsmcr;
+    }
+    break;
+    
+    case TIM_CLOCKSOURCE_ETRMODE2:
+    {
+      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance, 
+                        sClockSourceConfig->ClockPrescaler, 
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+      /* Enable the External clock mode2 */
+      htim->Instance->SMCR |= TIM_SMCR_ECE;
+    }
+    break;
+    
+    case TIM_CLOCKSOURCE_TI1:
+    {
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      TIM_TI1_ConfigInputStage(htim->Instance, 
+                        sClockSourceConfig->ClockPolarity, 
+                        sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+    }
+    break;
+    case TIM_CLOCKSOURCE_TI2:
+    {
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      TIM_TI2_ConfigInputStage(htim->Instance, 
+                        sClockSourceConfig->ClockPolarity, 
+                        sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+    }
+    break;
+    case TIM_CLOCKSOURCE_TI1ED:
+    {
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      TIM_TI1_ConfigInputStage(htim->Instance, 
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+    }
+    break;
+    case TIM_CLOCKSOURCE_ITR0:
+    {
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
+    }
+    break;
+    case TIM_CLOCKSOURCE_ITR1:
+    {
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
+    }
+    break;
+    case TIM_CLOCKSOURCE_ITR2:
+    {
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
+    }
+    break;
+    case TIM_CLOCKSOURCE_ITR3:
+    {
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
+    }
+    break;
+    
+    default:
+    break;    
+  }
+  htim->State = HAL_TIM_STATE_READY;
+  
+  __HAL_UNLOCK(htim);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
+  *         or a XOR combination between CH1_input, CH2_input & CH3_input
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module..
+  * @param  TI1_Selection: Indicate whether or not channel 1 is connected to the
+  *         output of a XOR gate.
+  *         This parameter can be one of the following values:
+  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+  *            pins are connected to the TI1 input (XOR combination)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+  uint32_t tmpcr2 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); 
+  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Reset the TI1 selection */
+  tmpcr2 &= ~TIM_CR2_TI1S;
+
+  /* Set the the TI1 selection */
+  tmpcr2 |= TI1_Selection;
+  
+  /* Write to TIMxCR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module..
+  * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the ) and the Slave 
+  *         mode (Disable, Reset, Gated, Trigger, External clock mode 1). 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+  uint32_t tmpsmcr  = 0;
+  uint32_t tmpccmr1 = 0;
+  uint32_t tmpccer = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+   
+  __HAL_LOCK(htim);
+  
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Reset the Trigger Selection Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source */
+  tmpsmcr |= sSlaveConfig->InputTrigger;
+
+  /* Reset the slave mode Bits */
+  tmpsmcr &= ~TIM_SMCR_SMS;
+  /* Set the slave mode */
+  tmpsmcr |= sSlaveConfig->SlaveMode;
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+  
+  /* Configure the trigger prescaler, filter, and polarity */
+  switch (sSlaveConfig->InputTrigger)
+  {
+  case TIM_TS_ETRF:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+      /* Configure the ETR Trigger source */
+      TIM_ETR_SetConfig(htim->Instance, 
+                        sSlaveConfig->TriggerPrescaler, 
+                        sSlaveConfig->TriggerPolarity, 
+                        sSlaveConfig->TriggerFilter);
+    }
+    break;
+    
+  case TIM_TS_TI1F_ED:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+      
+      /* Disable the Channel 1: Reset the CC1E Bit */
+      tmpccer = htim->Instance->CCER;
+      htim->Instance->CCER &= ~TIM_CCER_CC1E;
+      tmpccmr1 = htim->Instance->CCMR1;    
+      
+      /* Set the filter */
+      tmpccmr1 &= ~TIM_CCMR1_IC1F;
+      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
+      
+      /* Write to TIMx CCMR1 and CCER registers */
+      htim->Instance->CCMR1 = tmpccmr1;
+      htim->Instance->CCER = tmpccer;                               
+                               
+    }
+    break;
+    
+  case TIM_TS_TI1FP1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI1 Filter and Polarity */
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+    }
+    break;
+    
+  case TIM_TS_TI2FP2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+      
+      /* Configure TI2 Filter and Polarity */
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                                sSlaveConfig->TriggerPolarity,
+                                sSlaveConfig->TriggerFilter);
+    }
+    break;
+    
+  case TIM_TS_ITR0:
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+    }
+    break;
+    
+  case TIM_TS_ITR1:
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+    }
+    break;
+    
+  case TIM_TS_ITR2:
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+    }
+    break;
+    
+  case TIM_TS_ITR3:
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+    }
+    break;
+       
+  default:
+    break;
+  }
+  
+  htim->State = HAL_TIM_STATE_READY;
+     
+  __HAL_UNLOCK(htim);  
+  
+  return HAL_OK;
+} 
+
+/**
+  * @brief  Read the captured value from Capture Compare unit
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module..
+  * @param  Channel: TIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval Captured value
+  */
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpreg = 0;
+  
+  __HAL_LOCK(htim);
+  
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      
+      /* Return the capture 1 value */
+      tmpreg = htim->Instance->CCR1;
+      
+      break;
+    }
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      
+      /* Return the capture 2 value */
+      tmpreg = htim->Instance->CCR2;
+      
+      break;
+    }
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+      
+      /* Return the capture 3 value */
+      tmpreg = htim->Instance->CCR3;
+      
+      break;
+    }
+    
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+      
+      /* Return the capture 4 value */
+      tmpreg = htim->Instance->CCR4;
+      
+      break;
+    }
+    
+    default:
+    break;  
+  }
+     
+  __HAL_UNLOCK(htim);  
+  return tmpreg;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM_Group9 TIM Callbacks functions
+ *  @brief    TIM Callbacks functions 
+ *
+@verbatim   
+  ==============================================================================
+                        ##### TIM Callbacks functions #####
+  ==============================================================================  
+ [..]  
+   This section provides TIM callback functions:
+   (+) Timer Period elapsed callback
+   (+) Timer Output Compare callback
+   (+) Timer Input capture callback
+   (+) Timer Trigger callback
+   (+) Timer Error callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Period elapsed callback in non blocking mode 
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+   */
+  
+}
+/**
+  * @brief  Output Compare callback in non blocking mode 
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+   */
+}
+/**
+  * @brief  Input Capture callback in non blocking mode 
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished callback in non blocking mode 
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection callback in non blocking mode 
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timer error callback in non blocking mode 
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIM_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group10 Peripheral State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+  ==============================================================================
+                        ##### Peripheral State functions #####
+  ==============================================================================  
+  [..]
+    This subsection permits to get in run-time the status of the peripheral 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Base state
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM OC state
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM PWM state
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Input Capture state
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM One Pulse Mode state
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Encoder Mode state
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  TIM DMA error callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  htim->State= HAL_TIM_STATE_READY;
+   
+  HAL_TIM_ErrorCallback(htim);
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  htim->State= HAL_TIM_STATE_READY; 
+  
+  HAL_TIM_PWM_PulseFinishedCallback(htim);
+}
+/**
+  * @brief  TIM DMA Capture complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    
+   htim->State= HAL_TIM_STATE_READY; 
+    
+  HAL_TIM_IC_CaptureCallback(htim);
+
+}
+
+/**
+  * @brief  TIM DMA Period Elapse complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  htim->State= HAL_TIM_STATE_READY;
+  
+  HAL_TIM_PeriodElapsedCallback(htim);
+}
+
+/**
+  * @brief  TIM DMA Trigger callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;  
+  
+  htim->State= HAL_TIM_STATE_READY; 
+  
+  HAL_TIM_TriggerCallback(htim);
+}
+
+/**
+  * @brief  Time Base configuration
+  * @param  TIMx: TIM periheral
+  * @retval None
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+  uint32_t tmpcr1 = 0;
+  tmpcr1 = TIMx->CR1;
+  
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/
+  if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)   
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+    tmpcr1 |= Structure->CounterMode;
+  }
+ 
+  if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)  
+  {
+    /* Set the clock division */
+    tmpcr1 &= ~TIM_CR1_CKD;
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+  }
+
+  TIMx->CR1 = tmpcr1;
+
+  /* Set the Autoreload value */
+  TIMx->ARR = (uint32_t)Structure->Period ;
+ 
+  /* Set the Prescaler value */
+  TIMx->PSC = (uint32_t)Structure->Prescaler;
+    
+  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)  
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = Structure->RepetitionCounter;
+  }
+
+  /* Generate an update event to reload the Prescaler 
+     and the repetition counter(only for TIM1 and TIM8) value immediatly */
+  TIMx->EGR = TIM_EGR_UG;
+}
+
+/**
+  * @brief  Time Ouput Compare 1 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config: The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx = 0;
+  uint32_t tmpccer = 0;
+  uint32_t tmpcr2 = 0;  
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = TIMx->CR2;
+  
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+    
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC1M;
+  tmpccmrx &= ~TIM_CCMR1_CC1S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC1P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= OC_Config->OCPolarity;
+
+    
+  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+  {   
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC1NP;
+    /* Set the Output N Polarity */
+    tmpccer |= OC_Config->OCNPolarity;
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC1NE;
+    
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS1;
+    tmpcr2 &= ~TIM_CR2_OIS1N;
+    /* Set the Output Idle state */
+    tmpcr2 |= OC_Config->OCIdleState;
+    /* Set the Output N Idle state */
+    tmpcr2 |= OC_Config->OCNIdleState;
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+  
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = OC_Config->Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;  
+} 
+
+/**
+  * @brief  Time Ouput Compare 2 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config: The ouput configuration structure
+  * @retval None
+  */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx = 0;
+  uint32_t tmpccer = 0;
+  uint32_t tmpcr2 = 0;
+   
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  
+  /* Get the TIMx CCER register value */  
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = TIMx->CR2;
+  
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC2M;
+  tmpccmrx &= ~TIM_CCMR1_CC2S;
+  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8);
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC2P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 4);
+    
+  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+    
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC2NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 4);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC2NE;
+    
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS2;
+    tmpcr2 &= ~TIM_CR2_OIS2N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 2);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 2);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+  
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = OC_Config->Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Time Ouput Compare 3 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config: The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx = 0;
+  uint32_t tmpccer = 0;
+  uint32_t tmpcr2 = 0;   
+
+  /* Disable the Channel 3: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = TIMx->CR2;
+  
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC3M;
+  tmpccmrx &= ~TIM_CCMR2_CC3S;  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC3P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 8);
+    
+  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+    
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC3NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 8);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC3NE;
+    
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS3;
+    tmpcr2 &= ~TIM_CR2_OIS3N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 4);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 4);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+  
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = OC_Config->Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Time Ouput Compare 4 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config: The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx = 0;
+  uint32_t tmpccer = 0;
+  uint32_t tmpcr2 = 0;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = TIMx->CR2;
+  
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC4M;
+  tmpccmrx &= ~TIM_CCMR2_CC4S;
+  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8);
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC4P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 12);
+   
+  /*if((TIMx == TIM1) || (TIMx == TIM8))*/
+  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+  {
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS4;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 6);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR2 */  
+  TIMx->CCMR2 = tmpccmrx;
+    
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = OC_Config->Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge  
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
+  *            @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1 = 0;
+  uint32_t tmpccer = 0;
+  
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+  {
+    tmpccmr1 &= ~TIM_CCMR1_CC1S;
+    tmpccmr1 |= TIM_ICSelection;
+  } 
+  else
+  {
+    tmpccmr1 &= ~TIM_CCMR1_CC1S;
+    tmpccmr1 |= TIM_CCMR1_CC1S_0;
+  }
+ 
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= (TIM_ICFilter << 4);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= TIM_ICPolarity;
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI1.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1 = 0;
+  uint32_t tmpccer = 0;
+  
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;    
+  
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= (TIM_ICFilter << 4);
+  
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= TIM_ICPolarity;
+  
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge   
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
+  *            @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1 = 0;
+  uint32_t tmpccer = 0;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+  
+  /* Select the Input */
+  tmpccmr1 &= ~TIM_CCMR1_CC2S;
+  tmpccmr1 |= (TIM_ICSelection << 8);
+  
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= (TIM_ICFilter << 12);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (TIM_ICPolarity << 4);
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI2.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1 = 0;
+  uint32_t tmpccer = 0;
+  
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+  
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= (TIM_ICFilter << 12);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (TIM_ICPolarity << 4);
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge         
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
+  *            @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2 = 0;
+  uint32_t tmpccer = 0;
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC3S;
+  tmpccmr2 |= TIM_ICSelection;
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC3F;
+  tmpccmr2 |= (TIM_ICFilter << 4);
+
+  /* Select the Polarity and set the CC3E Bit */
+  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+  tmpccer |= (TIM_ICPolarity << 8);
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge     
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
+  *            @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2 = 0;
+  uint32_t tmpccer = 0;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC4S;
+  tmpccmr2 |= (TIM_ICSelection << 8);
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC4F;
+  tmpccmr2 |= (TIM_ICFilter << 12);
+
+  /* Select the Polarity and set the CC4E Bit */
+  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+  tmpccer |= (TIM_ICPolarity << 12);
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer ;
+}
+
+/**
+  * @brief  Selects the Input Trigger source
+  * @param  TIMx to select the TIM peripheral
+  * @param  InputTriggerSource: The Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
+  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM_TS_ETRF: External Trigger input
+  * @retval None
+  */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
+{
+  uint32_t tmpsmcr = 0;
+  
+   /* Get the TIMx SMCR register value */
+   tmpsmcr = TIMx->SMCR;
+   /* Reset the TS Bits */
+   tmpsmcr &= ~TIM_SMCR_TS;
+   /* Set the Input Trigger source and the slave mode*/
+   tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
+   /* Write to TIMx SMCR */
+   TIMx->SMCR = tmpsmcr;
+}
+/**
+  * @brief  Configures the TIMx External Trigger (ETR).
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
+  *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+  uint32_t tmpsmcr = 0;
+
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the ETR Bits */
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+} 
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel: specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_Channel_1: TIM Channel 1
+  *            @arg TIM_Channel_2: TIM Channel 2
+  *            @arg TIM_Channel_3: TIM Channel 3
+  *            @arg TIM_Channel_4: TIM Channel 4
+  * @param  ChannelState: specifies the TIM Channel CCxE bit new state.
+  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. 
+  * @retval None
+  */
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx)); 
+  assert_param(IS_TIM_CHANNELS(Channel));
+
+  tmp = TIM_CCER_CC1E << Channel;
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= ~tmp;
+
+  /* Set or reset the CCxE Bit */ 
+  TIMx->CCER |= (uint32_t)(ChannelState << Channel);
+}
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1378 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_tim.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of TIM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_TIM_H
+#define __STM32F4xx_HAL_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL
+  * @{
+  */
+
+/** @addtogroup TIM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  TIM Time base Configuration Structure definition  
+  */
+typedef struct
+{
+  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_ClockDivision */
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                    reaches zero, an update event is generated and counting restarts
+                                    from the RCR value (N).
+                                    This means in PWM mode that (N+1) corresponds to:
+                                        - the number of PWM periods in edge-aligned mode
+                                        - the number of half PWM period in center-aligned mode
+                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 
+                                     @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_Base_InitTypeDef;
+
+/** 
+  * @brief  TIM Output Compare Configuration Structure definition  
+  */
+
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for TIM1 and TIM8. */
+  
+  uint32_t OCFastMode;   /*!< Specifies the Fast mode state.
+                               This parameter can be a value of @ref TIM_Output_Fast_State
+                               @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OC_InitTypeDef;  
+
+/** 
+  * @brief  TIM One Pulse Mode Configuration Structure definition  
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;   /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  
+} TIM_OnePulse_InitTypeDef;  
+
+
+/** 
+  * @brief  TIM Input Capture Configuration Structure definition  
+  */
+
+typedef struct
+{
+  uint32_t  ICPolarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
+                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t ICFilter;     /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/** 
+  * @brief  TIM Encoder Configuration Structure definition  
+  */
+
+typedef struct
+{
+  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Mode */
+                                  
+  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t IC1Selection;  /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+                                  
+  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t IC2Selection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+/** 
+  * @brief  Clock Configuration Handle Structure definition  
+  */ 
+typedef struct
+{
+  uint32_t ClockSource;     /*!< TIM clock sources. 
+                                 This parameter can be a value of @ref TIM_Clock_Source */ 
+  uint32_t ClockPolarity;   /*!< TIM clock polarity. 
+                                 This parameter can be a value of @ref TIM_Clock_Polarity */
+  uint32_t ClockPrescaler;  /*!< TIM clock prescaler. 
+                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
+  uint32_t ClockFilter;    /*!< TIM clock filter. 
+                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+}TIM_ClockConfigTypeDef;
+
+/** 
+  * @brief  Clear Input Configuration Handle Structure definition  
+  */ 
+typedef struct
+{ 
+  uint32_t ClearInputState;      /*!< TIM clear Input state. 
+                                      This parameter can be ENABLE or DISABLE */  
+  uint32_t ClearInputSource;     /*!< TIM clear Input sources. 
+                                      This parameter can be a value of @ref TIM_ClearInput_Source */ 
+  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity. 
+                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
+  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler. 
+                                      This parameter can be a value of @ref TIM_ClearInput_Prescaler */
+  uint32_t ClearInputFilter;    /*!< TIM Clear Input filter. 
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+}TIM_ClearInputConfigTypeDef;
+
+/** 
+  * @brief  TIM Slave configuration Structure definition  
+  */ 
+typedef struct {
+  uint32_t  SlaveMode;         /*!< Slave mode selection 
+                                  This parameter can be a value of @ref TIM_Slave_Mode */ 
+  uint32_t  InputTrigger;      /*!< Input Trigger source 
+                                  This parameter can be a value of @ref TIM_Trigger_Selection */
+  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity 
+                                  This parameter can be a value of @ref TIM_Trigger_Polarity */
+  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler 
+                                  This parameter can be a value of @ref TIM_Trigger_Prescaler */
+  uint32_t  TriggerFilter;     /*!< Input trigger filter 
+                                  This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  
+
+}TIM_SlaveConfigTypeDef;
+
+/** 
+  * @brief  HAL State structures definition  
+  */ 
+typedef enum
+{
+  HAL_TIM_STATE_RESET             = 0x00,    /*!< Peripheral not yet initialized or disabled  */
+  HAL_TIM_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use    */
+  HAL_TIM_STATE_BUSY              = 0x02,    /*!< An internal process is ongoing              */
+  HAL_TIM_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                               */
+  HAL_TIM_STATE_ERROR             = 0x04     /*!< Reception process is ongoing                */
+}HAL_TIM_StateTypeDef;
+
+/** 
+  * @brief  HAL Active channel structures definition  
+  */ 
+typedef enum
+{
+  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01,    /*!< The active channel is 1     */
+  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02,    /*!< The active channel is 2     */
+  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04,    /*!< The active channel is 3     */
+  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08,    /*!< The active channel is 4     */
+  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00     /*!< All active channels cleared */
+}HAL_TIM_ActiveChannel;
+
+/** 
+  * @brief  TIM Time Base Handle Structure definition  
+  */ 
+typedef struct
+{
+  TIM_TypeDef                 *Instance;     /*!< Register base address             */
+  TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */
+  HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */
+  DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array
+                                             This array is accessed by a @ref DMA_Handle_index */
+  HAL_LockTypeDef             Lock;          /*!< Locking object                    */
+  __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
+}TIM_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants
+  * @{
+  */
+
+/** @defgroup TIM_Input_Channel_Polarity 
+  * @{
+  */
+#define  TIM_INPUTCHANNELPOLARITY_RISING      ((uint32_t)0x00000000)            /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Polarity 
+  * @{
+  */
+#define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED           ((uint32_t)0x0000)                /*!< Polarity for ETR source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Prescaler 
+  * @{
+  */
+#define TIM_ETRPRESCALER_DIV1                 ((uint32_t)0x0000)                /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Counter_Mode 
+  * @{
+  */
+#define TIM_COUNTERMODE_UP                 ((uint32_t)0x0000)
+#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR
+#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0
+#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1
+#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS
+
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP)              || \
+                                   ((MODE) == TIM_COUNTERMODE_DOWN)            || \
+                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
+                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
+                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClockDivision 
+  * @{
+  */
+#define TIM_CLOCKDIVISION_DIV1                       ((uint32_t)0x0000)
+#define TIM_CLOCKDIVISION_DIV2                       (TIM_CR1_CKD_0)
+#define TIM_CLOCKDIVISION_DIV4                       (TIM_CR1_CKD_1)
+
+#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
+                                       ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
+                                       ((DIV) == TIM_CLOCKDIVISION_DIV4))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes 
+  * @{
+  */
+#define TIM_OCMODE_TIMING                   ((uint32_t)0x0000)
+#define TIM_OCMODE_ACTIVE                   (TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_INACTIVE                 (TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M)
+#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_FORCED_INACTIVE          (TIM_CCMR1_OC1M_2)
+
+#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
+                               ((MODE) == TIM_OCMODE_PWM2))
+                              
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING)       || \
+                          ((MODE) == TIM_OCMODE_ACTIVE)           || \
+                          ((MODE) == TIM_OCMODE_INACTIVE)         || \
+                          ((MODE) == TIM_OCMODE_TOGGLE)           || \
+                          ((MODE) == TIM_OCMODE_FORCED_ACTIVE)    || \
+                          ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_State 
+  * @{
+  */
+#define TIM_OUTPUTSTATE_DISABLE            ((uint32_t)0x0000)
+#define TIM_OUTPUTSTATE_ENABLE             (TIM_CCER_CC1E)
+
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
+                                    ((STATE) == TIM_OUTPUTSTATE_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Fast_State 
+  * @{
+  */
+#define TIM_OCFAST_DISABLE                ((uint32_t)0x0000)
+#define TIM_OCFAST_ENABLE                 (TIM_CCMR1_OC1FE)
+
+#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
+                                  ((STATE) == TIM_OCFAST_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_State
+  * @{
+  */
+#define TIM_OUTPUTNSTATE_DISABLE            ((uint32_t)0x0000)
+#define TIM_OUTPUTNSTATE_ENABLE             (TIM_CCER_CC1NE)
+
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
+                                     ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Polarity 
+  * @{
+  */
+#define TIM_OCPOLARITY_HIGH                ((uint32_t)0x0000)
+#define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)
+
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
+                                      ((POLARITY) == TIM_OCPOLARITY_LOW))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Polarity 
+  * @{
+  */
+#define TIM_OCNPOLARITY_HIGH               ((uint32_t)0x0000)
+#define TIM_OCNPOLARITY_LOW                (TIM_CCER_CC1NP)
+
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
+                                       ((POLARITY) == TIM_OCNPOLARITY_LOW))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Idle_State 
+  * @{
+  */
+#define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)
+#define TIM_OCIDLESTATE_RESET              ((uint32_t)0x0000)
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
+                                    ((STATE) == TIM_OCIDLESTATE_RESET))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_N_Idle_State 
+  * @{
+  */
+#define TIM_OCNIDLESTATE_SET               (TIM_CR2_OIS1N)
+#define TIM_OCNIDLESTATE_RESET             ((uint32_t)0x0000)
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
+                                     ((STATE) == TIM_OCNIDLESTATE_RESET))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Channel 
+  * @{
+  */
+#define TIM_CHANNEL_1                      ((uint32_t)0x0000)
+#define TIM_CHANNEL_2                      ((uint32_t)0x0004)
+#define TIM_CHANNEL_3                      ((uint32_t)0x0008)
+#define TIM_CHANNEL_4                      ((uint32_t)0x000C)
+#define TIM_CHANNEL_ALL                    ((uint32_t)0x0018)
+                                 
+#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+                                  ((CHANNEL) == TIM_CHANNEL_2) || \
+                                  ((CHANNEL) == TIM_CHANNEL_3) || \
+                                  ((CHANNEL) == TIM_CHANNEL_4) || \
+                                  ((CHANNEL) == TIM_CHANNEL_ALL))
+                                 
+#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+                                       ((CHANNEL) == TIM_CHANNEL_2))
+
+#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+                                      ((CHANNEL) == TIM_CHANNEL_2))
+                                      
+#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+                                                ((CHANNEL) == TIM_CHANNEL_2) || \
+                                                ((CHANNEL) == TIM_CHANNEL_3))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Polarity 
+  * @{
+  */
+#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING
+#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING
+#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE
+
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING)   || \
+                                      ((POLARITY) == TIM_ICPOLARITY_FALLING)  || \
+                                      ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Selection 
+  * @{
+  */
+#define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1, 2, 3 or 4 is selected to be 
+                                                                     connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                     connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC                (TIM_CCMR1_CC1S)     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
+                                        ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
+                                        ((SELECTION) == TIM_ICSELECTION_TRC))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Prescaler 
+  * @{
+  */
+#define TIM_ICPSC_DIV1                     ((uint32_t)0x0000)       /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */
+#define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */
+#define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */
+
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV8))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_One_Pulse_Mode 
+  * @{
+  */
+#define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)
+#define TIM_OPMODE_REPETITIVE              ((uint32_t)0x0000)
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
+                               ((MODE) == TIM_OPMODE_REPETITIVE))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Mode 
+  * @{
+  */
+#define TIM_ENCODERMODE_TI1                (TIM_SMCR_SMS_0)
+#define TIM_ENCODERMODE_TI2                (TIM_SMCR_SMS_1)
+#define TIM_ENCODERMODE_TI12               (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
+                                   ((MODE) == TIM_ENCODERMODE_TI2) || \
+                                   ((MODE) == TIM_ENCODERMODE_TI12))   
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Interrupt_definition 
+  * @{
+  */ 
+#define TIM_IT_UPDATE           (TIM_DIER_UIE)
+#define TIM_IT_CC1              (TIM_DIER_CC1IE)
+#define TIM_IT_CC2              (TIM_DIER_CC2IE)
+#define TIM_IT_CC3              (TIM_DIER_CC3IE)
+#define TIM_IT_CC4              (TIM_DIER_CC4IE)
+#define TIM_IT_COM              (TIM_DIER_COMIE)
+#define TIM_IT_TRIGGER          (TIM_DIER_TIE)
+#define TIM_IT_BREAK            (TIM_DIER_BIE)
+
+#define IS_TIM_IT(IT) ((((IT) & 0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000))
+
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE)  || \
+                           ((IT) == TIM_IT_CC1)     || \
+                           ((IT) == TIM_IT_CC2)     || \
+                           ((IT) == TIM_IT_CC3)     || \
+                           ((IT) == TIM_IT_CC4)     || \
+                           ((IT) == TIM_IT_COM)     || \
+                           ((IT) == TIM_IT_TRIGGER) || \
+                           ((IT) == TIM_IT_BREAK))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_sources 
+  * @{
+  */
+#define TIM_DMA_UPDATE                     (TIM_DIER_UDE)
+#define TIM_DMA_CC1                        (TIM_DIER_CC1DE)
+#define TIM_DMA_CC2                        (TIM_DIER_CC2DE)
+#define TIM_DMA_CC3                        (TIM_DIER_CC3DE)
+#define TIM_DMA_CC4                        (TIM_DIER_CC4DE)
+#define TIM_DMA_COM                        (TIM_DIER_COMDE)
+#define TIM_DMA_TRIGGER                    (TIM_DIER_TDE)
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Event_Source 
+  * @{
+  */
+#define TIM_EventSource_Update              TIM_EGR_UG  
+#define TIM_EventSource_CC1                 TIM_EGR_CC1G
+#define TIM_EventSource_CC2                 TIM_EGR_CC2G
+#define TIM_EventSource_CC3                 TIM_EGR_CC3G
+#define TIM_EventSource_CC4                 TIM_EGR_CC4G
+#define TIM_EventSource_COM                 TIM_EGR_COMG
+#define TIM_EventSource_Trigger             TIM_EGR_TG  
+#define TIM_EventSource_Break               TIM_EGR_BG  
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Flag_definition 
+  * @{
+  */
+#define TIM_FLAG_UPDATE                    (TIM_SR_UIF)
+#define TIM_FLAG_CC1                       (TIM_SR_CC1IF)
+#define TIM_FLAG_CC2                       (TIM_SR_CC2IF)
+#define TIM_FLAG_CC3                       (TIM_SR_CC3IF)
+#define TIM_FLAG_CC4                       (TIM_SR_CC4IF)
+#define TIM_FLAG_COM                       (TIM_SR_COMIF)
+#define TIM_FLAG_TRIGGER                   (TIM_SR_TIF)
+#define TIM_FLAG_BREAK                     (TIM_SR_BIF)
+#define TIM_FLAG_CC1OF                     (TIM_SR_CC1OF)
+#define TIM_FLAG_CC2OF                     (TIM_SR_CC2OF)
+#define TIM_FLAG_CC3OF                     (TIM_SR_CC3OF)
+#define TIM_FLAG_CC4OF                     (TIM_SR_CC4OF)
+
+#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \
+                           ((FLAG) == TIM_FLAG_CC1)     || \
+                           ((FLAG) == TIM_FLAG_CC2)     || \
+                           ((FLAG) == TIM_FLAG_CC3)     || \
+                           ((FLAG) == TIM_FLAG_CC4)     || \
+                           ((FLAG) == TIM_FLAG_COM)     || \
+                           ((FLAG) == TIM_FLAG_TRIGGER) || \
+                           ((FLAG) == TIM_FLAG_BREAK)   || \
+                           ((FLAG) == TIM_FLAG_CC1OF)   || \
+                           ((FLAG) == TIM_FLAG_CC2OF)   || \
+                           ((FLAG) == TIM_FLAG_CC3OF)   || \
+                           ((FLAG) == TIM_FLAG_CC4OF))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Source 
+  * @{
+  */
+#define	TIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1) 
+#define	TIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0) 
+#define	TIM_CLOCKSOURCE_ITR0        ((uint32_t)0x0000)
+#define	TIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)
+#define	TIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)
+#define	TIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
+#define	TIM_CLOCKSOURCE_TI1ED       (TIM_SMCR_TS_2)
+#define	TIM_CLOCKSOURCE_TI1         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
+#define	TIM_CLOCKSOURCE_TI2         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
+#define	TIM_CLOCKSOURCE_ETRMODE1    (TIM_SMCR_TS)
+
+#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
+                                   ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
+                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR0)     || \
+                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR1)     || \
+                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR2)     || \
+                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR3)     || \
+                                   ((CLOCK) == TIM_CLOCKSOURCE_TI1ED)    || \
+                                   ((CLOCK) == TIM_CLOCKSOURCE_TI1)      || \
+                                   ((CLOCK) == TIM_CLOCKSOURCE_TI2)      || \
+                                   ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Polarity 
+  * @{
+  */
+#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED          /*!< Polarity for ETRx clock sources */ 
+#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED       /*!< Polarity for ETRx clock sources */ 
+#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING   /*!< Polarity for TIx clock sources */ 
+#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */ 
+#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */ 
+
+#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED)    || \
+                                        ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+                                        ((POLARITY) == TIM_CLOCKPOLARITY_RISING)      || \
+                                        ((POLARITY) == TIM_CLOCKPOLARITY_FALLING)     || \
+                                        ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Prescaler 
+  * @{
+  */
+#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
+#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+
+#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
+                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
+                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
+                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) 
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Filter
+  * @{
+  */
+#define IS_TIM_CLOCKFILTER(ICFILTER)      ((ICFILTER) <= 0xF) 
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Source
+  * @{
+  */
+#define TIM_CLEARINPUTSOURCE_ETR           ((uint32_t)0x0001) 
+#define TIM_CLEARINPUTSOURCE_NONE          ((uint32_t)0x0000)
+
+#define IS_TIM_CLEARINPUT_SOURCE(SOURCE)  (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
+                                         ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) 
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Polarity
+  * @{
+  */
+#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED                    /*!< Polarity for ETRx pin */ 
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED                 /*!< Polarity for ETRx pin */ 
+#define IS_TIM_CLEARINPUT_POLARITY(POLARITY)   (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+                                               ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Prescaler
+  * @{
+  */
+#define TIM_CLEARINPUTPRESCALER_DIV1                    TIM_ETRPRESCALER_DIV1      /*!< No prescaler is used */
+#define TIM_CLEARINPUTPRESCALER_DIV2                    TIM_ETRPRESCALER_DIV2      /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4                    TIM_ETRPRESCALER_DIV4      /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8                    TIM_ETRPRESCALER_DIV8        /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER)   (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+                                                 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+                                                 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+                                                 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Filter
+  * @{
+  */
+#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Slave_Mode 
+  * @{
+  */
+#define TIM_SLAVEMODE_DISABLE              ((uint32_t)0x0000)
+#define TIM_SLAVEMODE_RESET                ((uint32_t)0x0004)
+#define TIM_SLAVEMODE_GATED                ((uint32_t)0x0005)
+#define TIM_SLAVEMODE_TRIGGER              ((uint32_t)0x0006)
+#define TIM_SLAVEMODE_EXTERNAL1            ((uint32_t)0x0007)
+
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
+                                 ((MODE) == TIM_SLAVEMODE_GATED) || \
+                                 ((MODE) == TIM_SLAVEMODE_RESET) || \
+                                 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
+                                 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Selection 
+  * @{
+  */
+#define TIM_TS_ITR0                        ((uint32_t)0x0000)
+#define TIM_TS_ITR1                        ((uint32_t)0x0010)
+#define TIM_TS_ITR2                        ((uint32_t)0x0020)
+#define TIM_TS_ITR3                        ((uint32_t)0x0030)
+#define TIM_TS_TI1F_ED                     ((uint32_t)0x0040)
+#define TIM_TS_TI1FP1                      ((uint32_t)0x0050)
+#define TIM_TS_TI2FP2                      ((uint32_t)0x0060)
+#define TIM_TS_ETRF                        ((uint32_t)0x0070)
+#define TIM_TS_NONE                        ((uint32_t)0xFFFF)
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+                                             ((SELECTION) == TIM_TS_ITR1) || \
+                                             ((SELECTION) == TIM_TS_ITR2) || \
+                                             ((SELECTION) == TIM_TS_ITR3) || \
+                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
+                                             ((SELECTION) == TIM_TS_TI1FP1) || \
+                                             ((SELECTION) == TIM_TS_TI2FP2) || \
+                                             ((SELECTION) == TIM_TS_ETRF))
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+                                                      ((SELECTION) == TIM_TS_ITR1) || \
+                                                      ((SELECTION) == TIM_TS_ITR2) || \
+                                                      ((SELECTION) == TIM_TS_ITR3))
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+                                                           ((SELECTION) == TIM_TS_ITR1) || \
+                                                           ((SELECTION) == TIM_TS_ITR2) || \
+                                                           ((SELECTION) == TIM_TS_ITR3) || \
+                                                           ((SELECTION) == TIM_TS_NONE))
+/**
+  * @}
+  */  
+
+/** @defgroup TIM_Trigger_Polarity 
+  * @{
+  */
+#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx trigger sources */ 
+#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx trigger sources */ 
+#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 
+#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 
+#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 
+
+#define IS_TIM_TRIGGERPOLARITY(POLARITY)     (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
+                                              ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+                                              ((POLARITY) == TIM_TRIGGERPOLARITY_RISING     ) || \
+                                              ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING    ) || \
+                                              ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Prescaler 
+  * @{
+  */
+#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
+#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+
+#define IS_TIM_TRIGGERPRESCALER(PRESCALER)  (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
+                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
+                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
+                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) 
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Filter
+  * @{
+  */
+#define IS_TIM_TRIGGERFILTER(ICFILTER)     ((ICFILTER) <= 0xF) 
+/**
+  * @}
+  */
+
+  /** @defgroup TIM_TI1_Selection
+  * @{
+  */
+#define TIM_TI1SELECTION_CH1                ((uint32_t)0x0000)
+#define TIM_TI1SELECTION_XORCOMBINATION     (TIM_CR2_TI1S)
+
+#define IS_TIM_TI1SELECTION(TI1SELECTION)   (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
+                                             ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_DMA_Base_address 
+  * @{
+  */
+#define TIM_DMABase_CR1                    (0x00000000)
+#define TIM_DMABase_CR2                    (0x00000001)
+#define TIM_DMABase_SMCR                   (0x00000002)
+#define TIM_DMABase_DIER                   (0x00000003)
+#define TIM_DMABase_SR                     (0x00000004)
+#define TIM_DMABase_EGR                    (0x00000005)
+#define TIM_DMABase_CCMR1                  (0x00000006)
+#define TIM_DMABase_CCMR2                  (0x00000007)
+#define TIM_DMABase_CCER                   (0x00000008)
+#define TIM_DMABase_CNT                    (0x00000009)
+#define TIM_DMABase_PSC                    (0x0000000A)
+#define TIM_DMABase_ARR                    (0x0000000B)
+#define TIM_DMABase_RCR                    (0x0000000C)
+#define TIM_DMABase_CCR1                   (0x0000000D)
+#define TIM_DMABase_CCR2                   (0x0000000E)
+#define TIM_DMABase_CCR3                   (0x0000000F)
+#define TIM_DMABase_CCR4                   (0x00000010)
+#define TIM_DMABase_BDTR                   (0x00000011)
+#define TIM_DMABase_DCR                    (0x00000012)
+#define TIM_DMABase_OR                     (0x00000013)
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+                               ((BASE) == TIM_DMABase_CR2) || \
+                               ((BASE) == TIM_DMABase_SMCR) || \
+                               ((BASE) == TIM_DMABase_DIER) || \
+                               ((BASE) == TIM_DMABase_SR) || \
+                               ((BASE) == TIM_DMABase_EGR) || \
+                               ((BASE) == TIM_DMABase_CCMR1) || \
+                               ((BASE) == TIM_DMABase_CCMR2) || \
+                               ((BASE) == TIM_DMABase_CCER) || \
+                               ((BASE) == TIM_DMABase_CNT) || \
+                               ((BASE) == TIM_DMABase_PSC) || \
+                               ((BASE) == TIM_DMABase_ARR) || \
+                               ((BASE) == TIM_DMABase_RCR) || \
+                               ((BASE) == TIM_DMABase_CCR1) || \
+                               ((BASE) == TIM_DMABase_CCR2) || \
+                               ((BASE) == TIM_DMABase_CCR3) || \
+                               ((BASE) == TIM_DMABase_CCR4) || \
+                               ((BASE) == TIM_DMABase_BDTR) || \
+                               ((BASE) == TIM_DMABase_DCR) || \
+                               ((BASE) == TIM_DMABase_OR))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_DMA_Burst_Length 
+  * @{
+  */
+#define TIM_DMABurstLength_1Transfer           (0x00000000)
+#define TIM_DMABurstLength_2Transfers          (0x00000100)
+#define TIM_DMABurstLength_3Transfers          (0x00000200)
+#define TIM_DMABurstLength_4Transfers          (0x00000300)
+#define TIM_DMABurstLength_5Transfers          (0x00000400)
+#define TIM_DMABurstLength_6Transfers          (0x00000500)
+#define TIM_DMABurstLength_7Transfers          (0x00000600)
+#define TIM_DMABurstLength_8Transfers          (0x00000700)
+#define TIM_DMABurstLength_9Transfers          (0x00000800)
+#define TIM_DMABurstLength_10Transfers         (0x00000900)
+#define TIM_DMABurstLength_11Transfers         (0x00000A00)
+#define TIM_DMABurstLength_12Transfers         (0x00000B00)
+#define TIM_DMABurstLength_13Transfers         (0x00000C00)
+#define TIM_DMABurstLength_14Transfers         (0x00000D00)
+#define TIM_DMABurstLength_15Transfers         (0x00000E00)
+#define TIM_DMABurstLength_16Transfers         (0x00000F00)
+#define TIM_DMABurstLength_17Transfers         (0x00001000)
+#define TIM_DMABurstLength_18Transfers         (0x00001100)
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
+                                   ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_18Transfers))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Filer_Value 
+  * @{
+  */
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Handle_index 
+  * @{
+  */
+#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0)       /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1                   ((uint16_t) 0x1)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2                   ((uint16_t) 0x2)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3                   ((uint16_t) 0x3)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4                   ((uint16_t) 0x4)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x5)       /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x6)       /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+  * @}
+  */ 
+
+/** @defgroup Channel_CC_State 
+  * @{
+  */
+#define TIM_CCx_ENABLE                   ((uint32_t)0x0001)
+#define TIM_CCx_DISABLE                  ((uint32_t)0x0000)
+#define TIM_CCxN_ENABLE                  ((uint32_t)0x0004)
+#define TIM_CCxN_DISABLE                 ((uint32_t)0x0000)
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */   
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset TIM handle state
+  * @param  __HANDLE__: TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+
+/**
+  * @brief  Enable the TIM peripheral.
+  * @param  __HANDLE__: TIM handle
+  * @retval None
+ */
+#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+  * @brief  Enable the TIM main Output.
+  * @param  __HANDLE__: TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+   channels have been disabled */
+#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+
+/**
+  * @brief  Disable the TIM peripheral.
+  * @param  __HANDLE__: TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+                        do { \
+                          if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
+                          { \
+                            if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
+                            { \
+                              (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+                            } \
+                          } \
+                        } while(0)
+
+/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
+   channels have been disabled */
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__: TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+                        do { \
+                          if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
+                          { \
+                            if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
+                            { \
+                              (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+                            } \
+                          } \
+                        } while(0)
+
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+
+#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->SR &= ~(__INTERRUPT__))
+
+#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__)            (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC |= (__PRESC__))
+
+#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
+
+#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
+
+/**
+  * @brief  Sets the TIM Capture Compare Register value on runtime without
+  *         calling another time ConfigChannel function.
+  * @param  __HANDLE__: TIM handle.
+  * @param  __CHANNEL__ : TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __COMPARE__: specifies the Capture Compare register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
+(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
+
+/**
+  * @brief  Gets the TIM Capture Compare Register value on runtime
+  * @param  __HANDLE__: TIM handle.
+  * @param  __CHANNEL__ : TIM Channel associated with the capture compare register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
+  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
+  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
+  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
+  * @retval None
+  */
+#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
+  (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
+
+/**
+  * @brief  Sets the TIM Counter Register value on runtime.
+  * @param  __HANDLE__: TIM handle.
+  * @param  __COUNTER__: specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+  * @brief  Gets the TIM Counter Register value on runtime.
+  * @param  __HANDLE__: TIM handle.
+  * @retval None
+  */
+#define __HAL_TIM_GetCounter(__HANDLE__) ((__HANDLE__)->Instance->CNT)
+
+/**
+  * @brief  Sets the TIM Autoreload Register value on runtime without calling 
+  *         another time any Init function.
+  * @param  __HANDLE__: TIM handle.
+  * @param  __AUTORELOAD__: specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__)                  \
+                        do{                                                  \
+                            (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
+                            (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
+                          } while(0)
+/**
+  * @brief  Gets the TIM Autoreload Register value on runtime
+  * @param  __HANDLE__: TIM handle.
+  * @retval None
+  */
+#define __HAL_TIM_GetAutoreload(__HANDLE__) ((__HANDLE__)->Instance->ARR)
+
+/**
+  * @brief  Sets the TIM Clock Division value on runtime without calling 
+  *         another time any Init function. 
+  * @param  __HANDLE__: TIM handle.
+  * @param  __CKD__: specifies the clock division value.
+  *          This parameter can be one of the following value:
+  *            @arg TIM_CLOCKDIVISION_DIV1
+  *            @arg TIM_CLOCKDIVISION_DIV2
+  *            @arg TIM_CLOCKDIVISION_DIV4
+  * @retval None
+  */
+#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
+                        do{                                                             \
+                              (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
+                              (__HANDLE__)->Instance->CR1 |= (__CKD__);                 \
+                              (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
+                          } while(0)
+/**
+  * @brief  Gets the TIM Clock Division value on runtime
+  * @param  __HANDLE__: TIM handle.
+  * @retval None
+  */
+#define __HAL_TIM_GetClockDivision(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+  * @brief  Sets the TIM Input Capture prescaler on runtime without calling 
+  *         another time HAL_TIM_IC_ConfigChannel() function.
+  * @param  __HANDLE__: TIM handle.
+  * @param  __CHANNEL__ : TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __ICPSC__: specifies the Input Capture4 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
+                        do{                                                    \
+                              __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__));  \
+                              __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+                          } while(0)
+
+/**
+  * @brief  Gets the TIM Input Capture prescaler on runtime
+  * @param  __HANDLE__: TIM handle.
+  * @param  __CHANNEL__ : TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+  * @retval None
+  */
+#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__)  \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
+/**
+  * @}
+  */
+
+/* Include TIM HAL Extension module */
+#include "stm32f4xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+
+/* Timer Output Compare functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Timer PWM functions *********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Timer Input Capture functions ***********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Timer One Pulse functions ***************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Timer Encoder functions *****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Interrupt Handler functions  **********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+
+/* Control functions  *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);    
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+
+/* Peripheral State functions  **************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
+void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_TIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1844 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_tim_ex.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Timer extension peripheral:
+  *           + Time Hall Sensor Interface Initialization
+  *           + Time Hall Sensor Interface Start
+  *           + Time Complementary signal bread and dead time configuration  
+  *           + Time Master and Slave synchronization configuration
+  @verbatim 
+  ==============================================================================
+                      ##### TIMER Extended features #####
+  ==============================================================================
+  [..] 
+    The Timer Extension features include: 
+    (#) Complementary outputs with programmable dead-time for :
+        (++) Input Capture
+        (++) Output Compare
+        (++) PWM generation (Edge and Center-aligned Mode)
+        (++) One-pulse mode output
+    (#) Synchronization circuit to control the timer with external signals and to 
+        interconnect several timers together.
+    (#) Break input to put the timer output signals in reset state or in a known state.
+    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for 
+        positioning purposes                
+   
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+     (#) Initialize the TIM low level resources by implementing the following functions 
+         depending from feature used :
+           (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
+           (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
+           (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+           (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
+           
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); 
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+                 __GPIOx_CLK_ENABLE();   
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();  
+
+     (#) The external Clock can be configured, if needed (the default clock is the 
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before 
+         any start function.
+  
+    (#) Configure the TIM in the desired functioning mode using one of the 
+        initialization function of this driver:
+        (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the 
+             Timer Hall Sensor Interface and the commutation event with the corresponding 
+             Interrupt and DMA request if needed (Note that One Timer is used to interface 
+             with the Hall sensor Interface and another Timer should be used to use 
+             the commutation event).
+
+    (#) Activate the TIM peripheral using one of the start functions: 
+           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
+           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
+           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
+
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIMEx 
+  * @brief TIM HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);    
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup TIMEx_Private_Functions
+  * @{
+  */
+
+/** @defgroup TIMEx_Group1 Timer Hall Sensor functions 
+ *  @brief    Timer Hall Sensor functions 
+ *
+@verbatim    
+  ==============================================================================
+                      ##### Timer Hall Sensor functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to:
+    (+) Initialize and configure TIM HAL Sensor. 
+    (+) De-initialize TIM HAL Sensor.
+    (+) Start the Hall Sensor Interface.
+    (+) Stop the Hall Sensor Interface.
+    (+) Start the Hall Sensor Interface and enable interrupts.
+    (+) Stop the Hall Sensor Interface and disable interrupts.
+    (+) Start the Hall Sensor Interface and enable DMA transfers.
+    (+) Stop the Hall Sensor Interface and disable DMA transfers.
+ 
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Hall Sensor Interface and create the associated handle.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  sConfig: TIM Hall Sensor configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
+{
+  TIM_OC_InitTypeDef OC_Config;
+    
+  /* Check the TIM handle allocation */
+  if(htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+  /* Set the TIM state */
+  htim->State= HAL_TIM_STATE_BUSY;
+  
+  /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+  HAL_TIMEx_HallSensor_MspInit(htim);
+  
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+  
+  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
+  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+  
+  /* Reset the IC1PSC Bits */
+  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+  /* Set the IC1PSC value */
+  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+  
+  /* Enable the Hall sensor interface (XOR function of the three inputs) */
+  htim->Instance->CR2 |= TIM_CR2_TI1S;
+  
+  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+  htim->Instance->SMCR &= ~TIM_SMCR_TS;
+  htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+  
+  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */  
+  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+  
+  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+  OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+  OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+  OC_Config.OCMode = TIM_OCMODE_PWM2;
+  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+  OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+  OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+  OC_Config.Pulse = sConfig->Commutation_Delay; 
+    
+  TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+  
+  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+    register to 101 */
+  htim->Instance->CR2 &= ~TIM_CR2_MMS;
+  htim->Instance->CR2 |= TIM_TRGO_OC2REF; 
+  
+  /* Initialize the TIM state*/
+  htim->State= HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Hall Sensor interface  
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+  
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+    
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIMEx_HallSensor_MspDeInit(htim);
+    
+  /* Change TIM state */  
+  htim->State = HAL_TIM_STATE_RESET; 
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Hall Sensor MSP.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Hall Sensor MSP.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  
+  /* Enable the Input Capture channels 1
+    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 
+  
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall sensor Interface.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  
+  /* Disable the Input Capture channels 1, 2 and 3
+    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  
+  /* Enable the capture compare Interrupts 1 event */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+  
+  /* Enable the Input Capture channels 1
+    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);  
+  
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  
+  /* Disable the Input Capture channels 1
+    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
+  
+  /* Disable the capture compare Interrupts event */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+  
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  pData: The destination Buffer address.
+  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  
+   if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if(((uint32_t)pData == 0 ) && (Length > 0)) 
+    {
+      return HAL_ERROR;                                    
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  /* Enable the Input Capture channels 1
+    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 
+  
+  /* Set the DMA Input Capture 1 Callback */
+  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;     
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+  
+  /* Enable the DMA Stream for Capture 1*/
+  HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);    
+  
+  /* Enable the capture compare 1 Interrupt */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ 
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  
+  /* Disable the Input Capture channels 1
+    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
+ 
+  
+  /* Disable the capture compare Interrupts 1 event */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ 
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIMEx_Group2 Timer Complementary Output Compare functions
+ *  @brief    Timer Complementary Output Compare functions 
+ *
+@verbatim   
+  ==============================================================================
+              ##### Timer Complementary Output Compare functions #####
+  ==============================================================================  
+  [..]  
+    This section provides functions allowing to:
+    (+) Start the Complementary Output Compare/PWM.
+    (+) Stop the Complementary Output Compare/PWM.
+    (+) Start the Complementary Output Compare/PWM and enable interrupts.
+    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+               
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Starts the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.  
+  * @param  Channel: TIM Channel to be enabled.
+  *          This parameter can be one of the following values:
+  *            TIM_CHANNEL_1/
+  *            TIM_CHANNEL_2/
+  *            TIM_CHANNEL_3/
+  *            TIM_CHANNEL_4
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
+  
+     /* Enable the Capture compare channel N */
+     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+    
+  /* Enable the Main Ouput */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+} 
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channel to be disabled.
+  *          This parameter can be one of the following values:
+  *            TIM_CHANNEL_1/
+  *            TIM_CHANNEL_2/
+  *            TIM_CHANNEL_3/
+  *            TIM_CHANNEL_4
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
+  
+    /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+    
+  /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+} 
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode 
+  *         on the complementary output.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channel to be enabled.
+  *          This parameter can be one of the following values:
+  *            TIM_CHANNEL_1/
+  *            TIM_CHANNEL_2/
+  *            TIM_CHANNEL_3/
+  *            TIM_CHANNEL_4
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
+  
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {       
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+    
+    default:
+    break;
+  } 
+  
+     /* Enable the Capture compare channel N */
+     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+    
+  /* Enable the Main Ouput */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+} 
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode 
+  *         on the complementary output.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channel to be disabled.
+  *          This parameter can be one of the following values:
+  *            TIM_CHANNEL_1/
+  *            TIM_CHANNEL_2/
+  *            TIM_CHANNEL_3/
+  *            TIM_CHANNEL_4
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
+  
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {       
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+    
+    default:
+    break; 
+  }
+    
+     /* Disable the Capture compare channel N */
+     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+    
+  /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+} 
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode 
+  *         on the complementary output.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channel to be enabled.
+  *          This parameter can be one of the following values:
+  *            TIM_CHANNEL_1/
+  *            TIM_CHANNEL_2/
+  *            TIM_CHANNEL_3/
+  *            TIM_CHANNEL_4
+  * @param  pData: The source Buffer address.
+  * @param  Length: The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
+  
+  if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if(((uint32_t)pData == 0 ) && (Length > 0)) 
+    {
+      return HAL_ERROR;                                    
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }    
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {      
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+      
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+      
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+{
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+      
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+     /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+      
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+    
+    default:
+    break;
+  }
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+  
+  /* Enable the Main Ouput */
+  __HAL_TIM_MOE_ENABLE(htim);
+  
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim); 
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode 
+  *         on the complementary output.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channel to be disabled.
+  *          This parameter can be one of the following values:
+  *            TIM_CHANNEL_1/
+  *            TIM_CHANNEL_2/
+  *            TIM_CHANNEL_3/
+  *            TIM_CHANNEL_4
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
+  
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {       
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+    
+    default:
+    break;
+  } 
+  
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+  
+  /* Disable the Main Ouput */
+  __HAL_TIM_MOE_DISABLE(htim);
+  
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIMEx_Group3 Timer Complementary PWM functions
+ *  @brief    Timer Complementary PWM functions 
+ *
+@verbatim   
+  ==============================================================================
+                 ##### Timer Complementary PWM functions #####
+  ==============================================================================  
+  [..]  
+    This section provides functions allowing to:
+    (+) Start the Complementary PWM.
+    (+) Stop the Complementary PWM.
+    (+) Start the Complementary PWM and enable interrupts.
+    (+) Stop the Complementary PWM and disable interrupts.
+    (+) Start the Complementary PWM and enable DMA transfers.
+    (+) Stop the Complementary PWM and disable DMA transfers.
+    (+) Start the Complementary Input Capture measurement.
+    (+) Stop the Complementary Input Capture.
+    (+) Start the Complementary Input Capture and enable interrupts.
+    (+) Stop the Complementary Input Capture and disable interrupts.
+    (+) Start the Complementary Input Capture and enable DMA transfers.
+    (+) Stop the Complementary Input Capture and disable DMA transfers.
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+               
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the PWM signal generation on the complementary output.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channel to be enabled.
+  *          This parameter can be one of the following values:
+  *            TIM_CHANNEL_1/
+  *            TIM_CHANNEL_2/
+  *            TIM_CHANNEL_3/
+  *            TIM_CHANNEL_4
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
+  
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+  
+  /* Enable the Main Ouput */
+  __HAL_TIM_MOE_ENABLE(htim);
+  
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+} 
+
+/**
+  * @brief  Stops the PWM signal generation on the complementary output.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channel to be disabled.
+  *          This parameter can be one of the following values:
+  *            TIM_CHANNEL_1/
+  *            TIM_CHANNEL_2/
+  *            TIM_CHANNEL_3/
+  *            TIM_CHANNEL_4
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
+  
+  /* Disable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);  
+  
+  /* Disable the Main Ouput */
+  __HAL_TIM_MOE_DISABLE(htim);
+  
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+} 
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode on the 
+  *         complementary output.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channel to be disabled.
+  *          This parameter can be one of the following values:
+  *            TIM_CHANNEL_1/
+  *            TIM_CHANNEL_2/
+  *            TIM_CHANNEL_3/
+  *            TIM_CHANNEL_4
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
+  
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {       
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+    
+    default:
+    break;
+  } 
+  
+  /* Enable the TIM Break interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+  
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+  
+  /* Enable the Main Ouput */
+  __HAL_TIM_MOE_ENABLE(htim);
+  
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+} 
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode on the 
+  *         complementary output.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channel to be disabled.
+  *          This parameter can be one of the following values:
+  *            TIM_CHANNEL_1/
+  *            TIM_CHANNEL_2/
+  *            TIM_CHANNEL_3/
+  *            TIM_CHANNEL_4
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {       
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+    }
+    break;
+    
+    default:
+    break; 
+  }
+  
+  /* Disable the TIM Break interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+  
+  /* Disable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+  
+  /* Disable the Main Ouput */
+  __HAL_TIM_MOE_DISABLE(htim);
+  
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+} 
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode on the 
+  *         complementary output
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channel to be enabled.
+  *          This parameter can be one of the following values:
+  *            TIM_CHANNEL_1/
+  *            TIM_CHANNEL_2/
+  *            TIM_CHANNEL_3/
+  *            TIM_CHANNEL_4
+  * @param  pData: The source Buffer address.
+  * @param  Length: The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
+  
+  if((htim->State == HAL_TIM_STATE_BUSY))
+  {
+     return HAL_BUSY;
+  }
+  else if((htim->State == HAL_TIM_STATE_READY))
+  {
+    if(((uint32_t)pData == 0 ) && (Length > 0)) 
+    {
+      return HAL_ERROR;                                    
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }    
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {      
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+      
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+      
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+      
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+     /* Set the DMA Period elapsed callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
+     
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
+      
+      /* Enable the DMA Stream */
+      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+      
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+    
+    default:
+    break;
+  }
+
+  /* Enable the complementary PWM output  */
+     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+    
+  /* Enable the Main Ouput */
+    __HAL_TIM_MOE_ENABLE(htim);
+  
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim); 
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
+  *         output
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  Channel: TIM Channel to be disabled.
+  *          This parameter can be one of the following values:
+  *            TIM_CHANNEL_1/
+  *            TIM_CHANNEL_2/
+  *            TIM_CHANNEL_3/
+  *            TIM_CHANNEL_4
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
+  
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {       
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    }
+    break;
+    
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    }
+    break;
+    
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+    }
+    break;
+    
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+    }
+    break;
+    
+    default:
+    break;
+  } 
+  
+  /* Disable the complementary PWM output */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+     
+  /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+  
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIMEx_Group4 Timer Complementary One Pulse functions
+ *  @brief    Timer Complementary One Pulse functions 
+ *
+@verbatim   
+  ==============================================================================
+                ##### Timer Complementary One Pulse functions #####
+  ==============================================================================  
+  [..]  
+    This section provides functions allowing to:
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+               
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation on the complemetary 
+  *         output.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  OutputChannel: TIM Channel to be enabled.
+  *          This parameter can be one of the following values:
+  *            TIM_CHANNEL_1 /
+  *            IM_CHANNEL_2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+  {
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); 
+  
+  /* Enable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); 
+  
+  /* Enable the Main Ouput */
+  __HAL_TIM_MOE_ENABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation on the complementary 
+  *         output.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  OutputChannel: TIM Channel to be disabled.
+  *          This parameter can be one of the following values:
+  *            TIM_CHANNEL_1 / TIM_CHANNEL_2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); 
+
+  /* Disable the complementary One Pulse output */
+    TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+  
+  /* Disable the Main Ouput */
+    __HAL_TIM_MOE_DISABLE(htim);
+  
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim); 
+   
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  OutputChannel: TIM Channel to be enabled.
+  *          This parameter can be one of the following values:
+  *            TIM_CHANNEL_1 / IM_CHANNEL_2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); 
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+  
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+  
+  /* Enable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); 
+  
+  /* Enable the Main Ouput */
+  __HAL_TIM_MOE_ENABLE(htim);
+  
+  /* Return function status */
+  return HAL_OK;
+  } 
+  
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  OutputChannel: TIM Channel to be disabled.
+  *          This parameter can be one of the following values:
+  *            TIM_CHANNEL_1 / IM_CHANNEL_2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); 
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+  
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  
+  /* Disable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+  
+  /* Disable the Main Ouput */
+  __HAL_TIM_MOE_DISABLE(htim);
+  
+  /* Disable the Peripheral */
+   __HAL_TIM_DISABLE(htim);  
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+/** @defgroup TIMEx_Group5 Peripheral Control functions
+ *  @brief   	Peripheral Control functions 
+ *
+@verbatim   
+  ==============================================================================
+                    ##### Peripheral Control functions #####
+  ==============================================================================  
+  [..]  
+    This section provides functions allowing to:
+    (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. 
+    (+) Configure External Clock source.
+    (+) Configure Complementary channels, break features and dead time.
+    (+) Configure Master and the Slave synchronization.
+    (+) Configure the commutation event in case of use of the Hall sensor interface.
+    (+) Configure the DMA Burst Mode.
+      
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Configure the TIM commutation event sequence.
+  * @note  This function is mandatory to use the commutation event in order to 
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer) 
+  *        configured in Hall sensor interface, this interface Timer will generate the 
+  *        commutation at its TRGO output (connected to Timer used in this function) each time 
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
+  *          This parameter can be one of the following values:
+  *            TIM_TS_ITR0 /
+  *            TIM_TS_ITR1 /
+  *            TIM_TS_ITR2 /
+  *            TIM_TS_ITR3 /
+  *            TIM_TS_NONE
+  * @param  CommutationSource: the Commutation Event source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+  
+  __HAL_LOCK(htim);
+  
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+  {    
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+    
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+    
+  __HAL_UNLOCK(htim);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with interrupt.
+  * @note  This function is mandatory to use the commutation event in order to 
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer) 
+  *        configured in Hall sensor interface, this interface Timer will generate the 
+  *        commutation at its TRGO output (connected to Timer used in this function) each time 
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
+  *          This parameter can be one of the following values:
+  *            TIM_TS_ITR0 /
+  *            TIM_TS_ITR1 /
+  *            TIM_TS_ITR2 /
+  *            TIM_TS_ITR3 /
+  *            TIM_TS_NONE
+  * @param  CommutationSource: the Commutation Event source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+  
+  __HAL_LOCK(htim);
+  
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+  {    
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+  
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+    
+  /* Enable the Commutation Interrupt Request */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+  __HAL_UNLOCK(htim);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with DMA.
+  * @note  This function is mandatory to use the commutation event in order to 
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer) 
+  *        configured in Hall sensor interface, this interface Timer will generate the 
+  *        commutation at its TRGO output (connected to Timer used in this function) each time 
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
+  *          This parameter can be one of the following values:
+  *            TIM_TS_ITR0 /
+  *            TIM_TS_ITR1 /
+  *            TIM_TS_ITR2 /
+  *            TIM_TS_ITR3 /
+  *            TIM_TS_NONE
+  * @param  CommutationSource: the Commutation Event source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+  
+  __HAL_LOCK(htim);
+  
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+  {    
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+  
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+  
+  /* Enable the Commutation DMA Request */
+  /* Set the DMA Commutation Callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;     
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
+  
+  /* Enable the Commutation DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in master mode.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.   
+  * @param  sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
+  *         contains the selected trigger output (TRGO) and the Master/Slave 
+  *         mode. 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+  
+  __HAL_LOCK(htim);
+  
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Reset the MMS Bits */
+  htim->Instance->CR2 &= ~TIM_CR2_MMS;
+  /* Select the TRGO source */
+  htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
+
+  /* Reset the MSM Bit */
+  htim->Instance->SMCR &= ~TIM_SMCR_MSM;
+  /* Set or Reset the MSM Bit */
+  htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
+  
+  htim->State = HAL_TIM_STATE_READY;
+  
+  __HAL_UNLOCK(htim);
+  
+  return HAL_OK;
+} 
+                                                     
+/**
+  * @brief   Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+  *         and the AOE(automatic output enable).
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @param  sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
+  *         contains the BDTR Register configuration  information for the TIM peripheral. 
+  * @retval HAL status
+  */    
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, 
+                                              TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+  
+  /* Process Locked */
+  __HAL_LOCK(htim);
+  
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */
+  htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode  | 
+                                   sBreakDeadTimeConfig->OffStateIDLEMode |
+                                   sBreakDeadTimeConfig->LockLevel        |
+                                   sBreakDeadTimeConfig->DeadTime         |
+                                   sBreakDeadTimeConfig->BreakState       |
+                                   sBreakDeadTimeConfig->BreakPolarity    |
+                                   sBreakDeadTimeConfig->AutomaticOutput;
+  
+                                   
+  htim->State = HAL_TIM_STATE_READY;                                 
+  
+  __HAL_UNLOCK(htim);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module..
+  * @param  TIM_Remap: specifies the TIM input remapping source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
+  *            @arg TIM_TIM2_ETH_PTP:   TIM2 ITR1 input is connected to ETH PTP trogger output.
+  *            @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. 
+  *            @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. 
+  *            @arg TIM_TIM5_GPIO:      TIM5 CH4 input is connected to dedicated Timer pin(default)
+  *            @arg TIM_TIM5_LSI:       TIM5 CH4 input is connected to LSI clock.
+  *            @arg TIM_TIM5_LSE:       TIM5 CH4 input is connected to LSE clock.
+  *            @arg TIM_TIM5_RTC:       TIM5 CH4 input is connected to RTC Output event.
+  *            @arg TIM_TIM11_GPIO:     TIM11 CH4 input is connected to dedicated Timer pin(default) 
+  *            @arg TIM_TIM11_HSE:      TIM11 CH4 input is connected to HSE_RTC clock
+  *                                     (HSE divided by a programmable prescaler)  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+  __HAL_LOCK(htim);
+    
+  /* Check parameters */
+  assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_REMAP(Remap));
+  
+  /* Set the Timer remapping configuration */
+  htim->Instance->OR = Remap;
+  
+  htim->State = HAL_TIM_STATE_READY;
+  
+  __HAL_UNLOCK(htim);  
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Group6 Extension Callbacks functions 
+ *  @brief   Extension Callbacks functions 
+ *
+@verbatim   
+  ==============================================================================
+                    ##### Extension Callbacks functions #####
+  ==============================================================================  
+  [..]  
+    This section provides Extension TIM callback functions:
+    (+) Timer Commutation callback
+    (+) Timer Break callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Hall commutation changed callback in non blocking mode 
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutationCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Break detection callback in non blocking mode 
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIMEx_BreakCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Group7 Extension Peripheral State functions 
+ *  @brief   Extension Peripheral State functions 
+ *
+@verbatim   
+  ==============================================================================
+                ##### Extension Peripheral State functions #####
+  ==============================================================================  
+  [..]
+    This subsection permits to get in run-time the status of the peripheral 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Hall Sensor interface state
+  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  TIM DMA Commutation callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  htim->State= HAL_TIM_STATE_READY;
+    
+  HAL_TIMEx_CommutationCallback(htim); 
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel xN.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel: specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_Channel_1: TIM Channel 1
+  *            @arg TIM_Channel_2: TIM Channel 2
+  *            @arg TIM_Channel_3: TIM Channel 3
+  * @param  ChannelNState: specifies the TIM Channel CCxNE bit new state.
+  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. 
+  * @retval None
+  */
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+  assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));
+
+  tmp = TIM_CCER_CC1NE << Channel;
+
+  /* Reset the CCxNE Bit */
+  TIMx->CCER &= ~tmp;
+
+  /* Set or reset the CCxNE Bit */ 
+  TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,352 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_tim_ex.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of TIM HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_TIM_EX_H
+#define __STM32F4xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL
+  * @{
+  */
+
+/** @addtogroup TIMEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** 
+  * @brief  TIM Hall sensor Configuration Structure definition  
+  */
+
+typedef struct
+{
+                                  
+  uint32_t IC1Polarity;            /*!< Specifies the active edge of the input signal.
+                                        This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+                                                                   
+  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+                                  
+  uint32_t IC1Filter;           /*!< Specifies the input capture filter.
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  
+  uint32_t Commutation_Delay;  /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
+                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */                              
+} TIM_HallSensor_InitTypeDef;
+
+/** 
+  * @brief  TIM Master configuration Structure definition  
+  */ 
+typedef struct {
+  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection. 
+                                      This parameter can be a value of @ref TIMEx_Master_Mode_Selection */ 
+  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection. 
+                                      This parameter can be a value of @ref TIMEx_Master_Slave_Mode */
+}TIM_MasterConfigTypeDef;
+
+/** 
+  * @brief  TIM Break and Dead time configuration Structure definition  
+  */ 
+typedef struct
+{
+  uint32_t OffStateRunMode;	        /*!< TIM off state in run mode.
+                                         This parameter can be a value of @ref TIMEx_OSSR_Off_State_Selection_for_Run_mode_state */
+  uint32_t OffStateIDLEMode;	      /*!< TIM off state in IDLE mode.
+                                         This parameter can be a value of @ref TIMEx_OSSI_Off_State_Selection_for_Idle_mode_state */
+  uint32_t LockLevel;	 	            /*!< TIM Lock level.
+                                         This parameter can be a value of @ref TIMEx_Lock_level */                             
+  uint32_t DeadTime;	 	            /*!< TIM dead Time. 
+                                         This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+  uint32_t BreakState;	 	          /*!< TIM Break State. 
+                                         This parameter can be a value of @ref TIMEx_Break_Input_enable_disable */
+  uint32_t BreakPolarity;	 	        /*!< TIM Break input polarity. 
+                                         This parameter can be a value of @ref TIMEx_Break_Polarity */
+  uint32_t AutomaticOutput;	 	      /*!< TIM Automatic Output Enable state. 
+                                         This parameter can be a value of @ref TIMEx_AOE_Bit_Set_Reset */           
+}TIM_BreakDeadTimeConfigTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants
+  * @{
+  */
+/** @defgroup TIMEx_OSSR_Off_State_Selection_for_Run_mode_state
+  * @{
+  */  
+#define TIM_OSSR_ENABLE 	      (TIM_BDTR_OSSR)
+#define TIM_OSSR_DISABLE              ((uint32_t)0x0000)
+
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
+                                  ((STATE) == TIM_OSSR_DISABLE))
+/**
+  * @}
+  */
+  
+/** @defgroup TIMEx_OSSI_Off_State_Selection_for_Idle_mode_state 
+  * @{
+  */
+#define TIM_OSSI_ENABLE	 	    (TIM_BDTR_OSSI)
+#define TIM_OSSI_DISABLE            ((uint32_t)0x0000)
+
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
+                                  ((STATE) == TIM_OSSI_DISABLE))
+/**
+  * @}
+  */
+/** @defgroup TIMEx_Lock_level 
+  * @{
+  */
+#define TIM_LOCKLEVEL_OFF	   ((uint32_t)0x0000)
+#define TIM_LOCKLEVEL_1            (TIM_BDTR_LOCK_0)
+#define TIM_LOCKLEVEL_2            (TIM_BDTR_LOCK_1)
+#define TIM_LOCKLEVEL_3            (TIM_BDTR_LOCK)
+
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
+                                  ((LEVEL) == TIM_LOCKLEVEL_1) || \
+                                  ((LEVEL) == TIM_LOCKLEVEL_2) || \
+                                  ((LEVEL) == TIM_LOCKLEVEL_3)) 
+/**
+  * @}
+  */  
+/** @defgroup TIMEx_Break_Input_enable_disable 
+  * @{
+  */                         
+#define TIM_BREAK_ENABLE          (TIM_BDTR_BKE)
+#define TIM_BREAK_DISABLE         ((uint32_t)0x0000)
+
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
+                                   ((STATE) == TIM_BREAK_DISABLE))
+/**
+  * @}
+  */
+/** @defgroup TIMEx_Break_Polarity 
+  * @{
+  */
+#define TIM_BREAKPOLARITY_LOW        ((uint32_t)0x0000)
+#define TIM_BREAKPOLARITY_HIGH       (TIM_BDTR_BKP)
+
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
+                                         ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
+/**
+  * @}
+  */
+/** @defgroup TIMEx_AOE_Bit_Set_Reset 
+  * @{
+  */
+#define TIM_AUTOMATICOUTPUT_ENABLE           (TIM_BDTR_AOE)
+#define	TIM_AUTOMATICOUTPUT_DISABLE          ((uint32_t)0x0000)
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+                                              ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
+/**
+  * @}
+  */  
+  
+/** @defgroup TIMEx_Master_Mode_Selection
+  * @{
+  */  
+#define	TIM_TRGO_RESET            ((uint32_t)0x0000)             
+#define	TIM_TRGO_ENABLE           (TIM_CR2_MMS_0)           
+#define	TIM_TRGO_UPDATE           (TIM_CR2_MMS_1)             
+#define	TIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))    
+#define	TIM_TRGO_OC1REF           (TIM_CR2_MMS_2)           
+#define	TIM_TRGO_OC2REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))          
+#define	TIM_TRGO_OC3REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))           
+#define	TIM_TRGO_OC4REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))   
+
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
+                                    ((SOURCE) == TIM_TRGO_ENABLE) || \
+                                    ((SOURCE) == TIM_TRGO_UPDATE) || \
+                                    ((SOURCE) == TIM_TRGO_OC1) || \
+                                    ((SOURCE) == TIM_TRGO_OC1REF) || \
+                                    ((SOURCE) == TIM_TRGO_OC2REF) || \
+                                    ((SOURCE) == TIM_TRGO_OC3REF) || \
+                                    ((SOURCE) == TIM_TRGO_OC4REF))
+      
+   
+/**
+  * @}
+  */ 
+
+/** @defgroup TIMEx_Master_Slave_Mode 
+  * @{
+  */
+
+#define TIM_MASTERSLAVEMODE_ENABLE          ((uint32_t)0x0080)
+#define TIM_MASTERSLAVEMODE_DISABLE         ((uint32_t)0x0000)
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
+                                 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIMEx_Commutation_Mode 
+  * @{
+  */
+#define TIM_COMMUTATION_TRGI              (TIM_CR2_CCUS)
+#define TIM_COMMUTATION_SOFTWARE          ((uint32_t)0x0000)
+/**
+  * @}
+  */
+  
+/** @defgroup TIMEx_Remap 
+  * @{
+  */
+
+#define TIM_TIM2_TIM8_TRGO                     (0x00000000)
+#define TIM_TIM2_ETH_PTP                       (0x00000400)
+#define TIM_TIM2_USBFS_SOF                     (0x00000800)
+#define TIM_TIM2_USBHS_SOF                     (0x00000C00)
+#define TIM_TIM5_GPIO                          (0x00000000)
+#define TIM_TIM5_LSI                           (0x00000040)
+#define TIM_TIM5_LSE                           (0x00000080)
+#define TIM_TIM5_RTC                           (0x000000C0)
+#define TIM_TIM11_GPIO                         (0x00000000)
+#define TIM_TIM11_HSE                          (0x00000002)
+
+#define IS_TIM_REMAP(TIM_REMAP)	 (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
+                                  ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
+                                  ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
+                                  ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
+                                  ((TIM_REMAP) == TIM_TIM5_GPIO)||\
+                                  ((TIM_REMAP) == TIM_TIM5_LSI)||\
+                                  ((TIM_REMAP) == TIM_TIM5_LSE)||\
+                                  ((TIM_REMAP) == TIM_TIM5_RTC)||\
+                                  ((TIM_REMAP) == TIM_TIM11_GPIO)||\
+                                  ((TIM_REMAP) == TIM_TIM11_HSE))
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */   
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+
+/*  Timer Hall Sensor functions  **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);
+
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
+
+/*  Timer Complementary Output Compare functions  *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
+
+/*  Timer Complementary PWM functions  ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
+
+/*  Timer Complementary One Pulse functions  **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+
+/* Extnsion Control functions  ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
+
+/* Extension Callback *********************************************************/
+void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
+void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+
+/* Extension Peripheral State functions  **************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_TIM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1897 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_uart.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   UART HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions  
+  *           + Peripheral State and Errors functions  
+  *           
+  @verbatim       
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    The UART HAL driver can be used as follows:
+    
+    (#) Declare a UART_HandleTypeDef handle structure.
+  
+    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+        (##) Enable the USARTx interface clock.
+        (##) UART pins configuration:
+            (+++) Enable the clock for the UART GPIOs.
+            (+++) Configure these UART pins as alternate function pull-up.
+        (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+             and HAL_UART_Receive_IT() APIs):
+            (+++) Configure the USARTx interrupt priority.
+            (+++) Enable the NVIC USART IRQ handle.
+        (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+             and HAL_UART_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx stream.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required 
+                  Tx/Rx parameters.                
+            (+++) Configure the DMA Tx/Rx Stream.
+            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete 
+                  interrupt on the DMA Tx/Rx Stream.
+
+    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware 
+        flow control and Mode(Receiver/Transmitter) in the Init structure.
+
+    (#) For the UART asynchronous mode, initialize the UART registers by calling
+        the HAL_UART_Init() API.
+    
+    (#) For the UART Half duplex mode, initialize the UART registers by calling 
+        the HAL_HalfDuplex_Init() API.
+    
+    (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.
+    
+    (#) For the Multi-Processor mode, initialize the UART registers by calling 
+        the HAL_MultiProcessor_Init() API.
+        
+     [..] 
+       (@) The specific UART interrupts (Transmission complete interrupt, 
+            RXNE interrupt and Error Interrupts) will be managed using the macros
+            __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit 
+            and receive process.
+          
+     [..] 
+       (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the 
+            low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customed 
+            HAL_UART_MspInit() API.
+          
+     [..] 
+        Three operation modes are available within this driver :     
+  
+     *** Polling mode IO operation ***
+     =================================
+     [..]    
+       (+) Send an amount of data in blocking mode using HAL_UART_Transmit() 
+       (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
+       
+     *** Interrupt mode IO operation ***    
+     ===================================
+     [..]    
+       (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() 
+       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can 
+            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback 
+       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can 
+            add his own code by customization of function pointer HAL_UART_TxCpltCallback
+       (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() 
+       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can 
+            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback 
+       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can 
+            add his own code by customization of function pointer HAL_UART_RxCpltCallback                                      
+       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can 
+            add his own code by customization of function pointer HAL_UART_ErrorCallback
+
+     *** DMA mode IO operation ***    
+     ==============================
+     [..] 
+       (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() 
+       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can 
+            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback 
+       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can 
+            add his own code by customization of function pointer HAL_UART_TxCpltCallback
+       (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA() 
+       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can 
+            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback 
+       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can 
+            add his own code by customization of function pointer HAL_UART_RxCpltCallback                                      
+       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can 
+            add his own code by customization of function pointer HAL_UART_ErrorCallback
+       (+) Pause the DMA Transfer using HAL_UART_DMAPause()      
+       (+) Resume the DMA Transfer using HAL_UART_DMAResume()  
+       (+) Stop the DMA Transfer using HAL_UART_DMAStop()      
+    
+     *** UART HAL driver macros list ***
+     ============================================= 
+     [..]
+       Below the list of most used macros in UART HAL driver.
+       
+      (+) __HAL_UART_ENABLE: Enable the UART peripheral 
+      (+) __HAL_UART_DISABLE: Disable the UART peripheral     
+      (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
+      (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
+      (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
+      (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
+      
+     [..] 
+       (@) You can refer to the UART HAL driver header file for more useful macros 
+      
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup UART 
+  * @brief HAL UART module driver
+  * @{
+  */
+#ifdef HAL_UART_MODULE_ENABLED
+    
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define UART_TIMEOUT_VALUE  22000
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void UART_SetConfig (UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma); 
+static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup UART_Private_Functions
+  * @{
+  */
+
+/** @defgroup UART_Group1 Initialization and de-initialization functions 
+  *  @brief    Initialization and Configuration functions 
+  *
+@verbatim    
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy 
+    in asynchronous mode.
+      (+) For the asynchronous mode only these parameters can be configured: 
+        (++) Baud Rate
+        (++) Word Length 
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+             Depending on the frame length defined by the M bit (8-bits or 9-bits),
+             please refer to Reference manual for possible UART frame formats.           
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+        (++) Over Sampling Methode
+    [..]
+    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs 
+    follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
+    configuration procedures (details for the procedures are available in reference manual (RM0329)).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the UART mode according to the specified parameters in
+  *         the UART_InitTypeDef and create the associated handle.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if(huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+  {
+    /* Check the parameters */
+    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+  }
+  else
+  {
+    /* Check the parameters */
+    assert_param(IS_UART_INSTANCE(huart->Instance));
+  }
+  
+  if(huart->State == HAL_UART_STATE_RESET)
+  {  
+    /* Init the low level hardware */
+    HAL_UART_MspInit(huart);
+  }
+
+  huart->State = HAL_UART_STATE_BUSY;
+
+  /* Disable the peripheral */
+  __HAL_UART_DISABLE(huart);
+  
+  /* Set the UART Communication parameters */
+  UART_SetConfig(huart);
+  
+  /* In asynchronous mode, the following bits must be kept cleared: 
+     - LINEN and CLKEN bits in the USART_CR2 register,
+     - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
+  huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
+  huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+  
+  /* Enable the peripheral */
+  __HAL_UART_ENABLE(huart);
+  
+  /* Initialize the UART state */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->State= HAL_UART_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the half-duplex mode according to the specified
+  *         parameters in the UART_InitTypeDef and create the associated handle.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if(huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  if(huart->State == HAL_UART_STATE_RESET)
+  {   
+    /* Init the low level hardware */
+    HAL_UART_MspInit(huart);
+  }
+
+  huart->State = HAL_UART_STATE_BUSY;
+
+  /* Disable the peripheral */
+  __HAL_UART_DISABLE(huart);
+  
+  /* Set the UART Communication parameters */
+  UART_SetConfig(huart);
+  
+  /* In half-duplex mode, the following bits must be kept cleared: 
+     - LINEN and CLKEN bits in the USART_CR2 register,
+     - SCEN and IREN bits in the USART_CR3 register.*/
+  huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
+  huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN);
+  
+  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+  huart->Instance->CR3 |= USART_CR3_HDSEL;
+ 
+  /* Enable the peripheral */
+  __HAL_UART_ENABLE(huart);
+  
+  /* Initialize the UART state*/
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->State= HAL_UART_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the LIN mode according to the specified
+  *         parameters in the UART_InitTypeDef and create the associated handle.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @param  BreakDetectLength: Specifies the LIN break detection length.
+  *         This parameter can be one of the following values:
+  *            @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
+  *            @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+  /* Check the UART handle allocation */
+  if(huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Check the Break detection length parameter */
+  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+
+  if(huart->State == HAL_UART_STATE_RESET)
+  {   
+    /* Init the low level hardware */
+    HAL_UART_MspInit(huart);
+  }
+
+  huart->State = HAL_UART_STATE_BUSY;
+
+  /* Disable the peripheral */
+  __HAL_UART_DISABLE(huart);
+  
+  /* Set the UART Communication parameters */
+  UART_SetConfig(huart);
+  
+  /* In LIN mode, the following bits must be kept cleared: 
+     - LINEN and CLKEN bits in the USART_CR2 register,
+     - SCEN and IREN bits in the USART_CR3 register.*/
+  huart->Instance->CR2 &= ~(USART_CR2_CLKEN);
+  huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN);
+  
+  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+  huart->Instance->CR2 |= USART_CR2_LINEN;
+  
+  /* Set the USART LIN Break detection length. */
+  huart->Instance->CR2 &= ~(USART_CR2_LBDL);
+  huart->Instance->CR2 |= BreakDetectLength; 
+  
+  /* Enable the peripheral */
+  __HAL_UART_ENABLE(huart);
+  
+  /* Initialize the UART state*/
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->State= HAL_UART_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the Multi-Processor mode according to the specified
+  *         parameters in the UART_InitTypeDef and create the associated handle.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @param  Address: USART address
+  * @param  WakeUpMethode: specifies the USART wakeup method.
+  *          This parameter can be one of the following values:
+  *            @arg UART_WAKEUPMETHODE_IDLELINE: Wakeup by an idle line detection
+  *            @arg UART_WAKEUPMETHODE_ADDRESSMARK: Wakeup by an address mark
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethode)
+{
+  /* Check the UART handle allocation */
+  if(huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the Address & wake up method parameters */
+  assert_param(IS_UART_WAKEUPMETHODE(WakeUpMethode));
+  assert_param(IS_UART_ADDRESS(Address));
+  
+  if(huart->State == HAL_UART_STATE_RESET)
+  {   
+    /* Init the low level hardware */
+    HAL_UART_MspInit(huart);
+  }
+
+  huart->State = HAL_UART_STATE_BUSY;
+
+  /* Disable the peripheral */
+  __HAL_UART_DISABLE(huart);
+  
+  /* Set the UART Communication parameters */
+  UART_SetConfig(huart);
+  
+  /* In Multi-Processor mode, the following bits must be kept cleared: 
+     - LINEN and CLKEN bits in the USART_CR2 register,
+     - SCEN, HDSEL and IREN  bits in the USART_CR3 register */
+  huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
+  huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+  
+  /* Clear the USART address */
+  huart->Instance->CR2 &= ~(USART_CR2_ADD);
+  /* Set the USART address node */
+  huart->Instance->CR2 |= Address;
+  
+  /* Set the wake up methode by setting the WAKE bit in the CR1 register */
+  huart->Instance->CR1 &= ~(USART_CR1_WAKE);
+  huart->Instance->CR1 |= WakeUpMethode;
+  
+  /* Enable the peripheral */
+  __HAL_UART_ENABLE(huart);
+  
+  /* Initialize the UART state */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->State= HAL_UART_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the UART peripheral. 
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if(huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(huart->Instance));
+
+  huart->State = HAL_UART_STATE_BUSY;
+  
+  /* DeInit the low level hardware */
+  HAL_UART_MspDeInit(huart);
+  
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->State = HAL_UART_STATE_RESET;
+
+  /* Process Lock */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  UART MSP Init.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_UART_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  UART MSP DeInit.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_UART_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Group2 IO operation functions 
+  *  @brief UART Transmit and Receive functions 
+  *
+@verbatim   
+  ==============================================================================
+                      ##### IO operation functions #####
+  ==============================================================================  
+  [..]
+    This subsection provides a set of functions allowing to manage the UART asynchronous
+    and Half duplex data transfers.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode: The communication is performed in polling mode. 
+            The HAL status of all data processing is returned by the same function 
+            after finishing transfer.  
+       (++) Non blocking mode: The communication is performed using Interrupts 
+            or DMA, these APIs return the HAL status.
+            The end of the data processing will be indicated through the 
+            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when 
+            using DMA mode.
+            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks 
+            will be executed respectivelly at the end of the transmit or receive process.
+            The HAL_UART_ErrorCallback() user callback will be executed when 
+            a communication error is detected.
+
+    (#) Blocking mode APIs are:
+        (++) HAL_UART_Transmit()
+        (++) HAL_UART_Receive() 
+        
+    (#) Non Blocking mode APIs with Interrupt are:
+        (++) HAL_UART_Transmit_IT()
+        (++) HAL_UART_Receive_IT()
+        (++) HAL_UART_IRQHandler()
+
+    (#) Non Blocking mode functions with DMA are:
+        (++) HAL_UART_Transmit_DMA()
+        (++) HAL_UART_Receive_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non blocking mode:
+        (++) HAL_UART_TxCpltCallback()
+        (++) HAL_UART_RxCpltCallback()
+        (++) HAL_UART_ErrorCallback()
+
+    [..] 
+      (@) In the Half duplex communication, it is forbidden to run the transmit 
+          and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX 
+          can't be useful.
+      
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sends an amount of data in blocking mode. 
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @param  Timeout: Timeout duration  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+  uint32_t tmp1 = 0;
+  
+  tmp1 = huart->State;
+  if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_RX))
+  {
+    if((pData == NULL ) || (Size == 0)) 
+    {
+      return  HAL_ERROR;
+    }
+    
+    /* Process Locked */
+    __HAL_LOCK(huart);
+    
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    /* Check if a non-blocking receive process is ongoing or not */
+    if(huart->State == HAL_UART_STATE_BUSY_RX) 
+    {
+      huart->State = HAL_UART_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      huart->State = HAL_UART_STATE_BUSY_TX;
+    }
+
+    huart->TxXferSize = Size;
+    huart->TxXferCount = Size;
+    while(huart->TxXferCount > 0)
+    {
+      huart->TxXferCount--;
+      if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+      {
+        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        { 
+          return HAL_TIMEOUT;
+        }
+        tmp = (uint16_t*) pData;
+        huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
+        if(huart->Init.Parity == UART_PARITY_NONE)
+        {
+          pData +=2;
+        }
+        else
+        { 
+          pData +=1;
+        }
+      } 
+      else
+      {
+        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+        huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
+      } 
+    }
+    
+    if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK)
+    { 
+      return HAL_TIMEOUT;
+    }
+    
+    /* Check if a non-blocking receive process is ongoing or not */
+    if(huart->State == HAL_UART_STATE_BUSY_TX_RX) 
+    {
+      huart->State = HAL_UART_STATE_BUSY_RX;
+    }
+    else
+    {
+      huart->State = HAL_UART_STATE_READY;
+    }
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;   
+  }
+}
+
+/**
+  * @brief  Receives an amount of data in blocking mode. 
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be received
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{ 
+  uint16_t* tmp;
+  uint32_t tmp1 = 0;
+  
+  tmp1 = huart->State;
+  if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_TX))
+  { 
+    if((pData == NULL ) || (Size == 0)) 
+    {
+      return  HAL_ERROR;
+    }
+    
+    /* Process Locked */
+    __HAL_LOCK(huart);
+    
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    /* Check if a non-blocking transmit process is ongoing or not */
+    if(huart->State == HAL_UART_STATE_BUSY_TX) 
+    {
+      huart->State = HAL_UART_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      huart->State = HAL_UART_STATE_BUSY_RX;
+    }
+    
+    huart->RxXferSize = Size; 
+    huart->RxXferCount = Size;
+    
+    /* Check the remain data to be received */
+    while(huart->RxXferCount > 0)
+    {
+      huart->RxXferCount--;
+      if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+      {
+        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        { 
+          return HAL_TIMEOUT;
+        }
+        tmp = (uint16_t*) pData ;
+        if(huart->Init.Parity == UART_PARITY_NONE)
+        {
+          *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
+          pData +=2;
+        }
+        else
+        {
+          *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
+          pData +=1;
+        }
+
+      } 
+      else
+      {
+        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        { 
+          return HAL_TIMEOUT;
+        }
+        if(huart->Init.Parity == UART_PARITY_NONE)
+        {
+          *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
+        }
+        else
+        {
+          *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
+        }
+        
+      }
+    }
+    
+    /* Check if a non-blocking transmit process is ongoing or not */
+    if(huart->State == HAL_UART_STATE_BUSY_TX_RX) 
+    {
+      huart->State = HAL_UART_STATE_BUSY_TX;
+    }
+    else
+    {
+      huart->State = HAL_UART_STATE_READY;
+    } 
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;   
+  }
+}
+
+/**
+  * @brief  Sends an amount of data in non blocking mode.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tmp = 0;
+  
+  tmp = huart->State;
+  if((tmp == HAL_UART_STATE_READY) || (tmp == HAL_UART_STATE_BUSY_RX))
+  {
+    if((pData == NULL ) || (Size == 0)) 
+    {
+      return HAL_ERROR;
+    }
+    
+    /* Process Locked */
+    __HAL_LOCK(huart);
+    
+    huart->pTxBuffPtr = pData;
+    huart->TxXferSize = Size;
+    huart->TxXferCount = Size;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    /* Check if a receive process is ongoing or not */
+    if(huart->State == HAL_UART_STATE_BUSY_RX) 
+    {
+      huart->State = HAL_UART_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      huart->State = HAL_UART_STATE_BUSY_TX;
+    }
+
+    /* Enable the UART Parity Error Interrupt */
+    __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
+
+    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+    __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+
+    /* Enable the UART Transmit Complete Interrupt */
+    __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;   
+  }
+}
+
+/**
+  * @brief  Receives an amount of data in non blocking mode 
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tmp = 0;
+  
+  tmp = huart->State;  
+  if((tmp == HAL_UART_STATE_READY) || (tmp == HAL_UART_STATE_BUSY_TX))
+  {
+    if((pData == NULL ) || (Size == 0)) 
+    {
+      return HAL_ERROR;
+    }
+    
+    /* Process Locked */
+    __HAL_LOCK(huart);
+    
+    huart->pRxBuffPtr = pData;
+    huart->RxXferSize = Size;
+    huart->RxXferCount = Size;
+    
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    /* Check if a transmit process is ongoing or not */
+    if(huart->State == HAL_UART_STATE_BUSY_TX) 
+    {
+      huart->State = HAL_UART_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      huart->State = HAL_UART_STATE_BUSY_RX;
+    }
+    
+    /* Enable the UART Parity Error Interrupt */
+    __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
+    
+    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+    __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+    
+    /* Enable the UART Data Register not empty Interrupt */
+    __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY; 
+  }
+}
+
+/**
+  * @brief  Sends an amount of data in non blocking mode. 
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  uint32_t *tmp;
+  uint32_t tmp1 = 0;
+  
+  tmp1 = huart->State;  
+  if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_RX))
+  {
+    if((pData == NULL ) || (Size == 0)) 
+    {
+      return HAL_ERROR;
+    }
+    
+    /* Process Locked */
+    __HAL_LOCK(huart);
+    
+    huart->pTxBuffPtr = pData;
+    huart->TxXferSize = Size;
+    huart->TxXferCount = Size;
+    
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    /* Check if a receive process is ongoing or not */
+    if(huart->State == HAL_UART_STATE_BUSY_RX) 
+    {
+      huart->State = HAL_UART_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      huart->State = HAL_UART_STATE_BUSY_TX;
+    }
+    
+    /* Set the UART DMA transfer complete callback */
+    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+    
+    /* Set the UART DMA Half transfer complete callback */
+    huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+    
+    /* Set the DMA error callback */
+    huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+    /* Enable the UART transmit DMA Stream */
+    tmp = (uint32_t*)&pData;
+    HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size);
+    
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the UART CR3 register */
+    huart->Instance->CR3 |= USART_CR3_DMAT;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;   
+  }
+}
+
+/**
+  * @brief  Receives an amount of data in non blocking mode. 
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @param  pData: Pointer to data buffer
+  * @param  Size: Amount of data to be received
+  * @note   When the UART parity is enabled (PCE = 1) the data received contain the parity bit.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  uint32_t *tmp;
+  uint32_t tmp1 = 0;
+  
+  tmp1 = huart->State;    
+  if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_TX))
+  {
+    if((pData == NULL ) || (Size == 0)) 
+    {
+      return HAL_ERROR;
+    }
+    
+    /* Process Locked */
+    __HAL_LOCK(huart);
+    
+    huart->pRxBuffPtr = pData;
+    huart->RxXferSize = Size;
+    
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    /* Check if a transmit process is ongoing or not */
+    if(huart->State == HAL_UART_STATE_BUSY_TX) 
+    {
+      huart->State = HAL_UART_STATE_BUSY_TX_RX;
+    }
+    else
+    {
+      huart->State = HAL_UART_STATE_BUSY_RX;
+    }
+    
+    /* Set the UART DMA transfer complete callback */
+    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+    
+    /* Set the UART DMA Half transfer complete callback */
+    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+    
+    /* Set the DMA error callback */
+    huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+    /* Enable the DMA Stream */
+    tmp = (uint32_t*)&pData;
+    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
+    
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
+    in the UART CR3 register */
+    huart->Instance->CR3 |= USART_CR3_DMAR;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY; 
+  }
+}
+    
+/**
+  * @brief Pauses the DMA Transfer.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+  
+  if(huart->State == HAL_UART_STATE_BUSY_TX)
+  {
+    /* Disable the UART DMA Tx request */
+    huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+  }
+  else if(huart->State == HAL_UART_STATE_BUSY_RX)
+  {
+    /* Disable the UART DMA Rx request */
+    huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+  }
+  else if (huart->State == HAL_UART_STATE_BUSY_TX_RX)
+  {
+    /* Disable the UART DMA Tx & Rx requests */
+    huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+    huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief Resumes the DMA Transfer.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+  
+  if(huart->State == HAL_UART_STATE_BUSY_TX)
+  {
+    /* Enable the UART DMA Tx request */
+    huart->Instance->CR3 |= USART_CR3_DMAT;
+  }
+  else if(huart->State == HAL_UART_STATE_BUSY_RX)
+  {
+    /* Enable the UART DMA Rx request */
+    huart->Instance->CR3 |= USART_CR3_DMAR;
+  }
+  else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+  {
+    /* Enable the UART DMA Tx & Rx request */
+    huart->Instance->CR3 |= USART_CR3_DMAT;
+    huart->Instance->CR3 |= USART_CR3_DMAR;
+  }
+
+  /* If the UART peripheral is still not enabled, enable it */
+  if ((huart->Instance->CR1 & USART_CR1_UE) == 0)
+  {
+    /* Enable UART peripheral */    
+    __HAL_UART_ENABLE(huart);
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief Stops the DMA Transfer.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+  
+  /* Disable the UART Tx/Rx DMA requests */
+  huart->Instance->CR3 &= ~USART_CR3_DMAT;
+  huart->Instance->CR3 &= ~USART_CR3_DMAR;
+  
+  /* Abort the UART DMA tx Stream */
+  if(huart->hdmatx != NULL)
+  {
+    HAL_DMA_Abort(huart->hdmatx);
+  }
+  /* Abort the UART DMA rx Stream */
+  if(huart->hdmarx != NULL)
+  {
+    HAL_DMA_Abort(huart->hdmarx);
+  }
+  /* Disable UART peripheral */
+  __HAL_UART_DISABLE(huart);
+  
+  huart->State = HAL_UART_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles UART interrupt request.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+  uint32_t tmp1 = 0, tmp2 = 0;
+
+  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_PE);
+  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE);  
+  /* UART parity error interrupt occurred ------------------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET))
+  { 
+    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_PE);
+    
+    huart->ErrorCode |= HAL_UART_ERROR_PE;
+  }
+  
+  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_FE);
+  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR);
+  /* UART frame error interrupt occurred -------------------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET))
+  { 
+    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_FE);
+    
+    huart->ErrorCode |= HAL_UART_ERROR_FE;
+  }
+  
+  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_NE);
+  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR);
+  /* UART noise error interrupt occurred -------------------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET))
+  { 
+    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_NE);
+    
+    huart->ErrorCode |= HAL_UART_ERROR_NE;
+  }
+  
+  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_ORE);
+  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR);
+  /* UART Over-Run interrupt occurred ----------------------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET))
+  { 
+    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_ORE);
+    
+    huart->ErrorCode |= HAL_UART_ERROR_ORE;
+  }
+  
+  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE);
+  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE);
+  /* UART in mode Receiver ---------------------------------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET))
+  { 
+    UART_Receive_IT(huart);
+    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
+  }
+  
+  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TC);
+  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC);
+  /* UART in mode Transmitter ------------------------------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET))
+  {
+    UART_Transmit_IT(huart);
+    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
+  }
+  
+  if(huart->ErrorCode != HAL_UART_ERROR_NONE)
+  {
+    /* Set the UART state ready to be able to start again the process */
+    huart->State = HAL_UART_STATE_READY;
+    
+    HAL_UART_ErrorCallback(huart);
+  }  
+}
+
+/**
+  * @brief  Tx Transfer completed callbacks.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_UART_TxCpltCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Tx Half Transfer completed callbacks.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_UART_TxCpltCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Rx Transfer completed callbacks.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_UART_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Half Transfer completed callbacks.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_UART_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  UART error callbacks.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_UART_ErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Group3 Peripheral Control functions 
+  *  @brief   UART control functions 
+  *
+@verbatim   
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================  
+  [..]
+    This subsection provides a set of functions allowing to control the UART:
+    (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.
+    (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode. 
+    (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.
+    
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits break characters.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(huart->Instance));
+  
+  /* Process Locked */
+  __HAL_LOCK(huart);
+  
+  huart->State = HAL_UART_STATE_BUSY;
+  
+  /* Send break characters */
+  huart->Instance->CR1 |= USART_CR1_SBK;
+ 
+  huart->State = HAL_UART_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Enters the UART in mute mode. 
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(huart->Instance));
+  
+  /* Process Locked */
+  __HAL_LOCK(huart);
+  
+  huart->State = HAL_UART_STATE_BUSY;
+  
+  /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
+  huart->Instance->CR1 |= USART_CR1_RWU;
+  
+  huart->State = HAL_UART_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Exits the UART mute mode: wake up software. 
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
+{
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(huart->Instance));
+  
+  /* Process Locked */
+  __HAL_LOCK(huart);
+  
+  huart->State = HAL_UART_STATE_BUSY;
+  
+  /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
+  huart->Instance->CR1 &= (uint32_t)~((uint32_t)USART_CR1_RWU);
+  
+  huart->State = HAL_UART_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Enables the UART transmitter and disables the UART receiver.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpreg = 0x00;
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+  
+  huart->State = HAL_UART_STATE_BUSY;
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  tmpreg = huart->Instance->CR1;
+  
+  /* Clear TE and RE bits */
+  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
+  
+  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+  tmpreg |= (uint32_t)USART_CR1_TE;
+  
+  /* Write to USART CR1 */
+  huart->Instance->CR1 = (uint32_t)tmpreg;
+ 
+  huart->State = HAL_UART_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Enables the UART receiver and disables the UART transmitter.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpreg = 0x00;
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+  
+  huart->State = HAL_UART_STATE_BUSY;
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  tmpreg = huart->Instance->CR1;
+  
+  /* Clear TE and RE bits */
+  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
+  
+  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+  tmpreg |= (uint32_t)USART_CR1_RE;
+  
+  /* Write to USART CR1 */
+  huart->Instance->CR1 = (uint32_t)tmpreg;
+  
+  huart->State = HAL_UART_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+  
+  return HAL_OK; 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Group4 Peripheral State and Errors functions 
+  *  @brief   UART State and Errors functions 
+  *
+@verbatim   
+  ==============================================================================
+                 ##### Peripheral State and Errors functions #####
+  ==============================================================================  
+ [..]
+   This subsection provides a set of functions allowing to return the State of 
+   UART communication process, return Peripheral Errors occurred during communication 
+   process
+   (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.
+   (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication. 
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Returns the UART state.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL state
+  */
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+{
+  return huart->State;
+}
+
+/**
+* @brief  Return the UART error code
+* @param  huart : pointer to a UART_HandleTypeDef structure that contains
+  *              the configuration information for the specified UART.
+* @retval UART Error Code
+*/
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+{
+  return huart->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  DMA UART transmit process complete callback. 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)     
+{
+  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  huart->TxXferCount = 0;
+  
+  /* Disable the DMA transfer for transmit request by setting the DMAT bit
+     in the UART CR3 register */
+  huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
+
+  /* Wait for UART TC Flag */
+  if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, UART_TIMEOUT_VALUE) != HAL_OK)
+  {
+    /* Timeout occurred */ 
+    huart->State = HAL_UART_STATE_TIMEOUT;
+    HAL_UART_ErrorCallback(huart);
+  }
+  else
+  {
+    /* No Timeout */
+    /* Check if a receive process is ongoing or not */
+    if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+    {
+      huart->State = HAL_UART_STATE_BUSY_RX;
+    }
+    else
+    {
+      huart->State = HAL_UART_STATE_READY;
+    }
+    HAL_UART_TxCpltCallback(huart);
+  }
+}
+
+/**
+  * @brief DMA UART transmit process half complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  HAL_UART_TxHalfCpltCallback(huart);
+}
+
+/**
+  * @brief  DMA UART receive process complete callback. 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)  
+{
+  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  huart->RxXferCount = 0;
+  
+  /* Disable the DMA transfer for the receiver request by setting the DMAR bit 
+     in the UART CR3 register */
+  huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
+
+  /* Check if a transmit process is ongoing or not */
+  if(huart->State == HAL_UART_STATE_BUSY_TX_RX) 
+  {
+    huart->State = HAL_UART_STATE_BUSY_TX;
+  }
+  else
+  {
+    huart->State = HAL_UART_STATE_READY;
+  }
+  HAL_UART_RxCpltCallback(huart);
+}
+
+/**
+  * @brief DMA UART receive process half complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  HAL_UART_RxHalfCpltCallback(huart); 
+}
+
+/**
+  * @brief  DMA UART communication error callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)   
+{
+  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  huart->RxXferCount = 0;
+  huart->TxXferCount = 0;
+  huart->State= HAL_UART_STATE_READY;
+  huart->ErrorCode |= HAL_UART_ERROR_DMA;
+  HAL_UART_ErrorCallback(huart);
+}
+
+/**
+  * @brief  This function handles UART Communication Timeout.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @param  Flag: specifies the UART flag to check.
+  * @param  Status: The new Flag status (SET or RESET).
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+  uint32_t timeout = 0;
+  
+  timeout = HAL_GetTick() + Timeout;
+  
+  /* Wait until flag is set */
+  if(Status == RESET)
+  {
+    while(__HAL_UART_GET_FLAG(huart, Flag) == RESET)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+          __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+          __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+          __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+          __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+          huart->State= HAL_UART_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(huart);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  else
+  {
+    while(__HAL_UART_GET_FLAG(huart, Flag) != RESET)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+          __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+          __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+          __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+          __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+          huart->State= HAL_UART_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(huart);
+        
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  return HAL_OK;      
+}
+
+/**
+  * @brief  Sends an amount of data in non blocking mode.
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
+{
+  uint16_t* tmp;
+  uint32_t tmp1 = 0;
+  
+  tmp1 = huart->State;
+  if((tmp1 == HAL_UART_STATE_BUSY_TX) || (tmp1 == HAL_UART_STATE_BUSY_TX_RX))
+  {
+    if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+    {
+      tmp = (uint16_t*) huart->pTxBuffPtr;
+      huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
+      if(huart->Init.Parity == UART_PARITY_NONE)
+      {
+        huart->pTxBuffPtr += 2;
+      }
+      else
+      {
+        huart->pTxBuffPtr += 1;
+      }
+    } 
+    else
+    {
+      huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
+    }
+
+    if(--huart->TxXferCount == 0)
+    {
+      /* Disable the UART Transmit Complete Interrupt */
+      __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+      
+      /* Check if a receive process is ongoing or not */
+      if(huart->State == HAL_UART_STATE_BUSY_TX_RX) 
+      {
+        huart->State = HAL_UART_STATE_BUSY_RX;
+      }
+      else
+      {
+        /* Disable the UART Parity Error Interrupt */
+        __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+        
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+        __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+        
+        huart->State = HAL_UART_STATE_READY;
+      }
+      HAL_UART_TxCpltCallback(huart);
+      
+      return HAL_OK;
+    }
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Receives an amount of data in non blocking mode 
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
+{
+  uint16_t* tmp;
+  uint32_t tmp1 = 0;
+  
+  tmp1 = huart->State; 
+  if((tmp1 == HAL_UART_STATE_BUSY_RX) || (tmp1 == HAL_UART_STATE_BUSY_TX_RX))
+  {
+    if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+    {
+      tmp = (uint16_t*) huart->pRxBuffPtr;
+      if(huart->Init.Parity == UART_PARITY_NONE)
+      {
+        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
+        huart->pRxBuffPtr += 2;
+      }
+      else
+      {
+        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
+        huart->pRxBuffPtr += 1;
+      }
+    }
+    else
+    {
+      if(huart->Init.Parity == UART_PARITY_NONE)
+      {
+        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
+      }
+      else
+      {
+        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
+      }
+    }
+    
+    if(--huart->RxXferCount == 0)
+    {
+      if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, SET, UART_TIMEOUT_VALUE) != HAL_OK)
+      { 
+        return HAL_TIMEOUT;
+      }
+      __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+      
+      /* Check if a transmit process is ongoing or not */
+      if(huart->State == HAL_UART_STATE_BUSY_TX_RX) 
+      {
+        huart->State = HAL_UART_STATE_BUSY_TX;
+      }
+      else
+      {
+        /* Disable the UART Parity Error Interrupt */
+        __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+        
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+        __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+        
+        huart->State = HAL_UART_STATE_READY;
+      }
+      HAL_UART_RxCpltCallback(huart);
+      
+      return HAL_OK;
+    }
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY; 
+  }
+}
+
+/**
+  * @brief  Configures the UART peripheral. 
+  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+static void UART_SetConfig(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpreg = 0x00;
+  
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(huart->Instance));
+  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));  
+  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+  assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+  assert_param(IS_UART_PARITY(huart->Init.Parity));
+  assert_param(IS_UART_MODE(huart->Init.Mode));
+  assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+
+  /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
+  if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+  {
+    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+  }
+
+  /*-------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = huart->Instance->CR2;
+
+  /* Clear STOP[13:12] bits */
+  tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
+
+  /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */
+  tmpreg |= (uint32_t)huart->Init.StopBits;
+  
+  /* Write to USART CR2 */
+  huart->Instance->CR2 = (uint32_t)tmpreg;
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  tmpreg = huart->Instance->CR1;
+
+  /* Clear M, PCE, PS, TE and RE bits */
+  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
+                                   USART_CR1_RE | USART_CR1_OVER8));
+
+  /* Configure the UART Word Length, Parity and mode: 
+     Set the M bits according to huart->Init.WordLength value 
+     Set PCE and PS bits according to huart->Init.Parity value
+     Set TE and RE bits according to huart->Init.Mode value
+     Set OVER8 bit according to huart->Init.OverSampling value */
+  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
+  
+  /* Write to USART CR1 */
+  huart->Instance->CR1 = (uint32_t)tmpreg;
+  
+  /*-------------------------- USART CR3 Configuration -----------------------*/  
+  tmpreg = huart->Instance->CR3;
+  
+  /* Clear CTSE and RTSE bits */
+  tmpreg &= (uint32_t)~((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
+  
+  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
+  tmpreg |= huart->Init.HwFlowCtl;
+  
+  /* Write to USART CR3 */
+  huart->Instance->CR3 = (uint32_t)tmpreg;
+  
+  /* Check the Over Sampling */
+  if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
+  {
+    /*-------------------------- USART BRR Configuration ---------------------*/
+    if((huart->Instance == USART1) || (huart->Instance == USART6))
+    {
+      huart->Instance->BRR = __UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+    }
+    else
+    {
+      huart->Instance->BRR = __UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
+    }
+  }
+  else
+  {
+    /*-------------------------- USART BRR Configuration ---------------------*/
+    if((huart->Instance == USART1) || (huart->Instance == USART6))
+    {
+      huart->Instance->BRR = __UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+    }
+    else
+    {
+      huart->Instance->BRR = __UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_uart.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,494 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_uart.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of UART HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_UART_H
+#define __STM32F4xx_HAL_UART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UART
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** 
+  * @brief UART Init Structure definition  
+  */ 
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                           - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))
+                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 
+                                           Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref UART_Word_Length */
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref UART_Stop_Bits */
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref UART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+ 
+  uint32_t Mode;                      /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref UART_Mode */
+
+  uint32_t HwFlowCtl;                 /*!< Specifies wether the hardware flow control mode is enabled
+                                           or disabled.
+                                           This parameter can be a value of @ref UART_Hardware_Flow_Control */
+  
+  uint32_t OverSampling;              /*!< Specifies wether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
+                                           This parameter can be a value of @ref UART_Over_Sampling */ 
+}UART_InitTypeDef;
+
+/** 
+  * @brief HAL UART State structures definition  
+  */ 
+typedef enum
+{
+  HAL_UART_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized                  */
+  HAL_UART_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
+  HAL_UART_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */   
+  HAL_UART_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */ 
+  HAL_UART_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
+  HAL_UART_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */  
+  HAL_UART_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
+  HAL_UART_STATE_ERROR             = 0x04     /*!< Error                                              */      
+}HAL_UART_StateTypeDef;
+
+/** 
+  * @brief  HAL UART Error Code structure definition  
+  */ 
+typedef enum
+{
+  HAL_UART_ERROR_NONE      = 0x00,    /*!< No error            */
+  HAL_UART_ERROR_PE        = 0x01,    /*!< Parity error        */
+  HAL_UART_ERROR_NE        = 0x02,    /*!< Noise error         */
+  HAL_UART_ERROR_FE        = 0x04,    /*!< frame error         */
+  HAL_UART_ERROR_ORE       = 0x08,    /*!< Overrun error       */
+  HAL_UART_ERROR_DMA       = 0x10     /*!< DMA transfer error  */
+}HAL_UART_ErrorTypeDef;
+
+/** 
+  * @brief  UART handle Structure definition  
+  */  
+typedef struct
+{
+  USART_TypeDef                 *Instance;        /* UART registers base address        */
+  
+  UART_InitTypeDef              Init;             /* UART communication parameters      */
+  
+  uint8_t                       *pTxBuffPtr;      /* Pointer to UART Tx transfer Buffer */
+  
+  uint16_t                      TxXferSize;       /* UART Tx Transfer size              */
+  
+  uint16_t                      TxXferCount;      /* UART Tx Transfer Counter           */
+  
+  uint8_t                       *pRxBuffPtr;      /* Pointer to UART Rx transfer Buffer */
+  
+  uint16_t                      RxXferSize;       /* UART Rx Transfer size              */
+  
+  uint16_t                      RxXferCount;      /* UART Rx Transfer Counter           */  
+  
+  DMA_HandleTypeDef             *hdmatx;          /* UART Tx DMA Handle parameters      */
+    
+  DMA_HandleTypeDef             *hdmarx;          /* UART Rx DMA Handle parameters      */
+  
+  HAL_LockTypeDef               Lock;            /* Locking object                     */
+
+  __IO HAL_UART_StateTypeDef    State;            /* UART communication state           */
+  
+  __IO HAL_UART_ErrorTypeDef    ErrorCode;        /* UART Error code                    */
+  
+}UART_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants
+  * @{
+  */
+  
+/** @defgroup UART_Word_Length 
+  * @{
+  */
+#define UART_WORDLENGTH_8B                  ((uint32_t)0x00000000)
+#define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
+#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
+                                     ((LENGTH) == UART_WORDLENGTH_9B))
+/**
+  * @}
+  */
+
+/** @defgroup UART_Stop_Bits 
+  * @{
+  */
+#define UART_STOPBITS_1                     ((uint32_t)0x00000000)
+#define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
+                                    ((STOPBITS) == UART_STOPBITS_2))
+/**
+  * @}
+  */ 
+
+/** @defgroup UART_Parity 
+  * @{
+  */ 
+#define UART_PARITY_NONE                    ((uint32_t)0x00000000)
+#define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
+#define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
+                                ((PARITY) == UART_PARITY_EVEN) || \
+                                ((PARITY) == UART_PARITY_ODD))
+/**
+  * @}
+  */ 
+
+/** @defgroup UART_Hardware_Flow_Control 
+  * @{
+  */ 
+#define UART_HWCONTROL_NONE                  ((uint32_t)0x00000000)
+#define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)
+#define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)
+#define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
+#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
+                              (((CONTROL) == UART_HWCONTROL_NONE) || \
+                               ((CONTROL) == UART_HWCONTROL_RTS) || \
+                               ((CONTROL) == UART_HWCONTROL_CTS) || \
+                               ((CONTROL) == UART_HWCONTROL_RTS_CTS))
+/**
+  * @}
+  */
+
+/** @defgroup UART_Mode 
+  * @{
+  */ 
+#define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)
+#define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)
+#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
+/**
+  * @}
+  */
+    
+ /** @defgroup UART_State 
+  * @{
+  */ 
+#define UART_STATE_DISABLE                  ((uint32_t)0x00000000)
+#define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)
+#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
+                              ((STATE) == UART_STATE_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup UART_Over_Sampling 
+  * @{
+  */
+#define UART_OVERSAMPLING_16                    ((uint32_t)0x00000000)
+#define UART_OVERSAMPLING_8                     ((uint32_t)USART_CR1_OVER8)
+#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
+                                        ((SAMPLING) == UART_OVERSAMPLING_8))
+/**
+  * @}
+  */
+
+/** @defgroup UART_LIN_Break_Detection_Length 
+  * @{
+  */  
+#define UART_LINBREAKDETECTLENGTH_10B      ((uint32_t)0x00000000)
+#define UART_LINBREAKDETECTLENGTH_11B      ((uint32_t)0x00000020)
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
+                                                 ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
+/**
+  * @}
+  */
+                                         
+/** @defgroup UART_WakeUp_functions
+  * @{
+  */
+#define UART_WAKEUPMETHODE_IDLELINE                ((uint32_t)0x00000000)
+#define UART_WAKEUPMETHODE_ADDRESSMARK             ((uint32_t)0x00000800)
+#define IS_UART_WAKEUPMETHODE(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHODE_IDLELINE) || \
+                                       ((WAKEUP) == UART_WAKEUPMETHODE_ADDRESSMARK))
+/**
+  * @}
+  */
+
+/** @defgroup UART_Flags 
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the SR register
+  * @{
+  */
+#define UART_FLAG_CTS                       ((uint32_t)0x00000200)
+#define UART_FLAG_LBD                       ((uint32_t)0x00000100)
+#define UART_FLAG_TXE                       ((uint32_t)0x00000080)
+#define UART_FLAG_TC                        ((uint32_t)0x00000040)
+#define UART_FLAG_RXNE                      ((uint32_t)0x00000020)
+#define UART_FLAG_IDLE                      ((uint32_t)0x00000010)
+#define UART_FLAG_ORE                       ((uint32_t)0x00000008)
+#define UART_FLAG_NE                        ((uint32_t)0x00000004)
+#define UART_FLAG_FE                        ((uint32_t)0x00000002)
+#define UART_FLAG_PE                        ((uint32_t)0x00000001)
+/**
+  * @}
+  */
+
+/** @defgroup UART_Interrupt_definition 
+  *        Elements values convention: 0xY000XXXX
+  *           - XXXX  : Interrupt mask in the XX register
+  *           - Y  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *
+  * @{
+  */  
+#define UART_IT_PE                          ((uint32_t)0x10000100)
+#define UART_IT_TXE                         ((uint32_t)0x10000080)
+#define UART_IT_TC                          ((uint32_t)0x10000040)
+#define UART_IT_RXNE                        ((uint32_t)0x10000020)
+#define UART_IT_IDLE                        ((uint32_t)0x10000010)
+
+#define UART_IT_LBD                         ((uint32_t)0x20000040)
+#define UART_IT_CTS                         ((uint32_t)0x30000400)
+
+#define UART_IT_ERR                         ((uint32_t)0x30000001)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset UART handle state
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
+  * @retval None
+  */
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
+
+/** @brief  Flushs the UART DR register 
+  * @param  __HANDLE__: specifies the UART Handle.
+  */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
+
+/** @brief  Checks whether the specified UART flag is set or not.
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
+  *            @arg UART_FLAG_LBD:  LIN Break detection flag
+  *            @arg UART_FLAG_TXE:  Transmit data register empty flag
+  *            @arg UART_FLAG_TC:   Transmission Complete flag
+  *            @arg UART_FLAG_RXNE: Receive data register not empty flag
+  *            @arg UART_FLAG_IDLE: Idle Line detection flag
+  *            @arg UART_FLAG_ORE:  OverRun Error flag
+  *            @arg UART_FLAG_NE:   Noise Error flag
+  *            @arg UART_FLAG_FE:   Framing Error flag
+  *            @arg UART_FLAG_PE:   Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))   
+     
+/** @brief  Clears the specified UART pending flag.
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
+  * @param  __FLAG__: specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
+  *            @arg UART_FLAG_LBD:  LIN Break detection flag.
+  *            @arg UART_FLAG_TC:   Transmission Complete flag.
+  *            @arg UART_FLAG_RXNE: Receive data register not empty flag.
+  *   
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
+  *          error) and IDLE (Idle line detected) flags are cleared by software 
+  *          sequence: a read operation to USART_SR register followed by a read
+  *          operation to USART_DR register.
+  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
+  * @note   TC flag can be also cleared by software sequence: a read operation to 
+  *          USART_SR register followed by a write operation to USART_DR register.
+  * @note   TXE flag is cleared only by a write to the USART_DR register.
+  *   
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+
+/** @brief  Enables or disables the specified UART interrupt.
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
+  * @param  __INTERRUPT__: specifies the UART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg UART_IT_CTS:  CTS change interrupt
+  *            @arg UART_IT_LBD:  LIN Break detection interrupt
+  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
+  *            @arg UART_IT_TC:   Transmission complete interrupt
+  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg UART_IT_IDLE: Idle line detection interrupt
+  *            @arg UART_IT_PE:   Parity Error interrupt
+  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  * @param  NewState: new state of the specified UART interrupt.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+#define UART_IT_MASK  ((uint32_t)0x0000FFFF)
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+                                                           (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & UART_IT_MASK)): \
+                                                        ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+                                                           (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+                                                        ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
+    
+/** @brief  Checks whether the specified UART interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the UART Handle.
+  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
+  *         UART peripheral.
+  * @param  __IT__: specifies the UART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+  *            @arg UART_IT_LBD: LIN Break detection interrupt
+  *            @arg UART_IT_TXE: Transmit Data Register empty interrupt
+  *            @arg UART_IT_TC:  Transmission complete interrupt
+  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg UART_IT_IDLE: Idle line detection interrupt
+  *            @arg USART_IT_ERR: Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
+                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
+
+/** @brief  macros to enables or disables the UART's one bit sampling method
+  * @param  __HANDLE__: specifies the UART Handle.  
+  * @retval None
+  */     
+#define __HAL_UART_ONEBIT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+#define __HAL_UART_ONEBIT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
+
+#define __HAL_UART_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+#define __HAL_UART_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+    
+#define __DIV_SAMPLING16(_PCLK_, _BAUD_)            (((_PCLK_)*25)/(4*(_BAUD_)))
+#define __DIVMANT_SAMPLING16(_PCLK_, _BAUD_)        (__DIV_SAMPLING16((_PCLK_), (_BAUD_))/100)
+#define __DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_)        (((__DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (__DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define __UART_BRR_SAMPLING16(_PCLK_, _BAUD_)       ((__DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define __DIV_SAMPLING8(_PCLK_, _BAUD_)             (((_PCLK_)*25)/(2*(_BAUD_)))
+#define __DIVMANT_SAMPLING8(_PCLK_, _BAUD_)         (__DIV_SAMPLING8((_PCLK_), (_BAUD_))/100)
+#define __DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_)         (((__DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (__DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define __UART_BRR_SAMPLING8(_PCLK_, _BAUD_)        ((__DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
+#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)                             
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethode);
+HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+
+/* Peripheral State functions  **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
+uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_UART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1826 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_usart.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   USART HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions 
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    The USART HAL driver can be used as follows:
+
+    (#) Declare a USART_HandleTypeDef handle structure.
+    (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit () API:
+        (##) Enable the USARTx interface clock.
+        (##) USART pins configuration:
+             (+++) Enable the clock for the USART GPIOs.
+             (+++) Configure these USART pins as alternate function pull-up.
+        (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
+             HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
+             (+++) Configure the USARTx interrupt priority.
+             (+++) Enable the NVIC USART IRQ handle.
+        (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
+             HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
+             (+++) Declare a DMA handle structure for the Tx/Rx stream.
+             (+++) Enable the DMAx interface clock.
+             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+             (+++) Configure the DMA Tx/Rx Stream.
+             (+++) Associate the initilalized DMA handle to the USART DMA Tx/Rx handle.
+             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
+
+    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware 
+        flow control and Mode(Receiver/Transmitter) in the husart Init structure.
+
+    (#) Initialize the USART registers by calling the HAL_USART_Init() API:
+        (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+             by calling the customed HAL_USART_MspInit(&husart) API.
+                    
+        -@@- The specific USART interrupts (Transmission complete interrupt, 
+             RXNE interrupt and Error Interrupts) will be managed using the macros
+             __USART_ENABLE_IT() and __USART_DISABLE_IT() inside the transmit and receive process.
+          
+    (#) Three operation modes are available within this driver :     
+  
+     *** Polling mode IO operation ***
+     =================================
+     [..]    
+       (+) Send an amount of data in blocking mode using HAL_USART_Transmit() 
+       (+) Receive an amount of data in blocking mode using HAL_USART_Receive()
+       
+     *** Interrupt mode IO operation ***    
+     ===================================
+     [..]    
+       (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT() 
+       (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can 
+            add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback 
+       (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can 
+            add his own code by customization of function pointer HAL_USART_TxCpltCallback
+       (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT() 
+       (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can 
+            add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback 
+       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can 
+            add his own code by customization of function pointer HAL_USART_RxCpltCallback                                      
+       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can 
+            add his own code by customization of function pointer HAL_USART_ErrorCallback
+    
+     *** DMA mode IO operation ***    
+     ==============================
+     [..] 
+       (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA() 
+       (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can 
+            add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback 
+       (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can 
+            add his own code by customization of function pointer HAL_USART_TxCpltCallback
+       (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA() 
+       (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can 
+            add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback 
+       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can 
+            add his own code by customization of function pointer HAL_USART_RxCpltCallback                                      
+       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can 
+            add his own code by customization of function pointer HAL_USART_ErrorCallback
+       (+) Pause the DMA Transfer using HAL_USART_DMAPause()      
+       (+) Resume the DMA Transfer using HAL_USART_DMAResume()  
+       (+) Stop the DMA Transfer using HAL_USART_DMAStop()      
+     
+     *** USART HAL driver macros list ***
+     ============================================= 
+     [..]
+       Below the list of most used macros in USART HAL driver.
+       
+       (+) __HAL_USART_ENABLE: Enable the USART peripheral 
+       (+) __HAL_USART_DISABLE: Disable the USART peripheral     
+       (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
+       (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
+       (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
+       (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
+      
+     [..] 
+       (@) You can refer to the USART HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup USART 
+  * @brief HAL USART Synchronous module driver
+  * @{
+  */
+#ifdef HAL_USART_MODULE_ENABLED
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define DUMMY_DATA      0xFFFF
+#define USART_TIMEOUT_VALUE  22000
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
+static void USART_SetConfig (USART_HandleTypeDef *husart);
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAError(DMA_HandleTypeDef *hdma); 
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+/* Private functions ---------------------------------------------------------*/
+
+
+/** @defgroup USART_Private_Functions
+  * @{
+  */
+
+/** @defgroup USART_Group1 USART Initialization and de-initialization functions 
+  *  @brief    Initialization and Configuration functions 
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and Configuration functions #####
+  ==============================================================================
+  [..]
+  This subsection provides a set of functions allowing to initialize the USART 
+  in asynchronous and in synchronous modes.
+  (+) For the asynchronous mode only these parameters can be configured: 
+      (++) Baud Rate
+      (++) Word Length 
+      (++) Stop Bit
+      (++) Parity: If the parity is enabled, then the MSB bit of the data written
+           in the data register is transmitted but is changed by the parity bit.
+           Depending on the frame length defined by the M bit (8-bits or 9-bits),
+           please refer to Reference manual for possible USART frame formats.   
+      (++) USART polarity
+      (++) USART phase
+      (++) USART LastBit
+      (++) Receiver/transmitter modes
+
+  [..]
+    The HAL_USART_Init() function follows the USART  synchronous configuration 
+    procedure (details for the procedure are available in reference manual (RM0329)).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the USART mode according to the specified
+  *         parameters in the USART_InitTypeDef and create the associated handle.
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
+{
+  /* Check the USART handle allocation */
+  if(husart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_USART_INSTANCE(husart->Instance));
+
+  if(husart->State == HAL_USART_STATE_RESET)
+  {
+    /* Init the low level hardware */
+    HAL_USART_MspInit(husart);
+  }
+  
+  husart->State = HAL_USART_STATE_BUSY;  
+
+  /* Set the USART Communication parameters */
+  USART_SetConfig(husart);
+
+  /* In USART mode, the following bits must be kept cleared: 
+     - LINEN bit in the USART_CR2 register
+     - HDSEL, SCEN and IREN bits in the USART_CR3 register */
+  husart->Instance->CR2 &= ~USART_CR2_LINEN;
+  husart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL);
+
+  /* Enable the Peripheral */
+  __USART_ENABLE(husart);
+
+  /* Initialize the USART state */
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+  husart->State= HAL_USART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the USART peripheral.
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
+{
+   /* Check the USART handle allocation */
+  if(husart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_USART_INSTANCE(husart->Instance));
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  /* DeInit the low level hardware */
+  HAL_USART_MspDeInit(husart);
+
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+  husart->State = HAL_USART_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USART MSP Init.
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval None
+  */
+ __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_USART_MspInit could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @brief  USART MSP DeInit.
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval None
+  */
+ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_USART_MspDeInit could be implenetd in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group2 IO operation functions 
+  *  @brief   USART Transmit and Receive functions 
+  *
+@verbatim
+  ==============================================================================
+                         ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the USART synchronous
+    data transfers.
+      
+  [..] 
+    The USART supports master mode only: it cannot receive or send data related to an input
+    clock (SCLK is always an output).
+
+    (#) There are two modes of transfer:
+        (++) Blocking mode: The communication is performed in polling mode. 
+             The HAL status of all data processing is returned by the same function 
+             after finishing transfer.  
+        (++) No-Blocking mode: The communication is performed using Interrupts 
+             or DMA, These API's return the HAL status.
+             The end of the data processing will be indicated through the 
+             dedicated USART IRQ when using Interrupt mode or the DMA IRQ when 
+             using DMA mode.
+             The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() 
+              user callbacks 
+             will be executed respectivelly at the end of the transmit or Receive process
+             The HAL_USART_ErrorCallback() user callback will be executed when a communication 
+             error is detected
+
+    (#) Blocking mode APIs are :
+        (++) HAL_USART_Transmit() in simplex mode
+        (++) HAL_USART_Receive() in full duplex receive only
+        (++) HAL_USART_TransmitReceive() in full duplex mode
+        
+    (#) Non Blocking mode APIs with Interrupt are :
+        (++) HAL_USART_Transmit_IT()in simplex mode
+        (++) HAL_USART_Receive_IT() in full duplex receive only
+        (++) HAL_USART_TransmitReceive_IT() in full duplex mode
+        (++) HAL_USART_IRQHandler()
+
+    (#) Non Blocking mode functions with DMA are :
+        (++) HAL_USART_Transmit_DMA()in simplex mode
+        (++) HAL_USART_Receive_DMA() in full duplex receive only
+        (++) HAL_USART_TransmitReceie_DMA() in full duplex mode
+          
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_USART_TxCpltCallback()
+        (++) HAL_USART_RxCpltCallback()
+        (++) HAL_USART_ErrorCallback()
+        (++) HAL_USART_TxRxCpltCallback()
+      
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Simplex Send an amount of data in blocking mode. 
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @param  pTxData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @param  Timeout: Timeout duration    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pTxData == NULL) || (Size == 0)) 
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX;
+
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+    while(husart->TxXferCount > 0)
+    {
+      husart->TxXferCount--;
+      if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+      {
+        /* Wait for TC flag in order to write data in DR */
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+        tmp = (uint16_t*) pTxData;
+        husart->Instance->DR = (*tmp & (uint16_t)0x01FF);
+        if(husart->Init.Parity == USART_PARITY_NONE)
+        {
+          pTxData += 2;
+        }
+        else
+        {
+          pTxData += 1;
+        }
+      }
+      else
+      {
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+        husart->Instance->DR = (*pTxData++ & (uint8_t)0xFF);
+      }
+    }
+
+    if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+    { 
+      return HAL_TIMEOUT;
+    }
+
+    husart->State = HAL_USART_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Full-Duplex Receive an amount of data in blocking mode. 
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @param  pRxData: Pointer to data buffer
+  * @param  Size: Amount of data to be received
+  * @param  Timeout: Timeout duration    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pRxData == NULL) || (Size == 0)) 
+    {
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_RX;
+
+    husart->RxXferSize = Size;
+    husart->RxXferCount = Size;
+    /* Check the remain data to be received */
+    while(husart->RxXferCount > 0)
+    {
+      husart->RxXferCount--;
+      if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+      {
+        /* Wait until TC flag is set to send dummy byte in order to generate the clock for the slave to send data */
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+        { 
+          return HAL_TIMEOUT;
+        }
+        /* Send dummy byte in order to generate clock */
+        husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
+        
+        /* Wait for RXNE Flag */
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        { 
+          return HAL_TIMEOUT;
+        }
+        tmp = (uint16_t*) pRxData ;
+        if(husart->Init.Parity == USART_PARITY_NONE)
+        {
+          *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
+          pRxData +=2;
+        }
+        else
+        {
+          *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
+          pRxData +=1;
+        }
+      }
+      else
+      {
+        /* Wait until TC flag is set to send dummy byte in order to generate the clock for the slave to send data */
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+        { 
+          return HAL_TIMEOUT;
+        }
+
+        /* Send Dummy Byte in order to generate clock */
+        husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FF);
+
+        /* Wait until RXNE flag is set to receive the byte */
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+        if(husart->Init.Parity == USART_PARITY_NONE)
+        {
+          /* Receive data */
+          *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
+        }
+        else
+        {
+          /* Receive data */
+          *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
+        }
+        
+      }
+    }
+
+    husart->State = HAL_USART_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). 
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @param  pTxData: Pointer to data transmitted buffer
+  * @param  pRxData: Pointer to data received buffer  
+  * @param  Size: Amount of data to be sent
+   * @param  Timeout: Timeout duration    
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) 
+    {
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_RX;
+
+    husart->RxXferSize = Size;
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+    husart->RxXferCount = Size;
+
+    /* Check the remain data to be received */
+    while(husart->TxXferCount > 0)
+    {
+      husart->TxXferCount--;
+      husart->RxXferCount--;
+      if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+      {
+        /* Wait for TC flag in order to write data in DR */
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+        tmp = (uint16_t*) pTxData;
+        husart->Instance->DR = (*tmp & (uint16_t)0x01FF);
+        if(husart->Init.Parity == USART_PARITY_NONE)
+        {
+          pTxData += 2;
+        }
+        else
+        {
+          pTxData += 1;
+        }
+        
+        /* Wait for RXNE Flag */
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+        tmp = (uint16_t*) pRxData ;
+        if(husart->Init.Parity == USART_PARITY_NONE)
+        {
+          *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
+          pRxData += 2;
+        }
+        else
+        {
+          *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
+          pRxData += 1;
+        }
+      } 
+      else
+      {
+        /* Wait for TC flag in order to write data in DR */
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+        husart->Instance->DR = (*pTxData++ & (uint8_t)0x00FF);
+
+        /* Wait for RXNE Flag */
+        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+        if(husart->Init.Parity == USART_PARITY_NONE)
+        {
+          /* Receive data */
+          *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
+        }
+        else
+        {
+          /* Receive data */
+          *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
+        }
+      }
+    }
+
+    husart->State = HAL_USART_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Simplex Send an amount of data in non-blocking mode. 
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @param  pTxData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  * @note   The USART errors are not managed to avoid the overrun error.
+  */
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+{
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pTxData == NULL) || (Size == 0)) 
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pTxBuffPtr = pTxData;
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX;
+
+    /* The USART Error Interrupts: (Frame error, Noise error, Overrun error) 
+       are not managed by the USART transmit process to avoid the overrun interrupt
+       when the USART mode is configured for transmit and receive "USART_MODE_TX_RX"
+       to benefit for the frame error and noise interrupts the USART mode should be
+       configured only for transmit "USART_MODE_TX"
+       The __USART_ENABLE_IT(husart, USART_IT_ERR) can be used to enable the Frame error,
+       Noise error interrupt */
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    /* Enable the USART Transmit Complete Interrupt */
+    __USART_ENABLE_IT(husart, USART_IT_TC);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Simplex Receive an amount of data in non-blocking mode. 
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @param  pRxData: Pointer to data buffer
+  * @param  Size: Amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pRxData == NULL) || (Size == 0)) 
+    {
+      return HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pRxBuffPtr = pRxData;
+    husart->RxXferSize = Size;
+    husart->RxXferCount = Size;
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_RX;
+
+    /* Enable the USART Data Register not empty Interrupt */
+    __USART_ENABLE_IT(husart, USART_IT_RXNE); 
+
+    /* Enable the USART Parity Error Interrupt */
+    __USART_ENABLE_IT(husart, USART_IT_PE);
+
+    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+    __USART_ENABLE_IT(husart, USART_IT_ERR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    /* Send dummy byte in order to generate the clock for the slave to send data */
+    husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);    
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). 
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @param  pTxData: Pointer to data transmitted buffer
+  * @param  pRxData: Pointer to data received buffer 
+  * @param  Size: Amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size)
+{
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) 
+    {
+      return HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pRxBuffPtr = pRxData;
+    husart->RxXferSize = Size;
+    husart->RxXferCount = Size;
+    husart->pTxBuffPtr = pTxData;
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+    /* Enable the USART Data Register not empty Interrupt */
+    __USART_ENABLE_IT(husart, USART_IT_RXNE); 
+
+    /* Enable the USART Parity Error Interrupt */
+    __USART_ENABLE_IT(husart, USART_IT_PE);
+
+    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+    __USART_ENABLE_IT(husart, USART_IT_ERR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    /* Enable the USART Transmit Complete Interrupt */
+    __USART_ENABLE_IT(husart, USART_IT_TC);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY; 
+  }
+}
+
+/**
+  * @brief  Simplex Send an amount of data in non-blocking mode. 
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @param  pTxData: Pointer to data buffer
+  * @param  Size: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+{
+  uint32_t *tmp;
+  
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pTxData == NULL) || (Size == 0)) 
+    {
+      return HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(husart);  
+
+    husart->pTxBuffPtr = pTxData;
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX;
+
+    /* Set the USART DMA transfer complete callback */
+    husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+    /* Set the USART DMA Half transfer complete callback */
+    husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+    /* Set the DMA error callback */
+    husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+    /* Enable the USART transmit DMA Stream */
+    tmp = (uint32_t*)&pTxData;
+    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the USART CR3 register */
+    husart->Instance->CR3 |= USART_CR3_DMAT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Full-Duplex Receive an amount of data in non-blocking mode. 
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @param  pRxData: Pointer to data buffer
+  * @param  Size: Amount of data to be received
+  * @retval HAL status
+  * @note   The USART DMA transmit stream must be configured in order to generate the clock for the slave.
+  * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+  */
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+  uint32_t *tmp;
+  
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pRxData == NULL) || (Size == 0)) 
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pRxBuffPtr = pRxData;
+    husart->RxXferSize = Size;
+    husart->pTxBuffPtr = pRxData;
+    husart->TxXferSize = Size;
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_RX;
+
+    /* Set the USART DMA Rx transfer complete callback */
+    husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+    /* Set the USART DMA Half transfer complete callback */
+    husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+    /* Set the USART DMA Rx transfer error callback */
+    husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+    /* Enable the USART receive DMA Stream */
+    tmp = (uint32_t*)&pRxData;
+    HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
+
+    /* Enable the USART transmit DMA Stream: the transmit stream is used in order
+       to generate in the non-blocking mode the clock to the slave device, 
+       this mode isn't a simplex receive mode but a full-duplex receive one */
+    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
+       in the USART CR3 register */
+    husart->Instance->CR3 |= USART_CR3_DMAR;
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the USART CR3 register */
+    husart->Instance->CR3 |= USART_CR3_DMAT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Full-Duplex Transmit Receive an amount of data in non-blocking mode. 
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @param  pTxData: Pointer to data transmitted buffer
+  * @param  pRxData: Pointer to data received buffer 
+  * @param  Size: Amount of data to be received
+  * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+  uint32_t *tmp;
+  
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) 
+    {
+      return HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pRxBuffPtr = pRxData;
+    husart->RxXferSize = Size;
+    husart->pTxBuffPtr = pTxData;
+    husart->TxXferSize = Size;
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+    /* Set the USART DMA Rx transfer complete callback */
+    husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+    /* Set the USART DMA Half transfer complete callback */
+    husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+    /* Set the USART DMA Tx transfer complete callback */
+    husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+    /* Set the USART DMA Half transfer complete callback */
+    husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+    /* Set the USART DMA Tx transfer error callback */
+    husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+    /* Set the USART DMA Rx transfer error callback */
+    husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+    /* Enable the USART receive DMA Stream */
+    tmp = (uint32_t*)&pRxData;
+    HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
+
+    /* Enable the USART transmit DMA Stream */
+    tmp = (uint32_t*)&pTxData;
+    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
+       in the USART CR3 register */
+    husart->Instance->CR3 |= USART_CR3_DMAR;
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the USART CR3 register */
+    husart->Instance->CR3 |= USART_CR3_DMAT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Pauses the DMA Transfer.
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
+{
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  if(husart->State == HAL_USART_STATE_BUSY_TX)
+  {
+    /* Disable the USART DMA Tx request */
+    husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+  }
+  else if(husart->State == HAL_USART_STATE_BUSY_RX)
+  {
+    /* Disable the USART DMA Rx request */
+    husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+  }
+  else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+  {
+    /* Disable the USART DMA Tx request */
+    husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+    /* Disable the USART DMA Rx request */
+    husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK; 
+}
+
+/**
+  * @brief Resumes the DMA Transfer.
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
+{
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  if(husart->State == HAL_USART_STATE_BUSY_TX)
+  {
+    /* Enable the USART DMA Tx request */
+    husart->Instance->CR3 |= USART_CR3_DMAT;
+  }
+  else if(husart->State == HAL_USART_STATE_BUSY_RX)
+  {
+    /* Enable the USART DMA Rx request */
+    husart->Instance->CR3 |= USART_CR3_DMAR;
+  }
+  else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+  {
+    /* Enable the USART DMA Rx request  before the DMA Tx request */
+    husart->Instance->CR3 |= USART_CR3_DMAR;
+    /* Enable the USART DMA Tx request */
+    husart->Instance->CR3 |= USART_CR3_DMAT;
+  }
+
+  /* If the USART peripheral is still not enabled, enable it */
+  if ((husart->Instance->CR1 & USART_CR1_UE) == 0)
+  {
+    /* Enable USART peripheral */
+    __USART_ENABLE(husart);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Stops the DMA Transfer.
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
+{
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  /* Disable the USART Tx/Rx DMA requests */
+  husart->Instance->CR3 &= ~USART_CR3_DMAT;
+  husart->Instance->CR3 &= ~USART_CR3_DMAR;
+
+  /* Abort the USART DMA Tx Stream */
+  if(husart->hdmatx != NULL)
+  {
+    HAL_DMA_Abort(husart->hdmatx);
+  }
+  /* Abort the USART DMA Rx Stream */
+  if(husart->hdmarx != NULL)
+  {  
+    HAL_DMA_Abort(husart->hdmarx);
+  }
+  /* Disable USART peripheral */
+  __USART_DISABLE(husart);
+
+  husart->State = HAL_USART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles USART interrupt request.
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval None
+  */
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
+{
+  uint32_t tmp1 = 0, tmp2 = 0;
+  
+  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_PE);
+  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE);
+  /* USART parity error interrupt occurred -----------------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET))
+  {
+    __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_PE);
+    husart->ErrorCode |= HAL_USART_ERROR_PE;
+  }
+
+  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_FE);
+  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR);
+  /* USART frame error interrupt occurred ------------------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET))
+  {
+    __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_FE);
+    husart->ErrorCode |= HAL_USART_ERROR_FE;
+  }
+
+  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_NE);
+  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR);
+  /* USART noise error interrupt occurred ------------------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET))
+  {
+    __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_NE);
+    husart->ErrorCode |= HAL_USART_ERROR_NE;
+  }
+
+  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_ORE);
+  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR);
+  /* USART Over-Run interrupt occurred ---------------------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET))
+  {
+    __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_ORE);
+    husart->ErrorCode |= HAL_USART_ERROR_ORE;
+  }
+
+  if(husart->ErrorCode != HAL_USART_ERROR_NONE)
+  {
+    /* Set the USART state ready to be able to start again the process */
+    husart->State = HAL_USART_STATE_READY;
+    
+    HAL_USART_ErrorCallback(husart);
+  }
+
+  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE);
+  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE);
+  /* USART in mode Receiver --------------------------------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET))
+  {
+    if(husart->State == HAL_USART_STATE_BUSY_RX)
+    {
+      USART_Receive_IT(husart);
+    }
+    else
+    {
+      USART_TransmitReceive_IT(husart);
+    }
+  }
+
+  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TC);
+  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC);
+  /* USART in mode Transmitter -----------------------------------------------*/
+  if((tmp1 != RESET) && (tmp2 != RESET))
+  {
+    if(husart->State == HAL_USART_STATE_BUSY_TX)
+    {
+      USART_Transmit_IT(husart);
+    }
+    else
+    {
+      USART_TransmitReceive_IT(husart);
+    }
+  }
+}
+
+/**
+  * @brief  Tx Transfer completed callbacks.
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval None
+  */
+ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_USART_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callbacks.
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval None
+  */
+ __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_USART_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callbacks.
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval None
+  */
+__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_USART_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Half Transfer completed callbacks.
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval None
+  */
+__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_USART_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx/Rx Transfers completed callback for the non-blocking process.
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval None
+  */
+__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_USART_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  USART error callbacks.
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval None
+  */
+ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_USART_ErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group3 Peripheral State and Errors functions 
+  *  @brief   USART State and Errors functions 
+  *
+@verbatim   
+  ==============================================================================
+                  ##### Peripheral State and Errors functions #####
+  ==============================================================================  
+  [..]
+    This subsection provides a set of functions allowing to return the State of 
+    USART communication
+    process, return Peripheral Errors occurred during communication process
+     (+) HAL_USART_GetState() API can be helpful to check in run-time the state 
+         of the USART peripheral.
+     (+) HAL_USART_GetError() check in run-time errors that could be occurred during 
+         communication. 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the USART state.
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval HAL state
+  */
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
+{
+  return husart->State;
+}
+
+/**
+  * @brief  Return the USART error code
+  * @param  husart : pointer to a USART_HandleTypeDef structure that contains
+  *              the configuration information for the specified USART.
+  * @retval USART Error Code
+  */
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
+{
+  return husart->ErrorCode;
+}
+
+/**
+  * @}
+  */
+  
+
+/**
+  * @brief  DMA USART transmit process complete callback. 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  husart->TxXferCount = 0;
+  if(husart->State == HAL_USART_STATE_BUSY_TX)
+  {
+    /* Wait for USART TC Flag */
+    if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TIMEOUT_VALUE) != HAL_OK)
+    {
+      /* Timeout occurred */ 
+      husart->State = HAL_USART_STATE_TIMEOUT;
+      HAL_USART_ErrorCallback(husart);
+    }
+    else
+    {
+      /* No Timeout */
+      /* Disable the DMA transfer for transmit request by setting the DMAT bit
+       in the USART CR3 register */
+      husart->Instance->CR3 &= ~(USART_CR3_DMAT);
+      husart->State= HAL_USART_STATE_READY;
+    }
+  }
+  /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/
+  else
+  {
+    husart->State= HAL_USART_STATE_BUSY_RX;
+    HAL_USART_TxCpltCallback(husart);
+  }
+}
+
+/**
+  * @brief DMA USART transmit process half complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  HAL_USART_TxHalfCpltCallback(husart);
+}
+
+/**
+  * @brief  DMA USART receive process complete callback. 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)   
+{
+  USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  husart->RxXferCount = 0;
+
+  /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit 
+  in the USART CR3 register */
+  husart->Instance->CR3 &= ~(USART_CR3_DMAR);
+  husart->Instance->CR3 &= ~(USART_CR3_DMAT);
+
+  husart->State= HAL_USART_STATE_READY;
+  
+  HAL_USART_RxCpltCallback(husart);
+}
+
+/**
+  * @brief DMA USART receive process half complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  HAL_USART_RxHalfCpltCallback(husart); 
+}
+
+/**
+  * @brief  DMA USART communication error callback. 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void USART_DMAError(DMA_HandleTypeDef *hdma)   
+{
+  USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  husart->RxXferCount = 0;
+  husart->TxXferCount = 0;
+  husart->ErrorCode |= HAL_USART_ERROR_DMA;
+  husart->State= HAL_USART_STATE_READY;
+  
+  HAL_USART_ErrorCallback(husart);
+}
+
+/**
+  * @brief  This function handles USART Communication Timeout.
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @param  Flag: specifies the USART flag to check.
+  * @param  Status: The new Flag status (SET or RESET).
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+  uint32_t timeout = 0;
+
+  timeout = HAL_GetTick() + Timeout;
+
+  /* Wait until flag is set */
+  if(Status == RESET)
+  {
+    while(__HAL_USART_GET_FLAG(husart, Flag) == RESET)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+          __USART_DISABLE_IT(husart, USART_IT_TXE);
+          __USART_DISABLE_IT(husart, USART_IT_RXNE);
+          __USART_DISABLE_IT(husart, USART_IT_PE);
+          __USART_DISABLE_IT(husart, USART_IT_ERR);
+
+          husart->State= HAL_USART_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(husart);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  else
+  {
+    while(__HAL_USART_GET_FLAG(husart, Flag) != RESET)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(HAL_GetTick() >= timeout)
+        {
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+          __USART_DISABLE_IT(husart, USART_IT_TXE);
+          __USART_DISABLE_IT(husart, USART_IT_RXNE);
+          __USART_DISABLE_IT(husart, USART_IT_PE);
+          __USART_DISABLE_IT(husart, USART_IT_ERR);
+
+          husart->State= HAL_USART_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(husart);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+  
+/**
+  * @brief  Simplex Send an amount of data in non-blocking mode. 
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval HAL status
+  * @note   The USART errors are not managed to avoid the overrun error.
+  */
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
+{
+  uint16_t* tmp;
+ 
+  if(husart->State == HAL_USART_STATE_BUSY_TX)
+  {
+    if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+    {
+      tmp = (uint16_t*) husart->pTxBuffPtr;
+      husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
+      if(husart->Init.Parity == USART_PARITY_NONE)
+      {
+        husart->pTxBuffPtr += 2;
+      }
+      else
+      {
+        husart->pTxBuffPtr += 1;
+      }
+    } 
+    else
+    { 
+      husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF);
+    }
+    
+    if(--husart->TxXferCount == 0)
+    {
+      /* Disable the USART Transmit Complete Interrupt */
+      __USART_DISABLE_IT(husart, USART_IT_TC);
+
+      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+      __USART_DISABLE_IT(husart, USART_IT_ERR);
+
+      husart->State = HAL_USART_STATE_READY;
+
+      HAL_USART_TxCpltCallback(husart);
+
+      return HAL_OK;
+    }
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Simplex Receive an amount of data in non-blocking mode. 
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
+{
+  uint16_t* tmp;
+  if(husart->State == HAL_USART_STATE_BUSY_RX)
+  {
+    if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+    {
+      tmp = (uint16_t*) husart->pRxBuffPtr;
+      if(husart->Init.Parity == USART_PARITY_NONE)
+      {
+        *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
+        husart->pRxBuffPtr += 2;
+      }
+      else
+      {
+        *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
+        husart->pRxBuffPtr += 1;
+      }
+      if(--husart->RxXferCount != 0x00) 
+      {
+        /* Send dummy byte in order to generate the clock for the slave to send the next data */
+        husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF); 
+      }
+    } 
+    else
+    {
+      if(husart->Init.Parity == USART_PARITY_NONE)
+      {
+        *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
+      }
+      else
+      {
+        *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
+      }
+
+      if(--husart->RxXferCount != 0x00) 
+      {
+        /* Send dummy byte in order to generate the clock for the slave to send the next data */
+        husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FF);  
+      }
+    }
+
+    if(husart->RxXferCount == 0)
+    {
+      /* Disable the USART RXNE Interrupt */
+      __USART_DISABLE_IT(husart, USART_IT_RXNE);
+
+      /* Disable the USART Parity Error Interrupt */
+      __USART_DISABLE_IT(husart, USART_IT_PE);
+
+      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+      __USART_DISABLE_IT(husart, USART_IT_ERR);
+
+      husart->State = HAL_USART_STATE_READY;
+      HAL_USART_RxCpltCallback(husart);
+      
+      return HAL_OK;
+    }
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY; 
+  }
+}
+
+/**
+  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). 
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
+{
+  uint16_t* tmp;
+
+  if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+  {
+    /* Process Locked */
+    __HAL_LOCK(husart);
+    if(husart->TxXferCount != 0x00)
+    {
+      if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
+      {
+        if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+        {
+          tmp = (uint16_t*) husart->pTxBuffPtr;
+          husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
+          if(husart->Init.Parity == USART_PARITY_NONE)
+          {
+            husart->pTxBuffPtr += 2;
+          }
+          else
+          {
+            husart->pTxBuffPtr += 1;
+          }
+        } 
+        else
+        {
+          husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF);
+        }
+        husart->TxXferCount--;
+
+        /* Check the latest data transmitted */
+        if(husart->TxXferCount == 0)
+        {
+           __USART_DISABLE_IT(husart, USART_IT_TC);
+        }
+      }
+    }
+
+    if(husart->RxXferCount != 0x00)
+    {
+      if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
+      {
+        if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+        {
+          tmp = (uint16_t*) husart->pRxBuffPtr;
+          if(husart->Init.Parity == USART_PARITY_NONE)
+          {
+            *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
+            husart->pRxBuffPtr += 2;
+          }
+          else
+          {
+            *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
+            husart->pRxBuffPtr += 1;
+          }
+        } 
+        else
+        {
+          if(husart->Init.Parity == USART_PARITY_NONE)
+          {
+            *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
+          }
+          else
+          {
+            *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
+          }
+        }
+        husart->RxXferCount--;
+      }
+    }
+
+    /* Check the latest data received */
+    if(husart->RxXferCount == 0)
+    {
+      __USART_DISABLE_IT(husart, USART_IT_RXNE);
+
+      /* Disable the USART Parity Error Interrupt */
+      __USART_DISABLE_IT(husart, USART_IT_PE);
+
+      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+      __USART_DISABLE_IT(husart, USART_IT_ERR);
+
+      husart->State = HAL_USART_STATE_READY;
+
+      /* Call the Process Unlocked before calling the Tx\Rx callback API to give the possibility to
+         start again the Transmission\Reception under the Tx\Rx callback API */
+      __HAL_UNLOCK(husart);
+
+      HAL_USART_TxRxCpltCallback(husart);
+
+      return HAL_OK;
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY; 
+  }
+}
+
+/**
+  * @brief  Configures the USART peripheral. 
+  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval None
+  */
+static void USART_SetConfig(USART_HandleTypeDef *husart)
+{
+  uint32_t tmpreg = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_USART_INSTANCE(husart->Instance));
+  assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
+  assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
+  assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
+  assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));  
+  assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
+  assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
+  assert_param(IS_USART_PARITY(husart->Init.Parity));
+  assert_param(IS_USART_MODE(husart->Init.Mode));
+
+  /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
+     receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
+  husart->Instance->CR1 &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
+
+  /*---------------------------- USART CR2 Configuration ---------------------*/
+  tmpreg = husart->Instance->CR2;
+  /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+  tmpreg &= (uint32_t)~((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP));
+  /* Configure the USART Clock, CPOL, CPHA and LastBit -----------------------*/
+  /* Set CPOL bit according to husart->Init.CLKPolarity value */
+  /* Set CPHA bit according to husart->Init.CLKPhase value */
+  /* Set LBCL bit according to husart->Init.CLKLastBit value */
+  /* Set Stop Bits: Set STOP[13:12] bits according to husart->Init.StopBits value */
+  tmpreg |= (uint32_t)(USART_CLOCK_ENABLED| husart->Init.CLKPolarity | 
+                      husart->Init.CLKPhase| husart->Init.CLKLastBit | husart->Init.StopBits);
+  /* Write to USART CR2 */
+  husart->Instance->CR2 = (uint32_t)tmpreg;
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  tmpreg = husart->Instance->CR1;
+
+  /* Clear M, PCE, PS, TE and RE bits */
+  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
+                                   USART_CR1_RE));
+
+  /* Configure the USART Word Length, Parity and mode: 
+     Set the M bits according to husart->Init.WordLength value 
+     Set PCE and PS bits according to husart->Init.Parity value
+     Set TE and RE bits according to husart->Init.Mode value */
+  tmpreg |= (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode;
+
+  /* Write to USART CR1 */
+  husart->Instance->CR1 = (uint32_t)tmpreg;
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/  
+  /* Clear CTSE and RTSE bits */
+  husart->Instance->CR3 &= (uint32_t)~((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  if((husart->Instance == USART1) || (husart->Instance == USART6))
+  {
+    husart->Instance->BRR = __USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
+  }
+  else
+  {
+    husart->Instance->BRR = __USART_BRR(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_USART_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_usart.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,457 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_usart.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of USART HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_USART_H
+#define __STM32F4xx_HAL_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup USART
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** 
+  * @brief USART Init Structure definition  
+  */ 
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                           - IntegerDivider = ((PCLKx) / (8 * (husart->Init.BaudRate)))
+                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_Word_Length */
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_Stop_Bits */
+
+  uint32_t Parity;                   /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+ 
+  uint32_t Mode;                      /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_Mode */
+
+  uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref USART_Clock_Polarity */
+
+  uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref USART_Clock_Phase */
+
+  uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref USART_Last_Bit */
+}USART_InitTypeDef;
+
+/** 
+  * @brief HAL State structures definition  
+  */ 
+typedef enum
+{
+  HAL_USART_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized   */
+  HAL_USART_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
+  HAL_USART_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing */   
+  HAL_USART_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing */ 
+  HAL_USART_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing */
+  HAL_USART_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission Reception process is ongoing */
+  HAL_USART_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
+  HAL_USART_STATE_ERROR             = 0x04     /*!< Error */      
+}HAL_USART_StateTypeDef;
+
+/** 
+  * @brief  HAL USART Error Code structure definition  
+  */ 
+typedef enum
+{
+  HAL_USART_ERROR_NONE      = 0x00,    /*!< No error            */
+  HAL_USART_ERROR_PE        = 0x01,    /*!< Parity error        */
+  HAL_USART_ERROR_NE        = 0x02,    /*!< Noise error         */
+  HAL_USART_ERROR_FE        = 0x04,    /*!< frame error         */
+  HAL_USART_ERROR_ORE       = 0x08,    /*!< Overrun error       */
+  HAL_USART_ERROR_DMA       = 0x10     /*!< DMA transfer error  */
+}HAL_USART_ErrorTypeDef;
+
+/** 
+  * @brief  USART handle Structure definition  
+  */  
+typedef struct
+{
+  USART_TypeDef                 *Instance;        /* USART registers base address        */
+  
+  USART_InitTypeDef             Init;             /* Usart communication parameters      */
+  
+  uint8_t                       *pTxBuffPtr;      /* Pointer to Usart Tx transfer Buffer */
+  
+  uint16_t                      TxXferSize;       /* Usart Tx Transfer size              */
+  
+  __IO uint16_t                 TxXferCount;      /* Usart Tx Transfer Counter           */
+  
+  uint8_t                       *pRxBuffPtr;      /* Pointer to Usart Rx transfer Buffer */
+  
+  uint16_t                      RxXferSize;       /* Usart Rx Transfer size              */
+  
+  __IO uint16_t                 RxXferCount;      /* Usart Rx Transfer Counter           */  
+  
+  DMA_HandleTypeDef             *hdmatx;          /* Usart Tx DMA Handle parameters      */
+    
+  DMA_HandleTypeDef             *hdmarx;          /* Usart Rx DMA Handle parameters      */
+  
+  HAL_LockTypeDef                Lock;            /* Locking object                      */
+  
+  __IO HAL_USART_StateTypeDef    State;           /* Usart communication state           */
+  
+  __IO HAL_USART_ErrorTypeDef    ErrorCode;        /* USART Error code                    */
+  
+}USART_HandleTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_Exported_Constants
+  * @{
+  */
+
+/** @defgroup USART_Word_Length 
+  * @{
+  */
+#define USART_WORDLENGTH_8B                  ((uint32_t)0x00000000)
+#define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
+                                          ((LENGTH) == USART_WORDLENGTH_9B))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Stop_Bits 
+  * @{
+  */
+#define USART_STOPBITS_1                     ((uint32_t)0x00000000)
+#define USART_STOPBITS_0_5                   ((uint32_t)USART_CR2_STOP_0)
+#define USART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
+#define USART_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
+                                         ((STOPBITS) == USART_STOPBITS_0_5) || \
+                                         ((STOPBITS) == USART_STOPBITS_1_5) || \
+                                         ((STOPBITS) == USART_STOPBITS_2))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Parity 
+  * @{
+  */ 
+#define USART_PARITY_NONE                    ((uint32_t)0x00000000)
+#define USART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
+#define USART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
+                                     ((PARITY) == USART_PARITY_EVEN) || \
+                                     ((PARITY) == USART_PARITY_ODD))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Mode 
+  * @{
+  */ 
+#define USART_MODE_RX                        ((uint32_t)USART_CR1_RE)
+#define USART_MODE_TX                        ((uint32_t)USART_CR1_TE)
+#define USART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFF3) == 0x00) && ((MODE) != (uint32_t)0x00))
+/**
+  * @}
+  */
+    
+/** @defgroup USART_Clock 
+  * @{
+  */ 
+#define USART_CLOCK_DISABLED                 ((uint32_t)0x00000000)
+#define USART_CLOCK_ENABLED                  ((uint32_t)USART_CR2_CLKEN)
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLED) || \
+                                   ((CLOCK) == USART_CLOCK_ENABLED))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock_Polarity 
+  * @{
+  */
+#define USART_POLARITY_LOW                   ((uint32_t)0x00000000)
+#define USART_POLARITY_HIGH                  ((uint32_t)USART_CR2_CPOL)
+#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock_Phase
+  * @{
+  */
+#define USART_PHASE_1EDGE                    ((uint32_t)0x00000000)
+#define USART_PHASE_2EDGE                    ((uint32_t)USART_CR2_CPHA)
+#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Last_Bit
+  * @{
+  */
+#define USART_LASTBIT_DISABLE                ((uint32_t)0x00000000)
+#define USART_LASTBIT_ENABLE                 ((uint32_t)USART_CR2_LBCL)
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
+                                       ((LASTBIT) == USART_LASTBIT_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup USART_NACK_State 
+  * @{
+  */
+#define USARTNACK_ENABLED           ((uint32_t)USART_CR3_NACK)
+#define USARTNACK_DISABLED          ((uint32_t)0x00000000)
+#define IS_USART_NACK_STATE(NACK) (((NACK) == USARTNACK_ENABLED) || \
+                                       ((NACK) == USARTNACK_DISABLED))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Flags 
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the SR register
+  * @{
+  */
+
+#define USART_FLAG_TXE                       ((uint32_t)0x00000080)
+#define USART_FLAG_TC                        ((uint32_t)0x00000040)
+#define USART_FLAG_RXNE                      ((uint32_t)0x00000020)
+#define USART_FLAG_IDLE                      ((uint32_t)0x00000010)
+#define USART_FLAG_ORE                       ((uint32_t)0x00000008)
+#define USART_FLAG_NE                        ((uint32_t)0x00000004)
+#define USART_FLAG_FE                        ((uint32_t)0x00000002)
+#define USART_FLAG_PE                        ((uint32_t)0x00000001)
+/**
+  * @}
+  */
+
+/** @defgroup USART_Interrupt_definition 
+  *        Elements values convention: 0xY000XXXX
+  *           - XXXX  : Interrupt mask in the XX register
+  *           - Y  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *
+  * @{
+  */  
+#define USART_IT_PE                          ((uint32_t)0x10000100)
+#define USART_IT_TXE                         ((uint32_t)0x10000080)
+#define USART_IT_TC                          ((uint32_t)0x10000040)
+#define USART_IT_RXNE                        ((uint32_t)0x10000020)
+#define USART_IT_IDLE                        ((uint32_t)0x10000010)
+
+#define USART_IT_LBD                         ((uint32_t)0x20000040)
+#define USART_IT_CTS                         ((uint32_t)0x30000400)
+
+#define USART_IT_ERR                         ((uint32_t)0x30000001)
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @brief Reset USART handle state
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+  * @retval None
+  */
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
+
+/** @brief  Checks whether the specified Smartcard flag is set or not.
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg USART_FLAG_TXE:  Transmit data register empty flag
+  *            @arg USART_FLAG_TC:   Transmission Complete flag
+  *            @arg USART_FLAG_RXNE: Receive data register not empty flag
+  *            @arg USART_FLAG_IDLE: Idle Line detection flag
+  *            @arg USART_FLAG_ORE:  OverRun Error flag
+  *            @arg USART_FLAG_NE:   Noise Error flag
+  *            @arg USART_FLAG_FE:   Framing Error flag
+  *            @arg USART_FLAG_PE:   Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+
+#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clears the specified Smartcard pending flags.
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+  * @param  __FLAG__: specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg USART_FLAG_TC:   Transmission Complete flag.
+  *            @arg USART_FLAG_RXNE: Receive data register not empty flag.
+  *   
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
+  *          error) and IDLE (Idle line detected) flags are cleared by software 
+  *          sequence: a read operation to USART_SR register followed by a read
+  *          operation to USART_DR register.
+  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
+  * @note   TC flag can be also cleared by software sequence: a read operation to 
+  *          USART_SR register followed by a write operation to USART_DR register.
+  * @note   TXE flag is cleared only by a write to the USART_DR register.
+  *   
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+
+
+/** @brief  Enables or disables the specified Usart interrupts.
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+  * @param  __INTERRUPT__: specifies the USART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt
+  *            @arg USART_IT_TC:   Transmission complete interrupt
+  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg USART_IT_IDLE: Idle line detection interrupt
+  *            @arg USART_IT_PE:   Parity Error interrupt
+  *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  * @param  NewState: new state of the specified Usart interrupt.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+#define USART_IT_MASK  ((uint32_t)0x0000FFFF)
+#define __USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+                                                        (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & USART_IT_MASK)): \
+                                                        ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
+#define __USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+                                                        (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+                                                        ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
+
+    
+/** @brief  Checks whether the specified Usart interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the USART Handle.
+  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+  * @param  __IT__: specifies the USART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg USART_IT_TXE: Transmit Data Register empty interrupt
+  *            @arg USART_IT_TC:  Transmission complete interrupt
+  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg USART_IT_IDLE: Idle line detection interrupt
+  *            @arg USART_IT_ERR: Error interrupt
+  *            @arg USART_IT_PE: Parity Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
+                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
+
+#define __USART_ENABLE(__HANDLE__)               ( (__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+#define __USART_DISABLE(__HANDLE__)              ( (__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+    
+#define __DIV(_PCLK_, _BAUD_)                        (((_PCLK_)*25)/(4*(_BAUD_)))
+#define __DIVMANT(_PCLK_, _BAUD_)                    (__DIV((_PCLK_), (_BAUD_))/100)
+#define __DIVFRAQ(_PCLK_, _BAUD_)                    (((__DIV((_PCLK_), (_BAUD_)) - (__DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define __USART_BRR(_PCLK_, _BAUD_)              ((__DIVMANT((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
+                                 
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
+void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+
+/* Peripheral State functions  **************************************************/
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
+uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,462 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_wwdg.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   WWDG HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Window Watchdog (WWDG) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State functions       
+  @verbatim
+  ==============================================================================
+                      ##### WWDG specific features #####
+  ==============================================================================
+  [..] 
+    Once enabled the WWDG generates a system reset on expiry of a programmed
+    time period, unless the program refreshes the counter (downcounter) 
+    before reaching 0x3F value (i.e. a reset is generated when the counter
+    value rolls over from 0x40 to 0x3F). 
+       
+    (+) An MCU reset is also generated if the counter value is refreshed
+        before the counter has reached the refresh window value. This 
+        implies that the counter must be refreshed in a limited window.
+    (+) Once enabled the WWDG cannot be disabled except by a system reset.
+    (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
+        reset occurs.               
+    (+) The WWDG counter input clock is derived from the APB clock divided 
+        by a programmable prescaler.
+    (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
+    (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock
+    (+) WWDG Counter refresh is allowed between the following limits :
+        (++) min time (mS) = 1000 * (Counter – Window) / WWDG clock
+        (++) max time (mS) = 1000 * (Counter – 0x40) / WWDG clock
+    
+    (+) Min-max timeout value at 50 MHz(PCLK1): 81.9 us / 41.9 ms 
+
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (+) Enable WWDG APB1 clock using __WWDG_CLK_ENABLE().
+    (+) Set the WWDG prescaler, refresh window and counter value 
+        using HAL_WWDG_Init() function.
+    (+) Start the WWDG using HAL_WWDG_Start() function.
+        When the WWDG is enabled the counter value should be configured to 
+        a value greater than 0x40 to prevent generating an immediate reset.
+    (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is 
+        generated when the counter reaches 0x40, and then start the WWDG using
+        HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can 
+        add his own code by customization of function pointer HAL_WWDG_WakeupCallback
+        Once enabled, EWI interrupt cannot be disabled except by a system reset.          
+    (+) Then the application program must refresh the WWDG counter at regular
+        intervals during normal operation to prevent an MCU reset, using
+        HAL_WWDG_Refresh() function. This operation must occur only when
+        the counter is lower than the refresh window value already programmed.
+        
+     *** WWDG HAL driver macros list ***
+     ==================================
+     [..]
+       Below the list of most used macros in WWDG HAL driver.
+       
+      (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral 
+      (+) __HAL_IWDG_GET_FLAG: Get the selected WWDG's flag status
+      (+) __HAL_IWDG_CLEAR_FLAG: Clear the WWDG's pending flags 
+      (+) __HAL_IWDG_RELOAD_COUNTER: Enables the WWDG early wakeup interrupt  
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup WWDG 
+  * @brief WWDG HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup WWDG_Private_Functions
+  * @{
+  */
+
+/** @defgroup WWDG_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions. 
+ *
+@verbatim    
+  ==============================================================================
+          ##### Initialization and de-initialization functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to:
+    (+) Initialize the WWDG according to the specified parameters 
+        in the WWDG_InitTypeDef and create the associated handle
+    (+) DeInitialize the WWDG peripheral
+    (+) Initialize the WWDG MSP
+    (+) DeInitialize the WWDG MSP 
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the WWDG according to the specified
+  *         parameters in the WWDG_InitTypeDef and creates the associated handle.
+  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+  *              the configuration information for the specified WWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
+{
+  uint32_t tmp = 0;
+  
+  /* Check the WWDG handle allocation */
+  if(hwwdg == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
+  assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); 
+  assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); 
+  
+  if(hwwdg->State == HAL_WWDG_STATE_RESET)
+  {
+    /* Init the low level hardware */
+    HAL_WWDG_MspInit(hwwdg);
+  }
+  
+  /* Change WWDG peripheral state */
+  hwwdg->State = HAL_WWDG_STATE_BUSY;
+
+  /* Set WWDG Prescaler and Window */
+  /* Get the CFR register value */
+  tmp = hwwdg->Instance->CFR;
+  
+  /* Clear WDGTB[1:0] and W[6:0] bits */
+  tmp &= ((uint32_t)~(WWDG_CFR_WDGTB | WWDG_CFR_W));
+  
+  /* Prepare the WWDG Prescaler and Window parameters */
+  tmp |= hwwdg->Init.Prescaler | hwwdg->Init.Window;
+  
+  /* Write to WWDG CFR */
+  hwwdg->Instance->CFR = tmp;   
+ 
+  /* Set WWDG Counter */
+  /* Get the CR register value */
+  tmp = hwwdg->Instance->CR;
+  
+  /* Clear T[6:0] bits */
+  tmp &= ((uint32_t)~(WWDG_CR_T));
+  
+  /* Prepare the WWDG Counter parameter */
+  tmp |= (hwwdg->Init.Counter);  
+  
+  /* Write to WWDG CR */
+  hwwdg->Instance->CR = tmp;  
+   
+  /* Change WWDG peripheral state */
+  hwwdg->State = HAL_WWDG_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the WWDG peripheral. 
+  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+  *              the configuration information for the specified WWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg)
+{   
+  /* Change WWDG peripheral state */  
+  hwwdg->State = HAL_WWDG_STATE_BUSY;
+  
+  /* DeInit the low level hardware */
+  HAL_WWDG_MspDeInit(hwwdg);
+  
+  /* Reset WWDG Control register */
+  hwwdg->Instance->CR  = (uint32_t)0x0000007F;
+  
+  /* Reset WWDG Configuration register */
+  hwwdg->Instance->CFR = (uint32_t)0x0000007F;
+  
+  /* Reset WWDG Status register */
+  hwwdg->Instance->SR  = 0; 
+  
+  /* Change WWDG peripheral state */    
+  hwwdg->State = HAL_WWDG_STATE_RESET; 
+
+  /* Release Lock */
+  __HAL_UNLOCK(hwwdg);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the WWDG MSP.
+  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+  *              the configuration information for the specified WWDG module.
+  * @retval None
+  */
+__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_WWDG_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the WWDG MSP.
+  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+  *              the configuration information for the specified WWDG module.
+  * @retval None
+  */
+__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_WWDG_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Group2 IO operation functions 
+ *  @brief    IO operation functions 
+ *
+@verbatim   
+  ==============================================================================
+                       ##### IO operation functions #####
+  ==============================================================================  
+  [..]  
+    This section provides functions allowing to:
+    (+) Start the WWDG.
+    (+) Refresh the WWDG.
+    (+) Handle WWDG interrupt request. 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the WWDG.
+  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+  *              the configuration information for the specified WWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Process Locked */
+  __HAL_LOCK(hwwdg); 
+  
+  /* Change WWDG peripheral state */  
+  hwwdg->State = HAL_WWDG_STATE_BUSY;
+
+  /* Enable the peripheral */
+  __HAL_WWDG_ENABLE(hwwdg);  
+  
+  /* Change WWDG peripheral state */    
+  hwwdg->State = HAL_WWDG_STATE_READY; 
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hwwdg);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the WWDG with interrupt enabled.
+  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+  *              the configuration information for the specified WWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg)
+{   
+  /* Process Locked */
+  __HAL_LOCK(hwwdg); 
+  
+  /* Change WWDG peripheral state */  
+  hwwdg->State = HAL_WWDG_STATE_BUSY;
+  
+  /* Enable the Early Wakeup Interrupt */ 
+  __HAL_WWDG_ENABLE_IT(WWDG_IT_EWI);
+
+  /* Enable the peripheral */
+  __HAL_WWDG_ENABLE(hwwdg);  
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Refreshes the WWDG.
+  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+  *              the configuration information for the specified WWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
+{
+  /* Process Locked */
+  __HAL_LOCK(hwwdg); 
+  
+  /* Change WWDG peripheral state */  
+  hwwdg->State = HAL_WWDG_STATE_BUSY;
+  
+  /* Check the parameters */
+  assert_param(IS_WWDG_COUNTER(Counter));
+  
+  /* Write to WWDG CR the WWDG Counter value to refresh with */
+  MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, Counter);
+  
+  /* Change WWDG peripheral state */    
+  hwwdg->State = HAL_WWDG_STATE_READY; 
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hwwdg);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handles WWDG interrupt request.
+  * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations 
+  *         or data logging must be performed before the actual reset is generated. 
+  *         The EWI interrupt is enabled using __HAL_WWDG_ENABLE_IT() macro.
+  *         When the downcounter reaches the value 0x40, and EWI interrupt is 
+  *         generated and the corresponding Interrupt Service Routine (ISR) can 
+  *         be used to trigger specific actions (such as communications or data 
+  *         logging), before resetting the device. 
+  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+  *              the configuration information for the specified WWDG module.
+  * @retval None
+  */
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
+{ 
+  /* WWDG Early Wakeup Interrupt occurred */   
+  if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+  {
+    /* Early Wakeup callback */ 
+    HAL_WWDG_WakeupCallback(hwwdg);
+    
+    /* Change WWDG peripheral state */
+    hwwdg->State = HAL_WWDG_STATE_READY; 
+    
+    /* Clear the WWDG Data Ready flag */
+    __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hwwdg);
+  }
+} 
+
+/**
+  * @brief  Early Wakeup WWDG callback.
+  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+  *              the configuration information for the specified WWDG module.
+  * @retval None
+  */
+__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)
+{
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_WWDG_WakeupCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Group3 Peripheral State functions 
+ *  @brief    Peripheral State functions. 
+ *
+@verbatim   
+  ==============================================================================
+                        ##### Peripheral State functions #####
+  ==============================================================================  
+  [..]
+    This subsection permits to get in run-time the status of the peripheral 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the WWDG state.
+  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+  *              the configuration information for the specified WWDG module.
+  * @retval HAL state
+  */
+HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg)
+{
+  return hwwdg->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_WWDG_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_wwdg.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,250 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_wwdg.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of WWDG HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_WWDG_H
+#define __STM32F4xx_HAL_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup WWDG
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** 
+  * @brief  WWDG HAL State Structure definition  
+  */ 
+typedef enum
+{
+  HAL_WWDG_STATE_RESET     = 0x00,  /*!< WWDG not yet initialized or disabled */
+  HAL_WWDG_STATE_READY     = 0x01,  /*!< WWDG initialized and ready for use   */
+  HAL_WWDG_STATE_BUSY      = 0x02,  /*!< WWDG internal process is ongoing     */ 
+  HAL_WWDG_STATE_TIMEOUT   = 0x03,  /*!< WWDG timeout state                   */
+  HAL_WWDG_STATE_ERROR     = 0x04   /*!< WWDG error state                     */
+    
+}HAL_WWDG_StateTypeDef;
+
+/** 
+  * @brief  WWDG Init structure definition  
+  */ 
+typedef struct
+{
+  uint32_t Prescaler;  /*!< Specifies the prescaler.  
+                            This parameter can be a value of @ref WWDG_Prescaler */
+  
+  uint32_t Window;     /*!< Specifies the WWDG window value to be compared to the downcounter.
+                            This parameter must be a number lower than Max_Data = 0x80 */ 
+  
+  uint32_t Counter;    /*!< Specifies the WWDG free-running downcounter value.
+                            This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */                                    
+
+}WWDG_InitTypeDef;
+
+/** 
+  * @brief  WWDG handle Structure definition  
+  */ 
+typedef struct
+{
+  WWDG_TypeDef                 *Instance;  /*!< Register base address    */ 
+  
+  WWDG_InitTypeDef             Init;       /*!< WWDG required parameters */
+  
+  HAL_LockTypeDef              Lock;       /*!< WWDG locking object      */
+  
+  __IO HAL_WWDG_StateTypeDef   State;      /*!< WWDG communication state */
+  
+}WWDG_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_BitAddress_AliasRegion
+  * @{
+  */
+
+/* --- CFR Register ---*/
+/* Alias word address of EWI bit */
+#define CFR_BASE   (uint32_t)(WWDG_BASE + 0x04)
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Interrupt_definition 
+  * @{
+  */ 
+#define WWDG_IT_EWI   ((uint32_t)WWDG_CFR_EWI)  
+
+#define IS_WWDG_IT(IT) ((IT) == WWDG_IT_EWI)
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Flag_definition 
+  * @brief WWDG Flag definition
+  * @{
+  */ 
+#define WWDG_FLAG_EWIF   ((uint32_t)0x0001)  /*!< Early wakeup interrupt flag */
+
+#define IS_WWDG_FLAG(FLAG) ((FLAG) == WWDG_FLAG_EWIF)) 
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Prescaler 
+  * @{
+  */ 
+#define WWDG_PRESCALER_1   ((uint32_t)0x00000000)  /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2   ((uint32_t)0x00000080)  /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4   ((uint32_t)0x00000100)  /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8   ((uint32_t)0x00000180)  /*!< WWDG counter clock = (PCLK1/4096)/8 */
+
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_PRESCALER_1) || \
+                                      ((PRESCALER) == WWDG_PRESCALER_2) || \
+                                      ((PRESCALER) == WWDG_PRESCALER_4) || \
+                                      ((PRESCALER) == WWDG_PRESCALER_8))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup WWDG_Window 
+  * @{
+  */ 
+#define IS_WWDG_WINDOW(WINDOW) ((WINDOW) <= 0x7F)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup WWDG_Counter 
+  * @{
+  */ 
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset WWDG handle state
+  * @param  __HANDLE__: WWDG handle
+  * @retval None
+  */
+#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
+
+/**
+  * @brief  Enables the WWDG peripheral.
+  * @param  __HANDLE__: WWDG handle
+  * @retval None
+  */
+#define __HAL_WWDG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  WWDG_CR_WDGA)
+
+/**
+  * @brief  Gets the selected WWDG's flag status.
+  * @param  __HANDLE__: WWDG handle
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+  * @retval The new state of WWDG_FLAG (SET or RESET).
+  */
+#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clears the WWDG's pending flags.
+  * @param  __HANDLE__: WWDG handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+  * @retval None
+  */
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) &= ~(__FLAG__))
+
+/**
+  * @brief  Enables the WWDG early wakeup interrupt.
+  * @note   Once enabled this interrupt cannot be disabled except by a system reset.
+  * @retval None
+  */
+#define __HAL_WWDG_ENABLE_IT(__INTERRUPT__) (*(__IO uint32_t *) CFR_BASE |= (__INTERRUPT__))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
+
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter);
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+
+/* Peripheral State functions  **************************************************/
+HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_WWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_fmc.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1274 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_fmc.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   FMC Low Layer HAL module driver.
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Flexible Memory Controller (FMC) peripheral memories:
+  *           + Initialization/de-initialization functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                        ##### FMC peripheral features #####
+  ==============================================================================
+  [..] The Flexible memory controller (FMC) includes three memory controllers:
+       (+) The NOR/PSRAM memory controller
+       (+) The NAND/PC Card memory controller
+       (+) The Synchronous DRAM (SDRAM) controller 
+       
+  [..] The FMC functional block makes the interface with synchronous and asynchronous static
+       memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
+       (+) to translate AHB transactions into the appropriate external device protocol
+       (+) to meet the access time requirements of the external memory devices
+   
+  [..] All external memories share the addresses, data and control signals with the controller.
+       Each external device is accessed by means of a unique Chip Select. The FMC performs
+       only one access at a time to an external device.
+       The main features of the FMC controller are the following:
+        (+) Interface with static-memory mapped devices including:
+           (++) Static random access memory (SRAM)
+           (++) Read-only memory (ROM)
+           (++) NOR Flash memory/OneNAND Flash memory
+           (++) PSRAM (4 memory banks)
+           (++) 16-bit PC Card compatible devices
+           (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
+                data
+        (+) Interface with synchronous DRAM (SDRAM) memories
+        (+) Independent Chip Select control for each memory bank
+        (+) Independent configuration for each memory bank
+                    
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FMC 
+  * @brief FMC driver modules
+  * @{
+  */
+
+#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup FMC_Private_Functions
+  * @{
+  */
+
+/** @defgroup FMC_NORSRAM Controller functions
+  * @brief    NORSRAM Controller functions 
+  *
+  @verbatim 
+  ==============================================================================   
+                   ##### How to use NORSRAM device driver #####
+  ==============================================================================
+ 
+  [..] 
+    This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
+    to run the NORSRAM external devices.
+      
+    (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() 
+    (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
+    (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
+    (+) FMC NORSRAM bank extended timing configuration using the function 
+        FMC_NORSRAM_Extended_Timing_Init()
+    (+) FMC NORSRAM bank enable/disable write operation using the functions
+        FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
+        
+
+@endverbatim
+  * @{
+  */
+       
+/** @defgroup HAL_FMC_NORSRAM_Group1 Initialization/de-initialization functions 
+  * @brief    Initialization and Configuration functions 
+  *
+  @verbatim    
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to:
+    (+) Initialize and configure the FMC NORSRAM interface
+    (+) De-initialize the FMC NORSRAM interface 
+    (+) Configure the FMC clock and associated GPIOs    
+ 
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initialize the FMC_NORSRAM device according to the specified
+  *         control parameters in the FMC_NORSRAM_InitTypeDef
+  * @param  Device: Pointer to NORSRAM device instance
+  * @param  Init: Pointer to NORSRAM Initialization structure   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
+{ 
+  uint32_t tmpr = 0;
+    
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
+  assert_param(IS_FMC_MUX(Init->DataAddressMux));
+  assert_param(IS_FMC_MEMORY(Init->MemoryType));
+  assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
+  assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
+  assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
+  assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
+  assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
+  assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
+  assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
+  assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
+  assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
+  assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
+  assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); 
+  
+  /* Set NORSRAM device control parameters */
+  tmpr = (uint32_t)(Init->DataAddressMux       |\
+                    Init->MemoryType           |\
+                    Init->MemoryDataWidth      |\
+                    Init->BurstAccessMode      |\
+                    Init->WaitSignalPolarity   |\
+                    Init->WrapMode             |\
+                    Init->WaitSignalActive     |\
+                    Init->WriteOperation       |\
+                    Init->WaitSignal           |\
+                    Init->ExtendedMode         |\
+                    Init->AsynchronousWait     |\
+                    Init->WriteBurst           |\
+                    Init->ContinuousClock
+                    );
+                    
+  if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
+  {
+    tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
+  }
+  
+  Device->BTCR[Init->NSBank] = tmpr;
+
+  /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
+  if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
+  { 
+    Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE; 
+    Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode  |\
+                                                  Init->ContinuousClock);                    
+  }                       
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DeInitialize the FMC_NORSRAM peripheral 
+  * @param  Device: Pointer to NORSRAM device instance
+  * @param  ExDevice: Pointer to NORSRAM extended mode device instance  
+  * @param  Bank: NORSRAM bank number  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
+  assert_param(IS_FMC_NORSRAM_BANK(Bank));
+  
+  /* Disable the FMC_NORSRAM device */
+  __FMC_NORSRAM_DISABLE(Device, Bank);
+  
+  /* De-initialize the FMC_NORSRAM device */
+  /* FMC_NORSRAM_BANK1 */
+  if(Bank == FMC_NORSRAM_BANK1)
+  {
+    Device->BTCR[Bank] = 0x000030DB;    
+  }
+  /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
+  else
+  {   
+    Device->BTCR[Bank] = 0x000030D2; 
+  }
+  
+  Device->BTCR[Bank + 1] = 0x0FFFFFFF;
+  ExDevice->BWTR[Bank]   = 0x0FFFFFFF;
+   
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initialize the FMC_NORSRAM Timing according to the specified
+  *         parameters in the FMC_NORSRAM_TimingTypeDef
+  * @param  Device: Pointer to NORSRAM device instance
+  * @param  Timing: Pointer to NORSRAM Timing structure
+  * @param  Bank: NORSRAM bank number  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
+{
+  uint32_t tmpr = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+  assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+  assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
+  assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+  assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
+  assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
+  assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
+  assert_param(IS_FMC_NORSRAM_BANK(Bank));
+  
+  /* Set FMC_NORSRAM device timing parameters */  
+  tmpr = (uint32_t)(Timing->AddressSetupTime                  |\
+                   ((Timing->AddressHoldTime) << 4)          |\
+                   ((Timing->DataSetupTime) << 8)            |\
+                   ((Timing->BusTurnAroundDuration) << 16)   |\
+                   (((Timing->CLKDivision)-1) << 20)         |\
+                   (((Timing->DataLatency)-2) << 24)         |\
+                    (Timing->AccessMode)
+                    );
+  
+  Device->BTCR[Bank + 1] = tmpr;
+  
+  /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
+  if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
+  {
+    tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20)); 
+    tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);
+    Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
+  }  
+  
+  return HAL_OK;   
+}
+
+/**
+  * @brief  Initialize the FMC_NORSRAM Extended mode Timing according to the specified
+  *         parameters in the FMC_NORSRAM_TimingTypeDef
+  * @param  Device: Pointer to NORSRAM device instance
+  * @param  Timing: Pointer to NORSRAM Timing structure
+  * @param  Bank: NORSRAM bank number  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
+{  
+  /* Check the parameters */
+  assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
+  
+  /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+  if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
+  {
+    /* Check the parameters */  
+    assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));  
+    assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+    assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+    assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
+    assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+    assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
+    assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
+    assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
+    assert_param(IS_FMC_NORSRAM_BANK(Bank));  
+    
+    Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime                 |\
+                                   ((Timing->AddressHoldTime) << 4)          |\
+                                   ((Timing->DataSetupTime) << 8)            |\
+                                   ((Timing->BusTurnAroundDuration) << 16)   |\
+                                   (((Timing->CLKDivision)-1) << 20)         |\
+                                   (((Timing->DataLatency)-2) << 24)         |\
+                                   (Timing->AccessMode));
+  }
+  else                                        
+  {
+    Device->BWTR[Bank] = 0x0FFFFFFF;
+  }   
+  
+  return HAL_OK;  
+}
+
+
+/**
+  * @}
+  */
+  
+  
+/** @defgroup HAL_FMC_NORSRAM_Group3 Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### FMC_NORSRAM Control functions #####
+  ==============================================================================  
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the FMC NORSRAM interface.
+
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Enables dynamically FMC_NORSRAM write operation.
+  * @param  Device: Pointer to NORSRAM device instance
+  * @param  Bank: NORSRAM bank number   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_NORSRAM_BANK(Bank));
+  
+  /* Enable write operation */
+  Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; 
+
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Disables dynamically FMC_NORSRAM write operation.
+  * @param  Device: Pointer to NORSRAM device instance
+  * @param  Bank: NORSRAM bank number   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_NORSRAM_BANK(Bank));
+    
+  /* Disable write operation */
+  Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE; 
+
+  return HAL_OK;  
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/** @defgroup FMC_PCCARD Controller functions
+  * @brief    PCCARD Controller functions 
+  *
+  @verbatim 
+  ==============================================================================
+                    ##### How to use NAND device driver #####
+  ==============================================================================
+  [..]
+    This driver contains a set of APIs to interface with the FMC NAND banks in order
+    to run the NAND external devices.
+  
+    (+) FMC NAND bank reset using the function FMC_NAND_DeInit() 
+    (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
+    (+) FMC NAND bank common space timing configuration using the function 
+        FMC_NAND_CommonSpace_Timing_Init()
+    (+) FMC NAND bank attribute space timing configuration using the function 
+        FMC_NAND_AttributeSpace_Timing_Init()
+    (+) FMC NAND bank enable/disable ECC correction feature using the functions
+        FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
+    (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()    
+
+@endverbatim
+  * @{
+  */
+    
+/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to:
+    (+) Initialize and configure the FMC NAND interface
+    (+) De-initialize the FMC NAND interface 
+    (+) Configure the FMC clock and associated GPIOs
+        
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initializes the FMC_NAND device according to the specified
+  *         control parameters in the FMC_NAND_HandleTypeDef
+  * @param  Device: Pointer to NAND device instance
+  * @param  Init: Pointer to NAND Initialization structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
+{
+  uint32_t tmppcr  = 0; 
+    
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_NAND_BANK(Init->NandBank));
+  assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
+  assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
+  assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
+  assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
+  assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
+  assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));   
+
+  /* Set NAND device control parameters */
+  tmppcr = (uint32_t)(Init->Waitfeature                |\
+                      FMC_PCR_MEMORY_TYPE_NAND         |\
+                      Init->MemoryDataWidth            |\
+                      Init->EccComputation             |\
+                      Init->ECCPageSize                |\
+                      ((Init->TCLRSetupTime) << 9)     |\
+                      ((Init->TARSetupTime) << 13)
+                      );   
+  
+  if(Init->NandBank == FMC_NAND_BANK2)
+  {
+    /* NAND bank 2 registers configuration */
+    Device->PCR2  = tmppcr;
+  }
+  else
+  {
+    /* NAND bank 3 registers configuration */
+    Device->PCR3  = tmppcr;
+  }
+  
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Initializes the FMC_NAND Common space Timing according to the specified
+  *         parameters in the FMC_NAND_PCC_TimingTypeDef
+  * @param  Device: Pointer to NAND device instance
+  * @param  Timing: Pointer to NAND timing structure
+  * @param  Bank: NAND bank number   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+  uint32_t tmppmem = 0;  
+  
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+  
+  /* Set FMC_NAND device timing parameters */
+  tmppmem = (uint32_t)(Timing->SetupTime                  |\
+                       ((Timing->WaitSetupTime) << 8)     |\
+                       ((Timing->HoldSetupTime) << 16)    |\
+                       ((Timing->HiZSetupTime) << 24)
+                       );
+                            
+  if(Bank == FMC_NAND_BANK2)
+  {
+    /* NAND bank 2 registers configuration */
+    Device->PMEM2 = tmppmem;
+  }
+  else
+  {
+    /* NAND bank 3 registers configuration */
+    Device->PMEM3 = tmppmem;
+  }  
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Initializes the FMC_NAND Attribute space Timing according to the specified
+  *         parameters in the FMC_NAND_PCC_TimingTypeDef
+  * @param  Device: Pointer to NAND device instance
+  * @param  Timing: Pointer to NAND timing structure
+  * @param  Bank: NAND bank number 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+  uint32_t tmppatt = 0;  
+  
+  /* Check the parameters */ 
+  assert_param(IS_FMC_NAND_DEVICE(Device)); 
+  assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+  
+  /* Set FMC_NAND device timing parameters */
+  tmppatt = (uint32_t)(Timing->SetupTime                  |\
+                       ((Timing->WaitSetupTime) << 8)     |\
+                       ((Timing->HoldSetupTime) << 16)    |\
+                       ((Timing->HiZSetupTime) << 24)
+                       );
+                       
+  if(Bank == FMC_NAND_BANK2)
+  {
+    /* NAND bank 2 registers configuration */
+    Device->PATT2 = tmppatt;
+  }
+  else
+  {
+    /* NAND bank 3 registers configuration */
+    Device->PATT3 = tmppatt;
+  }   
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DeInitializes the FMC_NAND device 
+  * @param  Device: Pointer to NAND device instance
+  * @param  Bank: NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */ 
+  assert_param(IS_FMC_NAND_DEVICE(Device)); 
+  assert_param(IS_FMC_NAND_BANK(Bank));
+      
+  /* Disable the NAND Bank */
+  __FMC_NAND_DISABLE(Device, Bank);
+ 
+  /* De-initialize the NAND Bank */
+  if(Bank == FMC_NAND_BANK2)
+  {
+    /* Set the FMC_NAND_BANK2 registers to their reset values */
+    Device->PCR2  = 0x00000018;
+    Device->SR2   = 0x00000040;
+    Device->PMEM2 = 0xFCFCFCFC;
+    Device->PATT2 = 0xFCFCFCFC;  
+  }
+  /* FMC_Bank3_NAND */  
+  else
+  {
+    /* Set the FMC_NAND_BANK3 registers to their reset values */
+    Device->PCR3  = 0x00000018;
+    Device->SR3   = 0x00000040;
+    Device->PMEM3 = 0xFCFCFCFC;
+    Device->PATT3 = 0xFCFCFCFC; 
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+  
+  
+/** @defgroup HAL_FMC_NAND_Group3 Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+  ==============================================================================
+                       ##### FMC_NAND Control functions #####
+  ==============================================================================  
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the FMC NAND interface.
+
+@endverbatim
+  * @{
+  */ 
+
+    
+/**
+  * @brief  Enables dynamically FMC_NAND ECC feature.
+  * @param  Device: Pointer to NAND device instance
+  * @param  Bank: NAND bank number
+  * @retval HAL status
+  */    
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */ 
+  assert_param(IS_FMC_NAND_DEVICE(Device)); 
+  assert_param(IS_FMC_NAND_BANK(Bank));
+    
+  /* Enable ECC feature */
+  if(Bank == FMC_NAND_BANK2)
+  {
+    Device->PCR2 |= FMC_PCR2_ECCEN;
+  }
+  else
+  {
+    Device->PCR3 |= FMC_PCR3_ECCEN;
+  } 
+  
+  return HAL_OK;  
+}
+
+
+/**
+  * @brief  Disables dynamically FMC_NAND ECC feature.
+  * @param  Device: Pointer to NAND device instance
+  * @param  Bank: NAND bank number
+  * @retval HAL status
+  */  
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)  
+{  
+  /* Check the parameters */ 
+  assert_param(IS_FMC_NAND_DEVICE(Device)); 
+  assert_param(IS_FMC_NAND_BANK(Bank));
+    
+  /* Disable ECC feature */
+  if(Bank == FMC_NAND_BANK2)
+  {
+    Device->PCR2 &= ~FMC_PCR2_ECCEN;
+  }
+  else
+  {
+    Device->PCR3 &= ~FMC_PCR3_ECCEN;
+  } 
+
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Disables dynamically FMC_NAND ECC feature.
+  * @param  Device: Pointer to NAND device instance
+  * @param  ECCval: Pointer to ECC value
+  * @param  Bank: NAND bank number
+  * @param  Timeout: Timeout wait value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
+{
+  uint32_t timeout = 0;
+
+  /* Check the parameters */ 
+  assert_param(IS_FMC_NAND_DEVICE(Device)); 
+  assert_param(IS_FMC_NAND_BANK(Bank));
+      
+  timeout = HAL_GetTick() + Timeout;
+  
+  /* Wait untill FIFO is empty */
+  while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        return HAL_TIMEOUT;
+      }
+    }  
+  }
+     
+  if(Bank == FMC_NAND_BANK2)
+  {    
+    /* Get the ECCR2 register value */
+    *ECCval = (uint32_t)Device->ECCR2;
+  }
+  else
+  {    
+    /* Get the ECCR3 register value */
+    *ECCval = (uint32_t)Device->ECCR3;
+  }
+
+  return HAL_OK;  
+}
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+    
+/** @defgroup FMC_PCCARD Controller functions
+  * @brief    PCCARD Controller functions 
+  *
+  @verbatim 
+  ==============================================================================  
+                    ##### How to use PCCARD device driver #####
+  ==============================================================================
+  [..]
+    This driver contains a set of APIs to interface with the FMC PCCARD bank in order
+    to run the PCCARD/compact flash external devices.
+  
+    (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit() 
+    (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
+    (+) FMC PCCARD bank common space timing configuration using the function 
+        FMC_PCCARD_CommonSpace_Timing_Init()
+    (+) FMC PCCARD bank attribute space timing configuration using the function 
+        FMC_PCCARD_AttributeSpace_Timing_Init()
+    (+) FMC PCCARD bank IO space timing configuration using the function 
+        FMC_PCCARD_IOSpace_Timing_Init()
+
+       
+@endverbatim
+  * @{
+  */
+  
+/** @defgroup HAL_FMC_PCCARD_Group1 Initialization/de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to:
+    (+) Initialize and configure the FMC PCCARD interface
+    (+) De-initialize the FMC PCCARD interface 
+    (+) Configure the FMC clock and associated GPIOs
+        
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initializes the FMC_PCCARD device according to the specified
+  *         control parameters in the FMC_PCCARD_HandleTypeDef
+  * @param  Device: Pointer to PCCARD device instance
+  * @param  Init: Pointer to PCCARD Initialization structure   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
+{
+  /* Check the parameters */ 
+  assert_param(IS_FMC_PCCARD_DEVICE(Device));
+  assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
+  assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
+  assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));     
+  
+  /* Set FMC_PCCARD device control parameters */
+  Device->PCR4 = (uint32_t)(Init->Waitfeature               |\
+                            FMC_NAND_PCC_MEM_BUS_WIDTH_16   |\
+                            (Init->TCLRSetupTime << 9)      |\
+                            (Init->TARSetupTime << 13));
+  
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Initializes the FMC_PCCARD Common space Timing according to the specified
+  *         parameters in the FMC_NAND_PCC_TimingTypeDef
+  * @param  Device: Pointer to PCCARD device instance
+  * @param  Timing: Pointer to PCCARD timing structure 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_PCCARD_DEVICE(Device));
+  assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+
+  /* Set PCCARD timing parameters */
+  Device->PMEM4 = (uint32_t)((Timing->SetupTime                 |\
+                             ((Timing->WaitSetupTime) << 8)     |\
+                              (Timing->HoldSetupTime) << 16)    |\
+                              ((Timing->HiZSetupTime) << 24)
+                             ); 
+
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Initializes the FMC_PCCARD Attribute space Timing according to the specified
+  *         parameters in the FMC_NAND_PCC_TimingTypeDef
+  * @param  Device: Pointer to PCCARD device instance
+  * @param  Timing: Pointer to PCCARD timing structure  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
+{
+  /* Check the parameters */ 
+  assert_param(IS_FMC_PCCARD_DEVICE(Device)); 
+  assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+
+  /* Set PCCARD timing parameters */
+  Device->PATT4 = (uint32_t)((Timing->SetupTime                 |\
+                             ((Timing->WaitSetupTime) << 8)     |\
+                              (Timing->HoldSetupTime) << 16)    |\
+                              ((Timing->HiZSetupTime) << 24)
+                             );  
+                                        
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FMC_PCCARD IO space Timing according to the specified
+  *         parameters in the FMC_NAND_PCC_TimingTypeDef
+  * @param  Device: Pointer to PCCARD device instance
+  * @param  Timing: Pointer to PCCARD timing structure  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
+{
+  /* Check the parameters */  
+  assert_param(IS_FMC_PCCARD_DEVICE(Device));
+  assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+
+  /* Set FMC_PCCARD device timing parameters */
+  Device->PIO4 = (uint32_t)((Timing->SetupTime                  |\
+                             ((Timing->WaitSetupTime) << 8)     |\
+                              (Timing->HoldSetupTime) << 16)    |\
+                              ((Timing->HiZSetupTime) << 24)
+                             );   
+  
+  return HAL_OK;
+}
+                                           
+/**
+  * @brief  DeInitializes the FMC_PCCARD device 
+  * @param  Device: Pointer to PCCARD device instance
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
+{
+  /* Check the parameters */  
+  assert_param(IS_FMC_PCCARD_DEVICE(Device));
+    
+  /* Disable the FMC_PCCARD device */
+  __FMC_PCCARD_DISABLE(Device);
+  
+  /* De-initialize the FMC_PCCARD device */
+  Device->PCR4    = 0x00000018; 
+  Device->SR4     = 0x00000000;	
+  Device->PMEM4   = 0xFCFCFCFC;
+  Device->PATT4   = 0xFCFCFCFC;
+  Device->PIO4    = 0xFCFCFCFC;
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup FMC_SDRAM Controller functions
+  * @brief    SDRAM Controller functions 
+  *
+  @verbatim 
+  ==============================================================================
+                     ##### How to use SDRAM device driver #####
+  ==============================================================================
+  [..] 
+    This driver contains a set of APIs to interface with the FMC SDRAM banks in order
+    to run the SDRAM external devices.
+    
+    (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() 
+    (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
+    (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
+    (+) FMC SDRAM bank enable/disable write operation using the functions
+        FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()   
+    (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()      
+       
+@endverbatim
+  * @{
+  */
+         
+/** @defgroup HAL_FMC_SDRAM_Group1 Initialization/de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to:
+    (+) Initialize and configure the FMC SDRAM interface
+    (+) De-initialize the FMC SDRAM interface 
+    (+) Configure the FMC clock and associated GPIOs
+        
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the FMC_SDRAM device according to the specified
+  *         control parameters in the FMC_SDRAM_InitTypeDef
+  * @param  Device: Pointer to SDRAM device instance
+  * @param  Init: Pointer to SDRAM Initialization structure   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
+{
+  uint32_t tmpr1 = 0;
+  uint32_t tmpr2 = 0;
+    
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
+  assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
+  assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
+  assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
+  assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
+  assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
+  assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
+  assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
+  assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
+  assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));   
+
+  /* Set SDRAM bank configuration parameters */
+  if (Init->SDBank != FMC_SDRAM_BANK2) 
+  {                                      
+    Device->SDCR[FMC_SDRAM_BANK1] = (uint32_t)(Init->ColumnBitsNumber   |\
+                                               Init->RowBitsNumber      |\
+                                               Init->MemoryDataWidth    |\
+                                               Init->InternalBankNumber |\
+                                               Init->CASLatency         |\
+                                               Init->WriteProtection    |\
+                                               Init->SDClockPeriod      |\
+                                               Init->ReadBurst          |\
+                                               Init->ReadPipeDelay
+                                               );                                      
+  }
+  else /* FMC_Bank2_SDRAM */                      
+  {
+    tmpr1 = (uint32_t)(Init->SDClockPeriod      |\
+                       Init->ReadBurst          |\
+                       Init->ReadPipeDelay
+                       );  
+
+    tmpr2 = (uint32_t)(Init->ColumnBitsNumber   |\
+                       Init->RowBitsNumber      |\
+                       Init->MemoryDataWidth    |\
+                       Init->InternalBankNumber |\
+                       Init->CASLatency         |\
+                       Init->WriteProtection
+                       ); 
+  
+    Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
+    Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
+  }  
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FMC_SDRAM device timing according to the specified
+  *         parameters in the FMC_SDRAM_TimingTypeDef
+  * @param  Device: Pointer to SDRAM device instance
+  * @param  Timing: Pointer to SDRAM Timing structure
+  * @param  Bank: SDRAM bank number   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
+{
+  uint32_t tmpr1 = 0;
+  uint32_t tmpr2 = 0;
+    
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
+  assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
+  assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
+  assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
+  assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
+  assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
+  assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
+  assert_param(IS_FMC_SDRAM_BANK(Bank));
+  
+  /* Set SDRAM device timing parameters */ 
+  if (Bank != FMC_SDRAM_BANK2) 
+  {                                         
+    Device->SDTR[FMC_SDRAM_BANK1] = (uint32_t)(((Timing->LoadToActiveDelay)-1)           |\
+                                               (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
+                                               (((Timing->SelfRefreshTime)-1) << 8)      |\
+                                               (((Timing->RowCycleDelay)-1) << 12)       |\
+                                               (((Timing->WriteRecoveryTime)-1) <<16)    |\
+                                               (((Timing->RPDelay)-1) << 20)             |\
+                                               (((Timing->RCDDelay)-1) << 24)
+                                               );
+  }
+  else /* FMC_Bank2_SDRAM */
+  {  
+
+    tmpr1 = (uint32_t)(((Timing->LoadToActiveDelay)-1)           |\
+                       (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
+                       (((Timing->SelfRefreshTime)-1) << 8)      |\
+                       (((Timing->WriteRecoveryTime)-1) <<16)    |\
+                       (((Timing->RCDDelay)-1) << 24)
+                       );   
+                                                         
+    tmpr2  = (uint32_t)((((Timing->RowCycleDelay)-1) << 12)       |\
+                        (((Timing->RPDelay)-1) << 20)
+                        ); 
+
+    Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
+    Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;
+  }   
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the FMC_SDRAM peripheral 
+  * @param  Device: Pointer to SDRAM device instance
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_SDRAM_BANK(Bank));
+  
+  /* De-initialize the SDRAM device */
+  Device->SDCR[Bank] = 0x000002D0;
+  Device->SDTR[Bank] = 0x0FFFFFFF;    
+  Device->SDCMR      = 0x00000000;
+  Device->SDRTR      = 0x00000000;
+  Device->SDSR       = 0x00000000;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+  
+/** @defgroup HAL_FMC_SDRAM_Group3 Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### FMC_SDRAM Control functions #####
+  ==============================================================================  
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the FMC SDRAM interface.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables dynamically FMC_SDRAM write protection.
+  * @param  Device: Pointer to SDRAM device instance
+  * @param  Bank: SDRAM bank number 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_SDRAM_BANK(Bank));
+  
+  /* Enable write protection */
+  Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Disables dynamically FMC_SDRAM write protection.
+  * @param  hsdram: FMC_SDRAM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_SDRAM_BANK(Bank));
+  
+  /* Disable write protection */
+  Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
+  
+  return HAL_OK;
+}
+  
+/**
+  * @brief  Send Command to the FMC SDRAM bank
+  * @param  Device: Pointer to SDRAM device instance
+  * @param  Command: Pointer to SDRAM command structure   
+  * @param  Timing: Pointer to SDRAM Timing structure
+  * @param  Timeout: Timeout wait value
+  * @retval HAL state
+  */  
+HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
+{
+  __IO uint32_t tmpr = 0;
+  uint32_t timeout = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
+  assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
+  assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
+  assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));  
+
+  /* Set command register */
+  tmpr = (uint32_t)((Command->CommandMode)                  |\
+                    (Command->CommandTarget)                |\
+                    (((Command->AutoRefreshNumber)-1) << 5) |\
+                    ((Command->ModeRegisterDefinition) << 9)     
+                    );
+    
+  Device->SDCMR = tmpr;
+   
+  timeout = HAL_GetTick() + Timeout;
+
+  /* wait until command is send */
+  while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        return HAL_TIMEOUT;
+      }
+    }     
+    
+    return HAL_ERROR;
+  }
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Program the SDRAM Memory Refresh rate.
+  * @param  Device: Pointer to SDRAM device instance  
+  * @param  RefreshRate: The SDRAM refresh rate value.       
+  * @retval HAL state
+  */
+HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
+  
+  /* Set the refresh rate in command register */
+  Device->SDRTR |= (RefreshRate<<1);
+  
+  return HAL_OK;   
+}
+
+/**
+  * @brief  Set the Number of consecutive SDRAM Memory auto Refresh commands.
+  * @param  Device: Pointer to SDRAM device instance  
+  * @param  AutoRefreshNumber: Specifies the auto Refresh number.       
+  * @retval None
+  */
+HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
+  
+  /* Set the Auto-refresh number in command register */
+  Device->SDCMR |= (AutoRefreshNumber << 5); 
+
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Returns the indicated FMC SDRAM bank mode status.
+  * @param  Device: Pointer to SDRAM device instance  
+  * @param  Bank: Defines the FMC SDRAM bank. This parameter can be 
+  *                     FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. 
+  * @retval The FMC SDRAM bank mode status, could be on of the following values:
+  *         FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or 
+  *         FMC_SDRAM_POWER_DOWN_MODE.           
+  */
+uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_SDRAM_BANK(Bank));
+
+  /* Get the corresponding bank mode */
+  if(Bank == FMC_SDRAM_BANK1)
+  {
+    tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); 
+  }
+  else
+  {
+    tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);
+  }
+  
+  /* Return the mode status */
+  return tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#endif /* HAL_FMC_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_fmc.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1380 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_fmc.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of FMC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_FMC_H
+#define __STM32F4xx_LL_FMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FMC
+  * @{
+  */ 
+
+/* Exported typedef ----------------------------------------------------------*/ 
+#define FMC_NORSRAM_TypeDef            FMC_Bank1_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef   FMC_Bank1E_TypeDef
+#define FMC_NAND_TypeDef               FMC_Bank2_3_TypeDef
+#define FMC_PCCARD_TypeDef             FMC_Bank4_TypeDef
+#define FMC_SDRAM_TypeDef              FMC_Bank5_6_TypeDef
+
+#define FMC_NORSRAM_DEVICE             FMC_Bank1
+#define FMC_NORSRAM_EXTENDED_DEVICE    FMC_Bank1E
+#define FMC_NAND_DEVICE                FMC_Bank2_3
+#define FMC_PCCARD_DEVICE              FMC_Bank4
+#define FMC_SDRAM_DEVICE               FMC_Bank5_6
+
+/** 
+  * @brief  FMC_NORSRAM Configuration Structure definition
+  */ 
+typedef struct
+{
+  uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
+                                              This parameter can be a value of @ref FMC_NORSRAM_Bank                     */
+
+  uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
+                                              multiplexed on the data bus or not. 
+                                              This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing    */
+
+  uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
+                                              the corresponding memory device.
+                                              This parameter can be a value of @ref FMC_Memory_Type                      */
+
+  uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
+                                              This parameter can be a value of @ref FMC_NORSRAM_Data_Width               */
+
+  uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
+                                              valid only with synchronous burst Flash memories.
+                                              This parameter can be a value of @ref FMC_Burst_Access_Mode                */
+
+  uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
+                                              the Flash memory in burst mode.
+                                              This parameter can be a value of @ref FMC_Wait_Signal_Polarity             */
+
+  uint32_t WrapMode;                     /*!< Enables or disables the Wrapped burst access mode for Flash
+                                              memory, valid only when accessing Flash memories in burst mode.
+                                              This parameter can be a value of @ref FMC_Wrap_Mode                        */
+
+  uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
+                                              clock cycle before the wait state or during the wait state,
+                                              valid only when accessing memories in burst mode. 
+                                              This parameter can be a value of @ref FMC_Wait_Timing                      */
+
+  uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FMC. 
+                                              This parameter can be a value of @ref FMC_Write_Operation                  */
+
+  uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
+                                              signal, valid for Flash memory access in burst mode. 
+                                              This parameter can be a value of @ref FMC_Wait_Signal                      */
+
+  uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
+                                              This parameter can be a value of @ref FMC_Extended_Mode                    */
+
+  uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
+                                              valid only with asynchronous Flash memories.
+                                              This parameter can be a value of @ref FMC_AsynchronousWait                 */
+
+  uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
+                                              This parameter can be a value of @ref FMC_Write_Burst                      */
+
+  uint32_t ContinuousClock;              /*!< Enables or disables the FMC clock output to external memory devices.
+                                              This parameter is only enabled through the FMC_BCR1 register, and don't care 
+                                              through FMC_BCR2..4 registers.
+                                              This parameter can be a value of @ref FMC_Continous_Clock                  */
+
+}FMC_NORSRAM_InitTypeDef;
+
+/** 
+  * @brief  FMC_NORSRAM Timing parameters structure definition  
+  */
+typedef struct
+{
+  uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the address setup time. 
+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+                                              @note This parameter is not used with synchronous NOR Flash memories.      */
+
+  uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the address hold time.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15. 
+                                              @note This parameter is not used with synchronous NOR Flash memories.      */
+
+  uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the data setup time.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 255.
+                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 
+                                              NOR Flash memories.                                                        */
+
+  uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the bus turnaround.
+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+                                              @note This parameter is only used for multiplexed NOR Flash memories.      */
+
+  uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of 
+                                              HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
+                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 
+                                              accesses.                                                                  */
+
+  uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
+                                              to the memory before getting the first data.
+                                              The parameter value depends on the memory type as shown below:
+                                              - It must be set to 0 in case of a CRAM
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
+                                              - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
+                                                with synchronous burst mode enable                                       */
+
+  uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode. 
+                                              This parameter can be a value of @ref FMC_Access_Mode                      */
+}FMC_NORSRAM_TimingTypeDef;
+
+/** 
+  * @brief  FMC_NAND Configuration Structure definition  
+  */ 
+typedef struct
+{
+  uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.
+                                        This parameter can be a value of @ref FMC_NAND_Bank                    */
+
+  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.
+                                        This parameter can be any value of @ref FMC_Wait_feature               */
+
+  uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.
+                                        This parameter can be any value of @ref FMC_NAND_Data_Width            */
+
+  uint32_t EccComputation;         /*!< Enables or disables the ECC computation.
+                                        This parameter can be any value of @ref FMC_ECC                        */
+
+  uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.
+                                        This parameter can be any value of @ref FMC_ECC_Page_Size              */
+
+  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
+                                        delay between CLE low and RE low.
+                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
+
+  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
+                                        delay between ALE low and RE low.
+                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+}FMC_NAND_InitTypeDef;
+
+/** 
+  * @brief  FMC_NAND_PCCARD Timing parameters structure definition
+  */
+typedef struct
+{
+  uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before
+                                      the command assertion for NAND-Flash read or write access
+                                      to common/Attribute or I/O memory space (depending on
+                                      the memory space timing to be configured).
+                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255    */
+
+  uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the
+                                      command for NAND-Flash read or write access to
+                                      common/Attribute or I/O memory space (depending on the
+                                      memory space timing to be configured). 
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
+
+  uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address
+                                      (and data for write access) after the command de-assertion
+                                      for NAND-Flash read or write access to common/Attribute
+                                      or I/O memory space (depending on the memory space timing
+                                      to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
+
+  uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the
+                                      data bus is kept in HiZ after the start of a NAND-Flash
+                                      write access to common/Attribute or I/O memory space (depending
+                                      on the memory space timing to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
+}FMC_NAND_PCC_TimingTypeDef;
+
+/** 
+  * @brief  FMC_NAND Configuration Structure definition
+  */ 
+typedef struct
+{
+  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the PCCARD Memory device.
+                                        This parameter can be any value of @ref FMC_Wait_feature               */
+
+  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
+                                        delay between CLE low and RE low.
+                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
+
+  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
+                                        delay between ALE low and RE low.
+                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+}FMC_PCCARD_InitTypeDef;
+
+/** 
+  * @brief  FMC_SDRAM Configuration Structure definition  
+  */  
+typedef struct
+{
+  uint32_t SDBank;                      /*!< Specifies the SDRAM memory device that will be used.
+                                             This parameter can be a value of @ref FMC_SDRAM_Bank                */
+
+  uint32_t ColumnBitsNumber;            /*!< Defines the number of bits of column address.
+                                             This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
+
+  uint32_t RowBitsNumber;               /*!< Defines the number of bits of column address.
+                                             This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number.    */
+
+  uint32_t MemoryDataWidth;             /*!< Defines the memory device width.
+                                             This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width.   */
+
+  uint32_t InternalBankNumber;          /*!< Defines the number of the device's internal banks.
+                                             This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number.      */
+
+  uint32_t CASLatency;                  /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
+                                             This parameter can be a value of @ref FMC_SDRAM_CAS_Latency.        */
+
+  uint32_t WriteProtection;             /*!< Enables the SDRAM device to be accessed in write mode.
+                                             This parameter can be a value of @ref FMC_SDRAM_Write_Protection.   */
+
+  uint32_t SDClockPeriod;               /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow 
+                                             to disable the clock before changing frequency.
+                                             This parameter can be a value of @ref FMC_SDRAM_Clock_Period.       */
+
+  uint32_t ReadBurst;                   /*!< This bit enable the SDRAM controller to anticipate the next read 
+                                             commands during the CAS latency and stores data in the Read FIFO.
+                                             This parameter can be a value of @ref FMC_SDRAM_Read_Burst.         */
+
+  uint32_t ReadPipeDelay;               /*!< Define the delay in system clock cycles on read data path.
+                                             This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay.    */
+}FMC_SDRAM_InitTypeDef;
+
+/** 
+  * @brief  FMC_SDRAM Timing parameters structure definition
+  */
+typedef struct
+{
+  uint32_t LoadToActiveDelay;            /*!< Defines the delay between a Load Mode Register command and 
+                                              an active or Refresh command in number of memory clock cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+
+  uint32_t ExitSelfRefreshDelay;         /*!< Defines the delay from releasing the self refresh command to 
+                                              issuing the Activate command in number of memory clock cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+
+  uint32_t SelfRefreshTime;              /*!< Defines the minimum Self Refresh period in number of memory clock 
+                                              cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+
+  uint32_t RowCycleDelay;                /*!< Defines the delay between the Refresh command and the Activate command
+                                              and the delay between two consecutive Refresh commands in number of 
+                                              memory clock cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+
+  uint32_t WriteRecoveryTime;            /*!< Defines the Write recovery Time in number of memory clock cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+
+  uint32_t RPDelay;                      /*!< Defines the delay between a Precharge Command and an other command 
+                                              in number of memory clock cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+
+  uint32_t RCDDelay;                     /*!< Defines the delay between the Activate Command and a Read/Write 
+                                              command in number of memory clock cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */ 
+}FMC_SDRAM_TimingTypeDef;
+
+/** 
+  * @brief  SDRAM command parameters structure definition
+  */
+typedef struct
+{
+  uint32_t CommandMode;                  /*!< Defines the command issued to the SDRAM device.
+                                              This parameter can be a value of @ref FMC_SDRAM_Command_Mode.          */
+
+  uint32_t CommandTarget;                /*!< Defines which device (1 or 2) the command will be issued to.
+                                              This parameter can be a value of @ref FMC_SDRAM_Command_Target.        */
+
+  uint32_t AutoRefreshNumber;            /*!< Defines the number of consecutive auto refresh command issued
+                                              in auto refresh mode.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16   */
+  uint32_t ModeRegisterDefinition;       /*!< Defines the SDRAM Mode register content                                */
+}FMC_SDRAM_CommandTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FMC_NOR_SRAM_Controller 
+  * @{
+  */
+
+/** @defgroup FMC_NORSRAM_Bank 
+  * @{
+  */
+#define FMC_NORSRAM_BANK1                       ((uint32_t)0x00000000)
+#define FMC_NORSRAM_BANK2                       ((uint32_t)0x00000002)
+#define FMC_NORSRAM_BANK3                       ((uint32_t)0x00000004)
+#define FMC_NORSRAM_BANK4                       ((uint32_t)0x00000006)
+
+#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
+                                   ((BANK) == FMC_NORSRAM_BANK2) || \
+                                   ((BANK) == FMC_NORSRAM_BANK3) || \
+                                   ((BANK) == FMC_NORSRAM_BANK4))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Data_Address_Bus_Multiplexing 
+  * @{
+  */
+#define FMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000)
+#define FMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)0x00000002)
+
+#define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
+                         ((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Memory_Type 
+  * @{
+  */
+#define FMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000)
+#define FMC_MEMORY_TYPE_PSRAM                   ((uint32_t)0x00000004)
+#define FMC_MEMORY_TYPE_NOR                     ((uint32_t)0x00000008)
+
+#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) || \
+                               ((MEMORY) == FMC_MEMORY_TYPE_PSRAM)|| \
+                               ((MEMORY) == FMC_MEMORY_TYPE_NOR))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NORSRAM_Data_Width 
+  * @{
+  */
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)0x00000010)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)0x00000020)
+
+#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
+                                            ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+                                            ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NORSRAM_Flash_Access 
+  * @{
+  */
+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)0x00000040)
+#define FMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Burst_Access_Mode 
+  * @{
+  */
+#define FMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000) 
+#define FMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)0x00000100)
+
+#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) || \
+                                 ((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
+/**
+  * @}
+  */
+    
+
+/** @defgroup FMC_Wait_Signal_Polarity 
+  * @{
+  */
+#define FMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000)
+#define FMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)0x00000200)
+
+#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
+                                        ((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wrap_Mode 
+  * @{
+  */
+#define FMC_WRAP_MODE_DISABLE                   ((uint32_t)0x00000000)
+#define FMC_WRAP_MODE_ENABLE                    ((uint32_t)0x00000400)
+
+#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) || \
+                                ((MODE) == FMC_WRAP_MODE_ENABLE)) 
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_Timing 
+  * @{
+  */
+#define FMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000)
+#define FMC_WAIT_TIMING_DURING_WS               ((uint32_t)0x00000800)
+
+#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) || \
+                                           ((ACTIVE) == FMC_WAIT_TIMING_DURING_WS)) 
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Write_Operation 
+  * @{
+  */
+#define FMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000)
+#define FMC_WRITE_OPERATION_ENABLE              ((uint32_t)0x00001000)
+
+#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) || \
+                                           ((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_Signal 
+  * @{
+  */
+#define FMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000)
+#define FMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)0x00002000)
+
+#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) || \
+                                     ((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE)) 
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Extended_Mode 
+  * @{
+  */
+#define FMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000)
+#define FMC_EXTENDED_MODE_ENABLE                ((uint32_t)0x00004000)
+
+#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) || \
+                                    ((MODE) == FMC_EXTENDED_MODE_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_AsynchronousWait 
+  * @{
+  */
+#define FMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000)
+#define FMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)0x00008000)
+
+#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+                                ((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
+/**
+  * @}
+  */  
+
+/** @defgroup FMC_Write_Burst 
+  * @{
+  */
+#define FMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000)
+#define FMC_WRITE_BURST_ENABLE                  ((uint32_t)0x00080000)
+
+#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) || \
+                                   ((BURST) == FMC_WRITE_BURST_ENABLE)) 
+/**
+  * @}
+  */
+  
+/** @defgroup FMC_Continous_Clock 
+  * @{
+  */
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY          ((uint32_t)0x00000000)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC         ((uint32_t)0x00100000)
+
+#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+                                        ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 
+/**
+  * @}
+  */
+  
+/** @defgroup FMC_Address_Setup_Time 
+  * @{
+  */
+#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Address_Hold_Time 
+  * @{
+  */
+#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Data_Setup_Time 
+  * @{
+  */
+#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Bus_Turn_around_Duration 
+  * @{
+  */
+#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_CLK_Division 
+  * @{
+  */
+#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Data_Latency 
+  * @{
+  */
+#define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
+/**
+  * @}
+  */  
+
+/** @defgroup FMC_Access_Mode 
+  * @{
+  */
+#define FMC_ACCESS_MODE_A                        ((uint32_t)0x00000000)
+#define FMC_ACCESS_MODE_B                        ((uint32_t)0x10000000) 
+#define FMC_ACCESS_MODE_C                        ((uint32_t)0x20000000)
+#define FMC_ACCESS_MODE_D                        ((uint32_t)0x30000000)
+
+#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) || \
+                                  ((MODE) == FMC_ACCESS_MODE_B) || \
+                                  ((MODE) == FMC_ACCESS_MODE_C) || \
+                                  ((MODE) == FMC_ACCESS_MODE_D))
+/**
+  * @}
+  */
+    
+/**
+  * @}
+  */  
+
+/** @defgroup FMC_NAND_Controller 
+  * @{
+  */
+
+/** @defgroup FMC_NAND_Bank 
+  * @{
+  */  
+#define FMC_NAND_BANK2                          ((uint32_t)0x00000010)
+#define FMC_NAND_BANK3                          ((uint32_t)0x00000100)
+
+#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
+                                ((BANK) == FMC_NAND_BANK3))  
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_feature 
+  * @{
+  */
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE           ((uint32_t)0x00000000)
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE            ((uint32_t)0x00000002)
+
+#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+                                      ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_PCR_Memory_Type 
+  * @{
+  */
+#define FMC_PCR_MEMORY_TYPE_PCCARD        ((uint32_t)0x00000000)
+#define FMC_PCR_MEMORY_TYPE_NAND          ((uint32_t)0x00000008)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NAND_Data_Width 
+  * @{
+  */
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8                ((uint32_t)0x00000000)
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16               ((uint32_t)0x00000010)
+
+#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+                                         ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_ECC 
+  * @{
+  */
+#define FMC_NAND_ECC_DISABLE                    ((uint32_t)0x00000000)
+#define FMC_NAND_ECC_ENABLE                     ((uint32_t)0x00000040)
+
+#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
+                                 ((STATE) == FMC_NAND_ECC_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_ECC_Page_Size 
+  * @{
+  */
+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE          ((uint32_t)0x00000000)
+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE          ((uint32_t)0x00020000)
+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE         ((uint32_t)0x00040000)
+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE         ((uint32_t)0x00060000)
+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE         ((uint32_t)0x00080000)
+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE         ((uint32_t)0x000A0000)
+
+#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \
+                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \
+                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_TCLR_Setup_Time 
+  * @{
+  */
+#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_TAR_Setup_Time 
+  * @{
+  */
+#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Setup_Time 
+  * @{
+  */
+#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_Setup_Time 
+  * @{
+  */
+#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Hold_Setup_Time 
+  * @{
+  */
+#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_HiZ_Setup_Time 
+  * @{
+  */
+#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
+/**
+  * @}
+  */  
+    
+/**
+  * @}
+  */  
+
+/** @defgroup FMC_SDRAM_Controller 
+  * @{
+  */
+
+/** @defgroup FMC_SDRAM_Bank 
+  * @{
+  */
+#define FMC_SDRAM_BANK1                       ((uint32_t)0x00000000)
+#define FMC_SDRAM_BANK2                       ((uint32_t)0x00000001)
+
+#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
+                                 ((BANK) == FMC_SDRAM_BANK2))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Column_Bits_number 
+  * @{
+  */
+#define FMC_SDRAM_COLUMN_BITS_NUM_8           ((uint32_t)0x00000000)
+#define FMC_SDRAM_COLUMN_BITS_NUM_9           ((uint32_t)0x00000001)
+#define FMC_SDRAM_COLUMN_BITS_NUM_10          ((uint32_t)0x00000002)
+#define FMC_SDRAM_COLUMN_BITS_NUM_11          ((uint32_t)0x00000003)
+
+#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8)  || \
+                                          ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9)  || \
+                                          ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
+                                          ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Row_Bits_number 
+  * @{
+  */
+#define FMC_SDRAM_ROW_BITS_NUM_11             ((uint32_t)0x00000000)
+#define FMC_SDRAM_ROW_BITS_NUM_12             ((uint32_t)0x00000004)
+#define FMC_SDRAM_ROW_BITS_NUM_13             ((uint32_t)0x00000008)
+
+#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
+                                    ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
+                                    ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Memory_Bus_Width
+  * @{
+  */
+#define FMC_SDRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000)
+#define FMC_SDRAM_MEM_BUS_WIDTH_16            ((uint32_t)0x00000010)
+#define FMC_SDRAM_MEM_BUS_WIDTH_32            ((uint32_t)0x00000020)
+
+#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8)  || \
+                                      ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
+                                      ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Internal_Banks_Number
+  * @{
+  */
+#define FMC_SDRAM_INTERN_BANKS_NUM_2          ((uint32_t)0x00000000)
+#define FMC_SDRAM_INTERN_BANKS_NUM_4          ((uint32_t)0x00000040)
+
+#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
+                                            ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_CAS_Latency
+  * @{
+  */
+#define FMC_SDRAM_CAS_LATENCY_1               ((uint32_t)0x00000080)
+#define FMC_SDRAM_CAS_LATENCY_2               ((uint32_t)0x00000100)
+#define FMC_SDRAM_CAS_LATENCY_3               ((uint32_t)0x00000180)
+
+#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
+                                     ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
+                                     ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Write_Protection
+  * @{
+  */
+#define FMC_SDRAM_WRITE_PROTECTION_DISABLE    ((uint32_t)0x00000000)
+#define FMC_SDRAM_WRITE_PROTECTION_ENABLE     ((uint32_t)0x00000200)
+
+#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
+                                        ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Clock_Period
+  * @{
+  */
+#define FMC_SDRAM_CLOCK_DISABLE               ((uint32_t)0x00000000)
+#define FMC_SDRAM_CLOCK_PERIOD_2              ((uint32_t)0x00000800)
+#define FMC_SDRAM_CLOCK_PERIOD_3              ((uint32_t)0x00000C00)
+
+#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE)  || \
+                                       ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \
+                                       ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Read_Burst
+  * @{
+  */
+#define FMC_SDRAM_RBURST_DISABLE              ((uint32_t)0x00000000)
+#define FMC_SDRAM_RBURST_ENABLE               ((uint32_t)0x00001000)
+
+#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \
+                                   ((RBURST) == FMC_SDRAM_RBURST_ENABLE))
+/**
+  * @}
+  */
+  
+/** @defgroup FMC_SDRAM_Read_Pipe_Delay
+  * @{
+  */
+#define FMC_SDRAM_RPIPE_DELAY_0               ((uint32_t)0x00000000)
+#define FMC_SDRAM_RPIPE_DELAY_1               ((uint32_t)0x00002000)
+#define FMC_SDRAM_RPIPE_DELAY_2               ((uint32_t)0x00004000)
+
+#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \
+                                      ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
+                                      ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
+/**
+  * @}
+  */
+  
+/** @defgroup FMC_SDRAM_LoadToActive_Delay
+  * @{
+  */
+#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+/**
+  * @}
+  */
+  
+/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay
+  * @{
+  */
+#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+/**
+  * @}
+  */ 
+     
+/** @defgroup FMC_SDRAM_SelfRefresh_Time
+  * @{
+  */  
+#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
+/**
+  * @}
+  */
+  
+/** @defgroup FMC_SDRAM_RowCycle_Delay
+  * @{
+  */  
+#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+/**
+  * @}
+  */  
+  
+/** @defgroup FMC_SDRAM_Write_Recovery_Time
+  * @{
+  */  
+#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
+/**
+  * @}
+  */         
+  
+/** @defgroup FMC_SDRAM_RP_Delay
+  * @{
+  */  
+#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+/**
+  * @}
+  */ 
+  
+/** @defgroup FMC_SDRAM_RCD_Delay 
+  * @{
+  */  
+#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+
+/**
+  * @}
+  */  
+
+/** @defgroup FMC_SDRAM_Command_Mode
+  * @{
+  */
+#define FMC_SDRAM_CMD_NORMAL_MODE             ((uint32_t)0x00000000)
+#define FMC_SDRAM_CMD_CLK_ENABLE              ((uint32_t)0x00000001)
+#define FMC_SDRAM_CMD_PALL                    ((uint32_t)0x00000002)
+#define FMC_SDRAM_CMD_AUTOREFRESH_MODE        ((uint32_t)0x00000003)
+#define FMC_SDRAM_CMD_LOAD_MODE               ((uint32_t)0x00000004)
+#define FMC_SDRAM_CMD_SELFREFRESH_MODE        ((uint32_t)0x00000005)
+#define FMC_SDRAM_CMD_POWERDOWN_MODE          ((uint32_t)0x00000006)
+
+#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE)      || \
+                                      ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE)       || \
+                                      ((COMMAND) == FMC_SDRAM_CMD_PALL)             || \
+                                      ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
+                                      ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE)        || \
+                                      ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
+                                      ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Command_Target
+  * @{
+  */
+#define FMC_SDRAM_CMD_TARGET_BANK2            FMC_SDCMR_CTB2
+#define FMC_SDRAM_CMD_TARGET_BANK1            FMC_SDCMR_CTB1
+#define FMC_SDRAM_CMD_TARGET_BANK1_2          ((uint32_t)0x00000018)
+
+#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \
+                                       ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
+                                       ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2)) 
+/**
+  * @}
+  */ 
+
+/** @defgroup FMC_SDRAM_AutoRefresh_Number
+  * @{
+  */  
+#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_ModeRegister_Definition
+  * @{
+  */
+#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Refresh_rate
+  * @{
+  */
+#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Mode_Status 
+  * @{
+  */
+#define FMC_SDRAM_NORMAL_MODE                     ((uint32_t)0x00000000)
+#define FMC_SDRAM_SELF_REFRESH_MODE               FMC_SDSR_MODES1_0
+#define FMC_SDRAM_POWER_DOWN_MODE                 FMC_SDSR_MODES1_1
+/**
+  * @}
+  */ 
+  
+/** @defgroup FMC_NORSRAM_Device_Instance
+  * @{
+  */
+#define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
+  * @{
+  */
+#define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
+/**
+  * @}
+  */
+  
+/** @defgroup FMC_NAND_Device_Instance
+  * @{
+  */
+#define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
+/**
+  * @}
+  */  
+
+/** @defgroup FMC_PCCARD_Device_Instance
+  * @{
+  */
+#define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
+/**
+  * @}
+  */ 
+
+/** @defgroup FMC_SDRAM_Device_Instance
+  * @{
+  */
+#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/** @defgroup FMC_Interrupt_definition 
+  * @brief FMC Interrupt definition
+  * @{
+  */  
+#define FMC_IT_RISING_EDGE                ((uint32_t)0x00000008)
+#define FMC_IT_LEVEL                      ((uint32_t)0x00000010)
+#define FMC_IT_FALLING_EDGE               ((uint32_t)0x00000020)
+#define FMC_IT_REFRESH_ERROR              ((uint32_t)0x00004000)
+
+#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
+
+#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE)   || \
+                           ((IT) == FMC_IT_LEVEL)         || \
+                           ((IT) == FMC_IT_FALLING_EDGE)  || \
+                           ((IT) == FMC_IT_REFRESH_ERROR)) 
+/**
+  * @}
+  */
+    
+/** @defgroup FMC_Flag_definition 
+  * @brief FMC Flag definition
+  * @{
+  */ 
+#define FMC_FLAG_RISING_EDGE                    ((uint32_t)0x00000001)
+#define FMC_FLAG_LEVEL                          ((uint32_t)0x00000002)
+#define FMC_FLAG_FALLING_EDGE                   ((uint32_t)0x00000004)
+#define FMC_FLAG_FEMPT                          ((uint32_t)0x00000040)
+#define FMC_SDRAM_FLAG_REFRESH_IT               FMC_SDSR_RE
+#define FMC_SDRAM_FLAG_BUSY                     FMC_SDSR_BUSY
+#define FMC_SDRAM_FLAG_REFRESH_ERROR            FMC_SDRTR_CRE
+
+#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE)      || \
+                               ((FLAG) == FMC_FLAG_LEVEL)            || \
+                               ((FLAG) == FMC_FLAG_FALLING_EDGE)     || \
+                               ((FLAG) == FMC_FLAG_FEMPT)            || \
+                               ((FLAG) == FMC_SDRAM_FLAG_REFRESH_IT) || \
+                               ((FLAG) == FMC_SDRAM_FLAG_BUSY))
+
+#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))                               
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup FMC_NOR_Macros
+ *  @brief macros to handle NOR device enable/disable and read/write operations
+ *  @{
+ */
+ 
+/**
+  * @brief  Enable the NORSRAM device access.
+  * @param  __INSTANCE__: FMC_NORSRAM Instance
+  * @param  __BANK__: FMC_NORSRAM Bank     
+  * @retval None
+  */ 
+#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
+
+/**
+  * @brief  Disable the NORSRAM device access.
+  * @param  __INSTANCE__: FMC_NORSRAM Instance
+  * @param  __BANK__: FMC_NORSRAM Bank   
+  * @retval None
+  */ 
+#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)  
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FMC_NAND_Macros
+ *  @brief macros to handle NAND device enable/disable
+ *  @{
+ */
+ 
+/**
+  * @brief  Enable the NAND device access.
+  * @param  __INSTANCE__: FMC_NAND Instance
+  * @param  __BANK__: FMC_NAND Bank    
+  * @retval None
+  */  
+#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__)  (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
+                                                    ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
+
+/**
+  * @brief  Disable the NAND device access.
+  * @param  __INSTANCE__: FMC_NAND Instance
+  * @param  __BANK__: FMC_NAND Bank  
+  * @retval None
+  */
+#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
+                                                   ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
+/**
+  * @}
+  */ 
+  
+/** @defgroup FMC_PCCARD_Macros
+ *  @brief macros to handle SRAM read/write operations 
+ *  @{
+ */
+
+/**
+  * @brief  Enable the PCCARD device access.
+  * @param  __INSTANCE__: FMC_PCCARD Instance  
+  * @retval None
+  */ 
+#define __FMC_PCCARD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
+
+/**
+  * @brief  Disable the PCCARD device access.
+  * @param  __INSTANCE__: FMC_PCCARD Instance     
+  * @retval None
+  */ 
+#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
+/**
+  * @}
+  */
+  
+/** @defgroup FMC_Interrupt
+ *  @brief macros to handle FMC interrupts
+ * @{
+ */ 
+
+/**
+  * @brief  Enable the NAND device interrupt.
+  * @param  __INSTANCE__:  FMC_NAND instance
+  * @param  __BANK__:      FMC_NAND Bank     
+  * @param  __INTERRUPT__: FMC_NAND interrupt 
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg FMC_IT_LEVEL: Interrupt level.
+  *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.       
+  * @retval None
+  */  
+#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
+                                                                                                      ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
+
+/**
+  * @brief  Disable the NAND device interrupt.
+  * @param  __INSTANCE__:  FMC_NAND handle
+  * @param  __BANK__:      FMC_NAND Bank    
+  * @param  __INTERRUPT__: FMC_NAND interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg FMC_IT_LEVEL: Interrupt level.
+  *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.   
+  * @retval None
+  */
+#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
+                                                                                                      ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) 
+                                                                                                                             
+/**
+  * @brief  Get flag status of the NAND device.
+  * @param  __INSTANCE__: FMC_NAND handle
+  * @param  __BANK__:     FMC_NAND Bank      
+  * @param  __FLAG__: FMC_NAND flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg FMC_FLAG_FEMPT: FIFO empty flag.   
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
+                                                                                                (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+/**
+  * @brief  Clear flag status of the NAND device.
+  * @param  __INSTANCE__: FMC_NAND handle  
+  * @param  __BANK__:     FMC_NAND Bank  
+  * @param  __FLAG__: FMC_NAND flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg FMC_FLAG_FEMPT: FIFO empty flag.   
+  * @retval None
+  */
+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
+                                                                                                  ((__INSTANCE__)->SR3 &= ~(__FLAG__))) 
+/**
+  * @brief  Enable the PCCARD device interrupt.
+  * @param  __INSTANCE__: FMC_PCCARD instance  
+  * @param  __INTERRUPT__: FMC_PCCARD interrupt 
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg FMC_IT_LEVEL: Interrupt level.
+  *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.       
+  * @retval None
+  */ 
+#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the PCCARD device interrupt.
+  * @param  __INSTANCE__: FMC_PCCARD instance  
+  * @param  __INTERRUPT__: FMC_PCCARD interrupt 
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg FMC_IT_LEVEL: Interrupt level.
+  *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.       
+  * @retval None
+  */ 
+#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) 
+
+/**
+  * @brief  Get flag status of the PCCARD device.
+  * @param  __INSTANCE__: FMC_PCCARD instance  
+  * @param  __FLAG__: FMC_PCCARD flag
+  *         This parameter can be any combination of the following values:
+  *            @arg  FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg  FMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg  FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg  FMC_FLAG_FEMPT: FIFO empty flag.   
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear flag status of the PCCARD device.
+  * @param  __INSTANCE__: FMC_PCCARD instance  
+  * @param  __FLAG__: FMC_PCCARD flag
+  *         This parameter can be any combination of the following values:
+  *            @arg  FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg  FMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg  FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg  FMC_FLAG_FEMPT: FIFO empty flag.   
+  * @retval None
+  */
+#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SR4 &= ~(__FLAG__))
+ 
+/**
+  * @brief  Enable the SDRAM device interrupt.
+  * @param  __INSTANCE__: FMC_SDRAM instance  
+  * @param  __INTERRUPT__: FMC_SDRAM interrupt 
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error      
+  * @retval None
+  */
+#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SDRAM device interrupt.
+  * @param  __INSTANCE__: FMC_SDRAM instance  
+  * @param  __INTERRUPT__: FMC_SDRAM interrupt 
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error      
+  * @retval None
+  */
+#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Get flag status of the SDRAM device.
+  * @param  __INSTANCE__: FMC_SDRAM instance  
+  * @param  __FLAG__: FMC_SDRAM flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
+  *            @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
+  *            @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear flag status of the SDRAM device.
+  * @param  __INSTANCE__: FMC_SDRAM instance  
+  * @param  __FLAG__: FMC_SDRAM flag
+  *         This parameter can be any combination of the following values:
+  *           @arg FMC_SDRAM_FLAG_REFRESH_ERROR
+  * @retval None
+  */
+#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SDRTR |= (__FLAG__))
+/**
+  * @}
+  */ 
+
+/* Exported functions --------------------------------------------------------*/
+
+/* FMC_NORSRAM Controller functions *******************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef  FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
+HAL_StatusTypeDef  FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+
+/* FMC_NORSRAM Control functions */
+HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+
+/* FMC_NAND Controller functions **********************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef  FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef  FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
+
+/* FMC_NAND Control functions */
+HAL_StatusTypeDef  FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
+
+/* FMC_PCCARD Controller functions ********************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef  FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
+HAL_StatusTypeDef  FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef  FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef  FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing); 
+HAL_StatusTypeDef  FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
+
+/* FMC_SDRAM Controller functions *********************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef  FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
+HAL_StatusTypeDef  FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+
+/* FMC_SDRAM Control functions */
+HAL_StatusTypeDef  FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
+HAL_StatusTypeDef  FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
+HAL_StatusTypeDef  FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
+uint32_t           FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_FMC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_fsmc.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,857 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_fsmc.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   FSMC Low Layer HAL module driver.
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
+  *           + Initialization/de-initialization functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                        ##### FSMC peripheral features #####
+  ==============================================================================                  
+    [..] The Flexible static memory controller (FSMC) includes two memory controllers:
+         (+) The NOR/PSRAM memory controller
+         (+) The NAND/PC Card memory controller
+       
+    [..] The FSMC functional block makes the interface with synchronous and asynchronous static
+         memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
+         (+) to translate AHB transactions into the appropriate external device protocol.
+         (+) to meet the access time requirements of the external memory devices.
+   
+    [..] All external memories share the addresses, data and control signals with the controller.
+         Each external device is accessed by means of a unique Chip Select. The FSMC performs
+         only one access at a time to an external device.
+         The main features of the FSMC controller are the following:
+          (+) Interface with static-memory mapped devices including:
+             (++) Static random access memory (SRAM).
+             (++) Read-only memory (ROM).
+             (++) NOR Flash memory/OneNAND Flash memory.
+             (++) PSRAM (4 memory banks).
+             (++) 16-bit PC Card compatible devices.
+             (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
+                  data.
+          (+) Independent Chip Select control for each memory bank.
+          (+) Independent configuration for each memory bank.          
+        
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FSMC 
+  * @brief FSMC driver modules
+  * @{
+  */
+
+#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/    
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup FSMC_Private_Functions
+  * @{
+  */
+
+/** @defgroup FSMC_NORSRAM Controller functions
+  * @brief    NORSRAM Controller functions 
+  *
+  @verbatim 
+  ==============================================================================   
+                   ##### How to use NORSRAM device driver #####
+  ==============================================================================
+ 
+  [..] 
+    This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
+    to run the NORSRAM external devices.
+      
+    (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit() 
+    (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
+    (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
+    (+) FSMC NORSRAM bank extended timing configuration using the function 
+        FSMC_NORSRAM_Extended_Timing_Init()
+    (+) FSMC NORSRAM bank enable/disable write operation using the functions
+        FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
+
+@endverbatim
+  * @{
+  */
+       
+/** @defgroup HAL_FSMC_NORSRAM_Group1 Initialization/de-initialization functions 
+  * @brief    Initialization and Configuration functions 
+  *
+  @verbatim    
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to:
+    (+) Initialize and configure the FSMC NORSRAM interface
+    (+) De-initialize the FSMC NORSRAM interface 
+    (+) Configure the FSMC clock and associated GPIOs    
+ 
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initialize the FSMC_NORSRAM device according to the specified
+  *         control parameters in the FSMC_NORSRAM_InitTypeDef
+  * @param  Device: Pointer to NORSRAM device instance
+  * @param  Init: Pointer to NORSRAM Initialization structure   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
+{ 
+  uint32_t tmpr = 0;
+    
+  /* Check the parameters */
+  assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
+  assert_param(IS_FSMC_MUX(Init->DataAddressMux));
+  assert_param(IS_FSMC_MEMORY(Init->MemoryType));
+  assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
+  assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
+  assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
+  assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
+  assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
+  assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
+  assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
+  assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
+  assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
+  assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
+  
+  /* Set NORSRAM device control parameters */
+  tmpr = (uint32_t)(Init->DataAddressMux       |\
+                    Init->MemoryType           |\
+                    Init->MemoryDataWidth      |\
+                    Init->BurstAccessMode      |\
+                    Init->WaitSignalPolarity   |\
+                    Init->WrapMode             |\
+                    Init->WaitSignalActive     |\
+                    Init->WriteOperation       |\
+                    Init->WaitSignal           |\
+                    Init->ExtendedMode         |\
+                    Init->AsynchronousWait     |\
+                    Init->WriteBurst
+                    );
+                    
+  if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
+  {
+    tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
+  }
+  
+  Device->BTCR[Init->NSBank] = tmpr;                   
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DeInitialize the FSMC_NORSRAM peripheral 
+  * @param  Device: Pointer to NORSRAM device instance
+  * @param  ExDevice: Pointer to NORSRAM extended mode device instance  
+  * @param  Bank: NORSRAM bank number  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
+
+  /* Disable the FSMC_NORSRAM device */
+  __FSMC_NORSRAM_DISABLE(Device, Bank);
+  
+  /* De-initialize the FSMC_NORSRAM device */
+  /* FSMC_NORSRAM_BANK1 */
+  if(Bank == FSMC_NORSRAM_BANK1)
+  {
+    Device->BTCR[Bank] = 0x000030DB;    
+  }
+  /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
+  else
+  {   
+    Device->BTCR[Bank] = 0x000030D2; 
+  }
+  
+  Device->BTCR[Bank + 1] = 0x0FFFFFFF;
+  ExDevice->BWTR[Bank]   = 0x0FFFFFFF;
+   
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initialize the FSMC_NORSRAM Timing according to the specified
+  *         parameters in the FSMC_NORSRAM_TimingTypeDef
+  * @param  Device: Pointer to NORSRAM device instance
+  * @param  Timing: Pointer to NORSRAM Timing structure
+  * @param  Bank: NORSRAM bank number  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
+{
+  uint32_t tmpr = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+  assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+  assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
+  assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+  assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
+  assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
+  assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
+  
+  /* Set FSMC_NORSRAM device timing parameters */  
+  tmpr = (uint32_t)(Timing->AddressSetupTime                  |\
+                   ((Timing->AddressHoldTime) << 4)          |\
+                   ((Timing->DataSetupTime) << 8)            |\
+                   ((Timing->BusTurnAroundDuration) << 16)   |\
+                   (((Timing->CLKDivision)-1) << 20)         |\
+                   (((Timing->DataLatency)-2) << 24)         |\
+                    (Timing->AccessMode)
+                    );
+  
+  Device->BTCR[Bank + 1] = tmpr; 
+  
+  return HAL_OK;   
+}
+
+/**
+  * @brief  Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
+  *         parameters in the FSMC_NORSRAM_TimingTypeDef
+  * @param  Device: Pointer to NORSRAM device instance
+  * @param  Timing: Pointer to NORSRAM Timing structure
+  * @param  Bank: NORSRAM bank number  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
+{
+  /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+  if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
+  {
+    /* Check the parameters */  
+    assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+    assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+    assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
+    assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+    assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
+    assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
+    assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
+  
+    Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime                 |\
+                                   ((Timing->AddressHoldTime) << 4)          |\
+                                   ((Timing->DataSetupTime) << 8)            |\
+                                   ((Timing->BusTurnAroundDuration) << 16)   |\
+                                   (((Timing->CLKDivision)-1) << 20)         |\
+                                   (((Timing->DataLatency)-2) << 24)         |\
+                                   (Timing->AccessMode));
+  }
+  else                                        
+  {
+    Device->BWTR[Bank] = 0x0FFFFFFF;
+  }   
+  
+  return HAL_OK;  
+}
+
+
+/**
+  * @}
+  */
+  
+  
+/** @defgroup HAL_FSMC_NORSRAM_Group3 Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### FSMC_NORSRAM Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the FSMC NORSRAM interface.
+
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Enables dynamically FSMC_NORSRAM write operation.
+  * @param  Device: Pointer to NORSRAM device instance
+  * @param  Bank: NORSRAM bank number   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+  /* Enable write operation */
+  Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE; 
+
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Disables dynamically FSMC_NORSRAM write operation.
+  * @param  Device: Pointer to NORSRAM device instance
+  * @param  Bank: NORSRAM bank number   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{ 
+  /* Disable write operation */
+  Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE; 
+
+  return HAL_OK;  
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/** @defgroup FSMC_PCCARD Controller functions
+  * @brief    PCCARD Controller functions 
+  *
+  @verbatim 
+  ==============================================================================   
+                    ##### How to use NAND device driver #####
+  ==============================================================================
+  [..]
+    This driver contains a set of APIs to interface with the FSMC NAND banks in order
+    to run the NAND external devices.
+  
+    (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit() 
+    (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
+    (+) FSMC NAND bank common space timing configuration using the function 
+        FSMC_NAND_CommonSpace_Timing_Init()
+    (+) FSMC NAND bank attribute space timing configuration using the function 
+        FSMC_NAND_AttributeSpace_Timing_Init()
+    (+) FSMC NAND bank enable/disable ECC correction feature using the functions
+        FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
+    (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()  
+
+@endverbatim
+  * @{
+  */
+    
+/** @defgroup HAL_FSMC_NAND_Group1 Initialization/de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to:
+    (+) Initialize and configure the FSMC NAND interface
+    (+) De-initialize the FSMC NAND interface 
+    (+) Configure the FSMC clock and associated GPIOs
+        
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initializes the FSMC_NAND device according to the specified
+  *         control parameters in the FSMC_NAND_HandleTypeDef
+  * @param  Device: Pointer to NAND device instance
+  * @param  Init: Pointer to NAND Initialization structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
+{
+  uint32_t tmppcr  = 0; 
+    
+  /* Check the parameters */
+  assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
+  assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
+  assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
+  assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
+  assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
+  assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
+  assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));   
+
+  /* Set NAND device control parameters */
+  tmppcr = (uint32_t)(Init->Waitfeature                |\
+                      FSMC_PCR_MEMORY_TYPE_NAND         |\
+                      Init->MemoryDataWidth            |\
+                      Init->EccComputation             |\
+                      Init->ECCPageSize                |\
+                      ((Init->TCLRSetupTime) << 9)     |\
+                      ((Init->TARSetupTime) << 13)
+                      );   
+  
+  if(Init->NandBank == FSMC_NAND_BANK2)
+  {
+    /* NAND bank 2 registers configuration */
+    Device->PCR2  = tmppcr;
+  }
+  else
+  {
+    /* NAND bank 3 registers configuration */
+    Device->PCR3  = tmppcr;
+  }
+  
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Initializes the FSMC_NAND Common space Timing according to the specified
+  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
+  * @param  Device: Pointer to NAND device instance
+  * @param  Timing: Pointer to NAND timing structure
+  * @param  Bank: NAND bank number   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+  uint32_t tmppmem = 0;  
+  
+  /* Check the parameters */
+  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+  
+  /* Set FSMC_NAND device timing parameters */
+  tmppmem = (uint32_t)(Timing->SetupTime                  |\
+                       ((Timing->WaitSetupTime) << 8)     |\
+                       ((Timing->HoldSetupTime) << 16)    |\
+                       ((Timing->HiZSetupTime) << 24)
+                       );
+                            
+  if(Bank == FSMC_NAND_BANK2)
+  {
+    /* NAND bank 2 registers configuration */
+    Device->PMEM2 = tmppmem;
+  }
+  else
+  {
+    /* NAND bank 3 registers configuration */
+    Device->PMEM3 = tmppmem;
+  }  
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Initializes the FSMC_NAND Attribute space Timing according to the specified
+  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
+  * @param  Device: Pointer to NAND device instance
+  * @param  Timing: Pointer to NAND timing structure
+  * @param  Bank: NAND bank number 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+  uint32_t tmppatt = 0;  
+  
+  /* Check the parameters */  
+  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+  
+  /* Set FSMC_NAND device timing parameters */
+  tmppatt = (uint32_t)(Timing->SetupTime                  |\
+                       ((Timing->WaitSetupTime) << 8)     |\
+                       ((Timing->HoldSetupTime) << 16)    |\
+                       ((Timing->HiZSetupTime) << 24)
+                       );
+                       
+  if(Bank == FSMC_NAND_BANK2)
+  {
+    /* NAND bank 2 registers configuration */
+    Device->PATT2 = tmppatt;
+  }
+  else
+  {
+    /* NAND bank 3 registers configuration */
+    Device->PATT3 = tmppatt;
+  }   
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DeInitializes the FSMC_NAND device 
+  * @param  Device: Pointer to NAND device instance
+  * @param  Bank: NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+  /* Disable the NAND Bank */
+  __FSMC_NAND_DISABLE(Device, Bank);
+ 
+  /* De-initialize the NAND Bank */
+  if(Bank == FSMC_NAND_BANK2)
+  {
+    /* Set the FSMC_NAND_BANK2 registers to their reset values */
+    Device->PCR2  = 0x00000018;
+    Device->SR2   = 0x00000040;
+    Device->PMEM2 = 0xFCFCFCFC;
+    Device->PATT2 = 0xFCFCFCFC;  
+  }
+  /* FSMC_Bank3_NAND */  
+  else
+  {
+    /* Set the FSMC_NAND_BANK3 registers to their reset values */
+    Device->PCR3  = 0x00000018;
+    Device->SR3   = 0x00000040;
+    Device->PMEM3 = 0xFCFCFCFC;
+    Device->PATT3 = 0xFCFCFCFC; 
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+  
+  
+/** @defgroup HAL_FSMC_NAND_Group3 Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+  ==============================================================================
+                       ##### FSMC_NAND Control functions #####
+  ==============================================================================  
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the FSMC NAND interface.
+
+@endverbatim
+  * @{
+  */ 
+
+    
+/**
+  * @brief  Enables dynamically FSMC_NAND ECC feature.
+  * @param  Device: Pointer to NAND device instance
+  * @param  Bank: NAND bank number
+  * @retval HAL status
+  */    
+HAL_StatusTypeDef  FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+  /* Enable ECC feature */
+  if(Bank == FSMC_NAND_BANK2)
+  {
+    Device->PCR2 |= FSMC_PCR2_ECCEN;
+  }
+  else
+  {
+    Device->PCR3 |= FSMC_PCR3_ECCEN;
+  } 
+  
+  return HAL_OK;  
+}
+
+
+/**
+  * @brief  Disables dynamically FSMC_NAND ECC feature.
+  * @param  Device: Pointer to NAND device instance
+  * @param  Bank: NAND bank number
+  * @retval HAL status
+  */  
+HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)  
+{  
+  /* Disable ECC feature */
+  if(Bank == FSMC_NAND_BANK2)
+  {
+    Device->PCR2 &= ~FSMC_PCR2_ECCEN;
+  }
+  else
+  {
+    Device->PCR3 &= ~FSMC_PCR3_ECCEN;
+  } 
+
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Disables dynamically FSMC_NAND ECC feature.
+  * @param  Device: Pointer to NAND device instance
+  * @param  ECCval: Pointer to ECC value
+  * @param  Bank: NAND bank number
+  * @param  Timeout: Timeout wait value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
+{
+  uint32_t timeout = 0;
+  
+  /* Check the parameters */ 
+  assert_param(IS_FSMC_NAND_DEVICE(Device)); 
+  assert_param(IS_FSMC_NAND_BANK(Bank));
+    
+  timeout = HAL_GetTick() + Timeout;
+  
+  /* Wait untill FIFO is empty */
+  while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        return HAL_TIMEOUT;
+      }
+    }   
+  }
+     
+  if(Bank == FSMC_NAND_BANK2)
+  {    
+    /* Get the ECCR2 register value */
+    *ECCval = (uint32_t)Device->ECCR2;
+  }
+  else
+  {    
+    /* Get the ECCR3 register value */
+    *ECCval = (uint32_t)Device->ECCR3;
+  }
+
+  return HAL_OK;  
+}
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+    
+/** @defgroup FSMC_PCCARD Controller functions
+  * @brief    PCCARD Controller functions 
+  *
+  @verbatim 
+  ==============================================================================  
+                    ##### How to use PCCARD device driver #####
+  ==============================================================================
+  [..]
+    This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
+    to run the PCCARD/compact flash external devices.
+  
+    (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit() 
+    (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
+    (+) FSMC PCCARD bank common space timing configuration using the function 
+        FSMC_PCCARD_CommonSpace_Timing_Init()
+    (+) FSMC PCCARD bank attribute space timing configuration using the function 
+        FSMC_PCCARD_AttributeSpace_Timing_Init()
+    (+) FSMC PCCARD bank IO space timing configuration using the function 
+        FSMC_PCCARD_IOSpace_Timing_Init()
+       
+@endverbatim
+  * @{
+  */
+  
+/** @defgroup HAL_FSMC_PCCARD_Group1 Initialization/de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to:
+    (+) Initialize and configure the FSMC PCCARD interface
+    (+) De-initialize the FSMC PCCARD interface 
+    (+) Configure the FSMC clock and associated GPIOs
+        
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initializes the FSMC_PCCARD device according to the specified
+  *         control parameters in the FSMC_PCCARD_HandleTypeDef
+  * @param  Device: Pointer to PCCARD device instance
+  * @param  Init: Pointer to PCCARD Initialization structure   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
+{
+  /* Check the parameters */ 
+  assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
+  assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
+  assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));     
+  
+  /* Set FSMC_PCCARD device control parameters */
+  Device->PCR4 = (uint32_t)(Init->Waitfeature               |\
+                            FSMC_NAND_PCC_MEM_BUS_WIDTH_16   |\
+                            (Init->TCLRSetupTime << 9)      |\
+                            (Init->TARSetupTime << 13));
+  
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Initializes the FSMC_PCCARD Common space Timing according to the specified
+  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
+  * @param  Device: Pointer to PCCARD device instance
+  * @param  Timing: Pointer to PCCARD timing structure 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+
+  /* Set PCCARD timing parameters */
+  Device->PMEM4 = (uint32_t)((Timing->SetupTime                 |\
+                             ((Timing->WaitSetupTime) << 8)     |\
+                              (Timing->HoldSetupTime) << 16)    |\
+                              ((Timing->HiZSetupTime) << 24)
+                             ); 
+
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Initializes the FSMC_PCCARD Attribute space Timing according to the specified
+  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
+  * @param  Device: Pointer to PCCARD device instance
+  * @param  Timing: Pointer to PCCARD timing structure  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
+{
+  /* Check the parameters */  
+  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+
+  /* Set PCCARD timing parameters */
+  Device->PATT4 = (uint32_t)((Timing->SetupTime                 |\
+                             ((Timing->WaitSetupTime) << 8)     |\
+                              (Timing->HoldSetupTime) << 16)    |\
+                              ((Timing->HiZSetupTime) << 24)
+                             );  
+                                        
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FSMC_PCCARD IO space Timing according to the specified
+  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
+  * @param  Device: Pointer to PCCARD device instance
+  * @param  Timing: Pointer to PCCARD timing structure  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
+{
+  /* Check the parameters */  
+  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+
+  /* Set FSMC_PCCARD device timing parameters */
+  Device->PIO4 = (uint32_t)((Timing->SetupTime                  |\
+                             ((Timing->WaitSetupTime) << 8)     |\
+                              (Timing->HoldSetupTime) << 16)    |\
+                              ((Timing->HiZSetupTime) << 24)
+                             );   
+  
+  return HAL_OK;
+}
+                                           
+/**
+  * @brief  DeInitializes the FSMC_PCCARD device 
+  * @param  Device: Pointer to PCCARD device instance
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
+{
+  /* Disable the FSMC_PCCARD device */
+  __FSMC_PCCARD_DISABLE(Device);
+  
+  /* De-initialize the FSMC_PCCARD device */
+  Device->PCR4    = 0x00000018; 
+  Device->SR4     = 0x00000000;	
+  Device->PMEM4   = 0xFCFCFCFC;
+  Device->PATT4   = 0xFCFCFCFC;
+  Device->PIO4    = 0xFCFCFCFC;
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#endif /* HAL_FSMC_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_fsmc.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1045 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_fsmc.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of FSMC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_FSMC_H
+#define __STM32F4xx_LL_FSMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FSMC
+  * @{
+  */ 
+
+/* Exported typedef ----------------------------------------------------------*/ 
+#define FSMC_NORSRAM_TypeDef            FSMC_Bank1_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TypeDef   FSMC_Bank1E_TypeDef
+#define FSMC_NAND_TypeDef               FSMC_Bank2_3_TypeDef
+#define FSMC_PCCARD_TypeDef             FSMC_Bank4_TypeDef
+
+#define FSMC_NORSRAM_DEVICE             FSMC_Bank1
+#define FSMC_NORSRAM_EXTENDED_DEVICE    FSMC_Bank1E
+#define FSMC_NAND_DEVICE                FSMC_Bank2_3
+#define FSMC_PCCARD_DEVICE              FSMC_Bank4
+
+/** 
+  * @brief  FSMC_NORSRAM Configuration Structure definition
+  */ 
+typedef struct
+{
+  uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
+                                              This parameter can be a value of @ref FSMC_NORSRAM_Bank                     */
+
+  uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
+                                              multiplexed on the data bus or not. 
+                                              This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing    */
+
+  uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
+                                              the corresponding memory device.
+                                              This parameter can be a value of @ref FSMC_Memory_Type                      */
+
+  uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
+                                              This parameter can be a value of @ref FSMC_NORSRAM_Data_Width               */
+
+  uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
+                                              valid only with synchronous burst Flash memories.
+                                              This parameter can be a value of @ref FSMC_Burst_Access_Mode                */
+
+  uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
+                                              the Flash memory in burst mode.
+                                              This parameter can be a value of @ref FSMC_Wait_Signal_Polarity             */
+
+  uint32_t WrapMode;                     /*!< Enables or disables the Wrapped burst access mode for Flash
+                                              memory, valid only when accessing Flash memories in burst mode.
+                                              This parameter can be a value of @ref FSMC_Wrap_Mode                        */
+
+  uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
+                                              clock cycle before the wait state or during the wait state,
+                                              valid only when accessing memories in burst mode. 
+                                              This parameter can be a value of @ref FSMC_Wait_Timing                      */
+
+  uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FSMC. 
+                                              This parameter can be a value of @ref FSMC_Write_Operation                  */
+
+  uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
+                                              signal, valid for Flash memory access in burst mode. 
+                                              This parameter can be a value of @ref FSMC_Wait_Signal                      */
+
+  uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
+                                              This parameter can be a value of @ref FSMC_Extended_Mode                    */
+
+  uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
+                                              valid only with asynchronous Flash memories.
+                                              This parameter can be a value of @ref FSMC_AsynchronousWait                 */
+
+  uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
+                                              This parameter can be a value of @ref FSMC_Write_Burst                      */
+
+}FSMC_NORSRAM_InitTypeDef;
+
+/** 
+  * @brief  FSMC_NORSRAM Timing parameters structure definition
+  */
+typedef struct
+{
+  uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the address setup time. 
+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+                                              @note This parameter is not used with synchronous NOR Flash memories.      */
+
+  uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the address hold time.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15. 
+                                              @note This parameter is not used with synchronous NOR Flash memories.      */
+
+  uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the data setup time.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 255.
+                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 
+                                              NOR Flash memories.                                                        */
+
+  uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the bus turnaround.
+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+                                              @note This parameter is only used for multiplexed NOR Flash memories.      */
+
+  uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of 
+                                              HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
+                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 
+                                              accesses.                                                                  */
+
+  uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
+                                              to the memory before getting the first data.
+                                              The parameter value depends on the memory type as shown below:
+                                              - It must be set to 0 in case of a CRAM
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
+                                              - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
+                                                with synchronous burst mode enable                                       */
+
+  uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode. 
+                                              This parameter can be a value of @ref FSMC_Access_Mode                      */
+
+}FSMC_NORSRAM_TimingTypeDef;
+
+/** 
+  * @brief  FSMC_NAND Configuration Structure definition
+  */ 
+typedef struct
+{
+  uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.
+                                        This parameter can be a value of @ref FSMC_NAND_Bank                   */
+
+  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.
+                                        This parameter can be any value of @ref FSMC_Wait_feature              */
+
+  uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.
+                                        This parameter can be any value of @ref FSMC_NAND_Data_Width           */
+
+  uint32_t EccComputation;         /*!< Enables or disables the ECC computation.
+                                        This parameter can be any value of @ref FSMC_ECC                       */
+
+  uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.
+                                        This parameter can be any value of @ref FSMC_ECC_Page_Size             */
+
+  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
+                                        delay between CLE low and RE low.
+                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
+
+  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
+                                        delay between ALE low and RE low.
+                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FSMC_NAND_InitTypeDef;  
+
+/** 
+  * @brief  FSMC_NAND_PCCARD Timing parameters structure definition
+  */
+typedef struct
+{
+  uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before
+                                      the command assertion for NAND-Flash read or write access
+                                      to common/Attribute or I/O memory space (depending on
+                                      the memory space timing to be configured).
+                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255    */
+
+  uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the
+                                      command for NAND-Flash read or write access to
+                                      common/Attribute or I/O memory space (depending on the
+                                      memory space timing to be configured). 
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
+
+  uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address
+                                      (and data for write access) after the command de-assertion
+                                      for NAND-Flash read or write access to common/Attribute
+                                      or I/O memory space (depending on the memory space timing
+                                      to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
+
+  uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the
+                                      data bus is kept in HiZ after the start of a NAND-Flash
+                                      write access to common/Attribute or I/O memory space (depending
+                                      on the memory space timing to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
+
+}FSMC_NAND_PCC_TimingTypeDef;
+
+/** 
+  * @brief  FSMC_NAND Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the PCCARD Memory device.
+                                        This parameter can be any value of @ref FSMC_Wait_feature              */
+
+  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
+                                        delay between CLE low and RE low.
+                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
+
+  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
+                                        delay between ALE low and RE low.
+                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FSMC_PCCARD_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FSMC_NOR_SRAM_Controller 
+  * @{
+  */ 
+  
+/** @defgroup FSMC_NORSRAM_Bank 
+  * @{
+  */
+#define FSMC_NORSRAM_BANK1                       ((uint32_t)0x00000000)
+#define FSMC_NORSRAM_BANK2                       ((uint32_t)0x00000002)
+#define FSMC_NORSRAM_BANK3                       ((uint32_t)0x00000004)
+#define FSMC_NORSRAM_BANK4                       ((uint32_t)0x00000006)
+
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_NORSRAM_BANK1) || \
+                                    ((BANK) == FSMC_NORSRAM_BANK2) || \
+                                    ((BANK) == FSMC_NORSRAM_BANK3) || \
+                                    ((BANK) == FSMC_NORSRAM_BANK4))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing 
+  * @{
+  */
+
+#define FSMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000)
+#define FSMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)0x00000002)
+
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
+                          ((MUX) == FSMC_DATA_ADDRESS_MUX_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Memory_Type 
+  * @{
+  */
+
+#define FSMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000)
+#define FSMC_MEMORY_TYPE_PSRAM                   ((uint32_t)0x00000004)
+#define FSMC_MEMORY_TYPE_NOR                     ((uint32_t)0x00000008)
+
+
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MEMORY_TYPE_SRAM) || \
+                                ((MEMORY) == FSMC_MEMORY_TYPE_PSRAM)|| \
+                                ((MEMORY) == FSMC_MEMORY_TYPE_NOR))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_NORSRAM_Data_Width 
+  * @{
+  */
+
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000)
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)0x00000010)
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)0x00000020)
+
+#define IS_FSMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
+                                             ((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+                                             ((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_NORSRAM_Flash_Access 
+  * @{
+  */
+#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)0x00000040)
+#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Burst_Access_Mode 
+  * @{
+  */
+
+#define FSMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000) 
+#define FSMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)0x00000100)
+
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
+                                  ((STATE) == FSMC_BURST_ACCESS_MODE_ENABLE))
+/**
+  * @}
+  */
+    
+
+/** @defgroup FSMC_Wait_Signal_Polarity 
+  * @{
+  */
+#define FSMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000)
+#define FSMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)0x00000200)
+
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
+                                         ((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wrap_Mode 
+  * @{
+  */
+#define FSMC_WRAP_MODE_DISABLE                   ((uint32_t)0x00000000)
+#define FSMC_WRAP_MODE_ENABLE                    ((uint32_t)0x00000400)
+
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WRAP_MODE_DISABLE) || \
+                                 ((MODE) == FSMC_WRAP_MODE_ENABLE)) 
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Timing 
+  * @{
+  */
+#define FSMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000)
+#define FSMC_WAIT_TIMING_DURING_WS               ((uint32_t)0x00000800)
+
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WAIT_TIMING_BEFORE_WS) || \
+                                            ((ACTIVE) == FSMC_WAIT_TIMING_DURING_WS)) 
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Write_Operation 
+  * @{
+  */
+#define FSMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000)
+#define FSMC_WRITE_OPERATION_ENABLE              ((uint32_t)0x00001000)
+
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WRITE_OPERATION_DISABLE) || \
+                                            ((OPERATION) == FSMC_WRITE_OPERATION_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Signal 
+  * @{
+  */
+#define FSMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000)
+#define FSMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)0x00002000)
+
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WAIT_SIGNAL_DISABLE) || \
+                                      ((SIGNAL) == FSMC_WAIT_SIGNAL_ENABLE)) 
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Extended_Mode 
+  * @{
+  */
+#define FSMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000)
+#define FSMC_EXTENDED_MODE_ENABLE                ((uint32_t)0x00004000)
+
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_EXTENDED_MODE_DISABLE) || \
+                                     ((MODE) == FSMC_EXTENDED_MODE_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_AsynchronousWait 
+  * @{
+  */
+#define FSMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000)
+#define FSMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)0x00008000)
+
+#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+                                 ((STATE) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
+
+/**
+  * @}
+  */  
+
+/** @defgroup FSMC_Write_Burst 
+  * @{
+  */
+
+#define FSMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000)
+#define FSMC_WRITE_BURST_ENABLE                  ((uint32_t)0x00080000)
+
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WRITE_BURST_DISABLE) || \
+                                    ((BURST) == FSMC_WRITE_BURST_ENABLE)) 
+
+/**
+  * @}
+  */
+  
+/** @defgroup FSMC_Continous_Clock 
+  * @{
+  */
+
+#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY          ((uint32_t)0x00000000)
+#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC         ((uint32_t)0x00100000)
+
+#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+                                         ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 
+
+/**
+  * @}
+  */
+  
+/** @defgroup FSMC_Address_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Address_Hold_Time 
+  * @{
+  */
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Bus_Turn_around_Duration 
+  * @{
+  */
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_CLK_Division 
+  * @{
+  */
+#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Latency 
+  * @{
+  */
+#define IS_FSMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
+/**
+  * @}
+  */  
+
+/** @defgroup FSMC_Access_Mode 
+  * @{
+  */
+#define FSMC_ACCESS_MODE_A                        ((uint32_t)0x00000000)
+#define FSMC_ACCESS_MODE_B                        ((uint32_t)0x10000000) 
+#define FSMC_ACCESS_MODE_C                        ((uint32_t)0x20000000)
+#define FSMC_ACCESS_MODE_D                        ((uint32_t)0x30000000)
+
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_ACCESS_MODE_A) || \
+                                   ((MODE) == FSMC_ACCESS_MODE_B) || \
+                                   ((MODE) == FSMC_ACCESS_MODE_C) || \
+                                   ((MODE) == FSMC_ACCESS_MODE_D))
+/**
+  * @}
+  */
+    
+/**
+  * @}
+  */  
+
+/** @defgroup FSMC_NAND_Controller 
+  * @{
+  */
+
+/** @defgroup FSMC_NAND_Bank 
+  * @{
+  */  
+#define FSMC_NAND_BANK2                          ((uint32_t)0x00000010)
+#define FSMC_NAND_BANK3                          ((uint32_t)0x00000100)
+
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
+                                 ((BANK) == FSMC_NAND_BANK3))  
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_feature 
+  * @{
+  */
+#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE           ((uint32_t)0x00000000)
+#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE            ((uint32_t)0x00000002)
+
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+                                       ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_PCR_Memory_Type 
+  * @{
+  */
+#define FSMC_PCR_MEMORY_TYPE_PCCARD        ((uint32_t)0x00000000)
+#define FSMC_PCR_MEMORY_TYPE_NAND          ((uint32_t)0x00000008)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_NAND_Data_Width 
+  * @{
+  */
+#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8                ((uint32_t)0x00000000)
+#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16               ((uint32_t)0x00000010)
+
+#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+                                          ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_ECC 
+  * @{
+  */
+#define FSMC_NAND_ECC_DISABLE                    ((uint32_t)0x00000000)
+#define FSMC_NAND_ECC_ENABLE                     ((uint32_t)0x00000040)
+
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
+                                  ((STATE) == FSMC_NAND_ECC_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_ECC_Page_Size 
+  * @{
+  */
+#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE          ((uint32_t)0x00000000)
+#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE          ((uint32_t)0x00020000)
+#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE         ((uint32_t)0x00040000)
+#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE         ((uint32_t)0x00060000)
+#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE         ((uint32_t)0x00080000)
+#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE         ((uint32_t)0x000A0000)
+
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \
+                                    ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \
+                                    ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+                                    ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+                                    ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+                                    ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_TCLR_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_TAR_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Hold_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_HiZ_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
+/**
+  * @}
+  */  
+    
+/**
+  * @}
+  */  
+  
+
+/** @defgroup FSMC_NORSRAM_Device_Instance
+  * @{
+  */
+#define IS_FSMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_DEVICE)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance
+  * @{
+  */
+#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_EXTENDED_DEVICE)
+
+/**
+  * @}
+  */
+  
+  /** @defgroup FSMC_NAND_Device_Instance
+  * @{
+  */
+#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
+
+/**
+  * @}
+  */  
+
+/** @defgroup FSMC_PCCARD_Device_Instance
+  * @{
+  */
+#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
+
+/**
+  * @}
+  */ 
+   
+/** @defgroup FSMC_Interrupt_definition 
+  * @brief FSMC Interrupt definition
+  * @{
+  */  
+#define FSMC_IT_RISING_EDGE                ((uint32_t)0x00000008)
+#define FSMC_IT_LEVEL                      ((uint32_t)0x00000010)
+#define FSMC_IT_FALLING_EDGE               ((uint32_t)0x00000020)
+#define FSMC_IT_REFRESH_ERROR              ((uint32_t)0x00004000)
+
+#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RISING_EDGE)  || \
+                            ((IT) == FSMC_IT_LEVEL)        || \
+                            ((IT) == FSMC_IT_FALLING_EDGE) || \
+                            ((IT) == FSMC_IT_REFRESH_ERROR)) 
+/**
+  * @}
+  */
+    
+/** @defgroup FSMC_Flag_definition 
+  * @brief FSMC Flag definition
+  * @{
+  */ 
+#define FSMC_FLAG_RISING_EDGE                    ((uint32_t)0x00000001)
+#define FSMC_FLAG_LEVEL                          ((uint32_t)0x00000002)
+#define FSMC_FLAG_FALLING_EDGE                   ((uint32_t)0x00000004)
+#define FSMC_FLAG_FEMPT                          ((uint32_t)0x00000040)
+
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RISING_EDGE)  || \
+                                ((FLAG) == FSMC_FLAG_LEVEL)        || \
+                                ((FLAG) == FSMC_FLAG_FALLING_EDGE) || \
+                                ((FLAG) == FSMC_FLAG_FEMPT))
+
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+                               
+
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+
+
+/** @defgroup FSMC_NOR_Macros
+ *  @brief macros to handle NOR device enable/disable and read/write operations
+ *  @{
+ */
+ 
+/**
+  * @brief  Enable the NORSRAM device access.
+  * @param  __INSTANCE__: FSMC_NORSRAM Instance
+  * @param  __BANK__: FSMC_NORSRAM Bank    
+  * @retval none
+  */ 
+#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
+
+/**
+  * @brief  Disable the NORSRAM device access.
+  * @param  __INSTANCE__: FSMC_NORSRAM Instance
+  * @param  __BANK__: FSMC_NORSRAM Bank   
+  * @retval none
+  */ 
+#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)  
+
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup FSMC_NAND_Macros
+ *  @brief macros to handle NAND device enable/disable
+ *  @{
+ */
+ 
+/**
+  * @brief  Enable the NAND device access.
+  * @param  __INSTANCE__: FSMC_NAND Instance
+  * @param  __BANK__: FSMC_NAND Bank    
+  * @retval none
+  */  
+#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__)  (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
+                                                    ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
+                                         
+
+/**
+  * @brief  Disable the NAND device access.
+  * @param  __INSTANCE__: FSMC_NAND Instance
+  * @param  __BANK__: FSMC_NAND Bank  
+  * @retval none
+  */                                          
+#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
+                                                   ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
+                                         
+                                        
+/**
+  * @}
+  */ 
+  
+/** @defgroup FSMC_PCCARD_Macros
+ *  @brief macros to handle SRAM read/write operations 
+ *  @{
+ */
+
+/**
+  * @brief  Enable the PCCARD device access.
+  * @param  __INSTANCE__: FSMC_PCCARD Instance  
+  * @retval none
+  */ 
+#define __FSMC_PCCARD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
+
+/**
+  * @brief  Disable the PCCARD device access.
+  * @param  __INSTANCE__: FSMC_PCCARD Instance   
+  * @retval none
+  */ 
+#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
+
+/**
+  * @}
+  */
+  
+/** @defgroup FSMC_Interrupt
+ *  @brief macros to handle FSMC interrupts
+ * @{
+ */ 
+
+/**
+  * @brief  Enable the NAND device interrupt.
+  * @param  __INSTANCE__: FSMC_NAND Instance
+  * @param  __BANK__: FSMC_NAND Bank 
+  * @param  __INTERRUPT__: FSMC_NAND interrupt 
+  *         This parameter can be any combination of the following values:
+  *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg FSMC_IT_LEVEL: Interrupt level.
+  *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.        
+  * @retval None
+  */  
+#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
+                                                                                                      ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
+
+/**
+  * @brief  Disable the NAND device interrupt.
+  * @param  __INSTANCE__: FSMC_NAND Instance
+  * @param  __BANK__: FSMC_NAND Bank 
+  * @param  __INTERRUPT__: FSMC_NAND interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg FSMC_IT_LEVEL: Interrupt level.
+  *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.    
+  * @retval None
+  */
+#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
+                                                                                                      ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) 
+                                                                                                                             
+/**
+  * @brief  Get flag status of the NAND device.
+  * @param  __INSTANCE__: FSMC_NAND Instance
+  * @param  __BANK__: FSMC_NAND Bank 
+  * @param  __FLAG__: FSMC_NAND flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.   
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
+                                                                                                (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+/**
+  * @brief  Clear flag status of the NAND device.
+  * @param  __INSTANCE__: FSMC_NAND Instance
+  * @param  __BANK__: FSMC_NAND Bank 
+  * @param  __FLAG__: FSMC_NAND flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.   
+  * @retval None
+  */
+#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
+                                                                                                  ((__INSTANCE__)->SR3 &= ~(__FLAG__))) 
+/**
+  * @brief  Enable the PCCARD device interrupt.
+  * @param  __INSTANCE__: FSMC_PCCARD Instance  
+  * @param  __INTERRUPT__: FSMC_PCCARD interrupt 
+  *         This parameter can be any combination of the following values:
+  *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg FSMC_IT_LEVEL: Interrupt level.
+  *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.        
+  * @retval None
+  */ 
+#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the PCCARD device interrupt.
+  * @param  __INSTANCE__: FSMC_PCCARD Instance  
+  * @param  __INTERRUPT__: FSMC_PCCARD interrupt 
+  *         This parameter can be any combination of the following values:
+  *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg FSMC_IT_LEVEL: Interrupt level.
+  *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.        
+  * @retval None
+  */ 
+#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) 
+
+/**
+  * @brief  Get flag status of the PCCARD device.
+  * @param  __INSTANCE__: FSMC_PCCARD Instance    
+  * @param  __FLAG__: FSMC_PCCARD flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.   
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear flag status of the PCCARD device.
+  * @param  __INSTANCE__: FSMC_PCCARD Instance   
+  * @param  __FLAG__: FSMC_PCCARD flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.   
+  * @retval None
+  */
+#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SR4 &= ~(__FLAG__))
+
+/**
+  * @}
+  */ 
+
+/* Exported functions --------------------------------------------------------*/
+
+/* FSMC_NORSRAM Controller functions ******************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef  FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
+HAL_StatusTypeDef  FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+
+/* FSMC_NORSRAM Control functions */
+HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+
+/* FSMC_NAND Controller functions *********************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef  FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef  FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+
+/* FSMC_NAND Control functions */
+HAL_StatusTypeDef  FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
+
+/* FSMC_PCCARD Controller functions *******************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef  FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
+HAL_StatusTypeDef  FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef  FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef  FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); 
+HAL_StatusTypeDef  FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
+
+/* FSMC APIs, macros and typedefs redefinition */
+#define FMC_NORSRAM_TypeDef                   FSMC_NORSRAM_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef          FSMC_NORSRAM_EXTENDED_TypeDef
+#define FMC_NORSRAM_InitTypeDef               FSMC_NORSRAM_InitTypeDef
+#define FMC_NORSRAM_TimingTypeDef             FSMC_NORSRAM_TimingTypeDef
+
+#define FMC_NORSRAM_Init                      FSMC_NORSRAM_Init
+#define FMC_NORSRAM_Timing_Init               FSMC_NORSRAM_Timing_Init
+#define FMC_NORSRAM_Extended_Timing_Init      FSMC_NORSRAM_Extended_Timing_Init
+#define FMC_NORSRAM_DeInit                    FSMC_NORSRAM_DeInit
+#define FMC_NORSRAM_WriteOperation_Enable     FSMC_NORSRAM_WriteOperation_Enable
+#define FMC_NORSRAM_WriteOperation_Disable    FSMC_NORSRAM_WriteOperation_Disable
+
+#define __FMC_NORSRAM_ENABLE                  __FSMC_NORSRAM_ENABLE
+#define __FMC_NORSRAM_DISABLE                 __FSMC_NORSRAM_DISABLE 
+
+#define FMC_NAND_InitTypeDef                  FSMC_NAND_InitTypeDef
+#define FMC_PCCARD_InitTypeDef                FSMC_PCCARD_InitTypeDef
+#define FMC_NAND_PCC_TimingTypeDef            FSMC_NAND_PCC_TimingTypeDef
+
+#define FMC_NAND_Init                         FSMC_NAND_Init
+#define FMC_NAND_CommonSpace_Timing_Init      FSMC_NAND_CommonSpace_Timing_Init
+#define FMC_NAND_AttributeSpace_Timing_Init   FSMC_NAND_AttributeSpace_Timing_Init
+#define FMC_NAND_DeInit                       FSMC_NAND_DeInit
+#define FMC_NAND_ECC_Enable                   FSMC_NAND_ECC_Enable
+#define FMC_NAND_ECC_Disable                  FSMC_NAND_ECC_Disable
+#define FMC_NAND_GetECC                       FSMC_NAND_GetECC
+#define FMC_PCCARD_Init                       FSMC_PCCARD_Init
+#define FMC_PCCARD_CommonSpace_Timing_Init    FSMC_PCCARD_CommonSpace_Timing_Init
+#define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
+#define FMC_PCCARD_IOSpace_Timing_Init        FSMC_PCCARD_IOSpace_Timing_Init
+#define FMC_PCCARD_DeInit                     FSMC_PCCARD_DeInit
+
+#define __FMC_NAND_ENABLE                     __FSMC_NAND_ENABLE
+#define __FMC_NAND_DISABLE                    __FSMC_NAND_DISABLE
+#define __FMC_PCCARD_ENABLE                   __FSMC_PCCARD_ENABLE
+#define __FMC_PCCARD_DISABLE                  __FSMC_PCCARD_DISABLE
+#define __FMC_NAND_ENABLE_IT                  __FSMC_NAND_ENABLE_IT
+#define __FMC_NAND_DISABLE_IT                 __FSMC_NAND_DISABLE_IT
+#define __FMC_NAND_GET_FLAG                   __FSMC_NAND_GET_FLAG
+#define __FMC_NAND_CLEAR_FLAG                 __FSMC_NAND_CLEAR_FLAG
+#define __FMC_PCCARD_ENABLE_IT                __FSMC_PCCARD_ENABLE_IT
+#define __FMC_PCCARD_DISABLE_IT               __FSMC_PCCARD_DISABLE_IT
+#define __FMC_PCCARD_GET_FLAG                 __FSMC_PCCARD_GET_FLAG
+#define __FMC_PCCARD_CLEAR_FLAG               __FSMC_PCCARD_CLEAR_FLAG
+
+#define FMC_NORSRAM_TypeDef                   FSMC_NORSRAM_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef          FSMC_NORSRAM_EXTENDED_TypeDef
+#define FMC_NAND_TypeDef                      FSMC_NAND_TypeDef
+#define FMC_PCCARD_TypeDef                    FSMC_PCCARD_TypeDef
+
+#define FMC_NORSRAM_DEVICE                    FSMC_NORSRAM_DEVICE            
+#define FMC_NORSRAM_EXTENDED_DEVICE           FSMC_NORSRAM_EXTENDED_DEVICE   
+#define FMC_NAND_DEVICE                       FSMC_NAND_DEVICE             
+#define FMC_PCCARD_DEVICE                     FSMC_PCCARD_DEVICE 
+
+#define FMC_NAND_BANK2                        FSMC_NAND_BANK2
+
+#define FMC_IT_RISING_EDGE                    FSMC_IT_RISING_EDGE
+#define FMC_IT_LEVEL                          FSMC_IT_LEVEL
+#define FMC_IT_FALLING_EDGE                   FSMC_IT_FALLING_EDGE
+#define FMC_IT_REFRESH_ERROR                  FSMC_IT_REFRESH_ERROR
+
+#define FMC_FLAG_RISING_EDGE                  FSMC_FLAG_RISING_EDGE
+#define FMC_FLAG_LEVEL                        FSMC_FLAG_LEVEL
+#define FMC_FLAG_FALLING_EDGE                 FSMC_FLAG_FALLING_EDGE
+#define FMC_FLAG_FEMPT                        FSMC_FLAG_FEMPT
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_FSMC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,556 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_sdmmc.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   SDMMC Low Layer HAL module driver.
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the SDMMC peripheral:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                       ##### SDMMC peripheral features #####
+  ==============================================================================        
+    [..] The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2
+         peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA
+         devices.
+
+    [..] The MultiMedia Card system specifications are available through the MultiMedia Card
+         Association website at www.mmca.org, published by the MMCA technical committee.
+         SD memory card and SD I/O card system specifications are available through the SD card
+         Association website at www.sdcard.org.
+         CE-ATA system specifications are available through the CE-ATA work group web site at
+         www.ce-ata.org.
+    
+    [..] The SDIO features include the following:
+         (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
+             for three different databus modes: 1-bit (default), 4-bit and 8-bit
+         (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
+         (+) Full compliance with SD Memory Card Specifications Version 2.0
+         (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
+             different data bus modes: 1-bit (default) and 4-bit
+         (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
+             Rev1.1)
+         (+) Data transfer up to 48 MHz for the 8 bit mode
+         (+) Data and command output enable signals to control external bidirectional drivers.
+                 
+   
+                           ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      This driver is a considered as a driver of service for external devices drivers 
+      that interfaces with the SDIO peripheral.
+      According to the device used (SD card/ MMC card / SDIO card ...), a set of APIs 
+      is used in the device's driver to perform SDIO operations and functionalities.
+   
+      This driver is almost transparent for the final user, it is only used to implement other
+      functionalities of the external device.
+   
+    [..]
+      (+) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL 
+          (PLL48CLK). Before start working with SDIO peripheral make sure that the
+          PLL is well configured.
+          The SDIO peripheral uses two clock signals:
+          (++) SDIO adapter clock (SDIOCLK = 48 MHz)
+          (++) APB2 bus clock (PCLK2)
+       
+          -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition:
+               Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
+  
+      (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO
+          peripheral.
+
+      (+) Enable the Power ON State using the HAL_SDIO_PowerState_ON(hsdio) 
+          function and disable it using the function HAL_SDIO_PowerState_OFF(hsdio).
+                
+      (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
+  
+      (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hsdio, IT) 
+          and __SDIO_DISABLE_IT(hsdio, IT) if you need to use interrupt mode. 
+  
+      (+) When using the DMA mode 
+          (++) Configure the DMA in the MSP layer of the external device
+          (++) Active the needed channel Request 
+          (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro
+               __SDIO_DMA_DISABLE().
+  
+      (+) To control the CPSM (Command Path State Machine) and send 
+          commands to the card use the HAL_SDIO_SendCommand(), 
+          HAL_SDIO_GetCommandResponse() and HAL_SDIO_GetResponse() functions. First, user has
+          to fill the command structure (pointer to SDIO_CmdInitTypeDef) according 
+          to the selected command to be sent.
+          The parameters that should be filled are:
+           (++) Command Argument
+           (++) Command Index
+           (++) Command Response type
+           (++) Command Wait
+           (++) CPSM Status (Enable or Disable).
+  
+          -@@- To check if the command is well received, read the SDIO_CMDRESP
+              register using the HAL_SDIO_GetCommandResponse().
+              The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
+              HAL_SDIO_GetResponse() function.
+  
+      (+) To control the DPSM (Data Path State Machine) and send/receive 
+           data to/from the card use the HAL_SDIO_DataConfig(), HAL_SDIO_GetDataCounter(), 
+          HAL_SDIO_ReadFIFO(), HAL_SDIO_WriteFIFO() and HAL_SDIO_GetFIFOCount() functions.
+  
+    *** Read Operations ***
+    =======================
+    [..]
+      (#) First, user has to fill the data structure (pointer to
+          SDIO_DataInitTypeDef) according to the selected data type to be received.
+          The parameters that should be filled are:
+           (++) Data TimeOut
+           (++) Data Length
+           (++) Data Block size
+           (++) Data Transfer direction: should be from card (To SDIO)
+           (++) Data Transfer mode
+           (++) DPSM Status (Enable or Disable)
+                                     
+      (#) Configure the SDIO resources to receive the data from the card
+          according to selected transfer mode (Refer to Step 8, 9 and 10).
+  
+      (#) Send the selected Read command (refer to step 11).
+                    
+      (#) Use the SDIO flags/interrupts to check the transfer status.
+  
+    *** Write Operations ***
+    ========================
+    [..]
+     (#) First, user has to fill the data structure (pointer to
+         SDIO_DataInitTypeDef) according to the selected data type to be received.
+         The parameters that should be filled are:
+          (++) Data TimeOut
+          (++) Data Length
+          (++) Data Block size
+          (++) Data Transfer direction:  should be to card (To CARD)
+          (++) Data Transfer mode
+          (++) DPSM Status (Enable or Disable)
+  
+     (#) Configure the SDIO resources to send the data to the card according to 
+         selected transfer mode (Refer to Step 8, 9 and 10).
+                     
+     (#) Send the selected Write command (refer to step 11).
+                    
+     (#) Use the SDIO flags/interrupts to check the transfer status.
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SDMMC 
+  * @brief SDMMC HAL module driver
+  * @{
+  */
+
+#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SDIO_Private_Functions
+  * @{
+  */
+
+/** @defgroup HAL_SDIO_Group1 Initialization/de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization/de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SDIO according to the specified
+  *         parameters in the SDIO_InitTypeDef and create the associated handle.
+  * @param  SDIOx: Pointer to SDIO register base
+  * @param  Init: SDIO initialization structure   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
+{
+  __IO uint32_t tmpreg = 0; 
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
+  assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge)); 
+  assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass));
+  assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave));
+  assert_param(IS_SDIO_BUS_WIDE(Init.BusWide));
+  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
+  assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
+  
+  /* Get the SDIO CLKCR value */
+  tmpreg = SDIOx->CLKCR;
+  
+  /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
+  tmpreg &= CLKCR_CLEAR_MASK;
+  
+  /* Set SDIO configuration parameters */
+  tmpreg |= (Init.ClockEdge           |\
+             Init.ClockBypass         |\
+             Init.ClockPowerSave      |\
+             Init.BusWide             |\
+             Init.HardwareFlowControl |\
+             Init.ClockDiv
+             ); 
+  
+  /* Write to SDIO CLKCR */
+  SDIOx->CLKCR = tmpreg;  
+
+  return HAL_OK;
+}
+
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SDIO_Group2 I/O operation functions 
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### I/O operation functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the SDIO data 
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read data (word) from Rx FIFO in blocking mode (polling) 
+  * @param  SDIOx: Pointer to SDIO register base
+  * @param  ReadData: Data to read
+  * @retval HAL status
+  */
+uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
+{
+  /* Read data from Rx FIFO */ 
+  return (SDIOx->FIFO);
+}
+
+/**
+  * @brief  Write data (word) to Tx FIFO in blocking mode (polling) 
+  * @param  SDIOx: Pointer to SDIO register base
+  * @param  pWriteData: pointer to data to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
+{ 
+  /* Write data to FIFO */ 
+  SDIOx->FIFO = *pWriteData;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SDIO_Group3 Peripheral Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the SDIO data 
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set SDIO Power state to ON. 
+  * @param  SDIOx: Pointer to SDIO register base
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
+{  
+  /* Set power state to ON */ 
+  SDIOx->POWER = (uint32_t)0x00000003;
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Set SDIO Power state to OFF. 
+  * @param  SDIOx: Pointer to SDIO register base
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
+{
+  /* Set power state to OFF */
+  SDIOx->POWER = (uint32_t)0x00000000;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get SDIO Power state. 
+  * @param  SDIOx: Pointer to SDIO register base
+  * @retval Power status of the controller. The returned value can be one of the 
+  *         following values:
+  *            - 0x00: Power OFF
+  *            - 0x02: Power UP
+  *            - 0x03: Power ON 
+  */
+uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)  
+{
+  return (SDIOx->POWER & (~PWR_PWRCTRL_MASK));
+}
+
+/**
+  * @brief  Configure the SDIO command path according to the specified parameters in
+  *         SDIO_CmdInitTypeDef structure and send the command 
+  * @param  SDIOx: Pointer to SDIO register base
+  * @param  SDIO_CmdInitStruct: pointer to a SDIO_CmdInitTypeDef structure that contains 
+  *         the configuration information for the SDIO command
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->CmdIndex));
+  assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->Response));
+  assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->WaitForInterrupt));
+  assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->CPSM));
+
+  /* Set the SDIO Argument value */
+  SDIOx->ARG = SDIO_CmdInitStruct->Argument;
+  
+  /* SDIO CMD Configuration */  
+  /* Get the SDIO CMD value */
+  tmpreg = SDIOx->CMD;
+  
+  /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
+  tmpreg &= CMD_CLEAR_MASK;
+  
+  /* Set SDIO command parameters */
+  tmpreg |= (uint32_t)(SDIO_CmdInitStruct->CmdIndex         |\
+                       SDIO_CmdInitStruct->Response         |\
+                       SDIO_CmdInitStruct->WaitForInterrupt |\
+                       SDIO_CmdInitStruct->CPSM);
+  
+  /* Write to SDIO CMD register */
+  SDIOx->CMD = tmpreg;
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Return the command index of last command for which response received
+  * @param  SDIOx: Pointer to SDIO register base
+  * @retval Command index of the last command response received
+  */
+uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
+{
+  return (uint8_t)(SDIOx->RESPCMD);
+}
+
+
+/**
+  * @brief  Return the response received from the card for the last command
+  * @param  SDIO_RESP: Specifies the SDIO response register. 
+  *          This parameter can be one of the following values:
+  *            @arg SDIO_RESP1: Response Register 1
+  *            @arg SDIO_RESP2: Response Register 2
+  *            @arg SDIO_RESP3: Response Register 3
+  *            @arg SDIO_RESP4: Response Register 4  
+  * @retval The Corresponding response register value
+  */
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_RESP(SDIO_RESP));
+
+  /* Get the response */
+  tmp = SDIO_RESP_ADDR + SDIO_RESP;
+  
+  return (*(__IO uint32_t *) tmp);
+}  
+
+/**
+  * @brief  Configure the SDIO data path according to the specified 
+  *         parameters in the SDIO_DataInitTypeDef.
+  * @param  SDIOx: Pointer to SDIO register base  
+  * @param  SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure 
+  *         that contains the configuration information for the SDIO command.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->DataLength));
+  assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->DataBlockSize));
+  assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->TransferDir));
+  assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->TransferMode));
+  assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSM));
+
+  /* Set the SDIO Data TimeOut value */
+  SDIOx->DTIMER = SDIO_DataInitStruct->DataTimeOut;
+
+  /* Set the SDIO DataLength value */
+  SDIOx->DLEN = SDIO_DataInitStruct->DataLength;
+
+/* SDIO DCTRL Configuration */  
+  /* Get the SDIO DCTRL value */
+  tmpreg = SDIOx->DCTRL;
+  
+  /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
+  tmpreg &= DCTRL_CLEAR_MASK;
+  
+  /* Set the SDIO data configuration parameters */
+  tmpreg |= (uint32_t)(SDIO_DataInitStruct->DataBlockSize |\
+                       SDIO_DataInitStruct->TransferDir   |\
+                       SDIO_DataInitStruct->TransferMode  |\
+                       SDIO_DataInitStruct->DPSM);
+
+  /* Write to SDIO DCTRL */
+  SDIOx->DCTRL = tmpreg;
+
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Returns number of remaining data bytes to be transferred.
+  * @param  SDIOx: Pointer to SDIO register base
+  * @retval Number of remaining data bytes to be transferred
+  */
+uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
+{
+  return (SDIOx->DCOUNT);
+}
+
+/**
+  * @brief  Get the FIFO data
+  * @param  hsdio: SDIO handle
+  * @retval Data received
+  */
+uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
+{
+  return (SDIOx->FIFO);
+}
+
+
+/**
+  * @brief  Sets one of the two options of inserting read wait interval.
+  * @param  SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
+  *          This parameter can be:
+  *            @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK
+  *            @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2
+  * @retval None
+  */
+HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
+  
+  *(__IO uint32_t *)DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
+  
+  return HAL_OK;  
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SDIO_Group3 Peripheral State functions 
+ *  @brief   Peripheral State functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================  
+    [..]
+    This subsection permit to get in runtime the status of the SDIO peripheral 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,941 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_sdmmc.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of SDMMC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_SDMMC_H
+#define __STM32F4xx_LL_SDMMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_Driver
+  * @{
+  */
+
+/** @addtogroup SDMMC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** 
+  * @brief  SDMMC Configuration Structure definition  
+  */
+typedef struct
+{
+  uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
+                                      This parameter can be a value of @ref SDIO_Clock_Edge                 */
+
+  uint32_t ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
+                                      enabled or disabled.
+                                      This parameter can be a value of @ref SDIO_Clock_Bypass               */
+
+  uint32_t ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
+                                      disabled when the bus is idle.
+                                      This parameter can be a value of @ref SDIO_Clock_Power_Save           */
+
+  uint32_t BusWide;              /*!< Specifies the SDIO bus width.
+                                      This parameter can be a value of @ref SDIO_Bus_Wide                   */
+
+  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
+                                      This parameter can be a value of @ref SDIO_Hardware_Flow_Control      */
+
+  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDIO controller.
+                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255 */  
+  
+}SDIO_InitTypeDef;
+  
+
+/** 
+  * @brief  SDIO Command Control structure 
+  */
+typedef struct                                                                                            
+{
+  uint32_t Argument;            /*!< Specifies the SDIO command argument which is sent
+                                     to a card as part of a command message. If a command
+                                     contains an argument, it must be loaded into this register
+                                     before writing the command to the command register.              */
+
+  uint32_t CmdIndex;            /*!< Specifies the SDIO command index. It must be Min_Data = 0 and 
+                                     Max_Data = 64                                                    */
+
+  uint32_t Response;            /*!< Specifies the SDIO response type.
+                                     This parameter can be a value of @ref SDIO_Response_Type         */
+
+  uint32_t WaitForInterrupt;    /*!< Specifies whether SDIO wait for interrupt request is 
+                                     enabled or disabled.
+                                     This parameter can be a value of @ref SDIO_Wait_Interrupt_State  */
+
+  uint32_t CPSM;                /*!< Specifies whether SDIO Command path state machine (CPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDIO_CPSM_State            */
+}SDIO_CmdInitTypeDef;
+
+
+/** 
+  * @brief  SDIO Data Control structure 
+  */
+typedef struct
+{
+  uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */
+
+  uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
+ 
+  uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
+                                     This parameter can be a value of @ref SDIO_Data_Block_Size    */
+ 
+  uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
+                                     is a read or write.
+                                     This parameter can be a value of @ref SDIO_Transfer_Direction */
+ 
+  uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
+                                     This parameter can be a value of @ref SDIO_Transfer_Type      */
+ 
+  uint32_t DPSM;                /*!< Specifies whether SDIO Data path state machine (DPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDIO_DPSM_State         */
+}SDIO_DataInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SDIO_Exported_Constants
+  * @{
+  */
+
+/** @defgroup SDIO_Clock_Edge 
+  * @{
+  */
+#define SDIO_CLOCK_EDGE_RISING               ((uint32_t)0x00000000)
+#define SDIO_CLOCK_EDGE_FALLING              ((uint32_t)0x00002000)
+
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
+                                  ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Clock_Bypass 
+  * @{
+  */
+#define SDIO_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000)
+#define SDIO_CLOCK_BYPASS_ENABLE              ((uint32_t)0x00000400)    
+
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
+                                      ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Clock_Power_Save 
+  * @{
+  */
+#define SDIO_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000)
+#define SDIO_CLOCK_POWER_SAVE_ENABLE          ((uint32_t)0x00000200) 
+
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
+                                        ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Bus_Wide 
+  * @{
+  */
+#define SDIO_BUS_WIDE_1B                      ((uint32_t)0x00000000)
+#define SDIO_BUS_WIDE_4B                      ((uint32_t)0x00000800)
+#define SDIO_BUS_WIDE_8B                      ((uint32_t)0x00001000)
+
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
+                                ((WIDE) == SDIO_BUS_WIDE_4B) || \
+                                ((WIDE) == SDIO_BUS_WIDE_8B))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Hardware_Flow_Control 
+  * @{
+  */
+#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000)
+#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE     ((uint32_t)0x00004000)
+
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
+                                                ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
+/**
+  * @}
+  */
+  
+/** @defgroup SDIO_Clock_Division
+  * @{
+  */
+#define IS_SDIO_CLKDIV(DIV)   ((DIV) <= 0xFF)
+/**
+  * @}
+  */  
+  
+/**
+  * @}
+  */ 
+    
+/** @defgroup SDIO_Command_Index
+  * @{
+  */
+#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Response_Type
+  * @{
+  */
+#define SDIO_RESPONSE_NO                    ((uint32_t)0x00000000)
+#define SDIO_RESPONSE_SHORT                 ((uint32_t)0x00000040)
+#define SDIO_RESPONSE_LONG                  ((uint32_t)0x000000C0)
+
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO)    || \
+                                    ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
+                                    ((RESPONSE) == SDIO_RESPONSE_LONG))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Wait_Interrupt_State
+  * @{
+  */
+#define SDIO_WAIT_NO                        ((uint32_t)0x00000000)
+#define SDIO_WAIT_IT                        ((uint32_t)0x00000100) 
+#define SDIO_WAIT_PEND                      ((uint32_t)0x00000200) 
+
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
+                            ((WAIT) == SDIO_WAIT_IT) || \
+                            ((WAIT) == SDIO_WAIT_PEND))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_CPSM_State
+  * @{
+  */
+#define SDIO_CPSM_DISABLE                   ((uint32_t)0x00000000)
+#define SDIO_CPSM_ENABLE                    ((uint32_t)0x00000400)
+
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
+                            ((CPSM) == SDIO_CPSM_ENABLE))
+/**
+  * @}
+  */  
+
+/** @defgroup SDIO_Response_Registers
+  * @{
+  */
+#define SDIO_RESP1                          ((uint32_t)0x00000000)
+#define SDIO_RESP2                          ((uint32_t)0x00000004)
+#define SDIO_RESP3                          ((uint32_t)0x00000008)
+#define SDIO_RESP4                          ((uint32_t)0x0000000C)
+
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
+                            ((RESP) == SDIO_RESP2) || \
+                            ((RESP) == SDIO_RESP3) || \
+                            ((RESP) == SDIO_RESP4))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Data_Length 
+  * @{
+  */
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Data_Block_Size 
+  * @{
+  */
+#define SDIO_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000)
+#define SDIO_DATABLOCK_SIZE_2B               ((uint32_t)0x00000010)
+#define SDIO_DATABLOCK_SIZE_4B               ((uint32_t)0x00000020)
+#define SDIO_DATABLOCK_SIZE_8B               ((uint32_t)0x00000030)
+#define SDIO_DATABLOCK_SIZE_16B              ((uint32_t)0x00000040)
+#define SDIO_DATABLOCK_SIZE_32B              ((uint32_t)0x00000050)
+#define SDIO_DATABLOCK_SIZE_64B              ((uint32_t)0x00000060)
+#define SDIO_DATABLOCK_SIZE_128B             ((uint32_t)0x00000070)
+#define SDIO_DATABLOCK_SIZE_256B             ((uint32_t)0x00000080)
+#define SDIO_DATABLOCK_SIZE_512B             ((uint32_t)0x00000090)
+#define SDIO_DATABLOCK_SIZE_1024B            ((uint32_t)0x000000A0)
+#define SDIO_DATABLOCK_SIZE_2048B            ((uint32_t)0x000000B0)
+#define SDIO_DATABLOCK_SIZE_4096B            ((uint32_t)0x000000C0)
+#define SDIO_DATABLOCK_SIZE_8192B            ((uint32_t)0x000000D0)
+#define SDIO_DATABLOCK_SIZE_16384B           ((uint32_t)0x000000E0)
+
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B)    || \
+                                  ((SIZE) == SDIO_DATABLOCK_SIZE_2B)    || \
+                                  ((SIZE) == SDIO_DATABLOCK_SIZE_4B)    || \
+                                  ((SIZE) == SDIO_DATABLOCK_SIZE_8B)    || \
+                                  ((SIZE) == SDIO_DATABLOCK_SIZE_16B)   || \
+                                  ((SIZE) == SDIO_DATABLOCK_SIZE_32B)   || \
+                                  ((SIZE) == SDIO_DATABLOCK_SIZE_64B)   || \
+                                  ((SIZE) == SDIO_DATABLOCK_SIZE_128B)  || \
+                                  ((SIZE) == SDIO_DATABLOCK_SIZE_256B)  || \
+                                  ((SIZE) == SDIO_DATABLOCK_SIZE_512B)  || \
+                                  ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
+                                  ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
+                                  ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
+                                  ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
+                                  ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) 
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Transfer_Direction 
+  * @{
+  */
+#define SDIO_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000)
+#define SDIO_TRANSFER_DIR_TO_SDIO             ((uint32_t)0x00000002)
+
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
+                                   ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Transfer_Type 
+  * @{
+  */
+#define SDIO_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000)
+#define SDIO_TRANSFER_MODE_STREAM            ((uint32_t)0x00000004)
+
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
+                                     ((MODE) == SDIO_TRANSFER_MODE_STREAM))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_DPSM_State 
+  * @{
+  */
+#define SDIO_DPSM_DISABLE                    ((uint32_t)0x00000000)
+#define SDIO_DPSM_ENABLE                     ((uint32_t)0x00000001)
+
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
+                            ((DPSM) == SDIO_DPSM_ENABLE))
+/**
+  * @}
+  */
+  
+/** @defgroup SDIO_Read_Wait_Mode 
+  * @{
+  */
+#define SDIO_READ_WAIT_MODE_CLK               ((uint32_t)0x00000000)
+#define SDIO_READ_WAIT_MODE_DATA2             ((uint32_t)0x00000001)
+
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
+                                     ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
+/**
+  * @}
+  */  
+
+/** @defgroup SDIO_Interrupt_sources
+  * @{
+  */
+#define SDIO_IT_CCRCFAIL                    ((uint32_t)0x00000001)
+#define SDIO_IT_DCRCFAIL                    ((uint32_t)0x00000002)
+#define SDIO_IT_CTIMEOUT                    ((uint32_t)0x00000004)
+#define SDIO_IT_DTIMEOUT                    ((uint32_t)0x00000008)
+#define SDIO_IT_TXUNDERR                    ((uint32_t)0x00000010)
+#define SDIO_IT_RXOVERR                     ((uint32_t)0x00000020)
+#define SDIO_IT_CMDREND                     ((uint32_t)0x00000040)
+#define SDIO_IT_CMDSENT                     ((uint32_t)0x00000080)
+#define SDIO_IT_DATAEND                     ((uint32_t)0x00000100)
+#define SDIO_IT_STBITERR                    ((uint32_t)0x00000200)
+#define SDIO_IT_DBCKEND                     ((uint32_t)0x00000400)
+#define SDIO_IT_CMDACT                      ((uint32_t)0x00000800)
+#define SDIO_IT_TXACT                       ((uint32_t)0x00001000)
+#define SDIO_IT_RXACT                       ((uint32_t)0x00002000)
+#define SDIO_IT_TXFIFOHE                    ((uint32_t)0x00004000)
+#define SDIO_IT_RXFIFOHF                    ((uint32_t)0x00008000)
+#define SDIO_IT_TXFIFOF                     ((uint32_t)0x00010000)
+#define SDIO_IT_RXFIFOF                     ((uint32_t)0x00020000)
+#define SDIO_IT_TXFIFOE                     ((uint32_t)0x00040000)
+#define SDIO_IT_RXFIFOE                     ((uint32_t)0x00080000)
+#define SDIO_IT_TXDAVL                      ((uint32_t)0x00100000)
+#define SDIO_IT_RXDAVL                      ((uint32_t)0x00200000)
+#define SDIO_IT_SDIOIT                      ((uint32_t)0x00400000)
+#define SDIO_IT_CEATAEND                    ((uint32_t)0x00800000)
+
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Flags 
+  * @{
+  */
+#define SDIO_FLAG_CCRCFAIL                  ((uint32_t)0x00000001)
+#define SDIO_FLAG_DCRCFAIL                  ((uint32_t)0x00000002)
+#define SDIO_FLAG_CTIMEOUT                  ((uint32_t)0x00000004)
+#define SDIO_FLAG_DTIMEOUT                  ((uint32_t)0x00000008)
+#define SDIO_FLAG_TXUNDERR                  ((uint32_t)0x00000010)
+#define SDIO_FLAG_RXOVERR                   ((uint32_t)0x00000020)
+#define SDIO_FLAG_CMDREND                   ((uint32_t)0x00000040)
+#define SDIO_FLAG_CMDSENT                   ((uint32_t)0x00000080)
+#define SDIO_FLAG_DATAEND                   ((uint32_t)0x00000100)
+#define SDIO_FLAG_STBITERR                  ((uint32_t)0x00000200)
+#define SDIO_FLAG_DBCKEND                   ((uint32_t)0x00000400)
+#define SDIO_FLAG_CMDACT                    ((uint32_t)0x00000800)
+#define SDIO_FLAG_TXACT                     ((uint32_t)0x00001000)
+#define SDIO_FLAG_RXACT                     ((uint32_t)0x00002000)
+#define SDIO_FLAG_TXFIFOHE                  ((uint32_t)0x00004000)
+#define SDIO_FLAG_RXFIFOHF                  ((uint32_t)0x00008000)
+#define SDIO_FLAG_TXFIFOF                   ((uint32_t)0x00010000)
+#define SDIO_FLAG_RXFIFOF                   ((uint32_t)0x00020000)
+#define SDIO_FLAG_TXFIFOE                   ((uint32_t)0x00040000)
+#define SDIO_FLAG_RXFIFOE                   ((uint32_t)0x00080000)
+#define SDIO_FLAG_TXDAVL                    ((uint32_t)0x00100000)
+#define SDIO_FLAG_RXDAVL                    ((uint32_t)0x00200000)
+#define SDIO_FLAG_SDIOIT                    ((uint32_t)0x00400000)
+#define SDIO_FLAG_CEATAEND                  ((uint32_t)0x00800000)
+
+#define IS_SDIO_FLAG(FLAG) (((FLAG)  == SDIO_FLAG_CCRCFAIL) || \
+                            ((FLAG)  == SDIO_FLAG_DCRCFAIL) || \
+                            ((FLAG)  == SDIO_FLAG_CTIMEOUT) || \
+                            ((FLAG)  == SDIO_FLAG_DTIMEOUT) || \
+                            ((FLAG)  == SDIO_FLAG_TXUNDERR) || \
+                            ((FLAG)  == SDIO_FLAG_RXOVERR)  || \
+                            ((FLAG)  == SDIO_FLAG_CMDREND)  || \
+                            ((FLAG)  == SDIO_FLAG_CMDSENT)  || \
+                            ((FLAG)  == SDIO_FLAG_DATAEND)  || \
+                            ((FLAG)  == SDIO_FLAG_STBITERR) || \
+                            ((FLAG)  == SDIO_FLAG_DBCKEND)  || \
+                            ((FLAG)  == SDIO_FLAG_CMDACT)   || \
+                            ((FLAG)  == SDIO_FLAG_TXACT)    || \
+                            ((FLAG)  == SDIO_FLAG_RXACT)    || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOHE) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOHF) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOF)  || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOF)  || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOE)  || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOE)  || \
+                            ((FLAG)  == SDIO_FLAG_TXDAVL)   || \
+                            ((FLAG)  == SDIO_FLAG_RXDAVL)   || \
+                            ((FLAG)  == SDIO_FLAG_SDIOIT)   || \
+                            ((FLAG)  == SDIO_FLAG_CEATAEND))
+
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
+
+#define IS_SDIO_GET_IT(IT) (((IT)  == SDIO_IT_CCRCFAIL) || \
+                            ((IT)  == SDIO_IT_DCRCFAIL) || \
+                            ((IT)  == SDIO_IT_CTIMEOUT) || \
+                            ((IT)  == SDIO_IT_DTIMEOUT) || \
+                            ((IT)  == SDIO_IT_TXUNDERR) || \
+                            ((IT)  == SDIO_IT_RXOVERR)  || \
+                            ((IT)  == SDIO_IT_CMDREND)  || \
+                            ((IT)  == SDIO_IT_CMDSENT)  || \
+                            ((IT)  == SDIO_IT_DATAEND)  || \
+                            ((IT)  == SDIO_IT_STBITERR) || \
+                            ((IT)  == SDIO_IT_DBCKEND)  || \
+                            ((IT)  == SDIO_IT_CMDACT)   || \
+                            ((IT)  == SDIO_IT_TXACT)    || \
+                            ((IT)  == SDIO_IT_RXACT)    || \
+                            ((IT)  == SDIO_IT_TXFIFOHE) || \
+                            ((IT)  == SDIO_IT_RXFIFOHF) || \
+                            ((IT)  == SDIO_IT_TXFIFOF)  || \
+                            ((IT)  == SDIO_IT_RXFIFOF)  || \
+                            ((IT)  == SDIO_IT_TXFIFOE)  || \
+                            ((IT)  == SDIO_IT_RXFIFOE)  || \
+                            ((IT)  == SDIO_IT_TXDAVL)   || \
+                            ((IT)  == SDIO_IT_RXDAVL)   || \
+                            ((IT)  == SDIO_IT_SDIOIT)   || \
+                            ((IT)  == SDIO_IT_CEATAEND))
+
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup SDIO_Instance_definition 
+  * @{
+  */ 
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+/* ------------ SDIO registers bit address in the alias region -------------- */
+#define SDIO_OFFSET               (SDIO_BASE - PERIPH_BASE)
+
+/* --- CLKCR Register ---*/
+/* Alias word address of CLKEN bit */
+#define CLKCR_OFFSET              (SDIO_OFFSET + 0x04)
+#define CLKEN_BitNumber           0x08
+#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
+
+/* --- CMD Register ---*/
+/* Alias word address of SDIOSUSPEND bit */
+#define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
+#define SDIOSUSPEND_BitNumber     0x0B
+#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
+
+/* Alias word address of ENCMDCOMPL bit */
+#define ENCMDCOMPL_BitNumber      0x0C
+#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
+
+/* Alias word address of NIEN bit */
+#define NIEN_BitNumber            0x0D
+#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
+
+/* Alias word address of ATACMD bit */
+#define ATACMD_BitNumber          0x0E
+#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
+
+/* --- DCTRL Register ---*/
+/* Alias word address of DMAEN bit */
+#define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
+#define DMAEN_BitNumber           0x03
+#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
+
+/* Alias word address of RWSTART bit */
+#define RWSTART_BitNumber         0x08
+#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
+
+/* Alias word address of RWSTOP bit */
+#define RWSTOP_BitNumber          0x09
+#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
+
+/* Alias word address of RWMOD bit */
+#define RWMOD_BitNumber           0x0A
+#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
+
+/* Alias word address of SDIOEN bit */
+#define SDIOEN_BitNumber          0x0B
+#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
+
+/* ---------------------- SDIO registers bit mask --------------------------- */
+/* --- CLKCR Register ---*/
+/* CLKCR register clear mask */
+#define CLKCR_CLEAR_MASK         ((uint32_t)0xFFFF8100) 
+
+/* --- PWRCTRL Register ---*/
+/* SDIO PWRCTRL Mask */
+#define PWR_PWRCTRL_MASK         ((uint32_t)0xFFFFFFFC)
+
+/* --- DCTRL Register ---*/
+/* SDIO DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK         ((uint32_t)0xFFFFFF08)
+
+/* --- CMD Register ---*/
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK           ((uint32_t)0xFFFFF800)
+
+/* SDIO RESP Registers Address */
+#define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))
+
+/* SD FLASH SDIO Interface */
+#define SDIO_FIFO_ADDRESS ((uint32_t)0x40012C80)
+
+/* SDIO Intialization Frequency (400KHz max) */
+#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
+
+/* SDIO Data Transfer Frequency (25MHz max) */
+#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
+
+/** @defgroup SDIO_Interrupt_Clock
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+ 
+/**
+  * @brief  Enable the SDIO device.
+  * @param  None   
+  * @retval None
+  */ 
+#define __SDIO_ENABLE()   (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
+
+/**
+  * @brief  Disable the SDIO device.
+  * @param  None  
+  * @retval None
+  */
+#define __SDIO_DISABLE()   (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
+
+/**
+  * @brief  Enable the SDIO DMA transfer.
+  * @param  None  
+  * @retval None
+  */ 
+#define __SDIO_DMA_ENABLE()   (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
+
+/**
+  * @brief  Disable the SDIO DMA transfer.
+  * @param  None   
+  * @retval None
+  */
+#define __SDIO_DMA_DISABLE()   (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
+ 
+/**
+  * @brief  Enable the SDIO device interrupt.
+  * @param  __INSTANCE__ : Pointer to SDIO register base  
+  * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                                   bus mode interrupt
+  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
+  * @retval None
+  */
+#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SDIO device interrupt.
+  * @param  __INSTANCE__ : Pointer to SDIO register base   
+  * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                                   bus mode interrupt
+  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
+  * @retval None
+  */
+#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified SDIO flag is set or not. 
+  * @param  __INSTANCE__ : Pointer to SDIO register base   
+  * @param  __FLAG__: specifies the flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
+  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
+  *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
+  *            @arg SDIO_FLAG_RXACT:    Data receive in progress
+  *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+  *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+  *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
+  *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
+  *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
+  *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
+  *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
+  *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
+  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
+  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+  * @retval The new state of SDIO_FLAG (SET or RESET).
+  */
+#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__)   (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
+
+
+/**
+  * @brief  Clears the SDIO's pending flags.
+  * @param  __INSTANCE__ : Pointer to SDIO register base  
+  * @param  __FLAG__: specifies the flag to clear.  
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
+  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
+  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+  * @retval None
+  */
+#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__)   ((__INSTANCE__)->ICR = (__FLAG__))
+
+/**
+  * @brief  Checks whether the specified SDIO interrupt has occurred or not.
+  * @param  __INSTANCE__ : Pointer to SDIO register base   
+  * @param  __INTERRUPT__: specifies the SDIO interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                                   bus mode interrupt
+  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+  * @retval The new state of SDIO_IT (SET or RESET).
+  */
+#define __SDIO_GET_IT  (__INSTANCE__, __INTERRUPT__)   (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief  Clears the SDIO's interrupt pending bits.
+  * @param  __INSTANCE__ : Pointer to SDIO register base 
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIO_DCOUNT, is zero) interrupt
+  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                                   bus mode interrupt
+  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
+  * @retval None
+  */
+#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->ICR = (__INTERRUPT__))
+
+/**
+  * @brief  Enable Start the SD I/O Read Wait operation.
+  * @param  None  
+  * @retval None
+  */  
+#define __SDIO_START_READWAIT_ENABLE()   (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
+
+/**
+  * @brief  Disable Start the SD I/O Read Wait operations.
+  * @param  None  
+  * @retval None
+  */  
+#define __SDIO_START_READWAIT_DISABLE()   (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
+
+/**
+  * @brief  Enable Start the SD I/O Read Wait operation.
+  * @param  None  
+  * @retval None
+  */  
+#define __SDIO_STOP_READWAIT_ENABLE()   (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
+
+/**
+  * @brief  Disable Stop the SD I/O Read Wait operations.
+  * @param  None  
+  * @retval None
+  */  
+#define __SDIO_STOP_READWAIT_DISABLE()   (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
+
+/**
+  * @brief  Enable the SD I/O Mode Operation.
+  * @param  None  
+  * @retval None
+  */  
+#define __SDIO_OPERATION_ENABLE()   (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
+
+/**
+  * @brief  Disable the SD I/O Mode Operation.
+  * @param  None  
+  * @retval None
+  */  
+#define __SDIO_OPERATION_DISABLE()   (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
+
+/**
+  * @brief  Enable the SD I/O Suspend command sending.
+  * @param  None  
+  * @retval None
+  */  
+#define __SDIO_SUSPEND_CMD_ENABLE()   (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
+
+/**
+  * @brief  Disable the SD I/O Suspend command sending.
+  * @param  None  
+  * @retval None
+  */  
+#define __SDIO_SUSPEND_CMD_DISABLE()   (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
+    
+/**
+  * @brief  Enable the command completion signal.
+  * @param  None  
+  * @retval None
+  */    
+#define __SDIO_CEATA_CMD_COMPLETION_ENABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
+
+/**
+  * @brief  Disable the command completion signal.
+  * @param  None  
+  * @retval None
+  */  
+#define __SDIO_CEATA_CMD_COMPLETION_DISABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
+
+/**
+  * @brief  Enable the CE-ATA interrupt.
+  * @param  None  
+  * @retval None
+  */    
+#define __SDIO_CEATA_ENABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
+
+/**
+  * @brief  Disable the CE-ATA interrupt.
+  * @param  None  
+  * @retval None
+  */  
+#define __SDIO_CEATA_DISABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
+
+/**
+  * @brief  Enable send CE-ATA command (CMD61).
+  * @param  None  
+  * @retval None
+  */  
+#define __SDIO_CEATA_SENDCMD_ENABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
+
+/**
+  * @brief  Disable send CE-ATA command (CMD61).
+  * @param  None  
+  * @retval None
+  */  
+#define __SDIO_CEATA_SENDCMD_DISABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
+  
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
+
+/* I/O operation functions  *****************************************************/
+/* Blocking mode: Polling */
+uint32_t          SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
+HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
+HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
+uint32_t          SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
+
+/* Command path state machine (CPSM) management functions */
+HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
+uint8_t           SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
+uint32_t          SDIO_GetResponse(uint32_t SDIO_RESP);
+
+/* Data path state machine (DPSM) management functions */
+HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+uint32_t          SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
+uint32_t          SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
+
+/* SDIO IO Cards mode management functions */
+HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_SDMMC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1685 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_usb.c
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   USB Low Layer HAL module driver.
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the USB Peripheral Controller:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
+  
+      (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
+
+      (#) The upper HAL HCD/PCD driver will call the righ routines for its internal processes.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_LL_USB_DRIVER
+  * @{
+  */
+
+#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
+
+/** @defgroup PCD_Private_Functions
+  * @{
+  */
+
+/** @defgroup LL_USB_Group1 Initialization/de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization/de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the USB Core
+  * @param  USBx: USB Instance
+  * @param  cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+  if (cfg.phy_itface == USB_OTG_ULPI_PHY)
+  {
+    
+    USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
+
+    /* Init The ULPI Interface */
+    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
+   
+    /* Select vbus source */
+    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
+    if(cfg.use_external_vbus == 1)
+    {
+      USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
+    }
+    /* Reset after a PHY select  */
+    USB_CoreReset(USBx); 
+  }
+  else /* FS interface (embedded Phy) */
+  {
+    
+    /* Select FS Embedded PHY */
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
+    
+    /* Reset after a PHY select and set Host mode */
+    USB_CoreReset(USBx);
+    
+    /* Deactivate the power down*/
+    USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
+  }
+ 
+  if(cfg.dma_enable == ENABLE)
+  {
+    USBx->GAHBCFG |= (USB_OTG_GAHBCFG_HBSTLEN_1 | USB_OTG_GAHBCFG_HBSTLEN_2);
+    USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
+  }  
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EnableGlobalInt
+  *         Enables the controller's Global Int in the AHB Config reg
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
+{
+  USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  USB_DisableGlobalInt
+  *         Disable the controller's Global Int in the AHB Config reg
+  * @param  USBx : Selected device
+  * @retval HAL status
+*/
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
+{
+  USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
+  return HAL_OK;
+}
+   
+/**
+  * @brief  USB_SetCurrentMode : Set functional mode
+  * @param  USBx : Selected device
+  * @param  mode :  current core mode
+  *          This parameter can be one of the these values:
+  *            @arg USB_OTG_DEVICE_MODE: Peripheral mode mode
+  *            @arg USB_OTG_HOST_MODE: Host mode
+  *            @arg USB_OTG_DRD_MODE: Dual Role Device mode  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)
+{
+  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 
+  
+  if ( mode == USB_OTG_HOST_MODE)
+  {
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 
+  }
+  else if ( mode == USB_OTG_DEVICE_MODE)
+  {
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 
+  }
+  HAL_Delay(50);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevInit : Initializes the USB_OTG controller registers 
+  *         for device mode
+  * @param  USBx : Selected device
+  * @param  cfg  : pointer to a USB_OTG_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+  uint32_t i = 0;
+
+  /*Activate VBUS Sensing B */
+  USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
+  
+  if (cfg.vbus_sensing_enable == 0)
+  {
+    USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
+  }
+   
+  /* Restart the Phy Clock */
+  USBx_PCGCCTL = 0;
+
+  /* Device mode configuration */
+  USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
+  
+  if(cfg.phy_itface  == USB_OTG_ULPI_PHY)
+  {
+    if(cfg.speed == USB_OTG_SPEED_HIGH)
+    {      
+      /* Set High speed phy */
+      USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);
+    }
+    else 
+    {
+      /* set High speed phy in Full speed mode */
+      USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);
+    }
+  }
+  else
+  {
+    /* Set Full speed phy */
+    USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);
+  }
+
+  /* Flush the FIFOs */
+  USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */
+  USB_FlushRxFifo(USBx);
+
+  
+  /* Clear all pending Device Interrupts */
+  USBx_DEVICE->DIEPMSK = 0;
+  USBx_DEVICE->DOEPMSK = 0;
+  USBx_DEVICE->DAINT = 0xFFFFFFFF;
+  USBx_DEVICE->DAINTMSK = 0;
+  
+  for (i = 0; i < cfg.dev_endpoints; i++)
+  {
+    if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+    {
+      USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK);
+    }
+    else
+    {
+      USBx_INEP(i)->DIEPCTL = 0;
+    }
+    
+    USBx_INEP(i)->DIEPTSIZ = 0;
+    USBx_INEP(i)->DIEPINT  = 0xFF;
+  }
+  
+  for (i = 0; i < cfg.dev_endpoints; i++)
+  {
+    if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+    {
+      USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK);
+    }
+    else
+    {
+      USBx_OUTEP(i)->DOEPCTL = 0;
+    }
+    
+    USBx_OUTEP(i)->DOEPTSIZ = 0;
+    USBx_OUTEP(i)->DOEPINT  = 0xFF;
+  }
+  
+  USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
+  
+  if (cfg.dma_enable == 1)
+  {
+    /*Set threshold parameters */
+    USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6);
+    USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN);
+    
+    i= USBx_DEVICE->DTHRCTL;
+  }
+  
+  /* Disable all interrupts. */
+  USBx->GINTMSK = 0;
+  
+  /* Clear any pending interrupts */
+  USBx->GINTSTS = 0xBFFFFFFF;
+
+  /* Enable the common interrupts */
+  if (cfg.dma_enable == DISABLE)
+  {
+    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 
+  }
+  
+  /* Enable interrupts matching to the Device mode ONLY */
+  USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\
+                    USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\
+                    USB_OTG_GINTMSK_OEPINT   | USB_OTG_GINTMSK_IISOIXFRM|\
+                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
+  
+  if(cfg.Sof_enable)
+  {
+    USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
+  }
+
+  if (cfg.vbus_sensing_enable == ENABLE)
+  {
+    USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 
+  }
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  USB_OTG_FlushTxFifo : Flush a Tx FIFO
+  * @param  USBx : Selected device
+  * @param  num : FIFO number
+  *         This parameter can be a value from 1 to 15
+            15 means Flush all Tx FIFOs
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
+{
+  uint32_t count = 0;
+ 
+  USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 5 )); 
+ 
+  do
+  {
+    if (++count > 200000)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  USB_FlushRxFifo : Flush Rx FIFO
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t count = 0;
+  
+  USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
+  
+  do
+  {
+    if (++count > 200000)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_SetDevSpeed :Initializes the DevSpd field of DCFG register 
+  *         depending the PHY type and the enumeration speed of the device.
+  * @param  USBx : Selected device
+  * @param  speed : device speed
+  *          This parameter can be one of the these values:
+  *            @arg USB_OTG_SPEED_HIGH: High speed mode
+  *            @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
+  *            @arg USB_OTG_SPEED_FULL: Full speed mode
+  *            @arg USB_OTG_SPEED_LOW: Low speed mode
+  * @retval  Hal status
+  */
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
+{
+  USBx_DEVICE->DCFG |= speed;
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_GetDevSpeed :Return the  Dev Speed 
+  * @param  USBx : Selected device
+  * @retval speed : device speed
+  *          This parameter can be one of the these values:
+  *            @arg USB_OTG_SPEED_HIGH: High speed mode
+  *            @arg USB_OTG_SPEED_FULL: Full speed mode
+  *            @arg USB_OTG_SPEED_LOW: Low speed mode
+  */
+uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint8_t speed = 0;
+  
+  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
+  {
+    speed = USB_OTG_SPEED_HIGH;
+  }
+  else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||
+           ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))
+  {
+    speed = USB_OTG_SPEED_FULL;
+  }
+  else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
+  {
+    speed = USB_OTG_SPEED_LOW;
+  }
+  
+  return speed;
+}
+
+/**
+  * @brief  Activate and configure an endpoint
+  * @param  USBx : Selected device
+  * @param  ep: pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  if (ep->is_in == 1)
+  {
+   USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
+   
+    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
+    {
+      USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
+        ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); 
+    } 
+
+  }
+  else
+  {
+     USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
+     
+    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
+    {
+      USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
+       (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));
+    } 
+  }
+  return HAL_OK;
+}
+/**
+  * @brief  Activate and configure a dedicated endpoint
+  * @param  USBx : Selected device
+  * @param  ep: pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  static __IO uint32_t debug = 0;
+  
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1)
+  {
+    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
+    {
+      USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
+        ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); 
+    } 
+    
+    
+    debug  |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
+        ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); 
+    
+   USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
+  }
+  else
+  {
+    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
+    {
+      USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
+        ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));
+      
+      debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE);
+      debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;
+      debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
+        ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); 
+    } 
+    
+     USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  De-activate and de-initialize an endpoint
+  * @param  USBx : Selected device
+  * @param  ep: pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1)
+  {
+   USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
+   USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));   
+   USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;   
+  }
+  else
+  {
+
+     USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
+     USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));     
+     USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;      
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-activate and de-initialize a dedicated endpoint
+  * @param  USBx : Selected device
+  * @param  ep: pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1)
+  {
+   USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
+   USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
+  }
+  else
+  {
+     USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; 
+     USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EPStartXfer : setup and starts a transfer over an EP
+  * @param  USBx : Selected device
+  * @param  ep: pointer to endpoint structure
+  * @param  dma: USB dma enabled or disabled 
+  *          This parameter can be one of the these values:
+  *           0 : DMA feature not used 
+  *           1 : DMA feature used  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
+{
+  uint16_t pktcnt = 0;
+  
+  /* IN endpoint */
+  if (ep->is_in == 1)
+  {
+    /* Zero Length Packet? */
+    if (ep->xfer_len == 0)
+    {
+      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
+      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
+      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 
+    }
+    else
+    {
+      /* Program the transfer size and packet count
+      * as follows: xfersize = N * maxpacket +
+      * short_packet pktcnt = N + (short_packet
+      * exist ? 1 : 0)
+      */
+      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
+      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ;
+      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 
+      
+      if (ep->type == EP_TYPE_ISOC)
+      {
+        USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); 
+        USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); 
+      }       
+    }
+
+    if (dma == 1)
+    {
+      USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
+    }
+    else
+    {
+      if (ep->type != EP_TYPE_ISOC)
+      {
+        /* Enable the Tx FIFO Empty Interrupt for this EP */
+        if (ep->xfer_len > 0)
+        {
+          USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num;
+        }
+      }
+    }
+
+    if (ep->type == EP_TYPE_ISOC)
+    {
+      if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
+      {
+        USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+      }
+      else
+      {
+        USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+      }
+    } 
+    
+    /* EP enable, IN data in FIFO */
+    USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+    
+    if (ep->type == EP_TYPE_ISOC)
+    {
+      USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma);   
+    }    
+  }
+  else /* OUT endpoint */
+  {
+    /* Program the transfer size and packet count as follows:
+    * pktcnt = N
+    * xfersize = N * maxpacket
+    */  
+    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 
+    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 
+      
+    if (ep->xfer_len == 0)
+    {
+      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
+      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;      
+    }
+    else
+    {
+      pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket; 
+      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); ;
+      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); 
+    }
+
+    if (dma == 1)
+    {
+      USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;
+    }
+    
+    if (ep->type == EP_TYPE_ISOC)
+    {
+      if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
+      {
+        USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
+      }
+      else
+      {
+        USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
+      }
+    }
+    /* EP enable */
+    USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EP0StartXfer : setup and starts a transfer over the EP  0
+  * @param  USBx : Selected device
+  * @param  ep: pointer to endpoint structure
+  * @param  dma: USB dma enabled or disabled 
+  *          This parameter can be one of the these values:
+  *           0 : DMA feature not used 
+  *           1 : DMA feature used  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
+{
+  /* IN endpoint */
+  if (ep->is_in == 1)
+  {
+    /* Zero Length Packet? */
+    if (ep->xfer_len == 0)
+    {
+      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
+      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
+      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 
+    }
+    else
+    {
+      /* Program the transfer size and packet count
+      * as follows: xfersize = N * maxpacket +
+      * short_packet pktcnt = N + (short_packet
+      * exist ? 1 : 0)
+      */
+      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
+      
+      if(ep->xfer_len > ep->maxpacket)
+      {
+        ep->xfer_len = ep->maxpacket;
+      }
+      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
+      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 
+    
+    }
+    
+    if (dma == 1)
+    {
+      USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
+    }
+    else
+    {
+      /* Enable the Tx FIFO Empty Interrupt for this EP */
+      if (ep->xfer_len > 0)
+      {
+        USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num);
+      }
+    }
+    
+    /* EP enable, IN data in FIFO */
+    USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);   
+  }
+  else /* OUT endpoint */
+  {
+    /* Program the transfer size and packet count as follows:
+    * pktcnt = N
+    * xfersize = N * maxpacket
+    */
+    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 
+    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 
+      
+    if (ep->xfer_len > 0)
+    {
+      ep->xfer_len = ep->maxpacket;
+    }
+    
+    USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));
+    USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); 
+    
+
+    if (dma == 1)
+    {
+      USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+    }
+    
+    /* EP enable */
+    USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);    
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated 
+  *         with the EP/channel
+  * @param  USBx : Selected device           
+  * @param  src :  pointer to source buffer
+  * @param  ch_ep_num : endpoint or host channel number
+  * @param  len : Number of bytes to write
+  * @param  dma: USB dma enabled or disabled 
+  *          This parameter can be one of the these values:
+  *           0 : DMA feature not used 
+  *           1 : DMA feature used  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
+{
+  uint32_t count32b= 0 , i= 0;
+  
+  if (dma == 0)
+  {
+    count32b =  (len + 3) / 4;
+    for (i = 0; i < count32b; i++, src += 4)
+    {
+      USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src);
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_ReadPacket : read a packet from the Tx FIFO associated 
+  *         with the EP/channel
+  * @param  USBx : Selected device  
+  * @param  src : source pointer
+  * @param  ch_ep_num : endpoint or host channel number
+  * @param  len : Noumber of bytes to read
+  * @param  dma: USB dma enabled or disabled 
+  *          This parameter can be one of the these values:
+  *           0 : DMA feature not used 
+  *           1 : DMA feature used  
+  * @retval pointer to desctination buffer
+  */
+void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
+{
+  uint32_t i=0;
+  uint32_t count32b = (len + 3) / 4;
+  
+  for ( i = 0; i < count32b; i++, dest += 4 )
+  {
+    *(__packed uint32_t *)dest = USBx_DFIFO(0);
+    
+  }
+  return ((void *)dest);
+}
+
+/**
+  * @brief  USB_EPSetStall : set a stall condition over an EP
+  * @param  USBx : Selected device
+  * @param  ep: pointer to endpoint structure   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
+{
+  if (ep->is_in == 1)
+  {
+    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0)
+    {
+      USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); 
+    } 
+    USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
+  }
+  else
+  {
+    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0)
+    {
+      USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); 
+    } 
+    USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
+  }
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  USB_EPClearStall : Clear a stall condition over an EP
+  * @param  USBx : Selected device
+  * @param  ep: pointer to endpoint structure   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  if (ep->is_in == 1)
+  {
+    USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+    if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
+    {
+       USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+    }    
+  }
+  else
+  {
+    USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
+    if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
+    {
+      USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+    }    
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_StopDevice : Stop the usb device mode
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t i;
+  
+  /* Clear Pending interrupt */
+  for (i = 0; i < 15 ; i++)
+  {
+    USBx_INEP(i)->DIEPINT  = 0xFF;
+    USBx_OUTEP(i)->DOEPINT  = 0xFF;
+  }
+  USBx_DEVICE->DAINT = 0xFFFFFFFF;
+  
+  /* Clear interrupt masks */
+  USBx_DEVICE->DIEPMSK  = 0;
+  USBx_DEVICE->DOEPMSK  = 0;
+  USBx_DEVICE->DAINTMSK = 0;
+  
+  /* Flush the FIFO */
+  USB_FlushRxFifo(USBx);
+  USB_FlushTxFifo(USBx ,  0x10 );  
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_SetDevAddress : Stop the usb device mode
+  * @param  USBx : Selected device
+  * @param  address : new device address to be assigned
+  *          This parameter can be a value from 0 to 255
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)
+{
+  USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
+  USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ;
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
+{
+  USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;
+  HAL_Delay(3);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
+{
+  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ;
+  HAL_Delay(3);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  USB_ReadInterrupts: return the global USB interrupt status
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+uint32_t  USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t v = 0;
+  
+  v = USBx->GINTSTS;
+  v &= USBx->GINTMSK;
+  return v;  
+}
+
+/**
+  * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t v;
+  v  = USBx_DEVICE->DAINT;
+  v &= USBx_DEVICE->DAINTMSK;
+  return ((v & 0xffff0000) >> 16);
+}
+
+/**
+  * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t v;
+  v  = USBx_DEVICE->DAINT;
+  v &= USBx_DEVICE->DAINTMSK;
+  return ((v & 0xFFFF));
+}
+
+/**
+  * @brief  Returns Device OUT EP Interrupt register
+  * @param  USBx : Selected device
+  * @param  epnum : endpoint number
+  *          This parameter can be a value from 0 to 15
+  * @retval Device OUT EP Interrupt register
+  */
+uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
+{
+  uint32_t v;
+  v  = USBx_OUTEP(epnum)->DOEPINT;
+  v &= USBx_DEVICE->DOEPMSK;
+  return v;
+}
+
+/**
+  * @brief  Returns Device IN EP Interrupt register
+  * @param  USBx : Selected device
+  * @param  epnum : endpoint number
+  *          This parameter can be a value from 0 to 15
+  * @retval Device IN EP Interrupt register
+  */
+uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
+{
+  uint32_t v, msk, emp;
+  
+  msk = USBx_DEVICE->DIEPMSK;
+  emp = USBx_DEVICE->DIEPEMPMSK;
+  msk |= ((emp >> epnum) & 0x1) << 7;
+  v = USBx_INEP(epnum)->DIEPINT & msk;
+  return v;
+}
+
+/**
+  * @brief  USB_ClearInterrupts: clear a USB interrupt
+  * @param  USBx : Selected device
+  * @param  interrupt : interrupt flag
+  * @retval None
+  */
+void  USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
+{
+  USBx->GINTSTS |= interrupt; 
+}
+
+/**
+  * @brief  Returns USB core mode
+  * @param  USBx : Selected device
+  * @retval return core mode : Host or Device
+  *          This parameter can be one of the these values:
+  *           0 : Host 
+  *           1 : Device
+  */
+uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
+{
+  return ((USBx->GINTSTS ) & 0x1);
+}
+
+
+/**
+  * @brief  Activate EP0 for Setup transactions
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
+{
+  /* Set the MPS of the IN EP based on the enumeration speed */
+  USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
+  
+  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
+  {
+    USBx_INEP(0)->DIEPCTL |= 3;
+  }
+  USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Prepare the EP0 to start the first control setup
+  * @param  USBx : Selected device
+  * @param  dma: USB dma enabled or disabled 
+  *          This parameter can be one of the these values:
+  *           0 : DMA feature not used 
+  *           1 : DMA feature used  
+  * @param  psetup : pointer to setup packet
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
+{
+  USBx_OUTEP(0)->DOEPTSIZ = 0;
+  USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
+  USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8);
+  USBx_OUTEP(0)->DOEPTSIZ |=  USB_OTG_DOEPTSIZ_STUPCNT;  
+  
+  if (dma == 1)
+  {
+    USBx_OUTEP(0)->DOEPDMA = (uint32_t)psetup;
+    /* EP enable */
+    USBx_OUTEP(0)->DOEPCTL = 0x80008000;
+  }
+  
+  return HAL_OK;  
+}
+
+
+/**
+  * @brief  Reset the USB Core (needed after USB clock settings change)
+  * @param  USBx : Selected device
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t count = 0;
+
+  /* Wait for AHB master IDLE state. */
+  do
+  {
+    if (++count > 200000)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);
+  
+  /* Core Soft Reset */
+  count = 0;
+  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
+
+  do
+  {
+    if (++count > 200000)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  USB_HostInit : Initializes the USB OTG controller registers 
+  *         for Host mode 
+  * @param  USBx : Selected device
+  * @param  cfg  : pointer to a USB_OTG_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+  uint32_t i;
+  
+  /* Restart the Phy Clock */
+  USBx_PCGCCTL = 0;
+  
+  /* no VBUS sensing*/
+  USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSASEN);
+  USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSBSEN);
+  USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
+  
+  /* Disable the FS/LS support mode only */
+  if((cfg.speed == USB_OTG_SPEED_FULL)&&
+     (USBx != USB_OTG_FS))
+  {
+    USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; 
+  }
+  else
+  {
+    USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);  
+  }
+
+  /* Make sure the FIFOs are flushed. */
+  USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */
+  USB_FlushRxFifo(USBx);
+
+  /* Clear all pending HC Interrupts */
+  for (i = 0; i < cfg.Host_channels; i++)
+  {
+    USBx_HC(i)->HCINT = 0xFFFFFFFF;
+    USBx_HC(i)->HCINTMSK = 0;
+  }
+  
+  /* Enable VBUS driving */
+  USB_DriveVbus(USBx, 1);
+  
+  HAL_Delay(200);
+  
+  /* Disable all interrupts. */
+  USBx->GINTMSK = 0;
+  
+  /* Clear any pending interrupts */
+  USBx->GINTSTS = 0xFFFFFFFF;
+
+  
+  if(USBx == USB_OTG_FS)
+  {
+    /* set Rx FIFO size */
+    USBx->GRXFSIZ  = (uint32_t )0x80; 
+    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);
+    USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);
+
+  }
+
+  else
+  {
+    /* set Rx FIFO size */
+    USBx->GRXFSIZ  = (uint32_t )0x200; 
+    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100 << 16)& USB_OTG_NPTXFD) | 0x200);
+    USBx->HPTXFSIZ = (uint32_t )(((0xE0 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300);
+  }
+  
+  /* Enable the common interrupts */
+  if (cfg.dma_enable == DISABLE)
+  {
+    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 
+  }
+  
+  /* Enable interrupts matching to the Host mode ONLY */
+  USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM            | USB_OTG_GINTMSK_HCIM |\
+                    USB_OTG_GINTMSK_SOFM             |USB_OTG_GINTSTS_DISCINT|\
+                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM  | USB_OTG_GINTMSK_WUIM);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the 
+  *         HCFG register on the PHY type and set the right frame interval
+  * @param  USBx : Selected device
+  * @param  freq : clock frequency
+  *          This parameter can be one of the these values:
+  *           HCFG_48_MHZ : Full Speed 48 MHz Clock 
+  *           HCFG_6_MHZ : Low Speed 6 MHz Clock 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
+{
+  USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
+  USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);
+  
+  if (freq ==  HCFG_48_MHZ)
+  {
+    USBx_HOST->HFIR = (uint32_t)48000;
+  }
+  else if (freq ==  HCFG_6_MHZ)
+  {
+    USBx_HOST->HFIR = (uint32_t)6000;
+  } 
+  return HAL_OK;  
+}
+
+/**
+* @brief  USB_OTG_ResetPort : Reset Host Port
+  * @param  USBx : Selected device
+  * @retval HAL status
+  * @note : (1)The application must wait at least 10 ms
+  *   before clearing the reset bit.
+  */
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
+{
+  __IO uint32_t hprt0;
+  
+  hprt0 = USBx_HPRT0;
+  
+  hprt0 &= ~(USB_OTG_HPRT_PENA    | USB_OTG_HPRT_PCDET |\
+    USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+  
+  USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);  
+  HAL_Delay (10);                                /* See Note #1 */
+  USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); 
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DriveVbus : activate or de-activate vbus
+  * @param  state : VBUS state
+  *          This parameter can be one of the these values:
+  *           0 : VBUS Active 
+  *           1 : VBUS Inactive
+  * @retval HAL status
+*/
+HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
+{
+  __IO uint32_t hprt0;
+
+  hprt0 = USBx_HPRT0;
+  hprt0 &= ~(USB_OTG_HPRT_PENA    | USB_OTG_HPRT_PCDET |\
+                         USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+  
+  if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))
+  {
+    USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); 
+  }
+  if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 ))
+  {
+    USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); 
+  }
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Return Host Core speed
+  * @param  USBx : Selected device
+  * @retval speed : Host speed
+  *          This parameter can be one of the these values:
+  *            @arg USB_OTG_SPEED_HIGH: High speed mode
+  *            @arg USB_OTG_SPEED_FULL: Full speed mode
+  *            @arg USB_OTG_SPEED_LOW: Low speed mode
+  */
+uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
+{
+  __IO uint32_t hprt0;
+  
+  hprt0 = USBx_HPRT0;
+  return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
+}
+
+/**
+  * @brief  Return Host Current Frame number
+  * @param  USBx : Selected device
+  * @retval current frame number
+*/
+uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
+{
+  return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
+}
+
+/**
+  * @brief  Initialize a host channel
+  * @param  USBx : Selected device
+  * @param  ch_num : Channel number
+  *         This parameter can be a value from 1 to 15
+  * @param  epnum : Endpoint number
+  *          This parameter can be a value from 1 to 15
+  * @param  dev_address : Current device address
+  *          This parameter can be a value from 0 to 255
+  * @param  speed : Current device speed
+  *          This parameter can be one of the these values:
+  *            @arg USB_OTG_SPEED_HIGH: High speed mode
+  *            @arg USB_OTG_SPEED_FULL: Full speed mode
+  *            @arg USB_OTG_SPEED_LOW: Low speed mode
+  * @param  ep_type : Endpoint Type
+  *          This parameter can be one of the these values:
+  *            @arg EP_TYPE_CTRL: Control type
+  *            @arg EP_TYPE_ISOC: Isochrounous type
+  *            @arg EP_TYPE_BULK: Bulk type
+  *            @arg EP_TYPE_INTR: Interrupt type
+  * @param  mps : Max Packet Size
+  *          This parameter can be a value from 0 to32K
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,  
+                              uint8_t ch_num,
+                              uint8_t epnum,
+                              uint8_t dev_address,
+                              uint8_t speed,
+                              uint8_t ep_type,
+                              uint16_t mps)
+{
+    
+  /* Clear old interrupt conditions for this host channel. */
+  USBx_HC(ch_num)->HCINT = 0xFFFFFFFF;
+  
+  /* Enable channel interrupts required for this transfer. */
+  switch (ep_type) 
+  {
+  case EP_TYPE_CTRL:
+  case EP_TYPE_BULK:
+    
+    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
+                                USB_OTG_HCINTMSK_STALLM |\
+                                USB_OTG_HCINTMSK_TXERRM |\
+                                USB_OTG_HCINTMSK_DTERRM |\
+                                USB_OTG_HCINTMSK_AHBERR |\
+                                USB_OTG_HCINTMSK_NAKM ;
+ 
+    if (epnum & 0x80) 
+    {
+      USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+    } 
+    else 
+    {
+      if(USBx != USB_OTG_FS)
+      {
+        USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
+      }
+    }
+    break;
+  case EP_TYPE_INTR:
+    
+    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
+                                USB_OTG_HCINTMSK_STALLM |\
+                                USB_OTG_HCINTMSK_TXERRM |\
+                                USB_OTG_HCINTMSK_DTERRM |\
+                                USB_OTG_HCINTMSK_NAKM   |\
+                                USB_OTG_HCINTMSK_AHBERR |\
+                                USB_OTG_HCINTMSK_FRMORM ;    
+    
+    if (epnum & 0x80) 
+    {
+      USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+    }
+    
+    break;
+  case EP_TYPE_ISOC:
+    
+    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
+                                USB_OTG_HCINTMSK_ACKM   |\
+                                USB_OTG_HCINTMSK_AHBERR |\
+                                USB_OTG_HCINTMSK_FRMORM ;   
+    
+    if (epnum & 0x80) 
+    {
+      USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);      
+    }
+    break;
+  }
+  
+  /* Enable the top level host channel interrupt. */
+  USBx_HOST->HAINTMSK |= (1 << ch_num);
+  
+  /* Make sure host channel interrupts are enabled. */
+  USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
+  
+  /* Program the HCCHAR register */
+  USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD)  |\
+                             (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\
+                             ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\
+                             (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\
+                             ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\
+                             (mps & USB_OTG_HCCHAR_MPSIZ));
+    
+  if (ep_type == EP_TYPE_INTR)
+  {
+    USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
+  }
+
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Start a transfer over a host channel
+  * @param  USBx : Selected device
+  * @param  hc : pointer to host channel structure
+  * @param  dma: USB dma enabled or disabled 
+  *          This parameter can be one of the these values:
+  *           0 : DMA feature not used 
+  *           1 : DMA feature used  
+  * @retval HAL state
+  */
+#if defined   (__CC_ARM) /*!< ARM Compiler */
+#pragma O0
+#elif defined (__GNUC__) /*!< GNU Compiler */
+#pragma GCC optimize ("O0")
+#elif defined  (__TASKING__) /*!< TASKING Compiler */ 
+#pragma optimize=0                          
+#endif /* __CC_ARM */
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
+{
+  uint8_t  is_oddframe = 0; 
+  uint16_t len_words = 0;   
+  uint16_t num_packets = 0;
+  uint16_t max_hc_pkt_count = 256;
+  
+  if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))
+  {
+    if((dma == 0) && (hc->do_ping == 1))
+    {
+      USB_DoPing(USBx, hc->ch_num);
+      return HAL_OK;
+    }
+  }
+  
+  /* Compute the expected number of packets associated to the transfer */
+  if (hc->xfer_len > 0)
+  {
+    num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;
+    
+    if (num_packets > max_hc_pkt_count)
+    {
+      num_packets = max_hc_pkt_count;
+      hc->xfer_len = num_packets * hc->max_packet;
+    }
+  }
+  else
+  {
+    num_packets = 1;
+  }
+  if (hc->ep_is_in)
+  {
+    hc->xfer_len = num_packets * hc->max_packet;
+  }
+  
+  
+  
+  /* Initialize the HCTSIZn register */
+  USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
+                                ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
+                                (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);
+  
+  if (dma)
+  {
+    /* xfer_buff MUST be 32-bits aligned */
+    USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
+  }
+
+  is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;
+  USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
+  USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);
+  
+  /* Set host channel enable */
+  USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
+  USBx_HC(hc->ch_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+
+  if (dma == 0) /* Slave mode */
+  {  
+    if((hc->ep_is_in == 0) && (hc->xfer_len > 0))
+    {
+      switch(hc->ep_type) 
+      {
+        /* Non periodic transfer */
+      case EP_TYPE_CTRL:
+      case EP_TYPE_BULK:
+        
+        len_words = (hc->xfer_len + 3) / 4;
+        
+        /* check if there is enough space in FIFO space */
+        if(len_words > (USBx->HNPTXSTS & 0xFFFF))
+        {
+          /* need to process data in nptxfempty interrupt */
+          USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
+        }
+        break;
+        /* Periodic transfer */
+      case EP_TYPE_INTR:
+      case EP_TYPE_ISOC:
+        len_words = (hc->xfer_len + 3) / 4;
+        /* check if there is enough space in FIFO space */
+        if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */
+        {
+          /* need to process data in ptxfempty interrupt */
+          USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;          
+        }
+        break;
+        
+      default:
+        break;
+      }
+      
+      /* Write packet into the Tx FIFO. */
+      USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);
+    }
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief Read all host channel interrupts status
+  * @param  USBx : Selected device
+  * @retval HAL state
+  */
+uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
+{
+  return ((USBx_HOST->HAINT) & 0xFFFF);
+}
+
+/**
+  * @brief  Halt a host channel
+  * @param  USBx : Selected device
+  * @param  hc_num : Host Channel number
+  *         This parameter can be a value from 1 to 15
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
+{
+  uint32_t count = 0;
+  
+  /* Check for space in the request queue to issue the halt. */
+  if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18)))
+  {
+    USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+    
+    if ((USBx->HNPTXSTS & 0xFFFF) == 0)
+    {
+      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;  
+      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
+      do 
+      {
+        if (++count > 1000) 
+        {
+          break;
+        }
+      } 
+      while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);     
+    }
+    else
+    {
+      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 
+    }
+  }
+  else
+  {
+    USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+    
+    if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0)
+    {
+      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;  
+      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
+      do 
+      {
+        if (++count > 1000) 
+        {
+          break;
+        }
+      } 
+      while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);     
+    }
+    else
+    {
+       USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 
+    }
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initiate Do Ping protocol
+  * @param  USBx : Selected device
+  * @param  hc_num : Host Channel number
+  *         This parameter can be a value from 1 to 15
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
+{
+  uint8_t  num_packets = 1;
+
+  USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
+                                USB_OTG_HCTSIZ_DOPING;
+  
+  /* Set host channel enable */
+  USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS;
+  USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Stop Host Core
+  * @param  USBx : Selected device
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint8_t i;
+  uint32_t count = 0;
+  uint32_t value;
+  
+  USB_DisableGlobalInt(USBx);
+  
+    /* Flush FIFO */
+  USB_FlushTxFifo(USBx, 0x10);
+  USB_FlushRxFifo(USBx);
+  
+  /* Flush out any leftover queued requests. */
+  for (i = 0; i <= 15; i++)
+  {   
+
+    value = USBx_HC(i)->HCCHAR ;
+    value |=  USB_OTG_HCCHAR_CHDIS;
+    value &= ~USB_OTG_HCCHAR_CHENA;  
+    value &= ~USB_OTG_HCCHAR_EPDIR;
+    USBx_HC(i)->HCCHAR = value;
+  }
+  
+  /* Halt all channels to put them into a known state. */  
+  for (i = 0; i <= 15; i++)
+  {   
+
+    value = USBx_HC(i)->HCCHAR ;
+    
+    value |= USB_OTG_HCCHAR_CHDIS;
+    value |= USB_OTG_HCCHAR_CHENA;  
+    value &= ~USB_OTG_HCCHAR_EPDIR;
+    
+    USBx_HC(i)->HCCHAR = value;
+    do 
+    {
+      if (++count > 1000) 
+      {
+        break;
+      }
+    } 
+    while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+  }
+
+  /* Clear any pending Host interrups */  
+  USBx_HOST->HAINT = 0xFFFFFFFF;
+  USBx->GINTSTS = 0xFFFFFFFF;
+  USB_EnableGlobalInt(USBx);
+  return HAL_OK;  
+}
+/**
+  * @}
+  */
+
+#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_usb.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,460 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_usb.h
+  * @author  MCD Application Team
+  * @version V1.1.0RC2
+  * @date    14-May-2014
+  * @brief   Header file of USB Core HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_USB_H
+#define __STM32F4xx_LL_USB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL
+  * @{
+  */
+
+/** @addtogroup USB_Core
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** 
+  * @brief  USB Mode definition  
+  */  
+typedef enum 
+{
+   USB_OTG_DEVICE_MODE  = 0,
+   USB_OTG_HOST_MODE    = 1,
+   USB_OTG_DRD_MODE     = 2
+   
+}USB_OTG_ModeTypeDef;
+
+/** 
+  * @brief  URB States definition  
+  */ 
+typedef enum {
+  URB_IDLE = 0,
+  URB_DONE,
+  URB_NOTREADY,
+  URB_NYET,
+  URB_ERROR,
+  URB_STALL
+    
+}USB_OTG_URBStateTypeDef;
+
+/** 
+  * @brief  Host channel States  definition  
+  */ 
+typedef enum {
+  HC_IDLE = 0,
+  HC_XFRC,
+  HC_HALTED,
+  HC_NAK,
+  HC_NYET,
+  HC_STALL,
+  HC_XACTERR,  
+  HC_BBLERR,   
+  HC_DATATGLERR
+    
+}USB_OTG_HCStateTypeDef;
+
+/** 
+  * @brief  PCD Initialization Structure definition  
+  */
+typedef struct
+{
+  uint32_t dev_endpoints;        /*!< Device Endpoints number.
+                                      This parameter depends on the used USB core.   
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */    
+  
+  uint32_t Host_channels;        /*!< Host Channels number.
+                                      This parameter Depends on the used USB core.   
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */       
+
+  uint32_t speed;                /*!< USB Core speed.
+                                      This parameter can be any value of @ref USB_Core_Speed_                */        
+                               
+  uint32_t dma_enable;           /*!< Enable or disable of the USB embedded DMA.                             */            
+
+  uint32_t ep0_mps;              /*!< Set the Endpoint 0 Max Packet size. 
+                                      This parameter can be any value of @ref USB_EP0_MPS_                   */              
+                       
+  uint32_t phy_itface;           /*!< Select the used PHY interface.
+                                      This parameter can be any value of @ref USB_Core_PHY_                  */ 
+                                
+  uint32_t Sof_enable;           /*!< Enable or disable the output of the SOF signal.                        */     
+                               
+  uint32_t low_power_enable;     /*!< Enable or disable the low power mode.                                  */     
+                          
+  uint32_t vbus_sensing_enable;  /*!< Enable or disable the VBUS Sensing feature.                            */ 
+
+  uint32_t use_dedicated_ep1;    /*!< Enable or disable the use of the dedicated EP1 interrupt.              */      
+  
+  uint32_t use_external_vbus;    /*!< Enable or disable the use of the external VBUS.                        */   
+  
+}USB_OTG_CfgTypeDef;
+
+typedef struct
+{
+  uint8_t   num;            /*!< Endpoint number
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 15    */ 
+                                
+  uint8_t   is_in;          /*!< Endpoint direction
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */ 
+  
+  uint8_t   is_stall;       /*!< Endpoint stall condition
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */ 
+  
+  uint8_t   type;           /*!< Endpoint type
+                                 This parameter can be any value of @ref USB_EP_Type_                     */ 
+                                
+  uint8_t   data_pid_start; /*!< Initial data PID
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
+                                
+  uint8_t   even_odd_frame; /*!< IFrame parity
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+                                
+  uint16_t  tx_fifo_num;    /*!< Transmission FIFO number
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
+                                
+  uint32_t  maxpacket;      /*!< Endpoint Max packet size
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+  uint8_t   *xfer_buff;     /*!< Pointer to transfer buffer                                               */
+                                
+  uint32_t  dma_addr;       /*!< 32 bits aligned transfer buffer address                                  */
+  
+  uint32_t  xfer_len;       /*!< Current transfer length                                                  */
+  
+  uint32_t  xfer_count;     /*!< Partial transfer length in case of multi packet transfer                 */
+
+}USB_OTG_EPTypeDef;
+
+typedef struct
+{
+  uint8_t   dev_addr ;     /*!< USB device address.
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 255    */ 
+
+  uint8_t   ch_num;        /*!< Host channel number.
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */ 
+                                
+  uint8_t   ep_num;        /*!< Endpoint number.
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */ 
+                                
+  uint8_t   ep_is_in;      /*!< Endpoint direction
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */ 
+                                
+  uint8_t   speed;         /*!< USB Host speed.
+                                This parameter can be any value of @ref USB_Core_Speed_                    */
+                                
+  uint8_t   do_ping;       /*!< Enable or disable the use of the PING protocol for HS mode.                */
+  
+  uint8_t   process_ping;  /*!< Execute the PING protocol for HS mode.                                     */
+
+  uint8_t   ep_type;       /*!< Endpoint Type.
+                                This parameter can be any value of @ref USB_EP_Type_                       */
+                                
+  uint16_t  max_packet;    /*!< Endpoint Max packet size.
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */
+                                
+  uint8_t   data_pid;      /*!< Initial data PID.
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+                                
+  uint8_t   *xfer_buff;    /*!< Pointer to transfer buffer.                                                */
+  
+  uint32_t  xfer_len;      /*!< Current transfer length.                                                   */
+  
+  uint32_t  xfer_count;    /*!< Partial transfer length in case of multi packet transfer.                  */
+  
+  uint8_t   toggle_in;     /*!< IN transfer current toggle flag.
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+                                
+  uint8_t   toggle_out;    /*!< OUT transfer current toggle flag
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+  
+  uint32_t  dma_addr;      /*!< 32 bits aligned transfer buffer address.                                   */
+  
+  uint32_t  ErrCnt;        /*!< Host channel error count.*/
+  
+  USB_OTG_URBStateTypeDef  urb_state;  /*!< URB state. 
+                                           This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ 
+  
+  USB_OTG_HCStateTypeDef   state;     /*!< Host Channel state. 
+                                           This parameter can be any value of @ref USB_OTG_HCStateTypeDef  */ 
+                                             
+}USB_OTG_HCTypeDef;
+  
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PCD_Exported_Constants
+  * @{
+  */
+
+/** @defgroup USB_Core_Mode_
+  * @{
+  */
+#define USB_OTG_MODE_DEVICE                    0
+#define USB_OTG_MODE_HOST                      1
+#define USB_OTG_MODE_DRD                       2
+/**
+  * @}
+  */
+
+/** @defgroup USB_Core_Speed_
+  * @{
+  */  
+#define USB_OTG_SPEED_HIGH                     0
+#define USB_OTG_SPEED_HIGH_IN_FULL             1
+#define USB_OTG_SPEED_LOW                      2  
+#define USB_OTG_SPEED_FULL                     3
+/**
+  * @}
+  */
+  
+/** @defgroup USB_Core_PHY_
+  * @{
+  */   
+#define USB_OTG_ULPI_PHY                       1
+#define USB_OTG_EMBEDDED_PHY                   2
+/**
+  * @}
+  */
+  
+/** @defgroup USB_Core_MPS_
+  * @{
+  */
+#define USB_OTG_HS_MAX_PACKET_SIZE           512
+#define USB_OTG_FS_MAX_PACKET_SIZE           64
+#define USB_OTG_MAX_EP0_SIZE                 64
+/**
+  * @}
+  */
+
+/** @defgroup USB_Core_Phy_Frequency_
+  * @{
+  */
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0 << 1)
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1 << 1)
+#define DSTS_ENUMSPD_LS_PHY_6MHZ               (2 << 1)
+#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3 << 1)
+/**
+  * @}
+  */
+  
+/** @defgroup USB_CORE_Frame_Interval_
+  * @{
+  */  
+#define DCFG_FRAME_INTERVAL_80                 0
+#define DCFG_FRAME_INTERVAL_85                 1
+#define DCFG_FRAME_INTERVAL_90                 2
+#define DCFG_FRAME_INTERVAL_95                 3
+/**
+  * @}
+  */
+
+/** @defgroup USB_EP0_MPS_
+  * @{
+  */
+#define DEP0CTL_MPS_64                         0
+#define DEP0CTL_MPS_32                         1
+#define DEP0CTL_MPS_16                         2
+#define DEP0CTL_MPS_8                          3
+/**
+  * @}
+  */
+
+/** @defgroup USB_EP_Speed_
+  * @{
+  */
+#define EP_SPEED_LOW                           0
+#define EP_SPEED_FULL                          1
+#define EP_SPEED_HIGH                          2
+/**
+  * @}
+  */
+
+/** @defgroup USB_EP_Type_
+  * @{
+  */
+#define EP_TYPE_CTRL                           0
+#define EP_TYPE_ISOC                           1
+#define EP_TYPE_BULK                           2
+#define EP_TYPE_INTR                           3
+#define EP_TYPE_MSK                            3
+/**
+  * @}
+  */
+
+/** @defgroup USB_STS_Defines_
+  * @{
+  */
+#define STS_GOUT_NAK                           1
+#define STS_DATA_UPDT                          2
+#define STS_XFER_COMP                          3
+#define STS_SETUP_COMP                         4
+#define STS_SETUP_UPDT                         6
+/**
+  * @}
+  */
+
+/** @defgroup HCFG_SPEED_Defines_
+  * @{
+  */  
+#define HCFG_30_60_MHZ                         0
+#define HCFG_48_MHZ                            1
+#define HCFG_6_MHZ                             2
+/**
+  * @}
+  */
+    
+/** @defgroup HPRT0_PRTSPD_SPEED_Defines_
+  * @{
+  */    
+#define HPRT0_PRTSPD_HIGH_SPEED                0
+#define HPRT0_PRTSPD_FULL_SPEED                1
+#define HPRT0_PRTSPD_LOW_SPEED                 2
+/**
+  * @}
+  */  
+   
+#define HCCHAR_CTRL                            0
+#define HCCHAR_ISOC                            1
+#define HCCHAR_BULK                            2
+#define HCCHAR_INTR                            3
+       
+#define HC_PID_DATA0                           0
+#define HC_PID_DATA2                           1
+#define HC_PID_DATA1                           2
+#define HC_PID_SETUP                           3
+
+#define GRXSTS_PKTSTS_IN                       2
+#define GRXSTS_PKTSTS_IN_XFER_COMP             3
+#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5
+#define GRXSTS_PKTSTS_CH_HALTED                7
+    
+#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
+#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
+
+#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE)) 
+#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))        
+#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))        
+#define USBx_DFIFO(i)   *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
+
+#define USBx_HOST       ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))  
+#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
+
+/* Exported macro ------------------------------------------------------------*/
+#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
+#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
+    
+#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
+#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))  
+
+/* Exported functions --------------------------------------------------------*/
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
+HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
+void *            USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
+uint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
+uint32_t          USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
+void              USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
+
+HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+uint32_t          USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,  
+                                  uint8_t ch_num,
+                                  uint8_t epnum,
+                                  uint8_t dev_address,
+                                  uint8_t speed,
+                                  uint8_t ep_type,
+                                  uint16_t mps);
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
+uint32_t          USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_LL_USB_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,703 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.c
+  * @author  MCD Application Team
+  * @version V2.1.0RC2
+  * @date    14-May-2014
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f4xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 16 MHz)
+  *                                    | 2- PLL_HSE_XTAL        |
+  *                                    | (external 8 MHz xtal)  |
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 84                     | 84
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 84                     | 84
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 42                     | 42
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 84                     | 84
+  *-----------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | YES                    | NO
+  *-----------------------------------------------------------------------------  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F4xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f4xx.h"
+#include "hal_tick.h"
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
+     on STM324xG_EVAL/STM324x9I_EVAL boards as data memory  */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+ 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* #define DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
+ #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " 
+#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+  * @{
+  */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+uint32_t SystemCoreClock = 84000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and External memory 
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* Configure the Cube driver */
+  SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
+  HAL_Init();
+
+  /* Configure the System clock source, PLL Multiplier and Divider factors,
+     AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+  
+  /* Reset the timer to avoid issues after the RAM initialization */
+  TIM_MST_RESET_ON;
+  TIM_MST_RESET_OFF;  
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
+  *              depends on the application requirements), user has to ensure that HSE_VALUE
+  *              is same as the real frequency of the crystal used. Otherwise, this function
+  *              may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f4xx.s before jump to main.
+  *         This function configures the external memories (SRAM/SDRAM)
+  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined (DATA_IN_ExtSDRAM)
+  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register uint32_t index;
+
+  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
+      clock */
+  RCC->AHB1ENR |= 0x000001F8;
+  
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x000000CC;
+  GPIOD->AFR[1]  = 0xCC000CCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xA02A000A;
+  /* Configure PDx pins speed to 50 MHz */  
+  GPIOD->OSPEEDR = 0xA02A000A;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 50 MHz */ 
+  GPIOE->OSPEEDR = 0xAAAA800A;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0xCCCCCCCC;
+  GPIOF->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA800AAA;
+  /* Configure PFx pins speed to 50 MHz */ 
+  GPIOF->OSPEEDR = 0xAA800AAA;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0xCCCCCCCC;
+  GPIOG->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0xAAAAAAAA;
+  /* Configure PGx pins speed to 50 MHz */ 
+  GPIOG->OSPEEDR = 0xAAAAAAAA;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+  /* Connect PHx pins to FMC Alternate function */
+  GPIOH->AFR[0]  = 0x00C0CC00;
+  GPIOH->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PHx pins in Alternate function mode */ 
+  GPIOH->MODER   = 0xAAAA08A0;
+  /* Configure PHx pins speed to 50 MHz */ 
+  GPIOH->OSPEEDR = 0xAAAA08A0;
+  /* Configure PHx pins Output type to push-pull */  
+  GPIOH->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PHx pins */ 
+  GPIOH->PUPDR   = 0x00000000;
+  
+  /* Connect PIx pins to FMC Alternate function */
+  GPIOI->AFR[0]  = 0xCCCCCCCC;
+  GPIOI->AFR[1]  = 0x00000CC0;
+  /* Configure PIx pins in Alternate function mode */ 
+  GPIOI->MODER   = 0x0028AAAA;
+  /* Configure PIx pins speed to 50 MHz */ 
+  GPIOI->OSPEEDR = 0x0028AAAA;
+  /* Configure PIx pins Output type to push-pull */  
+  GPIOI->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PIx pins */ 
+  GPIOI->PUPDR   = 0x00000000;
+  
+/*-- FMC Configuration ------------------------------------------------------*/
+  /* Enable the FMC interface clock */
+  RCC->AHB3ENR |= 0x00000001;
+  
+  /* Configure and enable SDRAM bank1 */
+  FMC_Bank5_6->SDCR[0] = 0x000019E0;
+  FMC_Bank5_6->SDTR[0] = 0x01115351;      
+  
+  /* SDRAM initialization sequence */
+  /* Clock enable command */
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+
+  /* Delay */
+  for (index = 0; index<1000; index++);
+  
+  /* PALL command */
+  FMC_Bank5_6->SDCMR = 0x00000012;           
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+  
+  /* Auto refresh command */
+  FMC_Bank5_6->SDCMR = 0x00000073;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+ 
+  /* MRD register program */
+  FMC_Bank5_6->SDCMR = 0x00046014;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
+  /* Set refresh count */
+  tmpreg = FMC_Bank5_6->SDRTR;
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+  
+  /* Disable write protection */
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
+  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+#endif /* DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(DATA_IN_ExtSRAM)
+/*-- GPIOs Configuration -----------------------------------------------------*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   |= 0x00000078;
+  
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CCC0CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A8A;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0FCF;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00CC0CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA828A;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC3CF;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x000000C0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00085AAA;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000CAFFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FMC/FSMC Configuration --------------------------------------------------*/                                                                               
+  /* Enable the FMC/FSMC interface clock */
+  RCC->AHB3ENR         |= 0x00000001;
+  
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001011;
+  FMC_Bank1->BTCR[3]  = 0x00000201;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001011;
+  FSMC_Bank1->BTCR[3]  = 0x00000201;
+  FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
+}
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).             
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+  /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+  if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+  {
+    /* 2- If fail try to start with HSE and external xtal */
+    #if USE_PLL_HSE_XTAL != 0
+    if (SetSysClock_PLL_HSE(0) == 0)
+    #endif
+    {
+      /* 3- If fail start with HSI clock */
+      if (SetSysClock_PLL_HSI() == 0)
+      {
+        while(1)
+        {
+          // [TODO] Put something here to tell the user that a problem occured...
+        }
+      }
+    }
+  }
+  
+  /* Output clock on MCO2 pin(PC9) for debugging purpose */
+  //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1); // 84 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  /* The voltage scaling allows optimizing the power consumption when the device is 
+     clocked below the maximum system frequency, to update the voltage scaling value 
+     regarding system frequency refer to product datasheet. */
+  __PWR_CLK_ENABLE();
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+  
+  /* Enable HSE oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+  if (bypass == 0)
+  {
+    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+  }
+  else
+  {
+    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+  }
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM            = 8;             // VCO input clock = 1 MHz (8 MHz / 8)
+  RCC_OscInitStruct.PLL.PLLN            = 336;           // VCO output clock = 336 MHz (1 MHz * 336)
+  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
+  RCC_OscInitStruct.PLL.PLLQ            = 7;             // USB clock = 48 MHz (336 MHz / 7) --> OK for USB
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+ 
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 84 MHz
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 42 MHz
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 84 MHz
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+
+  /* Output clock on MCO1 pin(PA8) for debugging purpose */
+  /*
+  if (bypass == 0)
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+  else
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+  */
+  
+  return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  /* The voltage scaling allows optimizing the power consumption when the device is 
+     clocked below the maximum system frequency, to update the voltage scaling value 
+     regarding system frequency refer to product datasheet. */
+  __PWR_CLK_ENABLE();
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+ 
+  /* Enable HSI oscillator and activate PLL with HSI as source */
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+  RCC_OscInitStruct.HSICalibrationValue = 16;
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI; 
+  RCC_OscInitStruct.PLL.PLLM            = 16;            // VCO input clock = 1 MHz (16 MHz / 16)
+  RCC_OscInitStruct.PLL.PLLN            = 336;           // VCO output clock = 336 MHz (1 MHz * 336)
+  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
+  RCC_OscInitStruct.PLL.PLLQ            = 7;             // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+ 
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 84 MHz
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 42 MHz
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 84 MHz
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+  {
+    return 0; // FAIL
+  }
+
+  /* Output clock on MCO1 pin(PA8) for debugging purpose */
+  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+  return 1; // OK
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,125 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.h
+  * @author  MCD Application Team
+  * @version V2.1.0RC2
+  * @date    14-May-2014
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F4xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/core_cm0.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,683 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/core_cm0plus.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,794 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x20)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/core_cm3.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1628 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/core_cm4.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,1773 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/core_cm4_simd.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,674 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/core_cmFunc.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,637 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/cmsis/core_cmInstr.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,689 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.20
+ * @date     05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PeripheralNames.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,81 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+    UART_1 = (int)USART1_BASE,
+    UART_2 = (int)USART2_BASE,
+    UART_6 = (int)USART6_BASE
+} UARTName;
+
+#define STDIO_UART_TX  PA_2
+#define STDIO_UART_RX  PA_3
+#define STDIO_UART     UART_2
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE,
+    SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE,
+    I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1  = (int)TIM1_BASE,
+    PWM_2  = (int)TIM2_BASE,
+    PWM_3  = (int)TIM3_BASE,
+    PWM_4  = (int)TIM4_BASE,
+    PWM_5  = (int)TIM5_BASE,
+    PWM_9  = (int)TIM9_BASE,
+    PWM_10 = (int)TIM10_BASE,
+    PWM_11 = (int)TIM11_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PinNames.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,182 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
+#define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
+#define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
+#define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
+#define STM_MODE_INPUT              (0)
+#define STM_MODE_OUTPUT_PP          (1)
+#define STM_MODE_OUTPUT_OD          (2)
+#define STM_MODE_AF_PP              (3)
+#define STM_MODE_AF_OD              (4)
+#define STM_MODE_ANALOG             (5)
+#define STM_MODE_IT_RISING          (6)
+#define STM_MODE_IT_FALLING         (7)
+#define STM_MODE_IT_RISING_FALLING  (8)
+#define STM_MODE_EVT_RISING         (9)
+#define STM_MODE_EVT_FALLING        (10)
+#define STM_MODE_EVT_RISING_FALLING (11)
+
+// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
+// Low nibble  = pin number
+#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
+#define STM_PIN(X)  ((uint32_t)(X) & 0xF)
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+    PA_0  = 0x00,
+    PA_1  = 0x01,
+    PA_2  = 0x02,
+    PA_3  = 0x03,
+    PA_4  = 0x04,
+    PA_5  = 0x05,
+    PA_6  = 0x06,
+    PA_7  = 0x07,
+    PA_8  = 0x08,
+    PA_9  = 0x09,
+    PA_10 = 0x0A,
+    PA_11 = 0x0B,
+    PA_12 = 0x0C,
+    PA_13 = 0x0D,
+    PA_14 = 0x0E,
+    PA_15 = 0x0F,
+
+    PB_0  = 0x10,
+    PB_1  = 0x11,
+    PB_2  = 0x12,
+    PB_3  = 0x13,
+    PB_4  = 0x14,
+    PB_5  = 0x15,
+    PB_6  = 0x16,
+    PB_7  = 0x17,
+    PB_8  = 0x18,
+    PB_9  = 0x19,
+    PB_10 = 0x1A,
+    PB_12 = 0x1C,
+    PB_13 = 0x1D,
+    PB_14 = 0x1E,
+    PB_15 = 0x1F,
+
+    PC_0  = 0x20,
+    PC_1  = 0x21,
+    PC_2  = 0x22,
+    PC_3  = 0x23,
+    PC_4  = 0x24,
+    PC_5  = 0x25,
+    PC_6  = 0x26,
+    PC_7  = 0x27,
+    PC_8  = 0x28,
+    PC_9  = 0x29,
+    PC_10 = 0x2A,
+    PC_11 = 0x2B,
+    PC_12 = 0x2C,
+    PC_13 = 0x2D,
+    PC_14 = 0x2E,
+    PC_15 = 0x2F,
+
+    PD_2  = 0x32,
+
+    PH_0  = 0x70,
+    PH_1  = 0x71,
+
+    // Arduino connector namings
+    A0          = PA_0,
+    A1          = PA_1,
+    A2          = PA_4,
+    A3          = PB_0,
+    A4          = PC_1,
+    A5          = PC_0,
+    D0          = PA_3,
+    D1          = PA_2,
+    D2          = PA_10,
+    D3          = PB_3,
+    D4          = PB_5,
+    D5          = PB_4,
+    D6          = PB_10,
+    D7          = PA_8,
+    D8          = PA_9,
+    D9          = PC_7,
+    D10         = PB_6,
+    D11         = PA_7,
+    D12         = PA_6,
+    D13         = PA_5,
+    D14         = PB_9,
+    D15         = PB_8,
+
+    // Generic signals namings
+    LED1        = PA_5,
+    LED2        = PA_5,
+    LED3        = PA_5,
+    LED4        = PA_5,
+    USER_BUTTON = PC_13,
+    SERIAL_TX   = PA_2,
+    SERIAL_RX   = PA_3,
+    USBTX       = PA_2,
+    USBRX       = PA_3,
+    I2C_SCL     = PB_8,
+    I2C_SDA     = PB_9,
+    SPI_MOSI    = PA_7,
+    SPI_MISO    = PA_6,
+    SPI_SCK     = PA_5,
+    SPI_CS      = PB_6,
+    PWM_OUT     = PB_3,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullNone  = 0,
+    PullUp    = 1,
+    PullDown  = 2,
+    OpenDrain = 3,
+    PullDefault = PullNone
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/PortNames.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PortA = 0,
+    PortB = 1,
+    PortC = 2,
+    PortD = 3,
+    PortH = 7
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/analogin_api.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,182 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "wait_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+
+static const PinMap PinMap_ADC[] = {
+    {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0
+    {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1
+    {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2
+    {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3
+    {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4
+    {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5
+    {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6
+    {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7
+    {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8
+    {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9
+    {PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10
+    {PC_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN11
+    {PC_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN12
+    {PC_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN13
+    {PC_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN14
+    {PC_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN15
+    {NC,   NC,    0}
+};
+
+ADC_HandleTypeDef AdcHandle;
+
+int adc_inited = 0;
+
+void analogin_init(analogin_t *obj, PinName pin) {
+    // Get the peripheral name from the pin and assign it to the object
+    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    MBED_ASSERT(obj->adc != (ADCName)NC);
+
+    // Configure GPIO
+    pinmap_pinout(pin, PinMap_ADC);
+
+    // Save pin number for the read function
+    obj->pin = pin;
+
+    // The ADC initialization is done once
+    if (adc_inited == 0) {
+        adc_inited = 1;
+
+        // Enable ADC clock
+        __ADC1_CLK_ENABLE();
+
+        // Configure ADC
+        AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
+        AdcHandle.Init.ClockPrescaler        = ADC_CLOCKPRESCALER_PCLK_DIV2;
+        AdcHandle.Init.Resolution            = ADC_RESOLUTION12b;
+        AdcHandle.Init.ScanConvMode          = DISABLE;
+        AdcHandle.Init.ContinuousConvMode    = DISABLE;
+        AdcHandle.Init.DiscontinuousConvMode = DISABLE;
+        AdcHandle.Init.NbrOfDiscConversion   = 0;
+        AdcHandle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
+        AdcHandle.Init.ExternalTrigConv      = ADC_EXTERNALTRIGCONV_T1_CC1;
+        AdcHandle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+        AdcHandle.Init.NbrOfConversion       = 1;
+        AdcHandle.Init.DMAContinuousRequests = DISABLE;
+        AdcHandle.Init.EOCSelection          = DISABLE;
+        HAL_ADC_Init(&AdcHandle);
+    }
+}
+
+static inline uint16_t adc_read(analogin_t *obj) {
+    ADC_ChannelConfTypeDef sConfig;
+
+    AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
+
+    // Configure ADC channel
+    sConfig.Rank         = 1;
+    sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
+    sConfig.Offset       = 0;
+
+    switch (obj->pin) {
+        case PA_0:
+            sConfig.Channel = ADC_CHANNEL_0;
+            break;
+        case PA_1:
+            sConfig.Channel = ADC_CHANNEL_1;
+            break;
+        case PA_2:
+            sConfig.Channel = ADC_CHANNEL_2;
+            break;
+        case PA_3:
+            sConfig.Channel = ADC_CHANNEL_3;
+            break;
+        case PA_4:
+            sConfig.Channel = ADC_CHANNEL_4;
+            break;
+        case PA_5:
+            sConfig.Channel = ADC_CHANNEL_5;
+            break;
+        case PA_6:
+            sConfig.Channel = ADC_CHANNEL_6;
+            break;
+        case PA_7:
+            sConfig.Channel = ADC_CHANNEL_7;
+            break;
+        case PB_0:
+            sConfig.Channel = ADC_CHANNEL_8;
+            break;
+        case PB_1:
+            sConfig.Channel = ADC_CHANNEL_9;
+            break;
+        case PC_0:
+            sConfig.Channel = ADC_CHANNEL_10;
+            break;
+        case PC_1:
+            sConfig.Channel = ADC_CHANNEL_11;
+            break;
+        case PC_2:
+            sConfig.Channel = ADC_CHANNEL_12;
+            break;
+        case PC_3:
+            sConfig.Channel = ADC_CHANNEL_13;
+            break;
+        case PC_4:
+            sConfig.Channel = ADC_CHANNEL_14;
+            break;
+        case PC_5:
+            sConfig.Channel = ADC_CHANNEL_15;
+            break;
+        default:
+            return 0;
+    }
+
+    HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);
+
+    HAL_ADC_Start(&AdcHandle); // Start conversion
+
+    // Wait end of conversion and get value
+    if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) {
+        return (HAL_ADC_GetValue(&AdcHandle));
+    } else {
+        return 0;
+    }
+}
+
+uint16_t analogin_read_u16(analogin_t *obj) {
+    return (adc_read(obj));
+}
+
+float analogin_read(analogin_t *obj) {
+    uint16_t value = adc_read(obj);
+    return (float)value * (1.0f / (float)0xFFF); // 12 bits range
+}
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/device.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,71 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN           1
+#define DEVICE_PORTOUT          1
+#define DEVICE_PORTINOUT        1
+
+#define DEVICE_INTERRUPTIN      1
+
+#define DEVICE_ANALOGIN         1
+#define DEVICE_ANALOGOUT        0 // Not present on this device
+
+#define DEVICE_SERIAL           1
+
+#define DEVICE_I2C              1
+#define DEVICE_I2CSLAVE         1
+
+#define DEVICE_SPI              1
+#define DEVICE_SPISLAVE         1
+
+#define DEVICE_RTC              1
+
+#define DEVICE_PWMOUT           1
+
+#define DEVICE_SLEEP            1
+
+//=======================================
+
+#define DEVICE_SEMIHOST         0
+#define DEVICE_LOCALFILESYSTEM  0
+#define DEVICE_ID_LENGTH       24
+
+#define DEVICE_DEBUG_AWARENESS  0
+
+#define DEVICE_STDIO_MESSAGES   1
+
+#define DEVICE_ERROR_RED        0
+
+#include "objects.h"
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_api.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,74 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
+
+uint32_t gpio_set(PinName pin) {
+    MBED_ASSERT(pin != (PinName)NC);
+
+    pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
+}
+
+void gpio_init(gpio_t *obj, PinName pin) {
+    obj->pin = pin;
+    if (pin == (PinName)NC)
+        return;
+
+    uint32_t port_index = STM_PORT(pin);
+
+    // Enable GPIO clock
+    uint32_t gpio_add = Set_GPIO_Clock(port_index);
+    GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+    // Fill GPIO object structure for future use
+    obj->mask    = gpio_set(pin);
+    obj->reg_in  = &gpio->IDR;
+    obj->reg_set = &gpio->BSRRL;
+    obj->reg_clr = &gpio->BSRRH;
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+    pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction) {
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    if (direction == PIN_OUTPUT) {
+        pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
+    } else { // PIN_INPUT
+        pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_irq_api.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,239 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include <stddef.h>
+#include "cmsis.h"
+#include "gpio_irq_api.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+#define EDGE_NONE (0)
+#define EDGE_RISE (1)
+#define EDGE_FALL (2)
+#define EDGE_BOTH (3)
+
+#define CHANNEL_NUM (7)
+
+static uint32_t channel_ids[CHANNEL_NUM]  = {0, 0, 0, 0, 0, 0, 0};
+static uint32_t channel_gpio[CHANNEL_NUM] = {0, 0, 0, 0, 0, 0, 0};
+static uint32_t channel_pin[CHANNEL_NUM]  = {0, 0, 0, 0, 0, 0, 0};
+
+static gpio_irq_handler irq_handler;
+
+static void handle_interrupt_in(uint32_t irq_index) {
+    // Retrieve the gpio and pin that generate the irq
+    GPIO_TypeDef *gpio = (GPIO_TypeDef *)(channel_gpio[irq_index]);
+    uint32_t pin = (uint32_t)(1 << channel_pin[irq_index]);
+
+    // Clear interrupt flag
+    if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) {
+        __HAL_GPIO_EXTI_CLEAR_FLAG(pin);
+    }
+
+    if (channel_ids[irq_index] == 0) return;
+
+    // Check which edge has generated the irq
+    if ((gpio->IDR & pin) == 0) {
+        irq_handler(channel_ids[irq_index], IRQ_FALL);
+    } else  {
+        irq_handler(channel_ids[irq_index], IRQ_RISE);
+    }
+}
+
+// The irq_index is passed to the function
+// EXTI line 0
+static void gpio_irq0(void) {
+    handle_interrupt_in(0);
+}
+// EXTI line 1
+static void gpio_irq1(void) {
+    handle_interrupt_in(1);
+}
+// EXTI line 2
+static void gpio_irq2(void) {
+    handle_interrupt_in(2);
+}
+// EXTI line 3
+static void gpio_irq3(void) {
+    handle_interrupt_in(3);
+}
+// EXTI line 4
+static void gpio_irq4(void) {
+    handle_interrupt_in(4);
+}
+// EXTI lines 5 to 9
+static void gpio_irq5(void) {
+    handle_interrupt_in(5);
+}
+// EXTI lines 10 to 15
+static void gpio_irq6(void) {
+    handle_interrupt_in(6);
+}
+
+extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+    IRQn_Type irq_n = (IRQn_Type)0;
+    uint32_t vector = 0;
+    uint32_t irq_index;
+
+    if (pin == NC) return -1;
+
+    uint32_t port_index = STM_PORT(pin);
+    uint32_t pin_index  = STM_PIN(pin);
+
+    // Select irq number and interrupt routine
+    switch (pin_index) {
+        case 0:
+            irq_n = EXTI0_IRQn;
+            vector = (uint32_t)&gpio_irq0;
+            irq_index = 0;
+            break;
+        case 1:
+            irq_n = EXTI1_IRQn;
+            vector = (uint32_t)&gpio_irq1;
+            irq_index = 1;
+            break;
+        case 2:
+            irq_n = EXTI2_IRQn;
+            vector = (uint32_t)&gpio_irq2;
+            irq_index = 2;
+            break;
+        case 3:
+            irq_n = EXTI3_IRQn;
+            vector = (uint32_t)&gpio_irq3;
+            irq_index = 3;
+            break;
+        case 4:
+            irq_n = EXTI4_IRQn;
+            vector = (uint32_t)&gpio_irq4;
+            irq_index = 4;
+            break;
+        case 5:
+        case 6:
+        case 7:
+        case 8:
+        case 9:
+            irq_n = EXTI9_5_IRQn;
+            vector = (uint32_t)&gpio_irq5;
+            irq_index = 5;
+            break;
+        case 10:
+        case 11:
+        case 12:
+        case 13:
+        case 14:
+        case 15:
+            irq_n = EXTI15_10_IRQn;
+            vector = (uint32_t)&gpio_irq6;
+            irq_index = 6;
+            break;
+        default:
+            error("InterruptIn error: pin not supported.\n");
+            return -1;
+    }
+
+    // Enable GPIO clock
+    uint32_t gpio_add = Set_GPIO_Clock(port_index);
+
+    // Configure GPIO
+    pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0));
+
+    // Enable EXTI interrupt
+    NVIC_SetVector(irq_n, vector);
+    NVIC_EnableIRQ(irq_n);
+
+    // Save informations for future use
+    obj->irq_n = irq_n;
+    obj->irq_index = irq_index;
+    obj->event = EDGE_NONE;
+    obj->pin = pin;
+    channel_ids[irq_index] = id;
+    channel_gpio[irq_index] = gpio_add;
+    channel_pin[irq_index] = pin_index;
+
+    irq_handler = handler;
+
+    return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj) {
+    channel_ids[obj->irq_index] = 0;
+    channel_gpio[obj->irq_index] = 0;
+    channel_pin[obj->irq_index] = 0;
+    // Disable EXTI line
+    pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    obj->event = EDGE_NONE;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+    uint32_t mode = STM_MODE_INPUT;
+    uint32_t pull = GPIO_NOPULL;
+
+    if (enable) {
+
+        pull = GPIO_NOPULL;
+
+        if (event == IRQ_RISE) {
+            if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
+                mode = STM_MODE_IT_RISING_FALLING;
+                obj->event = EDGE_BOTH;
+            } else { // NONE or RISE
+                mode = STM_MODE_IT_RISING;
+                obj->event = EDGE_RISE;
+            }
+        }
+
+        if (event == IRQ_FALL) {
+            if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
+                mode = STM_MODE_IT_RISING_FALLING;
+                obj->event = EDGE_BOTH;
+            } else { // NONE or FALL
+                mode = STM_MODE_IT_FALLING;
+                obj->event = EDGE_FALL;
+            }
+        }
+    } else {
+        mode = STM_MODE_INPUT;
+        pull = GPIO_NOPULL;
+        obj->event = EDGE_NONE;
+    }
+
+    pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0));
+}
+
+void gpio_irq_enable(gpio_irq_t *obj) {
+    NVIC_EnableIRQ(obj->irq_n);
+}
+
+void gpio_irq_disable(gpio_irq_t *obj) {
+    NVIC_DisableIRQ(obj->irq_n);
+    obj->event = EDGE_NONE;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/gpio_object.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,70 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName  pin;
+    uint32_t mask;
+    __IO uint32_t *reg_in;
+    __IO uint16_t *reg_set;
+    __IO uint16_t *reg_clr;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    if (value) {
+        *obj->reg_set = obj->mask;
+    } else {
+        *obj->reg_clr = obj->mask;
+    }
+}
+
+static inline int gpio_read(gpio_t *obj) {
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/i2c_api.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,469 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "i2c_api.h"
+
+#if DEVICE_I2C
+
+#include "cmsis.h"
+#include "pinmap.h"
+
+/* Timeout values for flags and events waiting loops. These timeouts are
+   not based on accurate values, they just guarantee that the application will
+   not remain stuck if the I2C communication is corrupted. */
+#define FLAG_TIMEOUT ((int)0x1000)
+#define LONG_TIMEOUT ((int)0x8000)
+
+static const PinMap PinMap_I2C_SDA[] = {
+    {PB_3,  I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+    {PB_4,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF4_I2C1)},
+    {PC_9,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {NC,    NC,    0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+    {PA_8,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF4_I2C1)},
+    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {NC,    NC,    0}
+};
+
+I2C_HandleTypeDef I2cHandle;
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+    // Determine the I2C to use
+    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+
+    obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
+    MBED_ASSERT(obj->i2c != (I2CName)NC);
+
+    // Enable I2C clock
+    if (obj->i2c == I2C_1) {
+        __I2C1_CLK_ENABLE();
+    }
+    if (obj->i2c == I2C_2) {
+        __I2C2_CLK_ENABLE();
+    }
+    if (obj->i2c == I2C_3) {
+        __I2C3_CLK_ENABLE();
+    }
+
+    // Configure I2C pins
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+    pin_mode(sda, OpenDrain);
+    pin_mode(scl, OpenDrain);
+
+    // Reset to clear pending flags if any
+    i2c_reset(obj);
+
+    // I2C configuration
+    i2c_frequency(obj, 100000); // 100 kHz per default
+
+    // I2C master by default
+    obj->slave = 0;
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+    MBED_ASSERT((hz != 0) && (hz <= 400000));
+    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+
+    // I2C configuration
+    I2cHandle.Init.AddressingMode  = I2C_ADDRESSINGMODE_7BIT;
+    I2cHandle.Init.ClockSpeed      = hz;
+    I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED;
+    I2cHandle.Init.DutyCycle       = I2C_DUTYCYCLE_2;
+    I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED;
+    I2cHandle.Init.NoStretchMode   = I2C_NOSTRETCH_DISABLED;
+    I2cHandle.Init.OwnAddress1     = 0;
+    I2cHandle.Init.OwnAddress2     = 0;
+    HAL_I2C_Init(&I2cHandle);
+    if (obj->slave) {
+        /* Enable Address Acknowledge */
+        I2cHandle.Instance->CR1 |= I2C_CR1_ACK;
+    }
+
+}
+
+inline int i2c_start(i2c_t *obj) {
+    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+    int timeout;
+
+    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+
+    // Clear Acknowledge failure flag
+    __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF);
+
+    // Generate the START condition
+    i2c->CR1 |= I2C_CR1_START;
+
+    // Wait the START condition has been correctly sent
+    timeout = FLAG_TIMEOUT;
+    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_SB) == RESET) {
+        if ((timeout--) == 0) {
+            return 1;
+        }
+    }
+
+    return 0;
+}
+
+inline int i2c_stop(i2c_t *obj) {
+    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+
+    // Generate the STOP condition
+    i2c->CR1 |= I2C_CR1_STOP;
+
+    return 0;
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+    int timeout;
+    int count;
+    int value;
+
+    i2c_start(obj);
+
+    // Wait until SB flag is set
+    timeout = FLAG_TIMEOUT;
+    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_SB) == RESET) {
+        timeout--;
+        if (timeout == 0) {
+            return -1;
+        }
+    }
+
+    i2c->DR = __HAL_I2C_7BIT_ADD_READ(address);
+
+
+    // Wait address is acknowledged
+    timeout = FLAG_TIMEOUT;
+    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == RESET) {
+        timeout--;
+        if (timeout == 0) {
+            return -1;
+        }
+    }
+    __HAL_I2C_CLEAR_ADDRFLAG(&I2cHandle);
+
+    // Read all bytes except last one
+    for (count = 0; count < (length - 1); count++) {
+        value = i2c_byte_read(obj, 0);
+        data[count] = (char)value;
+    }
+
+    // If not repeated start, send stop.
+    // Warning: must be done BEFORE the data is read.
+    if (stop) {
+        i2c_stop(obj);
+    }
+
+    // Read the last byte
+    value = i2c_byte_read(obj, 1);
+    data[count] = (char)value;
+
+    return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+    int timeout;
+    int count;
+
+    i2c_start(obj);
+
+    // Wait until SB flag is set
+    timeout = FLAG_TIMEOUT;
+    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_SB) == RESET) {
+        timeout--;
+        if (timeout == 0) {
+            return -1;
+        }
+    }
+
+    i2c->DR = __HAL_I2C_7BIT_ADD_WRITE(address);
+
+
+    // Wait address is acknowledged
+    timeout = FLAG_TIMEOUT;
+    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == RESET) {
+        timeout--;
+        if (timeout == 0) {
+            return -1;
+        }
+    }
+    __HAL_I2C_CLEAR_ADDRFLAG(&I2cHandle);
+
+    for (count = 0; count < length; count++) {
+        if (i2c_byte_write(obj, data[count]) != 1) {
+            i2c_stop(obj);
+            return -1;
+        }
+    }
+
+    // If not repeated start, send stop.
+    if (stop) {
+        i2c_stop(obj);
+    }
+
+    return count;
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+    int timeout;
+
+    if (last) {
+        // Don't acknowledge the last byte
+        i2c->CR1 &= ~I2C_CR1_ACK;
+    } else {
+        // Acknowledge the byte
+        i2c->CR1 |= I2C_CR1_ACK;
+    }
+
+    // Wait until the byte is received
+    timeout = FLAG_TIMEOUT;
+    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) {
+        if ((timeout--) == 0) {
+            return -1;
+        }
+    }
+
+    return (int)i2c->DR;
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+    int timeout;
+
+    i2c->DR = (uint8_t)data;
+
+    // Wait until the byte is transmitted
+    timeout = FLAG_TIMEOUT;
+    while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXE) == RESET) &&
+            (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == RESET)) {
+        if ((timeout--) == 0) {
+            return 0;
+        }
+    }
+
+    return 1;
+}
+
+void i2c_reset(i2c_t *obj) {
+    if (obj->i2c == I2C_1) {
+        __I2C1_FORCE_RESET();
+        __I2C1_RELEASE_RESET();
+    }
+    if (obj->i2c == I2C_2) {
+        __I2C2_FORCE_RESET();
+        __I2C2_RELEASE_RESET();
+    }
+    if (obj->i2c == I2C_3) {
+        __I2C3_FORCE_RESET();
+        __I2C3_RELEASE_RESET();
+    }
+}
+
+#if DEVICE_I2CSLAVE
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+    uint16_t tmpreg = 0;
+
+    // Get the old register value
+    tmpreg = i2c->OAR1;
+    // Reset address bits
+    tmpreg &= 0xFC00;
+    // Set new address
+    tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits
+    // Store the new register value
+    i2c->OAR1 = tmpreg;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+    if (enable_slave) {
+        obj->slave = 1;
+        /* Enable Address Acknowledge */
+        I2cHandle.Instance->CR1 |= I2C_CR1_ACK;
+    }
+}
+
+// See I2CSlave.h
+#define NoData         0 // the slave has not been addressed
+#define ReadAddressed  1 // the master has requested a read from this slave (slave = transmitter)
+#define WriteGeneral   2 // the master is writing to all slave
+#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
+
+int i2c_slave_receive(i2c_t *obj) {
+    int retValue = NoData;
+
+    if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) {
+        if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) {
+            if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TRA) == 1)
+                retValue = ReadAddressed;
+            else
+                retValue = WriteAddressed;
+
+            __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR);
+        }
+    }
+
+    return (retValue);
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+    uint32_t Timeout;
+    int size = 0;
+
+    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+
+    while (length > 0) {
+        /* Wait until RXNE flag is set */
+        // Wait until the byte is received
+        Timeout = FLAG_TIMEOUT;
+        while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) {
+            Timeout--;
+            if (Timeout == 0) {
+                return -1;
+            }
+        }
+
+        /* Read data from DR */
+        (*data++) = I2cHandle.Instance->DR;
+        length--;
+        size++;
+
+        if ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == SET) && (length != 0)) {
+            /* Read data from DR */
+            (*data++) = I2cHandle.Instance->DR;
+            length--;
+            size++;
+        }
+    }
+
+    /* Wait until STOP flag is set */
+    Timeout = FLAG_TIMEOUT;
+    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) {
+        Timeout--;
+        if (Timeout == 0) {
+            return -1;
+        }
+    }
+
+    /* Clear STOP flag */
+    __HAL_I2C_CLEAR_STOPFLAG(&I2cHandle);
+
+    /* Wait until BUSY flag is reset */
+    Timeout = FLAG_TIMEOUT;
+    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == SET) {
+        Timeout--;
+        if (Timeout == 0) {
+            return -1;
+        }
+    }
+
+    return size;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+    uint32_t Timeout;
+    int size = 0;
+
+    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+
+    while (length > 0) {
+        /* Wait until TXE flag is set */
+        Timeout = FLAG_TIMEOUT;
+        while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXE) == RESET) {
+            Timeout--;
+            if (Timeout == 0) {
+                return -1;
+            }
+        }
+
+
+        /* Write data to DR */
+        I2cHandle.Instance->DR = (*data++);
+        length--;
+        size++;
+
+        if ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == SET) && (length != 0)) {
+            /* Write data to DR */
+            I2cHandle.Instance->DR = (*data++);
+            length--;
+            size++;
+        }
+    }
+
+    /* Wait until AF flag is set */
+    Timeout = FLAG_TIMEOUT;
+    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_AF) == RESET) {
+        Timeout--;
+        if (Timeout == 0) {
+            return -1;
+        }
+    }
+
+
+    /* Clear AF flag */
+    __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF);
+
+
+    /* Wait until BUSY flag is reset */
+    Timeout = FLAG_TIMEOUT;
+    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == SET) {
+        Timeout--;
+        if (Timeout == 0) {
+            return -1;
+        }
+    }
+
+    I2cHandle.State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(&I2cHandle);
+
+    return size;
+}
+
+
+#endif // DEVICE_I2CSLAVE
+
+#endif // DEVICE_I2C
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/mbed_overrides.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,37 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "cmsis.h"
+
+// This function is called after RAM initialization and before main.
+void mbed_sdk_init() {
+    // Update the SystemCoreClock variable.
+    SystemCoreClockUpdate();
+    // Need to restart HAL driver after the RAM is initialized
+    HAL_Init();
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/objects.h	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,106 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    IRQn_Type irq_n;
+    uint32_t irq_index;
+    uint32_t event;
+    PinName pin;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+    PinDirection direction;
+    __IO uint32_t *reg_in;
+    __IO uint32_t *reg_out;
+};
+
+struct analogin_s {
+    ADCName adc;
+    PinName pin;
+};
+
+struct serial_s {
+    UARTName uart;
+    int index; // Used by irq
+    uint32_t baudrate;
+    uint32_t databits;
+    uint32_t stopbits;
+    uint32_t parity;
+    PinName pin_tx;
+    PinName pin_rx;
+};
+
+struct spi_s {
+    SPIName spi;
+    uint32_t bits;
+    uint32_t cpol;
+    uint32_t cpha;
+    uint32_t mode;
+    uint32_t nss;
+    uint32_t br_presc;
+    PinName pin_miso;
+    PinName pin_mosi;
+    PinName pin_sclk;
+    PinName pin_ssel;
+};
+
+struct i2c_s {
+    I2CName  i2c;
+    uint32_t slave;
+};
+
+struct pwmout_s {
+    PWMName pwm;
+    PinName pin;
+    uint32_t period;
+    uint32_t pulse;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/pinmap.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,138 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "PortNames.h"
+#include "mbed_error.h"
+
+// GPIO mode look-up table
+static const uint32_t gpio_mode[12] = {
+    0x00000000, //  0 = GPIO_MODE_INPUT
+    0x00000001, //  1 = GPIO_MODE_OUTPUT_PP
+    0x00000011, //  2 = GPIO_MODE_OUTPUT_OD
+    0x00000002, //  3 = GPIO_MODE_AF_PP
+    0x00000012, //  4 = GPIO_MODE_AF_OD
+    0x00000003, //  5 = GPIO_MODE_ANALOG
+    0x10110000, //  6 = GPIO_MODE_IT_RISING
+    0x10210000, //  7 = GPIO_MODE_IT_FALLING
+    0x10310000, //  8 = GPIO_MODE_IT_RISING_FALLING
+    0x10120000, //  9 = GPIO_MODE_EVT_RISING
+    0x10220000, // 10 = GPIO_MODE_EVT_FALLING
+    0x10320000  // 11 = GPIO_MODE_EVT_RISING_FALLING
+};
+
+// Enable GPIO clock and return GPIO base address
+uint32_t Set_GPIO_Clock(uint32_t port_idx) {
+    uint32_t gpio_add = 0;
+    switch (port_idx) {
+        case PortA:
+            gpio_add = GPIOA_BASE;
+            __GPIOA_CLK_ENABLE();
+            break;
+        case PortB:
+            gpio_add = GPIOB_BASE;
+            __GPIOB_CLK_ENABLE();
+            break;
+        case PortC:
+            gpio_add = GPIOC_BASE;
+            __GPIOC_CLK_ENABLE();
+            break;
+        case PortD:
+            gpio_add = GPIOD_BASE;
+            __GPIOD_CLK_ENABLE();
+            break;
+        case PortH:
+            gpio_add = GPIOH_BASE;
+            __GPIOH_CLK_ENABLE();
+            break;
+        default:
+            error("Pinmap error: wrong port number.");
+            break;
+    }
+    return gpio_add;
+}
+
+/**
+ * Configure pin (mode, speed, output type and pull-up/pull-down)
+ */
+void pin_function(PinName pin, int data) {
+    MBED_ASSERT(pin != (PinName)NC);
+    // Get the pin informations
+    uint32_t mode  = STM_PIN_MODE(data);
+    uint32_t pupd  = STM_PIN_PUPD(data);
+    uint32_t afnum = STM_PIN_AFNUM(data);
+
+    uint32_t port_index = STM_PORT(pin);
+    uint32_t pin_index  = STM_PIN(pin);
+
+    // Enable GPIO clock
+    uint32_t gpio_add = Set_GPIO_Clock(port_index);
+    GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+    // Configure GPIO
+    GPIO_InitTypeDef GPIO_InitStructure;
+    GPIO_InitStructure.Pin       = (uint32_t)(1 << pin_index);
+    GPIO_InitStructure.Mode      = gpio_mode[mode];
+    GPIO_InitStructure.Pull      = pupd;
+    GPIO_InitStructure.Speed     = GPIO_SPEED_HIGH;
+    GPIO_InitStructure.Alternate = afnum;
+    HAL_GPIO_Init(gpio, &GPIO_InitStructure);
+
+    // [TODO] Disconnect JTAG-DP + SW-DP signals.
+    // Warning: Need to reconnect under reset
+    //if ((pin == PA_13) || (pin == PA_14)) {
+    //
+    //}
+    //if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
+    //
+    //}
+}
+
+/**
+ * Configure pin pull-up/pull-down
+ */
+void pin_mode(PinName pin, PinMode mode) {
+    MBED_ASSERT(pin != (PinName)NC);
+    uint32_t port_index = STM_PORT(pin);
+    uint32_t pin_index  = STM_PIN(pin);
+
+    // Enable GPIO clock
+    uint32_t gpio_add = Set_GPIO_Clock(port_index);
+    GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+    // Configure pull-up/pull-down resistors
+    uint32_t pupd = (uint32_t)mode;
+    if (pupd > 2)
+        pupd = 0; // Open-drain = No pull-up/No pull-down
+    gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPDR0 << (pin_index * 2)));
+    gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2));
+
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/port_api.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,98 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+#include "mbed_error.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
+extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
+
+// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...)
+// low nibble  = pin number
+PinName port_pin(PortName port, int pin_n) {
+    return (PinName)(pin_n + (port << 4));
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
+    uint32_t port_index = (uint32_t)port;
+
+    // Enable GPIO clock
+    uint32_t gpio_add = Set_GPIO_Clock(port_index);
+    GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+    // Fill PORT object structure for future use
+    obj->port      = port;
+    obj->mask      = mask;
+    obj->direction = dir;
+    obj->reg_in    = &gpio->IDR;
+    obj->reg_out   = &gpio->ODR;
+
+    port_dir(obj, dir);
+}
+
+void port_dir(port_t *obj, PinDirection dir) {
+    uint32_t i;
+    obj->direction = dir;
+    for (i = 0; i < 16; i++) { // Process all pins
+        if (obj->mask & (1 << i)) { // If the pin is used
+            if (dir == PIN_OUTPUT) {
+                pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
+            } else { // PIN_INPUT
+                pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+            }
+        }
+    }
+}
+
+void port_mode(port_t *obj, PinMode mode) {
+    uint32_t i;
+    for (i = 0; i < 16; i++) { // Process all pins
+        if (obj->mask & (1 << i)) { // If the pin is used
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_write(port_t *obj, int value) {
+    *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask);
+}
+
+int port_read(port_t *obj) {
+    if (obj->direction == PIN_OUTPUT) {
+        return (*obj->reg_out & obj->mask);
+    } else { // PIN_INPUT
+        return (*obj->reg_in & obj->mask);
+    }
+}
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/pwmout_api.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,273 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "pwmout_api.h"
+
+#if DEVICE_PWMOUT
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+// TIM5 cannot be used because already used by the us_ticker
+static const PinMap PinMap_PWM[] = {
+    {PA_0,  PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1
+//  {PA_0,  PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH1
+    {PA_1,  PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2
+//  {PA_1,  PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH2
+    {PA_2,  PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3
+//  {PA_2,  PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH3
+//  {PA_2,  PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1
+    {PA_3,  PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4
+//  {PA_3,  PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH4
+//  {PA_3,  PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2
+    {PA_5,  PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1
+    {PA_6,  PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1
+    {PA_7,  PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N
+//  {PA_7,  PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2
+    {PA_8,  PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1
+    {PA_9,  PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2
+    {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3
+    {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH4
+    {PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1
+
+    {PB_0,  PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)},  // TIM1_CH2N
+//  {PB_0,  PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH3
+    {PB_1,  PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)},  // TIM1_CH3N
+//  {PB_1,  PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH4
+    {PB_3,  PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH2
+    {PB_4,  PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH1
+    {PB_5,  PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH2
+    {PB_6,  PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)},  // TIM4_CH1
+    {PB_7,  PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)},  // TIM4_CH2
+    {PB_8,  PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)},  // TIM4_CH3
+//  {PB_8,  PWM_10,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1
+    {PB_9,  PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)},  // TIM4_CH4
+//  {PB_9,  PWM_11,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1
+    {PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH3
+    {PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)},  // TIM1_CH1N
+    {PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)},  // TIM1_CH2N
+    {PB_15, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)},  // TIM1_CH3N
+
+    {PC_6,  PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH1
+    {PC_7,  PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH2
+    {PC_8,  PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH3
+    {PC_9,  PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH4
+
+    {NC,    NC,    0}
+};
+
+static TIM_HandleTypeDef TimHandle;
+
+void pwmout_init(pwmout_t* obj, PinName pin) {
+    // Get the peripheral name from the pin and assign it to the object
+    obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+
+    if (obj->pwm == (PWMName)NC) {
+        error("PWM error: pinout mapping failed.");
+    }
+
+    // Enable TIM clock
+    if (obj->pwm == PWM_1) __TIM1_CLK_ENABLE();
+    if (obj->pwm == PWM_2) __TIM2_CLK_ENABLE();
+    if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE();
+    if (obj->pwm == PWM_4) __TIM4_CLK_ENABLE();
+    if (obj->pwm == PWM_9) __TIM9_CLK_ENABLE();
+    if (obj->pwm == PWM_10) __TIM10_CLK_ENABLE();
+    if (obj->pwm == PWM_11) __TIM11_CLK_ENABLE();
+
+    // Configure GPIO
+    pinmap_pinout(pin, PinMap_PWM);
+
+    obj->pin = pin;
+    obj->period = 0;
+    obj->pulse = 0;
+
+    pwmout_period_us(obj, 20000); // 20 ms per default
+}
+
+void pwmout_free(pwmout_t* obj) {
+    // Configure GPIO
+    pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+}
+
+void pwmout_write(pwmout_t* obj, float value) {
+    TIM_OC_InitTypeDef sConfig;
+    int channel = 0;
+    int complementary_channel = 0;
+
+    TimHandle.Instance = (TIM_TypeDef *)(obj->pwm);
+
+    if (value < (float)0.0) {
+        value = 0.0;
+    } else if (value > (float)1.0) {
+        value = 1.0;
+    }
+
+    obj->pulse = (uint32_t)((float)obj->period * value);
+
+    // Configure channels
+    sConfig.OCMode       = TIM_OCMODE_PWM1;
+    sConfig.Pulse        = obj->pulse;
+    sConfig.OCPolarity   = TIM_OCPOLARITY_HIGH;
+    sConfig.OCNPolarity  = TIM_OCNPOLARITY_HIGH;
+    sConfig.OCFastMode   = TIM_OCFAST_DISABLE;
+    sConfig.OCIdleState  = TIM_OCIDLESTATE_RESET;
+    sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+
+    switch (obj->pin) {
+
+        // Channels 1
+        case PA_0:
+        case PA_5:
+        case PA_6:
+        case PA_8:
+        case PA_15:
+        case PB_4:
+        case PB_6:
+        case PC_6:
+            channel = TIM_CHANNEL_1;
+            break;
+
+        // Channels 1N
+        case PA_7:
+        case PB_13:
+            channel = TIM_CHANNEL_1;
+            complementary_channel = 1;
+            break;
+
+        // Channels 2
+        case PA_1:
+        case PA_9:
+        case PB_3:
+        case PB_5:
+        case PB_7:
+        case PC_7:
+            channel = TIM_CHANNEL_2;
+            break;
+
+        // Channels 2N
+        case PB_0:
+        case PB_14:
+            channel = TIM_CHANNEL_2;
+            complementary_channel = 1;
+            break;
+
+        // Channels 3
+        case PA_2:
+        case PA_10:
+        case PB_8:
+        case PB_10:
+        case PC_8:
+            channel = TIM_CHANNEL_3;
+            break;
+
+        // Channels 3N
+        case PB_1:
+        case PB_15:
+            channel = TIM_CHANNEL_3;
+            complementary_channel = 1;
+            break;
+
+        // Channels 4
+        case PA_3:
+        case PA_11:
+        case PB_9:
+        case PC_9:
+            channel = TIM_CHANNEL_4;
+            break;
+
+        default:
+            return;
+    }
+
+    HAL_TIM_PWM_ConfigChannel(&TimHandle, &sConfig, channel);
+    if (complementary_channel) {
+        HAL_TIMEx_PWMN_Start(&TimHandle, channel);
+    } else {
+        HAL_TIM_PWM_Start(&TimHandle, channel);
+    }
+}
+
+float pwmout_read(pwmout_t* obj) {
+    float value = 0;
+    if (obj->period > 0) {
+        value = (float)(obj->pulse) / (float)(obj->period);
+    }
+    return ((value > (float)1.0) ? (float)(1.0) : (value));
+}
+
+void pwmout_period(pwmout_t* obj, float seconds) {
+    pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms) {
+    pwmout_period_us(obj, ms * 1000);
+}
+
+void pwmout_period_us(pwmout_t* obj, int us) {
+    TimHandle.Instance = (TIM_TypeDef *)(obj->pwm);
+
+    float dc = pwmout_read(obj);
+
+    __HAL_TIM_DISABLE(&TimHandle);
+
+    // Update the SystemCoreClock variable
+    SystemCoreClockUpdate();
+
+    TimHandle.Init.Period        = us - 1;
+    TimHandle.Init.Prescaler     = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
+    TimHandle.Init.ClockDivision = 0;
+    TimHandle.Init.CounterMode   = TIM_COUNTERMODE_UP;
+    HAL_TIM_PWM_Init(&TimHandle);
+
+    // Set duty cycle again
+    pwmout_write(obj, dc);
+
+    // Save for future use
+    obj->period = us;
+
+    __HAL_TIM_ENABLE(&TimHandle);
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+    pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+    float value = (float)us / (float)obj->period;
+    pwmout_write(obj, value);
+}
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/rtc_api.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,199 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "rtc_api.h"
+
+#if DEVICE_RTC
+
+#include "mbed_error.h"
+
+static int rtc_inited = 0;
+
+static RTC_HandleTypeDef RtcHandle;
+
+void rtc_init(void) {
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    uint32_t rtc_freq = 0;
+
+    if (rtc_inited) return;
+    rtc_inited = 1;
+
+    RtcHandle.Instance = RTC;
+
+    // Enable Power clock
+    __PWR_CLK_ENABLE();
+
+    // Enable access to Backup domain
+    HAL_PWR_EnableBkUpAccess();
+
+    // Reset Backup domain
+    __HAL_RCC_BACKUPRESET_FORCE();
+    __HAL_RCC_BACKUPRESET_RELEASE();
+
+    // Enable LSE Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; /* Mandatory, otherwise the PLL is reconfigured! */
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; /* External 32.768 kHz clock on OSC_IN/OSC_OUT */
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        // Connect LSE to RTC
+        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
+        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
+        rtc_freq = LSE_VALUE;
+    } else {
+        // Enable LSI clock
+        RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
+        RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+        RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
+        RCC_OscInitStruct.LSIState       = RCC_LSI_ON;
+        if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+            error("RTC error: LSI clock initialization failed.");
+        }
+        // Connect LSI to RTC
+        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
+        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
+        // [TODO] This value is LSI typical value. To be measured precisely using a timer input capture
+        rtc_freq = 32000;
+    }
+
+    // Enable RTC
+    __HAL_RCC_RTC_ENABLE();
+
+    RtcHandle.Init.HourFormat     = RTC_HOURFORMAT_24;
+    RtcHandle.Init.AsynchPrediv   = 127;
+    RtcHandle.Init.SynchPrediv    = (rtc_freq / 128) - 1;
+    RtcHandle.Init.OutPut         = RTC_OUTPUT_DISABLE;
+    RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+    RtcHandle.Init.OutPutType     = RTC_OUTPUT_TYPE_OPENDRAIN;
+
+    if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
+        error("RTC error: RTC initialization failed.");
+    }
+}
+
+void rtc_free(void) {
+    // Enable Power clock
+    __PWR_CLK_ENABLE();
+
+    // Enable access to Backup domain
+    HAL_PWR_EnableBkUpAccess();
+
+    // Reset Backup domain
+    __HAL_RCC_BACKUPRESET_FORCE();
+    __HAL_RCC_BACKUPRESET_RELEASE();
+
+    // Disable access to Backup domain
+    HAL_PWR_DisableBkUpAccess();
+
+    // Disable LSI and LSE clocks
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE;
+    RCC_OscInitStruct.LSIState       = RCC_LSI_OFF;
+    RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    rtc_inited = 0;
+}
+
+int rtc_isenabled(void) {
+    return rtc_inited;
+}
+
+/*
+ RTC Registers
+   RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday
+   RTC_Month   1=january, 2=february, ..., 12=december
+   RTC_Date    day of the month 1-31
+   RTC_Year    year 0-99
+ struct tm
+   tm_sec      seconds after the minute 0-61
+   tm_min      minutes after the hour 0-59
+   tm_hour     hours since midnight 0-23
+   tm_mday     day of the month 1-31
+   tm_mon      months since January 0-11
+   tm_year     years since 1900
+   tm_wday     days since Sunday 0-6
+   tm_yday     days since January 1 0-365
+   tm_isdst    Daylight Saving Time flag
+*/
+time_t rtc_read(void) {
+    RTC_DateTypeDef dateStruct;
+    RTC_TimeTypeDef timeStruct;
+    struct tm timeinfo;
+
+    RtcHandle.Instance = RTC;
+
+    // Read actual date and time
+    // Warning: the time must be read first!
+    HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
+    HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
+
+    // Setup a tm structure based on the RTC
+    timeinfo.tm_wday = dateStruct.WeekDay;
+    timeinfo.tm_mon  = dateStruct.Month - 1;
+    timeinfo.tm_mday = dateStruct.Date;
+    timeinfo.tm_year = dateStruct.Year + 100;
+    timeinfo.tm_hour = timeStruct.Hours;
+    timeinfo.tm_min  = timeStruct.Minutes;
+    timeinfo.tm_sec  = timeStruct.Seconds;
+
+    // Convert to timestamp
+    time_t t = mktime(&timeinfo);
+
+    return t;
+}
+
+void rtc_write(time_t t) {
+    RTC_DateTypeDef dateStruct;
+    RTC_TimeTypeDef timeStruct;
+
+    RtcHandle.Instance = RTC;
+
+    // Convert the time into a tm
+    struct tm *timeinfo = localtime(&t);
+
+    // Fill RTC structures
+    dateStruct.WeekDay        = timeinfo->tm_wday;
+    dateStruct.Month          = timeinfo->tm_mon + 1;
+    dateStruct.Date           = timeinfo->tm_mday;
+    dateStruct.Year           = timeinfo->tm_year - 100;
+    timeStruct.Hours          = timeinfo->tm_hour;
+    timeStruct.Minutes        = timeinfo->tm_min;
+    timeStruct.Seconds        = timeinfo->tm_sec;
+    timeStruct.TimeFormat     = RTC_HOURFORMAT12_PM;
+    timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
+    timeStruct.StoreOperation = RTC_STOREOPERATION_RESET;
+
+    // Change the RTC current date/time
+    HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
+    HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
+}
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/serial_api.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,331 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "serial_api.h"
+
+#if DEVICE_SERIAL
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include <string.h>
+
+static const PinMap PinMap_UART_TX[] = {
+    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PC_6,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {NC,    NC,     0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PC_7,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {NC,    NC,     0}
+};
+
+#define UART_NUM (3)
+
+static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0};
+
+static uart_irq_handler irq_handler;
+
+UART_HandleTypeDef UartHandle;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+static void init_uart(serial_t *obj) {
+    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+
+    UartHandle.Init.BaudRate   = obj->baudrate;
+    UartHandle.Init.WordLength = obj->databits;
+    UartHandle.Init.StopBits   = obj->stopbits;
+    UartHandle.Init.Parity     = obj->parity;
+    UartHandle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
+
+    if (obj->pin_rx == NC) {
+        UartHandle.Init.Mode = UART_MODE_TX;
+    } else if (obj->pin_tx == NC) {
+        UartHandle.Init.Mode = UART_MODE_RX;
+    } else {
+        UartHandle.Init.Mode = UART_MODE_TX_RX;
+    }
+
+    HAL_UART_Init(&UartHandle);
+}
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+    // Determine the UART to use (UART_1, UART_2, ...)
+    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+
+    // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
+    obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+    MBED_ASSERT(obj->uart != (UARTName)NC);
+
+    // Enable USART clock
+    if (obj->uart == UART_1) {
+        __USART1_CLK_ENABLE();
+        obj->index = 0;
+    }
+    if (obj->uart == UART_2) {
+        __USART2_CLK_ENABLE();
+        obj->index = 1;
+    }
+    if (obj->uart == UART_6) {
+        __USART6_CLK_ENABLE();
+        obj->index = 2;
+    }
+
+    // Configure the UART pins
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+    pin_mode(tx, PullUp);
+    pin_mode(rx, PullUp);
+
+    // Configure UART
+    obj->baudrate = 9600;
+    obj->databits = UART_WORDLENGTH_8B;
+    obj->stopbits = UART_STOPBITS_1;
+    obj->parity   = UART_PARITY_NONE;
+
+    obj->pin_tx = tx;
+    obj->pin_rx = rx;
+
+    init_uart(obj);
+
+    // For stdio management
+    if (obj->uart == STDIO_UART) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+
+}
+
+void serial_free(serial_t *obj) {
+    // Reset UART and disable clock
+    if (obj->uart == UART_1) {
+        __USART1_FORCE_RESET();
+        __USART1_RELEASE_RESET();
+        __USART1_CLK_DISABLE();
+    }
+    if (obj->uart == UART_2) {
+        __USART2_FORCE_RESET();
+        __USART2_RELEASE_RESET();
+        __USART2_CLK_DISABLE();
+    }
+    if (obj->uart == UART_6) {
+        __USART6_FORCE_RESET();
+        __USART6_RELEASE_RESET();
+        __USART6_CLK_DISABLE();
+    }
+
+    // Configure GPIOs
+    pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+
+    serial_irq_ids[obj->index] = 0;
+}
+
+void serial_baud(serial_t *obj, int baudrate) {
+    obj->baudrate = baudrate;
+    init_uart(obj);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+    if (data_bits == 9) {
+        obj->databits = UART_WORDLENGTH_9B;
+    } else {
+        obj->databits = UART_WORDLENGTH_8B;
+    }
+
+    switch (parity) {
+        case ParityOdd:
+        case ParityForced0:
+            obj->parity = UART_PARITY_ODD;
+            break;
+        case ParityEven:
+        case ParityForced1:
+            obj->parity = UART_PARITY_EVEN;
+            break;
+        default: // ParityNone
+            obj->parity = UART_PARITY_NONE;
+            break;
+    }
+
+    if (stop_bits == 2) {
+        obj->stopbits = UART_STOPBITS_2;
+    } else {
+        obj->stopbits = UART_STOPBITS_1;
+    }
+
+    init_uart(obj);
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+
+static void uart_irq(UARTName name, int id) {
+    UartHandle.Instance = (USART_TypeDef *)name;
+    if (serial_irq_ids[id] != 0) {
+        if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) {
+            irq_handler(serial_irq_ids[id], TxIrq);
+            __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_TC);
+        }
+        if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) {
+            irq_handler(serial_irq_ids[id], RxIrq);
+            __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_RXNE);
+        }
+    }
+}
+
+static void uart1_irq(void) {
+    uart_irq(UART_1, 0);
+}
+static void uart2_irq(void) {
+    uart_irq(UART_2, 1);
+}
+static void uart6_irq(void) {
+    uart_irq(UART_6, 2);
+}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+    irq_handler = handler;
+    serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+    IRQn_Type irq_n = (IRQn_Type)0;
+    uint32_t vector = 0;
+
+    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+
+    if (obj->uart == UART_1) {
+        irq_n = USART1_IRQn;
+        vector = (uint32_t)&uart1_irq;
+    }
+
+    if (obj->uart == UART_2) {
+        irq_n = USART2_IRQn;
+        vector = (uint32_t)&uart2_irq;
+    }
+
+    if (obj->uart == UART_6) {
+        irq_n = USART6_IRQn;
+        vector = (uint32_t)&uart6_irq;
+    }
+
+    if (enable) {
+
+        if (irq == RxIrq) {
+            __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE);
+        } else { // TxIrq
+            __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC);
+        }
+
+        NVIC_SetVector(irq_n, vector);
+        NVIC_EnableIRQ(irq_n);
+
+    } else { // disable
+
+        int all_disabled = 0;
+
+        if (irq == RxIrq) {
+            __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE);
+            // Check if TxIrq is disabled too
+            if ((UartHandle.Instance->CR1 & USART_CR1_TXEIE) == 0) all_disabled = 1;
+        } else { // TxIrq
+            __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TXE);
+            // Check if RxIrq is disabled too
+            if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;
+        }
+
+        if (all_disabled) NVIC_DisableIRQ(irq_n);
+
+    }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+
+int serial_getc(serial_t *obj) {
+    USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
+    while (!serial_readable(obj));
+    return (int)(uart->DR & 0x1FF);
+}
+
+void serial_putc(serial_t *obj, int c) {
+    USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
+    while (!serial_writable(obj));
+    uart->DR = (uint32_t)(c & 0x1FF);
+}
+
+int serial_readable(serial_t *obj) {
+    int status;
+    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+    // Check if data is received
+    status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0);
+    return status;
+}
+
+int serial_writable(serial_t *obj) {
+    int status;
+    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+    // Check if data is transmitted
+    status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0);
+    return status;
+}
+
+void serial_clear(serial_t *obj) {
+    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+    __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_TXE);
+    __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_RXNE);
+}
+
+void serial_pinout_tx(PinName tx) {
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+    HAL_LIN_SendBreak(&UartHandle);
+}
+
+void serial_break_clear(serial_t *obj) {
+}
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/sleep.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,60 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "sleep_api.h"
+
+#if DEVICE_SLEEP
+
+#include "cmsis.h"
+
+static TIM_HandleTypeDef TimMasterHandle;
+
+void sleep(void) {
+    TimMasterHandle.Instance = TIM5;
+
+    // Disable HAL tick interrupt
+    __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+
+    // Request to enter SLEEP mode
+    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+
+    // Enable HAL tick interrupt
+    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+}
+
+void deepsleep(void) {
+    // Request to enter STOP mode with regulator in low power mode
+    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+
+    // After wake-up from STOP reconfigure the PLL
+    SetSysClock();
+}
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/spi_api.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,303 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "spi_api.h"
+
+#if DEVICE_SPI
+
+#include <math.h>
+#include "cmsis.h"
+#include "pinmap.h"
+
+static const PinMap PinMap_SPI_MOSI[] = {
+    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+//  {PB_5,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_3,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+//  {PB_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_2,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+static const PinMap PinMap_SPI_SCLK[] = {
+    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+//  {PB_3,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+//  {PA_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+    {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+//  {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+    {PB_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+    {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+    {NC,    NC,    0}
+};
+
+static SPI_HandleTypeDef SpiHandle;
+
+static void init_spi(spi_t *obj) {
+    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
+
+    __HAL_SPI_DISABLE(&SpiHandle);
+
+    SpiHandle.Init.Mode              = obj->mode;
+    SpiHandle.Init.BaudRatePrescaler = obj->br_presc;
+    SpiHandle.Init.Direction         = SPI_DIRECTION_2LINES;
+    SpiHandle.Init.CLKPhase          = obj->cpha;
+    SpiHandle.Init.CLKPolarity       = obj->cpol;
+    SpiHandle.Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLED;
+    SpiHandle.Init.CRCPolynomial     = 7;
+    SpiHandle.Init.DataSize          = obj->bits;
+    SpiHandle.Init.FirstBit          = SPI_FIRSTBIT_MSB;
+    SpiHandle.Init.NSS               = obj->nss;
+    SpiHandle.Init.TIMode            = SPI_TIMODE_DISABLED;
+
+    HAL_SPI_Init(&SpiHandle);
+
+    __HAL_SPI_ENABLE(&SpiHandle);
+}
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+    // Determine the SPI to use
+    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+
+    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+
+    obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
+    MBED_ASSERT(obj->spi != (SPIName)NC);
+
+    // Enable SPI clock
+    if (obj->spi == SPI_1) {
+        __SPI1_CLK_ENABLE();
+    }
+    if (obj->spi == SPI_2) {
+        __SPI2_CLK_ENABLE();
+    }
+    if (obj->spi == SPI_3) {
+        __SPI3_CLK_ENABLE();
+    }
+
+    // Configure the SPI pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+
+    // Save new values
+    obj->bits = SPI_DATASIZE_8BIT;
+    obj->cpol = SPI_POLARITY_LOW;
+    obj->cpha = SPI_PHASE_1EDGE;
+    obj->br_presc = SPI_BAUDRATEPRESCALER_256;
+
+    obj->pin_miso = miso;
+    obj->pin_mosi = mosi;
+    obj->pin_sclk = sclk;
+    obj->pin_ssel = ssel;
+
+    if (ssel == NC) { // SW NSS Master mode
+        obj->mode = SPI_MODE_MASTER;
+        obj->nss = SPI_NSS_SOFT;
+    } else { // Slave
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);
+        obj->mode = SPI_MODE_SLAVE;
+        obj->nss = SPI_NSS_HARD_INPUT;
+    }
+
+    init_spi(obj);
+}
+
+void spi_free(spi_t *obj) {
+    // Reset SPI and disable clock
+    if (obj->spi == SPI_1) {
+        __SPI1_FORCE_RESET();
+        __SPI1_RELEASE_RESET();
+        __SPI1_CLK_DISABLE();
+    }
+
+    if (obj->spi == SPI_2) {
+        __SPI2_FORCE_RESET();
+        __SPI2_RELEASE_RESET();
+        __SPI2_CLK_DISABLE();
+    }
+
+    if (obj->spi == SPI_3) {
+        __SPI3_FORCE_RESET();
+        __SPI3_RELEASE_RESET();
+        __SPI3_CLK_DISABLE();
+    }
+
+    // Configure GPIOs
+    pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+    // Save new values
+    if (bits == 16) {
+        obj->bits = SPI_DATASIZE_16BIT;
+    } else {
+        obj->bits = SPI_DATASIZE_8BIT;
+    }
+
+    switch (mode) {
+        case 0:
+            obj->cpol = SPI_POLARITY_LOW;
+            obj->cpha = SPI_PHASE_1EDGE;
+            break;
+        case 1:
+            obj->cpol = SPI_POLARITY_LOW;
+            obj->cpha = SPI_PHASE_2EDGE;
+            break;
+        case 2:
+            obj->cpol = SPI_POLARITY_HIGH;
+            obj->cpha = SPI_PHASE_1EDGE;
+            break;
+        default:
+            obj->cpol = SPI_POLARITY_HIGH;
+            obj->cpha = SPI_PHASE_2EDGE;
+            break;
+    }
+
+    if (slave == 0) {
+        obj->mode = SPI_MODE_MASTER;
+        obj->nss = SPI_NSS_SOFT;
+    } else {
+        obj->mode = SPI_MODE_SLAVE;
+        obj->nss = SPI_NSS_HARD_INPUT;
+    }
+
+    init_spi(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+    // Note: The frequencies are obtained with SPI1 clock = 84 MHz (APB2 clock)
+    if (hz < 600000) {
+        obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 330 kHz
+    } else if ((hz >= 600000) && (hz < 1000000)) {
+        obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 656 kHz
+    } else if ((hz >= 1000000) && (hz < 2000000)) {
+        obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 1.3 MHz
+    } else if ((hz >= 2000000) && (hz < 5000000)) {
+        obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 2.6 MHz
+    } else if ((hz >= 5000000) && (hz < 10000000)) {
+        obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 5.25 MHz
+    } else if ((hz >= 10000000) && (hz < 21000000)) {
+        obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 10.5 MHz
+    } else if ((hz >= 21000000) && (hz < 42000000)) {
+        obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 21 MHz
+    } else { // >= 42000000
+        obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 42 MHz
+    }
+    init_spi(obj);
+}
+
+static inline int ssp_readable(spi_t *obj) {
+    int status;
+    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
+    // Check if data is received
+    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
+    return status;
+}
+
+static inline int ssp_writeable(spi_t *obj) {
+    int status;
+    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
+    // Check if data is transmitted
+    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
+    return status;
+}
+
+static inline void ssp_write(spi_t *obj, int value) {
+    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+    while (!ssp_writeable(obj));
+    spi->DR = (uint16_t)value;
+}
+
+static inline int ssp_read(spi_t *obj) {
+    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+    while (!ssp_readable(obj));
+    return (int)spi->DR;
+}
+
+static inline int ssp_busy(spi_t *obj) {
+    int status;
+    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
+    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
+    return status;
+}
+
+int spi_master_write(spi_t *obj, int value) {
+    ssp_write(obj, value);
+    return ssp_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj) {
+    return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
+};
+
+int spi_slave_read(spi_t *obj) {
+    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+    while (!ssp_readable(obj));
+    return (int)spi->DR;
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+    while (!ssp_writeable(obj));
+    spi->DR = (uint16_t)value;
+}
+
+int spi_busy(spi_t *obj) {
+    return ssp_busy(obj);
+}
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/us_ticker.c	Wed Oct 08 11:00:24 2014 +0000
@@ -0,0 +1,65 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+
+#define TIM_MST TIM5
+
+static TIM_HandleTypeDef TimMasterHandle;
+static int us_ticker_inited = 0;
+
+void us_ticker_init(void) {
+    if (us_ticker_inited) return;
+    us_ticker_inited = 1;
+
+    TimMasterHandle.Instance = TIM_MST;
+
+    HAL_InitTick(0); // The passed value is not used  
+}
+
+uint32_t us_ticker_read() {
+    if (!us_ticker_inited) us_ticker_init();
+    return TIM_MST->CNT;
+}
+
+void us_ticker_set_interrupt(unsigned int timestamp) {
+    // Set new output compare value
+    __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, timestamp);
+    // Enable IT
+    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+}
+
+void us_ticker_disable_interrupt(void) {
+    __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+}
+
+void us_ticker_clear_interrupt(void) {
+    __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
+}
+