Norimasa Okamoto / Mbed 2 deprecated lpcterm2

semihost server example program

Dependencies:   SWD mbed USBLocalFileSystem BaseDAP USBDAP

/media/uploads/va009039/kl46z-lpc800-360x480.jpg

LPCXpresso
LPC11U68		LPCXpresso
LPC1549		FRDM-KL46ZEA LPC4088 QSB
app-board		LPC1768
app-board		LPC810LPC1114FN28
serverserverserverserverserverclientclient
SWDIOD12D12D12p25p21p4(P0_2)p12
SWCLKD10D10D10p26p22p3(P0_3)p3
nRESET
*option		D6D6D6p34p30p1(P0_5)p23
GNDGNDGNDGNDp1p1p7p22
3.3VP3V3P3V3P3V3p44p40p6p21
flash writeSW2(P0_1)SW3(P1_9)SW1p14
joystick
center		p14
joystick
center

client example:

Import programlpc810-semihost_helloworld

semihost client example program

Last commit 20 Feb 2014 by Norimasa Okamoto

Target2.cpp@18:5ed1759e863b, 2014-06-22 (annotated)

Committer:
va009039
Date:
Sun Jun 22 12:04:16 2014 +0000
Revision:
18:5ed1759e863b
Parent:
7:acfd2dbff157 
add LPC11U68 interface.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
va009039 18:5ed1759e863b 1 // Target2.cpp 2014/6/22
va009039 0:27d35fa263b5 2 #include "Target2.h"
va009039 0:27d35fa263b5 3 #include "mydebug.h"
va009039 0:27d35fa263b5 4
va009039 3:d7a7cde0bfb8 5 #define SYSMEMREMAP 0x40048000
va009039 3:d7a7cde0bfb8 6
va009039 2:32e9437348ad 7 #define CoreDebug_BASE (0xE000EDF0UL)
va009039 2:32e9437348ad 8 #define DHCSR (CoreDebug_BASE+0)
va009039 2:32e9437348ad 9 #define DCRSR (CoreDebug_BASE+4)
va009039 2:32e9437348ad 10 #define DCRDR (CoreDebug_BASE+8)
va009039 2:32e9437348ad 11 #define DEMCR (CoreDebug_BASE+12)
va009039 2:32e9437348ad 12
va009039 2:32e9437348ad 13 #define NVIC_AIRCR 0xE000ED0C
va009039 0:27d35fa263b5 14
va009039 4:5e4107edcbdb 15 // FPB (breakpoint)
va009039 4:5e4107edcbdb 16 #define FP_CTRL (0xE0002000)
va009039 4:5e4107edcbdb 17 #define FP_CTRL_KEY (1 << 1)
va009039 4:5e4107edcbdb 18 #define FP_COMP0 (0xE0002008)
va009039 4:5e4107edcbdb 19
va009039 5:2774358f5e4f 20 Target2::Target2(PinName swdio, PinName swclk, PinName reset)
va009039 7:acfd2dbff157 21 {
va009039 7:acfd2dbff157 22 _swd = new SWD(swdio, swclk, reset);
va009039 7:acfd2dbff157 23 inst();
va009039 7:acfd2dbff157 24 }
va009039 7:acfd2dbff157 25
va009039 7:acfd2dbff157 26 Target2::Target2(SWD* swd) : _swd(swd)
va009039 7:acfd2dbff157 27 {
va009039 7:acfd2dbff157 28 inst();
va009039 7:acfd2dbff157 29 }
va009039 7:acfd2dbff157 30
va009039 7:acfd2dbff157 31 void Target2::inst()
va009039 0:27d35fa263b5 32 {
va009039 0:27d35fa263b5 33 r0.setup(this, 0);
va009039 0:27d35fa263b5 34 r1.setup(this, 1);
va009039 0:27d35fa263b5 35 r2.setup(this, 2);
va009039 0:27d35fa263b5 36 r3.setup(this, 3);
va009039 0:27d35fa263b5 37 r4.setup(this, 4);
va009039 0:27d35fa263b5 38 r5.setup(this, 5);
va009039 0:27d35fa263b5 39 r6.setup(this, 6);
va009039 0:27d35fa263b5 40 r7.setup(this, 7);
va009039 0:27d35fa263b5 41 r8.setup(this, 8);
va009039 0:27d35fa263b5 42 r9.setup(this, 9);
va009039 0:27d35fa263b5 43 r10.setup(this, 10);
va009039 0:27d35fa263b5 44 r11.setup(this, 11);
va009039 0:27d35fa263b5 45 r12.setup(this, 12);
va009039 0:27d35fa263b5 46 sp.setup(this, 13);
va009039 0:27d35fa263b5 47 lr.setup(this, 14);
va009039 0:27d35fa263b5 48 pc.setup(this, 15);
va009039 0:27d35fa263b5 49 xpsr.setup(this, 16);
va009039 0:27d35fa263b5 50 }
va009039 0:27d35fa263b5 51
va009039 0:27d35fa263b5 52 bool Target2::setup()
va009039 0:27d35fa263b5 53 {
va009039 18:5ed1759e863b 54 TRACE();
va009039 7:acfd2dbff157 55 _swd->Setup();
va009039 5:2774358f5e4f 56 JTAG2SWD();
va009039 0:27d35fa263b5 57
va009039 0:27d35fa263b5 58 uint32_t data;
va009039 7:acfd2dbff157 59 uint8_t ack = _swd->Transfer(DP_IDCODE, &data);
va009039 0:27d35fa263b5 60 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 61 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 62 return false;
va009039 0:27d35fa263b5 63 }
va009039 3:d7a7cde0bfb8 64 idcode = data;
va009039 0:27d35fa263b5 65
va009039 0:27d35fa263b5 66 Abort();
va009039 0:27d35fa263b5 67
va009039 0:27d35fa263b5 68 data = 0x0;
va009039 7:acfd2dbff157 69 ack = _swd->Transfer(DP_SELECT, &data);
va009039 0:27d35fa263b5 70 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 71 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 72 return false;
va009039 0:27d35fa263b5 73 }
va009039 0:27d35fa263b5 74
va009039 7:acfd2dbff157 75 ack = _swd->Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 76 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 77 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 78 return false;
va009039 0:27d35fa263b5 79 }
va009039 0:27d35fa263b5 80
va009039 0:27d35fa263b5 81 data = CSYSPWRUPREQ | CDBGPWRUPREQ;
va009039 7:acfd2dbff157 82 ack = _swd->Transfer(DP_CTRL_STAT, &data);
va009039 0:27d35fa263b5 83 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 84 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 85 return false;
va009039 0:27d35fa263b5 86 }
va009039 0:27d35fa263b5 87
va009039 7:acfd2dbff157 88 ack = _swd->Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 89 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 90 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 91 return false;
va009039 0:27d35fa263b5 92 }
va009039 0:27d35fa263b5 93
va009039 7:acfd2dbff157 94 ack = _swd->Transfer(DP_CTRL_STAT_R, &data);
va009039 0:27d35fa263b5 95 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 96 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 97 return false;
va009039 0:27d35fa263b5 98 }
va009039 0:27d35fa263b5 99 TEST_ASSERT(data == 0xf0000040);
va009039 0:27d35fa263b5 100
va009039 0:27d35fa263b5 101 data = CSYSPWRUPREQ | CDBGPWRUPREQ | 0x04000000;
va009039 7:acfd2dbff157 102 ack = _swd->Transfer(DP_CTRL_STAT, &data);
va009039 0:27d35fa263b5 103 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 104 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 105 return false;
va009039 0:27d35fa263b5 106 }
va009039 0:27d35fa263b5 107
va009039 7:acfd2dbff157 108 ack = _swd->Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 109 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 110 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 111 return false;
va009039 0:27d35fa263b5 112 }
va009039 0:27d35fa263b5 113
va009039 0:27d35fa263b5 114 data = CSYSPWRUPREQ | CDBGPWRUPREQ | MASKLANE;
va009039 7:acfd2dbff157 115 ack = _swd->Transfer(DP_CTRL_STAT, &data);
va009039 0:27d35fa263b5 116 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 117 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 118 return false;
va009039 0:27d35fa263b5 119 }
va009039 0:27d35fa263b5 120
va009039 7:acfd2dbff157 121 ack = _swd->Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 122 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 123 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 124 return false;
va009039 0:27d35fa263b5 125 }
va009039 0:27d35fa263b5 126 return true;
va009039 0:27d35fa263b5 127 }
va009039 0:27d35fa263b5 128
va009039 6:5da6ad51a18f 129 void Target2::SWJClock(uint32_t clock_hz)
va009039 6:5da6ad51a18f 130 {
va009039 7:acfd2dbff157 131 _swd->SWJClock(clock_hz);
va009039 6:5da6ad51a18f 132 }
va009039 6:5da6ad51a18f 133
va009039 5:2774358f5e4f 134 void Target2::JTAG2SWD()
va009039 5:2774358f5e4f 135 {
va009039 5:2774358f5e4f 136 const uint8_t data1[] = {0xff,0xff,0xff,0xff,0xff,0xff,0xff};
va009039 5:2774358f5e4f 137 const uint8_t data2[] = {0x9e,0xe7};
va009039 5:2774358f5e4f 138 const uint8_t data3[] = {0x00};
va009039 7:acfd2dbff157 139 _swd->SWJSequence(sizeof(data1)*8, data1);
va009039 7:acfd2dbff157 140 _swd->SWJSequence(sizeof(data2)*8, data2);
va009039 7:acfd2dbff157 141 _swd->SWJSequence(sizeof(data1)*8, data1);
va009039 7:acfd2dbff157 142 _swd->SWJSequence(sizeof(data3)*8, data3);
va009039 5:2774358f5e4f 143 }
va009039 5:2774358f5e4f 144
va009039 3:d7a7cde0bfb8 145 void Target2::HardwareReset()
va009039 0:27d35fa263b5 146 {
va009039 7:acfd2dbff157 147 _swd->SWJPins(0x00, 0x80); // nReset off
va009039 7:acfd2dbff157 148 _swd->SWJPins(0x80, 0x80); // nReset on
va009039 3:d7a7cde0bfb8 149 }
va009039 3:d7a7cde0bfb8 150
va009039 3:d7a7cde0bfb8 151 void Target2::SoftwareReset()
va009039 3:d7a7cde0bfb8 152 {
va009039 18:5ed1759e863b 153 TRACE();
va009039 3:d7a7cde0bfb8 154 writeMemory(NVIC_AIRCR, 0x05fa0004);
va009039 0:27d35fa263b5 155 }
va009039 0:27d35fa263b5 156
va009039 0:27d35fa263b5 157 uint32_t Target2::readMemory(uint32_t addr)
va009039 0:27d35fa263b5 158 {
va009039 18:5ed1759e863b 159 TRACE1(addr);
va009039 0:27d35fa263b5 160 _setaddr(addr);
va009039 0:27d35fa263b5 161
va009039 0:27d35fa263b5 162 uint32_t data;
va009039 7:acfd2dbff157 163 uint8_t ack = _swd->Transfer(AP_DRW_R, &data); // dummy read
va009039 18:5ed1759e863b 164 TRACE1(ack);
va009039 0:27d35fa263b5 165 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 166
va009039 7:acfd2dbff157 167 ack = _swd->Transfer(DP_RDBUFF, &data);
va009039 18:5ed1759e863b 168 TRACE1(ack);
va009039 0:27d35fa263b5 169 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 170 return data;
va009039 0:27d35fa263b5 171 }
va009039 0:27d35fa263b5 172
va009039 0:27d35fa263b5 173 void Target2::readMemory(uint32_t addr, uint32_t* data, int count)
va009039 0:27d35fa263b5 174 {
va009039 18:5ed1759e863b 175 TRACE1(addr);
va009039 0:27d35fa263b5 176 if (count == 0) {
va009039 0:27d35fa263b5 177 return;
va009039 0:27d35fa263b5 178 }
va009039 0:27d35fa263b5 179
va009039 0:27d35fa263b5 180 _setaddr(addr);
va009039 0:27d35fa263b5 181
va009039 7:acfd2dbff157 182 uint8_t ack = _swd->Transfer(AP_DRW_R, NULL); // dummy read
va009039 0:27d35fa263b5 183 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 184
va009039 0:27d35fa263b5 185 for(int i = 0; i < count-1; i++) {
va009039 7:acfd2dbff157 186 ack = _swd->Transfer(AP_DRW_R, data++);
va009039 0:27d35fa263b5 187 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 188 }
va009039 7:acfd2dbff157 189 ack = _swd->Transfer(DP_RDBUFF, data);
va009039 0:27d35fa263b5 190 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 191 }
va009039 0:27d35fa263b5 192
va009039 0:27d35fa263b5 193 void Target2::writeMemory(uint32_t addr, uint32_t data)
va009039 0:27d35fa263b5 194 {
va009039 0:27d35fa263b5 195 writeMemory(addr, &data, 1);
va009039 0:27d35fa263b5 196 }
va009039 0:27d35fa263b5 197
va009039 0:27d35fa263b5 198 void Target2::writeMemory(uint32_t addr, uint32_t* data, int count)
va009039 0:27d35fa263b5 199 {
va009039 0:27d35fa263b5 200 _setaddr(addr);
va009039 0:27d35fa263b5 201
va009039 0:27d35fa263b5 202 while(count-- > 0) {
va009039 7:acfd2dbff157 203 uint8_t ack = _swd->Transfer(AP_DRW_W, data);
va009039 0:27d35fa263b5 204 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 205 data++;
va009039 0:27d35fa263b5 206 }
va009039 0:27d35fa263b5 207 }
va009039 0:27d35fa263b5 208
va009039 1:eb30547ba84d 209 uint8_t Target2::readMemory8(uint32_t addr)
va009039 1:eb30547ba84d 210 {
va009039 18:5ed1759e863b 211 TRACE1(addr);
va009039 1:eb30547ba84d 212 _setaddr8(addr);
va009039 1:eb30547ba84d 213
va009039 1:eb30547ba84d 214 uint32_t data32;
va009039 7:acfd2dbff157 215 uint8_t ack = _swd->Transfer(AP_DRW_R, &data32); // dummy read
va009039 1:eb30547ba84d 216 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 217
va009039 7:acfd2dbff157 218 ack = _swd->Transfer(DP_RDBUFF, &data32);
va009039 1:eb30547ba84d 219 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 220 return (data32 >> ((addr & 0x03) << 3)) & 0xff;
va009039 1:eb30547ba84d 221 }
va009039 1:eb30547ba84d 222
va009039 1:eb30547ba84d 223 void Target2::writeMemory8(uint32_t addr, uint8_t data)
va009039 1:eb30547ba84d 224 {
va009039 1:eb30547ba84d 225 _setaddr8(addr);
va009039 1:eb30547ba84d 226
va009039 1:eb30547ba84d 227 uint32_t data32 = data;
va009039 1:eb30547ba84d 228 data32 <<= ((addr & 0x03) << 3);
va009039 7:acfd2dbff157 229 uint8_t ack = _swd->Transfer(AP_DRW_W, &data32);
va009039 1:eb30547ba84d 230 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 231 }
va009039 1:eb30547ba84d 232
va009039 0:27d35fa263b5 233 void Target2::_setaddr(uint32_t addr)
va009039 0:27d35fa263b5 234 {
va009039 18:5ed1759e863b 235 TRACE1(addr);
va009039 0:27d35fa263b5 236 uint32_t ctl = CSW_VALUE|CSW_SIZE32;
va009039 7:acfd2dbff157 237 uint8_t ack = _swd->Transfer(AP_CSW, &ctl);
va009039 18:5ed1759e863b 238 TRACE1(ack);
va009039 0:27d35fa263b5 239 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 240
va009039 7:acfd2dbff157 241 ack = _swd->Transfer(DP_RDBUFF, NULL);
va009039 18:5ed1759e863b 242 TRACE1(ack);
va009039 0:27d35fa263b5 243 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 244
va009039 7:acfd2dbff157 245 ack = _swd->Transfer(AP_TAR, &addr);
va009039 18:5ed1759e863b 246 TRACE1(ack);
va009039 0:27d35fa263b5 247 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 248
va009039 7:acfd2dbff157 249 ack = _swd->Transfer(DP_RDBUFF, NULL);
va009039 18:5ed1759e863b 250 TRACE1(ack);
va009039 0:27d35fa263b5 251 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 252 }
va009039 0:27d35fa263b5 253
va009039 1:eb30547ba84d 254 void Target2::_setaddr8(uint32_t addr)
va009039 1:eb30547ba84d 255 {
va009039 18:5ed1759e863b 256 TRACE1(addr);
va009039 1:eb30547ba84d 257 uint32_t ctl = CSW_VALUE|CSW_SIZE8;
va009039 7:acfd2dbff157 258 uint8_t ack = _swd->Transfer(AP_CSW, &ctl);
va009039 1:eb30547ba84d 259 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 260
va009039 7:acfd2dbff157 261 ack = _swd->Transfer(DP_RDBUFF, NULL);
va009039 1:eb30547ba84d 262 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 263
va009039 7:acfd2dbff157 264 ack = _swd->Transfer(AP_TAR, &addr);
va009039 1:eb30547ba84d 265 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 266
va009039 7:acfd2dbff157 267 ack = _swd->Transfer(DP_RDBUFF, NULL);
va009039 1:eb30547ba84d 268 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 269 }
va009039 1:eb30547ba84d 270
va009039 0:27d35fa263b5 271 void Target2::Abort()
va009039 0:27d35fa263b5 272 {
va009039 0:27d35fa263b5 273 uint32_t data = 0x1e;
va009039 7:acfd2dbff157 274 uint8_t ack = _swd->Transfer(DP_ABORT, &data);
va009039 0:27d35fa263b5 275 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 276 }
va009039 0:27d35fa263b5 277
va009039 0:27d35fa263b5 278 int Target2::getStatus()
va009039 0:27d35fa263b5 279 {
va009039 18:5ed1759e863b 280 TRACE();
va009039 0:27d35fa263b5 281 return readMemory(DHCSR) & 6 ? TARGET_HALTED : TARGET_RUNNING;
va009039 0:27d35fa263b5 282 }
va009039 0:27d35fa263b5 283
va009039 0:27d35fa263b5 284 bool Target2::wait_status(int status, int timeout_ms)
va009039 0:27d35fa263b5 285 {
va009039 18:5ed1759e863b 286 TRACE1(status);
va009039 0:27d35fa263b5 287 Timer t;
va009039 0:27d35fa263b5 288 t.reset();
va009039 0:27d35fa263b5 289 t.start();
va009039 0:27d35fa263b5 290 while(t.read_ms() < timeout_ms) {
va009039 0:27d35fa263b5 291 if (getStatus() == status) {
va009039 0:27d35fa263b5 292 return true;
va009039 0:27d35fa263b5 293 }
va009039 0:27d35fa263b5 294 }
va009039 0:27d35fa263b5 295 return false;
va009039 0:27d35fa263b5 296 }
va009039 0:27d35fa263b5 297
va009039 4:5e4107edcbdb 298 bool Target2::prog_status()
va009039 4:5e4107edcbdb 299 {
va009039 18:5ed1759e863b 300 TRACE();
va009039 4:5e4107edcbdb 301 writeMemory(DEMCR, 1);
va009039 4:5e4107edcbdb 302 int status = getStatus();
va009039 4:5e4107edcbdb 303 TEST_ASSERT(status == TARGET_HALTED);
va009039 4:5e4107edcbdb 304 if (status == TARGET_RUNNING) {
va009039 4:5e4107edcbdb 305 halt();
va009039 4:5e4107edcbdb 306 }
va009039 4:5e4107edcbdb 307 bool st = wait_status(TARGET_HALTED);
va009039 4:5e4107edcbdb 308 TEST_ASSERT(st == true);
va009039 4:5e4107edcbdb 309 writeMemory(DEMCR, 0);
va009039 4:5e4107edcbdb 310 writeMemory(SYSMEMREMAP, 2); // user flash page
va009039 4:5e4107edcbdb 311 uint32_t reset_handler = readMemory(4);
va009039 6:5da6ad51a18f 312 if (setBreakpoint0(reset_handler)) {
va009039 6:5da6ad51a18f 313 writeMemory(NVIC_AIRCR, 0x05fa0004); // SYSRESETREQ software reset
va009039 6:5da6ad51a18f 314 st = wait_status(TARGET_HALTED);
va009039 6:5da6ad51a18f 315 TEST_ASSERT(st == true);
va009039 6:5da6ad51a18f 316 TEST_ASSERT((reset_handler&0xfffffffe) == pc);
va009039 6:5da6ad51a18f 317 removeBreakpoint0(0);
va009039 6:5da6ad51a18f 318 }
va009039 4:5e4107edcbdb 319 return true;
va009039 4:5e4107edcbdb 320 }
va009039 4:5e4107edcbdb 321
va009039 6:5da6ad51a18f 322 bool Target2::setBreakpoint0(uint32_t addr)
va009039 4:5e4107edcbdb 323 {
va009039 18:5ed1759e863b 324 TRACE1(addr);
va009039 6:5da6ad51a18f 325 if ((addr&1) == 0 || addr >= 0x20000000) {
va009039 6:5da6ad51a18f 326 return false;
va009039 6:5da6ad51a18f 327 }
va009039 6:5da6ad51a18f 328 uint32_t data = (addr&0x1ffffffc) | 0xc0000001;
va009039 6:5da6ad51a18f 329 if (addr&0x00000002) {
va009039 6:5da6ad51a18f 330 data |= 0x80000000;
va009039 4:5e4107edcbdb 331 } else {
va009039 6:5da6ad51a18f 332 data |= 0x40000000;
va009039 4:5e4107edcbdb 333 }
va009039 6:5da6ad51a18f 334 writeMemory(FP_COMP0, data); // set breakpoint
va009039 6:5da6ad51a18f 335 writeMemory(FP_CTRL, 3); // enable FPB
va009039 6:5da6ad51a18f 336 return true;
va009039 6:5da6ad51a18f 337 }
va009039 6:5da6ad51a18f 338
va009039 6:5da6ad51a18f 339 void Target2::removeBreakpoint0(uint32_t addr)
va009039 6:5da6ad51a18f 340 {
va009039 18:5ed1759e863b 341 TRACE1(addr);
va009039 6:5da6ad51a18f 342 writeMemory(FP_COMP0, 0); // breakpoint clear
va009039 6:5da6ad51a18f 343 writeMemory(FP_CTRL, 2); // desable FPB
va009039 4:5e4107edcbdb 344 }
va009039 4:5e4107edcbdb 345
va009039 0:27d35fa263b5 346 void Target2::halt()
va009039 0:27d35fa263b5 347 {
va009039 18:5ed1759e863b 348 TRACE();
va009039 0:27d35fa263b5 349 writeMemory(DHCSR, 0xa05f0003);
va009039 0:27d35fa263b5 350 }
va009039 0:27d35fa263b5 351
va009039 0:27d35fa263b5 352 void Target2::resume()
va009039 0:27d35fa263b5 353 {
va009039 18:5ed1759e863b 354 TRACE();
va009039 0:27d35fa263b5 355 writeMemory(DHCSR, 0xa05f0001);
va009039 0:27d35fa263b5 356 }
va009039 0:27d35fa263b5 357
va009039 1:eb30547ba84d 358 void Target2::step()
va009039 1:eb30547ba84d 359 {
va009039 18:5ed1759e863b 360 TRACE();
va009039 1:eb30547ba84d 361 writeMemory(DHCSR, 0xa05f0005);
va009039 1:eb30547ba84d 362 }
va009039 1:eb30547ba84d 363
va009039 0:27d35fa263b5 364 uint32_t CoreReg::read()
va009039 0:27d35fa263b5 365 {
va009039 0:27d35fa263b5 366 _target->writeMemory(DCRSR, _reg);
va009039 0:27d35fa263b5 367 return _target->readMemory(DCRDR);
va009039 0:27d35fa263b5 368 }
va009039 0:27d35fa263b5 369
va009039 0:27d35fa263b5 370 void CoreReg::write(uint32_t value)
va009039 0:27d35fa263b5 371 {
va009039 0:27d35fa263b5 372 _target->writeMemory(DCRDR, value);
va009039 0:27d35fa263b5 373 _target->writeMemory(DCRSR, _reg|0x10000);
va009039 0:27d35fa263b5 374 }
va009039 0:27d35fa263b5 375
va009039 0:27d35fa263b5 376 void CoreReg::setup(Target2* target, uint8_t reg)
va009039 0:27d35fa263b5 377 {
va009039 0:27d35fa263b5 378 _target = target;
va009039 0:27d35fa263b5 379 _reg = reg;
va009039 0:27d35fa263b5 380 }