Norimasa Okamoto / Mbed 2 deprecated lpcterm2

semihost server example program

Dependencies:   SWD mbed USBLocalFileSystem BaseDAP USBDAP

/media/uploads/va009039/kl46z-lpc800-360x480.jpg

LPCXpresso
LPC11U68		LPCXpresso
LPC1549		FRDM-KL46ZEA LPC4088 QSB
app-board		LPC1768
app-board		LPC810LPC1114FN28
serverserverserverserverserverclientclient
SWDIOD12D12D12p25p21p4(P0_2)p12
SWCLKD10D10D10p26p22p3(P0_3)p3
nRESET
*option		D6D6D6p34p30p1(P0_5)p23
GNDGNDGNDGNDp1p1p7p22
3.3VP3V3P3V3P3V3p44p40p6p21
flash writeSW2(P0_1)SW3(P1_9)SW1p14
joystick
center		p14
joystick
center

client example:

Import programlpc810-semihost_helloworld

semihost client example program

Last commit 20 Feb 2014 by Norimasa Okamoto

Target2.cpp@1:eb30547ba84d, 2013-09-02 (annotated)

Committer:
va009039
Date:
Mon Sep 02 17:33:08 2013 +0000
Revision:
1:eb30547ba84d
Parent:
0:27d35fa263b5
Child:
2:32e9437348ad
add semihost

Who changed what in which revision?

UserRevisionLine numberNew contents of line
va009039 1:eb30547ba84d 1 // Target2.cpp 2013/9/2
va009039 0:27d35fa263b5 2 #include "Target2.h"
va009039 0:27d35fa263b5 3 #include "mydebug.h"
va009039 0:27d35fa263b5 4
va009039 0:27d35fa263b5 5 #define DHCSR 0xe000edf0
va009039 0:27d35fa263b5 6 #define DCRSR (DHCSR+4)
va009039 0:27d35fa263b5 7 #define DCRDR (DHCSR+8)
va009039 0:27d35fa263b5 8
va009039 0:27d35fa263b5 9 Target2::Target2(PinName swdio, PinName swclk, PinName reset, Serial* usbpc)
va009039 0:27d35fa263b5 10 : _swd(swdio, swclk, reset), _pc(usbpc)
va009039 0:27d35fa263b5 11 {
va009039 0:27d35fa263b5 12 r0.setup(this, 0);
va009039 0:27d35fa263b5 13 r1.setup(this, 1);
va009039 0:27d35fa263b5 14 r2.setup(this, 2);
va009039 0:27d35fa263b5 15 r3.setup(this, 3);
va009039 0:27d35fa263b5 16 r4.setup(this, 4);
va009039 0:27d35fa263b5 17 r5.setup(this, 5);
va009039 0:27d35fa263b5 18 r6.setup(this, 6);
va009039 0:27d35fa263b5 19 r7.setup(this, 7);
va009039 0:27d35fa263b5 20 r8.setup(this, 8);
va009039 0:27d35fa263b5 21 r9.setup(this, 9);
va009039 0:27d35fa263b5 22 r10.setup(this, 10);
va009039 0:27d35fa263b5 23 r11.setup(this, 11);
va009039 0:27d35fa263b5 24 r12.setup(this, 12);
va009039 0:27d35fa263b5 25 sp.setup(this, 13);
va009039 0:27d35fa263b5 26 lr.setup(this, 14);
va009039 0:27d35fa263b5 27 pc.setup(this, 15);
va009039 0:27d35fa263b5 28 xpsr.setup(this, 16);
va009039 0:27d35fa263b5 29 }
va009039 0:27d35fa263b5 30
va009039 0:27d35fa263b5 31 bool Target2::setup()
va009039 0:27d35fa263b5 32 {
va009039 0:27d35fa263b5 33 _swd.Setup();
va009039 0:27d35fa263b5 34 _swd.JTAG2SWD();
va009039 0:27d35fa263b5 35
va009039 0:27d35fa263b5 36 uint32_t data;
va009039 0:27d35fa263b5 37 uint8_t ack = _swd.Transfer(DP_IDCODE, &data);
va009039 0:27d35fa263b5 38 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 39 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 40 return false;
va009039 0:27d35fa263b5 41 }
va009039 0:27d35fa263b5 42 TEST_ASSERT(data == 0x0bb11477);
va009039 0:27d35fa263b5 43
va009039 0:27d35fa263b5 44 Abort();
va009039 0:27d35fa263b5 45
va009039 0:27d35fa263b5 46 data = 0x0;
va009039 0:27d35fa263b5 47 ack = _swd.Transfer(DP_SELECT, &data);
va009039 0:27d35fa263b5 48 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 49 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 50 return false;
va009039 0:27d35fa263b5 51 }
va009039 0:27d35fa263b5 52
va009039 0:27d35fa263b5 53 ack = _swd.Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 54 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 55 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 56 return false;
va009039 0:27d35fa263b5 57 }
va009039 0:27d35fa263b5 58
va009039 0:27d35fa263b5 59 data = CSYSPWRUPREQ | CDBGPWRUPREQ;
va009039 0:27d35fa263b5 60 TEST_ASSERT(data == 0x50000000);
va009039 0:27d35fa263b5 61 ack = _swd.Transfer(DP_CTRL_STAT, &data);
va009039 0:27d35fa263b5 62 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 63 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 64 return false;
va009039 0:27d35fa263b5 65 }
va009039 0:27d35fa263b5 66
va009039 0:27d35fa263b5 67 ack = _swd.Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 68 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 69 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 70 return false;
va009039 0:27d35fa263b5 71 }
va009039 0:27d35fa263b5 72
va009039 0:27d35fa263b5 73 ack = _swd.Transfer(DP_CTRL_STAT_R, &data);
va009039 0:27d35fa263b5 74 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 75 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 76 return false;
va009039 0:27d35fa263b5 77 }
va009039 0:27d35fa263b5 78 TEST_ASSERT(data == 0xf0000040);
va009039 0:27d35fa263b5 79
va009039 0:27d35fa263b5 80 data = CSYSPWRUPREQ | CDBGPWRUPREQ | 0x04000000;
va009039 0:27d35fa263b5 81 TEST_ASSERT(data == 0x54000000);
va009039 0:27d35fa263b5 82 ack = _swd.Transfer(DP_CTRL_STAT, &data);
va009039 0:27d35fa263b5 83 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 84 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 85 return false;
va009039 0:27d35fa263b5 86 }
va009039 0:27d35fa263b5 87
va009039 0:27d35fa263b5 88 ack = _swd.Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 89 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 90 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 91 return false;
va009039 0:27d35fa263b5 92 }
va009039 0:27d35fa263b5 93
va009039 0:27d35fa263b5 94 data = CSYSPWRUPREQ | CDBGPWRUPREQ | MASKLANE;
va009039 0:27d35fa263b5 95 TEST_ASSERT(data == 0x50000f00);
va009039 0:27d35fa263b5 96 ack = _swd.Transfer(DP_CTRL_STAT, &data);
va009039 0:27d35fa263b5 97 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 98 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 99 return false;
va009039 0:27d35fa263b5 100 }
va009039 0:27d35fa263b5 101
va009039 0:27d35fa263b5 102 ack = _swd.Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 103 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 104 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 105 return false;
va009039 0:27d35fa263b5 106 }
va009039 0:27d35fa263b5 107 return true;
va009039 0:27d35fa263b5 108 }
va009039 0:27d35fa263b5 109
va009039 0:27d35fa263b5 110 void Target2::Reset()
va009039 0:27d35fa263b5 111 {
va009039 0:27d35fa263b5 112 _swd.reset();
va009039 0:27d35fa263b5 113 }
va009039 0:27d35fa263b5 114
va009039 0:27d35fa263b5 115 uint32_t Target2::readMemory(uint32_t addr)
va009039 0:27d35fa263b5 116 {
va009039 0:27d35fa263b5 117 _setaddr(addr);
va009039 0:27d35fa263b5 118
va009039 0:27d35fa263b5 119 uint32_t data;
va009039 0:27d35fa263b5 120 uint8_t ack = _swd.Transfer(AP_DRW_R, &data); // dummy read
va009039 0:27d35fa263b5 121 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 122
va009039 0:27d35fa263b5 123 ack = _swd.Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 124 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 125 return data;
va009039 0:27d35fa263b5 126 }
va009039 0:27d35fa263b5 127
va009039 0:27d35fa263b5 128 void Target2::readMemory(uint32_t addr, uint32_t* data, int count)
va009039 0:27d35fa263b5 129 {
va009039 0:27d35fa263b5 130 if (count == 0) {
va009039 0:27d35fa263b5 131 return;
va009039 0:27d35fa263b5 132 }
va009039 0:27d35fa263b5 133
va009039 0:27d35fa263b5 134 _setaddr(addr);
va009039 0:27d35fa263b5 135
va009039 0:27d35fa263b5 136 uint8_t ack = _swd.Transfer(AP_DRW_R, NULL); // dummy read
va009039 0:27d35fa263b5 137 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 138
va009039 0:27d35fa263b5 139 for(int i = 0; i < count-1; i++) {
va009039 0:27d35fa263b5 140 ack = _swd.Transfer(AP_DRW_R, data++);
va009039 0:27d35fa263b5 141 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 142 }
va009039 0:27d35fa263b5 143 ack = _swd.Transfer(DP_RDBUFF, data);
va009039 0:27d35fa263b5 144 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 145 }
va009039 0:27d35fa263b5 146
va009039 0:27d35fa263b5 147 void Target2::writeMemory(uint32_t addr, uint32_t data)
va009039 0:27d35fa263b5 148 {
va009039 0:27d35fa263b5 149 writeMemory(addr, &data, 1);
va009039 0:27d35fa263b5 150 }
va009039 0:27d35fa263b5 151
va009039 0:27d35fa263b5 152 void Target2::writeMemory(uint32_t addr, uint32_t* data, int count)
va009039 0:27d35fa263b5 153 {
va009039 0:27d35fa263b5 154 _setaddr(addr);
va009039 0:27d35fa263b5 155
va009039 0:27d35fa263b5 156 while(count-- > 0) {
va009039 0:27d35fa263b5 157 uint8_t ack = _swd.Transfer(AP_DRW_W, data);
va009039 0:27d35fa263b5 158 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 159 data++;
va009039 0:27d35fa263b5 160 }
va009039 0:27d35fa263b5 161 }
va009039 0:27d35fa263b5 162
va009039 1:eb30547ba84d 163 uint8_t Target2::readMemory8(uint32_t addr)
va009039 1:eb30547ba84d 164 {
va009039 1:eb30547ba84d 165 _setaddr8(addr);
va009039 1:eb30547ba84d 166
va009039 1:eb30547ba84d 167 uint32_t data32;
va009039 1:eb30547ba84d 168 uint8_t ack = _swd.Transfer(AP_DRW_R, &data32); // dummy read
va009039 1:eb30547ba84d 169 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 170
va009039 1:eb30547ba84d 171 ack = _swd.Transfer(DP_RDBUFF, &data32);
va009039 1:eb30547ba84d 172 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 173 return (data32 >> ((addr & 0x03) << 3)) & 0xff;
va009039 1:eb30547ba84d 174 }
va009039 1:eb30547ba84d 175
va009039 1:eb30547ba84d 176 void Target2::writeMemory8(uint32_t addr, uint8_t data)
va009039 1:eb30547ba84d 177 {
va009039 1:eb30547ba84d 178 _setaddr8(addr);
va009039 1:eb30547ba84d 179
va009039 1:eb30547ba84d 180 uint32_t data32 = data;
va009039 1:eb30547ba84d 181 data32 <<= ((addr & 0x03) << 3);
va009039 1:eb30547ba84d 182 uint8_t ack = _swd.Transfer(AP_DRW_W, &data32);
va009039 1:eb30547ba84d 183 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 184 }
va009039 1:eb30547ba84d 185
va009039 0:27d35fa263b5 186 void Target2::_setaddr(uint32_t addr)
va009039 0:27d35fa263b5 187 {
va009039 0:27d35fa263b5 188 uint32_t ctl = CSW_VALUE|CSW_SIZE32;
va009039 0:27d35fa263b5 189 TEST_ASSERT(ctl == 0x23000052);
va009039 0:27d35fa263b5 190 uint8_t ack = _swd.Transfer(AP_CSW, &ctl);
va009039 0:27d35fa263b5 191 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 192
va009039 0:27d35fa263b5 193 ack = _swd.Transfer(DP_RDBUFF, NULL);
va009039 0:27d35fa263b5 194 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 195
va009039 0:27d35fa263b5 196 ack = _swd.Transfer(AP_TAR, &addr);
va009039 0:27d35fa263b5 197 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 198
va009039 0:27d35fa263b5 199 ack = _swd.Transfer(DP_RDBUFF, NULL);
va009039 0:27d35fa263b5 200 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 201 }
va009039 0:27d35fa263b5 202
va009039 1:eb30547ba84d 203 void Target2::_setaddr8(uint32_t addr)
va009039 1:eb30547ba84d 204 {
va009039 1:eb30547ba84d 205 uint32_t ctl = CSW_VALUE|CSW_SIZE8;
va009039 1:eb30547ba84d 206 TEST_ASSERT(ctl == 0x23000050);
va009039 1:eb30547ba84d 207 uint8_t ack = _swd.Transfer(AP_CSW, &ctl);
va009039 1:eb30547ba84d 208 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 209
va009039 1:eb30547ba84d 210 ack = _swd.Transfer(DP_RDBUFF, NULL);
va009039 1:eb30547ba84d 211 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 212
va009039 1:eb30547ba84d 213 ack = _swd.Transfer(AP_TAR, &addr);
va009039 1:eb30547ba84d 214 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 215
va009039 1:eb30547ba84d 216 ack = _swd.Transfer(DP_RDBUFF, NULL);
va009039 1:eb30547ba84d 217 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 218 }
va009039 1:eb30547ba84d 219
va009039 0:27d35fa263b5 220 void Target2::Abort()
va009039 0:27d35fa263b5 221 {
va009039 0:27d35fa263b5 222 uint32_t data = 0x1e;
va009039 0:27d35fa263b5 223 uint8_t ack = _swd.Transfer(DP_ABORT, &data);
va009039 0:27d35fa263b5 224 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 225 }
va009039 0:27d35fa263b5 226
va009039 0:27d35fa263b5 227 int Target2::getStatus()
va009039 0:27d35fa263b5 228 {
va009039 0:27d35fa263b5 229 return readMemory(DHCSR) & 6 ? TARGET_HALTED : TARGET_RUNNING;
va009039 0:27d35fa263b5 230 }
va009039 0:27d35fa263b5 231
va009039 0:27d35fa263b5 232 bool Target2::wait_status(int status, int timeout_ms)
va009039 0:27d35fa263b5 233 {
va009039 0:27d35fa263b5 234 Timer t;
va009039 0:27d35fa263b5 235 t.reset();
va009039 0:27d35fa263b5 236 t.start();
va009039 0:27d35fa263b5 237 while(t.read_ms() < timeout_ms) {
va009039 0:27d35fa263b5 238 if (getStatus() == status) {
va009039 0:27d35fa263b5 239 return true;
va009039 0:27d35fa263b5 240 }
va009039 0:27d35fa263b5 241 }
va009039 0:27d35fa263b5 242 return false;
va009039 0:27d35fa263b5 243 }
va009039 0:27d35fa263b5 244
va009039 0:27d35fa263b5 245 void Target2::halt()
va009039 0:27d35fa263b5 246 {
va009039 0:27d35fa263b5 247 writeMemory(DHCSR, 0xa05f0003);
va009039 0:27d35fa263b5 248 }
va009039 0:27d35fa263b5 249
va009039 0:27d35fa263b5 250 void Target2::resume()
va009039 0:27d35fa263b5 251 {
va009039 0:27d35fa263b5 252 writeMemory(DHCSR, 0xa05f0001);
va009039 0:27d35fa263b5 253 }
va009039 0:27d35fa263b5 254
va009039 1:eb30547ba84d 255 void Target2::step()
va009039 1:eb30547ba84d 256 {
va009039 1:eb30547ba84d 257 writeMemory(DHCSR, 0xa05f0005);
va009039 1:eb30547ba84d 258 }
va009039 1:eb30547ba84d 259
va009039 0:27d35fa263b5 260 uint32_t CoreReg::read()
va009039 0:27d35fa263b5 261 {
va009039 0:27d35fa263b5 262 _target->writeMemory(DCRSR, _reg);
va009039 0:27d35fa263b5 263 return _target->readMemory(DCRDR);
va009039 0:27d35fa263b5 264 }
va009039 0:27d35fa263b5 265
va009039 0:27d35fa263b5 266 void CoreReg::write(uint32_t value)
va009039 0:27d35fa263b5 267 {
va009039 0:27d35fa263b5 268 _target->writeMemory(DCRDR, value);
va009039 0:27d35fa263b5 269 _target->writeMemory(DCRSR, _reg|0x10000);
va009039 0:27d35fa263b5 270 }
va009039 0:27d35fa263b5 271
va009039 0:27d35fa263b5 272 void CoreReg::setup(Target2* target, uint8_t reg)
va009039 0:27d35fa263b5 273 {
va009039 0:27d35fa263b5 274 _target = target;
va009039 0:27d35fa263b5 275 _reg = reg;
va009039 0:27d35fa263b5 276 }