Norimasa Okamoto / Mbed 2 deprecated lpcterm2

semihost server example program

Dependencies:   SWD mbed USBLocalFileSystem BaseDAP USBDAP

/media/uploads/va009039/kl46z-lpc800-360x480.jpg

LPCXpresso
LPC11U68		LPCXpresso
LPC1549		FRDM-KL46ZEA LPC4088 QSB
app-board		LPC1768
app-board		LPC810LPC1114FN28
serverserverserverserverserverclientclient
SWDIOD12D12D12p25p21p4(P0_2)p12
SWCLKD10D10D10p26p22p3(P0_3)p3
nRESET
*option		D6D6D6p34p30p1(P0_5)p23
GNDGNDGNDGNDp1p1p7p22
3.3VP3V3P3V3P3V3p44p40p6p21
flash writeSW2(P0_1)SW3(P1_9)SW1p14
joystick
center		p14
joystick
center

client example:

Import programlpc810-semihost_helloworld

semihost client example program

Last commit 20 Feb 2014 by Norimasa Okamoto

Target2.cpp@7:acfd2dbff157, 2014-02-18 (annotated)

Committer:
va009039
Date:
Tue Feb 18 06:54:42 2014 +0000
Revision:
7:acfd2dbff157
Parent:
6:5da6ad51a18f
Child:
18:5ed1759e863b
run on FRDM-KL46Z.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
va009039 7:acfd2dbff157 1 // Target2.cpp 2013/9/23
va009039 0:27d35fa263b5 2 #include "Target2.h"
va009039 0:27d35fa263b5 3 #include "mydebug.h"
va009039 0:27d35fa263b5 4
va009039 3:d7a7cde0bfb8 5 #define SYSMEMREMAP 0x40048000
va009039 3:d7a7cde0bfb8 6
va009039 2:32e9437348ad 7 #define CoreDebug_BASE (0xE000EDF0UL)
va009039 2:32e9437348ad 8 #define DHCSR (CoreDebug_BASE+0)
va009039 2:32e9437348ad 9 #define DCRSR (CoreDebug_BASE+4)
va009039 2:32e9437348ad 10 #define DCRDR (CoreDebug_BASE+8)
va009039 2:32e9437348ad 11 #define DEMCR (CoreDebug_BASE+12)
va009039 2:32e9437348ad 12
va009039 2:32e9437348ad 13 #define NVIC_AIRCR 0xE000ED0C
va009039 0:27d35fa263b5 14
va009039 4:5e4107edcbdb 15 // FPB (breakpoint)
va009039 4:5e4107edcbdb 16 #define FP_CTRL (0xE0002000)
va009039 4:5e4107edcbdb 17 #define FP_CTRL_KEY (1 << 1)
va009039 4:5e4107edcbdb 18 #define FP_COMP0 (0xE0002008)
va009039 4:5e4107edcbdb 19
va009039 5:2774358f5e4f 20 Target2::Target2(PinName swdio, PinName swclk, PinName reset)
va009039 7:acfd2dbff157 21 {
va009039 7:acfd2dbff157 22 _swd = new SWD(swdio, swclk, reset);
va009039 7:acfd2dbff157 23 inst();
va009039 7:acfd2dbff157 24 }
va009039 7:acfd2dbff157 25
va009039 7:acfd2dbff157 26 Target2::Target2(SWD* swd) : _swd(swd)
va009039 7:acfd2dbff157 27 {
va009039 7:acfd2dbff157 28 inst();
va009039 7:acfd2dbff157 29 }
va009039 7:acfd2dbff157 30
va009039 7:acfd2dbff157 31 void Target2::inst()
va009039 0:27d35fa263b5 32 {
va009039 0:27d35fa263b5 33 r0.setup(this, 0);
va009039 0:27d35fa263b5 34 r1.setup(this, 1);
va009039 0:27d35fa263b5 35 r2.setup(this, 2);
va009039 0:27d35fa263b5 36 r3.setup(this, 3);
va009039 0:27d35fa263b5 37 r4.setup(this, 4);
va009039 0:27d35fa263b5 38 r5.setup(this, 5);
va009039 0:27d35fa263b5 39 r6.setup(this, 6);
va009039 0:27d35fa263b5 40 r7.setup(this, 7);
va009039 0:27d35fa263b5 41 r8.setup(this, 8);
va009039 0:27d35fa263b5 42 r9.setup(this, 9);
va009039 0:27d35fa263b5 43 r10.setup(this, 10);
va009039 0:27d35fa263b5 44 r11.setup(this, 11);
va009039 0:27d35fa263b5 45 r12.setup(this, 12);
va009039 0:27d35fa263b5 46 sp.setup(this, 13);
va009039 0:27d35fa263b5 47 lr.setup(this, 14);
va009039 0:27d35fa263b5 48 pc.setup(this, 15);
va009039 0:27d35fa263b5 49 xpsr.setup(this, 16);
va009039 0:27d35fa263b5 50 }
va009039 0:27d35fa263b5 51
va009039 0:27d35fa263b5 52 bool Target2::setup()
va009039 0:27d35fa263b5 53 {
va009039 7:acfd2dbff157 54 _swd->Setup();
va009039 5:2774358f5e4f 55 JTAG2SWD();
va009039 0:27d35fa263b5 56
va009039 0:27d35fa263b5 57 uint32_t data;
va009039 7:acfd2dbff157 58 uint8_t ack = _swd->Transfer(DP_IDCODE, &data);
va009039 0:27d35fa263b5 59 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 60 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 61 return false;
va009039 0:27d35fa263b5 62 }
va009039 3:d7a7cde0bfb8 63 idcode = data;
va009039 0:27d35fa263b5 64
va009039 0:27d35fa263b5 65 Abort();
va009039 0:27d35fa263b5 66
va009039 0:27d35fa263b5 67 data = 0x0;
va009039 7:acfd2dbff157 68 ack = _swd->Transfer(DP_SELECT, &data);
va009039 0:27d35fa263b5 69 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 70 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 71 return false;
va009039 0:27d35fa263b5 72 }
va009039 0:27d35fa263b5 73
va009039 7:acfd2dbff157 74 ack = _swd->Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 75 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 76 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 77 return false;
va009039 0:27d35fa263b5 78 }
va009039 0:27d35fa263b5 79
va009039 0:27d35fa263b5 80 data = CSYSPWRUPREQ | CDBGPWRUPREQ;
va009039 7:acfd2dbff157 81 ack = _swd->Transfer(DP_CTRL_STAT, &data);
va009039 0:27d35fa263b5 82 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 83 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 84 return false;
va009039 0:27d35fa263b5 85 }
va009039 0:27d35fa263b5 86
va009039 7:acfd2dbff157 87 ack = _swd->Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 88 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 89 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 90 return false;
va009039 0:27d35fa263b5 91 }
va009039 0:27d35fa263b5 92
va009039 7:acfd2dbff157 93 ack = _swd->Transfer(DP_CTRL_STAT_R, &data);
va009039 0:27d35fa263b5 94 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 95 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 96 return false;
va009039 0:27d35fa263b5 97 }
va009039 0:27d35fa263b5 98 TEST_ASSERT(data == 0xf0000040);
va009039 0:27d35fa263b5 99
va009039 0:27d35fa263b5 100 data = CSYSPWRUPREQ | CDBGPWRUPREQ | 0x04000000;
va009039 7:acfd2dbff157 101 ack = _swd->Transfer(DP_CTRL_STAT, &data);
va009039 0:27d35fa263b5 102 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 103 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 104 return false;
va009039 0:27d35fa263b5 105 }
va009039 0:27d35fa263b5 106
va009039 7:acfd2dbff157 107 ack = _swd->Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 108 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 109 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 110 return false;
va009039 0:27d35fa263b5 111 }
va009039 0:27d35fa263b5 112
va009039 0:27d35fa263b5 113 data = CSYSPWRUPREQ | CDBGPWRUPREQ | MASKLANE;
va009039 7:acfd2dbff157 114 ack = _swd->Transfer(DP_CTRL_STAT, &data);
va009039 0:27d35fa263b5 115 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 116 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 117 return false;
va009039 0:27d35fa263b5 118 }
va009039 0:27d35fa263b5 119
va009039 7:acfd2dbff157 120 ack = _swd->Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 121 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 122 if (ack != SWD_OK) {
va009039 0:27d35fa263b5 123 return false;
va009039 0:27d35fa263b5 124 }
va009039 0:27d35fa263b5 125 return true;
va009039 0:27d35fa263b5 126 }
va009039 0:27d35fa263b5 127
va009039 6:5da6ad51a18f 128 void Target2::SWJClock(uint32_t clock_hz)
va009039 6:5da6ad51a18f 129 {
va009039 7:acfd2dbff157 130 _swd->SWJClock(clock_hz);
va009039 6:5da6ad51a18f 131 }
va009039 6:5da6ad51a18f 132
va009039 5:2774358f5e4f 133 void Target2::JTAG2SWD()
va009039 5:2774358f5e4f 134 {
va009039 5:2774358f5e4f 135 const uint8_t data1[] = {0xff,0xff,0xff,0xff,0xff,0xff,0xff};
va009039 5:2774358f5e4f 136 const uint8_t data2[] = {0x9e,0xe7};
va009039 5:2774358f5e4f 137 const uint8_t data3[] = {0x00};
va009039 7:acfd2dbff157 138 _swd->SWJSequence(sizeof(data1)*8, data1);
va009039 7:acfd2dbff157 139 _swd->SWJSequence(sizeof(data2)*8, data2);
va009039 7:acfd2dbff157 140 _swd->SWJSequence(sizeof(data1)*8, data1);
va009039 7:acfd2dbff157 141 _swd->SWJSequence(sizeof(data3)*8, data3);
va009039 5:2774358f5e4f 142 }
va009039 5:2774358f5e4f 143
va009039 3:d7a7cde0bfb8 144 void Target2::HardwareReset()
va009039 0:27d35fa263b5 145 {
va009039 7:acfd2dbff157 146 _swd->SWJPins(0x00, 0x80); // nReset off
va009039 7:acfd2dbff157 147 _swd->SWJPins(0x80, 0x80); // nReset on
va009039 3:d7a7cde0bfb8 148 }
va009039 3:d7a7cde0bfb8 149
va009039 3:d7a7cde0bfb8 150 void Target2::SoftwareReset()
va009039 3:d7a7cde0bfb8 151 {
va009039 3:d7a7cde0bfb8 152 writeMemory(NVIC_AIRCR, 0x05fa0004);
va009039 0:27d35fa263b5 153 }
va009039 0:27d35fa263b5 154
va009039 0:27d35fa263b5 155 uint32_t Target2::readMemory(uint32_t addr)
va009039 0:27d35fa263b5 156 {
va009039 0:27d35fa263b5 157 _setaddr(addr);
va009039 0:27d35fa263b5 158
va009039 0:27d35fa263b5 159 uint32_t data;
va009039 7:acfd2dbff157 160 uint8_t ack = _swd->Transfer(AP_DRW_R, &data); // dummy read
va009039 0:27d35fa263b5 161 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 162
va009039 7:acfd2dbff157 163 ack = _swd->Transfer(DP_RDBUFF, &data);
va009039 0:27d35fa263b5 164 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 165 return data;
va009039 0:27d35fa263b5 166 }
va009039 0:27d35fa263b5 167
va009039 0:27d35fa263b5 168 void Target2::readMemory(uint32_t addr, uint32_t* data, int count)
va009039 0:27d35fa263b5 169 {
va009039 0:27d35fa263b5 170 if (count == 0) {
va009039 0:27d35fa263b5 171 return;
va009039 0:27d35fa263b5 172 }
va009039 0:27d35fa263b5 173
va009039 0:27d35fa263b5 174 _setaddr(addr);
va009039 0:27d35fa263b5 175
va009039 7:acfd2dbff157 176 uint8_t ack = _swd->Transfer(AP_DRW_R, NULL); // dummy read
va009039 0:27d35fa263b5 177 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 178
va009039 0:27d35fa263b5 179 for(int i = 0; i < count-1; i++) {
va009039 7:acfd2dbff157 180 ack = _swd->Transfer(AP_DRW_R, data++);
va009039 0:27d35fa263b5 181 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 182 }
va009039 7:acfd2dbff157 183 ack = _swd->Transfer(DP_RDBUFF, data);
va009039 0:27d35fa263b5 184 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 185 }
va009039 0:27d35fa263b5 186
va009039 0:27d35fa263b5 187 void Target2::writeMemory(uint32_t addr, uint32_t data)
va009039 0:27d35fa263b5 188 {
va009039 0:27d35fa263b5 189 writeMemory(addr, &data, 1);
va009039 0:27d35fa263b5 190 }
va009039 0:27d35fa263b5 191
va009039 0:27d35fa263b5 192 void Target2::writeMemory(uint32_t addr, uint32_t* data, int count)
va009039 0:27d35fa263b5 193 {
va009039 0:27d35fa263b5 194 _setaddr(addr);
va009039 0:27d35fa263b5 195
va009039 0:27d35fa263b5 196 while(count-- > 0) {
va009039 7:acfd2dbff157 197 uint8_t ack = _swd->Transfer(AP_DRW_W, data);
va009039 0:27d35fa263b5 198 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 199 data++;
va009039 0:27d35fa263b5 200 }
va009039 0:27d35fa263b5 201 }
va009039 0:27d35fa263b5 202
va009039 1:eb30547ba84d 203 uint8_t Target2::readMemory8(uint32_t addr)
va009039 1:eb30547ba84d 204 {
va009039 1:eb30547ba84d 205 _setaddr8(addr);
va009039 1:eb30547ba84d 206
va009039 1:eb30547ba84d 207 uint32_t data32;
va009039 7:acfd2dbff157 208 uint8_t ack = _swd->Transfer(AP_DRW_R, &data32); // dummy read
va009039 1:eb30547ba84d 209 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 210
va009039 7:acfd2dbff157 211 ack = _swd->Transfer(DP_RDBUFF, &data32);
va009039 1:eb30547ba84d 212 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 213 return (data32 >> ((addr & 0x03) << 3)) & 0xff;
va009039 1:eb30547ba84d 214 }
va009039 1:eb30547ba84d 215
va009039 1:eb30547ba84d 216 void Target2::writeMemory8(uint32_t addr, uint8_t data)
va009039 1:eb30547ba84d 217 {
va009039 1:eb30547ba84d 218 _setaddr8(addr);
va009039 1:eb30547ba84d 219
va009039 1:eb30547ba84d 220 uint32_t data32 = data;
va009039 1:eb30547ba84d 221 data32 <<= ((addr & 0x03) << 3);
va009039 7:acfd2dbff157 222 uint8_t ack = _swd->Transfer(AP_DRW_W, &data32);
va009039 1:eb30547ba84d 223 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 224 }
va009039 1:eb30547ba84d 225
va009039 0:27d35fa263b5 226 void Target2::_setaddr(uint32_t addr)
va009039 0:27d35fa263b5 227 {
va009039 0:27d35fa263b5 228 uint32_t ctl = CSW_VALUE|CSW_SIZE32;
va009039 7:acfd2dbff157 229 uint8_t ack = _swd->Transfer(AP_CSW, &ctl);
va009039 0:27d35fa263b5 230 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 231
va009039 7:acfd2dbff157 232 ack = _swd->Transfer(DP_RDBUFF, NULL);
va009039 0:27d35fa263b5 233 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 234
va009039 7:acfd2dbff157 235 ack = _swd->Transfer(AP_TAR, &addr);
va009039 0:27d35fa263b5 236 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 237
va009039 7:acfd2dbff157 238 ack = _swd->Transfer(DP_RDBUFF, NULL);
va009039 0:27d35fa263b5 239 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 240 }
va009039 0:27d35fa263b5 241
va009039 1:eb30547ba84d 242 void Target2::_setaddr8(uint32_t addr)
va009039 1:eb30547ba84d 243 {
va009039 1:eb30547ba84d 244 uint32_t ctl = CSW_VALUE|CSW_SIZE8;
va009039 7:acfd2dbff157 245 uint8_t ack = _swd->Transfer(AP_CSW, &ctl);
va009039 1:eb30547ba84d 246 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 247
va009039 7:acfd2dbff157 248 ack = _swd->Transfer(DP_RDBUFF, NULL);
va009039 1:eb30547ba84d 249 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 250
va009039 7:acfd2dbff157 251 ack = _swd->Transfer(AP_TAR, &addr);
va009039 1:eb30547ba84d 252 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 253
va009039 7:acfd2dbff157 254 ack = _swd->Transfer(DP_RDBUFF, NULL);
va009039 1:eb30547ba84d 255 TEST_ASSERT(ack == SWD_OK);
va009039 1:eb30547ba84d 256 }
va009039 1:eb30547ba84d 257
va009039 0:27d35fa263b5 258 void Target2::Abort()
va009039 0:27d35fa263b5 259 {
va009039 0:27d35fa263b5 260 uint32_t data = 0x1e;
va009039 7:acfd2dbff157 261 uint8_t ack = _swd->Transfer(DP_ABORT, &data);
va009039 0:27d35fa263b5 262 TEST_ASSERT(ack == SWD_OK);
va009039 0:27d35fa263b5 263 }
va009039 0:27d35fa263b5 264
va009039 0:27d35fa263b5 265 int Target2::getStatus()
va009039 0:27d35fa263b5 266 {
va009039 0:27d35fa263b5 267 return readMemory(DHCSR) & 6 ? TARGET_HALTED : TARGET_RUNNING;
va009039 0:27d35fa263b5 268 }
va009039 0:27d35fa263b5 269
va009039 0:27d35fa263b5 270 bool Target2::wait_status(int status, int timeout_ms)
va009039 0:27d35fa263b5 271 {
va009039 0:27d35fa263b5 272 Timer t;
va009039 0:27d35fa263b5 273 t.reset();
va009039 0:27d35fa263b5 274 t.start();
va009039 0:27d35fa263b5 275 while(t.read_ms() < timeout_ms) {
va009039 0:27d35fa263b5 276 if (getStatus() == status) {
va009039 0:27d35fa263b5 277 return true;
va009039 0:27d35fa263b5 278 }
va009039 0:27d35fa263b5 279 }
va009039 0:27d35fa263b5 280 return false;
va009039 0:27d35fa263b5 281 }
va009039 0:27d35fa263b5 282
va009039 4:5e4107edcbdb 283 bool Target2::prog_status()
va009039 4:5e4107edcbdb 284 {
va009039 4:5e4107edcbdb 285 writeMemory(DEMCR, 1);
va009039 4:5e4107edcbdb 286 int status = getStatus();
va009039 4:5e4107edcbdb 287 TEST_ASSERT(status == TARGET_HALTED);
va009039 4:5e4107edcbdb 288 if (status == TARGET_RUNNING) {
va009039 4:5e4107edcbdb 289 halt();
va009039 4:5e4107edcbdb 290 }
va009039 4:5e4107edcbdb 291 bool st = wait_status(TARGET_HALTED);
va009039 4:5e4107edcbdb 292 TEST_ASSERT(st == true);
va009039 4:5e4107edcbdb 293 writeMemory(DEMCR, 0);
va009039 4:5e4107edcbdb 294 writeMemory(SYSMEMREMAP, 2); // user flash page
va009039 4:5e4107edcbdb 295 uint32_t reset_handler = readMemory(4);
va009039 6:5da6ad51a18f 296 if (setBreakpoint0(reset_handler)) {
va009039 6:5da6ad51a18f 297 writeMemory(NVIC_AIRCR, 0x05fa0004); // SYSRESETREQ software reset
va009039 6:5da6ad51a18f 298 st = wait_status(TARGET_HALTED);
va009039 6:5da6ad51a18f 299 TEST_ASSERT(st == true);
va009039 6:5da6ad51a18f 300 TEST_ASSERT((reset_handler&0xfffffffe) == pc);
va009039 6:5da6ad51a18f 301 removeBreakpoint0(0);
va009039 6:5da6ad51a18f 302 }
va009039 4:5e4107edcbdb 303 return true;
va009039 4:5e4107edcbdb 304 }
va009039 4:5e4107edcbdb 305
va009039 6:5da6ad51a18f 306 bool Target2::setBreakpoint0(uint32_t addr)
va009039 4:5e4107edcbdb 307 {
va009039 6:5da6ad51a18f 308 if ((addr&1) == 0 || addr >= 0x20000000) {
va009039 6:5da6ad51a18f 309 return false;
va009039 6:5da6ad51a18f 310 }
va009039 6:5da6ad51a18f 311 uint32_t data = (addr&0x1ffffffc) | 0xc0000001;
va009039 6:5da6ad51a18f 312 if (addr&0x00000002) {
va009039 6:5da6ad51a18f 313 data |= 0x80000000;
va009039 4:5e4107edcbdb 314 } else {
va009039 6:5da6ad51a18f 315 data |= 0x40000000;
va009039 4:5e4107edcbdb 316 }
va009039 6:5da6ad51a18f 317 writeMemory(FP_COMP0, data); // set breakpoint
va009039 6:5da6ad51a18f 318 writeMemory(FP_CTRL, 3); // enable FPB
va009039 6:5da6ad51a18f 319 return true;
va009039 6:5da6ad51a18f 320 }
va009039 6:5da6ad51a18f 321
va009039 6:5da6ad51a18f 322 void Target2::removeBreakpoint0(uint32_t addr)
va009039 6:5da6ad51a18f 323 {
va009039 6:5da6ad51a18f 324 writeMemory(FP_COMP0, 0); // breakpoint clear
va009039 6:5da6ad51a18f 325 writeMemory(FP_CTRL, 2); // desable FPB
va009039 4:5e4107edcbdb 326 }
va009039 4:5e4107edcbdb 327
va009039 0:27d35fa263b5 328 void Target2::halt()
va009039 0:27d35fa263b5 329 {
va009039 0:27d35fa263b5 330 writeMemory(DHCSR, 0xa05f0003);
va009039 0:27d35fa263b5 331 }
va009039 0:27d35fa263b5 332
va009039 0:27d35fa263b5 333 void Target2::resume()
va009039 0:27d35fa263b5 334 {
va009039 0:27d35fa263b5 335 writeMemory(DHCSR, 0xa05f0001);
va009039 0:27d35fa263b5 336 }
va009039 0:27d35fa263b5 337
va009039 1:eb30547ba84d 338 void Target2::step()
va009039 1:eb30547ba84d 339 {
va009039 1:eb30547ba84d 340 writeMemory(DHCSR, 0xa05f0005);
va009039 1:eb30547ba84d 341 }
va009039 1:eb30547ba84d 342
va009039 0:27d35fa263b5 343 uint32_t CoreReg::read()
va009039 0:27d35fa263b5 344 {
va009039 0:27d35fa263b5 345 _target->writeMemory(DCRSR, _reg);
va009039 0:27d35fa263b5 346 return _target->readMemory(DCRDR);
va009039 0:27d35fa263b5 347 }
va009039 0:27d35fa263b5 348
va009039 0:27d35fa263b5 349 void CoreReg::write(uint32_t value)
va009039 0:27d35fa263b5 350 {
va009039 0:27d35fa263b5 351 _target->writeMemory(DCRDR, value);
va009039 0:27d35fa263b5 352 _target->writeMemory(DCRSR, _reg|0x10000);
va009039 0:27d35fa263b5 353 }
va009039 0:27d35fa263b5 354
va009039 0:27d35fa263b5 355 void CoreReg::setup(Target2* target, uint8_t reg)
va009039 0:27d35fa263b5 356 {
va009039 0:27d35fa263b5 357 _target = target;
va009039 0:27d35fa263b5 358 _reg = reg;
va009039 0:27d35fa263b5 359 }