Diff: Target2.cpp

Revision:

18:5ed1759e863b

Parent:

7:acfd2dbff157

--- a/Target2.cpp	Sat May 03 12:54:55 2014 +0000
+++ b/Target2.cpp	Sun Jun 22 12:04:16 2014 +0000
@@ -1,4 +1,4 @@
-// Target2.cpp 2013/9/23
+// Target2.cpp 2014/6/22
 #include "Target2.h"
 #include "mydebug.h"
 
@@ -51,6 +51,7 @@
 
 bool Target2::setup()
 {
+    TRACE();
     _swd->Setup();
     JTAG2SWD();
     
@@ -149,24 +150,29 @@
 
 void Target2::SoftwareReset()
 {
+    TRACE();
     writeMemory(NVIC_AIRCR, 0x05fa0004);
 }
 
 uint32_t Target2::readMemory(uint32_t addr)
 {
+    TRACE1(addr);
     _setaddr(addr);
 
     uint32_t data;
     uint8_t ack = _swd->Transfer(AP_DRW_R, &data); // dummy read
+    TRACE1(ack);
     TEST_ASSERT(ack == SWD_OK);
 
     ack = _swd->Transfer(DP_RDBUFF, &data);
+    TRACE1(ack);
     TEST_ASSERT(ack == SWD_OK);
     return data;
 }
 
 void Target2::readMemory(uint32_t addr, uint32_t* data, int count)
 {
+    TRACE1(addr);
     if (count == 0) {
         return;
     }
@@ -202,6 +208,7 @@
 
 uint8_t Target2::readMemory8(uint32_t addr)
 {
+    TRACE1(addr);
     _setaddr8(addr);
 
     uint32_t data32;
@@ -225,22 +232,28 @@
 
 void Target2::_setaddr(uint32_t addr)
 {
+    TRACE1(addr);
     uint32_t ctl = CSW_VALUE|CSW_SIZE32;
     uint8_t ack = _swd->Transfer(AP_CSW, &ctl);
+    TRACE1(ack);
     TEST_ASSERT(ack == SWD_OK);
 
     ack = _swd->Transfer(DP_RDBUFF, NULL);
+    TRACE1(ack);
     TEST_ASSERT(ack == SWD_OK);
 
     ack = _swd->Transfer(AP_TAR, &addr);
+    TRACE1(ack);
     TEST_ASSERT(ack == SWD_OK);
 
     ack = _swd->Transfer(DP_RDBUFF, NULL);
+    TRACE1(ack);
     TEST_ASSERT(ack == SWD_OK);
 } 
 
 void Target2::_setaddr8(uint32_t addr)
 {
+    TRACE1(addr);
     uint32_t ctl = CSW_VALUE|CSW_SIZE8;
     uint8_t ack = _swd->Transfer(AP_CSW, &ctl);
     TEST_ASSERT(ack == SWD_OK);
@@ -264,11 +277,13 @@
 
 int Target2::getStatus()
 {
+    TRACE();
     return readMemory(DHCSR) & 6 ? TARGET_HALTED : TARGET_RUNNING;
 }
 
 bool Target2::wait_status(int status, int timeout_ms)
 {
+    TRACE1(status);
     Timer t;
     t.reset();
     t.start();
@@ -282,6 +297,7 @@
 
 bool Target2::prog_status()
 {
+    TRACE();
     writeMemory(DEMCR, 1);
     int status = getStatus();
     TEST_ASSERT(status == TARGET_HALTED);
@@ -305,6 +321,7 @@
 
 bool Target2::setBreakpoint0(uint32_t addr)
 {
+    TRACE1(addr);
     if ((addr&1) == 0 || addr >= 0x20000000) {
         return false;
     }
@@ -321,22 +338,26 @@
 
 void Target2::removeBreakpoint0(uint32_t addr)
 {
+    TRACE1(addr);
     writeMemory(FP_COMP0, 0); // breakpoint clear
     writeMemory(FP_CTRL, 2); // desable FPB
 }
 
 void Target2::halt()
 {
+    TRACE();
     writeMemory(DHCSR, 0xa05f0003);     
 }
 
 void Target2::resume()
 {
+    TRACE();
     writeMemory(DHCSR, 0xa05f0001);     
 }
 
 void Target2::step()
 {
+    TRACE();
     writeMemory(DHCSR, 0xa05f0005);     
 }