Matt Briggs / Mbed OS xDotBridge_update_dev_latest

Fork to see if I can get working

Dependencies:   BufferedSerial OneWire WinbondSPIFlash libxDot-dev-mbed5-deprecated

Fork of xDotBridge_update_test20180823 by Matt Briggs

xDotBridge/src/BaseboardIO.cpp@100:0882cf295f8e, 2017-11-29 (annotated)

Committer:
mbriggs_vortex
Date:
Wed Nov 29 13:54:36 2017 -0700
Revision:
100:0882cf295f8e
Parent:
99:83b54c851187 
Adding relaese bin to repo

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Matt Briggs 40:2ec4be320961 1 /*
Matt Briggs 40:2ec4be320961 2 * baseboardIO.cpp
Matt Briggs 40:2ec4be320961 3 *
Matt Briggs 40:2ec4be320961 4 * Created on: Jan 25, 2017
Matt Briggs 40:2ec4be320961 5 * Author: mbriggs
Matt Briggs 40:2ec4be320961 6 */
Matt Briggs 40:2ec4be320961 7
Matt Briggs 40:2ec4be320961 8 #include "BaseboardIO.h"
Matt Briggs 75:600cb3a9f126 9 #include "dot_util.h" // XXX just need the reference to dot somehow
Matt Briggs 58:15aa7a785b9f 10 #include "xdot_low_power.h"
Matt Briggs 63:e1efbe3402d9 11 #include "MyLog.h"
Matt Briggs 40:2ec4be320961 12
Matt Briggs 61:8d9efd33cac9 13 // Original
Matt Briggs 62:9751a8504c82 14 //const float COIL_ON_TIME = 0.030; // 30 ms
Matt Briggs 61:8d9efd33cac9 15 // Test
Matt Briggs 62:9751a8504c82 16 const float COIL_ON_TIME = 0.300; // 300 ms
Matt Briggs 61:8d9efd33cac9 17
Matt Briggs 44:ece6330e9b57 18
Matt Briggs 49:18f1354f9e51 19 // Port expander 0 (Currently U7)
Matt Briggs 44:ece6330e9b57 20 const uint8_t pEx0232En = 0x01;
Matt Briggs 44:ece6330e9b57 21 const uint8_t pEx0232TxDis = 0x02;
Matt Briggs 44:ece6330e9b57 22 const uint8_t pEx0Rot1B1 = 0x04;
Matt Briggs 44:ece6330e9b57 23 const uint8_t pEx0Rot1B2 = 0x08;
Matt Briggs 44:ece6330e9b57 24 const uint8_t pEx0Rot1B4 = 0x10;
Matt Briggs 44:ece6330e9b57 25 const uint8_t pEx0Rot1B8 = 0x20;
Matt Briggs 44:ece6330e9b57 26 const uint8_t pEx0Rot2B1 = 0x40;
Matt Briggs 44:ece6330e9b57 27 const uint8_t pEx0Rot2B2 = 0x80;
Matt Briggs 49:18f1354f9e51 28 const uint8_t pEx0OutMask = 0x03; // Only allow bits 0,1 to be changed
Matt Briggs 44:ece6330e9b57 29
Matt Briggs 49:18f1354f9e51 30 // Port expander 1 (Currently U8)
Matt Briggs 44:ece6330e9b57 31 const uint8_t pEx1NoNcSel = 0x01;
Matt Briggs 44:ece6330e9b57 32 const uint8_t pEx1RxTxSel = 0x02;
Matt Briggs 44:ece6330e9b57 33 const uint8_t pEx1WanSel = 0x04;
Matt Briggs 44:ece6330e9b57 34 const uint8_t pEx1SerialEn = 0x08; // Labeled as reserved
Matt Briggs 44:ece6330e9b57 35 const uint8_t pEx1Rot2B8 = 0x10;
Matt Briggs 44:ece6330e9b57 36 const uint8_t pEx1Rot2B4 = 0x20;
Matt Briggs 44:ece6330e9b57 37 const uint8_t pEx1RlyB = 0x40; // This is actually a coil
Matt Briggs 44:ece6330e9b57 38 const uint8_t pEx1RlyA = 0x80; // This is actually a coil
Matt Briggs 49:18f1354f9e51 39 const uint8_t pEx1OutMask = 0xC0; // Only allow bits 6,7 to be changed
Matt Briggs 44:ece6330e9b57 40
Matt Briggs 44:ece6330e9b57 41 /**
Matt Briggs 44:ece6330e9b57 42 * Note for interrupt within uC cannot use two pins with the same numeric suffix (e.g. cannot
Matt Briggs 44:ece6330e9b57 43 * use both PA_0 and PB_0). Note 1, 6, 7, 8, and 13 are used by LoRa radio.
Matt Briggs 44:ece6330e9b57 44 */
Matt Briggs 44:ece6330e9b57 45
Matt Briggs 40:2ec4be320961 46 BaseboardIO::BaseboardIO()
Matt Briggs 58:15aa7a785b9f 47 : mOWMaster(OneWireMasterPinName),
Matt Briggs 58:15aa7a785b9f 48 mCCIn(CCInPinName),
Matt Briggs 58:15aa7a785b9f 49 mTamper(TamperPinName),
Matt Briggs 58:15aa7a785b9f 50 mPairBtn(PairBtnPinName),
Matt Briggs 58:15aa7a785b9f 51 mLed(LedPinName),
Matt Briggs 60:5179449a684f 52 mLrrLed(LrrLedPinName, 0),
Matt Briggs 58:15aa7a785b9f 53 mSwitchedIOCtrl(SwitchedIOCtrlPinName, 0)
Matt Briggs 40:2ec4be320961 54 {
Matt Briggs 44:ece6330e9b57 55 mPortExpanderVal0 = 0x00;
Matt Briggs 44:ece6330e9b57 56 mPortExpanderVal1 = 0x00;
Matt Briggs 44:ece6330e9b57 57
Matt Briggs 44:ece6330e9b57 58 mPortEx0 = NULL;
Matt Briggs 44:ece6330e9b57 59 mPortEx1 = NULL;
Matt Briggs 40:2ec4be320961 60 }
Matt Briggs 56:40b454c952cc 61 CmdResult BaseboardIO::init(bool overwriteNvm)
Matt Briggs 40:2ec4be320961 62 {
Matt Briggs 56:40b454c952cc 63 bool storedROMsGood = false;
Matt Briggs 56:40b454c952cc 64 uint8_t val;
Matt Briggs 44:ece6330e9b57 65 // Setup port expanders
Matt Briggs 56:40b454c952cc 66 if (readInfoFromNVM() == cmdSuccess && !overwriteNvm) {
Matt Briggs 63:e1efbe3402d9 67 myLogInfo("Stored ROM0 Addr: %02x:%02x:%02x:%02x:%02x:%02x:%02x%02x found.",
Matt Briggs 63:e1efbe3402d9 68 mNvmObj.mPortExpanderROM0[7],
Matt Briggs 63:e1efbe3402d9 69 mNvmObj.mPortExpanderROM0[6],
Matt Briggs 63:e1efbe3402d9 70 mNvmObj.mPortExpanderROM0[5],
Matt Briggs 63:e1efbe3402d9 71 mNvmObj.mPortExpanderROM0[4],
Matt Briggs 63:e1efbe3402d9 72 mNvmObj.mPortExpanderROM0[3],
Matt Briggs 63:e1efbe3402d9 73 mNvmObj.mPortExpanderROM0[2],
Matt Briggs 63:e1efbe3402d9 74 mNvmObj.mPortExpanderROM0[1],
Matt Briggs 63:e1efbe3402d9 75 mNvmObj.mPortExpanderROM0[0]);
Matt Briggs 63:e1efbe3402d9 76 myLogInfo("Stored ROM1 Addr: %02x:%02x:%02x:%02x:%02x:%02x:%02x%02x found.",
Matt Briggs 63:e1efbe3402d9 77 mNvmObj.mPortExpanderROM1[7],
Matt Briggs 63:e1efbe3402d9 78 mNvmObj.mPortExpanderROM1[6],
Matt Briggs 63:e1efbe3402d9 79 mNvmObj.mPortExpanderROM1[5],
Matt Briggs 63:e1efbe3402d9 80 mNvmObj.mPortExpanderROM1[4],
Matt Briggs 63:e1efbe3402d9 81 mNvmObj.mPortExpanderROM1[3],
Matt Briggs 63:e1efbe3402d9 82 mNvmObj.mPortExpanderROM1[2],
Matt Briggs 63:e1efbe3402d9 83 mNvmObj.mPortExpanderROM1[1],
Matt Briggs 63:e1efbe3402d9 84 mNvmObj.mPortExpanderROM1[0]);
Matt Briggs 63:e1efbe3402d9 85 myLogInfo("BaseboardIO parameters successfully loaded from NVM");
Matt Briggs 56:40b454c952cc 86 // Check that the ROM Addresses are correct and valid
Matt Briggs 56:40b454c952cc 87 uint8_t portEx0Ctrl, portEx1Ctrl;
Matt Briggs 56:40b454c952cc 88 mPortEx0 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM0);
Matt Briggs 56:40b454c952cc 89 mPortEx0->registerReadReliable(0x8D, portEx0Ctrl);
Matt Briggs 56:40b454c952cc 90 // Gets 0xFF if it is not the correct address
Matt Briggs 63:e1efbe3402d9 91 myLogInfo("PortEx0 Control register reads %02X", portEx0Ctrl);
Matt Briggs 56:40b454c952cc 92
Matt Briggs 56:40b454c952cc 93 mPortEx1 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM1);
Matt Briggs 56:40b454c952cc 94 mPortEx1->registerReadReliable(0x8D, portEx1Ctrl);
Matt Briggs 63:e1efbe3402d9 95 myLogInfo("PortEx1 Control register reads %02X", portEx1Ctrl);
Matt Briggs 56:40b454c952cc 96 if ((portEx0Ctrl == 0xFF) || (portEx1Ctrl == 0xFF)) {
Matt Briggs 63:e1efbe3402d9 97 myLogError("Stored port expander ROM check failed. Set EEPROM to defaults.");
Matt Briggs 56:40b454c952cc 98 }
Matt Briggs 56:40b454c952cc 99 else {
Matt Briggs 56:40b454c952cc 100 storedROMsGood = true;
Matt Briggs 56:40b454c952cc 101 }
Matt Briggs 44:ece6330e9b57 102 }
Matt Briggs 56:40b454c952cc 103 if (!storedROMsGood)
Matt Briggs 56:40b454c952cc 104 { // EEPROM values not there or corrupt. Should only happen in factory.
Matt Briggs 55:79ab0bbc5008 105 mNvmObj.setDefaults();
Matt Briggs 47:a68747642a7a 106 // Find ROM address and test which one is which. Requires user
Matt Briggs 47:a68747642a7a 107 // switches to be in known state.
Matt Briggs 47:a68747642a7a 108 if (identifyPortExpanders() != cmdSuccess) {
Matt Briggs 63:e1efbe3402d9 109 myLogError("Error identifying port expanders");
Matt Briggs 44:ece6330e9b57 110 return cmdError;
Matt Briggs 44:ece6330e9b57 111 }
Matt Briggs 55:79ab0bbc5008 112 if (writeInfoToNVM() == cmdSuccess) {
Matt Briggs 63:e1efbe3402d9 113 myLogInfo("Baseboard config saved to NVM");
Matt Briggs 55:79ab0bbc5008 114 }
Matt Briggs 55:79ab0bbc5008 115 else {
Matt Briggs 63:e1efbe3402d9 116 myLogError("Baseboard config failed to save to NVM");
Matt Briggs 55:79ab0bbc5008 117 }
Matt Briggs 56:40b454c952cc 118 mPortEx0 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM0);
Matt Briggs 56:40b454c952cc 119 mPortEx0->registerReadReliable(0x8D, val);
Matt Briggs 56:40b454c952cc 120 // Gets 0xFF if it is not the correct address
Matt Briggs 63:e1efbe3402d9 121 myLogInfo("PortEx0 Control register reads %02X", val);
Matt Briggs 56:40b454c952cc 122 mPortEx1 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM1);
Matt Briggs 56:40b454c952cc 123 mPortEx1->registerReadReliable(0x8D, val);
Matt Briggs 63:e1efbe3402d9 124 myLogInfo("PortEx1 Control register reads %02X", val);
Matt Briggs 44:ece6330e9b57 125 }
Matt Briggs 44:ece6330e9b57 126
Matt Briggs 57:bdac7dd17af2 127 if (sampleUserSwitches() != cmdSuccess) {
Matt Briggs 63:e1efbe3402d9 128 myLogError("Error sampling user switches");
Matt Briggs 57:bdac7dd17af2 129 return cmdError;
Matt Briggs 57:bdac7dd17af2 130 }
Matt Briggs 57:bdac7dd17af2 131
Matt Briggs 44:ece6330e9b57 132 // Put relay in known state
Matt Briggs 47:a68747642a7a 133 if (relayNormal() != cmdSuccess) {
Matt Briggs 63:e1efbe3402d9 134 myLogError("Error setting relay during init");
Matt Briggs 47:a68747642a7a 135 return cmdError;
Matt Briggs 47:a68747642a7a 136 }
Matt Briggs 60:5179449a684f 137 ledOff();
Matt Briggs 47:a68747642a7a 138
Matt Briggs 63:e1efbe3402d9 139 myLogInfo("Baseboard IO initialization successful");
Matt Briggs 44:ece6330e9b57 140 return cmdSuccess;
Matt Briggs 40:2ec4be320961 141 }
Matt Briggs 40:2ec4be320961 142
Matt Briggs 40:2ec4be320961 143 // Registering for interrupts
Matt Briggs 44:ece6330e9b57 144 void BaseboardIO::regCCInInt(Callback<void()> func)
Matt Briggs 40:2ec4be320961 145 {
Matt Briggs 48:bab9f747d9ed 146 if (isCCNO()) {
Matt Briggs 48:bab9f747d9ed 147 // Pulled high, switched low
Matt Briggs 48:bab9f747d9ed 148 mCCIn.fall(func);
Matt Briggs 48:bab9f747d9ed 149 }
Matt Briggs 48:bab9f747d9ed 150 else {
Matt Briggs 48:bab9f747d9ed 151 mCCIn.rise(func);
Matt Briggs 48:bab9f747d9ed 152 }
Matt Briggs 53:a1563574a980 153 mCCIn.mode(PullNone);
Matt Briggs 49:18f1354f9e51 154 mCCIn.enable_irq();
Matt Briggs 40:2ec4be320961 155 }
Matt Briggs 44:ece6330e9b57 156 void BaseboardIO::regTamperInt(Callback<void()> func)
Matt Briggs 40:2ec4be320961 157 {
Matt Briggs 44:ece6330e9b57 158 // Pulled high, switched low
Matt Briggs 53:a1563574a980 159 mTamper.mode(PullNone);
Matt Briggs 49:18f1354f9e51 160 mTamper.rise(func);
Matt Briggs 44:ece6330e9b57 161 mTamper.fall(func);
Matt Briggs 49:18f1354f9e51 162 mTamper.enable_irq();
Matt Briggs 40:2ec4be320961 163 }
Matt Briggs 44:ece6330e9b57 164 void BaseboardIO::regPairBtnInt(Callback<void()> func)
Matt Briggs 40:2ec4be320961 165 {
Matt Briggs 44:ece6330e9b57 166 // Pulled low, switched high
Matt Briggs 58:15aa7a785b9f 167 mPairBtn.mode(PullNone);
Matt Briggs 44:ece6330e9b57 168 mPairBtn.rise(func);
Matt Briggs 49:18f1354f9e51 169 mPairBtn.enable_irq();
Matt Briggs 40:2ec4be320961 170 }
Matt Briggs 40:2ec4be320961 171
Matt Briggs 40:2ec4be320961 172 // Input
Matt Briggs 40:2ec4be320961 173 CmdResult BaseboardIO::sampleUserSwitches()
Matt Briggs 40:2ec4be320961 174 {
Matt Briggs 48:bab9f747d9ed 175 if ((mPortEx0 == NULL) || (mPortEx1 == NULL))
Matt Briggs 48:bab9f747d9ed 176 return cmdError;
Matt Briggs 44:ece6330e9b57 177 // Sample port expanders
Matt Briggs 49:18f1354f9e51 178 enableSwitchedIO();
Matt Briggs 49:18f1354f9e51 179 wait(0.001); // Wait 1 ms
Matt Briggs 53:a1563574a980 180 if (mPortEx0->pioLogicReliableRead(mPortExpanderVal0) != cmdSuccess) {
Matt Briggs 49:18f1354f9e51 181 disableSwitchedIO();
Matt Briggs 63:e1efbe3402d9 182 myLogError("Error reading port expander 0.");
Matt Briggs 44:ece6330e9b57 183 return cmdError;
Matt Briggs 44:ece6330e9b57 184 }
Matt Briggs 53:a1563574a980 185 if (mPortEx1->pioLogicReliableRead(mPortExpanderVal1) != cmdSuccess) {
Matt Briggs 49:18f1354f9e51 186 disableSwitchedIO();
Matt Briggs 63:e1efbe3402d9 187 myLogError("Error reading port expander 1.");
Matt Briggs 44:ece6330e9b57 188 return cmdError;
Matt Briggs 44:ece6330e9b57 189 }
Matt Briggs 49:18f1354f9e51 190 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 191 return cmdSuccess;
Matt Briggs 40:2ec4be320961 192 }
Matt Briggs 57:bdac7dd17af2 193 bool BaseboardIO::isCCInAlert()
Matt Briggs 57:bdac7dd17af2 194 {
Matt Briggs 57:bdac7dd17af2 195 if (isCCNO()) { // If NO then the CCIn should float high if not in alert state
Matt Briggs 57:bdac7dd17af2 196 return mCCIn == 0;
Matt Briggs 57:bdac7dd17af2 197 }
Matt Briggs 57:bdac7dd17af2 198 else { // If NC then the CCIN should be held low if not in alert state
Matt Briggs 57:bdac7dd17af2 199 return mCCIn == 1;
Matt Briggs 57:bdac7dd17af2 200 }
Matt Briggs 57:bdac7dd17af2 201 }
Matt Briggs 40:2ec4be320961 202 bool BaseboardIO::isPairBtn()
Matt Briggs 40:2ec4be320961 203 {
Matt Briggs 44:ece6330e9b57 204 // Depressed button is high
Matt Briggs 44:ece6330e9b57 205 return mPairBtn.read() == 1;
Matt Briggs 40:2ec4be320961 206 }
Matt Briggs 48:bab9f747d9ed 207 bool BaseboardIO::isCCNO()
Matt Briggs 40:2ec4be320961 208 {
Matt Briggs 44:ece6330e9b57 209 // When DIP switch is not closed (i.e. value reads high) assume NO
Matt Briggs 49:18f1354f9e51 210 return (mPortExpanderVal1 & pEx1NoNcSel) != 0; // Open NO, closed NC
Matt Briggs 40:2ec4be320961 211 }
mbriggs_vortex 98:3609f600c2f5 212 void BaseboardIO::setIsCCNO(bool val)
mbriggs_vortex 98:3609f600c2f5 213 {
mbriggs_vortex 98:3609f600c2f5 214 // When DIP switch is not closed (i.e. value reads high) assume NO
mbriggs_vortex 98:3609f600c2f5 215 if (val) {
mbriggs_vortex 98:3609f600c2f5 216 mPortExpanderVal1 |= pEx1NoNcSel; // Set bit
mbriggs_vortex 98:3609f600c2f5 217 }
mbriggs_vortex 98:3609f600c2f5 218 else {
mbriggs_vortex 98:3609f600c2f5 219 mPortExpanderVal1 &= ~pEx1NoNcSel; // Clear bit
mbriggs_vortex 98:3609f600c2f5 220 }
mbriggs_vortex 98:3609f600c2f5 221 }
Matt Briggs 40:2ec4be320961 222 bool BaseboardIO::isRx()
Matt Briggs 40:2ec4be320961 223 {
Matt Briggs 44:ece6330e9b57 224 // When DIP switch is not closed (i.e. value reads high) assume RX
Matt Briggs 44:ece6330e9b57 225 return (mPortExpanderVal1 & pEx1RxTxSel) != 0;
Matt Briggs 40:2ec4be320961 226 }
mbriggs_vortex 98:3609f600c2f5 227 void BaseboardIO::setIsRx(bool val)
mbriggs_vortex 98:3609f600c2f5 228 {
mbriggs_vortex 98:3609f600c2f5 229 // When DIP switch is not closed (i.e. value reads high) assume RX
mbriggs_vortex 98:3609f600c2f5 230 if (val) {
mbriggs_vortex 98:3609f600c2f5 231 mPortExpanderVal1 |= pEx1RxTxSel; // Set bit
mbriggs_vortex 98:3609f600c2f5 232 }
mbriggs_vortex 98:3609f600c2f5 233 else {
mbriggs_vortex 98:3609f600c2f5 234 mPortExpanderVal1 &= ~pEx1RxTxSel; // Clear bit
mbriggs_vortex 98:3609f600c2f5 235 }
mbriggs_vortex 98:3609f600c2f5 236 }
Matt Briggs 40:2ec4be320961 237 bool BaseboardIO::isLoRaWANMode()
Matt Briggs 40:2ec4be320961 238 {
Matt Briggs 44:ece6330e9b57 239 // When DIP switch is not closed (i.e. value reads high) assume P2P not WAN
Matt Briggs 44:ece6330e9b57 240 return (mPortExpanderVal1 & pEx1WanSel) == 0;
Matt Briggs 40:2ec4be320961 241 }
Matt Briggs 50:e89647e77fd5 242 bool BaseboardIO::isSerialEnabled()
Matt Briggs 50:e89647e77fd5 243 {
Matt Briggs 50:e89647e77fd5 244 // When DIP switch is not closed (i.e. value reads high) assume not in serial mode
Matt Briggs 50:e89647e77fd5 245 return (mPortExpanderVal1 & pEx1SerialEn) == 0;
Matt Briggs 50:e89647e77fd5 246 }
Matt Briggs 40:2ec4be320961 247 uint8_t BaseboardIO::rotarySwitch1()
Matt Briggs 40:2ec4be320961 248 {
Matt Briggs 44:ece6330e9b57 249 // If a bit of a nibble is asserted then the port expander line is switched low.
Matt Briggs 44:ece6330e9b57 250 uint8_t val = 0;
Matt Briggs 44:ece6330e9b57 251 if ((mPortExpanderVal0 & pEx0Rot1B8) == 0)
Matt Briggs 44:ece6330e9b57 252 val |= 0x08;
Matt Briggs 44:ece6330e9b57 253 if ((mPortExpanderVal0 & pEx0Rot1B4) == 0)
Matt Briggs 44:ece6330e9b57 254 val |= 0x04;
Matt Briggs 44:ece6330e9b57 255 if ((mPortExpanderVal0 & pEx0Rot1B2) == 0)
Matt Briggs 44:ece6330e9b57 256 val |= 0x02;
Matt Briggs 44:ece6330e9b57 257 if ((mPortExpanderVal0 & pEx0Rot1B1) == 0)
Matt Briggs 44:ece6330e9b57 258 val |= 0x01;
Matt Briggs 44:ece6330e9b57 259 return val;
Matt Briggs 40:2ec4be320961 260 }
mbriggs_vortex 98:3609f600c2f5 261 void BaseboardIO::setRotarySwitch1(uint8_t val)
mbriggs_vortex 98:3609f600c2f5 262 {
mbriggs_vortex 99:83b54c851187 263 // Clear all then set
mbriggs_vortex 99:83b54c851187 264 mPortExpanderVal0 &= ~pEx0Rot1B8;
mbriggs_vortex 99:83b54c851187 265 mPortExpanderVal0 &= ~pEx0Rot1B4;
mbriggs_vortex 99:83b54c851187 266 mPortExpanderVal0 &= ~pEx0Rot1B2;
mbriggs_vortex 99:83b54c851187 267 mPortExpanderVal0 &= ~pEx0Rot1B1;
mbriggs_vortex 99:83b54c851187 268
mbriggs_vortex 99:83b54c851187 269 if ((val & 0x08) == 0) {
mbriggs_vortex 99:83b54c851187 270 mPortExpanderVal0 |= pEx0Rot1B8;
mbriggs_vortex 98:3609f600c2f5 271 }
mbriggs_vortex 99:83b54c851187 272 if ((val & 0x04) == 0) {
mbriggs_vortex 99:83b54c851187 273 mPortExpanderVal0 |= pEx0Rot1B4;
mbriggs_vortex 98:3609f600c2f5 274 }
mbriggs_vortex 99:83b54c851187 275 if ((val & 0x02) == 0) {
mbriggs_vortex 99:83b54c851187 276 mPortExpanderVal0 |= pEx0Rot1B2;
mbriggs_vortex 99:83b54c851187 277 }
mbriggs_vortex 99:83b54c851187 278 if ((val & 0x01) == 0) {
mbriggs_vortex 99:83b54c851187 279 mPortExpanderVal0 |= pEx0Rot1B1;
mbriggs_vortex 98:3609f600c2f5 280 }
mbriggs_vortex 98:3609f600c2f5 281 }
Matt Briggs 40:2ec4be320961 282 uint8_t BaseboardIO::rotarySwitch2()
Matt Briggs 40:2ec4be320961 283 {
Matt Briggs 44:ece6330e9b57 284 // If a bit of a nibble is asserted then the port expander line is switched low.
Matt Briggs 44:ece6330e9b57 285 uint8_t val = 0;
Matt Briggs 44:ece6330e9b57 286 if ((mPortExpanderVal1 & pEx1Rot2B8) == 0)
Matt Briggs 44:ece6330e9b57 287 val |= 0x08;
Matt Briggs 44:ece6330e9b57 288 if ((mPortExpanderVal1 & pEx1Rot2B4) == 0)
Matt Briggs 44:ece6330e9b57 289 val |= 0x04;
Matt Briggs 44:ece6330e9b57 290 if ((mPortExpanderVal0 & pEx0Rot2B2) == 0)
Matt Briggs 44:ece6330e9b57 291 val |= 0x02;
Matt Briggs 44:ece6330e9b57 292 if ((mPortExpanderVal0 & pEx0Rot2B1) == 0)
Matt Briggs 44:ece6330e9b57 293 val |= 0x01;
Matt Briggs 44:ece6330e9b57 294 return val;
Matt Briggs 40:2ec4be320961 295 }
Matt Briggs 40:2ec4be320961 296
Matt Briggs 40:2ec4be320961 297 // Output
Matt Briggs 40:2ec4be320961 298 CmdResult BaseboardIO::ledOn()
Matt Briggs 40:2ec4be320961 299 {
Matt Briggs 44:ece6330e9b57 300 mLed = 1;
Matt Briggs 59:485545afc4dc 301 #if ALSO_USE_LRR_LED
Matt Briggs 59:485545afc4dc 302 mLrrLed = 1;
Matt Briggs 59:485545afc4dc 303 #endif
Matt Briggs 44:ece6330e9b57 304 return cmdSuccess;
Matt Briggs 40:2ec4be320961 305 }
Matt Briggs 40:2ec4be320961 306 CmdResult BaseboardIO::ledOff()
Matt Briggs 40:2ec4be320961 307 {
Matt Briggs 44:ece6330e9b57 308 mLed = 0;
Matt Briggs 60:5179449a684f 309 // Always allow setting GPIO0 to 0
Matt Briggs 60:5179449a684f 310 //#if ALSO_USE_LRR_LED
Matt Briggs 59:485545afc4dc 311 mLrrLed = 0;
Matt Briggs 60:5179449a684f 312 //#endif
Matt Briggs 44:ece6330e9b57 313 return cmdSuccess;
Matt Briggs 40:2ec4be320961 314 }
Matt Briggs 40:2ec4be320961 315 CmdResult BaseboardIO::relayAlert()
Matt Briggs 40:2ec4be320961 316 {
Matt Briggs 48:bab9f747d9ed 317 if (isCCNO()) { // Normally Open
Matt Briggs 44:ece6330e9b57 318 return closeRelay();
Matt Briggs 44:ece6330e9b57 319 }
Matt Briggs 44:ece6330e9b57 320 else { // Normally Close
Matt Briggs 44:ece6330e9b57 321 return openRelay();
Matt Briggs 44:ece6330e9b57 322 }
Matt Briggs 40:2ec4be320961 323 }
Matt Briggs 40:2ec4be320961 324 CmdResult BaseboardIO::relayNormal()
Matt Briggs 40:2ec4be320961 325 {
Matt Briggs 48:bab9f747d9ed 326 if (isCCNO()) { // Normally Open
Matt Briggs 44:ece6330e9b57 327 return openRelay();
Matt Briggs 44:ece6330e9b57 328 }
Matt Briggs 44:ece6330e9b57 329 else { // Normally Close
Matt Briggs 44:ece6330e9b57 330 return closeRelay();
Matt Briggs 44:ece6330e9b57 331 }
Matt Briggs 40:2ec4be320961 332 }
Matt Briggs 40:2ec4be320961 333
Matt Briggs 40:2ec4be320961 334 // Future
Matt Briggs 40:2ec4be320961 335 CmdResult BaseboardIO::serialRx(bool enable)
Matt Briggs 40:2ec4be320961 336 {
Matt Briggs 44:ece6330e9b57 337 uint8_t val;
Matt Briggs 49:18f1354f9e51 338 if (mPortEx0 == NULL) {
Matt Briggs 63:e1efbe3402d9 339 myLogError("Error enabling 232. Port expanders not initialized.");
Matt Briggs 49:18f1354f9e51 340 return cmdError;
Matt Briggs 49:18f1354f9e51 341 }
Matt Briggs 53:a1563574a980 342 mPortEx0->pioLogicReliableRead(val);
Matt Briggs 44:ece6330e9b57 343
Matt Briggs 44:ece6330e9b57 344 // Active low from port expander -> pmos -> 232 (active chip EN)
Matt Briggs 44:ece6330e9b57 345 if (enable) {
Matt Briggs 44:ece6330e9b57 346 val &= ~pEx0232En;
Matt Briggs 44:ece6330e9b57 347 }
Matt Briggs 44:ece6330e9b57 348 else {
Matt Briggs 44:ece6330e9b57 349 val |= pEx0232En;
Matt Briggs 44:ece6330e9b57 350 }
Matt Briggs 44:ece6330e9b57 351
Matt Briggs 53:a1563574a980 352 if (mPortEx0->pioLogicReliableWrite(val | ~pEx0OutMask) != cmdSuccess) {
Matt Briggs 63:e1efbe3402d9 353 myLogError("Error enabling 232");
Matt Briggs 44:ece6330e9b57 354 return cmdError;
Matt Briggs 44:ece6330e9b57 355 }
Matt Briggs 44:ece6330e9b57 356 return cmdSuccess;
Matt Briggs 44:ece6330e9b57 357 }
Matt Briggs 44:ece6330e9b57 358 CmdResult BaseboardIO::serialTx(bool enable)
Matt Briggs 44:ece6330e9b57 359 {
Matt Briggs 44:ece6330e9b57 360 uint8_t val;
Matt Briggs 49:18f1354f9e51 361 if (mPortEx0 == NULL) {
Matt Briggs 63:e1efbe3402d9 362 myLogError("Error enabling 232 TX. Port expanders not initialized.");
Matt Briggs 49:18f1354f9e51 363 return cmdError;
Matt Briggs 49:18f1354f9e51 364 }
Matt Briggs 53:a1563574a980 365 mPortEx0->pioLogicReliableRead(val);
Matt Briggs 44:ece6330e9b57 366
Matt Briggs 44:ece6330e9b57 367 // Active high tx disable therefore active low tx enable (note chip must also be enabled for TX)
Matt Briggs 44:ece6330e9b57 368 if (enable) {
Matt Briggs 44:ece6330e9b57 369 val &= ~pEx0232TxDis;
Matt Briggs 44:ece6330e9b57 370 }
Matt Briggs 44:ece6330e9b57 371 else {
Matt Briggs 44:ece6330e9b57 372 val |= pEx0232TxDis;
Matt Briggs 44:ece6330e9b57 373 }
Matt Briggs 44:ece6330e9b57 374
Matt Briggs 53:a1563574a980 375 if (mPortEx0->pioLogicReliableWrite(val | ~pEx0OutMask) != cmdSuccess) {
Matt Briggs 63:e1efbe3402d9 376 myLogError("Error enabling 232 TX");
Matt Briggs 44:ece6330e9b57 377 return cmdError;
Matt Briggs 44:ece6330e9b57 378 }
Matt Briggs 44:ece6330e9b57 379 return cmdSuccess;
Matt Briggs 44:ece6330e9b57 380 }
Matt Briggs 44:ece6330e9b57 381
Matt Briggs 44:ece6330e9b57 382 // private
Matt Briggs 44:ece6330e9b57 383 CmdResult BaseboardIO::readInfoFromNVM()
Matt Briggs 44:ece6330e9b57 384 {
Matt Briggs 55:79ab0bbc5008 385 bool nvmReadResult;
Matt Briggs 55:79ab0bbc5008 386 uint8_t *data = new uint8_t [BASEBOARDIO_NVM_SIZE];
Matt Briggs 55:79ab0bbc5008 387
Matt Briggs 55:79ab0bbc5008 388 nvmReadResult = dot->nvmRead(BASEBOARDIO_NVM_START_ADDR, data, BASEBOARDIO_NVM_SIZE);
Matt Briggs 55:79ab0bbc5008 389 if (!nvmReadResult) {
Matt Briggs 55:79ab0bbc5008 390 delete [] data;
Matt Briggs 55:79ab0bbc5008 391 return cmdError;
Matt Briggs 55:79ab0bbc5008 392 }
Matt Briggs 55:79ab0bbc5008 393 mNvmObj.fromBytes(data, BASEBOARDIO_NVM_SIZE);
Matt Briggs 55:79ab0bbc5008 394 delete [] data;
Matt Briggs 55:79ab0bbc5008 395 if (!mNvmObj.validBaseboardIOFlag()) {
Matt Briggs 63:e1efbe3402d9 396 myLogWarning("Invalid BaseboardIO Flag. Using default values.");
Matt Briggs 55:79ab0bbc5008 397 return cmdError;
Matt Briggs 55:79ab0bbc5008 398 }
Matt Briggs 55:79ab0bbc5008 399 else if (!mNvmObj.validBaseboardIORev()) {
Matt Briggs 63:e1efbe3402d9 400 myLogWarning("Invalid BaseboardIO Rev. Using default values.");
Matt Briggs 55:79ab0bbc5008 401 return cmdError;
Matt Briggs 55:79ab0bbc5008 402 }
Matt Briggs 55:79ab0bbc5008 403 else {
Matt Briggs 55:79ab0bbc5008 404 return cmdSuccess;
Matt Briggs 55:79ab0bbc5008 405 }
Matt Briggs 40:2ec4be320961 406 }
Matt Briggs 44:ece6330e9b57 407 CmdResult BaseboardIO::writeInfoToNVM()
Matt Briggs 40:2ec4be320961 408 {
Matt Briggs 55:79ab0bbc5008 409 uint8_t *data = new uint8_t [BASEBOARDIO_NVM_SIZE];
Matt Briggs 55:79ab0bbc5008 410 uint8_t size = BASEBOARDIO_NVM_SIZE;
Matt Briggs 55:79ab0bbc5008 411 mNvmObj.toBytes(data, size);
Matt Briggs 55:79ab0bbc5008 412 dot->nvmWrite(BASEBOARDIO_NVM_START_ADDR, data, BASEBOARDIO_NVM_SIZE);
Matt Briggs 55:79ab0bbc5008 413
Matt Briggs 55:79ab0bbc5008 414 delete [] data;
Matt Briggs 55:79ab0bbc5008 415 return cmdSuccess;
Matt Briggs 40:2ec4be320961 416 }
Matt Briggs 44:ece6330e9b57 417 CmdResult BaseboardIO::identifyPortExpanders()
Matt Briggs 44:ece6330e9b57 418 {
Matt Briggs 44:ece6330e9b57 419 uint8_t addr[8];
Matt Briggs 44:ece6330e9b57 420 uint8_t result;
Matt Briggs 49:18f1354f9e51 421 int i;
Matt Briggs 40:2ec4be320961 422
Matt Briggs 44:ece6330e9b57 423 // Search Bus
Matt Briggs 63:e1efbe3402d9 424 myLogInfo("Starting OneWire Search");
Matt Briggs 49:18f1354f9e51 425 enableSwitchedIO();
Matt Briggs 49:18f1354f9e51 426 for (int j=0;j<10;j++) { // Try 5 times
Matt Briggs 49:18f1354f9e51 427 i=0;
Matt Briggs 49:18f1354f9e51 428 mOWMaster.reset();
Matt Briggs 49:18f1354f9e51 429 mOWMaster.reset_search();
Matt Briggs 49:18f1354f9e51 430 wait(1.0);
Matt Briggs 49:18f1354f9e51 431 while (true) {
Matt Briggs 49:18f1354f9e51 432 // TODO maybe change to family based search
Matt Briggs 49:18f1354f9e51 433 result = mOWMaster.search(addr);
Matt Briggs 49:18f1354f9e51 434 if (result != 1) {
Matt Briggs 49:18f1354f9e51 435 break;
Matt Briggs 49:18f1354f9e51 436 }
Matt Briggs 63:e1efbe3402d9 437 myLogInfo("ROM Addr: %02x:%02x:%02x:%02x:%02x:%02x:%02x%02x found.",
Matt Briggs 49:18f1354f9e51 438 addr[7],addr[6],addr[5],addr[4],addr[3],addr[2],addr[1],addr[0]);
Matt Briggs 49:18f1354f9e51 439 if (i == 0) {
Matt Briggs 55:79ab0bbc5008 440 std::memcpy(mNvmObj.mPortExpanderROM0, addr, sizeof(mNvmObj.mPortExpanderROM0));
Matt Briggs 49:18f1354f9e51 441 }
Matt Briggs 49:18f1354f9e51 442 else if (i == 1) {
Matt Briggs 55:79ab0bbc5008 443 std::memcpy(mNvmObj.mPortExpanderROM1, addr, sizeof(mNvmObj.mPortExpanderROM1));
Matt Briggs 49:18f1354f9e51 444 }
Matt Briggs 49:18f1354f9e51 445 i++;
Matt Briggs 49:18f1354f9e51 446 }
Matt Briggs 49:18f1354f9e51 447 // TODO maybe only allow a reasonable number of Port Expanders
Matt Briggs 49:18f1354f9e51 448 if (i >=2) {
Matt Briggs 44:ece6330e9b57 449 break;
Matt Briggs 44:ece6330e9b57 450 }
Matt Briggs 44:ece6330e9b57 451 }
Matt Briggs 44:ece6330e9b57 452
Matt Briggs 63:e1efbe3402d9 453 myLogInfo("Finished OneWire Search");
Matt Briggs 44:ece6330e9b57 454 if (i != 2) {
Matt Briggs 63:e1efbe3402d9 455 myLogError("Incorrect Number of OneWire devices (Got %d. Expected 2) OneWire port expanders found.", i);
Matt Briggs 44:ece6330e9b57 456 return cmdError;
Matt Briggs 44:ece6330e9b57 457 }
Matt Briggs 44:ece6330e9b57 458
Matt Briggs 49:18f1354f9e51 459 // All rotary switches should be at 0. DIPS should be asserted.
Matt Briggs 44:ece6330e9b57 460 // If switches are set in factory default mode then port expander 1 should read 0xFF and
Matt Briggs 44:ece6330e9b57 461 // port expander 2 should read 0xF0.
Matt Briggs 40:2ec4be320961 462
Matt Briggs 55:79ab0bbc5008 463 mPortEx0 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM0);
Matt Briggs 55:79ab0bbc5008 464 mPortEx1 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM1);
Matt Briggs 44:ece6330e9b57 465
Matt Briggs 49:18f1354f9e51 466
Matt Briggs 49:18f1354f9e51 467 enableSwitchedIO();
Matt Briggs 53:a1563574a980 468 if (mPortEx0->pioLogicReliableRead(mPortExpanderVal0) != cmdSuccess) {
Matt Briggs 63:e1efbe3402d9 469 myLogError("Error during port expander ID. Read failed.");
Matt Briggs 49:18f1354f9e51 470 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 471 delete mPortEx0;
Matt Briggs 44:ece6330e9b57 472 delete mPortEx1;
Matt Briggs 44:ece6330e9b57 473 return cmdError;
Matt Briggs 44:ece6330e9b57 474 }
Matt Briggs 53:a1563574a980 475 if (mPortEx1->pioLogicReliableRead(mPortExpanderVal1) != cmdSuccess) {
Matt Briggs 63:e1efbe3402d9 476 myLogError("Error during port expander ID. Read failed.");
Matt Briggs 49:18f1354f9e51 477 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 478 delete mPortEx0;
Matt Briggs 44:ece6330e9b57 479 delete mPortEx1;
Matt Briggs 44:ece6330e9b57 480 return cmdError;
Matt Briggs 44:ece6330e9b57 481 }
Matt Briggs 44:ece6330e9b57 482
Matt Briggs 49:18f1354f9e51 483 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 484 if ((mPortExpanderVal0 == 0xFF) and (mPortExpanderVal1 == 0xF0)) { // Luckily got it right
Matt Briggs 63:e1efbe3402d9 485 myLogInfo("ROMS Swap Not Needed.");
Matt Briggs 44:ece6330e9b57 486 }
Matt Briggs 44:ece6330e9b57 487 else if ((mPortExpanderVal0 == 0xF0) and (mPortExpanderVal1 == 0xFF)) { // Just need to swap
Matt Briggs 55:79ab0bbc5008 488 std::memcpy(addr, mNvmObj.mPortExpanderROM0, sizeof(addr)); // Store Orig ROM0 -> addr
Matt Briggs 55:79ab0bbc5008 489 std::memcpy(mNvmObj.mPortExpanderROM0, mNvmObj.mPortExpanderROM1, sizeof(mNvmObj.mPortExpanderROM0)); // Store Orig ROM1 -> ROM0
Matt Briggs 55:79ab0bbc5008 490 std::memcpy(mNvmObj.mPortExpanderROM1, addr, sizeof(mNvmObj.mPortExpanderROM1)); // Store Orig ROM0 (addr) -> ROM1
Matt Briggs 63:e1efbe3402d9 491 myLogInfo("Swapped ROMS.");
Matt Briggs 44:ece6330e9b57 492 }
Matt Briggs 44:ece6330e9b57 493 else {
Matt Briggs 63:e1efbe3402d9 494 myLogError("Error during port expander ID. Port expanders not in "
Matt Briggs 55:79ab0bbc5008 495 "expected states (0xFF and 0xF0). Check user switches. Got %02X and %02X",
Matt Briggs 49:18f1354f9e51 496 mPortExpanderVal0, mPortExpanderVal1);
Matt Briggs 44:ece6330e9b57 497 delete mPortEx0;
Matt Briggs 44:ece6330e9b57 498 delete mPortEx1;
Matt Briggs 44:ece6330e9b57 499 return cmdError;
Matt Briggs 44:ece6330e9b57 500 }
Matt Briggs 44:ece6330e9b57 501
Matt Briggs 44:ece6330e9b57 502 // Cleanup
Matt Briggs 44:ece6330e9b57 503 delete mPortEx0;
Matt Briggs 44:ece6330e9b57 504 delete mPortEx1;
Matt Briggs 44:ece6330e9b57 505
Matt Briggs 44:ece6330e9b57 506 return cmdSuccess;
Matt Briggs 40:2ec4be320961 507 }
Matt Briggs 49:18f1354f9e51 508 CmdResult BaseboardIO::openRelay() {
Matt Briggs 44:ece6330e9b57 509 uint8_t val;
Matt Briggs 53:a1563574a980 510 mPortEx1->pioLogicReliableRead(val);
Matt Briggs 44:ece6330e9b57 511
Matt Briggs 49:18f1354f9e51 512 val |= pEx1RlyA; // Make sure Relay A is off
Matt Briggs 49:18f1354f9e51 513 val &= ~pEx1RlyB; // Turn on Relay B
Matt Briggs 44:ece6330e9b57 514
Matt Briggs 53:a1563574a980 515 if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) {
Matt Briggs 49:18f1354f9e51 516 val |= pEx1RlyA; // Turn Relay A off
Matt Briggs 49:18f1354f9e51 517 val |= pEx1RlyB; // Turn Relay B off
Matt Briggs 53:a1563574a980 518 mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask); // Write a non assert value just to try to overcome an error
Matt Briggs 63:e1efbe3402d9 519 myLogError ("Error turning on coil. Turning both coils off.");
Matt Briggs 44:ece6330e9b57 520 return cmdError;
Matt Briggs 44:ece6330e9b57 521 }
Matt Briggs 44:ece6330e9b57 522
Matt Briggs 47:a68747642a7a 523 wait(COIL_ON_TIME);
Matt Briggs 44:ece6330e9b57 524
Matt Briggs 49:18f1354f9e51 525 val |= pEx1RlyA; // Turn Relay A off
Matt Briggs 49:18f1354f9e51 526 val |= pEx1RlyB; // Turn Relay B off
Matt Briggs 44:ece6330e9b57 527
Matt Briggs 53:a1563574a980 528 if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) {
Matt Briggs 53:a1563574a980 529 mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask);
Matt Briggs 63:e1efbe3402d9 530 myLogError ("Error turning off coils. Trying again.");
Matt Briggs 44:ece6330e9b57 531 return cmdError;
Matt Briggs 44:ece6330e9b57 532 }
Matt Briggs 44:ece6330e9b57 533
Matt Briggs 44:ece6330e9b57 534 return cmdSuccess;
Matt Briggs 40:2ec4be320961 535 }
Matt Briggs 49:18f1354f9e51 536 CmdResult BaseboardIO::closeRelay() {
Matt Briggs 44:ece6330e9b57 537 uint8_t val;
Matt Briggs 53:a1563574a980 538 mPortEx1->pioLogicReliableRead(val);
Matt Briggs 44:ece6330e9b57 539
Matt Briggs 49:18f1354f9e51 540 val &= ~pEx1RlyA; // Turn on Relay A
Matt Briggs 49:18f1354f9e51 541 val |= pEx1RlyB; // Make sure Relay B is off
Matt Briggs 44:ece6330e9b57 542
Matt Briggs 53:a1563574a980 543 if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) {
Matt Briggs 49:18f1354f9e51 544 val |= pEx1RlyA; // Turn Relay A off
Matt Briggs 49:18f1354f9e51 545 val |= pEx1RlyB; // Turn Relay B off
Matt Briggs 53:a1563574a980 546 mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask); // Write a non assert value just to try to overcome an error
Matt Briggs 63:e1efbe3402d9 547 myLogError ("Error turning on coil. Turning both coils off.");
Matt Briggs 44:ece6330e9b57 548 return cmdError;
Matt Briggs 44:ece6330e9b57 549 }
Matt Briggs 44:ece6330e9b57 550
Matt Briggs 47:a68747642a7a 551 wait(COIL_ON_TIME);
Matt Briggs 44:ece6330e9b57 552
Matt Briggs 49:18f1354f9e51 553 val |= pEx1RlyA; // Turn Relay A off
Matt Briggs 49:18f1354f9e51 554 val |= pEx1RlyB; // Turn Relay B off
Matt Briggs 44:ece6330e9b57 555
Matt Briggs 53:a1563574a980 556 if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) {
Matt Briggs 53:a1563574a980 557 mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask);
Matt Briggs 63:e1efbe3402d9 558 myLogError ("Error turning off coils. Trying again.");
Matt Briggs 44:ece6330e9b57 559 return cmdError;
Matt Briggs 44:ece6330e9b57 560 }
Matt Briggs 44:ece6330e9b57 561
Matt Briggs 44:ece6330e9b57 562 return cmdSuccess;
Matt Briggs 40:2ec4be320961 563 }
Matt Briggs 55:79ab0bbc5008 564
Matt Briggs 58:15aa7a785b9f 565 CmdResult BaseboardIO::prepareSleep()
Matt Briggs 58:15aa7a785b9f 566 {
Matt Briggs 58:15aa7a785b9f 567 // Save current GPUIO state
Matt Briggs 58:15aa7a785b9f 568 xdot_save_gpio_state();
Matt Briggs 58:15aa7a785b9f 569
Matt Briggs 58:15aa7a785b9f 570 // Configure all IO expect for pins for interrupt in lowest mode possible
Matt Briggs 58:15aa7a785b9f 571 // GPIO Ports Clock Enable
Matt Briggs 58:15aa7a785b9f 572 __GPIOA_CLK_ENABLE();
Matt Briggs 58:15aa7a785b9f 573 __GPIOB_CLK_ENABLE();
Matt Briggs 58:15aa7a785b9f 574 __GPIOC_CLK_ENABLE();
Matt Briggs 58:15aa7a785b9f 575 __GPIOH_CLK_ENABLE();
Matt Briggs 58:15aa7a785b9f 576
Matt Briggs 58:15aa7a785b9f 577 GPIO_InitTypeDef GPIO_InitStruct;
Matt Briggs 58:15aa7a785b9f 578
Matt Briggs 58:15aa7a785b9f 579 // UART1_TX, UART1_RTS & UART1_CTS to analog nopull - RX could be a wakeup source
Matt Briggs 58:15aa7a785b9f 580 // UART1_TX, UART1_RTS & UART1_CTS to analog nopull - RX could be a wakeup source
Matt Briggs 58:15aa7a785b9f 581 // GPIO_InitStruct.Pin = GPIO_PIN_9 | GPIO_PIN_11 | GPIO_PIN_12;
Matt Briggs 58:15aa7a785b9f 582 GPIO_InitStruct.Pin = GPIO_PIN_9 | GPIO_PIN_12;
Matt Briggs 58:15aa7a785b9f 583 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 584 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 585 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 586
Matt Briggs 58:15aa7a785b9f 587 // I2C_SDA & I2C_SCL to analog nopull
Matt Briggs 58:15aa7a785b9f 588 GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9;
Matt Briggs 58:15aa7a785b9f 589 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 590 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 591 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 592
Matt Briggs 58:15aa7a785b9f 593 // SPI_MOSI, SPI_MISO, SPI_SCK, & SPI_NSS to analog nopull
Matt Briggs 58:15aa7a785b9f 594 GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
Matt Briggs 58:15aa7a785b9f 595 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 596 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 597 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 598
Matt Briggs 58:15aa7a785b9f 599 // iterate through potential wake pins - leave the configured wake pin alone if one is needed
Matt Briggs 58:15aa7a785b9f 600 if ((CCInPinName != WAKE && TamperPinName != WAKE && PairBtnPinName != WAKE)
Matt Briggs 58:15aa7a785b9f 601 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 602 GPIO_InitStruct.Pin = GPIO_PIN_0;
Matt Briggs 58:15aa7a785b9f 603 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 604 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 605 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 606 }
Matt Briggs 58:15aa7a785b9f 607 if ((CCInPinName != GPIO0 && TamperPinName != GPIO0 && PairBtnPinName != GPIO0)
Matt Briggs 58:15aa7a785b9f 608 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 609 GPIO_InitStruct.Pin = GPIO_PIN_4;
Matt Briggs 58:15aa7a785b9f 610 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 611 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 612 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 613 }
Matt Briggs 58:15aa7a785b9f 614 if ((CCInPinName != GPIO1 && TamperPinName != GPIO1 && PairBtnPinName != GPIO1)
Matt Briggs 58:15aa7a785b9f 615 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 616 GPIO_InitStruct.Pin = GPIO_PIN_5;
Matt Briggs 58:15aa7a785b9f 617 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 618 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 619 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 620 }
Matt Briggs 58:15aa7a785b9f 621 if ((CCInPinName != GPIO2 && TamperPinName != GPIO2 && PairBtnPinName != GPIO2)
Matt Briggs 58:15aa7a785b9f 622 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 623 GPIO_InitStruct.Pin = GPIO_PIN_0;
Matt Briggs 58:15aa7a785b9f 624 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 625 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 626 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 627 }
Matt Briggs 74:dc969906f1f7 628 // Changed to always do pull down for now.. Should implement discrete pull on new rev
Matt Briggs 74:dc969906f1f7 629 // if ((CCInPinName != GPIO3 && TamperPinName != GPIO3 && PairBtnPinName != GPIO3)
Matt Briggs 74:dc969906f1f7 630 // || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 74:dc969906f1f7 631 // GPIO_InitStruct.Pin = GPIO_PIN_2;
Matt Briggs 74:dc969906f1f7 632 // GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 74:dc969906f1f7 633 // GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 74:dc969906f1f7 634 // HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
Matt Briggs 74:dc969906f1f7 635 // }
Matt Briggs 74:dc969906f1f7 636
Matt Briggs 74:dc969906f1f7 637 // Try doing nothing so that the GPIO3 is still and active output
Matt Briggs 74:dc969906f1f7 638
Matt Briggs 74:dc969906f1f7 639
Matt Briggs 75:600cb3a9f126 640 // Cannot do this and have serial data
Matt Briggs 75:600cb3a9f126 641 // if ((CCInPinName != UART1_RX && TamperPinName != UART1_RX && PairBtnPinName != UART1_RX)
Matt Briggs 75:600cb3a9f126 642 // || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 75:600cb3a9f126 643 // GPIO_InitStruct.Pin = GPIO_PIN_10;
Matt Briggs 75:600cb3a9f126 644 // GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 75:600cb3a9f126 645 // GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 75:600cb3a9f126 646 // HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 75:600cb3a9f126 647 // }
Matt Briggs 58:15aa7a785b9f 648 if ((CCInPinName != UART_CTS && TamperPinName != UART_CTS && PairBtnPinName != UART_CTS)
Matt Briggs 58:15aa7a785b9f 649 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 650 GPIO_InitStruct.Pin = GPIO_PIN_11;
Matt Briggs 58:15aa7a785b9f 651 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 652 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 653 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 654 }
Matt Briggs 58:15aa7a785b9f 655
Matt Briggs 58:15aa7a785b9f 656 return cmdSuccess;
Matt Briggs 58:15aa7a785b9f 657 }
Matt Briggs 58:15aa7a785b9f 658
Matt Briggs 58:15aa7a785b9f 659 CmdResult BaseboardIO::exitSleep()
Matt Briggs 58:15aa7a785b9f 660 {
Matt Briggs 58:15aa7a785b9f 661 xdot_restore_gpio_state();
Matt Briggs 58:15aa7a785b9f 662 return cmdSuccess;
Matt Briggs 58:15aa7a785b9f 663 }
Matt Briggs 58:15aa7a785b9f 664
Matt Briggs 55:79ab0bbc5008 665 // NvmBBIOObj
Matt Briggs 55:79ab0bbc5008 666 NvmBBIOObj::NvmBBIOObj()
Matt Briggs 55:79ab0bbc5008 667 {
Matt Briggs 55:79ab0bbc5008 668 setDefaults();
Matt Briggs 55:79ab0bbc5008 669 }
Matt Briggs 55:79ab0bbc5008 670 void NvmBBIOObj::setDefaults()
Matt Briggs 55:79ab0bbc5008 671 {
Matt Briggs 55:79ab0bbc5008 672 mBaseboardIOFlag = BASEBOARDIO_FLAG;
Matt Briggs 55:79ab0bbc5008 673 mBaseboardIORev = BASEBOARDIO_REV;
Matt Briggs 55:79ab0bbc5008 674 mSerialNum = 0x0000;
Matt Briggs 55:79ab0bbc5008 675 mBaseboardIOConfig = 0x0000;
Matt Briggs 55:79ab0bbc5008 676 std::memset(mPortExpanderROM0, 0x00, 8);
Matt Briggs 55:79ab0bbc5008 677 std::memset(mPortExpanderROM1, 0x00, 8);
Matt Briggs 55:79ab0bbc5008 678 }
Matt Briggs 55:79ab0bbc5008 679 CmdResult NvmBBIOObj::fromBytes(uint8_t *data, uint8_t size)
Matt Briggs 55:79ab0bbc5008 680 {
Matt Briggs 55:79ab0bbc5008 681 if (size != BASEBOARDIO_NVM_SIZE) {
Matt Briggs 55:79ab0bbc5008 682 return cmdError;
Matt Briggs 55:79ab0bbc5008 683 }
Matt Briggs 55:79ab0bbc5008 684
Matt Briggs 55:79ab0bbc5008 685 mBaseboardIOFlag = *((uint16_t *) (data));
Matt Briggs 55:79ab0bbc5008 686 mBaseboardIORev = *((uint16_t *) (data+2));
Matt Briggs 55:79ab0bbc5008 687 mSerialNum = *((uint32_t *) (data+4));
Matt Briggs 55:79ab0bbc5008 688 mBaseboardIOConfig = *((uint32_t *) (data+6));
Matt Briggs 55:79ab0bbc5008 689
Matt Briggs 55:79ab0bbc5008 690 std::memcpy(&mPortExpanderROM0, data+0x10, 8);
Matt Briggs 55:79ab0bbc5008 691 std::memcpy(&mPortExpanderROM1, data+0x18, 8);
Matt Briggs 55:79ab0bbc5008 692
Matt Briggs 55:79ab0bbc5008 693 return cmdSuccess;
Matt Briggs 55:79ab0bbc5008 694 }
Matt Briggs 55:79ab0bbc5008 695 CmdResult NvmBBIOObj::toBytes(uint8_t *data, uint8_t &size) {
Matt Briggs 55:79ab0bbc5008 696 // TODO check data size
Matt Briggs 55:79ab0bbc5008 697
Matt Briggs 55:79ab0bbc5008 698 *((uint16_t *) (data)) = mBaseboardIOFlag;
Matt Briggs 55:79ab0bbc5008 699 *((uint16_t *) (data+2)) = mBaseboardIORev;
Matt Briggs 55:79ab0bbc5008 700 *((uint32_t *) (data+4)) = mSerialNum;
Matt Briggs 55:79ab0bbc5008 701 *((uint32_t *) (data+6)) = mBaseboardIOConfig;
Matt Briggs 55:79ab0bbc5008 702
Matt Briggs 55:79ab0bbc5008 703 std::memcpy(data+0x10, &mPortExpanderROM0, 8);
Matt Briggs 55:79ab0bbc5008 704 std::memcpy(data+0x18, &mPortExpanderROM1, 8);
Matt Briggs 55:79ab0bbc5008 705
Matt Briggs 55:79ab0bbc5008 706 size = BASEBOARDIO_NVM_SIZE;
Matt Briggs 55:79ab0bbc5008 707
Matt Briggs 55:79ab0bbc5008 708 return cmdSuccess;
Matt Briggs 55:79ab0bbc5008 709 }
Matt Briggs 55:79ab0bbc5008 710 uint16_t NvmBBIOObj::getBaseboardIOFlag()
Matt Briggs 55:79ab0bbc5008 711 {
Matt Briggs 55:79ab0bbc5008 712 return mBaseboardIOFlag;
Matt Briggs 55:79ab0bbc5008 713 }
Matt Briggs 55:79ab0bbc5008 714 bool NvmBBIOObj::validBaseboardIOFlag()
Matt Briggs 55:79ab0bbc5008 715 {
Matt Briggs 55:79ab0bbc5008 716 return mBaseboardIOFlag == BASEBOARDIO_FLAG;
Matt Briggs 55:79ab0bbc5008 717 }
Matt Briggs 55:79ab0bbc5008 718 uint16_t NvmBBIOObj::getBaseboardIORev()
Matt Briggs 55:79ab0bbc5008 719 {
Matt Briggs 55:79ab0bbc5008 720 return mBaseboardIORev;
Matt Briggs 55:79ab0bbc5008 721 }
Matt Briggs 55:79ab0bbc5008 722 bool NvmBBIOObj::validBaseboardIORev()
Matt Briggs 55:79ab0bbc5008 723 {
Matt Briggs 55:79ab0bbc5008 724 return mBaseboardIORev == BASEBOARDIO_REV;
Matt Briggs 55:79ab0bbc5008 725 }
Matt Briggs 55:79ab0bbc5008 726 uint16_t NvmBBIOObj::getSerialNum()
Matt Briggs 55:79ab0bbc5008 727 {
Matt Briggs 55:79ab0bbc5008 728 return mSerialNum;
Matt Briggs 55:79ab0bbc5008 729 }
Matt Briggs 55:79ab0bbc5008 730 void NvmBBIOObj::setSerialNum(uint16_t in)
Matt Briggs 55:79ab0bbc5008 731 {
Matt Briggs 55:79ab0bbc5008 732 mSerialNum = in;
Matt Briggs 55:79ab0bbc5008 733 }
Matt Briggs 55:79ab0bbc5008 734 uint32_t NvmBBIOObj::getBaseboardIOConfig()
Matt Briggs 55:79ab0bbc5008 735 {
Matt Briggs 55:79ab0bbc5008 736 return mBaseboardIOConfig;
Matt Briggs 55:79ab0bbc5008 737 }
Matt Briggs 55:79ab0bbc5008 738 void NvmBBIOObj::setBaseboardIOConfig(uint32_t in)
Matt Briggs 55:79ab0bbc5008 739 {
Matt Briggs 55:79ab0bbc5008 740 mBaseboardIOConfig = in;
Matt Briggs 55:79ab0bbc5008 741 }
Matt Briggs 55:79ab0bbc5008 742 void NvmBBIOObj::getPortExpanderROM0(uint8_t *addr)
Matt Briggs 55:79ab0bbc5008 743 {
Matt Briggs 55:79ab0bbc5008 744 std::memcpy(addr, &mPortExpanderROM0, 8);
Matt Briggs 55:79ab0bbc5008 745 }
Matt Briggs 55:79ab0bbc5008 746 void NvmBBIOObj::setPortExpanderROM0(const uint8_t *addr)
Matt Briggs 55:79ab0bbc5008 747 {
Matt Briggs 55:79ab0bbc5008 748 std::memcpy(&mPortExpanderROM0, addr, 8);
Matt Briggs 55:79ab0bbc5008 749 }
Matt Briggs 55:79ab0bbc5008 750 void NvmBBIOObj::getPortExpanderROM1(uint8_t *addr)
Matt Briggs 55:79ab0bbc5008 751 {
Matt Briggs 55:79ab0bbc5008 752 std::memcpy(addr, &mPortExpanderROM1, 8);
Matt Briggs 55:79ab0bbc5008 753 }
Matt Briggs 55:79ab0bbc5008 754 void NvmBBIOObj::setPortExpanderROM1(const uint8_t *addr)
Matt Briggs 55:79ab0bbc5008 755 {
Matt Briggs 55:79ab0bbc5008 756 std::memcpy(&mPortExpanderROM1, addr, 8);
Matt Briggs 55:79ab0bbc5008 757 }