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Fork to see if I can get working
Dependencies: BufferedSerial OneWire WinbondSPIFlash libxDot-dev-mbed5-deprecated
Fork of xDotBridge_update_test20180823 by
xDotBridge/src/BaseboardIO.cpp@56:40b454c952cc, 2017-02-27 (annotated)
- Committer:
- Matt Briggs
- Date:
- Mon Feb 27 14:06:54 2017 -0700
- Revision:
- 56:40b454c952cc
- Parent:
- 55:79ab0bbc5008
- Child:
- 57:bdac7dd17af2
Updated test BBIO to v3. Added some sanity checks for LRR if on a new board.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Matt Briggs | 40:2ec4be320961 | 1 | /* |
Matt Briggs | 40:2ec4be320961 | 2 | * baseboardIO.cpp |
Matt Briggs | 40:2ec4be320961 | 3 | * |
Matt Briggs | 40:2ec4be320961 | 4 | * Created on: Jan 25, 2017 |
Matt Briggs | 40:2ec4be320961 | 5 | * Author: mbriggs |
Matt Briggs | 40:2ec4be320961 | 6 | */ |
Matt Briggs | 40:2ec4be320961 | 7 | |
Matt Briggs | 40:2ec4be320961 | 8 | #include "BaseboardIO.h" |
Matt Briggs | 41:9ef4c4d77711 | 9 | #include "MTSLog.h" |
Matt Briggs | 55:79ab0bbc5008 | 10 | #include "dot_util.h" // FIXME just need the reference to dot somehow |
Matt Briggs | 40:2ec4be320961 | 11 | |
Matt Briggs | 47:a68747642a7a | 12 | const float COIL_ON_TIME = 0.030; // 30 ms |
Matt Briggs | 44:ece6330e9b57 | 13 | |
Matt Briggs | 49:18f1354f9e51 | 14 | // Port expander 0 (Currently U7) |
Matt Briggs | 44:ece6330e9b57 | 15 | const uint8_t pEx0232En = 0x01; |
Matt Briggs | 44:ece6330e9b57 | 16 | const uint8_t pEx0232TxDis = 0x02; |
Matt Briggs | 44:ece6330e9b57 | 17 | const uint8_t pEx0Rot1B1 = 0x04; |
Matt Briggs | 44:ece6330e9b57 | 18 | const uint8_t pEx0Rot1B2 = 0x08; |
Matt Briggs | 44:ece6330e9b57 | 19 | const uint8_t pEx0Rot1B4 = 0x10; |
Matt Briggs | 44:ece6330e9b57 | 20 | const uint8_t pEx0Rot1B8 = 0x20; |
Matt Briggs | 44:ece6330e9b57 | 21 | const uint8_t pEx0Rot2B1 = 0x40; |
Matt Briggs | 44:ece6330e9b57 | 22 | const uint8_t pEx0Rot2B2 = 0x80; |
Matt Briggs | 49:18f1354f9e51 | 23 | const uint8_t pEx0OutMask = 0x03; // Only allow bits 0,1 to be changed |
Matt Briggs | 44:ece6330e9b57 | 24 | |
Matt Briggs | 49:18f1354f9e51 | 25 | // Port expander 1 (Currently U8) |
Matt Briggs | 44:ece6330e9b57 | 26 | const uint8_t pEx1NoNcSel = 0x01; |
Matt Briggs | 44:ece6330e9b57 | 27 | const uint8_t pEx1RxTxSel = 0x02; |
Matt Briggs | 44:ece6330e9b57 | 28 | const uint8_t pEx1WanSel = 0x04; |
Matt Briggs | 44:ece6330e9b57 | 29 | const uint8_t pEx1SerialEn = 0x08; // Labeled as reserved |
Matt Briggs | 44:ece6330e9b57 | 30 | const uint8_t pEx1Rot2B8 = 0x10; |
Matt Briggs | 44:ece6330e9b57 | 31 | const uint8_t pEx1Rot2B4 = 0x20; |
Matt Briggs | 44:ece6330e9b57 | 32 | const uint8_t pEx1RlyB = 0x40; // This is actually a coil |
Matt Briggs | 44:ece6330e9b57 | 33 | const uint8_t pEx1RlyA = 0x80; // This is actually a coil |
Matt Briggs | 49:18f1354f9e51 | 34 | const uint8_t pEx1OutMask = 0xC0; // Only allow bits 6,7 to be changed |
Matt Briggs | 44:ece6330e9b57 | 35 | |
Matt Briggs | 44:ece6330e9b57 | 36 | /** |
Matt Briggs | 44:ece6330e9b57 | 37 | * Note for interrupt within uC cannot use two pins with the same numeric suffix (e.g. cannot |
Matt Briggs | 44:ece6330e9b57 | 38 | * use both PA_0 and PB_0). Note 1, 6, 7, 8, and 13 are used by LoRa radio. |
Matt Briggs | 44:ece6330e9b57 | 39 | */ |
Matt Briggs | 44:ece6330e9b57 | 40 | |
Matt Briggs | 40:2ec4be320961 | 41 | BaseboardIO::BaseboardIO() |
Matt Briggs | 44:ece6330e9b57 | 42 | : mOWMaster(I2C_SDA), |
Matt Briggs | 44:ece6330e9b57 | 43 | mCCIn(WAKE), // Interrupt pin PA_0 |
Matt Briggs | 44:ece6330e9b57 | 44 | mTamper(GPIO1), // Interrupt pin PA_5 |
Matt Briggs | 44:ece6330e9b57 | 45 | mPairBtn(UART_CTS), // Interrupt pin PA_11 |
Matt Briggs | 48:bab9f747d9ed | 46 | // mLed(SWDIO), |
Matt Briggs | 48:bab9f747d9ed | 47 | mLed(GPIO0), |
Matt Briggs | 49:18f1354f9e51 | 48 | mSwitchedIOCtrl(I2C_SCL, 0) |
Matt Briggs | 40:2ec4be320961 | 49 | { |
Matt Briggs | 44:ece6330e9b57 | 50 | mPortExpanderVal0 = 0x00; |
Matt Briggs | 44:ece6330e9b57 | 51 | mPortExpanderVal1 = 0x00; |
Matt Briggs | 44:ece6330e9b57 | 52 | |
Matt Briggs | 44:ece6330e9b57 | 53 | mPortEx0 = NULL; |
Matt Briggs | 44:ece6330e9b57 | 54 | mPortEx1 = NULL; |
Matt Briggs | 40:2ec4be320961 | 55 | } |
Matt Briggs | 56:40b454c952cc | 56 | CmdResult BaseboardIO::init(bool overwriteNvm) |
Matt Briggs | 40:2ec4be320961 | 57 | { |
Matt Briggs | 56:40b454c952cc | 58 | bool storedROMsGood = false; |
Matt Briggs | 56:40b454c952cc | 59 | uint8_t val; |
Matt Briggs | 44:ece6330e9b57 | 60 | // Setup port expanders |
Matt Briggs | 56:40b454c952cc | 61 | if (readInfoFromNVM() == cmdSuccess && !overwriteNvm) { |
Matt Briggs | 55:79ab0bbc5008 | 62 | logInfo("Stored ROM0 Addr: %02x:%02x:%02x:%02x:%02x:%02x:%02x%02x found.", |
Matt Briggs | 55:79ab0bbc5008 | 63 | mNvmObj.mPortExpanderROM0[7], |
Matt Briggs | 55:79ab0bbc5008 | 64 | mNvmObj.mPortExpanderROM0[6], |
Matt Briggs | 55:79ab0bbc5008 | 65 | mNvmObj.mPortExpanderROM0[5], |
Matt Briggs | 55:79ab0bbc5008 | 66 | mNvmObj.mPortExpanderROM0[4], |
Matt Briggs | 55:79ab0bbc5008 | 67 | mNvmObj.mPortExpanderROM0[3], |
Matt Briggs | 55:79ab0bbc5008 | 68 | mNvmObj.mPortExpanderROM0[2], |
Matt Briggs | 55:79ab0bbc5008 | 69 | mNvmObj.mPortExpanderROM0[1], |
Matt Briggs | 55:79ab0bbc5008 | 70 | mNvmObj.mPortExpanderROM0[0]); |
Matt Briggs | 55:79ab0bbc5008 | 71 | logInfo("Stored ROM1 Addr: %02x:%02x:%02x:%02x:%02x:%02x:%02x%02x found.", |
Matt Briggs | 55:79ab0bbc5008 | 72 | mNvmObj.mPortExpanderROM1[7], |
Matt Briggs | 55:79ab0bbc5008 | 73 | mNvmObj.mPortExpanderROM1[6], |
Matt Briggs | 55:79ab0bbc5008 | 74 | mNvmObj.mPortExpanderROM1[5], |
Matt Briggs | 55:79ab0bbc5008 | 75 | mNvmObj.mPortExpanderROM1[4], |
Matt Briggs | 55:79ab0bbc5008 | 76 | mNvmObj.mPortExpanderROM1[3], |
Matt Briggs | 55:79ab0bbc5008 | 77 | mNvmObj.mPortExpanderROM1[2], |
Matt Briggs | 55:79ab0bbc5008 | 78 | mNvmObj.mPortExpanderROM1[1], |
Matt Briggs | 55:79ab0bbc5008 | 79 | mNvmObj.mPortExpanderROM1[0]); |
Matt Briggs | 55:79ab0bbc5008 | 80 | logInfo("BaseboardIO parameters successfully loaded from NVM"); |
Matt Briggs | 56:40b454c952cc | 81 | // Check that the ROM Addresses are correct and valid |
Matt Briggs | 56:40b454c952cc | 82 | uint8_t portEx0Ctrl, portEx1Ctrl; |
Matt Briggs | 56:40b454c952cc | 83 | mPortEx0 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM0); |
Matt Briggs | 56:40b454c952cc | 84 | mPortEx0->registerReadReliable(0x8D, portEx0Ctrl); |
Matt Briggs | 56:40b454c952cc | 85 | // Gets 0xFF if it is not the correct address |
Matt Briggs | 56:40b454c952cc | 86 | logInfo("PortEx0 Control register reads %02X", portEx0Ctrl); |
Matt Briggs | 56:40b454c952cc | 87 | |
Matt Briggs | 56:40b454c952cc | 88 | mPortEx1 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM1); |
Matt Briggs | 56:40b454c952cc | 89 | mPortEx1->registerReadReliable(0x8D, portEx1Ctrl); |
Matt Briggs | 56:40b454c952cc | 90 | logInfo("PortEx1 Control register reads %02X", portEx1Ctrl); |
Matt Briggs | 56:40b454c952cc | 91 | if ((portEx0Ctrl == 0xFF) || (portEx1Ctrl == 0xFF)) { |
Matt Briggs | 56:40b454c952cc | 92 | logError("Stored port expander ROM check failed. Set EEPROM to defaults."); |
Matt Briggs | 56:40b454c952cc | 93 | } |
Matt Briggs | 56:40b454c952cc | 94 | else { |
Matt Briggs | 56:40b454c952cc | 95 | storedROMsGood = true; |
Matt Briggs | 56:40b454c952cc | 96 | } |
Matt Briggs | 44:ece6330e9b57 | 97 | } |
Matt Briggs | 56:40b454c952cc | 98 | if (!storedROMsGood) |
Matt Briggs | 56:40b454c952cc | 99 | { // EEPROM values not there or corrupt. Should only happen in factory. |
Matt Briggs | 55:79ab0bbc5008 | 100 | mNvmObj.setDefaults(); |
Matt Briggs | 47:a68747642a7a | 101 | // Find ROM address and test which one is which. Requires user |
Matt Briggs | 47:a68747642a7a | 102 | // switches to be in known state. |
Matt Briggs | 47:a68747642a7a | 103 | if (identifyPortExpanders() != cmdSuccess) { |
Matt Briggs | 44:ece6330e9b57 | 104 | logError("Error identifying port expanders"); |
Matt Briggs | 44:ece6330e9b57 | 105 | return cmdError; |
Matt Briggs | 44:ece6330e9b57 | 106 | } |
Matt Briggs | 55:79ab0bbc5008 | 107 | if (writeInfoToNVM() == cmdSuccess) { |
Matt Briggs | 55:79ab0bbc5008 | 108 | logInfo("Baseboard config saved to NVM"); |
Matt Briggs | 55:79ab0bbc5008 | 109 | } |
Matt Briggs | 55:79ab0bbc5008 | 110 | else { |
Matt Briggs | 55:79ab0bbc5008 | 111 | logError("Baseboard config failed to save to NVM"); |
Matt Briggs | 55:79ab0bbc5008 | 112 | } |
Matt Briggs | 56:40b454c952cc | 113 | mPortEx0 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM0); |
Matt Briggs | 56:40b454c952cc | 114 | mPortEx0->registerReadReliable(0x8D, val); |
Matt Briggs | 56:40b454c952cc | 115 | // Gets 0xFF if it is not the correct address |
Matt Briggs | 56:40b454c952cc | 116 | logInfo("PortEx0 Control register reads %02X", val); |
Matt Briggs | 56:40b454c952cc | 117 | mPortEx1 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM1); |
Matt Briggs | 56:40b454c952cc | 118 | mPortEx1->registerReadReliable(0x8D, val); |
Matt Briggs | 56:40b454c952cc | 119 | logInfo("PortEx1 Control register reads %02X", val); |
Matt Briggs | 44:ece6330e9b57 | 120 | } |
Matt Briggs | 44:ece6330e9b57 | 121 | |
Matt Briggs | 44:ece6330e9b57 | 122 | // Put relay in known state |
Matt Briggs | 47:a68747642a7a | 123 | if (relayNormal() != cmdSuccess) { |
Matt Briggs | 47:a68747642a7a | 124 | logError("Error setting relay during init"); |
Matt Briggs | 47:a68747642a7a | 125 | return cmdError; |
Matt Briggs | 47:a68747642a7a | 126 | } |
Matt Briggs | 47:a68747642a7a | 127 | |
Matt Briggs | 47:a68747642a7a | 128 | if (sampleUserSwitches() != cmdSuccess) { |
Matt Briggs | 47:a68747642a7a | 129 | logError("Error sampling user switches"); |
Matt Briggs | 47:a68747642a7a | 130 | return cmdError; |
Matt Briggs | 47:a68747642a7a | 131 | } |
Matt Briggs | 44:ece6330e9b57 | 132 | |
Matt Briggs | 44:ece6330e9b57 | 133 | logInfo("Baseboard IO initialization successful"); |
Matt Briggs | 44:ece6330e9b57 | 134 | return cmdSuccess; |
Matt Briggs | 40:2ec4be320961 | 135 | } |
Matt Briggs | 40:2ec4be320961 | 136 | |
Matt Briggs | 40:2ec4be320961 | 137 | // Registering for interrupts |
Matt Briggs | 44:ece6330e9b57 | 138 | void BaseboardIO::regCCInInt(Callback<void()> func) |
Matt Briggs | 40:2ec4be320961 | 139 | { |
Matt Briggs | 48:bab9f747d9ed | 140 | sampleUserSwitches(); |
Matt Briggs | 48:bab9f747d9ed | 141 | if (isCCNO()) { |
Matt Briggs | 48:bab9f747d9ed | 142 | // Pulled high, switched low |
Matt Briggs | 48:bab9f747d9ed | 143 | mCCIn.fall(func); |
Matt Briggs | 48:bab9f747d9ed | 144 | } |
Matt Briggs | 48:bab9f747d9ed | 145 | else { |
Matt Briggs | 48:bab9f747d9ed | 146 | mCCIn.rise(func); |
Matt Briggs | 48:bab9f747d9ed | 147 | } |
Matt Briggs | 53:a1563574a980 | 148 | mCCIn.mode(PullNone); |
Matt Briggs | 49:18f1354f9e51 | 149 | mCCIn.enable_irq(); |
Matt Briggs | 40:2ec4be320961 | 150 | } |
Matt Briggs | 44:ece6330e9b57 | 151 | void BaseboardIO::regTamperInt(Callback<void()> func) |
Matt Briggs | 40:2ec4be320961 | 152 | { |
Matt Briggs | 44:ece6330e9b57 | 153 | // Pulled high, switched low |
Matt Briggs | 53:a1563574a980 | 154 | mTamper.mode(PullNone); |
Matt Briggs | 49:18f1354f9e51 | 155 | mTamper.rise(func); |
Matt Briggs | 44:ece6330e9b57 | 156 | mTamper.fall(func); |
Matt Briggs | 49:18f1354f9e51 | 157 | mTamper.enable_irq(); |
Matt Briggs | 40:2ec4be320961 | 158 | } |
Matt Briggs | 44:ece6330e9b57 | 159 | void BaseboardIO::regPairBtnInt(Callback<void()> func) |
Matt Briggs | 40:2ec4be320961 | 160 | { |
Matt Briggs | 44:ece6330e9b57 | 161 | // Pulled low, switched high |
Matt Briggs | 49:18f1354f9e51 | 162 | mPairBtn.mode(PullDown); |
Matt Briggs | 44:ece6330e9b57 | 163 | mPairBtn.rise(func); |
Matt Briggs | 49:18f1354f9e51 | 164 | mPairBtn.enable_irq(); |
Matt Briggs | 40:2ec4be320961 | 165 | } |
Matt Briggs | 40:2ec4be320961 | 166 | |
Matt Briggs | 40:2ec4be320961 | 167 | // Input |
Matt Briggs | 40:2ec4be320961 | 168 | CmdResult BaseboardIO::sampleUserSwitches() |
Matt Briggs | 40:2ec4be320961 | 169 | { |
Matt Briggs | 48:bab9f747d9ed | 170 | if ((mPortEx0 == NULL) || (mPortEx1 == NULL)) |
Matt Briggs | 48:bab9f747d9ed | 171 | return cmdError; |
Matt Briggs | 44:ece6330e9b57 | 172 | // Sample port expanders |
Matt Briggs | 49:18f1354f9e51 | 173 | enableSwitchedIO(); |
Matt Briggs | 49:18f1354f9e51 | 174 | wait(0.001); // Wait 1 ms |
Matt Briggs | 53:a1563574a980 | 175 | if (mPortEx0->pioLogicReliableRead(mPortExpanderVal0) != cmdSuccess) { |
Matt Briggs | 49:18f1354f9e51 | 176 | disableSwitchedIO(); |
Matt Briggs | 44:ece6330e9b57 | 177 | logError("Error reading port expander 0."); |
Matt Briggs | 44:ece6330e9b57 | 178 | return cmdError; |
Matt Briggs | 44:ece6330e9b57 | 179 | } |
Matt Briggs | 53:a1563574a980 | 180 | if (mPortEx1->pioLogicReliableRead(mPortExpanderVal1) != cmdSuccess) { |
Matt Briggs | 49:18f1354f9e51 | 181 | disableSwitchedIO(); |
Matt Briggs | 44:ece6330e9b57 | 182 | logError("Error reading port expander 1."); |
Matt Briggs | 44:ece6330e9b57 | 183 | return cmdError; |
Matt Briggs | 44:ece6330e9b57 | 184 | } |
Matt Briggs | 49:18f1354f9e51 | 185 | disableSwitchedIO(); |
Matt Briggs | 44:ece6330e9b57 | 186 | return cmdSuccess; |
Matt Briggs | 40:2ec4be320961 | 187 | } |
Matt Briggs | 40:2ec4be320961 | 188 | bool BaseboardIO::isPairBtn() |
Matt Briggs | 40:2ec4be320961 | 189 | { |
Matt Briggs | 44:ece6330e9b57 | 190 | // Depressed button is high |
Matt Briggs | 44:ece6330e9b57 | 191 | return mPairBtn.read() == 1; |
Matt Briggs | 40:2ec4be320961 | 192 | } |
Matt Briggs | 48:bab9f747d9ed | 193 | bool BaseboardIO::isCCNO() |
Matt Briggs | 40:2ec4be320961 | 194 | { |
Matt Briggs | 44:ece6330e9b57 | 195 | // When DIP switch is not closed (i.e. value reads high) assume NO |
Matt Briggs | 49:18f1354f9e51 | 196 | return (mPortExpanderVal1 & pEx1NoNcSel) != 0; // Open NO, closed NC |
Matt Briggs | 40:2ec4be320961 | 197 | } |
Matt Briggs | 40:2ec4be320961 | 198 | bool BaseboardIO::isRx() |
Matt Briggs | 40:2ec4be320961 | 199 | { |
Matt Briggs | 44:ece6330e9b57 | 200 | // When DIP switch is not closed (i.e. value reads high) assume RX |
Matt Briggs | 44:ece6330e9b57 | 201 | return (mPortExpanderVal1 & pEx1RxTxSel) != 0; |
Matt Briggs | 40:2ec4be320961 | 202 | } |
Matt Briggs | 40:2ec4be320961 | 203 | bool BaseboardIO::isLoRaWANMode() |
Matt Briggs | 40:2ec4be320961 | 204 | { |
Matt Briggs | 44:ece6330e9b57 | 205 | // When DIP switch is not closed (i.e. value reads high) assume P2P not WAN |
Matt Briggs | 44:ece6330e9b57 | 206 | return (mPortExpanderVal1 & pEx1WanSel) == 0; |
Matt Briggs | 40:2ec4be320961 | 207 | } |
Matt Briggs | 50:e89647e77fd5 | 208 | bool BaseboardIO::isSerialEnabled() |
Matt Briggs | 50:e89647e77fd5 | 209 | { |
Matt Briggs | 50:e89647e77fd5 | 210 | // When DIP switch is not closed (i.e. value reads high) assume not in serial mode |
Matt Briggs | 50:e89647e77fd5 | 211 | return (mPortExpanderVal1 & pEx1SerialEn) == 0; |
Matt Briggs | 50:e89647e77fd5 | 212 | } |
Matt Briggs | 40:2ec4be320961 | 213 | uint8_t BaseboardIO::rotarySwitch1() |
Matt Briggs | 40:2ec4be320961 | 214 | { |
Matt Briggs | 44:ece6330e9b57 | 215 | // If a bit of a nibble is asserted then the port expander line is switched low. |
Matt Briggs | 44:ece6330e9b57 | 216 | uint8_t val = 0; |
Matt Briggs | 44:ece6330e9b57 | 217 | if ((mPortExpanderVal0 & pEx0Rot1B8) == 0) |
Matt Briggs | 44:ece6330e9b57 | 218 | val |= 0x08; |
Matt Briggs | 44:ece6330e9b57 | 219 | if ((mPortExpanderVal0 & pEx0Rot1B4) == 0) |
Matt Briggs | 44:ece6330e9b57 | 220 | val |= 0x04; |
Matt Briggs | 44:ece6330e9b57 | 221 | if ((mPortExpanderVal0 & pEx0Rot1B2) == 0) |
Matt Briggs | 44:ece6330e9b57 | 222 | val |= 0x02; |
Matt Briggs | 44:ece6330e9b57 | 223 | if ((mPortExpanderVal0 & pEx0Rot1B1) == 0) |
Matt Briggs | 44:ece6330e9b57 | 224 | val |= 0x01; |
Matt Briggs | 44:ece6330e9b57 | 225 | return val; |
Matt Briggs | 40:2ec4be320961 | 226 | } |
Matt Briggs | 40:2ec4be320961 | 227 | uint8_t BaseboardIO::rotarySwitch2() |
Matt Briggs | 40:2ec4be320961 | 228 | { |
Matt Briggs | 44:ece6330e9b57 | 229 | // If a bit of a nibble is asserted then the port expander line is switched low. |
Matt Briggs | 44:ece6330e9b57 | 230 | uint8_t val = 0; |
Matt Briggs | 44:ece6330e9b57 | 231 | if ((mPortExpanderVal1 & pEx1Rot2B8) == 0) |
Matt Briggs | 44:ece6330e9b57 | 232 | val |= 0x08; |
Matt Briggs | 44:ece6330e9b57 | 233 | if ((mPortExpanderVal1 & pEx1Rot2B4) == 0) |
Matt Briggs | 44:ece6330e9b57 | 234 | val |= 0x04; |
Matt Briggs | 44:ece6330e9b57 | 235 | if ((mPortExpanderVal0 & pEx0Rot2B2) == 0) |
Matt Briggs | 44:ece6330e9b57 | 236 | val |= 0x02; |
Matt Briggs | 44:ece6330e9b57 | 237 | if ((mPortExpanderVal0 & pEx0Rot2B1) == 0) |
Matt Briggs | 44:ece6330e9b57 | 238 | val |= 0x01; |
Matt Briggs | 44:ece6330e9b57 | 239 | return val; |
Matt Briggs | 40:2ec4be320961 | 240 | } |
Matt Briggs | 40:2ec4be320961 | 241 | |
Matt Briggs | 40:2ec4be320961 | 242 | // Output |
Matt Briggs | 40:2ec4be320961 | 243 | CmdResult BaseboardIO::ledOn() |
Matt Briggs | 40:2ec4be320961 | 244 | { |
Matt Briggs | 44:ece6330e9b57 | 245 | mLed = 1; |
Matt Briggs | 44:ece6330e9b57 | 246 | return cmdSuccess; |
Matt Briggs | 40:2ec4be320961 | 247 | } |
Matt Briggs | 40:2ec4be320961 | 248 | CmdResult BaseboardIO::ledOff() |
Matt Briggs | 40:2ec4be320961 | 249 | { |
Matt Briggs | 44:ece6330e9b57 | 250 | mLed = 0; |
Matt Briggs | 44:ece6330e9b57 | 251 | return cmdSuccess; |
Matt Briggs | 40:2ec4be320961 | 252 | } |
Matt Briggs | 40:2ec4be320961 | 253 | CmdResult BaseboardIO::relayAlert() |
Matt Briggs | 40:2ec4be320961 | 254 | { |
Matt Briggs | 48:bab9f747d9ed | 255 | if (isCCNO()) { // Normally Open |
Matt Briggs | 44:ece6330e9b57 | 256 | return closeRelay(); |
Matt Briggs | 44:ece6330e9b57 | 257 | } |
Matt Briggs | 44:ece6330e9b57 | 258 | else { // Normally Close |
Matt Briggs | 44:ece6330e9b57 | 259 | return openRelay(); |
Matt Briggs | 44:ece6330e9b57 | 260 | } |
Matt Briggs | 40:2ec4be320961 | 261 | } |
Matt Briggs | 40:2ec4be320961 | 262 | CmdResult BaseboardIO::relayNormal() |
Matt Briggs | 40:2ec4be320961 | 263 | { |
Matt Briggs | 48:bab9f747d9ed | 264 | if (isCCNO()) { // Normally Open |
Matt Briggs | 44:ece6330e9b57 | 265 | return openRelay(); |
Matt Briggs | 44:ece6330e9b57 | 266 | } |
Matt Briggs | 44:ece6330e9b57 | 267 | else { // Normally Close |
Matt Briggs | 44:ece6330e9b57 | 268 | return closeRelay(); |
Matt Briggs | 44:ece6330e9b57 | 269 | } |
Matt Briggs | 40:2ec4be320961 | 270 | } |
Matt Briggs | 40:2ec4be320961 | 271 | |
Matt Briggs | 40:2ec4be320961 | 272 | // Future |
Matt Briggs | 40:2ec4be320961 | 273 | CmdResult BaseboardIO::serialRx(bool enable) |
Matt Briggs | 40:2ec4be320961 | 274 | { |
Matt Briggs | 44:ece6330e9b57 | 275 | uint8_t val; |
Matt Briggs | 49:18f1354f9e51 | 276 | if (mPortEx0 == NULL) { |
Matt Briggs | 49:18f1354f9e51 | 277 | logError("Error enabling 232. Port expanders not initialized."); |
Matt Briggs | 49:18f1354f9e51 | 278 | return cmdError; |
Matt Briggs | 49:18f1354f9e51 | 279 | } |
Matt Briggs | 53:a1563574a980 | 280 | mPortEx0->pioLogicReliableRead(val); |
Matt Briggs | 44:ece6330e9b57 | 281 | |
Matt Briggs | 44:ece6330e9b57 | 282 | // Active low from port expander -> pmos -> 232 (active chip EN) |
Matt Briggs | 44:ece6330e9b57 | 283 | if (enable) { |
Matt Briggs | 44:ece6330e9b57 | 284 | val &= ~pEx0232En; |
Matt Briggs | 44:ece6330e9b57 | 285 | } |
Matt Briggs | 44:ece6330e9b57 | 286 | else { |
Matt Briggs | 44:ece6330e9b57 | 287 | val |= pEx0232En; |
Matt Briggs | 44:ece6330e9b57 | 288 | } |
Matt Briggs | 44:ece6330e9b57 | 289 | |
Matt Briggs | 53:a1563574a980 | 290 | if (mPortEx0->pioLogicReliableWrite(val | ~pEx0OutMask) != cmdSuccess) { |
Matt Briggs | 44:ece6330e9b57 | 291 | logError("Error enabling 232"); |
Matt Briggs | 44:ece6330e9b57 | 292 | return cmdError; |
Matt Briggs | 44:ece6330e9b57 | 293 | } |
Matt Briggs | 44:ece6330e9b57 | 294 | return cmdSuccess; |
Matt Briggs | 44:ece6330e9b57 | 295 | } |
Matt Briggs | 44:ece6330e9b57 | 296 | CmdResult BaseboardIO::serialTx(bool enable) |
Matt Briggs | 44:ece6330e9b57 | 297 | { |
Matt Briggs | 44:ece6330e9b57 | 298 | uint8_t val; |
Matt Briggs | 49:18f1354f9e51 | 299 | if (mPortEx0 == NULL) { |
Matt Briggs | 49:18f1354f9e51 | 300 | logError("Error enabling 232 TX. Port expanders not initialized."); |
Matt Briggs | 49:18f1354f9e51 | 301 | return cmdError; |
Matt Briggs | 49:18f1354f9e51 | 302 | } |
Matt Briggs | 53:a1563574a980 | 303 | mPortEx0->pioLogicReliableRead(val); |
Matt Briggs | 44:ece6330e9b57 | 304 | |
Matt Briggs | 44:ece6330e9b57 | 305 | // Active high tx disable therefore active low tx enable (note chip must also be enabled for TX) |
Matt Briggs | 44:ece6330e9b57 | 306 | if (enable) { |
Matt Briggs | 44:ece6330e9b57 | 307 | val &= ~pEx0232TxDis; |
Matt Briggs | 44:ece6330e9b57 | 308 | } |
Matt Briggs | 44:ece6330e9b57 | 309 | else { |
Matt Briggs | 44:ece6330e9b57 | 310 | val |= pEx0232TxDis; |
Matt Briggs | 44:ece6330e9b57 | 311 | } |
Matt Briggs | 44:ece6330e9b57 | 312 | |
Matt Briggs | 53:a1563574a980 | 313 | if (mPortEx0->pioLogicReliableWrite(val | ~pEx0OutMask) != cmdSuccess) { |
Matt Briggs | 44:ece6330e9b57 | 314 | logError("Error enabling 232 TX"); |
Matt Briggs | 44:ece6330e9b57 | 315 | return cmdError; |
Matt Briggs | 44:ece6330e9b57 | 316 | } |
Matt Briggs | 44:ece6330e9b57 | 317 | return cmdSuccess; |
Matt Briggs | 44:ece6330e9b57 | 318 | } |
Matt Briggs | 44:ece6330e9b57 | 319 | |
Matt Briggs | 44:ece6330e9b57 | 320 | // private |
Matt Briggs | 44:ece6330e9b57 | 321 | CmdResult BaseboardIO::readInfoFromNVM() |
Matt Briggs | 44:ece6330e9b57 | 322 | { |
Matt Briggs | 55:79ab0bbc5008 | 323 | bool nvmReadResult; |
Matt Briggs | 55:79ab0bbc5008 | 324 | uint8_t *data = new uint8_t [BASEBOARDIO_NVM_SIZE]; |
Matt Briggs | 55:79ab0bbc5008 | 325 | |
Matt Briggs | 55:79ab0bbc5008 | 326 | nvmReadResult = dot->nvmRead(BASEBOARDIO_NVM_START_ADDR, data, BASEBOARDIO_NVM_SIZE); |
Matt Briggs | 55:79ab0bbc5008 | 327 | if (!nvmReadResult) { |
Matt Briggs | 55:79ab0bbc5008 | 328 | delete [] data; |
Matt Briggs | 55:79ab0bbc5008 | 329 | return cmdError; |
Matt Briggs | 55:79ab0bbc5008 | 330 | } |
Matt Briggs | 55:79ab0bbc5008 | 331 | mNvmObj.fromBytes(data, BASEBOARDIO_NVM_SIZE); |
Matt Briggs | 55:79ab0bbc5008 | 332 | delete [] data; |
Matt Briggs | 55:79ab0bbc5008 | 333 | if (!mNvmObj.validBaseboardIOFlag()) { |
Matt Briggs | 55:79ab0bbc5008 | 334 | logWarning("Invalid BaseboardIO Flag. Using default values."); |
Matt Briggs | 55:79ab0bbc5008 | 335 | return cmdError; |
Matt Briggs | 55:79ab0bbc5008 | 336 | } |
Matt Briggs | 55:79ab0bbc5008 | 337 | else if (!mNvmObj.validBaseboardIORev()) { |
Matt Briggs | 55:79ab0bbc5008 | 338 | logWarning("Invalid BaseboardIO Rev. Using default values."); |
Matt Briggs | 55:79ab0bbc5008 | 339 | return cmdError; |
Matt Briggs | 55:79ab0bbc5008 | 340 | } |
Matt Briggs | 55:79ab0bbc5008 | 341 | else { |
Matt Briggs | 55:79ab0bbc5008 | 342 | return cmdSuccess; |
Matt Briggs | 55:79ab0bbc5008 | 343 | } |
Matt Briggs | 40:2ec4be320961 | 344 | } |
Matt Briggs | 44:ece6330e9b57 | 345 | CmdResult BaseboardIO::writeInfoToNVM() |
Matt Briggs | 40:2ec4be320961 | 346 | { |
Matt Briggs | 55:79ab0bbc5008 | 347 | uint8_t *data = new uint8_t [BASEBOARDIO_NVM_SIZE]; |
Matt Briggs | 55:79ab0bbc5008 | 348 | uint8_t size = BASEBOARDIO_NVM_SIZE; |
Matt Briggs | 55:79ab0bbc5008 | 349 | mNvmObj.toBytes(data, size); |
Matt Briggs | 55:79ab0bbc5008 | 350 | dot->nvmWrite(BASEBOARDIO_NVM_START_ADDR, data, BASEBOARDIO_NVM_SIZE); |
Matt Briggs | 55:79ab0bbc5008 | 351 | |
Matt Briggs | 55:79ab0bbc5008 | 352 | delete [] data; |
Matt Briggs | 55:79ab0bbc5008 | 353 | return cmdSuccess; |
Matt Briggs | 40:2ec4be320961 | 354 | } |
Matt Briggs | 44:ece6330e9b57 | 355 | CmdResult BaseboardIO::identifyPortExpanders() |
Matt Briggs | 44:ece6330e9b57 | 356 | { |
Matt Briggs | 44:ece6330e9b57 | 357 | uint8_t addr[8]; |
Matt Briggs | 44:ece6330e9b57 | 358 | uint8_t result; |
Matt Briggs | 49:18f1354f9e51 | 359 | int i; |
Matt Briggs | 40:2ec4be320961 | 360 | |
Matt Briggs | 44:ece6330e9b57 | 361 | // Search Bus |
Matt Briggs | 44:ece6330e9b57 | 362 | logInfo("Starting OneWire Search"); |
Matt Briggs | 49:18f1354f9e51 | 363 | enableSwitchedIO(); |
Matt Briggs | 49:18f1354f9e51 | 364 | for (int j=0;j<10;j++) { // Try 5 times |
Matt Briggs | 49:18f1354f9e51 | 365 | i=0; |
Matt Briggs | 49:18f1354f9e51 | 366 | mOWMaster.reset(); |
Matt Briggs | 49:18f1354f9e51 | 367 | mOWMaster.reset_search(); |
Matt Briggs | 49:18f1354f9e51 | 368 | wait(1.0); |
Matt Briggs | 49:18f1354f9e51 | 369 | while (true) { |
Matt Briggs | 49:18f1354f9e51 | 370 | // TODO maybe change to family based search |
Matt Briggs | 49:18f1354f9e51 | 371 | result = mOWMaster.search(addr); |
Matt Briggs | 49:18f1354f9e51 | 372 | if (result != 1) { |
Matt Briggs | 49:18f1354f9e51 | 373 | break; |
Matt Briggs | 49:18f1354f9e51 | 374 | } |
Matt Briggs | 49:18f1354f9e51 | 375 | logInfo("ROM Addr: %02x:%02x:%02x:%02x:%02x:%02x:%02x%02x found.", |
Matt Briggs | 49:18f1354f9e51 | 376 | addr[7],addr[6],addr[5],addr[4],addr[3],addr[2],addr[1],addr[0]); |
Matt Briggs | 49:18f1354f9e51 | 377 | if (i == 0) { |
Matt Briggs | 55:79ab0bbc5008 | 378 | std::memcpy(mNvmObj.mPortExpanderROM0, addr, sizeof(mNvmObj.mPortExpanderROM0)); |
Matt Briggs | 49:18f1354f9e51 | 379 | } |
Matt Briggs | 49:18f1354f9e51 | 380 | else if (i == 1) { |
Matt Briggs | 55:79ab0bbc5008 | 381 | std::memcpy(mNvmObj.mPortExpanderROM1, addr, sizeof(mNvmObj.mPortExpanderROM1)); |
Matt Briggs | 49:18f1354f9e51 | 382 | } |
Matt Briggs | 49:18f1354f9e51 | 383 | i++; |
Matt Briggs | 49:18f1354f9e51 | 384 | } |
Matt Briggs | 49:18f1354f9e51 | 385 | // TODO maybe only allow a reasonable number of Port Expanders |
Matt Briggs | 49:18f1354f9e51 | 386 | if (i >=2) { |
Matt Briggs | 44:ece6330e9b57 | 387 | break; |
Matt Briggs | 44:ece6330e9b57 | 388 | } |
Matt Briggs | 44:ece6330e9b57 | 389 | } |
Matt Briggs | 44:ece6330e9b57 | 390 | |
Matt Briggs | 44:ece6330e9b57 | 391 | logInfo("Finished OneWire Search"); |
Matt Briggs | 44:ece6330e9b57 | 392 | if (i != 2) { |
Matt Briggs | 48:bab9f747d9ed | 393 | logError("Incorrect Number of OneWire devices (Got %d. Expected 2) OneWire port expanders found.", i); |
Matt Briggs | 44:ece6330e9b57 | 394 | return cmdError; |
Matt Briggs | 44:ece6330e9b57 | 395 | } |
Matt Briggs | 44:ece6330e9b57 | 396 | |
Matt Briggs | 49:18f1354f9e51 | 397 | // All rotary switches should be at 0. DIPS should be asserted. |
Matt Briggs | 44:ece6330e9b57 | 398 | // If switches are set in factory default mode then port expander 1 should read 0xFF and |
Matt Briggs | 44:ece6330e9b57 | 399 | // port expander 2 should read 0xF0. |
Matt Briggs | 40:2ec4be320961 | 400 | |
Matt Briggs | 55:79ab0bbc5008 | 401 | mPortEx0 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM0); |
Matt Briggs | 55:79ab0bbc5008 | 402 | mPortEx1 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM1); |
Matt Briggs | 44:ece6330e9b57 | 403 | |
Matt Briggs | 49:18f1354f9e51 | 404 | |
Matt Briggs | 49:18f1354f9e51 | 405 | enableSwitchedIO(); |
Matt Briggs | 53:a1563574a980 | 406 | if (mPortEx0->pioLogicReliableRead(mPortExpanderVal0) != cmdSuccess) { |
Matt Briggs | 44:ece6330e9b57 | 407 | logError("Error during port expander ID. Read failed."); |
Matt Briggs | 49:18f1354f9e51 | 408 | disableSwitchedIO(); |
Matt Briggs | 44:ece6330e9b57 | 409 | delete mPortEx0; |
Matt Briggs | 44:ece6330e9b57 | 410 | delete mPortEx1; |
Matt Briggs | 44:ece6330e9b57 | 411 | return cmdError; |
Matt Briggs | 44:ece6330e9b57 | 412 | } |
Matt Briggs | 53:a1563574a980 | 413 | if (mPortEx1->pioLogicReliableRead(mPortExpanderVal1) != cmdSuccess) { |
Matt Briggs | 44:ece6330e9b57 | 414 | logError("Error during port expander ID. Read failed."); |
Matt Briggs | 49:18f1354f9e51 | 415 | disableSwitchedIO(); |
Matt Briggs | 44:ece6330e9b57 | 416 | delete mPortEx0; |
Matt Briggs | 44:ece6330e9b57 | 417 | delete mPortEx1; |
Matt Briggs | 44:ece6330e9b57 | 418 | return cmdError; |
Matt Briggs | 44:ece6330e9b57 | 419 | } |
Matt Briggs | 44:ece6330e9b57 | 420 | |
Matt Briggs | 49:18f1354f9e51 | 421 | disableSwitchedIO(); |
Matt Briggs | 44:ece6330e9b57 | 422 | if ((mPortExpanderVal0 == 0xFF) and (mPortExpanderVal1 == 0xF0)) { // Luckily got it right |
Matt Briggs | 44:ece6330e9b57 | 423 | logInfo("ROMS Swap Not Needed."); |
Matt Briggs | 44:ece6330e9b57 | 424 | } |
Matt Briggs | 44:ece6330e9b57 | 425 | else if ((mPortExpanderVal0 == 0xF0) and (mPortExpanderVal1 == 0xFF)) { // Just need to swap |
Matt Briggs | 55:79ab0bbc5008 | 426 | std::memcpy(addr, mNvmObj.mPortExpanderROM0, sizeof(addr)); // Store Orig ROM0 -> addr |
Matt Briggs | 55:79ab0bbc5008 | 427 | std::memcpy(mNvmObj.mPortExpanderROM0, mNvmObj.mPortExpanderROM1, sizeof(mNvmObj.mPortExpanderROM0)); // Store Orig ROM1 -> ROM0 |
Matt Briggs | 55:79ab0bbc5008 | 428 | std::memcpy(mNvmObj.mPortExpanderROM1, addr, sizeof(mNvmObj.mPortExpanderROM1)); // Store Orig ROM0 (addr) -> ROM1 |
Matt Briggs | 44:ece6330e9b57 | 429 | logInfo("Swapped ROMS."); |
Matt Briggs | 44:ece6330e9b57 | 430 | } |
Matt Briggs | 44:ece6330e9b57 | 431 | else { |
Matt Briggs | 49:18f1354f9e51 | 432 | logError("Error during port expander ID. Port expanders not in " |
Matt Briggs | 55:79ab0bbc5008 | 433 | "expected states (0xFF and 0xF0). Check user switches. Got %02X and %02X", |
Matt Briggs | 49:18f1354f9e51 | 434 | mPortExpanderVal0, mPortExpanderVal1); |
Matt Briggs | 44:ece6330e9b57 | 435 | delete mPortEx0; |
Matt Briggs | 44:ece6330e9b57 | 436 | delete mPortEx1; |
Matt Briggs | 44:ece6330e9b57 | 437 | return cmdError; |
Matt Briggs | 44:ece6330e9b57 | 438 | } |
Matt Briggs | 44:ece6330e9b57 | 439 | |
Matt Briggs | 44:ece6330e9b57 | 440 | // Cleanup |
Matt Briggs | 44:ece6330e9b57 | 441 | delete mPortEx0; |
Matt Briggs | 44:ece6330e9b57 | 442 | delete mPortEx1; |
Matt Briggs | 44:ece6330e9b57 | 443 | |
Matt Briggs | 44:ece6330e9b57 | 444 | return cmdSuccess; |
Matt Briggs | 40:2ec4be320961 | 445 | } |
Matt Briggs | 49:18f1354f9e51 | 446 | CmdResult BaseboardIO::openRelay() { |
Matt Briggs | 44:ece6330e9b57 | 447 | uint8_t val; |
Matt Briggs | 53:a1563574a980 | 448 | mPortEx1->pioLogicReliableRead(val); |
Matt Briggs | 44:ece6330e9b57 | 449 | |
Matt Briggs | 49:18f1354f9e51 | 450 | val |= pEx1RlyA; // Make sure Relay A is off |
Matt Briggs | 49:18f1354f9e51 | 451 | val &= ~pEx1RlyB; // Turn on Relay B |
Matt Briggs | 44:ece6330e9b57 | 452 | |
Matt Briggs | 53:a1563574a980 | 453 | if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) { |
Matt Briggs | 49:18f1354f9e51 | 454 | val |= pEx1RlyA; // Turn Relay A off |
Matt Briggs | 49:18f1354f9e51 | 455 | val |= pEx1RlyB; // Turn Relay B off |
Matt Briggs | 53:a1563574a980 | 456 | mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask); // Write a non assert value just to try to overcome an error |
Matt Briggs | 44:ece6330e9b57 | 457 | logError ("Error turning on coil. Turning both coils off."); |
Matt Briggs | 44:ece6330e9b57 | 458 | return cmdError; |
Matt Briggs | 44:ece6330e9b57 | 459 | } |
Matt Briggs | 44:ece6330e9b57 | 460 | |
Matt Briggs | 47:a68747642a7a | 461 | wait(COIL_ON_TIME); |
Matt Briggs | 44:ece6330e9b57 | 462 | |
Matt Briggs | 49:18f1354f9e51 | 463 | val |= pEx1RlyA; // Turn Relay A off |
Matt Briggs | 49:18f1354f9e51 | 464 | val |= pEx1RlyB; // Turn Relay B off |
Matt Briggs | 44:ece6330e9b57 | 465 | |
Matt Briggs | 53:a1563574a980 | 466 | if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) { |
Matt Briggs | 53:a1563574a980 | 467 | mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask); |
Matt Briggs | 44:ece6330e9b57 | 468 | logError ("Error turning off coils. Trying again."); |
Matt Briggs | 44:ece6330e9b57 | 469 | return cmdError; |
Matt Briggs | 44:ece6330e9b57 | 470 | } |
Matt Briggs | 44:ece6330e9b57 | 471 | |
Matt Briggs | 44:ece6330e9b57 | 472 | return cmdSuccess; |
Matt Briggs | 40:2ec4be320961 | 473 | } |
Matt Briggs | 49:18f1354f9e51 | 474 | CmdResult BaseboardIO::closeRelay() { |
Matt Briggs | 44:ece6330e9b57 | 475 | uint8_t val; |
Matt Briggs | 53:a1563574a980 | 476 | mPortEx1->pioLogicReliableRead(val); |
Matt Briggs | 44:ece6330e9b57 | 477 | |
Matt Briggs | 49:18f1354f9e51 | 478 | val &= ~pEx1RlyA; // Turn on Relay A |
Matt Briggs | 49:18f1354f9e51 | 479 | val |= pEx1RlyB; // Make sure Relay B is off |
Matt Briggs | 44:ece6330e9b57 | 480 | |
Matt Briggs | 53:a1563574a980 | 481 | if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) { |
Matt Briggs | 49:18f1354f9e51 | 482 | val |= pEx1RlyA; // Turn Relay A off |
Matt Briggs | 49:18f1354f9e51 | 483 | val |= pEx1RlyB; // Turn Relay B off |
Matt Briggs | 53:a1563574a980 | 484 | mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask); // Write a non assert value just to try to overcome an error |
Matt Briggs | 44:ece6330e9b57 | 485 | logError ("Error turning on coil. Turning both coils off."); |
Matt Briggs | 44:ece6330e9b57 | 486 | return cmdError; |
Matt Briggs | 44:ece6330e9b57 | 487 | } |
Matt Briggs | 44:ece6330e9b57 | 488 | |
Matt Briggs | 47:a68747642a7a | 489 | wait(COIL_ON_TIME); |
Matt Briggs | 44:ece6330e9b57 | 490 | |
Matt Briggs | 49:18f1354f9e51 | 491 | val |= pEx1RlyA; // Turn Relay A off |
Matt Briggs | 49:18f1354f9e51 | 492 | val |= pEx1RlyB; // Turn Relay B off |
Matt Briggs | 44:ece6330e9b57 | 493 | |
Matt Briggs | 53:a1563574a980 | 494 | if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) { |
Matt Briggs | 53:a1563574a980 | 495 | mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask); |
Matt Briggs | 44:ece6330e9b57 | 496 | logError ("Error turning off coils. Trying again."); |
Matt Briggs | 44:ece6330e9b57 | 497 | return cmdError; |
Matt Briggs | 44:ece6330e9b57 | 498 | } |
Matt Briggs | 44:ece6330e9b57 | 499 | |
Matt Briggs | 44:ece6330e9b57 | 500 | return cmdSuccess; |
Matt Briggs | 40:2ec4be320961 | 501 | } |
Matt Briggs | 55:79ab0bbc5008 | 502 | |
Matt Briggs | 55:79ab0bbc5008 | 503 | // NvmBBIOObj |
Matt Briggs | 55:79ab0bbc5008 | 504 | NvmBBIOObj::NvmBBIOObj() |
Matt Briggs | 55:79ab0bbc5008 | 505 | { |
Matt Briggs | 55:79ab0bbc5008 | 506 | setDefaults(); |
Matt Briggs | 55:79ab0bbc5008 | 507 | } |
Matt Briggs | 55:79ab0bbc5008 | 508 | void NvmBBIOObj::setDefaults() |
Matt Briggs | 55:79ab0bbc5008 | 509 | { |
Matt Briggs | 55:79ab0bbc5008 | 510 | mBaseboardIOFlag = BASEBOARDIO_FLAG; |
Matt Briggs | 55:79ab0bbc5008 | 511 | mBaseboardIORev = BASEBOARDIO_REV; |
Matt Briggs | 55:79ab0bbc5008 | 512 | mSerialNum = 0x0000; |
Matt Briggs | 55:79ab0bbc5008 | 513 | mBaseboardIOConfig = 0x0000; |
Matt Briggs | 55:79ab0bbc5008 | 514 | std::memset(mPortExpanderROM0, 0x00, 8); |
Matt Briggs | 55:79ab0bbc5008 | 515 | std::memset(mPortExpanderROM1, 0x00, 8); |
Matt Briggs | 55:79ab0bbc5008 | 516 | } |
Matt Briggs | 55:79ab0bbc5008 | 517 | CmdResult NvmBBIOObj::fromBytes(uint8_t *data, uint8_t size) |
Matt Briggs | 55:79ab0bbc5008 | 518 | { |
Matt Briggs | 55:79ab0bbc5008 | 519 | if (size != BASEBOARDIO_NVM_SIZE) { |
Matt Briggs | 55:79ab0bbc5008 | 520 | return cmdError; |
Matt Briggs | 55:79ab0bbc5008 | 521 | } |
Matt Briggs | 55:79ab0bbc5008 | 522 | |
Matt Briggs | 55:79ab0bbc5008 | 523 | mBaseboardIOFlag = *((uint16_t *) (data)); |
Matt Briggs | 55:79ab0bbc5008 | 524 | mBaseboardIORev = *((uint16_t *) (data+2)); |
Matt Briggs | 55:79ab0bbc5008 | 525 | mSerialNum = *((uint32_t *) (data+4)); |
Matt Briggs | 55:79ab0bbc5008 | 526 | mBaseboardIOConfig = *((uint32_t *) (data+6)); |
Matt Briggs | 55:79ab0bbc5008 | 527 | |
Matt Briggs | 55:79ab0bbc5008 | 528 | std::memcpy(&mPortExpanderROM0, data+0x10, 8); |
Matt Briggs | 55:79ab0bbc5008 | 529 | std::memcpy(&mPortExpanderROM1, data+0x18, 8); |
Matt Briggs | 55:79ab0bbc5008 | 530 | |
Matt Briggs | 55:79ab0bbc5008 | 531 | return cmdSuccess; |
Matt Briggs | 55:79ab0bbc5008 | 532 | } |
Matt Briggs | 55:79ab0bbc5008 | 533 | CmdResult NvmBBIOObj::toBytes(uint8_t *data, uint8_t &size) { |
Matt Briggs | 55:79ab0bbc5008 | 534 | // TODO check data size |
Matt Briggs | 55:79ab0bbc5008 | 535 | |
Matt Briggs | 55:79ab0bbc5008 | 536 | *((uint16_t *) (data)) = mBaseboardIOFlag; |
Matt Briggs | 55:79ab0bbc5008 | 537 | *((uint16_t *) (data+2)) = mBaseboardIORev; |
Matt Briggs | 55:79ab0bbc5008 | 538 | *((uint32_t *) (data+4)) = mSerialNum; |
Matt Briggs | 55:79ab0bbc5008 | 539 | *((uint32_t *) (data+6)) = mBaseboardIOConfig; |
Matt Briggs | 55:79ab0bbc5008 | 540 | |
Matt Briggs | 55:79ab0bbc5008 | 541 | std::memcpy(data+0x10, &mPortExpanderROM0, 8); |
Matt Briggs | 55:79ab0bbc5008 | 542 | std::memcpy(data+0x18, &mPortExpanderROM1, 8); |
Matt Briggs | 55:79ab0bbc5008 | 543 | |
Matt Briggs | 55:79ab0bbc5008 | 544 | size = BASEBOARDIO_NVM_SIZE; |
Matt Briggs | 55:79ab0bbc5008 | 545 | |
Matt Briggs | 55:79ab0bbc5008 | 546 | return cmdSuccess; |
Matt Briggs | 55:79ab0bbc5008 | 547 | } |
Matt Briggs | 55:79ab0bbc5008 | 548 | uint16_t NvmBBIOObj::getBaseboardIOFlag() |
Matt Briggs | 55:79ab0bbc5008 | 549 | { |
Matt Briggs | 55:79ab0bbc5008 | 550 | return mBaseboardIOFlag; |
Matt Briggs | 55:79ab0bbc5008 | 551 | } |
Matt Briggs | 55:79ab0bbc5008 | 552 | bool NvmBBIOObj::validBaseboardIOFlag() |
Matt Briggs | 55:79ab0bbc5008 | 553 | { |
Matt Briggs | 55:79ab0bbc5008 | 554 | return mBaseboardIOFlag == BASEBOARDIO_FLAG; |
Matt Briggs | 55:79ab0bbc5008 | 555 | } |
Matt Briggs | 55:79ab0bbc5008 | 556 | uint16_t NvmBBIOObj::getBaseboardIORev() |
Matt Briggs | 55:79ab0bbc5008 | 557 | { |
Matt Briggs | 55:79ab0bbc5008 | 558 | return mBaseboardIORev; |
Matt Briggs | 55:79ab0bbc5008 | 559 | } |
Matt Briggs | 55:79ab0bbc5008 | 560 | bool NvmBBIOObj::validBaseboardIORev() |
Matt Briggs | 55:79ab0bbc5008 | 561 | { |
Matt Briggs | 55:79ab0bbc5008 | 562 | return mBaseboardIORev == BASEBOARDIO_REV; |
Matt Briggs | 55:79ab0bbc5008 | 563 | } |
Matt Briggs | 55:79ab0bbc5008 | 564 | uint16_t NvmBBIOObj::getSerialNum() |
Matt Briggs | 55:79ab0bbc5008 | 565 | { |
Matt Briggs | 55:79ab0bbc5008 | 566 | return mSerialNum; |
Matt Briggs | 55:79ab0bbc5008 | 567 | } |
Matt Briggs | 55:79ab0bbc5008 | 568 | void NvmBBIOObj::setSerialNum(uint16_t in) |
Matt Briggs | 55:79ab0bbc5008 | 569 | { |
Matt Briggs | 55:79ab0bbc5008 | 570 | mSerialNum = in; |
Matt Briggs | 55:79ab0bbc5008 | 571 | } |
Matt Briggs | 55:79ab0bbc5008 | 572 | uint32_t NvmBBIOObj::getBaseboardIOConfig() |
Matt Briggs | 55:79ab0bbc5008 | 573 | { |
Matt Briggs | 55:79ab0bbc5008 | 574 | return mBaseboardIOConfig; |
Matt Briggs | 55:79ab0bbc5008 | 575 | } |
Matt Briggs | 55:79ab0bbc5008 | 576 | void NvmBBIOObj::setBaseboardIOConfig(uint32_t in) |
Matt Briggs | 55:79ab0bbc5008 | 577 | { |
Matt Briggs | 55:79ab0bbc5008 | 578 | mBaseboardIOConfig = in; |
Matt Briggs | 55:79ab0bbc5008 | 579 | } |
Matt Briggs | 55:79ab0bbc5008 | 580 | void NvmBBIOObj::getPortExpanderROM0(uint8_t *addr) |
Matt Briggs | 55:79ab0bbc5008 | 581 | { |
Matt Briggs | 55:79ab0bbc5008 | 582 | std::memcpy(addr, &mPortExpanderROM0, 8); |
Matt Briggs | 55:79ab0bbc5008 | 583 | } |
Matt Briggs | 55:79ab0bbc5008 | 584 | void NvmBBIOObj::setPortExpanderROM0(const uint8_t *addr) |
Matt Briggs | 55:79ab0bbc5008 | 585 | { |
Matt Briggs | 55:79ab0bbc5008 | 586 | std::memcpy(&mPortExpanderROM0, addr, 8); |
Matt Briggs | 55:79ab0bbc5008 | 587 | } |
Matt Briggs | 55:79ab0bbc5008 | 588 | void NvmBBIOObj::getPortExpanderROM1(uint8_t *addr) |
Matt Briggs | 55:79ab0bbc5008 | 589 | { |
Matt Briggs | 55:79ab0bbc5008 | 590 | std::memcpy(addr, &mPortExpanderROM1, 8); |
Matt Briggs | 55:79ab0bbc5008 | 591 | } |
Matt Briggs | 55:79ab0bbc5008 | 592 | void NvmBBIOObj::setPortExpanderROM1(const uint8_t *addr) |
Matt Briggs | 55:79ab0bbc5008 | 593 | { |
Matt Briggs | 55:79ab0bbc5008 | 594 | std::memcpy(&mPortExpanderROM1, addr, 8); |
Matt Briggs | 55:79ab0bbc5008 | 595 | } |