Matt Briggs / Mbed OS xDotBridge_update_dev_latest

Fork to see if I can get working

Dependencies:   BufferedSerial OneWire WinbondSPIFlash libxDot-dev-mbed5-deprecated

Fork of xDotBridge_update_test20180823 by Matt Briggs

xDotBridge/src/BaseboardIO.cpp@58:15aa7a785b9f, 2017-03-01 (annotated)

Committer:
Matt Briggs
Date:
Wed Mar 01 17:28:32 2017 -0700
Revision:
58:15aa7a785b9f
Parent:
57:bdac7dd17af2
Child:
59:485545afc4dc
Major updates to power down during sleep code.  Other minior updates.  Used for test on 2017/03/01.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Matt Briggs 40:2ec4be320961 1 /*
Matt Briggs 40:2ec4be320961 2 * baseboardIO.cpp
Matt Briggs 40:2ec4be320961 3 *
Matt Briggs 40:2ec4be320961 4 * Created on: Jan 25, 2017
Matt Briggs 40:2ec4be320961 5 * Author: mbriggs
Matt Briggs 40:2ec4be320961 6 */
Matt Briggs 40:2ec4be320961 7
Matt Briggs 40:2ec4be320961 8 #include "BaseboardIO.h"
Matt Briggs 41:9ef4c4d77711 9 #include "MTSLog.h"
Matt Briggs 55:79ab0bbc5008 10 #include "dot_util.h" // FIXME just need the reference to dot somehow
Matt Briggs 58:15aa7a785b9f 11 #include "xdot_low_power.h"
Matt Briggs 40:2ec4be320961 12
Matt Briggs 47:a68747642a7a 13 const float COIL_ON_TIME = 0.030; // 30 ms
Matt Briggs 44:ece6330e9b57 14
Matt Briggs 49:18f1354f9e51 15 // Port expander 0 (Currently U7)
Matt Briggs 44:ece6330e9b57 16 const uint8_t pEx0232En = 0x01;
Matt Briggs 44:ece6330e9b57 17 const uint8_t pEx0232TxDis = 0x02;
Matt Briggs 44:ece6330e9b57 18 const uint8_t pEx0Rot1B1 = 0x04;
Matt Briggs 44:ece6330e9b57 19 const uint8_t pEx0Rot1B2 = 0x08;
Matt Briggs 44:ece6330e9b57 20 const uint8_t pEx0Rot1B4 = 0x10;
Matt Briggs 44:ece6330e9b57 21 const uint8_t pEx0Rot1B8 = 0x20;
Matt Briggs 44:ece6330e9b57 22 const uint8_t pEx0Rot2B1 = 0x40;
Matt Briggs 44:ece6330e9b57 23 const uint8_t pEx0Rot2B2 = 0x80;
Matt Briggs 49:18f1354f9e51 24 const uint8_t pEx0OutMask = 0x03; // Only allow bits 0,1 to be changed
Matt Briggs 44:ece6330e9b57 25
Matt Briggs 49:18f1354f9e51 26 // Port expander 1 (Currently U8)
Matt Briggs 44:ece6330e9b57 27 const uint8_t pEx1NoNcSel = 0x01;
Matt Briggs 44:ece6330e9b57 28 const uint8_t pEx1RxTxSel = 0x02;
Matt Briggs 44:ece6330e9b57 29 const uint8_t pEx1WanSel = 0x04;
Matt Briggs 44:ece6330e9b57 30 const uint8_t pEx1SerialEn = 0x08; // Labeled as reserved
Matt Briggs 44:ece6330e9b57 31 const uint8_t pEx1Rot2B8 = 0x10;
Matt Briggs 44:ece6330e9b57 32 const uint8_t pEx1Rot2B4 = 0x20;
Matt Briggs 44:ece6330e9b57 33 const uint8_t pEx1RlyB = 0x40; // This is actually a coil
Matt Briggs 44:ece6330e9b57 34 const uint8_t pEx1RlyA = 0x80; // This is actually a coil
Matt Briggs 49:18f1354f9e51 35 const uint8_t pEx1OutMask = 0xC0; // Only allow bits 6,7 to be changed
Matt Briggs 44:ece6330e9b57 36
Matt Briggs 44:ece6330e9b57 37 /**
Matt Briggs 44:ece6330e9b57 38 * Note for interrupt within uC cannot use two pins with the same numeric suffix (e.g. cannot
Matt Briggs 44:ece6330e9b57 39 * use both PA_0 and PB_0). Note 1, 6, 7, 8, and 13 are used by LoRa radio.
Matt Briggs 44:ece6330e9b57 40 */
Matt Briggs 44:ece6330e9b57 41
Matt Briggs 40:2ec4be320961 42 BaseboardIO::BaseboardIO()
Matt Briggs 58:15aa7a785b9f 43 : mOWMaster(OneWireMasterPinName),
Matt Briggs 58:15aa7a785b9f 44 mCCIn(CCInPinName),
Matt Briggs 58:15aa7a785b9f 45 mTamper(TamperPinName),
Matt Briggs 58:15aa7a785b9f 46 mPairBtn(PairBtnPinName),
Matt Briggs 58:15aa7a785b9f 47 mLed(LedPinName),
Matt Briggs 58:15aa7a785b9f 48 mSwitchedIOCtrl(SwitchedIOCtrlPinName, 0)
Matt Briggs 40:2ec4be320961 49 {
Matt Briggs 44:ece6330e9b57 50 mPortExpanderVal0 = 0x00;
Matt Briggs 44:ece6330e9b57 51 mPortExpanderVal1 = 0x00;
Matt Briggs 44:ece6330e9b57 52
Matt Briggs 44:ece6330e9b57 53 mPortEx0 = NULL;
Matt Briggs 44:ece6330e9b57 54 mPortEx1 = NULL;
Matt Briggs 40:2ec4be320961 55 }
Matt Briggs 56:40b454c952cc 56 CmdResult BaseboardIO::init(bool overwriteNvm)
Matt Briggs 40:2ec4be320961 57 {
Matt Briggs 56:40b454c952cc 58 bool storedROMsGood = false;
Matt Briggs 56:40b454c952cc 59 uint8_t val;
Matt Briggs 44:ece6330e9b57 60 // Setup port expanders
Matt Briggs 56:40b454c952cc 61 if (readInfoFromNVM() == cmdSuccess && !overwriteNvm) {
Matt Briggs 55:79ab0bbc5008 62 logInfo("Stored ROM0 Addr: %02x:%02x:%02x:%02x:%02x:%02x:%02x%02x found.",
Matt Briggs 55:79ab0bbc5008 63 mNvmObj.mPortExpanderROM0[7],
Matt Briggs 55:79ab0bbc5008 64 mNvmObj.mPortExpanderROM0[6],
Matt Briggs 55:79ab0bbc5008 65 mNvmObj.mPortExpanderROM0[5],
Matt Briggs 55:79ab0bbc5008 66 mNvmObj.mPortExpanderROM0[4],
Matt Briggs 55:79ab0bbc5008 67 mNvmObj.mPortExpanderROM0[3],
Matt Briggs 55:79ab0bbc5008 68 mNvmObj.mPortExpanderROM0[2],
Matt Briggs 55:79ab0bbc5008 69 mNvmObj.mPortExpanderROM0[1],
Matt Briggs 55:79ab0bbc5008 70 mNvmObj.mPortExpanderROM0[0]);
Matt Briggs 55:79ab0bbc5008 71 logInfo("Stored ROM1 Addr: %02x:%02x:%02x:%02x:%02x:%02x:%02x%02x found.",
Matt Briggs 55:79ab0bbc5008 72 mNvmObj.mPortExpanderROM1[7],
Matt Briggs 55:79ab0bbc5008 73 mNvmObj.mPortExpanderROM1[6],
Matt Briggs 55:79ab0bbc5008 74 mNvmObj.mPortExpanderROM1[5],
Matt Briggs 55:79ab0bbc5008 75 mNvmObj.mPortExpanderROM1[4],
Matt Briggs 55:79ab0bbc5008 76 mNvmObj.mPortExpanderROM1[3],
Matt Briggs 55:79ab0bbc5008 77 mNvmObj.mPortExpanderROM1[2],
Matt Briggs 55:79ab0bbc5008 78 mNvmObj.mPortExpanderROM1[1],
Matt Briggs 55:79ab0bbc5008 79 mNvmObj.mPortExpanderROM1[0]);
Matt Briggs 55:79ab0bbc5008 80 logInfo("BaseboardIO parameters successfully loaded from NVM");
Matt Briggs 56:40b454c952cc 81 // Check that the ROM Addresses are correct and valid
Matt Briggs 56:40b454c952cc 82 uint8_t portEx0Ctrl, portEx1Ctrl;
Matt Briggs 56:40b454c952cc 83 mPortEx0 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM0);
Matt Briggs 56:40b454c952cc 84 mPortEx0->registerReadReliable(0x8D, portEx0Ctrl);
Matt Briggs 56:40b454c952cc 85 // Gets 0xFF if it is not the correct address
Matt Briggs 56:40b454c952cc 86 logInfo("PortEx0 Control register reads %02X", portEx0Ctrl);
Matt Briggs 56:40b454c952cc 87
Matt Briggs 56:40b454c952cc 88 mPortEx1 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM1);
Matt Briggs 56:40b454c952cc 89 mPortEx1->registerReadReliable(0x8D, portEx1Ctrl);
Matt Briggs 56:40b454c952cc 90 logInfo("PortEx1 Control register reads %02X", portEx1Ctrl);
Matt Briggs 56:40b454c952cc 91 if ((portEx0Ctrl == 0xFF) || (portEx1Ctrl == 0xFF)) {
Matt Briggs 56:40b454c952cc 92 logError("Stored port expander ROM check failed. Set EEPROM to defaults.");
Matt Briggs 56:40b454c952cc 93 }
Matt Briggs 56:40b454c952cc 94 else {
Matt Briggs 56:40b454c952cc 95 storedROMsGood = true;
Matt Briggs 56:40b454c952cc 96 }
Matt Briggs 44:ece6330e9b57 97 }
Matt Briggs 56:40b454c952cc 98 if (!storedROMsGood)
Matt Briggs 56:40b454c952cc 99 { // EEPROM values not there or corrupt. Should only happen in factory.
Matt Briggs 55:79ab0bbc5008 100 mNvmObj.setDefaults();
Matt Briggs 47:a68747642a7a 101 // Find ROM address and test which one is which. Requires user
Matt Briggs 47:a68747642a7a 102 // switches to be in known state.
Matt Briggs 47:a68747642a7a 103 if (identifyPortExpanders() != cmdSuccess) {
Matt Briggs 44:ece6330e9b57 104 logError("Error identifying port expanders");
Matt Briggs 44:ece6330e9b57 105 return cmdError;
Matt Briggs 44:ece6330e9b57 106 }
Matt Briggs 55:79ab0bbc5008 107 if (writeInfoToNVM() == cmdSuccess) {
Matt Briggs 55:79ab0bbc5008 108 logInfo("Baseboard config saved to NVM");
Matt Briggs 55:79ab0bbc5008 109 }
Matt Briggs 55:79ab0bbc5008 110 else {
Matt Briggs 55:79ab0bbc5008 111 logError("Baseboard config failed to save to NVM");
Matt Briggs 55:79ab0bbc5008 112 }
Matt Briggs 56:40b454c952cc 113 mPortEx0 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM0);
Matt Briggs 56:40b454c952cc 114 mPortEx0->registerReadReliable(0x8D, val);
Matt Briggs 56:40b454c952cc 115 // Gets 0xFF if it is not the correct address
Matt Briggs 56:40b454c952cc 116 logInfo("PortEx0 Control register reads %02X", val);
Matt Briggs 56:40b454c952cc 117 mPortEx1 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM1);
Matt Briggs 56:40b454c952cc 118 mPortEx1->registerReadReliable(0x8D, val);
Matt Briggs 56:40b454c952cc 119 logInfo("PortEx1 Control register reads %02X", val);
Matt Briggs 44:ece6330e9b57 120 }
Matt Briggs 44:ece6330e9b57 121
Matt Briggs 57:bdac7dd17af2 122 if (sampleUserSwitches() != cmdSuccess) {
Matt Briggs 57:bdac7dd17af2 123 logError("Error sampling user switches");
Matt Briggs 57:bdac7dd17af2 124 return cmdError;
Matt Briggs 57:bdac7dd17af2 125 }
Matt Briggs 57:bdac7dd17af2 126
Matt Briggs 44:ece6330e9b57 127 // Put relay in known state
Matt Briggs 47:a68747642a7a 128 if (relayNormal() != cmdSuccess) {
Matt Briggs 47:a68747642a7a 129 logError("Error setting relay during init");
Matt Briggs 47:a68747642a7a 130 return cmdError;
Matt Briggs 47:a68747642a7a 131 }
Matt Briggs 47:a68747642a7a 132
Matt Briggs 44:ece6330e9b57 133 logInfo("Baseboard IO initialization successful");
Matt Briggs 44:ece6330e9b57 134 return cmdSuccess;
Matt Briggs 40:2ec4be320961 135 }
Matt Briggs 40:2ec4be320961 136
Matt Briggs 40:2ec4be320961 137 // Registering for interrupts
Matt Briggs 44:ece6330e9b57 138 void BaseboardIO::regCCInInt(Callback<void()> func)
Matt Briggs 40:2ec4be320961 139 {
Matt Briggs 48:bab9f747d9ed 140 sampleUserSwitches();
Matt Briggs 48:bab9f747d9ed 141 if (isCCNO()) {
Matt Briggs 48:bab9f747d9ed 142 // Pulled high, switched low
Matt Briggs 48:bab9f747d9ed 143 mCCIn.fall(func);
Matt Briggs 48:bab9f747d9ed 144 }
Matt Briggs 48:bab9f747d9ed 145 else {
Matt Briggs 48:bab9f747d9ed 146 mCCIn.rise(func);
Matt Briggs 48:bab9f747d9ed 147 }
Matt Briggs 53:a1563574a980 148 mCCIn.mode(PullNone);
Matt Briggs 49:18f1354f9e51 149 mCCIn.enable_irq();
Matt Briggs 40:2ec4be320961 150 }
Matt Briggs 44:ece6330e9b57 151 void BaseboardIO::regTamperInt(Callback<void()> func)
Matt Briggs 40:2ec4be320961 152 {
Matt Briggs 44:ece6330e9b57 153 // Pulled high, switched low
Matt Briggs 53:a1563574a980 154 mTamper.mode(PullNone);
Matt Briggs 49:18f1354f9e51 155 mTamper.rise(func);
Matt Briggs 44:ece6330e9b57 156 mTamper.fall(func);
Matt Briggs 49:18f1354f9e51 157 mTamper.enable_irq();
Matt Briggs 40:2ec4be320961 158 }
Matt Briggs 44:ece6330e9b57 159 void BaseboardIO::regPairBtnInt(Callback<void()> func)
Matt Briggs 40:2ec4be320961 160 {
Matt Briggs 44:ece6330e9b57 161 // Pulled low, switched high
Matt Briggs 58:15aa7a785b9f 162 mPairBtn.mode(PullNone);
Matt Briggs 44:ece6330e9b57 163 mPairBtn.rise(func);
Matt Briggs 49:18f1354f9e51 164 mPairBtn.enable_irq();
Matt Briggs 40:2ec4be320961 165 }
Matt Briggs 40:2ec4be320961 166
Matt Briggs 40:2ec4be320961 167 // Input
Matt Briggs 40:2ec4be320961 168 CmdResult BaseboardIO::sampleUserSwitches()
Matt Briggs 40:2ec4be320961 169 {
Matt Briggs 48:bab9f747d9ed 170 if ((mPortEx0 == NULL) || (mPortEx1 == NULL))
Matt Briggs 48:bab9f747d9ed 171 return cmdError;
Matt Briggs 44:ece6330e9b57 172 // Sample port expanders
Matt Briggs 49:18f1354f9e51 173 enableSwitchedIO();
Matt Briggs 49:18f1354f9e51 174 wait(0.001); // Wait 1 ms
Matt Briggs 53:a1563574a980 175 if (mPortEx0->pioLogicReliableRead(mPortExpanderVal0) != cmdSuccess) {
Matt Briggs 49:18f1354f9e51 176 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 177 logError("Error reading port expander 0.");
Matt Briggs 44:ece6330e9b57 178 return cmdError;
Matt Briggs 44:ece6330e9b57 179 }
Matt Briggs 53:a1563574a980 180 if (mPortEx1->pioLogicReliableRead(mPortExpanderVal1) != cmdSuccess) {
Matt Briggs 49:18f1354f9e51 181 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 182 logError("Error reading port expander 1.");
Matt Briggs 44:ece6330e9b57 183 return cmdError;
Matt Briggs 44:ece6330e9b57 184 }
Matt Briggs 49:18f1354f9e51 185 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 186 return cmdSuccess;
Matt Briggs 40:2ec4be320961 187 }
Matt Briggs 57:bdac7dd17af2 188 bool BaseboardIO::isCCInAlert()
Matt Briggs 57:bdac7dd17af2 189 {
Matt Briggs 57:bdac7dd17af2 190 if (isCCNO()) { // If NO then the CCIn should float high if not in alert state
Matt Briggs 57:bdac7dd17af2 191 return mCCIn == 0;
Matt Briggs 57:bdac7dd17af2 192 }
Matt Briggs 57:bdac7dd17af2 193 else { // If NC then the CCIN should be held low if not in alert state
Matt Briggs 57:bdac7dd17af2 194 return mCCIn == 1;
Matt Briggs 57:bdac7dd17af2 195 }
Matt Briggs 57:bdac7dd17af2 196 }
Matt Briggs 40:2ec4be320961 197 bool BaseboardIO::isPairBtn()
Matt Briggs 40:2ec4be320961 198 {
Matt Briggs 44:ece6330e9b57 199 // Depressed button is high
Matt Briggs 44:ece6330e9b57 200 return mPairBtn.read() == 1;
Matt Briggs 40:2ec4be320961 201 }
Matt Briggs 48:bab9f747d9ed 202 bool BaseboardIO::isCCNO()
Matt Briggs 40:2ec4be320961 203 {
Matt Briggs 44:ece6330e9b57 204 // When DIP switch is not closed (i.e. value reads high) assume NO
Matt Briggs 49:18f1354f9e51 205 return (mPortExpanderVal1 & pEx1NoNcSel) != 0; // Open NO, closed NC
Matt Briggs 40:2ec4be320961 206 }
Matt Briggs 40:2ec4be320961 207 bool BaseboardIO::isRx()
Matt Briggs 40:2ec4be320961 208 {
Matt Briggs 44:ece6330e9b57 209 // When DIP switch is not closed (i.e. value reads high) assume RX
Matt Briggs 44:ece6330e9b57 210 return (mPortExpanderVal1 & pEx1RxTxSel) != 0;
Matt Briggs 40:2ec4be320961 211 }
Matt Briggs 40:2ec4be320961 212 bool BaseboardIO::isLoRaWANMode()
Matt Briggs 40:2ec4be320961 213 {
Matt Briggs 44:ece6330e9b57 214 // When DIP switch is not closed (i.e. value reads high) assume P2P not WAN
Matt Briggs 44:ece6330e9b57 215 return (mPortExpanderVal1 & pEx1WanSel) == 0;
Matt Briggs 40:2ec4be320961 216 }
Matt Briggs 50:e89647e77fd5 217 bool BaseboardIO::isSerialEnabled()
Matt Briggs 50:e89647e77fd5 218 {
Matt Briggs 50:e89647e77fd5 219 // When DIP switch is not closed (i.e. value reads high) assume not in serial mode
Matt Briggs 50:e89647e77fd5 220 return (mPortExpanderVal1 & pEx1SerialEn) == 0;
Matt Briggs 50:e89647e77fd5 221 }
Matt Briggs 40:2ec4be320961 222 uint8_t BaseboardIO::rotarySwitch1()
Matt Briggs 40:2ec4be320961 223 {
Matt Briggs 44:ece6330e9b57 224 // If a bit of a nibble is asserted then the port expander line is switched low.
Matt Briggs 44:ece6330e9b57 225 uint8_t val = 0;
Matt Briggs 44:ece6330e9b57 226 if ((mPortExpanderVal0 & pEx0Rot1B8) == 0)
Matt Briggs 44:ece6330e9b57 227 val |= 0x08;
Matt Briggs 44:ece6330e9b57 228 if ((mPortExpanderVal0 & pEx0Rot1B4) == 0)
Matt Briggs 44:ece6330e9b57 229 val |= 0x04;
Matt Briggs 44:ece6330e9b57 230 if ((mPortExpanderVal0 & pEx0Rot1B2) == 0)
Matt Briggs 44:ece6330e9b57 231 val |= 0x02;
Matt Briggs 44:ece6330e9b57 232 if ((mPortExpanderVal0 & pEx0Rot1B1) == 0)
Matt Briggs 44:ece6330e9b57 233 val |= 0x01;
Matt Briggs 44:ece6330e9b57 234 return val;
Matt Briggs 40:2ec4be320961 235 }
Matt Briggs 40:2ec4be320961 236 uint8_t BaseboardIO::rotarySwitch2()
Matt Briggs 40:2ec4be320961 237 {
Matt Briggs 44:ece6330e9b57 238 // If a bit of a nibble is asserted then the port expander line is switched low.
Matt Briggs 44:ece6330e9b57 239 uint8_t val = 0;
Matt Briggs 44:ece6330e9b57 240 if ((mPortExpanderVal1 & pEx1Rot2B8) == 0)
Matt Briggs 44:ece6330e9b57 241 val |= 0x08;
Matt Briggs 44:ece6330e9b57 242 if ((mPortExpanderVal1 & pEx1Rot2B4) == 0)
Matt Briggs 44:ece6330e9b57 243 val |= 0x04;
Matt Briggs 44:ece6330e9b57 244 if ((mPortExpanderVal0 & pEx0Rot2B2) == 0)
Matt Briggs 44:ece6330e9b57 245 val |= 0x02;
Matt Briggs 44:ece6330e9b57 246 if ((mPortExpanderVal0 & pEx0Rot2B1) == 0)
Matt Briggs 44:ece6330e9b57 247 val |= 0x01;
Matt Briggs 44:ece6330e9b57 248 return val;
Matt Briggs 40:2ec4be320961 249 }
Matt Briggs 40:2ec4be320961 250
Matt Briggs 40:2ec4be320961 251 // Output
Matt Briggs 40:2ec4be320961 252 CmdResult BaseboardIO::ledOn()
Matt Briggs 40:2ec4be320961 253 {
Matt Briggs 44:ece6330e9b57 254 mLed = 1;
Matt Briggs 44:ece6330e9b57 255 return cmdSuccess;
Matt Briggs 40:2ec4be320961 256 }
Matt Briggs 40:2ec4be320961 257 CmdResult BaseboardIO::ledOff()
Matt Briggs 40:2ec4be320961 258 {
Matt Briggs 44:ece6330e9b57 259 mLed = 0;
Matt Briggs 44:ece6330e9b57 260 return cmdSuccess;
Matt Briggs 40:2ec4be320961 261 }
Matt Briggs 40:2ec4be320961 262 CmdResult BaseboardIO::relayAlert()
Matt Briggs 40:2ec4be320961 263 {
Matt Briggs 48:bab9f747d9ed 264 if (isCCNO()) { // Normally Open
Matt Briggs 44:ece6330e9b57 265 return closeRelay();
Matt Briggs 44:ece6330e9b57 266 }
Matt Briggs 44:ece6330e9b57 267 else { // Normally Close
Matt Briggs 44:ece6330e9b57 268 return openRelay();
Matt Briggs 44:ece6330e9b57 269 }
Matt Briggs 40:2ec4be320961 270 }
Matt Briggs 40:2ec4be320961 271 CmdResult BaseboardIO::relayNormal()
Matt Briggs 40:2ec4be320961 272 {
Matt Briggs 48:bab9f747d9ed 273 if (isCCNO()) { // Normally Open
Matt Briggs 44:ece6330e9b57 274 return openRelay();
Matt Briggs 44:ece6330e9b57 275 }
Matt Briggs 44:ece6330e9b57 276 else { // Normally Close
Matt Briggs 44:ece6330e9b57 277 return closeRelay();
Matt Briggs 44:ece6330e9b57 278 }
Matt Briggs 40:2ec4be320961 279 }
Matt Briggs 40:2ec4be320961 280
Matt Briggs 40:2ec4be320961 281 // Future
Matt Briggs 40:2ec4be320961 282 CmdResult BaseboardIO::serialRx(bool enable)
Matt Briggs 40:2ec4be320961 283 {
Matt Briggs 44:ece6330e9b57 284 uint8_t val;
Matt Briggs 49:18f1354f9e51 285 if (mPortEx0 == NULL) {
Matt Briggs 49:18f1354f9e51 286 logError("Error enabling 232. Port expanders not initialized.");
Matt Briggs 49:18f1354f9e51 287 return cmdError;
Matt Briggs 49:18f1354f9e51 288 }
Matt Briggs 53:a1563574a980 289 mPortEx0->pioLogicReliableRead(val);
Matt Briggs 44:ece6330e9b57 290
Matt Briggs 44:ece6330e9b57 291 // Active low from port expander -> pmos -> 232 (active chip EN)
Matt Briggs 44:ece6330e9b57 292 if (enable) {
Matt Briggs 44:ece6330e9b57 293 val &= ~pEx0232En;
Matt Briggs 44:ece6330e9b57 294 }
Matt Briggs 44:ece6330e9b57 295 else {
Matt Briggs 44:ece6330e9b57 296 val |= pEx0232En;
Matt Briggs 44:ece6330e9b57 297 }
Matt Briggs 44:ece6330e9b57 298
Matt Briggs 53:a1563574a980 299 if (mPortEx0->pioLogicReliableWrite(val | ~pEx0OutMask) != cmdSuccess) {
Matt Briggs 44:ece6330e9b57 300 logError("Error enabling 232");
Matt Briggs 44:ece6330e9b57 301 return cmdError;
Matt Briggs 44:ece6330e9b57 302 }
Matt Briggs 44:ece6330e9b57 303 return cmdSuccess;
Matt Briggs 44:ece6330e9b57 304 }
Matt Briggs 44:ece6330e9b57 305 CmdResult BaseboardIO::serialTx(bool enable)
Matt Briggs 44:ece6330e9b57 306 {
Matt Briggs 44:ece6330e9b57 307 uint8_t val;
Matt Briggs 49:18f1354f9e51 308 if (mPortEx0 == NULL) {
Matt Briggs 49:18f1354f9e51 309 logError("Error enabling 232 TX. Port expanders not initialized.");
Matt Briggs 49:18f1354f9e51 310 return cmdError;
Matt Briggs 49:18f1354f9e51 311 }
Matt Briggs 53:a1563574a980 312 mPortEx0->pioLogicReliableRead(val);
Matt Briggs 44:ece6330e9b57 313
Matt Briggs 44:ece6330e9b57 314 // Active high tx disable therefore active low tx enable (note chip must also be enabled for TX)
Matt Briggs 44:ece6330e9b57 315 if (enable) {
Matt Briggs 44:ece6330e9b57 316 val &= ~pEx0232TxDis;
Matt Briggs 44:ece6330e9b57 317 }
Matt Briggs 44:ece6330e9b57 318 else {
Matt Briggs 44:ece6330e9b57 319 val |= pEx0232TxDis;
Matt Briggs 44:ece6330e9b57 320 }
Matt Briggs 44:ece6330e9b57 321
Matt Briggs 53:a1563574a980 322 if (mPortEx0->pioLogicReliableWrite(val | ~pEx0OutMask) != cmdSuccess) {
Matt Briggs 44:ece6330e9b57 323 logError("Error enabling 232 TX");
Matt Briggs 44:ece6330e9b57 324 return cmdError;
Matt Briggs 44:ece6330e9b57 325 }
Matt Briggs 44:ece6330e9b57 326 return cmdSuccess;
Matt Briggs 44:ece6330e9b57 327 }
Matt Briggs 44:ece6330e9b57 328
Matt Briggs 44:ece6330e9b57 329 // private
Matt Briggs 44:ece6330e9b57 330 CmdResult BaseboardIO::readInfoFromNVM()
Matt Briggs 44:ece6330e9b57 331 {
Matt Briggs 55:79ab0bbc5008 332 bool nvmReadResult;
Matt Briggs 55:79ab0bbc5008 333 uint8_t *data = new uint8_t [BASEBOARDIO_NVM_SIZE];
Matt Briggs 55:79ab0bbc5008 334
Matt Briggs 55:79ab0bbc5008 335 nvmReadResult = dot->nvmRead(BASEBOARDIO_NVM_START_ADDR, data, BASEBOARDIO_NVM_SIZE);
Matt Briggs 55:79ab0bbc5008 336 if (!nvmReadResult) {
Matt Briggs 55:79ab0bbc5008 337 delete [] data;
Matt Briggs 55:79ab0bbc5008 338 return cmdError;
Matt Briggs 55:79ab0bbc5008 339 }
Matt Briggs 55:79ab0bbc5008 340 mNvmObj.fromBytes(data, BASEBOARDIO_NVM_SIZE);
Matt Briggs 55:79ab0bbc5008 341 delete [] data;
Matt Briggs 55:79ab0bbc5008 342 if (!mNvmObj.validBaseboardIOFlag()) {
Matt Briggs 55:79ab0bbc5008 343 logWarning("Invalid BaseboardIO Flag. Using default values.");
Matt Briggs 55:79ab0bbc5008 344 return cmdError;
Matt Briggs 55:79ab0bbc5008 345 }
Matt Briggs 55:79ab0bbc5008 346 else if (!mNvmObj.validBaseboardIORev()) {
Matt Briggs 55:79ab0bbc5008 347 logWarning("Invalid BaseboardIO Rev. Using default values.");
Matt Briggs 55:79ab0bbc5008 348 return cmdError;
Matt Briggs 55:79ab0bbc5008 349 }
Matt Briggs 55:79ab0bbc5008 350 else {
Matt Briggs 55:79ab0bbc5008 351 return cmdSuccess;
Matt Briggs 55:79ab0bbc5008 352 }
Matt Briggs 40:2ec4be320961 353 }
Matt Briggs 44:ece6330e9b57 354 CmdResult BaseboardIO::writeInfoToNVM()
Matt Briggs 40:2ec4be320961 355 {
Matt Briggs 55:79ab0bbc5008 356 uint8_t *data = new uint8_t [BASEBOARDIO_NVM_SIZE];
Matt Briggs 55:79ab0bbc5008 357 uint8_t size = BASEBOARDIO_NVM_SIZE;
Matt Briggs 55:79ab0bbc5008 358 mNvmObj.toBytes(data, size);
Matt Briggs 55:79ab0bbc5008 359 dot->nvmWrite(BASEBOARDIO_NVM_START_ADDR, data, BASEBOARDIO_NVM_SIZE);
Matt Briggs 55:79ab0bbc5008 360
Matt Briggs 55:79ab0bbc5008 361 delete [] data;
Matt Briggs 55:79ab0bbc5008 362 return cmdSuccess;
Matt Briggs 40:2ec4be320961 363 }
Matt Briggs 44:ece6330e9b57 364 CmdResult BaseboardIO::identifyPortExpanders()
Matt Briggs 44:ece6330e9b57 365 {
Matt Briggs 44:ece6330e9b57 366 uint8_t addr[8];
Matt Briggs 44:ece6330e9b57 367 uint8_t result;
Matt Briggs 49:18f1354f9e51 368 int i;
Matt Briggs 40:2ec4be320961 369
Matt Briggs 44:ece6330e9b57 370 // Search Bus
Matt Briggs 44:ece6330e9b57 371 logInfo("Starting OneWire Search");
Matt Briggs 49:18f1354f9e51 372 enableSwitchedIO();
Matt Briggs 49:18f1354f9e51 373 for (int j=0;j<10;j++) { // Try 5 times
Matt Briggs 49:18f1354f9e51 374 i=0;
Matt Briggs 49:18f1354f9e51 375 mOWMaster.reset();
Matt Briggs 49:18f1354f9e51 376 mOWMaster.reset_search();
Matt Briggs 49:18f1354f9e51 377 wait(1.0);
Matt Briggs 49:18f1354f9e51 378 while (true) {
Matt Briggs 49:18f1354f9e51 379 // TODO maybe change to family based search
Matt Briggs 49:18f1354f9e51 380 result = mOWMaster.search(addr);
Matt Briggs 49:18f1354f9e51 381 if (result != 1) {
Matt Briggs 49:18f1354f9e51 382 break;
Matt Briggs 49:18f1354f9e51 383 }
Matt Briggs 49:18f1354f9e51 384 logInfo("ROM Addr: %02x:%02x:%02x:%02x:%02x:%02x:%02x%02x found.",
Matt Briggs 49:18f1354f9e51 385 addr[7],addr[6],addr[5],addr[4],addr[3],addr[2],addr[1],addr[0]);
Matt Briggs 49:18f1354f9e51 386 if (i == 0) {
Matt Briggs 55:79ab0bbc5008 387 std::memcpy(mNvmObj.mPortExpanderROM0, addr, sizeof(mNvmObj.mPortExpanderROM0));
Matt Briggs 49:18f1354f9e51 388 }
Matt Briggs 49:18f1354f9e51 389 else if (i == 1) {
Matt Briggs 55:79ab0bbc5008 390 std::memcpy(mNvmObj.mPortExpanderROM1, addr, sizeof(mNvmObj.mPortExpanderROM1));
Matt Briggs 49:18f1354f9e51 391 }
Matt Briggs 49:18f1354f9e51 392 i++;
Matt Briggs 49:18f1354f9e51 393 }
Matt Briggs 49:18f1354f9e51 394 // TODO maybe only allow a reasonable number of Port Expanders
Matt Briggs 49:18f1354f9e51 395 if (i >=2) {
Matt Briggs 44:ece6330e9b57 396 break;
Matt Briggs 44:ece6330e9b57 397 }
Matt Briggs 44:ece6330e9b57 398 }
Matt Briggs 44:ece6330e9b57 399
Matt Briggs 44:ece6330e9b57 400 logInfo("Finished OneWire Search");
Matt Briggs 44:ece6330e9b57 401 if (i != 2) {
Matt Briggs 48:bab9f747d9ed 402 logError("Incorrect Number of OneWire devices (Got %d. Expected 2) OneWire port expanders found.", i);
Matt Briggs 44:ece6330e9b57 403 return cmdError;
Matt Briggs 44:ece6330e9b57 404 }
Matt Briggs 44:ece6330e9b57 405
Matt Briggs 49:18f1354f9e51 406 // All rotary switches should be at 0. DIPS should be asserted.
Matt Briggs 44:ece6330e9b57 407 // If switches are set in factory default mode then port expander 1 should read 0xFF and
Matt Briggs 44:ece6330e9b57 408 // port expander 2 should read 0xF0.
Matt Briggs 40:2ec4be320961 409
Matt Briggs 55:79ab0bbc5008 410 mPortEx0 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM0);
Matt Briggs 55:79ab0bbc5008 411 mPortEx1 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM1);
Matt Briggs 44:ece6330e9b57 412
Matt Briggs 49:18f1354f9e51 413
Matt Briggs 49:18f1354f9e51 414 enableSwitchedIO();
Matt Briggs 53:a1563574a980 415 if (mPortEx0->pioLogicReliableRead(mPortExpanderVal0) != cmdSuccess) {
Matt Briggs 44:ece6330e9b57 416 logError("Error during port expander ID. Read failed.");
Matt Briggs 49:18f1354f9e51 417 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 418 delete mPortEx0;
Matt Briggs 44:ece6330e9b57 419 delete mPortEx1;
Matt Briggs 44:ece6330e9b57 420 return cmdError;
Matt Briggs 44:ece6330e9b57 421 }
Matt Briggs 53:a1563574a980 422 if (mPortEx1->pioLogicReliableRead(mPortExpanderVal1) != cmdSuccess) {
Matt Briggs 44:ece6330e9b57 423 logError("Error during port expander ID. Read failed.");
Matt Briggs 49:18f1354f9e51 424 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 425 delete mPortEx0;
Matt Briggs 44:ece6330e9b57 426 delete mPortEx1;
Matt Briggs 44:ece6330e9b57 427 return cmdError;
Matt Briggs 44:ece6330e9b57 428 }
Matt Briggs 44:ece6330e9b57 429
Matt Briggs 49:18f1354f9e51 430 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 431 if ((mPortExpanderVal0 == 0xFF) and (mPortExpanderVal1 == 0xF0)) { // Luckily got it right
Matt Briggs 44:ece6330e9b57 432 logInfo("ROMS Swap Not Needed.");
Matt Briggs 44:ece6330e9b57 433 }
Matt Briggs 44:ece6330e9b57 434 else if ((mPortExpanderVal0 == 0xF0) and (mPortExpanderVal1 == 0xFF)) { // Just need to swap
Matt Briggs 55:79ab0bbc5008 435 std::memcpy(addr, mNvmObj.mPortExpanderROM0, sizeof(addr)); // Store Orig ROM0 -> addr
Matt Briggs 55:79ab0bbc5008 436 std::memcpy(mNvmObj.mPortExpanderROM0, mNvmObj.mPortExpanderROM1, sizeof(mNvmObj.mPortExpanderROM0)); // Store Orig ROM1 -> ROM0
Matt Briggs 55:79ab0bbc5008 437 std::memcpy(mNvmObj.mPortExpanderROM1, addr, sizeof(mNvmObj.mPortExpanderROM1)); // Store Orig ROM0 (addr) -> ROM1
Matt Briggs 44:ece6330e9b57 438 logInfo("Swapped ROMS.");
Matt Briggs 44:ece6330e9b57 439 }
Matt Briggs 44:ece6330e9b57 440 else {
Matt Briggs 49:18f1354f9e51 441 logError("Error during port expander ID. Port expanders not in "
Matt Briggs 55:79ab0bbc5008 442 "expected states (0xFF and 0xF0). Check user switches. Got %02X and %02X",
Matt Briggs 49:18f1354f9e51 443 mPortExpanderVal0, mPortExpanderVal1);
Matt Briggs 44:ece6330e9b57 444 delete mPortEx0;
Matt Briggs 44:ece6330e9b57 445 delete mPortEx1;
Matt Briggs 44:ece6330e9b57 446 return cmdError;
Matt Briggs 44:ece6330e9b57 447 }
Matt Briggs 44:ece6330e9b57 448
Matt Briggs 44:ece6330e9b57 449 // Cleanup
Matt Briggs 44:ece6330e9b57 450 delete mPortEx0;
Matt Briggs 44:ece6330e9b57 451 delete mPortEx1;
Matt Briggs 44:ece6330e9b57 452
Matt Briggs 44:ece6330e9b57 453 return cmdSuccess;
Matt Briggs 40:2ec4be320961 454 }
Matt Briggs 49:18f1354f9e51 455 CmdResult BaseboardIO::openRelay() {
Matt Briggs 44:ece6330e9b57 456 uint8_t val;
Matt Briggs 53:a1563574a980 457 mPortEx1->pioLogicReliableRead(val);
Matt Briggs 44:ece6330e9b57 458
Matt Briggs 49:18f1354f9e51 459 val |= pEx1RlyA; // Make sure Relay A is off
Matt Briggs 49:18f1354f9e51 460 val &= ~pEx1RlyB; // Turn on Relay B
Matt Briggs 44:ece6330e9b57 461
Matt Briggs 53:a1563574a980 462 if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) {
Matt Briggs 49:18f1354f9e51 463 val |= pEx1RlyA; // Turn Relay A off
Matt Briggs 49:18f1354f9e51 464 val |= pEx1RlyB; // Turn Relay B off
Matt Briggs 53:a1563574a980 465 mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask); // Write a non assert value just to try to overcome an error
Matt Briggs 44:ece6330e9b57 466 logError ("Error turning on coil. Turning both coils off.");
Matt Briggs 44:ece6330e9b57 467 return cmdError;
Matt Briggs 44:ece6330e9b57 468 }
Matt Briggs 44:ece6330e9b57 469
Matt Briggs 47:a68747642a7a 470 wait(COIL_ON_TIME);
Matt Briggs 44:ece6330e9b57 471
Matt Briggs 49:18f1354f9e51 472 val |= pEx1RlyA; // Turn Relay A off
Matt Briggs 49:18f1354f9e51 473 val |= pEx1RlyB; // Turn Relay B off
Matt Briggs 44:ece6330e9b57 474
Matt Briggs 53:a1563574a980 475 if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) {
Matt Briggs 53:a1563574a980 476 mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask);
Matt Briggs 44:ece6330e9b57 477 logError ("Error turning off coils. Trying again.");
Matt Briggs 44:ece6330e9b57 478 return cmdError;
Matt Briggs 44:ece6330e9b57 479 }
Matt Briggs 44:ece6330e9b57 480
Matt Briggs 44:ece6330e9b57 481 return cmdSuccess;
Matt Briggs 40:2ec4be320961 482 }
Matt Briggs 49:18f1354f9e51 483 CmdResult BaseboardIO::closeRelay() {
Matt Briggs 44:ece6330e9b57 484 uint8_t val;
Matt Briggs 53:a1563574a980 485 mPortEx1->pioLogicReliableRead(val);
Matt Briggs 44:ece6330e9b57 486
Matt Briggs 49:18f1354f9e51 487 val &= ~pEx1RlyA; // Turn on Relay A
Matt Briggs 49:18f1354f9e51 488 val |= pEx1RlyB; // Make sure Relay B is off
Matt Briggs 44:ece6330e9b57 489
Matt Briggs 53:a1563574a980 490 if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) {
Matt Briggs 49:18f1354f9e51 491 val |= pEx1RlyA; // Turn Relay A off
Matt Briggs 49:18f1354f9e51 492 val |= pEx1RlyB; // Turn Relay B off
Matt Briggs 53:a1563574a980 493 mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask); // Write a non assert value just to try to overcome an error
Matt Briggs 44:ece6330e9b57 494 logError ("Error turning on coil. Turning both coils off.");
Matt Briggs 44:ece6330e9b57 495 return cmdError;
Matt Briggs 44:ece6330e9b57 496 }
Matt Briggs 44:ece6330e9b57 497
Matt Briggs 47:a68747642a7a 498 wait(COIL_ON_TIME);
Matt Briggs 44:ece6330e9b57 499
Matt Briggs 49:18f1354f9e51 500 val |= pEx1RlyA; // Turn Relay A off
Matt Briggs 49:18f1354f9e51 501 val |= pEx1RlyB; // Turn Relay B off
Matt Briggs 44:ece6330e9b57 502
Matt Briggs 53:a1563574a980 503 if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) {
Matt Briggs 53:a1563574a980 504 mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask);
Matt Briggs 44:ece6330e9b57 505 logError ("Error turning off coils. Trying again.");
Matt Briggs 44:ece6330e9b57 506 return cmdError;
Matt Briggs 44:ece6330e9b57 507 }
Matt Briggs 44:ece6330e9b57 508
Matt Briggs 44:ece6330e9b57 509 return cmdSuccess;
Matt Briggs 40:2ec4be320961 510 }
Matt Briggs 55:79ab0bbc5008 511
Matt Briggs 58:15aa7a785b9f 512 CmdResult BaseboardIO::prepareSleep()
Matt Briggs 58:15aa7a785b9f 513 {
Matt Briggs 58:15aa7a785b9f 514 // Save current GPUIO state
Matt Briggs 58:15aa7a785b9f 515 xdot_save_gpio_state();
Matt Briggs 58:15aa7a785b9f 516
Matt Briggs 58:15aa7a785b9f 517 // Configure all IO expect for pins for interrupt in lowest mode possible
Matt Briggs 58:15aa7a785b9f 518 // GPIO Ports Clock Enable
Matt Briggs 58:15aa7a785b9f 519 __GPIOA_CLK_ENABLE();
Matt Briggs 58:15aa7a785b9f 520 __GPIOB_CLK_ENABLE();
Matt Briggs 58:15aa7a785b9f 521 __GPIOC_CLK_ENABLE();
Matt Briggs 58:15aa7a785b9f 522 __GPIOH_CLK_ENABLE();
Matt Briggs 58:15aa7a785b9f 523
Matt Briggs 58:15aa7a785b9f 524 GPIO_InitTypeDef GPIO_InitStruct;
Matt Briggs 58:15aa7a785b9f 525
Matt Briggs 58:15aa7a785b9f 526 // UART1_TX, UART1_RTS & UART1_CTS to analog nopull - RX could be a wakeup source
Matt Briggs 58:15aa7a785b9f 527 // UART1_TX, UART1_RTS & UART1_CTS to analog nopull - RX could be a wakeup source
Matt Briggs 58:15aa7a785b9f 528 // GPIO_InitStruct.Pin = GPIO_PIN_9 | GPIO_PIN_11 | GPIO_PIN_12;
Matt Briggs 58:15aa7a785b9f 529 GPIO_InitStruct.Pin = GPIO_PIN_9 | GPIO_PIN_12;
Matt Briggs 58:15aa7a785b9f 530 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 531 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 532 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 533
Matt Briggs 58:15aa7a785b9f 534 // I2C_SDA & I2C_SCL to analog nopull
Matt Briggs 58:15aa7a785b9f 535 GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9;
Matt Briggs 58:15aa7a785b9f 536 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 537 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 538 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 539
Matt Briggs 58:15aa7a785b9f 540 // SPI_MOSI, SPI_MISO, SPI_SCK, & SPI_NSS to analog nopull
Matt Briggs 58:15aa7a785b9f 541 GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
Matt Briggs 58:15aa7a785b9f 542 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 543 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 544 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 545
Matt Briggs 58:15aa7a785b9f 546 // iterate through potential wake pins - leave the configured wake pin alone if one is needed
Matt Briggs 58:15aa7a785b9f 547 if ((CCInPinName != WAKE && TamperPinName != WAKE && PairBtnPinName != WAKE)
Matt Briggs 58:15aa7a785b9f 548 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 549 GPIO_InitStruct.Pin = GPIO_PIN_0;
Matt Briggs 58:15aa7a785b9f 550 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 551 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 552 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 553 }
Matt Briggs 58:15aa7a785b9f 554 if ((CCInPinName != GPIO0 && TamperPinName != GPIO0 && PairBtnPinName != GPIO0)
Matt Briggs 58:15aa7a785b9f 555 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 556 GPIO_InitStruct.Pin = GPIO_PIN_4;
Matt Briggs 58:15aa7a785b9f 557 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 558 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 559 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 560 }
Matt Briggs 58:15aa7a785b9f 561 if ((CCInPinName != GPIO1 && TamperPinName != GPIO1 && PairBtnPinName != GPIO1)
Matt Briggs 58:15aa7a785b9f 562 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 563 GPIO_InitStruct.Pin = GPIO_PIN_5;
Matt Briggs 58:15aa7a785b9f 564 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 565 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 566 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 567 }
Matt Briggs 58:15aa7a785b9f 568 if ((CCInPinName != GPIO2 && TamperPinName != GPIO2 && PairBtnPinName != GPIO2)
Matt Briggs 58:15aa7a785b9f 569 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 570 GPIO_InitStruct.Pin = GPIO_PIN_0;
Matt Briggs 58:15aa7a785b9f 571 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 572 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 573 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 574 }
Matt Briggs 58:15aa7a785b9f 575 if ((CCInPinName != GPIO3 && TamperPinName != GPIO3 && PairBtnPinName != GPIO3)
Matt Briggs 58:15aa7a785b9f 576 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 577 GPIO_InitStruct.Pin = GPIO_PIN_2;
Matt Briggs 58:15aa7a785b9f 578 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 579 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 580 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 581 }
Matt Briggs 58:15aa7a785b9f 582 if ((CCInPinName != UART1_RX && TamperPinName != UART1_RX && PairBtnPinName != UART1_RX)
Matt Briggs 58:15aa7a785b9f 583 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 584 GPIO_InitStruct.Pin = GPIO_PIN_10;
Matt Briggs 58:15aa7a785b9f 585 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 586 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 587 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 588 }
Matt Briggs 58:15aa7a785b9f 589 if ((CCInPinName != UART_CTS && TamperPinName != UART_CTS && PairBtnPinName != UART_CTS)
Matt Briggs 58:15aa7a785b9f 590 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 591 GPIO_InitStruct.Pin = GPIO_PIN_11;
Matt Briggs 58:15aa7a785b9f 592 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 593 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 594 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 595 }
Matt Briggs 58:15aa7a785b9f 596
Matt Briggs 58:15aa7a785b9f 597 return cmdSuccess;
Matt Briggs 58:15aa7a785b9f 598 }
Matt Briggs 58:15aa7a785b9f 599
Matt Briggs 58:15aa7a785b9f 600 CmdResult BaseboardIO::exitSleep()
Matt Briggs 58:15aa7a785b9f 601 {
Matt Briggs 58:15aa7a785b9f 602 xdot_restore_gpio_state();
Matt Briggs 58:15aa7a785b9f 603 return cmdSuccess;
Matt Briggs 58:15aa7a785b9f 604 }
Matt Briggs 58:15aa7a785b9f 605
Matt Briggs 55:79ab0bbc5008 606 // NvmBBIOObj
Matt Briggs 55:79ab0bbc5008 607 NvmBBIOObj::NvmBBIOObj()
Matt Briggs 55:79ab0bbc5008 608 {
Matt Briggs 55:79ab0bbc5008 609 setDefaults();
Matt Briggs 55:79ab0bbc5008 610 }
Matt Briggs 55:79ab0bbc5008 611 void NvmBBIOObj::setDefaults()
Matt Briggs 55:79ab0bbc5008 612 {
Matt Briggs 55:79ab0bbc5008 613 mBaseboardIOFlag = BASEBOARDIO_FLAG;
Matt Briggs 55:79ab0bbc5008 614 mBaseboardIORev = BASEBOARDIO_REV;
Matt Briggs 55:79ab0bbc5008 615 mSerialNum = 0x0000;
Matt Briggs 55:79ab0bbc5008 616 mBaseboardIOConfig = 0x0000;
Matt Briggs 55:79ab0bbc5008 617 std::memset(mPortExpanderROM0, 0x00, 8);
Matt Briggs 55:79ab0bbc5008 618 std::memset(mPortExpanderROM1, 0x00, 8);
Matt Briggs 55:79ab0bbc5008 619 }
Matt Briggs 55:79ab0bbc5008 620 CmdResult NvmBBIOObj::fromBytes(uint8_t *data, uint8_t size)
Matt Briggs 55:79ab0bbc5008 621 {
Matt Briggs 55:79ab0bbc5008 622 if (size != BASEBOARDIO_NVM_SIZE) {
Matt Briggs 55:79ab0bbc5008 623 return cmdError;
Matt Briggs 55:79ab0bbc5008 624 }
Matt Briggs 55:79ab0bbc5008 625
Matt Briggs 55:79ab0bbc5008 626 mBaseboardIOFlag = *((uint16_t *) (data));
Matt Briggs 55:79ab0bbc5008 627 mBaseboardIORev = *((uint16_t *) (data+2));
Matt Briggs 55:79ab0bbc5008 628 mSerialNum = *((uint32_t *) (data+4));
Matt Briggs 55:79ab0bbc5008 629 mBaseboardIOConfig = *((uint32_t *) (data+6));
Matt Briggs 55:79ab0bbc5008 630
Matt Briggs 55:79ab0bbc5008 631 std::memcpy(&mPortExpanderROM0, data+0x10, 8);
Matt Briggs 55:79ab0bbc5008 632 std::memcpy(&mPortExpanderROM1, data+0x18, 8);
Matt Briggs 55:79ab0bbc5008 633
Matt Briggs 55:79ab0bbc5008 634 return cmdSuccess;
Matt Briggs 55:79ab0bbc5008 635 }
Matt Briggs 55:79ab0bbc5008 636 CmdResult NvmBBIOObj::toBytes(uint8_t *data, uint8_t &size) {
Matt Briggs 55:79ab0bbc5008 637 // TODO check data size
Matt Briggs 55:79ab0bbc5008 638
Matt Briggs 55:79ab0bbc5008 639 *((uint16_t *) (data)) = mBaseboardIOFlag;
Matt Briggs 55:79ab0bbc5008 640 *((uint16_t *) (data+2)) = mBaseboardIORev;
Matt Briggs 55:79ab0bbc5008 641 *((uint32_t *) (data+4)) = mSerialNum;
Matt Briggs 55:79ab0bbc5008 642 *((uint32_t *) (data+6)) = mBaseboardIOConfig;
Matt Briggs 55:79ab0bbc5008 643
Matt Briggs 55:79ab0bbc5008 644 std::memcpy(data+0x10, &mPortExpanderROM0, 8);
Matt Briggs 55:79ab0bbc5008 645 std::memcpy(data+0x18, &mPortExpanderROM1, 8);
Matt Briggs 55:79ab0bbc5008 646
Matt Briggs 55:79ab0bbc5008 647 size = BASEBOARDIO_NVM_SIZE;
Matt Briggs 55:79ab0bbc5008 648
Matt Briggs 55:79ab0bbc5008 649 return cmdSuccess;
Matt Briggs 55:79ab0bbc5008 650 }
Matt Briggs 55:79ab0bbc5008 651 uint16_t NvmBBIOObj::getBaseboardIOFlag()
Matt Briggs 55:79ab0bbc5008 652 {
Matt Briggs 55:79ab0bbc5008 653 return mBaseboardIOFlag;
Matt Briggs 55:79ab0bbc5008 654 }
Matt Briggs 55:79ab0bbc5008 655 bool NvmBBIOObj::validBaseboardIOFlag()
Matt Briggs 55:79ab0bbc5008 656 {
Matt Briggs 55:79ab0bbc5008 657 return mBaseboardIOFlag == BASEBOARDIO_FLAG;
Matt Briggs 55:79ab0bbc5008 658 }
Matt Briggs 55:79ab0bbc5008 659 uint16_t NvmBBIOObj::getBaseboardIORev()
Matt Briggs 55:79ab0bbc5008 660 {
Matt Briggs 55:79ab0bbc5008 661 return mBaseboardIORev;
Matt Briggs 55:79ab0bbc5008 662 }
Matt Briggs 55:79ab0bbc5008 663 bool NvmBBIOObj::validBaseboardIORev()
Matt Briggs 55:79ab0bbc5008 664 {
Matt Briggs 55:79ab0bbc5008 665 return mBaseboardIORev == BASEBOARDIO_REV;
Matt Briggs 55:79ab0bbc5008 666 }
Matt Briggs 55:79ab0bbc5008 667 uint16_t NvmBBIOObj::getSerialNum()
Matt Briggs 55:79ab0bbc5008 668 {
Matt Briggs 55:79ab0bbc5008 669 return mSerialNum;
Matt Briggs 55:79ab0bbc5008 670 }
Matt Briggs 55:79ab0bbc5008 671 void NvmBBIOObj::setSerialNum(uint16_t in)
Matt Briggs 55:79ab0bbc5008 672 {
Matt Briggs 55:79ab0bbc5008 673 mSerialNum = in;
Matt Briggs 55:79ab0bbc5008 674 }
Matt Briggs 55:79ab0bbc5008 675 uint32_t NvmBBIOObj::getBaseboardIOConfig()
Matt Briggs 55:79ab0bbc5008 676 {
Matt Briggs 55:79ab0bbc5008 677 return mBaseboardIOConfig;
Matt Briggs 55:79ab0bbc5008 678 }
Matt Briggs 55:79ab0bbc5008 679 void NvmBBIOObj::setBaseboardIOConfig(uint32_t in)
Matt Briggs 55:79ab0bbc5008 680 {
Matt Briggs 55:79ab0bbc5008 681 mBaseboardIOConfig = in;
Matt Briggs 55:79ab0bbc5008 682 }
Matt Briggs 55:79ab0bbc5008 683 void NvmBBIOObj::getPortExpanderROM0(uint8_t *addr)
Matt Briggs 55:79ab0bbc5008 684 {
Matt Briggs 55:79ab0bbc5008 685 std::memcpy(addr, &mPortExpanderROM0, 8);
Matt Briggs 55:79ab0bbc5008 686 }
Matt Briggs 55:79ab0bbc5008 687 void NvmBBIOObj::setPortExpanderROM0(const uint8_t *addr)
Matt Briggs 55:79ab0bbc5008 688 {
Matt Briggs 55:79ab0bbc5008 689 std::memcpy(&mPortExpanderROM0, addr, 8);
Matt Briggs 55:79ab0bbc5008 690 }
Matt Briggs 55:79ab0bbc5008 691 void NvmBBIOObj::getPortExpanderROM1(uint8_t *addr)
Matt Briggs 55:79ab0bbc5008 692 {
Matt Briggs 55:79ab0bbc5008 693 std::memcpy(addr, &mPortExpanderROM1, 8);
Matt Briggs 55:79ab0bbc5008 694 }
Matt Briggs 55:79ab0bbc5008 695 void NvmBBIOObj::setPortExpanderROM1(const uint8_t *addr)
Matt Briggs 55:79ab0bbc5008 696 {
Matt Briggs 55:79ab0bbc5008 697 std::memcpy(&mPortExpanderROM1, addr, 8);
Matt Briggs 55:79ab0bbc5008 698 }