Matt Briggs / Mbed OS xDotBridge_update_dev_latest

Fork to see if I can get working

Dependencies:   BufferedSerial OneWire WinbondSPIFlash libxDot-dev-mbed5-deprecated

Fork of xDotBridge_update_test20180823 by Matt Briggs

xDotBridge/src/BaseboardIO.cpp@98:3609f600c2f5, 2017-11-28 (annotated)

Committer:
mbriggs_vortex
Date:
Tue Nov 28 14:31:54 2017 -0700
Revision:
98:3609f600c2f5
Parent:
75:600cb3a9f126
Child:
99:83b54c851187
Adding first cut of term settings.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Matt Briggs 40:2ec4be320961 1 /*
Matt Briggs 40:2ec4be320961 2 * baseboardIO.cpp
Matt Briggs 40:2ec4be320961 3 *
Matt Briggs 40:2ec4be320961 4 * Created on: Jan 25, 2017
Matt Briggs 40:2ec4be320961 5 * Author: mbriggs
Matt Briggs 40:2ec4be320961 6 */
Matt Briggs 40:2ec4be320961 7
Matt Briggs 40:2ec4be320961 8 #include "BaseboardIO.h"
Matt Briggs 75:600cb3a9f126 9 #include "dot_util.h" // XXX just need the reference to dot somehow
Matt Briggs 58:15aa7a785b9f 10 #include "xdot_low_power.h"
Matt Briggs 63:e1efbe3402d9 11 #include "MyLog.h"
Matt Briggs 40:2ec4be320961 12
Matt Briggs 61:8d9efd33cac9 13 // Original
Matt Briggs 62:9751a8504c82 14 //const float COIL_ON_TIME = 0.030; // 30 ms
Matt Briggs 61:8d9efd33cac9 15 // Test
Matt Briggs 62:9751a8504c82 16 const float COIL_ON_TIME = 0.300; // 300 ms
Matt Briggs 61:8d9efd33cac9 17
Matt Briggs 44:ece6330e9b57 18
Matt Briggs 49:18f1354f9e51 19 // Port expander 0 (Currently U7)
Matt Briggs 44:ece6330e9b57 20 const uint8_t pEx0232En = 0x01;
Matt Briggs 44:ece6330e9b57 21 const uint8_t pEx0232TxDis = 0x02;
Matt Briggs 44:ece6330e9b57 22 const uint8_t pEx0Rot1B1 = 0x04;
Matt Briggs 44:ece6330e9b57 23 const uint8_t pEx0Rot1B2 = 0x08;
Matt Briggs 44:ece6330e9b57 24 const uint8_t pEx0Rot1B4 = 0x10;
Matt Briggs 44:ece6330e9b57 25 const uint8_t pEx0Rot1B8 = 0x20;
Matt Briggs 44:ece6330e9b57 26 const uint8_t pEx0Rot2B1 = 0x40;
Matt Briggs 44:ece6330e9b57 27 const uint8_t pEx0Rot2B2 = 0x80;
Matt Briggs 49:18f1354f9e51 28 const uint8_t pEx0OutMask = 0x03; // Only allow bits 0,1 to be changed
Matt Briggs 44:ece6330e9b57 29
Matt Briggs 49:18f1354f9e51 30 // Port expander 1 (Currently U8)
Matt Briggs 44:ece6330e9b57 31 const uint8_t pEx1NoNcSel = 0x01;
Matt Briggs 44:ece6330e9b57 32 const uint8_t pEx1RxTxSel = 0x02;
Matt Briggs 44:ece6330e9b57 33 const uint8_t pEx1WanSel = 0x04;
Matt Briggs 44:ece6330e9b57 34 const uint8_t pEx1SerialEn = 0x08; // Labeled as reserved
Matt Briggs 44:ece6330e9b57 35 const uint8_t pEx1Rot2B8 = 0x10;
Matt Briggs 44:ece6330e9b57 36 const uint8_t pEx1Rot2B4 = 0x20;
Matt Briggs 44:ece6330e9b57 37 const uint8_t pEx1RlyB = 0x40; // This is actually a coil
Matt Briggs 44:ece6330e9b57 38 const uint8_t pEx1RlyA = 0x80; // This is actually a coil
Matt Briggs 49:18f1354f9e51 39 const uint8_t pEx1OutMask = 0xC0; // Only allow bits 6,7 to be changed
Matt Briggs 44:ece6330e9b57 40
Matt Briggs 44:ece6330e9b57 41 /**
Matt Briggs 44:ece6330e9b57 42 * Note for interrupt within uC cannot use two pins with the same numeric suffix (e.g. cannot
Matt Briggs 44:ece6330e9b57 43 * use both PA_0 and PB_0). Note 1, 6, 7, 8, and 13 are used by LoRa radio.
Matt Briggs 44:ece6330e9b57 44 */
Matt Briggs 44:ece6330e9b57 45
Matt Briggs 40:2ec4be320961 46 BaseboardIO::BaseboardIO()
Matt Briggs 58:15aa7a785b9f 47 : mOWMaster(OneWireMasterPinName),
Matt Briggs 58:15aa7a785b9f 48 mCCIn(CCInPinName),
Matt Briggs 58:15aa7a785b9f 49 mTamper(TamperPinName),
Matt Briggs 58:15aa7a785b9f 50 mPairBtn(PairBtnPinName),
Matt Briggs 58:15aa7a785b9f 51 mLed(LedPinName),
Matt Briggs 60:5179449a684f 52 mLrrLed(LrrLedPinName, 0),
Matt Briggs 58:15aa7a785b9f 53 mSwitchedIOCtrl(SwitchedIOCtrlPinName, 0)
Matt Briggs 40:2ec4be320961 54 {
Matt Briggs 44:ece6330e9b57 55 mPortExpanderVal0 = 0x00;
Matt Briggs 44:ece6330e9b57 56 mPortExpanderVal1 = 0x00;
Matt Briggs 44:ece6330e9b57 57
Matt Briggs 44:ece6330e9b57 58 mPortEx0 = NULL;
Matt Briggs 44:ece6330e9b57 59 mPortEx1 = NULL;
Matt Briggs 40:2ec4be320961 60 }
Matt Briggs 56:40b454c952cc 61 CmdResult BaseboardIO::init(bool overwriteNvm)
Matt Briggs 40:2ec4be320961 62 {
Matt Briggs 56:40b454c952cc 63 bool storedROMsGood = false;
Matt Briggs 56:40b454c952cc 64 uint8_t val;
Matt Briggs 44:ece6330e9b57 65 // Setup port expanders
Matt Briggs 56:40b454c952cc 66 if (readInfoFromNVM() == cmdSuccess && !overwriteNvm) {
Matt Briggs 63:e1efbe3402d9 67 myLogInfo("Stored ROM0 Addr: %02x:%02x:%02x:%02x:%02x:%02x:%02x%02x found.",
Matt Briggs 63:e1efbe3402d9 68 mNvmObj.mPortExpanderROM0[7],
Matt Briggs 63:e1efbe3402d9 69 mNvmObj.mPortExpanderROM0[6],
Matt Briggs 63:e1efbe3402d9 70 mNvmObj.mPortExpanderROM0[5],
Matt Briggs 63:e1efbe3402d9 71 mNvmObj.mPortExpanderROM0[4],
Matt Briggs 63:e1efbe3402d9 72 mNvmObj.mPortExpanderROM0[3],
Matt Briggs 63:e1efbe3402d9 73 mNvmObj.mPortExpanderROM0[2],
Matt Briggs 63:e1efbe3402d9 74 mNvmObj.mPortExpanderROM0[1],
Matt Briggs 63:e1efbe3402d9 75 mNvmObj.mPortExpanderROM0[0]);
Matt Briggs 63:e1efbe3402d9 76 myLogInfo("Stored ROM1 Addr: %02x:%02x:%02x:%02x:%02x:%02x:%02x%02x found.",
Matt Briggs 63:e1efbe3402d9 77 mNvmObj.mPortExpanderROM1[7],
Matt Briggs 63:e1efbe3402d9 78 mNvmObj.mPortExpanderROM1[6],
Matt Briggs 63:e1efbe3402d9 79 mNvmObj.mPortExpanderROM1[5],
Matt Briggs 63:e1efbe3402d9 80 mNvmObj.mPortExpanderROM1[4],
Matt Briggs 63:e1efbe3402d9 81 mNvmObj.mPortExpanderROM1[3],
Matt Briggs 63:e1efbe3402d9 82 mNvmObj.mPortExpanderROM1[2],
Matt Briggs 63:e1efbe3402d9 83 mNvmObj.mPortExpanderROM1[1],
Matt Briggs 63:e1efbe3402d9 84 mNvmObj.mPortExpanderROM1[0]);
Matt Briggs 63:e1efbe3402d9 85 myLogInfo("BaseboardIO parameters successfully loaded from NVM");
Matt Briggs 56:40b454c952cc 86 // Check that the ROM Addresses are correct and valid
Matt Briggs 56:40b454c952cc 87 uint8_t portEx0Ctrl, portEx1Ctrl;
Matt Briggs 56:40b454c952cc 88 mPortEx0 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM0);
Matt Briggs 56:40b454c952cc 89 mPortEx0->registerReadReliable(0x8D, portEx0Ctrl);
Matt Briggs 56:40b454c952cc 90 // Gets 0xFF if it is not the correct address
Matt Briggs 63:e1efbe3402d9 91 myLogInfo("PortEx0 Control register reads %02X", portEx0Ctrl);
Matt Briggs 56:40b454c952cc 92
Matt Briggs 56:40b454c952cc 93 mPortEx1 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM1);
Matt Briggs 56:40b454c952cc 94 mPortEx1->registerReadReliable(0x8D, portEx1Ctrl);
Matt Briggs 63:e1efbe3402d9 95 myLogInfo("PortEx1 Control register reads %02X", portEx1Ctrl);
Matt Briggs 56:40b454c952cc 96 if ((portEx0Ctrl == 0xFF) || (portEx1Ctrl == 0xFF)) {
Matt Briggs 63:e1efbe3402d9 97 myLogError("Stored port expander ROM check failed. Set EEPROM to defaults.");
Matt Briggs 56:40b454c952cc 98 }
Matt Briggs 56:40b454c952cc 99 else {
Matt Briggs 56:40b454c952cc 100 storedROMsGood = true;
Matt Briggs 56:40b454c952cc 101 }
Matt Briggs 44:ece6330e9b57 102 }
Matt Briggs 56:40b454c952cc 103 if (!storedROMsGood)
Matt Briggs 56:40b454c952cc 104 { // EEPROM values not there or corrupt. Should only happen in factory.
Matt Briggs 55:79ab0bbc5008 105 mNvmObj.setDefaults();
Matt Briggs 47:a68747642a7a 106 // Find ROM address and test which one is which. Requires user
Matt Briggs 47:a68747642a7a 107 // switches to be in known state.
Matt Briggs 47:a68747642a7a 108 if (identifyPortExpanders() != cmdSuccess) {
Matt Briggs 63:e1efbe3402d9 109 myLogError("Error identifying port expanders");
Matt Briggs 44:ece6330e9b57 110 return cmdError;
Matt Briggs 44:ece6330e9b57 111 }
Matt Briggs 55:79ab0bbc5008 112 if (writeInfoToNVM() == cmdSuccess) {
Matt Briggs 63:e1efbe3402d9 113 myLogInfo("Baseboard config saved to NVM");
Matt Briggs 55:79ab0bbc5008 114 }
Matt Briggs 55:79ab0bbc5008 115 else {
Matt Briggs 63:e1efbe3402d9 116 myLogError("Baseboard config failed to save to NVM");
Matt Briggs 55:79ab0bbc5008 117 }
Matt Briggs 56:40b454c952cc 118 mPortEx0 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM0);
Matt Briggs 56:40b454c952cc 119 mPortEx0->registerReadReliable(0x8D, val);
Matt Briggs 56:40b454c952cc 120 // Gets 0xFF if it is not the correct address
Matt Briggs 63:e1efbe3402d9 121 myLogInfo("PortEx0 Control register reads %02X", val);
Matt Briggs 56:40b454c952cc 122 mPortEx1 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM1);
Matt Briggs 56:40b454c952cc 123 mPortEx1->registerReadReliable(0x8D, val);
Matt Briggs 63:e1efbe3402d9 124 myLogInfo("PortEx1 Control register reads %02X", val);
Matt Briggs 44:ece6330e9b57 125 }
Matt Briggs 44:ece6330e9b57 126
Matt Briggs 57:bdac7dd17af2 127 if (sampleUserSwitches() != cmdSuccess) {
Matt Briggs 63:e1efbe3402d9 128 myLogError("Error sampling user switches");
Matt Briggs 57:bdac7dd17af2 129 return cmdError;
Matt Briggs 57:bdac7dd17af2 130 }
Matt Briggs 57:bdac7dd17af2 131
Matt Briggs 44:ece6330e9b57 132 // Put relay in known state
Matt Briggs 47:a68747642a7a 133 if (relayNormal() != cmdSuccess) {
Matt Briggs 63:e1efbe3402d9 134 myLogError("Error setting relay during init");
Matt Briggs 47:a68747642a7a 135 return cmdError;
Matt Briggs 47:a68747642a7a 136 }
Matt Briggs 60:5179449a684f 137 ledOff();
Matt Briggs 47:a68747642a7a 138
Matt Briggs 63:e1efbe3402d9 139 myLogInfo("Baseboard IO initialization successful");
Matt Briggs 44:ece6330e9b57 140 return cmdSuccess;
Matt Briggs 40:2ec4be320961 141 }
Matt Briggs 40:2ec4be320961 142
Matt Briggs 40:2ec4be320961 143 // Registering for interrupts
Matt Briggs 44:ece6330e9b57 144 void BaseboardIO::regCCInInt(Callback<void()> func)
Matt Briggs 40:2ec4be320961 145 {
Matt Briggs 48:bab9f747d9ed 146 sampleUserSwitches();
Matt Briggs 48:bab9f747d9ed 147 if (isCCNO()) {
Matt Briggs 48:bab9f747d9ed 148 // Pulled high, switched low
Matt Briggs 48:bab9f747d9ed 149 mCCIn.fall(func);
Matt Briggs 48:bab9f747d9ed 150 }
Matt Briggs 48:bab9f747d9ed 151 else {
Matt Briggs 48:bab9f747d9ed 152 mCCIn.rise(func);
Matt Briggs 48:bab9f747d9ed 153 }
Matt Briggs 53:a1563574a980 154 mCCIn.mode(PullNone);
Matt Briggs 49:18f1354f9e51 155 mCCIn.enable_irq();
Matt Briggs 40:2ec4be320961 156 }
Matt Briggs 44:ece6330e9b57 157 void BaseboardIO::regTamperInt(Callback<void()> func)
Matt Briggs 40:2ec4be320961 158 {
Matt Briggs 44:ece6330e9b57 159 // Pulled high, switched low
Matt Briggs 53:a1563574a980 160 mTamper.mode(PullNone);
Matt Briggs 49:18f1354f9e51 161 mTamper.rise(func);
Matt Briggs 44:ece6330e9b57 162 mTamper.fall(func);
Matt Briggs 49:18f1354f9e51 163 mTamper.enable_irq();
Matt Briggs 40:2ec4be320961 164 }
Matt Briggs 44:ece6330e9b57 165 void BaseboardIO::regPairBtnInt(Callback<void()> func)
Matt Briggs 40:2ec4be320961 166 {
Matt Briggs 44:ece6330e9b57 167 // Pulled low, switched high
Matt Briggs 58:15aa7a785b9f 168 mPairBtn.mode(PullNone);
Matt Briggs 44:ece6330e9b57 169 mPairBtn.rise(func);
Matt Briggs 49:18f1354f9e51 170 mPairBtn.enable_irq();
Matt Briggs 40:2ec4be320961 171 }
Matt Briggs 40:2ec4be320961 172
Matt Briggs 40:2ec4be320961 173 // Input
Matt Briggs 40:2ec4be320961 174 CmdResult BaseboardIO::sampleUserSwitches()
Matt Briggs 40:2ec4be320961 175 {
Matt Briggs 48:bab9f747d9ed 176 if ((mPortEx0 == NULL) || (mPortEx1 == NULL))
Matt Briggs 48:bab9f747d9ed 177 return cmdError;
Matt Briggs 44:ece6330e9b57 178 // Sample port expanders
Matt Briggs 49:18f1354f9e51 179 enableSwitchedIO();
Matt Briggs 49:18f1354f9e51 180 wait(0.001); // Wait 1 ms
Matt Briggs 53:a1563574a980 181 if (mPortEx0->pioLogicReliableRead(mPortExpanderVal0) != cmdSuccess) {
Matt Briggs 49:18f1354f9e51 182 disableSwitchedIO();
Matt Briggs 63:e1efbe3402d9 183 myLogError("Error reading port expander 0.");
Matt Briggs 44:ece6330e9b57 184 return cmdError;
Matt Briggs 44:ece6330e9b57 185 }
Matt Briggs 53:a1563574a980 186 if (mPortEx1->pioLogicReliableRead(mPortExpanderVal1) != cmdSuccess) {
Matt Briggs 49:18f1354f9e51 187 disableSwitchedIO();
Matt Briggs 63:e1efbe3402d9 188 myLogError("Error reading port expander 1.");
Matt Briggs 44:ece6330e9b57 189 return cmdError;
Matt Briggs 44:ece6330e9b57 190 }
Matt Briggs 49:18f1354f9e51 191 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 192 return cmdSuccess;
Matt Briggs 40:2ec4be320961 193 }
Matt Briggs 57:bdac7dd17af2 194 bool BaseboardIO::isCCInAlert()
Matt Briggs 57:bdac7dd17af2 195 {
Matt Briggs 57:bdac7dd17af2 196 if (isCCNO()) { // If NO then the CCIn should float high if not in alert state
Matt Briggs 57:bdac7dd17af2 197 return mCCIn == 0;
Matt Briggs 57:bdac7dd17af2 198 }
Matt Briggs 57:bdac7dd17af2 199 else { // If NC then the CCIN should be held low if not in alert state
Matt Briggs 57:bdac7dd17af2 200 return mCCIn == 1;
Matt Briggs 57:bdac7dd17af2 201 }
Matt Briggs 57:bdac7dd17af2 202 }
Matt Briggs 40:2ec4be320961 203 bool BaseboardIO::isPairBtn()
Matt Briggs 40:2ec4be320961 204 {
Matt Briggs 44:ece6330e9b57 205 // Depressed button is high
Matt Briggs 44:ece6330e9b57 206 return mPairBtn.read() == 1;
Matt Briggs 40:2ec4be320961 207 }
Matt Briggs 48:bab9f747d9ed 208 bool BaseboardIO::isCCNO()
Matt Briggs 40:2ec4be320961 209 {
Matt Briggs 44:ece6330e9b57 210 // When DIP switch is not closed (i.e. value reads high) assume NO
Matt Briggs 49:18f1354f9e51 211 return (mPortExpanderVal1 & pEx1NoNcSel) != 0; // Open NO, closed NC
Matt Briggs 40:2ec4be320961 212 }
mbriggs_vortex 98:3609f600c2f5 213 void BaseboardIO::setIsCCNO(bool val)
mbriggs_vortex 98:3609f600c2f5 214 {
mbriggs_vortex 98:3609f600c2f5 215 // When DIP switch is not closed (i.e. value reads high) assume NO
mbriggs_vortex 98:3609f600c2f5 216 if (val) {
mbriggs_vortex 98:3609f600c2f5 217 mPortExpanderVal1 |= pEx1NoNcSel; // Set bit
mbriggs_vortex 98:3609f600c2f5 218 }
mbriggs_vortex 98:3609f600c2f5 219 else {
mbriggs_vortex 98:3609f600c2f5 220 mPortExpanderVal1 &= ~pEx1NoNcSel; // Clear bit
mbriggs_vortex 98:3609f600c2f5 221 }
mbriggs_vortex 98:3609f600c2f5 222 }
Matt Briggs 40:2ec4be320961 223 bool BaseboardIO::isRx()
Matt Briggs 40:2ec4be320961 224 {
Matt Briggs 44:ece6330e9b57 225 // When DIP switch is not closed (i.e. value reads high) assume RX
Matt Briggs 44:ece6330e9b57 226 return (mPortExpanderVal1 & pEx1RxTxSel) != 0;
Matt Briggs 40:2ec4be320961 227 }
mbriggs_vortex 98:3609f600c2f5 228 void BaseboardIO::setIsRx(bool val)
mbriggs_vortex 98:3609f600c2f5 229 {
mbriggs_vortex 98:3609f600c2f5 230 // When DIP switch is not closed (i.e. value reads high) assume RX
mbriggs_vortex 98:3609f600c2f5 231 if (val) {
mbriggs_vortex 98:3609f600c2f5 232 mPortExpanderVal1 |= pEx1RxTxSel; // Set bit
mbriggs_vortex 98:3609f600c2f5 233 }
mbriggs_vortex 98:3609f600c2f5 234 else {
mbriggs_vortex 98:3609f600c2f5 235 mPortExpanderVal1 &= ~pEx1RxTxSel; // Clear bit
mbriggs_vortex 98:3609f600c2f5 236 }
mbriggs_vortex 98:3609f600c2f5 237 }
Matt Briggs 40:2ec4be320961 238 bool BaseboardIO::isLoRaWANMode()
Matt Briggs 40:2ec4be320961 239 {
Matt Briggs 44:ece6330e9b57 240 // When DIP switch is not closed (i.e. value reads high) assume P2P not WAN
Matt Briggs 44:ece6330e9b57 241 return (mPortExpanderVal1 & pEx1WanSel) == 0;
Matt Briggs 40:2ec4be320961 242 }
Matt Briggs 50:e89647e77fd5 243 bool BaseboardIO::isSerialEnabled()
Matt Briggs 50:e89647e77fd5 244 {
Matt Briggs 50:e89647e77fd5 245 // When DIP switch is not closed (i.e. value reads high) assume not in serial mode
Matt Briggs 50:e89647e77fd5 246 return (mPortExpanderVal1 & pEx1SerialEn) == 0;
Matt Briggs 50:e89647e77fd5 247 }
Matt Briggs 40:2ec4be320961 248 uint8_t BaseboardIO::rotarySwitch1()
Matt Briggs 40:2ec4be320961 249 {
Matt Briggs 44:ece6330e9b57 250 // If a bit of a nibble is asserted then the port expander line is switched low.
Matt Briggs 44:ece6330e9b57 251 uint8_t val = 0;
Matt Briggs 44:ece6330e9b57 252 if ((mPortExpanderVal0 & pEx0Rot1B8) == 0)
Matt Briggs 44:ece6330e9b57 253 val |= 0x08;
Matt Briggs 44:ece6330e9b57 254 if ((mPortExpanderVal0 & pEx0Rot1B4) == 0)
Matt Briggs 44:ece6330e9b57 255 val |= 0x04;
Matt Briggs 44:ece6330e9b57 256 if ((mPortExpanderVal0 & pEx0Rot1B2) == 0)
Matt Briggs 44:ece6330e9b57 257 val |= 0x02;
Matt Briggs 44:ece6330e9b57 258 if ((mPortExpanderVal0 & pEx0Rot1B1) == 0)
Matt Briggs 44:ece6330e9b57 259 val |= 0x01;
Matt Briggs 44:ece6330e9b57 260 return val;
Matt Briggs 40:2ec4be320961 261 }
mbriggs_vortex 98:3609f600c2f5 262 void BaseboardIO::setRotarySwitch1(uint8_t val)
mbriggs_vortex 98:3609f600c2f5 263 {
mbriggs_vortex 98:3609f600c2f5 264 if ((val & 0x08) == 1) {
mbriggs_vortex 98:3609f600c2f5 265 mPortExpanderVal0 &= ~pEx0Rot1B8;
mbriggs_vortex 98:3609f600c2f5 266 }
mbriggs_vortex 98:3609f600c2f5 267 if ((val & 0x04) == 1) {
mbriggs_vortex 98:3609f600c2f5 268 mPortExpanderVal0 &= ~pEx0Rot1B4;
mbriggs_vortex 98:3609f600c2f5 269 }
mbriggs_vortex 98:3609f600c2f5 270 if ((val & 0x02) == 1) {
mbriggs_vortex 98:3609f600c2f5 271 mPortExpanderVal0 &= ~pEx0Rot1B2;
mbriggs_vortex 98:3609f600c2f5 272 }
mbriggs_vortex 98:3609f600c2f5 273 if ((val & 0x01) == 1) {
mbriggs_vortex 98:3609f600c2f5 274 mPortExpanderVal0 &= ~pEx0Rot1B1;
mbriggs_vortex 98:3609f600c2f5 275 }
mbriggs_vortex 98:3609f600c2f5 276 }
Matt Briggs 40:2ec4be320961 277 uint8_t BaseboardIO::rotarySwitch2()
Matt Briggs 40:2ec4be320961 278 {
Matt Briggs 44:ece6330e9b57 279 // If a bit of a nibble is asserted then the port expander line is switched low.
Matt Briggs 44:ece6330e9b57 280 uint8_t val = 0;
Matt Briggs 44:ece6330e9b57 281 if ((mPortExpanderVal1 & pEx1Rot2B8) == 0)
Matt Briggs 44:ece6330e9b57 282 val |= 0x08;
Matt Briggs 44:ece6330e9b57 283 if ((mPortExpanderVal1 & pEx1Rot2B4) == 0)
Matt Briggs 44:ece6330e9b57 284 val |= 0x04;
Matt Briggs 44:ece6330e9b57 285 if ((mPortExpanderVal0 & pEx0Rot2B2) == 0)
Matt Briggs 44:ece6330e9b57 286 val |= 0x02;
Matt Briggs 44:ece6330e9b57 287 if ((mPortExpanderVal0 & pEx0Rot2B1) == 0)
Matt Briggs 44:ece6330e9b57 288 val |= 0x01;
Matt Briggs 44:ece6330e9b57 289 return val;
Matt Briggs 40:2ec4be320961 290 }
Matt Briggs 40:2ec4be320961 291
Matt Briggs 40:2ec4be320961 292 // Output
Matt Briggs 40:2ec4be320961 293 CmdResult BaseboardIO::ledOn()
Matt Briggs 40:2ec4be320961 294 {
Matt Briggs 44:ece6330e9b57 295 mLed = 1;
Matt Briggs 59:485545afc4dc 296 #if ALSO_USE_LRR_LED
Matt Briggs 59:485545afc4dc 297 mLrrLed = 1;
Matt Briggs 59:485545afc4dc 298 #endif
Matt Briggs 44:ece6330e9b57 299 return cmdSuccess;
Matt Briggs 40:2ec4be320961 300 }
Matt Briggs 40:2ec4be320961 301 CmdResult BaseboardIO::ledOff()
Matt Briggs 40:2ec4be320961 302 {
Matt Briggs 44:ece6330e9b57 303 mLed = 0;
Matt Briggs 60:5179449a684f 304 // Always allow setting GPIO0 to 0
Matt Briggs 60:5179449a684f 305 //#if ALSO_USE_LRR_LED
Matt Briggs 59:485545afc4dc 306 mLrrLed = 0;
Matt Briggs 60:5179449a684f 307 //#endif
Matt Briggs 44:ece6330e9b57 308 return cmdSuccess;
Matt Briggs 40:2ec4be320961 309 }
Matt Briggs 40:2ec4be320961 310 CmdResult BaseboardIO::relayAlert()
Matt Briggs 40:2ec4be320961 311 {
Matt Briggs 48:bab9f747d9ed 312 if (isCCNO()) { // Normally Open
Matt Briggs 44:ece6330e9b57 313 return closeRelay();
Matt Briggs 44:ece6330e9b57 314 }
Matt Briggs 44:ece6330e9b57 315 else { // Normally Close
Matt Briggs 44:ece6330e9b57 316 return openRelay();
Matt Briggs 44:ece6330e9b57 317 }
Matt Briggs 40:2ec4be320961 318 }
Matt Briggs 40:2ec4be320961 319 CmdResult BaseboardIO::relayNormal()
Matt Briggs 40:2ec4be320961 320 {
Matt Briggs 48:bab9f747d9ed 321 if (isCCNO()) { // Normally Open
Matt Briggs 44:ece6330e9b57 322 return openRelay();
Matt Briggs 44:ece6330e9b57 323 }
Matt Briggs 44:ece6330e9b57 324 else { // Normally Close
Matt Briggs 44:ece6330e9b57 325 return closeRelay();
Matt Briggs 44:ece6330e9b57 326 }
Matt Briggs 40:2ec4be320961 327 }
Matt Briggs 40:2ec4be320961 328
Matt Briggs 40:2ec4be320961 329 // Future
Matt Briggs 40:2ec4be320961 330 CmdResult BaseboardIO::serialRx(bool enable)
Matt Briggs 40:2ec4be320961 331 {
Matt Briggs 44:ece6330e9b57 332 uint8_t val;
Matt Briggs 49:18f1354f9e51 333 if (mPortEx0 == NULL) {
Matt Briggs 63:e1efbe3402d9 334 myLogError("Error enabling 232. Port expanders not initialized.");
Matt Briggs 49:18f1354f9e51 335 return cmdError;
Matt Briggs 49:18f1354f9e51 336 }
Matt Briggs 53:a1563574a980 337 mPortEx0->pioLogicReliableRead(val);
Matt Briggs 44:ece6330e9b57 338
Matt Briggs 44:ece6330e9b57 339 // Active low from port expander -> pmos -> 232 (active chip EN)
Matt Briggs 44:ece6330e9b57 340 if (enable) {
Matt Briggs 44:ece6330e9b57 341 val &= ~pEx0232En;
Matt Briggs 44:ece6330e9b57 342 }
Matt Briggs 44:ece6330e9b57 343 else {
Matt Briggs 44:ece6330e9b57 344 val |= pEx0232En;
Matt Briggs 44:ece6330e9b57 345 }
Matt Briggs 44:ece6330e9b57 346
Matt Briggs 53:a1563574a980 347 if (mPortEx0->pioLogicReliableWrite(val | ~pEx0OutMask) != cmdSuccess) {
Matt Briggs 63:e1efbe3402d9 348 myLogError("Error enabling 232");
Matt Briggs 44:ece6330e9b57 349 return cmdError;
Matt Briggs 44:ece6330e9b57 350 }
Matt Briggs 44:ece6330e9b57 351 return cmdSuccess;
Matt Briggs 44:ece6330e9b57 352 }
Matt Briggs 44:ece6330e9b57 353 CmdResult BaseboardIO::serialTx(bool enable)
Matt Briggs 44:ece6330e9b57 354 {
Matt Briggs 44:ece6330e9b57 355 uint8_t val;
Matt Briggs 49:18f1354f9e51 356 if (mPortEx0 == NULL) {
Matt Briggs 63:e1efbe3402d9 357 myLogError("Error enabling 232 TX. Port expanders not initialized.");
Matt Briggs 49:18f1354f9e51 358 return cmdError;
Matt Briggs 49:18f1354f9e51 359 }
Matt Briggs 53:a1563574a980 360 mPortEx0->pioLogicReliableRead(val);
Matt Briggs 44:ece6330e9b57 361
Matt Briggs 44:ece6330e9b57 362 // Active high tx disable therefore active low tx enable (note chip must also be enabled for TX)
Matt Briggs 44:ece6330e9b57 363 if (enable) {
Matt Briggs 44:ece6330e9b57 364 val &= ~pEx0232TxDis;
Matt Briggs 44:ece6330e9b57 365 }
Matt Briggs 44:ece6330e9b57 366 else {
Matt Briggs 44:ece6330e9b57 367 val |= pEx0232TxDis;
Matt Briggs 44:ece6330e9b57 368 }
Matt Briggs 44:ece6330e9b57 369
Matt Briggs 53:a1563574a980 370 if (mPortEx0->pioLogicReliableWrite(val | ~pEx0OutMask) != cmdSuccess) {
Matt Briggs 63:e1efbe3402d9 371 myLogError("Error enabling 232 TX");
Matt Briggs 44:ece6330e9b57 372 return cmdError;
Matt Briggs 44:ece6330e9b57 373 }
Matt Briggs 44:ece6330e9b57 374 return cmdSuccess;
Matt Briggs 44:ece6330e9b57 375 }
Matt Briggs 44:ece6330e9b57 376
Matt Briggs 44:ece6330e9b57 377 // private
Matt Briggs 44:ece6330e9b57 378 CmdResult BaseboardIO::readInfoFromNVM()
Matt Briggs 44:ece6330e9b57 379 {
Matt Briggs 55:79ab0bbc5008 380 bool nvmReadResult;
Matt Briggs 55:79ab0bbc5008 381 uint8_t *data = new uint8_t [BASEBOARDIO_NVM_SIZE];
Matt Briggs 55:79ab0bbc5008 382
Matt Briggs 55:79ab0bbc5008 383 nvmReadResult = dot->nvmRead(BASEBOARDIO_NVM_START_ADDR, data, BASEBOARDIO_NVM_SIZE);
Matt Briggs 55:79ab0bbc5008 384 if (!nvmReadResult) {
Matt Briggs 55:79ab0bbc5008 385 delete [] data;
Matt Briggs 55:79ab0bbc5008 386 return cmdError;
Matt Briggs 55:79ab0bbc5008 387 }
Matt Briggs 55:79ab0bbc5008 388 mNvmObj.fromBytes(data, BASEBOARDIO_NVM_SIZE);
Matt Briggs 55:79ab0bbc5008 389 delete [] data;
Matt Briggs 55:79ab0bbc5008 390 if (!mNvmObj.validBaseboardIOFlag()) {
Matt Briggs 63:e1efbe3402d9 391 myLogWarning("Invalid BaseboardIO Flag. Using default values.");
Matt Briggs 55:79ab0bbc5008 392 return cmdError;
Matt Briggs 55:79ab0bbc5008 393 }
Matt Briggs 55:79ab0bbc5008 394 else if (!mNvmObj.validBaseboardIORev()) {
Matt Briggs 63:e1efbe3402d9 395 myLogWarning("Invalid BaseboardIO Rev. Using default values.");
Matt Briggs 55:79ab0bbc5008 396 return cmdError;
Matt Briggs 55:79ab0bbc5008 397 }
Matt Briggs 55:79ab0bbc5008 398 else {
Matt Briggs 55:79ab0bbc5008 399 return cmdSuccess;
Matt Briggs 55:79ab0bbc5008 400 }
Matt Briggs 40:2ec4be320961 401 }
Matt Briggs 44:ece6330e9b57 402 CmdResult BaseboardIO::writeInfoToNVM()
Matt Briggs 40:2ec4be320961 403 {
Matt Briggs 55:79ab0bbc5008 404 uint8_t *data = new uint8_t [BASEBOARDIO_NVM_SIZE];
Matt Briggs 55:79ab0bbc5008 405 uint8_t size = BASEBOARDIO_NVM_SIZE;
Matt Briggs 55:79ab0bbc5008 406 mNvmObj.toBytes(data, size);
Matt Briggs 55:79ab0bbc5008 407 dot->nvmWrite(BASEBOARDIO_NVM_START_ADDR, data, BASEBOARDIO_NVM_SIZE);
Matt Briggs 55:79ab0bbc5008 408
Matt Briggs 55:79ab0bbc5008 409 delete [] data;
Matt Briggs 55:79ab0bbc5008 410 return cmdSuccess;
Matt Briggs 40:2ec4be320961 411 }
Matt Briggs 44:ece6330e9b57 412 CmdResult BaseboardIO::identifyPortExpanders()
Matt Briggs 44:ece6330e9b57 413 {
Matt Briggs 44:ece6330e9b57 414 uint8_t addr[8];
Matt Briggs 44:ece6330e9b57 415 uint8_t result;
Matt Briggs 49:18f1354f9e51 416 int i;
Matt Briggs 40:2ec4be320961 417
Matt Briggs 44:ece6330e9b57 418 // Search Bus
Matt Briggs 63:e1efbe3402d9 419 myLogInfo("Starting OneWire Search");
Matt Briggs 49:18f1354f9e51 420 enableSwitchedIO();
Matt Briggs 49:18f1354f9e51 421 for (int j=0;j<10;j++) { // Try 5 times
Matt Briggs 49:18f1354f9e51 422 i=0;
Matt Briggs 49:18f1354f9e51 423 mOWMaster.reset();
Matt Briggs 49:18f1354f9e51 424 mOWMaster.reset_search();
Matt Briggs 49:18f1354f9e51 425 wait(1.0);
Matt Briggs 49:18f1354f9e51 426 while (true) {
Matt Briggs 49:18f1354f9e51 427 // TODO maybe change to family based search
Matt Briggs 49:18f1354f9e51 428 result = mOWMaster.search(addr);
Matt Briggs 49:18f1354f9e51 429 if (result != 1) {
Matt Briggs 49:18f1354f9e51 430 break;
Matt Briggs 49:18f1354f9e51 431 }
Matt Briggs 63:e1efbe3402d9 432 myLogInfo("ROM Addr: %02x:%02x:%02x:%02x:%02x:%02x:%02x%02x found.",
Matt Briggs 49:18f1354f9e51 433 addr[7],addr[6],addr[5],addr[4],addr[3],addr[2],addr[1],addr[0]);
Matt Briggs 49:18f1354f9e51 434 if (i == 0) {
Matt Briggs 55:79ab0bbc5008 435 std::memcpy(mNvmObj.mPortExpanderROM0, addr, sizeof(mNvmObj.mPortExpanderROM0));
Matt Briggs 49:18f1354f9e51 436 }
Matt Briggs 49:18f1354f9e51 437 else if (i == 1) {
Matt Briggs 55:79ab0bbc5008 438 std::memcpy(mNvmObj.mPortExpanderROM1, addr, sizeof(mNvmObj.mPortExpanderROM1));
Matt Briggs 49:18f1354f9e51 439 }
Matt Briggs 49:18f1354f9e51 440 i++;
Matt Briggs 49:18f1354f9e51 441 }
Matt Briggs 49:18f1354f9e51 442 // TODO maybe only allow a reasonable number of Port Expanders
Matt Briggs 49:18f1354f9e51 443 if (i >=2) {
Matt Briggs 44:ece6330e9b57 444 break;
Matt Briggs 44:ece6330e9b57 445 }
Matt Briggs 44:ece6330e9b57 446 }
Matt Briggs 44:ece6330e9b57 447
Matt Briggs 63:e1efbe3402d9 448 myLogInfo("Finished OneWire Search");
Matt Briggs 44:ece6330e9b57 449 if (i != 2) {
Matt Briggs 63:e1efbe3402d9 450 myLogError("Incorrect Number of OneWire devices (Got %d. Expected 2) OneWire port expanders found.", i);
Matt Briggs 44:ece6330e9b57 451 return cmdError;
Matt Briggs 44:ece6330e9b57 452 }
Matt Briggs 44:ece6330e9b57 453
Matt Briggs 49:18f1354f9e51 454 // All rotary switches should be at 0. DIPS should be asserted.
Matt Briggs 44:ece6330e9b57 455 // If switches are set in factory default mode then port expander 1 should read 0xFF and
Matt Briggs 44:ece6330e9b57 456 // port expander 2 should read 0xF0.
Matt Briggs 40:2ec4be320961 457
Matt Briggs 55:79ab0bbc5008 458 mPortEx0 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM0);
Matt Briggs 55:79ab0bbc5008 459 mPortEx1 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM1);
Matt Briggs 44:ece6330e9b57 460
Matt Briggs 49:18f1354f9e51 461
Matt Briggs 49:18f1354f9e51 462 enableSwitchedIO();
Matt Briggs 53:a1563574a980 463 if (mPortEx0->pioLogicReliableRead(mPortExpanderVal0) != cmdSuccess) {
Matt Briggs 63:e1efbe3402d9 464 myLogError("Error during port expander ID. Read failed.");
Matt Briggs 49:18f1354f9e51 465 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 466 delete mPortEx0;
Matt Briggs 44:ece6330e9b57 467 delete mPortEx1;
Matt Briggs 44:ece6330e9b57 468 return cmdError;
Matt Briggs 44:ece6330e9b57 469 }
Matt Briggs 53:a1563574a980 470 if (mPortEx1->pioLogicReliableRead(mPortExpanderVal1) != cmdSuccess) {
Matt Briggs 63:e1efbe3402d9 471 myLogError("Error during port expander ID. Read failed.");
Matt Briggs 49:18f1354f9e51 472 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 473 delete mPortEx0;
Matt Briggs 44:ece6330e9b57 474 delete mPortEx1;
Matt Briggs 44:ece6330e9b57 475 return cmdError;
Matt Briggs 44:ece6330e9b57 476 }
Matt Briggs 44:ece6330e9b57 477
Matt Briggs 49:18f1354f9e51 478 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 479 if ((mPortExpanderVal0 == 0xFF) and (mPortExpanderVal1 == 0xF0)) { // Luckily got it right
Matt Briggs 63:e1efbe3402d9 480 myLogInfo("ROMS Swap Not Needed.");
Matt Briggs 44:ece6330e9b57 481 }
Matt Briggs 44:ece6330e9b57 482 else if ((mPortExpanderVal0 == 0xF0) and (mPortExpanderVal1 == 0xFF)) { // Just need to swap
Matt Briggs 55:79ab0bbc5008 483 std::memcpy(addr, mNvmObj.mPortExpanderROM0, sizeof(addr)); // Store Orig ROM0 -> addr
Matt Briggs 55:79ab0bbc5008 484 std::memcpy(mNvmObj.mPortExpanderROM0, mNvmObj.mPortExpanderROM1, sizeof(mNvmObj.mPortExpanderROM0)); // Store Orig ROM1 -> ROM0
Matt Briggs 55:79ab0bbc5008 485 std::memcpy(mNvmObj.mPortExpanderROM1, addr, sizeof(mNvmObj.mPortExpanderROM1)); // Store Orig ROM0 (addr) -> ROM1
Matt Briggs 63:e1efbe3402d9 486 myLogInfo("Swapped ROMS.");
Matt Briggs 44:ece6330e9b57 487 }
Matt Briggs 44:ece6330e9b57 488 else {
Matt Briggs 63:e1efbe3402d9 489 myLogError("Error during port expander ID. Port expanders not in "
Matt Briggs 55:79ab0bbc5008 490 "expected states (0xFF and 0xF0). Check user switches. Got %02X and %02X",
Matt Briggs 49:18f1354f9e51 491 mPortExpanderVal0, mPortExpanderVal1);
Matt Briggs 44:ece6330e9b57 492 delete mPortEx0;
Matt Briggs 44:ece6330e9b57 493 delete mPortEx1;
Matt Briggs 44:ece6330e9b57 494 return cmdError;
Matt Briggs 44:ece6330e9b57 495 }
Matt Briggs 44:ece6330e9b57 496
Matt Briggs 44:ece6330e9b57 497 // Cleanup
Matt Briggs 44:ece6330e9b57 498 delete mPortEx0;
Matt Briggs 44:ece6330e9b57 499 delete mPortEx1;
Matt Briggs 44:ece6330e9b57 500
Matt Briggs 44:ece6330e9b57 501 return cmdSuccess;
Matt Briggs 40:2ec4be320961 502 }
Matt Briggs 49:18f1354f9e51 503 CmdResult BaseboardIO::openRelay() {
Matt Briggs 44:ece6330e9b57 504 uint8_t val;
Matt Briggs 53:a1563574a980 505 mPortEx1->pioLogicReliableRead(val);
Matt Briggs 44:ece6330e9b57 506
Matt Briggs 49:18f1354f9e51 507 val |= pEx1RlyA; // Make sure Relay A is off
Matt Briggs 49:18f1354f9e51 508 val &= ~pEx1RlyB; // Turn on Relay B
Matt Briggs 44:ece6330e9b57 509
Matt Briggs 53:a1563574a980 510 if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) {
Matt Briggs 49:18f1354f9e51 511 val |= pEx1RlyA; // Turn Relay A off
Matt Briggs 49:18f1354f9e51 512 val |= pEx1RlyB; // Turn Relay B off
Matt Briggs 53:a1563574a980 513 mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask); // Write a non assert value just to try to overcome an error
Matt Briggs 63:e1efbe3402d9 514 myLogError ("Error turning on coil. Turning both coils off.");
Matt Briggs 44:ece6330e9b57 515 return cmdError;
Matt Briggs 44:ece6330e9b57 516 }
Matt Briggs 44:ece6330e9b57 517
Matt Briggs 47:a68747642a7a 518 wait(COIL_ON_TIME);
Matt Briggs 44:ece6330e9b57 519
Matt Briggs 49:18f1354f9e51 520 val |= pEx1RlyA; // Turn Relay A off
Matt Briggs 49:18f1354f9e51 521 val |= pEx1RlyB; // Turn Relay B off
Matt Briggs 44:ece6330e9b57 522
Matt Briggs 53:a1563574a980 523 if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) {
Matt Briggs 53:a1563574a980 524 mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask);
Matt Briggs 63:e1efbe3402d9 525 myLogError ("Error turning off coils. Trying again.");
Matt Briggs 44:ece6330e9b57 526 return cmdError;
Matt Briggs 44:ece6330e9b57 527 }
Matt Briggs 44:ece6330e9b57 528
Matt Briggs 44:ece6330e9b57 529 return cmdSuccess;
Matt Briggs 40:2ec4be320961 530 }
Matt Briggs 49:18f1354f9e51 531 CmdResult BaseboardIO::closeRelay() {
Matt Briggs 44:ece6330e9b57 532 uint8_t val;
Matt Briggs 53:a1563574a980 533 mPortEx1->pioLogicReliableRead(val);
Matt Briggs 44:ece6330e9b57 534
Matt Briggs 49:18f1354f9e51 535 val &= ~pEx1RlyA; // Turn on Relay A
Matt Briggs 49:18f1354f9e51 536 val |= pEx1RlyB; // Make sure Relay B is off
Matt Briggs 44:ece6330e9b57 537
Matt Briggs 53:a1563574a980 538 if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) {
Matt Briggs 49:18f1354f9e51 539 val |= pEx1RlyA; // Turn Relay A off
Matt Briggs 49:18f1354f9e51 540 val |= pEx1RlyB; // Turn Relay B off
Matt Briggs 53:a1563574a980 541 mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask); // Write a non assert value just to try to overcome an error
Matt Briggs 63:e1efbe3402d9 542 myLogError ("Error turning on coil. Turning both coils off.");
Matt Briggs 44:ece6330e9b57 543 return cmdError;
Matt Briggs 44:ece6330e9b57 544 }
Matt Briggs 44:ece6330e9b57 545
Matt Briggs 47:a68747642a7a 546 wait(COIL_ON_TIME);
Matt Briggs 44:ece6330e9b57 547
Matt Briggs 49:18f1354f9e51 548 val |= pEx1RlyA; // Turn Relay A off
Matt Briggs 49:18f1354f9e51 549 val |= pEx1RlyB; // Turn Relay B off
Matt Briggs 44:ece6330e9b57 550
Matt Briggs 53:a1563574a980 551 if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) {
Matt Briggs 53:a1563574a980 552 mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask);
Matt Briggs 63:e1efbe3402d9 553 myLogError ("Error turning off coils. Trying again.");
Matt Briggs 44:ece6330e9b57 554 return cmdError;
Matt Briggs 44:ece6330e9b57 555 }
Matt Briggs 44:ece6330e9b57 556
Matt Briggs 44:ece6330e9b57 557 return cmdSuccess;
Matt Briggs 40:2ec4be320961 558 }
Matt Briggs 55:79ab0bbc5008 559
Matt Briggs 58:15aa7a785b9f 560 CmdResult BaseboardIO::prepareSleep()
Matt Briggs 58:15aa7a785b9f 561 {
Matt Briggs 58:15aa7a785b9f 562 // Save current GPUIO state
Matt Briggs 58:15aa7a785b9f 563 xdot_save_gpio_state();
Matt Briggs 58:15aa7a785b9f 564
Matt Briggs 58:15aa7a785b9f 565 // Configure all IO expect for pins for interrupt in lowest mode possible
Matt Briggs 58:15aa7a785b9f 566 // GPIO Ports Clock Enable
Matt Briggs 58:15aa7a785b9f 567 __GPIOA_CLK_ENABLE();
Matt Briggs 58:15aa7a785b9f 568 __GPIOB_CLK_ENABLE();
Matt Briggs 58:15aa7a785b9f 569 __GPIOC_CLK_ENABLE();
Matt Briggs 58:15aa7a785b9f 570 __GPIOH_CLK_ENABLE();
Matt Briggs 58:15aa7a785b9f 571
Matt Briggs 58:15aa7a785b9f 572 GPIO_InitTypeDef GPIO_InitStruct;
Matt Briggs 58:15aa7a785b9f 573
Matt Briggs 58:15aa7a785b9f 574 // UART1_TX, UART1_RTS & UART1_CTS to analog nopull - RX could be a wakeup source
Matt Briggs 58:15aa7a785b9f 575 // UART1_TX, UART1_RTS & UART1_CTS to analog nopull - RX could be a wakeup source
Matt Briggs 58:15aa7a785b9f 576 // GPIO_InitStruct.Pin = GPIO_PIN_9 | GPIO_PIN_11 | GPIO_PIN_12;
Matt Briggs 58:15aa7a785b9f 577 GPIO_InitStruct.Pin = GPIO_PIN_9 | GPIO_PIN_12;
Matt Briggs 58:15aa7a785b9f 578 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 579 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 580 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 581
Matt Briggs 58:15aa7a785b9f 582 // I2C_SDA & I2C_SCL to analog nopull
Matt Briggs 58:15aa7a785b9f 583 GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9;
Matt Briggs 58:15aa7a785b9f 584 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 585 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 586 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 587
Matt Briggs 58:15aa7a785b9f 588 // SPI_MOSI, SPI_MISO, SPI_SCK, & SPI_NSS to analog nopull
Matt Briggs 58:15aa7a785b9f 589 GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
Matt Briggs 58:15aa7a785b9f 590 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 591 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 592 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 593
Matt Briggs 58:15aa7a785b9f 594 // iterate through potential wake pins - leave the configured wake pin alone if one is needed
Matt Briggs 58:15aa7a785b9f 595 if ((CCInPinName != WAKE && TamperPinName != WAKE && PairBtnPinName != WAKE)
Matt Briggs 58:15aa7a785b9f 596 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 597 GPIO_InitStruct.Pin = GPIO_PIN_0;
Matt Briggs 58:15aa7a785b9f 598 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 599 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 600 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 601 }
Matt Briggs 58:15aa7a785b9f 602 if ((CCInPinName != GPIO0 && TamperPinName != GPIO0 && PairBtnPinName != GPIO0)
Matt Briggs 58:15aa7a785b9f 603 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 604 GPIO_InitStruct.Pin = GPIO_PIN_4;
Matt Briggs 58:15aa7a785b9f 605 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 606 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 607 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 608 }
Matt Briggs 58:15aa7a785b9f 609 if ((CCInPinName != GPIO1 && TamperPinName != GPIO1 && PairBtnPinName != GPIO1)
Matt Briggs 58:15aa7a785b9f 610 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 611 GPIO_InitStruct.Pin = GPIO_PIN_5;
Matt Briggs 58:15aa7a785b9f 612 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 613 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 614 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 615 }
Matt Briggs 58:15aa7a785b9f 616 if ((CCInPinName != GPIO2 && TamperPinName != GPIO2 && PairBtnPinName != GPIO2)
Matt Briggs 58:15aa7a785b9f 617 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 618 GPIO_InitStruct.Pin = GPIO_PIN_0;
Matt Briggs 58:15aa7a785b9f 619 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 620 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 621 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 622 }
Matt Briggs 74:dc969906f1f7 623 // Changed to always do pull down for now.. Should implement discrete pull on new rev
Matt Briggs 74:dc969906f1f7 624 // if ((CCInPinName != GPIO3 && TamperPinName != GPIO3 && PairBtnPinName != GPIO3)
Matt Briggs 74:dc969906f1f7 625 // || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 74:dc969906f1f7 626 // GPIO_InitStruct.Pin = GPIO_PIN_2;
Matt Briggs 74:dc969906f1f7 627 // GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 74:dc969906f1f7 628 // GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 74:dc969906f1f7 629 // HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
Matt Briggs 74:dc969906f1f7 630 // }
Matt Briggs 74:dc969906f1f7 631
Matt Briggs 74:dc969906f1f7 632 // Try doing nothing so that the GPIO3 is still and active output
Matt Briggs 74:dc969906f1f7 633
Matt Briggs 74:dc969906f1f7 634
Matt Briggs 75:600cb3a9f126 635 // Cannot do this and have serial data
Matt Briggs 75:600cb3a9f126 636 // if ((CCInPinName != UART1_RX && TamperPinName != UART1_RX && PairBtnPinName != UART1_RX)
Matt Briggs 75:600cb3a9f126 637 // || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 75:600cb3a9f126 638 // GPIO_InitStruct.Pin = GPIO_PIN_10;
Matt Briggs 75:600cb3a9f126 639 // GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 75:600cb3a9f126 640 // GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 75:600cb3a9f126 641 // HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 75:600cb3a9f126 642 // }
Matt Briggs 58:15aa7a785b9f 643 if ((CCInPinName != UART_CTS && TamperPinName != UART_CTS && PairBtnPinName != UART_CTS)
Matt Briggs 58:15aa7a785b9f 644 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 645 GPIO_InitStruct.Pin = GPIO_PIN_11;
Matt Briggs 58:15aa7a785b9f 646 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 647 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 648 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 649 }
Matt Briggs 58:15aa7a785b9f 650
Matt Briggs 58:15aa7a785b9f 651 return cmdSuccess;
Matt Briggs 58:15aa7a785b9f 652 }
Matt Briggs 58:15aa7a785b9f 653
Matt Briggs 58:15aa7a785b9f 654 CmdResult BaseboardIO::exitSleep()
Matt Briggs 58:15aa7a785b9f 655 {
Matt Briggs 58:15aa7a785b9f 656 xdot_restore_gpio_state();
Matt Briggs 58:15aa7a785b9f 657 return cmdSuccess;
Matt Briggs 58:15aa7a785b9f 658 }
Matt Briggs 58:15aa7a785b9f 659
Matt Briggs 55:79ab0bbc5008 660 // NvmBBIOObj
Matt Briggs 55:79ab0bbc5008 661 NvmBBIOObj::NvmBBIOObj()
Matt Briggs 55:79ab0bbc5008 662 {
Matt Briggs 55:79ab0bbc5008 663 setDefaults();
Matt Briggs 55:79ab0bbc5008 664 }
Matt Briggs 55:79ab0bbc5008 665 void NvmBBIOObj::setDefaults()
Matt Briggs 55:79ab0bbc5008 666 {
Matt Briggs 55:79ab0bbc5008 667 mBaseboardIOFlag = BASEBOARDIO_FLAG;
Matt Briggs 55:79ab0bbc5008 668 mBaseboardIORev = BASEBOARDIO_REV;
Matt Briggs 55:79ab0bbc5008 669 mSerialNum = 0x0000;
Matt Briggs 55:79ab0bbc5008 670 mBaseboardIOConfig = 0x0000;
Matt Briggs 55:79ab0bbc5008 671 std::memset(mPortExpanderROM0, 0x00, 8);
Matt Briggs 55:79ab0bbc5008 672 std::memset(mPortExpanderROM1, 0x00, 8);
Matt Briggs 55:79ab0bbc5008 673 }
Matt Briggs 55:79ab0bbc5008 674 CmdResult NvmBBIOObj::fromBytes(uint8_t *data, uint8_t size)
Matt Briggs 55:79ab0bbc5008 675 {
Matt Briggs 55:79ab0bbc5008 676 if (size != BASEBOARDIO_NVM_SIZE) {
Matt Briggs 55:79ab0bbc5008 677 return cmdError;
Matt Briggs 55:79ab0bbc5008 678 }
Matt Briggs 55:79ab0bbc5008 679
Matt Briggs 55:79ab0bbc5008 680 mBaseboardIOFlag = *((uint16_t *) (data));
Matt Briggs 55:79ab0bbc5008 681 mBaseboardIORev = *((uint16_t *) (data+2));
Matt Briggs 55:79ab0bbc5008 682 mSerialNum = *((uint32_t *) (data+4));
Matt Briggs 55:79ab0bbc5008 683 mBaseboardIOConfig = *((uint32_t *) (data+6));
Matt Briggs 55:79ab0bbc5008 684
Matt Briggs 55:79ab0bbc5008 685 std::memcpy(&mPortExpanderROM0, data+0x10, 8);
Matt Briggs 55:79ab0bbc5008 686 std::memcpy(&mPortExpanderROM1, data+0x18, 8);
Matt Briggs 55:79ab0bbc5008 687
Matt Briggs 55:79ab0bbc5008 688 return cmdSuccess;
Matt Briggs 55:79ab0bbc5008 689 }
Matt Briggs 55:79ab0bbc5008 690 CmdResult NvmBBIOObj::toBytes(uint8_t *data, uint8_t &size) {
Matt Briggs 55:79ab0bbc5008 691 // TODO check data size
Matt Briggs 55:79ab0bbc5008 692
Matt Briggs 55:79ab0bbc5008 693 *((uint16_t *) (data)) = mBaseboardIOFlag;
Matt Briggs 55:79ab0bbc5008 694 *((uint16_t *) (data+2)) = mBaseboardIORev;
Matt Briggs 55:79ab0bbc5008 695 *((uint32_t *) (data+4)) = mSerialNum;
Matt Briggs 55:79ab0bbc5008 696 *((uint32_t *) (data+6)) = mBaseboardIOConfig;
Matt Briggs 55:79ab0bbc5008 697
Matt Briggs 55:79ab0bbc5008 698 std::memcpy(data+0x10, &mPortExpanderROM0, 8);
Matt Briggs 55:79ab0bbc5008 699 std::memcpy(data+0x18, &mPortExpanderROM1, 8);
Matt Briggs 55:79ab0bbc5008 700
Matt Briggs 55:79ab0bbc5008 701 size = BASEBOARDIO_NVM_SIZE;
Matt Briggs 55:79ab0bbc5008 702
Matt Briggs 55:79ab0bbc5008 703 return cmdSuccess;
Matt Briggs 55:79ab0bbc5008 704 }
Matt Briggs 55:79ab0bbc5008 705 uint16_t NvmBBIOObj::getBaseboardIOFlag()
Matt Briggs 55:79ab0bbc5008 706 {
Matt Briggs 55:79ab0bbc5008 707 return mBaseboardIOFlag;
Matt Briggs 55:79ab0bbc5008 708 }
Matt Briggs 55:79ab0bbc5008 709 bool NvmBBIOObj::validBaseboardIOFlag()
Matt Briggs 55:79ab0bbc5008 710 {
Matt Briggs 55:79ab0bbc5008 711 return mBaseboardIOFlag == BASEBOARDIO_FLAG;
Matt Briggs 55:79ab0bbc5008 712 }
Matt Briggs 55:79ab0bbc5008 713 uint16_t NvmBBIOObj::getBaseboardIORev()
Matt Briggs 55:79ab0bbc5008 714 {
Matt Briggs 55:79ab0bbc5008 715 return mBaseboardIORev;
Matt Briggs 55:79ab0bbc5008 716 }
Matt Briggs 55:79ab0bbc5008 717 bool NvmBBIOObj::validBaseboardIORev()
Matt Briggs 55:79ab0bbc5008 718 {
Matt Briggs 55:79ab0bbc5008 719 return mBaseboardIORev == BASEBOARDIO_REV;
Matt Briggs 55:79ab0bbc5008 720 }
Matt Briggs 55:79ab0bbc5008 721 uint16_t NvmBBIOObj::getSerialNum()
Matt Briggs 55:79ab0bbc5008 722 {
Matt Briggs 55:79ab0bbc5008 723 return mSerialNum;
Matt Briggs 55:79ab0bbc5008 724 }
Matt Briggs 55:79ab0bbc5008 725 void NvmBBIOObj::setSerialNum(uint16_t in)
Matt Briggs 55:79ab0bbc5008 726 {
Matt Briggs 55:79ab0bbc5008 727 mSerialNum = in;
Matt Briggs 55:79ab0bbc5008 728 }
Matt Briggs 55:79ab0bbc5008 729 uint32_t NvmBBIOObj::getBaseboardIOConfig()
Matt Briggs 55:79ab0bbc5008 730 {
Matt Briggs 55:79ab0bbc5008 731 return mBaseboardIOConfig;
Matt Briggs 55:79ab0bbc5008 732 }
Matt Briggs 55:79ab0bbc5008 733 void NvmBBIOObj::setBaseboardIOConfig(uint32_t in)
Matt Briggs 55:79ab0bbc5008 734 {
Matt Briggs 55:79ab0bbc5008 735 mBaseboardIOConfig = in;
Matt Briggs 55:79ab0bbc5008 736 }
Matt Briggs 55:79ab0bbc5008 737 void NvmBBIOObj::getPortExpanderROM0(uint8_t *addr)
Matt Briggs 55:79ab0bbc5008 738 {
Matt Briggs 55:79ab0bbc5008 739 std::memcpy(addr, &mPortExpanderROM0, 8);
Matt Briggs 55:79ab0bbc5008 740 }
Matt Briggs 55:79ab0bbc5008 741 void NvmBBIOObj::setPortExpanderROM0(const uint8_t *addr)
Matt Briggs 55:79ab0bbc5008 742 {
Matt Briggs 55:79ab0bbc5008 743 std::memcpy(&mPortExpanderROM0, addr, 8);
Matt Briggs 55:79ab0bbc5008 744 }
Matt Briggs 55:79ab0bbc5008 745 void NvmBBIOObj::getPortExpanderROM1(uint8_t *addr)
Matt Briggs 55:79ab0bbc5008 746 {
Matt Briggs 55:79ab0bbc5008 747 std::memcpy(addr, &mPortExpanderROM1, 8);
Matt Briggs 55:79ab0bbc5008 748 }
Matt Briggs 55:79ab0bbc5008 749 void NvmBBIOObj::setPortExpanderROM1(const uint8_t *addr)
Matt Briggs 55:79ab0bbc5008 750 {
Matt Briggs 55:79ab0bbc5008 751 std::memcpy(&mPortExpanderROM1, addr, 8);
Matt Briggs 55:79ab0bbc5008 752 }