Matt Briggs / Mbed OS xDotBridge_update_dev_latest

Fork to see if I can get working

Dependencies:   BufferedSerial OneWire WinbondSPIFlash libxDot-dev-mbed5-deprecated

Fork of xDotBridge_update_test20180823 by Matt Briggs

xDotBridge/src/BaseboardIO.cpp@59:485545afc4dc, 2017-03-06 (annotated)

Committer:
Matt Briggs
Date:
Mon Mar 06 09:37:15 2017 -0700
Revision:
59:485545afc4dc
Parent:
58:15aa7a785b9f
Child:
60:5179449a684f
Adding code to allow GPIO3 to be used as LED and added option to allow LrrLed to be used i.e. GPIO0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Matt Briggs 40:2ec4be320961 1 /*
Matt Briggs 40:2ec4be320961 2 * baseboardIO.cpp
Matt Briggs 40:2ec4be320961 3 *
Matt Briggs 40:2ec4be320961 4 * Created on: Jan 25, 2017
Matt Briggs 40:2ec4be320961 5 * Author: mbriggs
Matt Briggs 40:2ec4be320961 6 */
Matt Briggs 40:2ec4be320961 7
Matt Briggs 40:2ec4be320961 8 #include "BaseboardIO.h"
Matt Briggs 41:9ef4c4d77711 9 #include "MTSLog.h"
Matt Briggs 55:79ab0bbc5008 10 #include "dot_util.h" // FIXME just need the reference to dot somehow
Matt Briggs 58:15aa7a785b9f 11 #include "xdot_low_power.h"
Matt Briggs 40:2ec4be320961 12
Matt Briggs 47:a68747642a7a 13 const float COIL_ON_TIME = 0.030; // 30 ms
Matt Briggs 44:ece6330e9b57 14
Matt Briggs 49:18f1354f9e51 15 // Port expander 0 (Currently U7)
Matt Briggs 44:ece6330e9b57 16 const uint8_t pEx0232En = 0x01;
Matt Briggs 44:ece6330e9b57 17 const uint8_t pEx0232TxDis = 0x02;
Matt Briggs 44:ece6330e9b57 18 const uint8_t pEx0Rot1B1 = 0x04;
Matt Briggs 44:ece6330e9b57 19 const uint8_t pEx0Rot1B2 = 0x08;
Matt Briggs 44:ece6330e9b57 20 const uint8_t pEx0Rot1B4 = 0x10;
Matt Briggs 44:ece6330e9b57 21 const uint8_t pEx0Rot1B8 = 0x20;
Matt Briggs 44:ece6330e9b57 22 const uint8_t pEx0Rot2B1 = 0x40;
Matt Briggs 44:ece6330e9b57 23 const uint8_t pEx0Rot2B2 = 0x80;
Matt Briggs 49:18f1354f9e51 24 const uint8_t pEx0OutMask = 0x03; // Only allow bits 0,1 to be changed
Matt Briggs 44:ece6330e9b57 25
Matt Briggs 49:18f1354f9e51 26 // Port expander 1 (Currently U8)
Matt Briggs 44:ece6330e9b57 27 const uint8_t pEx1NoNcSel = 0x01;
Matt Briggs 44:ece6330e9b57 28 const uint8_t pEx1RxTxSel = 0x02;
Matt Briggs 44:ece6330e9b57 29 const uint8_t pEx1WanSel = 0x04;
Matt Briggs 44:ece6330e9b57 30 const uint8_t pEx1SerialEn = 0x08; // Labeled as reserved
Matt Briggs 44:ece6330e9b57 31 const uint8_t pEx1Rot2B8 = 0x10;
Matt Briggs 44:ece6330e9b57 32 const uint8_t pEx1Rot2B4 = 0x20;
Matt Briggs 44:ece6330e9b57 33 const uint8_t pEx1RlyB = 0x40; // This is actually a coil
Matt Briggs 44:ece6330e9b57 34 const uint8_t pEx1RlyA = 0x80; // This is actually a coil
Matt Briggs 49:18f1354f9e51 35 const uint8_t pEx1OutMask = 0xC0; // Only allow bits 6,7 to be changed
Matt Briggs 44:ece6330e9b57 36
Matt Briggs 44:ece6330e9b57 37 /**
Matt Briggs 44:ece6330e9b57 38 * Note for interrupt within uC cannot use two pins with the same numeric suffix (e.g. cannot
Matt Briggs 44:ece6330e9b57 39 * use both PA_0 and PB_0). Note 1, 6, 7, 8, and 13 are used by LoRa radio.
Matt Briggs 44:ece6330e9b57 40 */
Matt Briggs 44:ece6330e9b57 41
Matt Briggs 40:2ec4be320961 42 BaseboardIO::BaseboardIO()
Matt Briggs 58:15aa7a785b9f 43 : mOWMaster(OneWireMasterPinName),
Matt Briggs 58:15aa7a785b9f 44 mCCIn(CCInPinName),
Matt Briggs 58:15aa7a785b9f 45 mTamper(TamperPinName),
Matt Briggs 58:15aa7a785b9f 46 mPairBtn(PairBtnPinName),
Matt Briggs 58:15aa7a785b9f 47 mLed(LedPinName),
Matt Briggs 59:485545afc4dc 48 mLrrLed(LrrLedPinName),
Matt Briggs 58:15aa7a785b9f 49 mSwitchedIOCtrl(SwitchedIOCtrlPinName, 0)
Matt Briggs 40:2ec4be320961 50 {
Matt Briggs 44:ece6330e9b57 51 mPortExpanderVal0 = 0x00;
Matt Briggs 44:ece6330e9b57 52 mPortExpanderVal1 = 0x00;
Matt Briggs 44:ece6330e9b57 53
Matt Briggs 44:ece6330e9b57 54 mPortEx0 = NULL;
Matt Briggs 44:ece6330e9b57 55 mPortEx1 = NULL;
Matt Briggs 40:2ec4be320961 56 }
Matt Briggs 56:40b454c952cc 57 CmdResult BaseboardIO::init(bool overwriteNvm)
Matt Briggs 40:2ec4be320961 58 {
Matt Briggs 56:40b454c952cc 59 bool storedROMsGood = false;
Matt Briggs 56:40b454c952cc 60 uint8_t val;
Matt Briggs 44:ece6330e9b57 61 // Setup port expanders
Matt Briggs 56:40b454c952cc 62 if (readInfoFromNVM() == cmdSuccess && !overwriteNvm) {
Matt Briggs 55:79ab0bbc5008 63 logInfo("Stored ROM0 Addr: %02x:%02x:%02x:%02x:%02x:%02x:%02x%02x found.",
Matt Briggs 55:79ab0bbc5008 64 mNvmObj.mPortExpanderROM0[7],
Matt Briggs 55:79ab0bbc5008 65 mNvmObj.mPortExpanderROM0[6],
Matt Briggs 55:79ab0bbc5008 66 mNvmObj.mPortExpanderROM0[5],
Matt Briggs 55:79ab0bbc5008 67 mNvmObj.mPortExpanderROM0[4],
Matt Briggs 55:79ab0bbc5008 68 mNvmObj.mPortExpanderROM0[3],
Matt Briggs 55:79ab0bbc5008 69 mNvmObj.mPortExpanderROM0[2],
Matt Briggs 55:79ab0bbc5008 70 mNvmObj.mPortExpanderROM0[1],
Matt Briggs 55:79ab0bbc5008 71 mNvmObj.mPortExpanderROM0[0]);
Matt Briggs 55:79ab0bbc5008 72 logInfo("Stored ROM1 Addr: %02x:%02x:%02x:%02x:%02x:%02x:%02x%02x found.",
Matt Briggs 55:79ab0bbc5008 73 mNvmObj.mPortExpanderROM1[7],
Matt Briggs 55:79ab0bbc5008 74 mNvmObj.mPortExpanderROM1[6],
Matt Briggs 55:79ab0bbc5008 75 mNvmObj.mPortExpanderROM1[5],
Matt Briggs 55:79ab0bbc5008 76 mNvmObj.mPortExpanderROM1[4],
Matt Briggs 55:79ab0bbc5008 77 mNvmObj.mPortExpanderROM1[3],
Matt Briggs 55:79ab0bbc5008 78 mNvmObj.mPortExpanderROM1[2],
Matt Briggs 55:79ab0bbc5008 79 mNvmObj.mPortExpanderROM1[1],
Matt Briggs 55:79ab0bbc5008 80 mNvmObj.mPortExpanderROM1[0]);
Matt Briggs 55:79ab0bbc5008 81 logInfo("BaseboardIO parameters successfully loaded from NVM");
Matt Briggs 56:40b454c952cc 82 // Check that the ROM Addresses are correct and valid
Matt Briggs 56:40b454c952cc 83 uint8_t portEx0Ctrl, portEx1Ctrl;
Matt Briggs 56:40b454c952cc 84 mPortEx0 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM0);
Matt Briggs 56:40b454c952cc 85 mPortEx0->registerReadReliable(0x8D, portEx0Ctrl);
Matt Briggs 56:40b454c952cc 86 // Gets 0xFF if it is not the correct address
Matt Briggs 56:40b454c952cc 87 logInfo("PortEx0 Control register reads %02X", portEx0Ctrl);
Matt Briggs 56:40b454c952cc 88
Matt Briggs 56:40b454c952cc 89 mPortEx1 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM1);
Matt Briggs 56:40b454c952cc 90 mPortEx1->registerReadReliable(0x8D, portEx1Ctrl);
Matt Briggs 56:40b454c952cc 91 logInfo("PortEx1 Control register reads %02X", portEx1Ctrl);
Matt Briggs 56:40b454c952cc 92 if ((portEx0Ctrl == 0xFF) || (portEx1Ctrl == 0xFF)) {
Matt Briggs 56:40b454c952cc 93 logError("Stored port expander ROM check failed. Set EEPROM to defaults.");
Matt Briggs 56:40b454c952cc 94 }
Matt Briggs 56:40b454c952cc 95 else {
Matt Briggs 56:40b454c952cc 96 storedROMsGood = true;
Matt Briggs 56:40b454c952cc 97 }
Matt Briggs 44:ece6330e9b57 98 }
Matt Briggs 56:40b454c952cc 99 if (!storedROMsGood)
Matt Briggs 56:40b454c952cc 100 { // EEPROM values not there or corrupt. Should only happen in factory.
Matt Briggs 55:79ab0bbc5008 101 mNvmObj.setDefaults();
Matt Briggs 47:a68747642a7a 102 // Find ROM address and test which one is which. Requires user
Matt Briggs 47:a68747642a7a 103 // switches to be in known state.
Matt Briggs 47:a68747642a7a 104 if (identifyPortExpanders() != cmdSuccess) {
Matt Briggs 44:ece6330e9b57 105 logError("Error identifying port expanders");
Matt Briggs 44:ece6330e9b57 106 return cmdError;
Matt Briggs 44:ece6330e9b57 107 }
Matt Briggs 55:79ab0bbc5008 108 if (writeInfoToNVM() == cmdSuccess) {
Matt Briggs 55:79ab0bbc5008 109 logInfo("Baseboard config saved to NVM");
Matt Briggs 55:79ab0bbc5008 110 }
Matt Briggs 55:79ab0bbc5008 111 else {
Matt Briggs 55:79ab0bbc5008 112 logError("Baseboard config failed to save to NVM");
Matt Briggs 55:79ab0bbc5008 113 }
Matt Briggs 56:40b454c952cc 114 mPortEx0 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM0);
Matt Briggs 56:40b454c952cc 115 mPortEx0->registerReadReliable(0x8D, val);
Matt Briggs 56:40b454c952cc 116 // Gets 0xFF if it is not the correct address
Matt Briggs 56:40b454c952cc 117 logInfo("PortEx0 Control register reads %02X", val);
Matt Briggs 56:40b454c952cc 118 mPortEx1 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM1);
Matt Briggs 56:40b454c952cc 119 mPortEx1->registerReadReliable(0x8D, val);
Matt Briggs 56:40b454c952cc 120 logInfo("PortEx1 Control register reads %02X", val);
Matt Briggs 44:ece6330e9b57 121 }
Matt Briggs 44:ece6330e9b57 122
Matt Briggs 57:bdac7dd17af2 123 if (sampleUserSwitches() != cmdSuccess) {
Matt Briggs 57:bdac7dd17af2 124 logError("Error sampling user switches");
Matt Briggs 57:bdac7dd17af2 125 return cmdError;
Matt Briggs 57:bdac7dd17af2 126 }
Matt Briggs 57:bdac7dd17af2 127
Matt Briggs 44:ece6330e9b57 128 // Put relay in known state
Matt Briggs 47:a68747642a7a 129 if (relayNormal() != cmdSuccess) {
Matt Briggs 47:a68747642a7a 130 logError("Error setting relay during init");
Matt Briggs 47:a68747642a7a 131 return cmdError;
Matt Briggs 47:a68747642a7a 132 }
Matt Briggs 47:a68747642a7a 133
Matt Briggs 44:ece6330e9b57 134 logInfo("Baseboard IO initialization successful");
Matt Briggs 44:ece6330e9b57 135 return cmdSuccess;
Matt Briggs 40:2ec4be320961 136 }
Matt Briggs 40:2ec4be320961 137
Matt Briggs 40:2ec4be320961 138 // Registering for interrupts
Matt Briggs 44:ece6330e9b57 139 void BaseboardIO::regCCInInt(Callback<void()> func)
Matt Briggs 40:2ec4be320961 140 {
Matt Briggs 48:bab9f747d9ed 141 sampleUserSwitches();
Matt Briggs 48:bab9f747d9ed 142 if (isCCNO()) {
Matt Briggs 48:bab9f747d9ed 143 // Pulled high, switched low
Matt Briggs 48:bab9f747d9ed 144 mCCIn.fall(func);
Matt Briggs 48:bab9f747d9ed 145 }
Matt Briggs 48:bab9f747d9ed 146 else {
Matt Briggs 48:bab9f747d9ed 147 mCCIn.rise(func);
Matt Briggs 48:bab9f747d9ed 148 }
Matt Briggs 53:a1563574a980 149 mCCIn.mode(PullNone);
Matt Briggs 49:18f1354f9e51 150 mCCIn.enable_irq();
Matt Briggs 40:2ec4be320961 151 }
Matt Briggs 44:ece6330e9b57 152 void BaseboardIO::regTamperInt(Callback<void()> func)
Matt Briggs 40:2ec4be320961 153 {
Matt Briggs 44:ece6330e9b57 154 // Pulled high, switched low
Matt Briggs 53:a1563574a980 155 mTamper.mode(PullNone);
Matt Briggs 49:18f1354f9e51 156 mTamper.rise(func);
Matt Briggs 44:ece6330e9b57 157 mTamper.fall(func);
Matt Briggs 49:18f1354f9e51 158 mTamper.enable_irq();
Matt Briggs 40:2ec4be320961 159 }
Matt Briggs 44:ece6330e9b57 160 void BaseboardIO::regPairBtnInt(Callback<void()> func)
Matt Briggs 40:2ec4be320961 161 {
Matt Briggs 44:ece6330e9b57 162 // Pulled low, switched high
Matt Briggs 58:15aa7a785b9f 163 mPairBtn.mode(PullNone);
Matt Briggs 44:ece6330e9b57 164 mPairBtn.rise(func);
Matt Briggs 49:18f1354f9e51 165 mPairBtn.enable_irq();
Matt Briggs 40:2ec4be320961 166 }
Matt Briggs 40:2ec4be320961 167
Matt Briggs 40:2ec4be320961 168 // Input
Matt Briggs 40:2ec4be320961 169 CmdResult BaseboardIO::sampleUserSwitches()
Matt Briggs 40:2ec4be320961 170 {
Matt Briggs 48:bab9f747d9ed 171 if ((mPortEx0 == NULL) || (mPortEx1 == NULL))
Matt Briggs 48:bab9f747d9ed 172 return cmdError;
Matt Briggs 44:ece6330e9b57 173 // Sample port expanders
Matt Briggs 49:18f1354f9e51 174 enableSwitchedIO();
Matt Briggs 49:18f1354f9e51 175 wait(0.001); // Wait 1 ms
Matt Briggs 53:a1563574a980 176 if (mPortEx0->pioLogicReliableRead(mPortExpanderVal0) != cmdSuccess) {
Matt Briggs 49:18f1354f9e51 177 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 178 logError("Error reading port expander 0.");
Matt Briggs 44:ece6330e9b57 179 return cmdError;
Matt Briggs 44:ece6330e9b57 180 }
Matt Briggs 53:a1563574a980 181 if (mPortEx1->pioLogicReliableRead(mPortExpanderVal1) != cmdSuccess) {
Matt Briggs 49:18f1354f9e51 182 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 183 logError("Error reading port expander 1.");
Matt Briggs 44:ece6330e9b57 184 return cmdError;
Matt Briggs 44:ece6330e9b57 185 }
Matt Briggs 49:18f1354f9e51 186 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 187 return cmdSuccess;
Matt Briggs 40:2ec4be320961 188 }
Matt Briggs 57:bdac7dd17af2 189 bool BaseboardIO::isCCInAlert()
Matt Briggs 57:bdac7dd17af2 190 {
Matt Briggs 57:bdac7dd17af2 191 if (isCCNO()) { // If NO then the CCIn should float high if not in alert state
Matt Briggs 57:bdac7dd17af2 192 return mCCIn == 0;
Matt Briggs 57:bdac7dd17af2 193 }
Matt Briggs 57:bdac7dd17af2 194 else { // If NC then the CCIN should be held low if not in alert state
Matt Briggs 57:bdac7dd17af2 195 return mCCIn == 1;
Matt Briggs 57:bdac7dd17af2 196 }
Matt Briggs 57:bdac7dd17af2 197 }
Matt Briggs 40:2ec4be320961 198 bool BaseboardIO::isPairBtn()
Matt Briggs 40:2ec4be320961 199 {
Matt Briggs 44:ece6330e9b57 200 // Depressed button is high
Matt Briggs 44:ece6330e9b57 201 return mPairBtn.read() == 1;
Matt Briggs 40:2ec4be320961 202 }
Matt Briggs 48:bab9f747d9ed 203 bool BaseboardIO::isCCNO()
Matt Briggs 40:2ec4be320961 204 {
Matt Briggs 44:ece6330e9b57 205 // When DIP switch is not closed (i.e. value reads high) assume NO
Matt Briggs 49:18f1354f9e51 206 return (mPortExpanderVal1 & pEx1NoNcSel) != 0; // Open NO, closed NC
Matt Briggs 40:2ec4be320961 207 }
Matt Briggs 40:2ec4be320961 208 bool BaseboardIO::isRx()
Matt Briggs 40:2ec4be320961 209 {
Matt Briggs 44:ece6330e9b57 210 // When DIP switch is not closed (i.e. value reads high) assume RX
Matt Briggs 44:ece6330e9b57 211 return (mPortExpanderVal1 & pEx1RxTxSel) != 0;
Matt Briggs 40:2ec4be320961 212 }
Matt Briggs 40:2ec4be320961 213 bool BaseboardIO::isLoRaWANMode()
Matt Briggs 40:2ec4be320961 214 {
Matt Briggs 44:ece6330e9b57 215 // When DIP switch is not closed (i.e. value reads high) assume P2P not WAN
Matt Briggs 44:ece6330e9b57 216 return (mPortExpanderVal1 & pEx1WanSel) == 0;
Matt Briggs 40:2ec4be320961 217 }
Matt Briggs 50:e89647e77fd5 218 bool BaseboardIO::isSerialEnabled()
Matt Briggs 50:e89647e77fd5 219 {
Matt Briggs 50:e89647e77fd5 220 // When DIP switch is not closed (i.e. value reads high) assume not in serial mode
Matt Briggs 50:e89647e77fd5 221 return (mPortExpanderVal1 & pEx1SerialEn) == 0;
Matt Briggs 50:e89647e77fd5 222 }
Matt Briggs 40:2ec4be320961 223 uint8_t BaseboardIO::rotarySwitch1()
Matt Briggs 40:2ec4be320961 224 {
Matt Briggs 44:ece6330e9b57 225 // If a bit of a nibble is asserted then the port expander line is switched low.
Matt Briggs 44:ece6330e9b57 226 uint8_t val = 0;
Matt Briggs 44:ece6330e9b57 227 if ((mPortExpanderVal0 & pEx0Rot1B8) == 0)
Matt Briggs 44:ece6330e9b57 228 val |= 0x08;
Matt Briggs 44:ece6330e9b57 229 if ((mPortExpanderVal0 & pEx0Rot1B4) == 0)
Matt Briggs 44:ece6330e9b57 230 val |= 0x04;
Matt Briggs 44:ece6330e9b57 231 if ((mPortExpanderVal0 & pEx0Rot1B2) == 0)
Matt Briggs 44:ece6330e9b57 232 val |= 0x02;
Matt Briggs 44:ece6330e9b57 233 if ((mPortExpanderVal0 & pEx0Rot1B1) == 0)
Matt Briggs 44:ece6330e9b57 234 val |= 0x01;
Matt Briggs 44:ece6330e9b57 235 return val;
Matt Briggs 40:2ec4be320961 236 }
Matt Briggs 40:2ec4be320961 237 uint8_t BaseboardIO::rotarySwitch2()
Matt Briggs 40:2ec4be320961 238 {
Matt Briggs 44:ece6330e9b57 239 // If a bit of a nibble is asserted then the port expander line is switched low.
Matt Briggs 44:ece6330e9b57 240 uint8_t val = 0;
Matt Briggs 44:ece6330e9b57 241 if ((mPortExpanderVal1 & pEx1Rot2B8) == 0)
Matt Briggs 44:ece6330e9b57 242 val |= 0x08;
Matt Briggs 44:ece6330e9b57 243 if ((mPortExpanderVal1 & pEx1Rot2B4) == 0)
Matt Briggs 44:ece6330e9b57 244 val |= 0x04;
Matt Briggs 44:ece6330e9b57 245 if ((mPortExpanderVal0 & pEx0Rot2B2) == 0)
Matt Briggs 44:ece6330e9b57 246 val |= 0x02;
Matt Briggs 44:ece6330e9b57 247 if ((mPortExpanderVal0 & pEx0Rot2B1) == 0)
Matt Briggs 44:ece6330e9b57 248 val |= 0x01;
Matt Briggs 44:ece6330e9b57 249 return val;
Matt Briggs 40:2ec4be320961 250 }
Matt Briggs 40:2ec4be320961 251
Matt Briggs 40:2ec4be320961 252 // Output
Matt Briggs 40:2ec4be320961 253 CmdResult BaseboardIO::ledOn()
Matt Briggs 40:2ec4be320961 254 {
Matt Briggs 44:ece6330e9b57 255 mLed = 1;
Matt Briggs 59:485545afc4dc 256 #if ALSO_USE_LRR_LED
Matt Briggs 59:485545afc4dc 257 mLrrLed = 1;
Matt Briggs 59:485545afc4dc 258 #endif
Matt Briggs 44:ece6330e9b57 259 return cmdSuccess;
Matt Briggs 40:2ec4be320961 260 }
Matt Briggs 40:2ec4be320961 261 CmdResult BaseboardIO::ledOff()
Matt Briggs 40:2ec4be320961 262 {
Matt Briggs 44:ece6330e9b57 263 mLed = 0;
Matt Briggs 59:485545afc4dc 264 #if ALSO_USE_LRR_LED
Matt Briggs 59:485545afc4dc 265 mLrrLed = 0;
Matt Briggs 59:485545afc4dc 266 #endif
Matt Briggs 44:ece6330e9b57 267 return cmdSuccess;
Matt Briggs 40:2ec4be320961 268 }
Matt Briggs 40:2ec4be320961 269 CmdResult BaseboardIO::relayAlert()
Matt Briggs 40:2ec4be320961 270 {
Matt Briggs 48:bab9f747d9ed 271 if (isCCNO()) { // Normally Open
Matt Briggs 44:ece6330e9b57 272 return closeRelay();
Matt Briggs 44:ece6330e9b57 273 }
Matt Briggs 44:ece6330e9b57 274 else { // Normally Close
Matt Briggs 44:ece6330e9b57 275 return openRelay();
Matt Briggs 44:ece6330e9b57 276 }
Matt Briggs 40:2ec4be320961 277 }
Matt Briggs 40:2ec4be320961 278 CmdResult BaseboardIO::relayNormal()
Matt Briggs 40:2ec4be320961 279 {
Matt Briggs 48:bab9f747d9ed 280 if (isCCNO()) { // Normally Open
Matt Briggs 44:ece6330e9b57 281 return openRelay();
Matt Briggs 44:ece6330e9b57 282 }
Matt Briggs 44:ece6330e9b57 283 else { // Normally Close
Matt Briggs 44:ece6330e9b57 284 return closeRelay();
Matt Briggs 44:ece6330e9b57 285 }
Matt Briggs 40:2ec4be320961 286 }
Matt Briggs 40:2ec4be320961 287
Matt Briggs 40:2ec4be320961 288 // Future
Matt Briggs 40:2ec4be320961 289 CmdResult BaseboardIO::serialRx(bool enable)
Matt Briggs 40:2ec4be320961 290 {
Matt Briggs 44:ece6330e9b57 291 uint8_t val;
Matt Briggs 49:18f1354f9e51 292 if (mPortEx0 == NULL) {
Matt Briggs 49:18f1354f9e51 293 logError("Error enabling 232. Port expanders not initialized.");
Matt Briggs 49:18f1354f9e51 294 return cmdError;
Matt Briggs 49:18f1354f9e51 295 }
Matt Briggs 53:a1563574a980 296 mPortEx0->pioLogicReliableRead(val);
Matt Briggs 44:ece6330e9b57 297
Matt Briggs 44:ece6330e9b57 298 // Active low from port expander -> pmos -> 232 (active chip EN)
Matt Briggs 44:ece6330e9b57 299 if (enable) {
Matt Briggs 44:ece6330e9b57 300 val &= ~pEx0232En;
Matt Briggs 44:ece6330e9b57 301 }
Matt Briggs 44:ece6330e9b57 302 else {
Matt Briggs 44:ece6330e9b57 303 val |= pEx0232En;
Matt Briggs 44:ece6330e9b57 304 }
Matt Briggs 44:ece6330e9b57 305
Matt Briggs 53:a1563574a980 306 if (mPortEx0->pioLogicReliableWrite(val | ~pEx0OutMask) != cmdSuccess) {
Matt Briggs 44:ece6330e9b57 307 logError("Error enabling 232");
Matt Briggs 44:ece6330e9b57 308 return cmdError;
Matt Briggs 44:ece6330e9b57 309 }
Matt Briggs 44:ece6330e9b57 310 return cmdSuccess;
Matt Briggs 44:ece6330e9b57 311 }
Matt Briggs 44:ece6330e9b57 312 CmdResult BaseboardIO::serialTx(bool enable)
Matt Briggs 44:ece6330e9b57 313 {
Matt Briggs 44:ece6330e9b57 314 uint8_t val;
Matt Briggs 49:18f1354f9e51 315 if (mPortEx0 == NULL) {
Matt Briggs 49:18f1354f9e51 316 logError("Error enabling 232 TX. Port expanders not initialized.");
Matt Briggs 49:18f1354f9e51 317 return cmdError;
Matt Briggs 49:18f1354f9e51 318 }
Matt Briggs 53:a1563574a980 319 mPortEx0->pioLogicReliableRead(val);
Matt Briggs 44:ece6330e9b57 320
Matt Briggs 44:ece6330e9b57 321 // Active high tx disable therefore active low tx enable (note chip must also be enabled for TX)
Matt Briggs 44:ece6330e9b57 322 if (enable) {
Matt Briggs 44:ece6330e9b57 323 val &= ~pEx0232TxDis;
Matt Briggs 44:ece6330e9b57 324 }
Matt Briggs 44:ece6330e9b57 325 else {
Matt Briggs 44:ece6330e9b57 326 val |= pEx0232TxDis;
Matt Briggs 44:ece6330e9b57 327 }
Matt Briggs 44:ece6330e9b57 328
Matt Briggs 53:a1563574a980 329 if (mPortEx0->pioLogicReliableWrite(val | ~pEx0OutMask) != cmdSuccess) {
Matt Briggs 44:ece6330e9b57 330 logError("Error enabling 232 TX");
Matt Briggs 44:ece6330e9b57 331 return cmdError;
Matt Briggs 44:ece6330e9b57 332 }
Matt Briggs 44:ece6330e9b57 333 return cmdSuccess;
Matt Briggs 44:ece6330e9b57 334 }
Matt Briggs 44:ece6330e9b57 335
Matt Briggs 44:ece6330e9b57 336 // private
Matt Briggs 44:ece6330e9b57 337 CmdResult BaseboardIO::readInfoFromNVM()
Matt Briggs 44:ece6330e9b57 338 {
Matt Briggs 55:79ab0bbc5008 339 bool nvmReadResult;
Matt Briggs 55:79ab0bbc5008 340 uint8_t *data = new uint8_t [BASEBOARDIO_NVM_SIZE];
Matt Briggs 55:79ab0bbc5008 341
Matt Briggs 55:79ab0bbc5008 342 nvmReadResult = dot->nvmRead(BASEBOARDIO_NVM_START_ADDR, data, BASEBOARDIO_NVM_SIZE);
Matt Briggs 55:79ab0bbc5008 343 if (!nvmReadResult) {
Matt Briggs 55:79ab0bbc5008 344 delete [] data;
Matt Briggs 55:79ab0bbc5008 345 return cmdError;
Matt Briggs 55:79ab0bbc5008 346 }
Matt Briggs 55:79ab0bbc5008 347 mNvmObj.fromBytes(data, BASEBOARDIO_NVM_SIZE);
Matt Briggs 55:79ab0bbc5008 348 delete [] data;
Matt Briggs 55:79ab0bbc5008 349 if (!mNvmObj.validBaseboardIOFlag()) {
Matt Briggs 55:79ab0bbc5008 350 logWarning("Invalid BaseboardIO Flag. Using default values.");
Matt Briggs 55:79ab0bbc5008 351 return cmdError;
Matt Briggs 55:79ab0bbc5008 352 }
Matt Briggs 55:79ab0bbc5008 353 else if (!mNvmObj.validBaseboardIORev()) {
Matt Briggs 55:79ab0bbc5008 354 logWarning("Invalid BaseboardIO Rev. Using default values.");
Matt Briggs 55:79ab0bbc5008 355 return cmdError;
Matt Briggs 55:79ab0bbc5008 356 }
Matt Briggs 55:79ab0bbc5008 357 else {
Matt Briggs 55:79ab0bbc5008 358 return cmdSuccess;
Matt Briggs 55:79ab0bbc5008 359 }
Matt Briggs 40:2ec4be320961 360 }
Matt Briggs 44:ece6330e9b57 361 CmdResult BaseboardIO::writeInfoToNVM()
Matt Briggs 40:2ec4be320961 362 {
Matt Briggs 55:79ab0bbc5008 363 uint8_t *data = new uint8_t [BASEBOARDIO_NVM_SIZE];
Matt Briggs 55:79ab0bbc5008 364 uint8_t size = BASEBOARDIO_NVM_SIZE;
Matt Briggs 55:79ab0bbc5008 365 mNvmObj.toBytes(data, size);
Matt Briggs 55:79ab0bbc5008 366 dot->nvmWrite(BASEBOARDIO_NVM_START_ADDR, data, BASEBOARDIO_NVM_SIZE);
Matt Briggs 55:79ab0bbc5008 367
Matt Briggs 55:79ab0bbc5008 368 delete [] data;
Matt Briggs 55:79ab0bbc5008 369 return cmdSuccess;
Matt Briggs 40:2ec4be320961 370 }
Matt Briggs 44:ece6330e9b57 371 CmdResult BaseboardIO::identifyPortExpanders()
Matt Briggs 44:ece6330e9b57 372 {
Matt Briggs 44:ece6330e9b57 373 uint8_t addr[8];
Matt Briggs 44:ece6330e9b57 374 uint8_t result;
Matt Briggs 49:18f1354f9e51 375 int i;
Matt Briggs 40:2ec4be320961 376
Matt Briggs 44:ece6330e9b57 377 // Search Bus
Matt Briggs 44:ece6330e9b57 378 logInfo("Starting OneWire Search");
Matt Briggs 49:18f1354f9e51 379 enableSwitchedIO();
Matt Briggs 49:18f1354f9e51 380 for (int j=0;j<10;j++) { // Try 5 times
Matt Briggs 49:18f1354f9e51 381 i=0;
Matt Briggs 49:18f1354f9e51 382 mOWMaster.reset();
Matt Briggs 49:18f1354f9e51 383 mOWMaster.reset_search();
Matt Briggs 49:18f1354f9e51 384 wait(1.0);
Matt Briggs 49:18f1354f9e51 385 while (true) {
Matt Briggs 49:18f1354f9e51 386 // TODO maybe change to family based search
Matt Briggs 49:18f1354f9e51 387 result = mOWMaster.search(addr);
Matt Briggs 49:18f1354f9e51 388 if (result != 1) {
Matt Briggs 49:18f1354f9e51 389 break;
Matt Briggs 49:18f1354f9e51 390 }
Matt Briggs 49:18f1354f9e51 391 logInfo("ROM Addr: %02x:%02x:%02x:%02x:%02x:%02x:%02x%02x found.",
Matt Briggs 49:18f1354f9e51 392 addr[7],addr[6],addr[5],addr[4],addr[3],addr[2],addr[1],addr[0]);
Matt Briggs 49:18f1354f9e51 393 if (i == 0) {
Matt Briggs 55:79ab0bbc5008 394 std::memcpy(mNvmObj.mPortExpanderROM0, addr, sizeof(mNvmObj.mPortExpanderROM0));
Matt Briggs 49:18f1354f9e51 395 }
Matt Briggs 49:18f1354f9e51 396 else if (i == 1) {
Matt Briggs 55:79ab0bbc5008 397 std::memcpy(mNvmObj.mPortExpanderROM1, addr, sizeof(mNvmObj.mPortExpanderROM1));
Matt Briggs 49:18f1354f9e51 398 }
Matt Briggs 49:18f1354f9e51 399 i++;
Matt Briggs 49:18f1354f9e51 400 }
Matt Briggs 49:18f1354f9e51 401 // TODO maybe only allow a reasonable number of Port Expanders
Matt Briggs 49:18f1354f9e51 402 if (i >=2) {
Matt Briggs 44:ece6330e9b57 403 break;
Matt Briggs 44:ece6330e9b57 404 }
Matt Briggs 44:ece6330e9b57 405 }
Matt Briggs 44:ece6330e9b57 406
Matt Briggs 44:ece6330e9b57 407 logInfo("Finished OneWire Search");
Matt Briggs 44:ece6330e9b57 408 if (i != 2) {
Matt Briggs 48:bab9f747d9ed 409 logError("Incorrect Number of OneWire devices (Got %d. Expected 2) OneWire port expanders found.", i);
Matt Briggs 44:ece6330e9b57 410 return cmdError;
Matt Briggs 44:ece6330e9b57 411 }
Matt Briggs 44:ece6330e9b57 412
Matt Briggs 49:18f1354f9e51 413 // All rotary switches should be at 0. DIPS should be asserted.
Matt Briggs 44:ece6330e9b57 414 // If switches are set in factory default mode then port expander 1 should read 0xFF and
Matt Briggs 44:ece6330e9b57 415 // port expander 2 should read 0xF0.
Matt Briggs 40:2ec4be320961 416
Matt Briggs 55:79ab0bbc5008 417 mPortEx0 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM0);
Matt Briggs 55:79ab0bbc5008 418 mPortEx1 = new DS2408(&mOWMaster, mNvmObj.mPortExpanderROM1);
Matt Briggs 44:ece6330e9b57 419
Matt Briggs 49:18f1354f9e51 420
Matt Briggs 49:18f1354f9e51 421 enableSwitchedIO();
Matt Briggs 53:a1563574a980 422 if (mPortEx0->pioLogicReliableRead(mPortExpanderVal0) != cmdSuccess) {
Matt Briggs 44:ece6330e9b57 423 logError("Error during port expander ID. Read failed.");
Matt Briggs 49:18f1354f9e51 424 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 425 delete mPortEx0;
Matt Briggs 44:ece6330e9b57 426 delete mPortEx1;
Matt Briggs 44:ece6330e9b57 427 return cmdError;
Matt Briggs 44:ece6330e9b57 428 }
Matt Briggs 53:a1563574a980 429 if (mPortEx1->pioLogicReliableRead(mPortExpanderVal1) != cmdSuccess) {
Matt Briggs 44:ece6330e9b57 430 logError("Error during port expander ID. Read failed.");
Matt Briggs 49:18f1354f9e51 431 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 432 delete mPortEx0;
Matt Briggs 44:ece6330e9b57 433 delete mPortEx1;
Matt Briggs 44:ece6330e9b57 434 return cmdError;
Matt Briggs 44:ece6330e9b57 435 }
Matt Briggs 44:ece6330e9b57 436
Matt Briggs 49:18f1354f9e51 437 disableSwitchedIO();
Matt Briggs 44:ece6330e9b57 438 if ((mPortExpanderVal0 == 0xFF) and (mPortExpanderVal1 == 0xF0)) { // Luckily got it right
Matt Briggs 44:ece6330e9b57 439 logInfo("ROMS Swap Not Needed.");
Matt Briggs 44:ece6330e9b57 440 }
Matt Briggs 44:ece6330e9b57 441 else if ((mPortExpanderVal0 == 0xF0) and (mPortExpanderVal1 == 0xFF)) { // Just need to swap
Matt Briggs 55:79ab0bbc5008 442 std::memcpy(addr, mNvmObj.mPortExpanderROM0, sizeof(addr)); // Store Orig ROM0 -> addr
Matt Briggs 55:79ab0bbc5008 443 std::memcpy(mNvmObj.mPortExpanderROM0, mNvmObj.mPortExpanderROM1, sizeof(mNvmObj.mPortExpanderROM0)); // Store Orig ROM1 -> ROM0
Matt Briggs 55:79ab0bbc5008 444 std::memcpy(mNvmObj.mPortExpanderROM1, addr, sizeof(mNvmObj.mPortExpanderROM1)); // Store Orig ROM0 (addr) -> ROM1
Matt Briggs 44:ece6330e9b57 445 logInfo("Swapped ROMS.");
Matt Briggs 44:ece6330e9b57 446 }
Matt Briggs 44:ece6330e9b57 447 else {
Matt Briggs 49:18f1354f9e51 448 logError("Error during port expander ID. Port expanders not in "
Matt Briggs 55:79ab0bbc5008 449 "expected states (0xFF and 0xF0). Check user switches. Got %02X and %02X",
Matt Briggs 49:18f1354f9e51 450 mPortExpanderVal0, mPortExpanderVal1);
Matt Briggs 44:ece6330e9b57 451 delete mPortEx0;
Matt Briggs 44:ece6330e9b57 452 delete mPortEx1;
Matt Briggs 44:ece6330e9b57 453 return cmdError;
Matt Briggs 44:ece6330e9b57 454 }
Matt Briggs 44:ece6330e9b57 455
Matt Briggs 44:ece6330e9b57 456 // Cleanup
Matt Briggs 44:ece6330e9b57 457 delete mPortEx0;
Matt Briggs 44:ece6330e9b57 458 delete mPortEx1;
Matt Briggs 44:ece6330e9b57 459
Matt Briggs 44:ece6330e9b57 460 return cmdSuccess;
Matt Briggs 40:2ec4be320961 461 }
Matt Briggs 49:18f1354f9e51 462 CmdResult BaseboardIO::openRelay() {
Matt Briggs 44:ece6330e9b57 463 uint8_t val;
Matt Briggs 53:a1563574a980 464 mPortEx1->pioLogicReliableRead(val);
Matt Briggs 44:ece6330e9b57 465
Matt Briggs 49:18f1354f9e51 466 val |= pEx1RlyA; // Make sure Relay A is off
Matt Briggs 49:18f1354f9e51 467 val &= ~pEx1RlyB; // Turn on Relay B
Matt Briggs 44:ece6330e9b57 468
Matt Briggs 53:a1563574a980 469 if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) {
Matt Briggs 49:18f1354f9e51 470 val |= pEx1RlyA; // Turn Relay A off
Matt Briggs 49:18f1354f9e51 471 val |= pEx1RlyB; // Turn Relay B off
Matt Briggs 53:a1563574a980 472 mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask); // Write a non assert value just to try to overcome an error
Matt Briggs 44:ece6330e9b57 473 logError ("Error turning on coil. Turning both coils off.");
Matt Briggs 44:ece6330e9b57 474 return cmdError;
Matt Briggs 44:ece6330e9b57 475 }
Matt Briggs 44:ece6330e9b57 476
Matt Briggs 47:a68747642a7a 477 wait(COIL_ON_TIME);
Matt Briggs 44:ece6330e9b57 478
Matt Briggs 49:18f1354f9e51 479 val |= pEx1RlyA; // Turn Relay A off
Matt Briggs 49:18f1354f9e51 480 val |= pEx1RlyB; // Turn Relay B off
Matt Briggs 44:ece6330e9b57 481
Matt Briggs 53:a1563574a980 482 if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) {
Matt Briggs 53:a1563574a980 483 mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask);
Matt Briggs 44:ece6330e9b57 484 logError ("Error turning off coils. Trying again.");
Matt Briggs 44:ece6330e9b57 485 return cmdError;
Matt Briggs 44:ece6330e9b57 486 }
Matt Briggs 44:ece6330e9b57 487
Matt Briggs 44:ece6330e9b57 488 return cmdSuccess;
Matt Briggs 40:2ec4be320961 489 }
Matt Briggs 49:18f1354f9e51 490 CmdResult BaseboardIO::closeRelay() {
Matt Briggs 44:ece6330e9b57 491 uint8_t val;
Matt Briggs 53:a1563574a980 492 mPortEx1->pioLogicReliableRead(val);
Matt Briggs 44:ece6330e9b57 493
Matt Briggs 49:18f1354f9e51 494 val &= ~pEx1RlyA; // Turn on Relay A
Matt Briggs 49:18f1354f9e51 495 val |= pEx1RlyB; // Make sure Relay B is off
Matt Briggs 44:ece6330e9b57 496
Matt Briggs 53:a1563574a980 497 if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) {
Matt Briggs 49:18f1354f9e51 498 val |= pEx1RlyA; // Turn Relay A off
Matt Briggs 49:18f1354f9e51 499 val |= pEx1RlyB; // Turn Relay B off
Matt Briggs 53:a1563574a980 500 mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask); // Write a non assert value just to try to overcome an error
Matt Briggs 44:ece6330e9b57 501 logError ("Error turning on coil. Turning both coils off.");
Matt Briggs 44:ece6330e9b57 502 return cmdError;
Matt Briggs 44:ece6330e9b57 503 }
Matt Briggs 44:ece6330e9b57 504
Matt Briggs 47:a68747642a7a 505 wait(COIL_ON_TIME);
Matt Briggs 44:ece6330e9b57 506
Matt Briggs 49:18f1354f9e51 507 val |= pEx1RlyA; // Turn Relay A off
Matt Briggs 49:18f1354f9e51 508 val |= pEx1RlyB; // Turn Relay B off
Matt Briggs 44:ece6330e9b57 509
Matt Briggs 53:a1563574a980 510 if (mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask) != cmdSuccess) {
Matt Briggs 53:a1563574a980 511 mPortEx1->pioLogicReliableWrite(val | ~pEx1OutMask);
Matt Briggs 44:ece6330e9b57 512 logError ("Error turning off coils. Trying again.");
Matt Briggs 44:ece6330e9b57 513 return cmdError;
Matt Briggs 44:ece6330e9b57 514 }
Matt Briggs 44:ece6330e9b57 515
Matt Briggs 44:ece6330e9b57 516 return cmdSuccess;
Matt Briggs 40:2ec4be320961 517 }
Matt Briggs 55:79ab0bbc5008 518
Matt Briggs 58:15aa7a785b9f 519 CmdResult BaseboardIO::prepareSleep()
Matt Briggs 58:15aa7a785b9f 520 {
Matt Briggs 58:15aa7a785b9f 521 // Save current GPUIO state
Matt Briggs 58:15aa7a785b9f 522 xdot_save_gpio_state();
Matt Briggs 58:15aa7a785b9f 523
Matt Briggs 58:15aa7a785b9f 524 // Configure all IO expect for pins for interrupt in lowest mode possible
Matt Briggs 58:15aa7a785b9f 525 // GPIO Ports Clock Enable
Matt Briggs 58:15aa7a785b9f 526 __GPIOA_CLK_ENABLE();
Matt Briggs 58:15aa7a785b9f 527 __GPIOB_CLK_ENABLE();
Matt Briggs 58:15aa7a785b9f 528 __GPIOC_CLK_ENABLE();
Matt Briggs 58:15aa7a785b9f 529 __GPIOH_CLK_ENABLE();
Matt Briggs 58:15aa7a785b9f 530
Matt Briggs 58:15aa7a785b9f 531 GPIO_InitTypeDef GPIO_InitStruct;
Matt Briggs 58:15aa7a785b9f 532
Matt Briggs 58:15aa7a785b9f 533 // UART1_TX, UART1_RTS & UART1_CTS to analog nopull - RX could be a wakeup source
Matt Briggs 58:15aa7a785b9f 534 // UART1_TX, UART1_RTS & UART1_CTS to analog nopull - RX could be a wakeup source
Matt Briggs 58:15aa7a785b9f 535 // GPIO_InitStruct.Pin = GPIO_PIN_9 | GPIO_PIN_11 | GPIO_PIN_12;
Matt Briggs 58:15aa7a785b9f 536 GPIO_InitStruct.Pin = GPIO_PIN_9 | GPIO_PIN_12;
Matt Briggs 58:15aa7a785b9f 537 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 538 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 539 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 540
Matt Briggs 58:15aa7a785b9f 541 // I2C_SDA & I2C_SCL to analog nopull
Matt Briggs 58:15aa7a785b9f 542 GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9;
Matt Briggs 58:15aa7a785b9f 543 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 544 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 545 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 546
Matt Briggs 58:15aa7a785b9f 547 // SPI_MOSI, SPI_MISO, SPI_SCK, & SPI_NSS to analog nopull
Matt Briggs 58:15aa7a785b9f 548 GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
Matt Briggs 58:15aa7a785b9f 549 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 550 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 551 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 552
Matt Briggs 58:15aa7a785b9f 553 // iterate through potential wake pins - leave the configured wake pin alone if one is needed
Matt Briggs 58:15aa7a785b9f 554 if ((CCInPinName != WAKE && TamperPinName != WAKE && PairBtnPinName != WAKE)
Matt Briggs 58:15aa7a785b9f 555 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 556 GPIO_InitStruct.Pin = GPIO_PIN_0;
Matt Briggs 58:15aa7a785b9f 557 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 558 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 559 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 560 }
Matt Briggs 58:15aa7a785b9f 561 if ((CCInPinName != GPIO0 && TamperPinName != GPIO0 && PairBtnPinName != GPIO0)
Matt Briggs 58:15aa7a785b9f 562 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 563 GPIO_InitStruct.Pin = GPIO_PIN_4;
Matt Briggs 58:15aa7a785b9f 564 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 565 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 566 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 567 }
Matt Briggs 58:15aa7a785b9f 568 if ((CCInPinName != GPIO1 && TamperPinName != GPIO1 && PairBtnPinName != GPIO1)
Matt Briggs 58:15aa7a785b9f 569 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 570 GPIO_InitStruct.Pin = GPIO_PIN_5;
Matt Briggs 58:15aa7a785b9f 571 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 572 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 573 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 574 }
Matt Briggs 58:15aa7a785b9f 575 if ((CCInPinName != GPIO2 && TamperPinName != GPIO2 && PairBtnPinName != GPIO2)
Matt Briggs 58:15aa7a785b9f 576 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 577 GPIO_InitStruct.Pin = GPIO_PIN_0;
Matt Briggs 58:15aa7a785b9f 578 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 579 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 580 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 581 }
Matt Briggs 58:15aa7a785b9f 582 if ((CCInPinName != GPIO3 && TamperPinName != GPIO3 && PairBtnPinName != GPIO3)
Matt Briggs 58:15aa7a785b9f 583 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 584 GPIO_InitStruct.Pin = GPIO_PIN_2;
Matt Briggs 58:15aa7a785b9f 585 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 586 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 587 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 588 }
Matt Briggs 58:15aa7a785b9f 589 if ((CCInPinName != UART1_RX && TamperPinName != UART1_RX && PairBtnPinName != UART1_RX)
Matt Briggs 58:15aa7a785b9f 590 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 591 GPIO_InitStruct.Pin = GPIO_PIN_10;
Matt Briggs 58:15aa7a785b9f 592 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 593 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 594 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 595 }
Matt Briggs 58:15aa7a785b9f 596 if ((CCInPinName != UART_CTS && TamperPinName != UART_CTS && PairBtnPinName != UART_CTS)
Matt Briggs 58:15aa7a785b9f 597 || dot->getWakeMode() == mDot::RTC_ALARM) {
Matt Briggs 58:15aa7a785b9f 598 GPIO_InitStruct.Pin = GPIO_PIN_11;
Matt Briggs 58:15aa7a785b9f 599 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
Matt Briggs 58:15aa7a785b9f 600 GPIO_InitStruct.Pull = GPIO_NOPULL;
Matt Briggs 58:15aa7a785b9f 601 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
Matt Briggs 58:15aa7a785b9f 602 }
Matt Briggs 58:15aa7a785b9f 603
Matt Briggs 58:15aa7a785b9f 604 return cmdSuccess;
Matt Briggs 58:15aa7a785b9f 605 }
Matt Briggs 58:15aa7a785b9f 606
Matt Briggs 58:15aa7a785b9f 607 CmdResult BaseboardIO::exitSleep()
Matt Briggs 58:15aa7a785b9f 608 {
Matt Briggs 58:15aa7a785b9f 609 xdot_restore_gpio_state();
Matt Briggs 58:15aa7a785b9f 610 return cmdSuccess;
Matt Briggs 58:15aa7a785b9f 611 }
Matt Briggs 58:15aa7a785b9f 612
Matt Briggs 55:79ab0bbc5008 613 // NvmBBIOObj
Matt Briggs 55:79ab0bbc5008 614 NvmBBIOObj::NvmBBIOObj()
Matt Briggs 55:79ab0bbc5008 615 {
Matt Briggs 55:79ab0bbc5008 616 setDefaults();
Matt Briggs 55:79ab0bbc5008 617 }
Matt Briggs 55:79ab0bbc5008 618 void NvmBBIOObj::setDefaults()
Matt Briggs 55:79ab0bbc5008 619 {
Matt Briggs 55:79ab0bbc5008 620 mBaseboardIOFlag = BASEBOARDIO_FLAG;
Matt Briggs 55:79ab0bbc5008 621 mBaseboardIORev = BASEBOARDIO_REV;
Matt Briggs 55:79ab0bbc5008 622 mSerialNum = 0x0000;
Matt Briggs 55:79ab0bbc5008 623 mBaseboardIOConfig = 0x0000;
Matt Briggs 55:79ab0bbc5008 624 std::memset(mPortExpanderROM0, 0x00, 8);
Matt Briggs 55:79ab0bbc5008 625 std::memset(mPortExpanderROM1, 0x00, 8);
Matt Briggs 55:79ab0bbc5008 626 }
Matt Briggs 55:79ab0bbc5008 627 CmdResult NvmBBIOObj::fromBytes(uint8_t *data, uint8_t size)
Matt Briggs 55:79ab0bbc5008 628 {
Matt Briggs 55:79ab0bbc5008 629 if (size != BASEBOARDIO_NVM_SIZE) {
Matt Briggs 55:79ab0bbc5008 630 return cmdError;
Matt Briggs 55:79ab0bbc5008 631 }
Matt Briggs 55:79ab0bbc5008 632
Matt Briggs 55:79ab0bbc5008 633 mBaseboardIOFlag = *((uint16_t *) (data));
Matt Briggs 55:79ab0bbc5008 634 mBaseboardIORev = *((uint16_t *) (data+2));
Matt Briggs 55:79ab0bbc5008 635 mSerialNum = *((uint32_t *) (data+4));
Matt Briggs 55:79ab0bbc5008 636 mBaseboardIOConfig = *((uint32_t *) (data+6));
Matt Briggs 55:79ab0bbc5008 637
Matt Briggs 55:79ab0bbc5008 638 std::memcpy(&mPortExpanderROM0, data+0x10, 8);
Matt Briggs 55:79ab0bbc5008 639 std::memcpy(&mPortExpanderROM1, data+0x18, 8);
Matt Briggs 55:79ab0bbc5008 640
Matt Briggs 55:79ab0bbc5008 641 return cmdSuccess;
Matt Briggs 55:79ab0bbc5008 642 }
Matt Briggs 55:79ab0bbc5008 643 CmdResult NvmBBIOObj::toBytes(uint8_t *data, uint8_t &size) {
Matt Briggs 55:79ab0bbc5008 644 // TODO check data size
Matt Briggs 55:79ab0bbc5008 645
Matt Briggs 55:79ab0bbc5008 646 *((uint16_t *) (data)) = mBaseboardIOFlag;
Matt Briggs 55:79ab0bbc5008 647 *((uint16_t *) (data+2)) = mBaseboardIORev;
Matt Briggs 55:79ab0bbc5008 648 *((uint32_t *) (data+4)) = mSerialNum;
Matt Briggs 55:79ab0bbc5008 649 *((uint32_t *) (data+6)) = mBaseboardIOConfig;
Matt Briggs 55:79ab0bbc5008 650
Matt Briggs 55:79ab0bbc5008 651 std::memcpy(data+0x10, &mPortExpanderROM0, 8);
Matt Briggs 55:79ab0bbc5008 652 std::memcpy(data+0x18, &mPortExpanderROM1, 8);
Matt Briggs 55:79ab0bbc5008 653
Matt Briggs 55:79ab0bbc5008 654 size = BASEBOARDIO_NVM_SIZE;
Matt Briggs 55:79ab0bbc5008 655
Matt Briggs 55:79ab0bbc5008 656 return cmdSuccess;
Matt Briggs 55:79ab0bbc5008 657 }
Matt Briggs 55:79ab0bbc5008 658 uint16_t NvmBBIOObj::getBaseboardIOFlag()
Matt Briggs 55:79ab0bbc5008 659 {
Matt Briggs 55:79ab0bbc5008 660 return mBaseboardIOFlag;
Matt Briggs 55:79ab0bbc5008 661 }
Matt Briggs 55:79ab0bbc5008 662 bool NvmBBIOObj::validBaseboardIOFlag()
Matt Briggs 55:79ab0bbc5008 663 {
Matt Briggs 55:79ab0bbc5008 664 return mBaseboardIOFlag == BASEBOARDIO_FLAG;
Matt Briggs 55:79ab0bbc5008 665 }
Matt Briggs 55:79ab0bbc5008 666 uint16_t NvmBBIOObj::getBaseboardIORev()
Matt Briggs 55:79ab0bbc5008 667 {
Matt Briggs 55:79ab0bbc5008 668 return mBaseboardIORev;
Matt Briggs 55:79ab0bbc5008 669 }
Matt Briggs 55:79ab0bbc5008 670 bool NvmBBIOObj::validBaseboardIORev()
Matt Briggs 55:79ab0bbc5008 671 {
Matt Briggs 55:79ab0bbc5008 672 return mBaseboardIORev == BASEBOARDIO_REV;
Matt Briggs 55:79ab0bbc5008 673 }
Matt Briggs 55:79ab0bbc5008 674 uint16_t NvmBBIOObj::getSerialNum()
Matt Briggs 55:79ab0bbc5008 675 {
Matt Briggs 55:79ab0bbc5008 676 return mSerialNum;
Matt Briggs 55:79ab0bbc5008 677 }
Matt Briggs 55:79ab0bbc5008 678 void NvmBBIOObj::setSerialNum(uint16_t in)
Matt Briggs 55:79ab0bbc5008 679 {
Matt Briggs 55:79ab0bbc5008 680 mSerialNum = in;
Matt Briggs 55:79ab0bbc5008 681 }
Matt Briggs 55:79ab0bbc5008 682 uint32_t NvmBBIOObj::getBaseboardIOConfig()
Matt Briggs 55:79ab0bbc5008 683 {
Matt Briggs 55:79ab0bbc5008 684 return mBaseboardIOConfig;
Matt Briggs 55:79ab0bbc5008 685 }
Matt Briggs 55:79ab0bbc5008 686 void NvmBBIOObj::setBaseboardIOConfig(uint32_t in)
Matt Briggs 55:79ab0bbc5008 687 {
Matt Briggs 55:79ab0bbc5008 688 mBaseboardIOConfig = in;
Matt Briggs 55:79ab0bbc5008 689 }
Matt Briggs 55:79ab0bbc5008 690 void NvmBBIOObj::getPortExpanderROM0(uint8_t *addr)
Matt Briggs 55:79ab0bbc5008 691 {
Matt Briggs 55:79ab0bbc5008 692 std::memcpy(addr, &mPortExpanderROM0, 8);
Matt Briggs 55:79ab0bbc5008 693 }
Matt Briggs 55:79ab0bbc5008 694 void NvmBBIOObj::setPortExpanderROM0(const uint8_t *addr)
Matt Briggs 55:79ab0bbc5008 695 {
Matt Briggs 55:79ab0bbc5008 696 std::memcpy(&mPortExpanderROM0, addr, 8);
Matt Briggs 55:79ab0bbc5008 697 }
Matt Briggs 55:79ab0bbc5008 698 void NvmBBIOObj::getPortExpanderROM1(uint8_t *addr)
Matt Briggs 55:79ab0bbc5008 699 {
Matt Briggs 55:79ab0bbc5008 700 std::memcpy(addr, &mPortExpanderROM1, 8);
Matt Briggs 55:79ab0bbc5008 701 }
Matt Briggs 55:79ab0bbc5008 702 void NvmBBIOObj::setPortExpanderROM1(const uint8_t *addr)
Matt Briggs 55:79ab0bbc5008 703 {
Matt Briggs 55:79ab0bbc5008 704 std::memcpy(&mPortExpanderROM1, addr, 8);
Matt Briggs 55:79ab0bbc5008 705 }